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sde_rotator_r3_hwio.h

sde_rotator_r3_hwio.h 17 KB
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  1. /* SPDX-License-Identifier: GPL-2.0-only */
    2. 

  2. /*
    3. 

  3.  * Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.
    4. 

  4.  */
    5. 

  5. 

  6. #ifndef _SDE_ROTATOR_R3_HWIO_H
    7. 

  7. #define _SDE_ROTATOR_R3_HWIO_H
    8. 

  8. 

  9. #include <linux/bitops.h>
    10. 

  10. 

  11. /* MMSS_MDSS:
    12. 

  12.  * OFFSET=0x000000
    13. 

  13.  */
    14. 

  14. #define MMSS_MDSS_HW_INTR_STATUS		0x10
    15. 

  15. #define MMSS_MDSS_HW_INTR_STATUS_ROT		BIT(2)
    16. 

  16. 

  17. /* SDE_ROT_ROTTOP:
    18. 

  18.  * OFFSET=0x0A8800
    19. 

  19.  */
    20. 

  20. #define SDE_ROT_ROTTOP_OFFSET                   0xA8800
    21. 

  21. #define ROTTOP_HW_VERSION                       (SDE_ROT_ROTTOP_OFFSET+0x00)
    22. 

  22. #define ROTTOP_CLK_CTRL                         (SDE_ROT_ROTTOP_OFFSET+0x10)
    23. 

  23. #define ROTTOP_CLK_STATUS                       (SDE_ROT_ROTTOP_OFFSET+0x14)
    24. 

  24. #define ROTTOP_ROT_NEWROI_PRIOR_TO_START        (SDE_ROT_ROTTOP_OFFSET+0x18)
    25. 

  25. #define ROTTOP_SW_RESET                         (SDE_ROT_ROTTOP_OFFSET+0x20)
    26. 

  26. #define ROTTOP_SW_RESET_CTRL                    (SDE_ROT_ROTTOP_OFFSET+0x24)
    27. 

  27. #define ROTTOP_SW_RESET_OVERRIDE                (SDE_ROT_ROTTOP_OFFSET+0x28)
    28. 

  28. #define ROTTOP_INTR_EN                          (SDE_ROT_ROTTOP_OFFSET+0x30)
    29. 

  29. #define ROTTOP_INTR_STATUS                      (SDE_ROT_ROTTOP_OFFSET+0x34)
    30. 

  30. #define ROTTOP_INTR_CLEAR                       (SDE_ROT_ROTTOP_OFFSET+0x38)
    31. 

  31. #define ROTTOP_START_CTRL                       (SDE_ROT_ROTTOP_OFFSET+0x40)
    32. 

  32. #define ROTTOP_STATUS                           (SDE_ROT_ROTTOP_OFFSET+0x44)
    33. 

  33. #define ROTTOP_OP_MODE                          (SDE_ROT_ROTTOP_OFFSET+0x48)
    34. 

  34. #define ROTTOP_DNSC                             (SDE_ROT_ROTTOP_OFFSET+0x4C)
    35. 

  35. #define ROTTOP_DEBUGBUS_CTRL                    (SDE_ROT_ROTTOP_OFFSET+0x50)
    36. 

  36. #define ROTTOP_DEBUGBUS_STATUS                  (SDE_ROT_ROTTOP_OFFSET+0x54)
    37. 

  37. #define ROTTOP_ROT_UBWC_DEC_VERSION             (SDE_ROT_ROTTOP_OFFSET+0x58)
    38. 

  38. #define ROTTOP_ROT_UBWC_ENC_VERSION             (SDE_ROT_ROTTOP_OFFSET+0x5C)
    39. 

  39. #define ROTTOP_ROT_CNTR_CTRL                    (SDE_ROT_ROTTOP_OFFSET+0x60)
    40. 

  40. #define ROTTOP_ROT_CNTR_0                       (SDE_ROT_ROTTOP_OFFSET+0x64)
    41. 

  41. #define ROTTOP_ROT_CNTR_1                       (SDE_ROT_ROTTOP_OFFSET+0x68)
    42. 

  42. #define ROTTOP_ROT_SCRATCH_0                    (SDE_ROT_ROTTOP_OFFSET+0x70)
    43. 

  43. #define ROTTOP_ROT_SCRATCH_1                    (SDE_ROT_ROTTOP_OFFSET+0x74)
    44. 

  44. #define ROTTOP_ROT_SCRATCH_2                    (SDE_ROT_ROTTOP_OFFSET+0x78)
    45. 

  45. #define ROTTOP_ROT_SCRATCH_3                    (SDE_ROT_ROTTOP_OFFSET+0x7C)
    46. 

  46. 

  47. #define ROTTOP_START_CTRL_TRIG_SEL_SW           0
    48. 

  48. #define ROTTOP_START_CTRL_TRIG_SEL_DONE         1
    49. 

  49. #define ROTTOP_START_CTRL_TRIG_SEL_REGDMA       2
    50. 

  50. #define ROTTOP_START_CTRL_TRIG_SEL_MDP          3
    51. 

  51. 

  52. #define ROTTOP_OP_MODE_ROT_OUT_MASK             (0x3 << 4)
    53. 

  53. 

  54. /* SDE_ROT_SSPP:
    55. 

  55.  * OFFSET=0x0A8900
    56. 

  56.  */
    57. 

  57. #define SDE_ROT_SSPP_OFFSET                     0xA8900
    58. 

  58. #define ROT_SSPP_SRC_SIZE                       (SDE_ROT_SSPP_OFFSET+0x00)
    59. 

  59. #define ROT_SSPP_SRC_IMG_SIZE                   (SDE_ROT_SSPP_OFFSET+0x04)
    60. 

  60. #define ROT_SSPP_SRC_XY                         (SDE_ROT_SSPP_OFFSET+0x08)
    61. 

  61. #define ROT_SSPP_OUT_SIZE                       (SDE_ROT_SSPP_OFFSET+0x0C)
    62. 

  62. #define ROT_SSPP_OUT_XY                         (SDE_ROT_SSPP_OFFSET+0x10)
    63. 

  63. #define ROT_SSPP_SRC0_ADDR                      (SDE_ROT_SSPP_OFFSET+0x14)
    64. 

  64. #define ROT_SSPP_SRC1_ADDR                      (SDE_ROT_SSPP_OFFSET+0x18)
    65. 

  65. #define ROT_SSPP_SRC2_ADDR                      (SDE_ROT_SSPP_OFFSET+0x1C)
    66. 

  66. #define ROT_SSPP_SRC3_ADDR                      (SDE_ROT_SSPP_OFFSET+0x20)
    67. 

  67. #define ROT_SSPP_SRC_YSTRIDE0                   (SDE_ROT_SSPP_OFFSET+0x24)
    68. 

  68. #define ROT_SSPP_SRC_YSTRIDE1                   (SDE_ROT_SSPP_OFFSET+0x28)
    69. 

  69. #define ROT_SSPP_TILE_FRAME_SIZE                (SDE_ROT_SSPP_OFFSET+0x2C)
    70. 

  70. #define ROT_SSPP_SRC_FORMAT                     (SDE_ROT_SSPP_OFFSET+0x30)
    71. 

  71. #define ROT_SSPP_SRC_UNPACK_PATTERN             (SDE_ROT_SSPP_OFFSET+0x34)
    72. 

  72. #define ROT_SSPP_SRC_OP_MODE                    (SDE_ROT_SSPP_OFFSET+0x38)
    73. 

  73. #define ROT_SSPP_SRC_CONSTANT_COLOR             (SDE_ROT_SSPP_OFFSET+0x3C)
    74. 

  74. #define ROT_SSPP_UBWC_STATIC_CTRL               (SDE_ROT_SSPP_OFFSET+0x44)
    75. 

  75. #define ROT_SSPP_FETCH_CONFIG                   (SDE_ROT_SSPP_OFFSET+0x48)
    76. 

  76. #define ROT_SSPP_VC1_RANGE                      (SDE_ROT_SSPP_OFFSET+0x4C)
    77. 

  77. #define ROT_SSPP_REQPRIORITY_FIFO_WATERMARK_0   (SDE_ROT_SSPP_OFFSET+0x50)
    78. 

  78. #define ROT_SSPP_REQPRIORITY_FIFO_WATERMARK_1   (SDE_ROT_SSPP_OFFSET+0x54)
    79. 

  79. #define ROT_SSPP_REQPRIORITY_FIFO_WATERMARK_2   (SDE_ROT_SSPP_OFFSET+0x58)
    80. 

  80. #define ROT_SSPP_DANGER_LUT                     (SDE_ROT_SSPP_OFFSET+0x60)
    81. 

  81. #define ROT_SSPP_SAFE_LUT                       (SDE_ROT_SSPP_OFFSET+0x64)
    82. 

  82. #define ROT_SSPP_CREQ_LUT                       (SDE_ROT_SSPP_OFFSET+0x68)
    83. 

  83. #define ROT_SSPP_QOS_CTRL                       (SDE_ROT_SSPP_OFFSET+0x6C)
    84. 

  84. #define ROT_SSPP_SRC_ADDR_SW_STATUS             (SDE_ROT_SSPP_OFFSET+0x70)
    85. 

  85. #define ROT_SSPP_CREQ_LUT_0                     (SDE_ROT_SSPP_OFFSET+0x74)
    86. 

  86. #define ROT_SSPP_CREQ_LUT_1                     (SDE_ROT_SSPP_OFFSET+0x78)
    87. 

  87. #define ROT_SSPP_CURRENT_SRC0_ADDR              (SDE_ROT_SSPP_OFFSET+0xA4)
    88. 

  88. #define ROT_SSPP_CURRENT_SRC1_ADDR              (SDE_ROT_SSPP_OFFSET+0xA8)
    89. 

  89. #define ROT_SSPP_CURRENT_SRC2_ADDR              (SDE_ROT_SSPP_OFFSET+0xAC)
    90. 

  90. #define ROT_SSPP_CURRENT_SRC3_ADDR              (SDE_ROT_SSPP_OFFSET+0xB0)
    91. 

  91. #define ROT_SSPP_DECIMATION_CONFIG              (SDE_ROT_SSPP_OFFSET+0xB4)
    92. 

  92. #define ROT_SSPP_FETCH_SMP_WR_PLANE0            (SDE_ROT_SSPP_OFFSET+0xD0)
    93. 

  93. #define ROT_SSPP_FETCH_SMP_WR_PLANE1            (SDE_ROT_SSPP_OFFSET+0xD4)
    94. 

  94. #define ROT_SSPP_FETCH_SMP_WR_PLANE2            (SDE_ROT_SSPP_OFFSET+0xD8)
    95. 

  95. #define ROT_SSPP_SMP_UNPACK_RD_PLANE0           (SDE_ROT_SSPP_OFFSET+0xE0)
    96. 

  96. #define ROT_SSPP_SMP_UNPACK_RD_PLANE1           (SDE_ROT_SSPP_OFFSET+0xE4)
    97. 

  97. #define ROT_SSPP_SMP_UNPACK_RD_PLANE2           (SDE_ROT_SSPP_OFFSET+0xE8)
    98. 

  98. #define ROT_SSPP_FILL_LEVELS                    (SDE_ROT_SSPP_OFFSET+0xF0)
    99. 

  99. #define ROT_SSPP_STATUS                         (SDE_ROT_SSPP_OFFSET+0xF4)
    100. 

  100. #define ROT_SSPP_UNPACK_LINE_COUNT              (SDE_ROT_SSPP_OFFSET+0xF8)
    101. 

  101. #define ROT_SSPP_UNPACK_BLK_COUNT               (SDE_ROT_SSPP_OFFSET+0xFC)
    102. 

  102. #define ROT_SSPP_SW_PIX_EXT_C0_LR               (SDE_ROT_SSPP_OFFSET+0x100)
    103. 

  103. #define ROT_SSPP_SW_PIX_EXT_C0_TB               (SDE_ROT_SSPP_OFFSET+0x104)
    104. 

  104. #define ROT_SSPP_SW_PIX_EXT_C0_REQ_PIXELS       (SDE_ROT_SSPP_OFFSET+0x108)
    105. 

  105. #define ROT_SSPP_SW_PIX_EXT_C1C2_LR             (SDE_ROT_SSPP_OFFSET+0x110)
    106. 

  106. #define ROT_SSPP_SW_PIX_EXT_C1C2_TB             (SDE_ROT_SSPP_OFFSET+0x114)
    107. 

  107. #define ROT_SSPP_SW_PIX_EXT_C1C2_REQ_PIXELS     (SDE_ROT_SSPP_OFFSET+0x118)
    108. 

  108. #define ROT_SSPP_SW_PIX_EXT_C3_LR               (SDE_ROT_SSPP_OFFSET+0x120)
    109. 

  109. #define ROT_SSPP_SW_PIX_EXT_C3_TB               (SDE_ROT_SSPP_OFFSET+0x124)
    110. 

  110. #define ROT_SSPP_SW_PIX_EXT_C3_REQ_PIXELS       (SDE_ROT_SSPP_OFFSET+0x128)
    111. 

  111. #define ROT_SSPP_TRAFFIC_SHAPER                 (SDE_ROT_SSPP_OFFSET+0x130)
    112. 

  112. #define ROT_SSPP_CDP_CNTL                       (SDE_ROT_SSPP_OFFSET+0x134)
    113. 

  113. #define ROT_SSPP_UBWC_ERROR_STATUS              (SDE_ROT_SSPP_OFFSET+0x138)
    114. 

  114. #define ROT_SSPP_SW_CROP_W_C0C3                 (SDE_ROT_SSPP_OFFSET+0x140)
    115. 

  115. #define ROT_SSPP_SW_CROP_W_C1C2                 (SDE_ROT_SSPP_OFFSET+0x144)
    116. 

  116. #define ROT_SSPP_SW_CROP_H_C0C3                 (SDE_ROT_SSPP_OFFSET+0x148)
    117. 

  117. #define ROT_SSPP_SW_CROP_H_C1C2                 (SDE_ROT_SSPP_OFFSET+0x14C)
    118. 

  118. #define ROT_SSPP_TRAFFIC_SHAPER_PREFILL         (SDE_ROT_SSPP_OFFSET+0x150)
    119. 

  119. #define ROT_SSPP_TRAFFIC_SHAPER_REC1_PREFILL    (SDE_ROT_SSPP_OFFSET+0x154)
    120. 

  120. #define ROT_SSPP_OUT_SIZE_REC1                  (SDE_ROT_SSPP_OFFSET+0x160)
    121. 

  121. #define ROT_SSPP_OUT_XY_REC1                    (SDE_ROT_SSPP_OFFSET+0x164)
    122. 

  122. #define ROT_SSPP_SRC_XY_REC1                    (SDE_ROT_SSPP_OFFSET+0x168)
    123. 

  123. #define ROT_SSPP_SRC_SIZE_REC1                  (SDE_ROT_SSPP_OFFSET+0x16C)
    124. 

  124. #define ROT_SSPP_MULTI_REC_OP_MODE              (SDE_ROT_SSPP_OFFSET+0x170)
    125. 

  125. #define ROT_SSPP_SRC_FORMAT_REC1                (SDE_ROT_SSPP_OFFSET+0x174)
    126. 

  126. #define ROT_SSPP_SRC_UNPACK_PATTERN_REC1        (SDE_ROT_SSPP_OFFSET+0x178)
    127. 

  127. #define ROT_SSPP_SRC_OP_MODE_REC1               (SDE_ROT_SSPP_OFFSET+0x17C)
    128. 

  128. #define ROT_SSPP_SRC_CONSTANT_COLOR_REC1        (SDE_ROT_SSPP_OFFSET+0x180)
    129. 

  129. #define ROT_SSPP_TPG_CONTROL                    (SDE_ROT_SSPP_OFFSET+0x190)
    130. 

  130. #define ROT_SSPP_TPG_CONFIG                     (SDE_ROT_SSPP_OFFSET+0x194)
    131. 

  131. #define ROT_SSPP_TPG_COMPONENT_LIMITS           (SDE_ROT_SSPP_OFFSET+0x198)
    132. 

  132. #define ROT_SSPP_TPG_RECTANGLE                  (SDE_ROT_SSPP_OFFSET+0x19C)
    133. 

  133. #define ROT_SSPP_TPG_BLACK_WHITE_PATTERN_FRAMES (SDE_ROT_SSPP_OFFSET+0x1A0)
    134. 

  134. #define ROT_SSPP_TPG_RGB_MAPPING                (SDE_ROT_SSPP_OFFSET+0x1A4)
    135. 

  135. #define ROT_SSPP_TPG_PATTERN_GEN_INIT_VAL       (SDE_ROT_SSPP_OFFSET+0x1A8)
    136. 

  136. 

  137. #define SDE_ROT_SSPP_FETCH_CONFIG_RESET_VALUE   0x00087
    138. 

  138. #define SDE_ROT_SSPP_FETCH_BLOCKSIZE_128        (0 << 16)
    139. 

  139. #define SDE_ROT_SSPP_FETCH_BLOCKSIZE_96         (2 << 16)
    140. 

  140. #define SDE_ROT_SSPP_FETCH_BLOCKSIZE_192_EXT    ((0 << 16) | (1 << 15))
    141. 

  141. #define SDE_ROT_SSPP_FETCH_BLOCKSIZE_144_EXT    ((2 << 16) | (1 << 15))
    142. 

  142. 

  143. 

  144. /* SDE_ROT_WB:
    145. 

  145.  * OFFSET=0x0A8B00
    146. 

  146.  */
    147. 

  147. #define SDE_ROT_WB_OFFSET                       0xA8B00
    148. 

  148. #define ROT_WB_DST_FORMAT                       (SDE_ROT_WB_OFFSET+0x000)
    149. 

  149. #define ROT_WB_DST_OP_MODE                      (SDE_ROT_WB_OFFSET+0x004)
    150. 

  150. #define ROT_WB_DST_PACK_PATTERN                 (SDE_ROT_WB_OFFSET+0x008)
    151. 

  151. #define ROT_WB_DST0_ADDR                        (SDE_ROT_WB_OFFSET+0x00C)
    152. 

  152. #define ROT_WB_DST1_ADDR                        (SDE_ROT_WB_OFFSET+0x010)
    153. 

  153. #define ROT_WB_DST2_ADDR                        (SDE_ROT_WB_OFFSET+0x014)
    154. 

  154. #define ROT_WB_DST3_ADDR                        (SDE_ROT_WB_OFFSET+0x018)
    155. 

  155. #define ROT_WB_DST_YSTRIDE0                     (SDE_ROT_WB_OFFSET+0x01C)
    156. 

  156. #define ROT_WB_DST_YSTRIDE1                     (SDE_ROT_WB_OFFSET+0x020)
    157. 

  157. #define ROT_WB_DST_DITHER_BITDEPTH              (SDE_ROT_WB_OFFSET+0x024)
    158. 

  158. #define ROT_WB_DITHER_MATRIX_ROW0               (SDE_ROT_WB_OFFSET+0x030)
    159. 

  159. #define ROT_WB_DITHER_MATRIX_ROW1               (SDE_ROT_WB_OFFSET+0x034)
    160. 

  160. #define ROT_WB_DITHER_MATRIX_ROW2               (SDE_ROT_WB_OFFSET+0x038)
    161. 

  161. #define ROT_WB_DITHER_MATRIX_ROW3               (SDE_ROT_WB_OFFSET+0x03C)
    162. 

  162. #define ROT_WB_TRAFFIC_SHAPER_WR_CLIENT         (SDE_ROT_WB_OFFSET+0x040)
    163. 

  163. #define ROT_WB_DST_WRITE_CONFIG                 (SDE_ROT_WB_OFFSET+0x048)
    164. 

  164. #define ROT_WB_ROTATOR_PIPE_DOWNSCALER          (SDE_ROT_WB_OFFSET+0x054)
    165. 

  165. #define ROT_WB_OUT_SIZE                         (SDE_ROT_WB_OFFSET+0x074)
    166. 

  166. #define ROT_WB_DST_ALPHA_X_VALUE                (SDE_ROT_WB_OFFSET+0x078)
    167. 

  167. #define ROT_WB_HW_VERSION                       (SDE_ROT_WB_OFFSET+0x080)
    168. 

  168. #define ROT_WB_DANGER_LUT                       (SDE_ROT_WB_OFFSET+0x084)
    169. 

  169. #define ROT_WB_SAFE_LUT                         (SDE_ROT_WB_OFFSET+0x088)
    170. 

  170. #define ROT_WB_CREQ_LUT                         (SDE_ROT_WB_OFFSET+0x08C)
    171. 

  171. #define ROT_WB_QOS_CTRL                         (SDE_ROT_WB_OFFSET+0x090)
    172. 

  172. #define ROT_WB_SYS_CACHE_MODE                   (SDE_ROT_WB_OFFSET+0x094)
    173. 

  173. #define ROT_WB_CREQ_LUT_0                       (SDE_ROT_WB_OFFSET+0x098)
    174. 

  174. #define ROT_WB_CREQ_LUT_1                       (SDE_ROT_WB_OFFSET+0x09C)
    175. 

  175. #define ROT_WB_UBWC_STATIC_CTRL                 (SDE_ROT_WB_OFFSET+0x144)
    176. 

  176. #define ROT_WB_SBUF_STATUS_PLANE0               (SDE_ROT_WB_OFFSET+0x148)
    177. 

  177. #define ROT_WB_SBUF_STATUS_PLANE1               (SDE_ROT_WB_OFFSET+0x14C)
    178. 

  178. #define ROT_WB_CSC_MATRIX_COEFF_0               (SDE_ROT_WB_OFFSET+0x260)
    179. 

  179. #define ROT_WB_CSC_MATRIX_COEFF_1               (SDE_ROT_WB_OFFSET+0x264)
    180. 

  180. #define ROT_WB_CSC_MATRIX_COEFF_2               (SDE_ROT_WB_OFFSET+0x268)
    181. 

  181. #define ROT_WB_CSC_MATRIX_COEFF_3               (SDE_ROT_WB_OFFSET+0x26C)
    182. 

  182. #define ROT_WB_CSC_MATRIX_COEFF_4               (SDE_ROT_WB_OFFSET+0x270)
    183. 

  183. #define ROT_WB_CSC_COMP0_PRECLAMP               (SDE_ROT_WB_OFFSET+0x274)
    184. 

  184. #define ROT_WB_CSC_COMP1_PRECLAMP               (SDE_ROT_WB_OFFSET+0x278)
    185. 

  185. #define ROT_WB_CSC_COMP2_PRECLAMP               (SDE_ROT_WB_OFFSET+0x27C)
    186. 

  186. #define ROT_WB_CSC_COMP0_POSTCLAMP              (SDE_ROT_WB_OFFSET+0x280)
    187. 

  187. #define ROT_WB_CSC_COMP1_POSTCLAMP              (SDE_ROT_WB_OFFSET+0x284)
    188. 

  188. #define ROT_WB_CSC_COMP2_POSTCLAMP              (SDE_ROT_WB_OFFSET+0x288)
    189. 

  189. #define ROT_WB_CSC_COMP0_PREBIAS                (SDE_ROT_WB_OFFSET+0x28C)
    190. 

  190. #define ROT_WB_CSC_COMP1_PREBIAS                (SDE_ROT_WB_OFFSET+0x290)
    191. 

  191. #define ROT_WB_CSC_COMP2_PREBIAS                (SDE_ROT_WB_OFFSET+0x294)
    192. 

  192. #define ROT_WB_CSC_COMP0_POSTBIAS               (SDE_ROT_WB_OFFSET+0x298)
    193. 

  193. #define ROT_WB_CSC_COMP1_POSTBIAS               (SDE_ROT_WB_OFFSET+0x29C)
    194. 

  194. #define ROT_WB_CSC_COMP2_POSTBIAS               (SDE_ROT_WB_OFFSET+0x2A0)
    195. 

  195. #define ROT_WB_DST_ADDR_SW_STATUS               (SDE_ROT_WB_OFFSET+0x2B0)
    196. 

  196. #define ROT_WB_CDP_CNTL                         (SDE_ROT_WB_OFFSET+0x2B4)
    197. 

  197. #define ROT_WB_STATUS                           (SDE_ROT_WB_OFFSET+0x2B8)
    198. 

  198. #define ROT_WB_UBWC_ERROR_STATUS                (SDE_ROT_WB_OFFSET+0x2BC)
    199. 

  199. #define ROT_WB_OUT_IMG_SIZE                     (SDE_ROT_WB_OFFSET+0x2C0)
    200. 

  200. #define ROT_WB_OUT_XY                           (SDE_ROT_WB_OFFSET+0x2C4)
    201. 

  201. 

  202. 

  203. /* SDE_ROT_REGDMA_RAM:
    204. 

  204.  * OFFSET=0x0A8E00
    205. 

  205.  */
    206. 

  206. #define SDE_ROT_REGDMA_RAM_OFFSET              0xA8E00
    207. 

  207. #define REGDMA_RAM_REGDMA_CMD_RAM              (SDE_ROT_REGDMA_RAM_OFFSET+0x00)
    208. 

  208. 

  209. 

  210. /* SDE_ROT_REGDMA_CSR:
    211. 

  211.  * OFFSET=0x0AAE00
    212. 

  212.  */
    213. 

  213. #define SDE_ROT_REGDMA_OFFSET                    0xAAE00
    214. 

  214. #define REGDMA_CSR_REGDMA_VERSION                (SDE_ROT_REGDMA_OFFSET+0x00)
    215. 

  215. #define REGDMA_CSR_REGDMA_OP_MODE                (SDE_ROT_REGDMA_OFFSET+0x04)
    216. 

  216. #define REGDMA_CSR_REGDMA_QUEUE_0_SUBMIT         (SDE_ROT_REGDMA_OFFSET+0x10)
    217. 

  217. #define REGDMA_CSR_REGDMA_QUEUE_0_STATUS         (SDE_ROT_REGDMA_OFFSET+0x14)
    218. 

  218. #define REGDMA_CSR_REGDMA_QUEUE_1_SUBMIT         (SDE_ROT_REGDMA_OFFSET+0x18)
    219. 

  219. #define REGDMA_CSR_REGDMA_QUEUE_1_STATUS         (SDE_ROT_REGDMA_OFFSET+0x1C)
    220. 

  220. #define REGDMA_CSR_REGDMA_BLOCK_LO_0             (SDE_ROT_REGDMA_OFFSET+0x20)
    221. 

  221. #define REGDMA_CSR_REGDMA_BLOCK_HI_0             (SDE_ROT_REGDMA_OFFSET+0x24)
    222. 

  222. #define REGDMA_CSR_REGDMA_BLOCK_LO_1             (SDE_ROT_REGDMA_OFFSET+0x28)
    223. 

  223. #define REGDMA_CSR_REGDMA_BLOCK_HI_1             (SDE_ROT_REGDMA_OFFSET+0x2C)
    224. 

  224. #define REGDMA_CSR_REGDMA_BLOCK_LO_2             (SDE_ROT_REGDMA_OFFSET+0x30)
    225. 

  225. #define REGDMA_CSR_REGDMA_BLOCK_HI_2             (SDE_ROT_REGDMA_OFFSET+0x34)
    226. 

  226. #define REGDMA_CSR_REGDMA_BLOCK_LO_3             (SDE_ROT_REGDMA_OFFSET+0x38)
    227. 

  227. #define REGDMA_CSR_REGDMA_BLOCK_HI_3             (SDE_ROT_REGDMA_OFFSET+0x3C)
    228. 

  228. #define REGDMA_CSR_REGDMA_WD_TIMER_CTL           (SDE_ROT_REGDMA_OFFSET+0x40)
    229. 

  229. #define REGDMA_CSR_REGDMA_WD_TIMER_CTL2          (SDE_ROT_REGDMA_OFFSET+0x44)
    230. 

  230. #define REGDMA_CSR_REGDMA_WD_TIMER_LOAD_VALUE    (SDE_ROT_REGDMA_OFFSET+0x48)
    231. 

  231. #define REGDMA_CSR_REGDMA_WD_TIMER_STATUS_VALUE  (SDE_ROT_REGDMA_OFFSET+0x4C)
    232. 

  232. #define REGDMA_CSR_REGDMA_INT_STATUS             (SDE_ROT_REGDMA_OFFSET+0x50)
    233. 

  233. #define REGDMA_CSR_REGDMA_INT_EN                 (SDE_ROT_REGDMA_OFFSET+0x54)
    234. 

  234. #define REGDMA_CSR_REGDMA_INT_CLEAR              (SDE_ROT_REGDMA_OFFSET+0x58)
    235. 

  235. #define REGDMA_CSR_REGDMA_BLOCK_STATUS           (SDE_ROT_REGDMA_OFFSET+0x5C)
    236. 

  236. #define REGDMA_CSR_REGDMA_INVALID_CMD_RAM_OFFSET (SDE_ROT_REGDMA_OFFSET+0x60)
    237. 

  237. #define REGDMA_CSR_REGDMA_FSM_STATE              (SDE_ROT_REGDMA_OFFSET+0x64)
    238. 

  238. #define REGDMA_CSR_REGDMA_DEBUG_SEL              (SDE_ROT_REGDMA_OFFSET+0x68)
    239. 

  239. 

  240. 

  241. /* SDE_ROT_QDSS:
    242. 

  242.  * OFFSET=0x0AAF00
    243. 

  243.  */
    244. 

  244. #define ROT_QDSS_CONFIG                          0x00
    245. 

  245. #define ROT_QDSS_ATB_DATA_ENABLE0                0x04
    246. 

  246. #define ROT_QDSS_ATB_DATA_ENABLE1                0x08
    247. 

  247. #define ROT_QDSS_ATB_DATA_ENABLE2                0x0C
    248. 

  248. #define ROT_QDSS_ATB_DATA_ENABLE3                0x10
    249. 

  249. #define ROT_QDSS_CLK_CTRL                        0x14
    250. 

  250. #define ROT_QDSS_CLK_STATUS                      0x18
    251. 

  251. #define ROT_QDSS_PULSE_TRIGGER                   0x20
    252. 

  252. 

  253. /*
    254. 

  254.  * SDE_ROT_VBIF_NRT:
    255. 

  255.  */
    256. 

  256. #define SDE_ROT_VBIF_NRT_OFFSET                  0
    257. 

  257. 

  258. /* REGDMA OP Code */
    259. 

  259. #define REGDMA_OP_NOP                   (0 << 28)
    260. 

  260. #define REGDMA_OP_REGWRITE              (1 << 28)
    261. 

  261. #define REGDMA_OP_REGMODIFY             (2 << 28)
    262. 

  262. #define REGDMA_OP_BLKWRITE_SINGLE       (3 << 28)
    263. 

  263. #define REGDMA_OP_BLKWRITE_INC          (4 << 28)
    264. 

  264. #define REGDMA_OP_MASK                  0xF0000000
    265. 

  265. 

  266. /* REGDMA ADDR offset Mask */
    267. 

  267. #define REGDMA_ADDR_OFFSET_MASK         0xFFFFF
    268. 

  268. 

  269. /* REGDMA command trigger select */
    270. 

  270. #define REGDMA_CMD_TRIG_SEL_SW_START    (0 << 27)
    271. 

  271. #define REGDMA_CMD_TRIG_SEL_MDP_FLUSH   (1 << 27)
    272. 

  272. 

  273. /* General defines */
    274. 

  274. #define ROT_DONE_MASK                   0x1
    275. 

  275. #define ROT_DONE_CLEAR                  0x1
    276. 

  276. #define ROT_BUSY_BIT                    BIT(0)
    277. 

  277. #define ROT_ERROR_BIT                   BIT(8)
    278. 

  278. #define ROT_STATUS_MASK                 (ROT_BUSY_BIT | ROT_ERROR_BIT)
    279. 

  279. #define REGDMA_BUSY                     BIT(0)
    280. 

  280. #define REGDMA_EN                       0x1
    281. 

  281. #define REGDMA_SECURE_EN                BIT(8)
    282. 

  282. #define REGDMA_HALT                     BIT(16)
    283. 

  283. 

  284. #define REGDMA_WATCHDOG_INT             BIT(19)
    285. 

  285. #define REGDMA_INVALID_DESCRIPTOR       BIT(18)
    286. 

  286. #define REGDMA_INCOMPLETE_CMD           BIT(17)
    287. 

  287. #define REGDMA_INVALID_CMD              BIT(16)
    288. 

  288. #define REGDMA_QUEUE1_INT2              BIT(10)
    289. 

  289. #define REGDMA_QUEUE1_INT1              BIT(9)
    290. 

  290. #define REGDMA_QUEUE1_INT0              BIT(8)
    291. 

  291. #define REGDMA_QUEUE0_INT2              BIT(2)
    292. 

  292. #define REGDMA_QUEUE0_INT1              BIT(1)
    293. 

  293. #define REGDMA_QUEUE0_INT0              BIT(0)
    294. 

  294. #define REGDMA_INT_MASK                 0x000F0707
    295. 

  295. #define REGDMA_INT_HIGH_MASK            0x00000007
    296. 

  296. #define REGDMA_INT_LOW_MASK             0x00000700
    297. 

  297. #define REGDMA_INT_ERR_MASK             0x000F0000
    298. 

  298. #define REGDMA_TIMESTAMP_REG            ROT_SSPP_TPG_PATTERN_GEN_INIT_VAL
    299. 

  299. #define REGDMA_RESET_STATUS_REG         ROT_SSPP_TPG_RGB_MAPPING
    300. 

  300. 

  301. #define REGDMA_INT_0_MASK               0x101
    302. 

  302. #define REGDMA_INT_1_MASK               0x202
    303. 

  303. #define REGDMA_INT_2_MASK               0x404
    304. 

  304. 

  305. #endif /*_SDE_ROTATOR_R3_HWIO_H */
    306.