dsi_phy.h 9.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #ifndef _DSI_PHY_H_
  6. #define _DSI_PHY_H_
  7. #include "dsi_defs.h"
  8. #include "dsi_clk.h"
  9. #include "dsi_pwr.h"
  10. #include "dsi_phy_hw.h"
  11. #include "dsi_pll.h"
  12. struct dsi_ver_spec_info {
  13. enum dsi_phy_version version;
  14. u32 lane_cfg_count;
  15. u32 strength_cfg_count;
  16. u32 regulator_cfg_count;
  17. u32 timing_cfg_count;
  18. };
  19. /**
  20. * struct dsi_phy_power_info - digital and analog power supplies for DSI PHY
  21. * @digital: Digital power supply for DSI PHY.
  22. * @phy_pwr: Analog power supplies for DSI PHY to work.
  23. */
  24. struct dsi_phy_power_info {
  25. struct dsi_regulator_info digital;
  26. struct dsi_regulator_info phy_pwr;
  27. };
  28. /**
  29. * enum phy_engine_state - define engine status for dsi phy.
  30. * @DSI_PHY_ENGINE_OFF: Engine is turned off.
  31. * @DSI_PHY_ENGINE_ON: Engine is turned on.
  32. * @DSI_PHY_ENGINE_MAX: Maximum value.
  33. */
  34. enum phy_engine_state {
  35. DSI_PHY_ENGINE_OFF = 0,
  36. DSI_PHY_ENGINE_ON,
  37. DSI_PHY_ENGINE_MAX,
  38. };
  39. /**
  40. * enum phy_ulps_return_type - define set_ulps return type for dsi phy.
  41. * @DSI_PHY_ULPS_HANDLED: ulps is handled in phy.
  42. * @DSI_PHY_ULPS_NOT_HANDLED: ulps is not handled in phy.
  43. * @DSI_PHY_ULPS_ERROR: ulps request failed in phy.
  44. */
  45. enum phy_ulps_return_type {
  46. DSI_PHY_ULPS_HANDLED = 0,
  47. DSI_PHY_ULPS_NOT_HANDLED,
  48. DSI_PHY_ULPS_ERROR,
  49. };
  50. /**
  51. * struct msm_dsi_phy - DSI PHY object
  52. * @pdev: Pointer to platform device.
  53. * @index: Instance id.
  54. * @name: Name of the PHY instance.
  55. * @refcount: Reference count.
  56. * @phy_lock: Mutex for hardware and object access.
  57. * @ver_info: Version specific phy parameters.
  58. * @hw: DSI PHY hardware object.
  59. * @pwr_info: Power information.
  60. * @cfg: DSI phy configuration.
  61. * @clk_cb: structure containing call backs for clock control
  62. * @power_state: True if PHY is powered on.
  63. * @dsi_phy_state: PHY state information.
  64. * @mode: Current mode.
  65. * @data_lanes: Number of data lanes used.
  66. * @dst_format: Destination format.
  67. * @pll: Pointer to PLL resource.
  68. * @allow_phy_power_off: True if PHY is allowed to power off when idle
  69. * @regulator_min_datarate_bps: Minimum per lane data rate to turn on regulator
  70. * @regulator_required: True if phy regulator is required
  71. */
  72. struct msm_dsi_phy {
  73. struct platform_device *pdev;
  74. int index;
  75. const char *name;
  76. u32 refcount;
  77. struct mutex phy_lock;
  78. const struct dsi_ver_spec_info *ver_info;
  79. struct dsi_phy_hw hw;
  80. struct dsi_phy_power_info pwr_info;
  81. struct dsi_phy_cfg cfg;
  82. struct clk_ctrl_cb clk_cb;
  83. enum phy_engine_state dsi_phy_state;
  84. bool power_state;
  85. struct dsi_mode_info mode;
  86. enum dsi_data_lanes data_lanes;
  87. enum dsi_pixel_format dst_format;
  88. struct dsi_pll_resource *pll;
  89. bool allow_phy_power_off;
  90. u32 regulator_min_datarate_bps;
  91. bool regulator_required;
  92. };
  93. /**
  94. * dsi_phy_get() - get a dsi phy handle from device node
  95. * @of_node: device node for dsi phy controller
  96. *
  97. * Gets the DSI PHY handle for the corresponding of_node. The ref count is
  98. * incremented to one all subsequents get will fail until the original client
  99. * calls a put.
  100. *
  101. * Return: DSI PHY handle or an error code.
  102. */
  103. struct msm_dsi_phy *dsi_phy_get(struct device_node *of_node);
  104. /**
  105. * dsi_phy_put() - release dsi phy handle
  106. * @dsi_phy: DSI PHY handle.
  107. *
  108. * Release the DSI PHY hardware. Driver will clean up all resources and puts
  109. * back the DSI PHY into reset state.
  110. */
  111. void dsi_phy_put(struct msm_dsi_phy *dsi_phy);
  112. /**
  113. * dsi_phy_get_version() - returns dsi phy version
  114. * @dsi_phy: DSI PHY handle.
  115. *
  116. * Return: phy version
  117. */
  118. int dsi_phy_get_version(struct msm_dsi_phy *phy);
  119. /**
  120. * dsi_phy_drv_init() - initialize dsi phy driver
  121. * @dsi_phy: DSI PHY handle.
  122. *
  123. * Initializes DSI PHY driver. Should be called after dsi_phy_get().
  124. *
  125. * Return: error code.
  126. */
  127. int dsi_phy_drv_init(struct msm_dsi_phy *dsi_phy);
  128. /**
  129. * dsi_phy_drv_deinit() - de-initialize dsi phy driver
  130. * @dsi_phy: DSI PHY handle.
  131. *
  132. * Release all resources acquired by dsi_phy_drv_init().
  133. *
  134. * Return: error code.
  135. */
  136. int dsi_phy_drv_deinit(struct msm_dsi_phy *dsi_phy);
  137. /**
  138. * dsi_phy_validate_mode() - validate a display mode
  139. * @dsi_phy: DSI PHY handle.
  140. * @mode: Mode information.
  141. *
  142. * Validation will fail if the mode cannot be supported by the PHY driver or
  143. * hardware.
  144. *
  145. * Return: error code.
  146. */
  147. int dsi_phy_validate_mode(struct msm_dsi_phy *dsi_phy,
  148. struct dsi_mode_info *mode);
  149. /**
  150. * dsi_phy_set_power_state() - enable/disable dsi phy power supplies
  151. * @dsi_phy: DSI PHY handle.
  152. * @enable: Boolean flag to enable/disable.
  153. *
  154. * Return: error code.
  155. */
  156. int dsi_phy_set_power_state(struct msm_dsi_phy *dsi_phy, bool enable);
  157. /**
  158. * dsi_phy_enable() - enable DSI PHY hardware
  159. * @dsi_phy: DSI PHY handle.
  160. * @config: DSI host configuration.
  161. * @pll_source: Source PLL for PHY clock.
  162. * @skip_validation: Validation will not be performed on parameters.
  163. * @is_cont_splash_enabled: check whether continuous splash enabled.
  164. *
  165. * Validates and enables DSI PHY.
  166. *
  167. * Return: error code.
  168. */
  169. int dsi_phy_enable(struct msm_dsi_phy *dsi_phy,
  170. struct dsi_host_config *config,
  171. enum dsi_phy_pll_source pll_source,
  172. bool skip_validation,
  173. bool is_cont_splash_enabled);
  174. /**
  175. * dsi_phy_disable() - disable DSI PHY hardware.
  176. * @phy: DSI PHY handle.
  177. *
  178. * Return: error code.
  179. */
  180. int dsi_phy_disable(struct msm_dsi_phy *phy);
  181. /**
  182. * dsi_phy_set_ulps() - set ulps state for DSI pHY
  183. * @phy: DSI PHY handle
  184. * @config: DSi host configuration information.
  185. * @enable: Enable/Disable
  186. * @clamp_enabled: mmss_clamp enabled/disabled
  187. *
  188. * Return: error code.
  189. */
  190. int dsi_phy_set_ulps(struct msm_dsi_phy *phy, struct dsi_host_config *config,
  191. bool enable, bool clamp_enabled);
  192. /**
  193. * dsi_phy_clk_cb_register() - Register PHY clock control callback
  194. * @phy: DSI PHY handle
  195. * @clk_cb: Structure containing call back for clock control
  196. *
  197. * Return: error code.
  198. */
  199. int dsi_phy_clk_cb_register(struct msm_dsi_phy *phy,
  200. struct clk_ctrl_cb *clk_cb);
  201. /**
  202. * dsi_phy_idle_ctrl() - enable/disable DSI PHY during idle screen
  203. * @phy: DSI PHY handle
  204. * @enable: boolean to specify PHY enable/disable.
  205. *
  206. * Return: error code.
  207. */
  208. int dsi_phy_idle_ctrl(struct msm_dsi_phy *phy, bool enable);
  209. /**
  210. * dsi_phy_set_clamp_state() - configure clamps for DSI lanes
  211. * @phy: DSI PHY handle.
  212. * @enable: boolean to specify clamp enable/disable.
  213. *
  214. * Return: error code.
  215. */
  216. int dsi_phy_set_clamp_state(struct msm_dsi_phy *phy, bool enable);
  217. /**
  218. * dsi_phy_set_clk_freq() - set DSI PHY clock frequency setting
  219. * @phy: DSI PHY handle
  220. * @clk_freq: link clock frequency
  221. *
  222. * Return: error code.
  223. */
  224. int dsi_phy_set_clk_freq(struct msm_dsi_phy *phy,
  225. struct link_clk_freq *clk_freq);
  226. /**
  227. * dsi_phy_set_timing_params() - timing parameters for the panel
  228. * @phy: DSI PHY handle
  229. * @timing: array holding timing params.
  230. * @size: size of the array.
  231. * @commit: boolean to indicate if programming PHY HW registers is
  232. * required
  233. *
  234. * When PHY timing calculator is not implemented, this array will be used to
  235. * pass PHY timing information.
  236. *
  237. * Return: error code.
  238. */
  239. int dsi_phy_set_timing_params(struct msm_dsi_phy *phy,
  240. u32 *timing, u32 size, bool commit);
  241. /**
  242. * dsi_phy_lane_reset() - Reset DSI PHY lanes in case of error
  243. * @phy: DSI PHY handle
  244. *
  245. * Return: error code.
  246. */
  247. int dsi_phy_lane_reset(struct msm_dsi_phy *phy);
  248. /**
  249. * dsi_phy_toggle_resync_fifo() - toggle resync retime FIFO
  250. * @phy: DSI PHY handle
  251. *
  252. * Toggle the resync retime FIFO to synchronize the data paths.
  253. * This should be done everytime there is a change in the link clock
  254. * rate
  255. */
  256. void dsi_phy_toggle_resync_fifo(struct msm_dsi_phy *phy);
  257. /**
  258. * dsi_phy_reset_clk_en_sel() - reset clk_en_select on cmn_clk_cfg1 register
  259. * @phy: DSI PHY handle
  260. *
  261. * After toggling resync fifo regiater, clk_en_sel bit on cmn_clk_cfg1
  262. * register has to be reset
  263. */
  264. void dsi_phy_reset_clk_en_sel(struct msm_dsi_phy *phy);
  265. /**
  266. * dsi_phy_drv_register() - register platform driver for dsi phy
  267. */
  268. void dsi_phy_drv_register(void);
  269. /**
  270. * dsi_phy_drv_unregister() - unregister platform driver
  271. */
  272. void dsi_phy_drv_unregister(void);
  273. /**
  274. * dsi_phy_update_phy_timings() - Update dsi phy timings
  275. * @phy: DSI PHY handle
  276. * @config: DSI Host config parameters
  277. *
  278. * Return: error code.
  279. */
  280. int dsi_phy_update_phy_timings(struct msm_dsi_phy *phy,
  281. struct dsi_host_config *config);
  282. /**
  283. * dsi_phy_config_dynamic_refresh() - Configure dynamic refresh registers
  284. * @phy: DSI PHY handle
  285. * @delay: pipe delays for dynamic refresh
  286. * @is_master: Boolean to indicate if for master or slave
  287. */
  288. void dsi_phy_config_dynamic_refresh(struct msm_dsi_phy *phy,
  289. struct dsi_dyn_clk_delay *delay,
  290. bool is_master);
  291. /**
  292. * dsi_phy_dynamic_refresh_trigger() - trigger dynamic refresh
  293. * @phy: DSI PHY handle
  294. * @is_master: Boolean to indicate if for master or slave.
  295. */
  296. void dsi_phy_dynamic_refresh_trigger(struct msm_dsi_phy *phy, bool is_master);
  297. /**
  298. * dsi_phy_dynamic_refresh_clear() - clear dynamic refresh config
  299. * @phy: DSI PHY handle
  300. */
  301. void dsi_phy_dynamic_refresh_clear(struct msm_dsi_phy *phy);
  302. /**
  303. * dsi_phy_dyn_refresh_cache_phy_timings - cache the phy timings calculated
  304. * as part of dynamic refresh.
  305. * @phy: DSI PHY Handle.
  306. * @dst: Pointer to cache location.
  307. * @size: Number of phy lane settings.
  308. */
  309. int dsi_phy_dyn_refresh_cache_phy_timings(struct msm_dsi_phy *phy,
  310. u32 *dst, u32 size);
  311. /**
  312. * dsi_phy_set_continuous_clk() - API to set/unset force clock lane HS request.
  313. * @phy: DSI PHY Handle.
  314. * @enable: variable to control continuous clock.
  315. */
  316. void dsi_phy_set_continuous_clk(struct msm_dsi_phy *phy, bool enable);
  317. #endif /* _DSI_PHY_H_ */