dp_tx.c 98 KB

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  1. /*
  2. * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "hal_hw_headers.h"
  20. #include "dp_tx.h"
  21. #include "dp_tx_desc.h"
  22. #include "dp_peer.h"
  23. #include "dp_types.h"
  24. #include "hal_tx.h"
  25. #include "qdf_mem.h"
  26. #include "qdf_nbuf.h"
  27. #include "qdf_net_types.h"
  28. #include <wlan_cfg.h>
  29. #ifdef MESH_MODE_SUPPORT
  30. #include "if_meta_hdr.h"
  31. #endif
  32. #define DP_TX_QUEUE_MASK 0x3
  33. /* TODO Add support in TSO */
  34. #define DP_DESC_NUM_FRAG(x) 0
  35. /* disable TQM_BYPASS */
  36. #define TQM_BYPASS_WAR 0
  37. /* invalid peer id for reinject*/
  38. #define DP_INVALID_PEER 0XFFFE
  39. /*mapping between hal encrypt type and cdp_sec_type*/
  40. #define MAX_CDP_SEC_TYPE 12
  41. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  42. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  43. HAL_TX_ENCRYPT_TYPE_WEP_128,
  44. HAL_TX_ENCRYPT_TYPE_WEP_104,
  45. HAL_TX_ENCRYPT_TYPE_WEP_40,
  46. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  47. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  48. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  49. HAL_TX_ENCRYPT_TYPE_WAPI,
  50. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  51. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  52. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  53. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  54. /**
  55. * dp_tx_get_queue() - Returns Tx queue IDs to be used for this Tx frame
  56. * @vdev: DP Virtual device handle
  57. * @nbuf: Buffer pointer
  58. * @queue: queue ids container for nbuf
  59. *
  60. * TX packet queue has 2 instances, software descriptors id and dma ring id
  61. * Based on tx feature and hardware configuration queue id combination could be
  62. * different.
  63. * For example -
  64. * With XPS enabled,all TX descriptor pools and dma ring are assigned per cpu id
  65. * With no XPS,lock based resource protection, Descriptor pool ids are different
  66. * for each vdev, dma ring id will be same as single pdev id
  67. *
  68. * Return: None
  69. */
  70. #ifdef QCA_OL_TX_MULTIQ_SUPPORT
  71. static inline void dp_tx_get_queue(struct dp_vdev *vdev,
  72. qdf_nbuf_t nbuf, struct dp_tx_queue *queue)
  73. {
  74. uint16_t queue_offset = qdf_nbuf_get_queue_mapping(nbuf) & DP_TX_QUEUE_MASK;
  75. queue->desc_pool_id = queue_offset;
  76. queue->ring_id = vdev->pdev->soc->tx_ring_map[queue_offset];
  77. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  78. "%s, pool_id:%d ring_id: %d",
  79. __func__, queue->desc_pool_id, queue->ring_id);
  80. return;
  81. }
  82. #else /* QCA_OL_TX_MULTIQ_SUPPORT */
  83. static inline void dp_tx_get_queue(struct dp_vdev *vdev,
  84. qdf_nbuf_t nbuf, struct dp_tx_queue *queue)
  85. {
  86. /* get flow id */
  87. queue->desc_pool_id = DP_TX_GET_DESC_POOL_ID(vdev);
  88. queue->ring_id = DP_TX_GET_RING_ID(vdev);
  89. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  90. "%s, pool_id:%d ring_id: %d",
  91. __func__, queue->desc_pool_id, queue->ring_id);
  92. return;
  93. }
  94. #endif
  95. #if defined(FEATURE_TSO)
  96. /**
  97. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  98. *
  99. * @soc - core txrx main context
  100. * @tx_desc - Tx software descriptor
  101. */
  102. static void dp_tx_tso_unmap_segment(struct dp_soc *soc,
  103. struct dp_tx_desc_s *tx_desc)
  104. {
  105. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  106. if (qdf_unlikely(!tx_desc->tso_desc)) {
  107. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  108. "%s %d TSO desc is NULL!",
  109. __func__, __LINE__);
  110. qdf_assert(0);
  111. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  112. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  113. "%s %d TSO num desc is NULL!",
  114. __func__, __LINE__);
  115. qdf_assert(0);
  116. } else {
  117. bool is_last_seg;
  118. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  119. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  120. if (tso_num_desc->num_seg.tso_cmn_num_seg > 1)
  121. is_last_seg = false;
  122. else
  123. is_last_seg = true;
  124. tso_num_desc->num_seg.tso_cmn_num_seg--;
  125. qdf_nbuf_unmap_tso_segment(soc->osdev,
  126. tx_desc->tso_desc, is_last_seg);
  127. }
  128. }
  129. /**
  130. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  131. * back to the freelist
  132. *
  133. * @soc - soc device handle
  134. * @tx_desc - Tx software descriptor
  135. */
  136. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  137. struct dp_tx_desc_s *tx_desc)
  138. {
  139. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  140. if (qdf_unlikely(!tx_desc->tso_desc)) {
  141. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  142. "%s %d TSO desc is NULL!",
  143. __func__, __LINE__);
  144. qdf_assert(0);
  145. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  146. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  147. "%s %d TSO num desc is NULL!",
  148. __func__, __LINE__);
  149. qdf_assert(0);
  150. } else {
  151. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  152. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  153. /* Add the tso num segment into the free list */
  154. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  155. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  156. tx_desc->tso_num_desc);
  157. tx_desc->tso_num_desc = NULL;
  158. }
  159. /* Add the tso segment into the free list*/
  160. dp_tx_tso_desc_free(soc,
  161. tx_desc->pool_id, tx_desc->tso_desc);
  162. tx_desc->tso_desc = NULL;
  163. }
  164. }
  165. #else
  166. static void dp_tx_tso_unmap_segment(struct dp_soc *soc,
  167. struct dp_tx_desc_s *tx_desc)
  168. {
  169. }
  170. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  171. struct dp_tx_desc_s *tx_desc)
  172. {
  173. }
  174. #endif
  175. /**
  176. * dp_tx_desc_release() - Release Tx Descriptor
  177. * @tx_desc : Tx Descriptor
  178. * @desc_pool_id: Descriptor Pool ID
  179. *
  180. * Deallocate all resources attached to Tx descriptor and free the Tx
  181. * descriptor.
  182. *
  183. * Return:
  184. */
  185. static void
  186. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  187. {
  188. struct dp_pdev *pdev = tx_desc->pdev;
  189. struct dp_soc *soc;
  190. uint8_t comp_status = 0;
  191. qdf_assert(pdev);
  192. soc = pdev->soc;
  193. if (tx_desc->frm_type == dp_tx_frm_tso)
  194. dp_tx_tso_desc_release(soc, tx_desc);
  195. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  196. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  197. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  198. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  199. qdf_atomic_dec(&pdev->num_tx_outstanding);
  200. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  201. qdf_atomic_dec(&pdev->num_tx_exception);
  202. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  203. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  204. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp);
  205. else
  206. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  207. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  208. "Tx Completion Release desc %d status %d outstanding %d",
  209. tx_desc->id, comp_status,
  210. qdf_atomic_read(&pdev->num_tx_outstanding));
  211. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  212. return;
  213. }
  214. /**
  215. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  216. * @vdev: DP vdev Handle
  217. * @nbuf: skb
  218. *
  219. * Prepares and fills HTT metadata in the frame pre-header for special frames
  220. * that should be transmitted using varying transmit parameters.
  221. * There are 2 VDEV modes that currently needs this special metadata -
  222. * 1) Mesh Mode
  223. * 2) DSRC Mode
  224. *
  225. * Return: HTT metadata size
  226. *
  227. */
  228. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  229. uint32_t *meta_data)
  230. {
  231. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  232. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  233. uint8_t htt_desc_size;
  234. /* Size rounded of multiple of 8 bytes */
  235. uint8_t htt_desc_size_aligned;
  236. uint8_t *hdr = NULL;
  237. /*
  238. * Metadata - HTT MSDU Extension header
  239. */
  240. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  241. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  242. if (vdev->mesh_vdev) {
  243. /* Fill and add HTT metaheader */
  244. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  245. if (hdr == NULL) {
  246. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  247. "Error in filling HTT metadata");
  248. return 0;
  249. }
  250. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  251. } else if (vdev->opmode == wlan_op_mode_ocb) {
  252. /* Todo - Add support for DSRC */
  253. }
  254. return htt_desc_size_aligned;
  255. }
  256. /**
  257. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  258. * @tso_seg: TSO segment to process
  259. * @ext_desc: Pointer to MSDU extension descriptor
  260. *
  261. * Return: void
  262. */
  263. #if defined(FEATURE_TSO)
  264. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  265. void *ext_desc)
  266. {
  267. uint8_t num_frag;
  268. uint32_t tso_flags;
  269. /*
  270. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  271. * tcp_flag_mask
  272. *
  273. * Checksum enable flags are set in TCL descriptor and not in Extension
  274. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  275. */
  276. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  277. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  278. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  279. tso_seg->tso_flags.ip_len);
  280. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  281. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  282. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  283. uint32_t lo = 0;
  284. uint32_t hi = 0;
  285. qdf_dmaaddr_to_32s(
  286. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  287. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  288. tso_seg->tso_frags[num_frag].length);
  289. }
  290. return;
  291. }
  292. #else
  293. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  294. void *ext_desc)
  295. {
  296. return;
  297. }
  298. #endif
  299. #if defined(FEATURE_TSO)
  300. /**
  301. * dp_tx_free_tso_seg() - Loop through the tso segments
  302. * allocated and free them
  303. *
  304. * @soc: soc handle
  305. * @free_seg: list of tso segments
  306. * @msdu_info: msdu descriptor
  307. *
  308. * Return - void
  309. */
  310. static void dp_tx_free_tso_seg(struct dp_soc *soc,
  311. struct qdf_tso_seg_elem_t *free_seg,
  312. struct dp_tx_msdu_info_s *msdu_info)
  313. {
  314. struct qdf_tso_seg_elem_t *next_seg;
  315. while (free_seg) {
  316. next_seg = free_seg->next;
  317. dp_tx_tso_desc_free(soc,
  318. msdu_info->tx_queue.desc_pool_id,
  319. free_seg);
  320. free_seg = next_seg;
  321. }
  322. }
  323. /**
  324. * dp_tx_free_tso_num_seg() - Loop through the tso num segments
  325. * allocated and free them
  326. *
  327. * @soc: soc handle
  328. * @free_seg: list of tso segments
  329. * @msdu_info: msdu descriptor
  330. * Return - void
  331. */
  332. static void dp_tx_free_tso_num_seg(struct dp_soc *soc,
  333. struct qdf_tso_num_seg_elem_t *free_seg,
  334. struct dp_tx_msdu_info_s *msdu_info)
  335. {
  336. struct qdf_tso_num_seg_elem_t *next_seg;
  337. while (free_seg) {
  338. next_seg = free_seg->next;
  339. dp_tso_num_seg_free(soc,
  340. msdu_info->tx_queue.desc_pool_id,
  341. free_seg);
  342. free_seg = next_seg;
  343. }
  344. }
  345. /**
  346. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  347. * @vdev: virtual device handle
  348. * @msdu: network buffer
  349. * @msdu_info: meta data associated with the msdu
  350. *
  351. * Return: QDF_STATUS_SUCCESS success
  352. */
  353. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  354. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  355. {
  356. struct qdf_tso_seg_elem_t *tso_seg;
  357. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  358. struct dp_soc *soc = vdev->pdev->soc;
  359. struct qdf_tso_info_t *tso_info;
  360. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  361. tso_info = &msdu_info->u.tso_info;
  362. tso_info->curr_seg = NULL;
  363. tso_info->tso_seg_list = NULL;
  364. tso_info->num_segs = num_seg;
  365. msdu_info->frm_type = dp_tx_frm_tso;
  366. tso_info->tso_num_seg_list = NULL;
  367. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  368. while (num_seg) {
  369. tso_seg = dp_tx_tso_desc_alloc(
  370. soc, msdu_info->tx_queue.desc_pool_id);
  371. if (tso_seg) {
  372. tso_seg->next = tso_info->tso_seg_list;
  373. tso_info->tso_seg_list = tso_seg;
  374. num_seg--;
  375. } else {
  376. struct qdf_tso_seg_elem_t *free_seg =
  377. tso_info->tso_seg_list;
  378. dp_tx_free_tso_seg(soc, free_seg, msdu_info);
  379. return QDF_STATUS_E_NOMEM;
  380. }
  381. }
  382. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  383. tso_num_seg = dp_tso_num_seg_alloc(soc,
  384. msdu_info->tx_queue.desc_pool_id);
  385. if (tso_num_seg) {
  386. tso_num_seg->next = tso_info->tso_num_seg_list;
  387. tso_info->tso_num_seg_list = tso_num_seg;
  388. } else {
  389. /* Bug: free tso_num_seg and tso_seg */
  390. /* Free the already allocated num of segments */
  391. struct qdf_tso_seg_elem_t *free_seg =
  392. tso_info->tso_seg_list;
  393. TSO_DEBUG(" %s: Failed alloc - Number of segs for a TSO packet",
  394. __func__);
  395. dp_tx_free_tso_seg(soc, free_seg, msdu_info);
  396. return QDF_STATUS_E_NOMEM;
  397. }
  398. msdu_info->num_seg =
  399. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  400. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  401. msdu_info->num_seg);
  402. if (!(msdu_info->num_seg)) {
  403. dp_tx_free_tso_seg(soc, tso_info->tso_seg_list, msdu_info);
  404. dp_tx_free_tso_num_seg(soc, tso_info->tso_num_seg_list,
  405. msdu_info);
  406. return QDF_STATUS_E_INVAL;
  407. }
  408. tso_info->curr_seg = tso_info->tso_seg_list;
  409. return QDF_STATUS_SUCCESS;
  410. }
  411. #else
  412. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  413. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  414. {
  415. return QDF_STATUS_E_NOMEM;
  416. }
  417. #endif
  418. /**
  419. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  420. * @vdev: DP Vdev handle
  421. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  422. * @desc_pool_id: Descriptor Pool ID
  423. *
  424. * Return:
  425. */
  426. static
  427. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  428. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  429. {
  430. uint8_t i;
  431. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  432. struct dp_tx_seg_info_s *seg_info;
  433. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  434. struct dp_soc *soc = vdev->pdev->soc;
  435. /* Allocate an extension descriptor */
  436. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  437. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  438. if (!msdu_ext_desc) {
  439. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  440. return NULL;
  441. }
  442. if (msdu_info->exception_fw &&
  443. qdf_unlikely(vdev->mesh_vdev)) {
  444. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  445. &msdu_info->meta_data[0],
  446. sizeof(struct htt_tx_msdu_desc_ext2_t));
  447. qdf_atomic_inc(&vdev->pdev->num_tx_exception);
  448. }
  449. switch (msdu_info->frm_type) {
  450. case dp_tx_frm_sg:
  451. case dp_tx_frm_me:
  452. case dp_tx_frm_raw:
  453. seg_info = msdu_info->u.sg_info.curr_seg;
  454. /* Update the buffer pointers in MSDU Extension Descriptor */
  455. for (i = 0; i < seg_info->frag_cnt; i++) {
  456. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  457. seg_info->frags[i].paddr_lo,
  458. seg_info->frags[i].paddr_hi,
  459. seg_info->frags[i].len);
  460. }
  461. break;
  462. case dp_tx_frm_tso:
  463. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  464. &cached_ext_desc[0]);
  465. break;
  466. default:
  467. break;
  468. }
  469. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  470. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  471. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  472. msdu_ext_desc->vaddr);
  473. return msdu_ext_desc;
  474. }
  475. /**
  476. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  477. *
  478. * @skb: skb to be traced
  479. * @msdu_id: msdu_id of the packet
  480. * @vdev_id: vdev_id of the packet
  481. *
  482. * Return: None
  483. */
  484. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  485. uint8_t vdev_id)
  486. {
  487. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  488. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  489. DPTRACE(qdf_dp_trace_ptr(skb,
  490. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  491. QDF_TRACE_DEFAULT_PDEV_ID,
  492. qdf_nbuf_data_addr(skb),
  493. sizeof(qdf_nbuf_data(skb)),
  494. msdu_id, vdev_id));
  495. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  496. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  497. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  498. msdu_id, QDF_TX));
  499. }
  500. /**
  501. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  502. * @vdev: DP vdev handle
  503. * @nbuf: skb
  504. * @desc_pool_id: Descriptor pool ID
  505. * @meta_data: Metadata to the fw
  506. * @tx_exc_metadata: Handle that holds exception path metadata
  507. * Allocate and prepare Tx descriptor with msdu information.
  508. *
  509. * Return: Pointer to Tx Descriptor on success,
  510. * NULL on failure
  511. */
  512. static
  513. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  514. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  515. struct dp_tx_msdu_info_s *msdu_info,
  516. struct cdp_tx_exception_metadata *tx_exc_metadata)
  517. {
  518. uint8_t align_pad;
  519. uint8_t is_exception = 0;
  520. uint8_t htt_hdr_size;
  521. struct ether_header *eh;
  522. struct dp_tx_desc_s *tx_desc;
  523. struct dp_pdev *pdev = vdev->pdev;
  524. struct dp_soc *soc = pdev->soc;
  525. /* Allocate software Tx descriptor */
  526. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  527. if (qdf_unlikely(!tx_desc)) {
  528. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  529. return NULL;
  530. }
  531. /* Flow control/Congestion Control counters */
  532. qdf_atomic_inc(&pdev->num_tx_outstanding);
  533. /* Initialize the SW tx descriptor */
  534. tx_desc->nbuf = nbuf;
  535. tx_desc->frm_type = dp_tx_frm_std;
  536. tx_desc->tx_encap_type = (tx_exc_metadata ?
  537. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  538. tx_desc->vdev = vdev;
  539. tx_desc->pdev = pdev;
  540. tx_desc->msdu_ext_desc = NULL;
  541. tx_desc->pkt_offset = 0;
  542. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  543. /* Reset the control block */
  544. qdf_nbuf_reset_ctxt(nbuf);
  545. /*
  546. * For special modes (vdev_type == ocb or mesh), data frames should be
  547. * transmitted using varying transmit parameters (tx spec) which include
  548. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  549. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  550. * These frames are sent as exception packets to firmware.
  551. *
  552. * HW requirement is that metadata should always point to a
  553. * 8-byte aligned address. So we add alignment pad to start of buffer.
  554. * HTT Metadata should be ensured to be multiple of 8-bytes,
  555. * to get 8-byte aligned start address along with align_pad added
  556. *
  557. * |-----------------------------|
  558. * | |
  559. * |-----------------------------| <-----Buffer Pointer Address given
  560. * | | ^ in HW descriptor (aligned)
  561. * | HTT Metadata | |
  562. * | | |
  563. * | | | Packet Offset given in descriptor
  564. * | | |
  565. * |-----------------------------| |
  566. * | Alignment Pad | v
  567. * |-----------------------------| <----- Actual buffer start address
  568. * | SKB Data | (Unaligned)
  569. * | |
  570. * | |
  571. * | |
  572. * | |
  573. * | |
  574. * |-----------------------------|
  575. */
  576. if (qdf_unlikely((msdu_info->exception_fw)) ||
  577. (vdev->opmode == wlan_op_mode_ocb)) {
  578. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  579. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  580. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  581. "qdf_nbuf_push_head failed");
  582. goto failure;
  583. }
  584. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  585. msdu_info->meta_data);
  586. if (htt_hdr_size == 0)
  587. goto failure;
  588. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  589. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  590. is_exception = 1;
  591. }
  592. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  593. qdf_nbuf_map(soc->osdev, nbuf,
  594. QDF_DMA_TO_DEVICE))) {
  595. /* Handle failure */
  596. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  597. "qdf_nbuf_map failed");
  598. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  599. goto failure;
  600. }
  601. if (qdf_unlikely(vdev->nawds_enabled)) {
  602. eh = (struct ether_header *) qdf_nbuf_data(nbuf);
  603. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  604. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  605. is_exception = 1;
  606. }
  607. }
  608. #if !TQM_BYPASS_WAR
  609. if (is_exception || tx_exc_metadata)
  610. #endif
  611. {
  612. /* Temporary WAR due to TQM VP issues */
  613. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  614. qdf_atomic_inc(&pdev->num_tx_exception);
  615. }
  616. return tx_desc;
  617. failure:
  618. dp_tx_desc_release(tx_desc, desc_pool_id);
  619. return NULL;
  620. }
  621. /**
  622. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  623. * @vdev: DP vdev handle
  624. * @nbuf: skb
  625. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  626. * @desc_pool_id : Descriptor Pool ID
  627. *
  628. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  629. * information. For frames wth fragments, allocate and prepare
  630. * an MSDU extension descriptor
  631. *
  632. * Return: Pointer to Tx Descriptor on success,
  633. * NULL on failure
  634. */
  635. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  636. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  637. uint8_t desc_pool_id)
  638. {
  639. struct dp_tx_desc_s *tx_desc;
  640. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  641. struct dp_pdev *pdev = vdev->pdev;
  642. struct dp_soc *soc = pdev->soc;
  643. /* Allocate software Tx descriptor */
  644. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  645. if (!tx_desc) {
  646. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  647. return NULL;
  648. }
  649. /* Flow control/Congestion Control counters */
  650. qdf_atomic_inc(&pdev->num_tx_outstanding);
  651. /* Initialize the SW tx descriptor */
  652. tx_desc->nbuf = nbuf;
  653. tx_desc->frm_type = msdu_info->frm_type;
  654. tx_desc->tx_encap_type = vdev->tx_encap_type;
  655. tx_desc->vdev = vdev;
  656. tx_desc->pdev = pdev;
  657. tx_desc->pkt_offset = 0;
  658. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  659. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  660. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  661. /* Reset the control block */
  662. qdf_nbuf_reset_ctxt(nbuf);
  663. /* Handle scattered frames - TSO/SG/ME */
  664. /* Allocate and prepare an extension descriptor for scattered frames */
  665. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  666. if (!msdu_ext_desc) {
  667. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  668. "%s Tx Extension Descriptor Alloc Fail",
  669. __func__);
  670. goto failure;
  671. }
  672. #if TQM_BYPASS_WAR
  673. /* Temporary WAR due to TQM VP issues */
  674. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  675. qdf_atomic_inc(&pdev->num_tx_exception);
  676. #endif
  677. if (qdf_unlikely(msdu_info->exception_fw))
  678. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  679. tx_desc->msdu_ext_desc = msdu_ext_desc;
  680. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  681. return tx_desc;
  682. failure:
  683. dp_tx_desc_release(tx_desc, desc_pool_id);
  684. return NULL;
  685. }
  686. /**
  687. * dp_tx_prepare_raw() - Prepare RAW packet TX
  688. * @vdev: DP vdev handle
  689. * @nbuf: buffer pointer
  690. * @seg_info: Pointer to Segment info Descriptor to be prepared
  691. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  692. * descriptor
  693. *
  694. * Return:
  695. */
  696. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  697. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  698. {
  699. qdf_nbuf_t curr_nbuf = NULL;
  700. uint16_t total_len = 0;
  701. qdf_dma_addr_t paddr;
  702. int32_t i;
  703. int32_t mapped_buf_num = 0;
  704. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  705. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  706. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  707. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  708. if (qos_wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS)
  709. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  710. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  711. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  712. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, curr_nbuf,
  713. QDF_DMA_TO_DEVICE)) {
  714. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  715. "%s dma map error ", __func__);
  716. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  717. mapped_buf_num = i;
  718. goto error;
  719. }
  720. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  721. seg_info->frags[i].paddr_lo = paddr;
  722. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  723. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  724. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  725. total_len += qdf_nbuf_len(curr_nbuf);
  726. }
  727. seg_info->frag_cnt = i;
  728. seg_info->total_len = total_len;
  729. seg_info->next = NULL;
  730. sg_info->curr_seg = seg_info;
  731. msdu_info->frm_type = dp_tx_frm_raw;
  732. msdu_info->num_seg = 1;
  733. return nbuf;
  734. error:
  735. i = 0;
  736. while (nbuf) {
  737. curr_nbuf = nbuf;
  738. if (i < mapped_buf_num) {
  739. qdf_nbuf_unmap(vdev->osdev, curr_nbuf, QDF_DMA_TO_DEVICE);
  740. i++;
  741. }
  742. nbuf = qdf_nbuf_next(nbuf);
  743. qdf_nbuf_free(curr_nbuf);
  744. }
  745. return NULL;
  746. }
  747. /**
  748. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  749. * @soc: DP Soc Handle
  750. * @vdev: DP vdev handle
  751. * @tx_desc: Tx Descriptor Handle
  752. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  753. * @fw_metadata: Metadata to send to Target Firmware along with frame
  754. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  755. * @tx_exc_metadata: Handle that holds exception path meta data
  756. *
  757. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  758. * from software Tx descriptor
  759. *
  760. * Return:
  761. */
  762. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  763. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  764. uint16_t fw_metadata, uint8_t ring_id,
  765. struct cdp_tx_exception_metadata
  766. *tx_exc_metadata)
  767. {
  768. uint8_t type;
  769. uint16_t length;
  770. void *hal_tx_desc, *hal_tx_desc_cached;
  771. qdf_dma_addr_t dma_addr;
  772. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES];
  773. enum cdp_sec_type sec_type = (tx_exc_metadata ?
  774. tx_exc_metadata->sec_type : vdev->sec_type);
  775. /* Return Buffer Manager ID */
  776. uint8_t bm_id = ring_id;
  777. void *hal_srng = soc->tcl_data_ring[ring_id].hal_srng;
  778. hal_tx_desc_cached = (void *) cached_desc;
  779. qdf_mem_zero_outline(hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
  780. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  781. length = HAL_TX_EXT_DESC_WITH_META_DATA;
  782. type = HAL_TX_BUF_TYPE_EXT_DESC;
  783. dma_addr = tx_desc->msdu_ext_desc->paddr;
  784. } else {
  785. length = qdf_nbuf_len(tx_desc->nbuf) - tx_desc->pkt_offset;
  786. type = HAL_TX_BUF_TYPE_BUFFER;
  787. dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  788. }
  789. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  790. hal_tx_desc_set_buf_addr(hal_tx_desc_cached,
  791. dma_addr , bm_id, tx_desc->id, type);
  792. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id))
  793. return QDF_STATUS_E_RESOURCES;
  794. hal_tx_desc_set_buf_length(hal_tx_desc_cached, length);
  795. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  796. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  797. hal_tx_desc_set_lmac_id(soc->hal_soc, hal_tx_desc_cached,
  798. HAL_TX_DESC_DEFAULT_LMAC_ID);
  799. hal_tx_desc_set_dscp_tid_table_id(soc->hal_soc, hal_tx_desc_cached,
  800. vdev->dscp_tid_map_id);
  801. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  802. sec_type_map[sec_type]);
  803. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  804. "%s length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  805. __func__, length, type, (uint64_t)dma_addr,
  806. tx_desc->pkt_offset, tx_desc->id);
  807. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  808. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  809. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  810. vdev->hal_desc_addr_search_flags);
  811. /* verify checksum offload configuration*/
  812. if ((wlan_cfg_get_checksum_offload(soc->wlan_cfg_ctx)) &&
  813. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  814. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  815. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  816. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  817. }
  818. if (tid != HTT_TX_EXT_TID_INVALID)
  819. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  820. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  821. hal_tx_desc_set_mesh_en(hal_tx_desc_cached, 1);
  822. /* Sync cached descriptor with HW */
  823. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_srng);
  824. if (!hal_tx_desc) {
  825. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  826. "%s TCL ring full ring_id:%d", __func__, ring_id);
  827. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  828. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  829. return QDF_STATUS_E_RESOURCES;
  830. }
  831. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  832. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  833. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, length);
  834. return QDF_STATUS_SUCCESS;
  835. }
  836. /**
  837. * dp_cce_classify() - Classify the frame based on CCE rules
  838. * @vdev: DP vdev handle
  839. * @nbuf: skb
  840. *
  841. * Classify frames based on CCE rules
  842. * Return: bool( true if classified,
  843. * else false)
  844. */
  845. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  846. {
  847. struct ether_header *eh = NULL;
  848. uint16_t ether_type;
  849. qdf_llc_t *llcHdr;
  850. qdf_nbuf_t nbuf_clone = NULL;
  851. qdf_dot3_qosframe_t *qos_wh = NULL;
  852. /* for mesh packets don't do any classification */
  853. if (qdf_unlikely(vdev->mesh_vdev))
  854. return false;
  855. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  856. eh = (struct ether_header *) qdf_nbuf_data(nbuf);
  857. ether_type = eh->ether_type;
  858. llcHdr = (qdf_llc_t *)(nbuf->data +
  859. sizeof(struct ether_header));
  860. } else {
  861. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  862. /* For encrypted packets don't do any classification */
  863. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  864. return false;
  865. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  866. if (qdf_unlikely(
  867. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  868. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  869. ether_type = *(uint16_t *)(nbuf->data
  870. + QDF_IEEE80211_4ADDR_HDR_LEN
  871. + sizeof(qdf_llc_t)
  872. - sizeof(ether_type));
  873. llcHdr = (qdf_llc_t *)(nbuf->data +
  874. QDF_IEEE80211_4ADDR_HDR_LEN);
  875. } else {
  876. ether_type = *(uint16_t *)(nbuf->data
  877. + QDF_IEEE80211_3ADDR_HDR_LEN
  878. + sizeof(qdf_llc_t)
  879. - sizeof(ether_type));
  880. llcHdr = (qdf_llc_t *)(nbuf->data +
  881. QDF_IEEE80211_3ADDR_HDR_LEN);
  882. }
  883. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  884. && (ether_type ==
  885. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  886. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  887. return true;
  888. }
  889. }
  890. return false;
  891. }
  892. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  893. ether_type = *(uint16_t *)(nbuf->data + 2*ETHER_ADDR_LEN +
  894. sizeof(*llcHdr));
  895. nbuf_clone = qdf_nbuf_clone(nbuf);
  896. if (qdf_unlikely(nbuf_clone)) {
  897. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  898. if (ether_type == htons(ETHERTYPE_8021Q)) {
  899. qdf_nbuf_pull_head(nbuf_clone,
  900. sizeof(qdf_net_vlanhdr_t));
  901. }
  902. }
  903. } else {
  904. if (ether_type == htons(ETHERTYPE_8021Q)) {
  905. nbuf_clone = qdf_nbuf_clone(nbuf);
  906. if (qdf_unlikely(nbuf_clone)) {
  907. qdf_nbuf_pull_head(nbuf_clone,
  908. sizeof(qdf_net_vlanhdr_t));
  909. }
  910. }
  911. }
  912. if (qdf_unlikely(nbuf_clone))
  913. nbuf = nbuf_clone;
  914. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  915. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  916. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  917. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  918. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  919. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  920. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  921. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  922. if (qdf_unlikely(nbuf_clone != NULL))
  923. qdf_nbuf_free(nbuf_clone);
  924. return true;
  925. }
  926. if (qdf_unlikely(nbuf_clone != NULL))
  927. qdf_nbuf_free(nbuf_clone);
  928. return false;
  929. }
  930. /**
  931. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  932. * @vdev: DP vdev handle
  933. * @nbuf: skb
  934. *
  935. * Extract the DSCP or PCP information from frame and map into TID value.
  936. * Software based TID classification is required when more than 2 DSCP-TID
  937. * mapping tables are needed.
  938. * Hardware supports 2 DSCP-TID mapping tables
  939. *
  940. * Return: void
  941. */
  942. static void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  943. struct dp_tx_msdu_info_s *msdu_info)
  944. {
  945. uint8_t tos = 0, dscp_tid_override = 0;
  946. uint8_t *hdr_ptr, *L3datap;
  947. uint8_t is_mcast = 0;
  948. struct ether_header *eh = NULL;
  949. qdf_ethervlan_header_t *evh = NULL;
  950. uint16_t ether_type;
  951. qdf_llc_t *llcHdr;
  952. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  953. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  954. if (vdev->dscp_tid_map_id <= 1)
  955. return;
  956. /* for mesh packets don't do any classification */
  957. if (qdf_unlikely(vdev->mesh_vdev))
  958. return;
  959. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  960. eh = (struct ether_header *) nbuf->data;
  961. hdr_ptr = eh->ether_dhost;
  962. L3datap = hdr_ptr + sizeof(struct ether_header);
  963. } else {
  964. qdf_dot3_qosframe_t *qos_wh =
  965. (qdf_dot3_qosframe_t *) nbuf->data;
  966. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  967. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  968. return;
  969. }
  970. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  971. ether_type = eh->ether_type;
  972. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(struct ether_header));
  973. /*
  974. * Check if packet is dot3 or eth2 type.
  975. */
  976. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  977. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN +
  978. sizeof(*llcHdr));
  979. if (ether_type == htons(ETHERTYPE_8021Q)) {
  980. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  981. sizeof(*llcHdr);
  982. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN
  983. + sizeof(*llcHdr) +
  984. sizeof(qdf_net_vlanhdr_t));
  985. } else {
  986. L3datap = hdr_ptr + sizeof(struct ether_header) +
  987. sizeof(*llcHdr);
  988. }
  989. } else {
  990. if (ether_type == htons(ETHERTYPE_8021Q)) {
  991. evh = (qdf_ethervlan_header_t *) eh;
  992. ether_type = evh->ether_type;
  993. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  994. }
  995. }
  996. /*
  997. * Find priority from IP TOS DSCP field
  998. */
  999. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1000. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1001. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1002. /* Only for unicast frames */
  1003. if (!is_mcast) {
  1004. /* send it on VO queue */
  1005. msdu_info->tid = DP_VO_TID;
  1006. }
  1007. } else {
  1008. /*
  1009. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1010. * from TOS byte.
  1011. */
  1012. tos = ip->ip_tos;
  1013. dscp_tid_override = 1;
  1014. }
  1015. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1016. /* TODO
  1017. * use flowlabel
  1018. *igmpmld cases to be handled in phase 2
  1019. */
  1020. unsigned long ver_pri_flowlabel;
  1021. unsigned long pri;
  1022. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1023. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1024. DP_IPV6_PRIORITY_SHIFT;
  1025. tos = pri;
  1026. dscp_tid_override = 1;
  1027. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1028. msdu_info->tid = DP_VO_TID;
  1029. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1030. /* Only for unicast frames */
  1031. if (!is_mcast) {
  1032. /* send ucast arp on VO queue */
  1033. msdu_info->tid = DP_VO_TID;
  1034. }
  1035. }
  1036. /*
  1037. * Assign all MCAST packets to BE
  1038. */
  1039. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1040. if (is_mcast) {
  1041. tos = 0;
  1042. dscp_tid_override = 1;
  1043. }
  1044. }
  1045. if (dscp_tid_override == 1) {
  1046. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1047. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1048. }
  1049. return;
  1050. }
  1051. #ifdef CONVERGED_TDLS_ENABLE
  1052. /**
  1053. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1054. * @tx_desc: TX descriptor
  1055. *
  1056. * Return: None
  1057. */
  1058. static void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1059. {
  1060. if (tx_desc->vdev) {
  1061. if (tx_desc->vdev->is_tdls_frame)
  1062. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1063. tx_desc->vdev->is_tdls_frame = false;
  1064. }
  1065. }
  1066. /**
  1067. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1068. * @tx_desc: TX descriptor
  1069. * @vdev: datapath vdev handle
  1070. *
  1071. * Return: None
  1072. */
  1073. static void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1074. struct dp_vdev *vdev)
  1075. {
  1076. struct hal_tx_completion_status ts = {0};
  1077. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1078. hal_tx_comp_get_status(&tx_desc->comp, &ts);
  1079. if (vdev->tx_non_std_data_callback.func) {
  1080. qdf_nbuf_set_next(tx_desc->nbuf, NULL);
  1081. vdev->tx_non_std_data_callback.func(
  1082. vdev->tx_non_std_data_callback.ctxt,
  1083. nbuf, ts.status);
  1084. return;
  1085. }
  1086. }
  1087. #endif
  1088. /**
  1089. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1090. * @vdev: DP vdev handle
  1091. * @nbuf: skb
  1092. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1093. * @meta_data: Metadata to the fw
  1094. * @tx_q: Tx queue to be used for this Tx frame
  1095. * @peer_id: peer_id of the peer in case of NAWDS frames
  1096. * @tx_exc_metadata: Handle that holds exception path metadata
  1097. *
  1098. * Return: NULL on success,
  1099. * nbuf when it fails to send
  1100. */
  1101. static qdf_nbuf_t dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1102. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1103. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1104. {
  1105. struct dp_pdev *pdev = vdev->pdev;
  1106. struct dp_soc *soc = pdev->soc;
  1107. struct dp_tx_desc_s *tx_desc;
  1108. QDF_STATUS status;
  1109. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1110. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1111. uint16_t htt_tcl_metadata = 0;
  1112. uint8_t tid = msdu_info->tid;
  1113. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1114. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1115. msdu_info, tx_exc_metadata);
  1116. if (!tx_desc) {
  1117. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1118. "%s Tx_desc prepare Fail vdev %pK queue %d",
  1119. __func__, vdev, tx_q->desc_pool_id);
  1120. return nbuf;
  1121. }
  1122. if (qdf_unlikely(soc->cce_disable)) {
  1123. if (dp_cce_classify(vdev, nbuf) == true) {
  1124. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1125. tid = DP_VO_TID;
  1126. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1127. }
  1128. }
  1129. dp_tx_update_tdls_flags(tx_desc);
  1130. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1131. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1132. "%s %d : HAL RING Access Failed -- %pK",
  1133. __func__, __LINE__, hal_srng);
  1134. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1135. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1136. goto fail_return;
  1137. }
  1138. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1139. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1140. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1141. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1142. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1143. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1144. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1145. peer_id);
  1146. } else
  1147. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1148. if (msdu_info->exception_fw) {
  1149. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1150. }
  1151. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1152. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  1153. htt_tcl_metadata, tx_q->ring_id, tx_exc_metadata);
  1154. if (status != QDF_STATUS_SUCCESS) {
  1155. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1156. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1157. __func__, tx_desc, tx_q->ring_id);
  1158. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1159. goto fail_return;
  1160. }
  1161. nbuf = NULL;
  1162. fail_return:
  1163. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1164. hal_srng_access_end(soc->hal_soc, hal_srng);
  1165. hif_pm_runtime_put(soc->hif_handle);
  1166. } else {
  1167. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1168. }
  1169. return nbuf;
  1170. }
  1171. /**
  1172. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1173. * @vdev: DP vdev handle
  1174. * @nbuf: skb
  1175. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1176. *
  1177. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1178. *
  1179. * Return: NULL on success,
  1180. * nbuf when it fails to send
  1181. */
  1182. #if QDF_LOCK_STATS
  1183. static noinline
  1184. #else
  1185. static
  1186. #endif
  1187. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1188. struct dp_tx_msdu_info_s *msdu_info)
  1189. {
  1190. uint8_t i;
  1191. struct dp_pdev *pdev = vdev->pdev;
  1192. struct dp_soc *soc = pdev->soc;
  1193. struct dp_tx_desc_s *tx_desc;
  1194. bool is_cce_classified = false;
  1195. QDF_STATUS status;
  1196. uint16_t htt_tcl_metadata = 0;
  1197. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1198. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1199. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1200. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1201. "%s %d : HAL RING Access Failed -- %pK",
  1202. __func__, __LINE__, hal_srng);
  1203. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1204. return nbuf;
  1205. }
  1206. if (qdf_unlikely(soc->cce_disable)) {
  1207. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1208. if (is_cce_classified) {
  1209. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1210. msdu_info->tid = DP_VO_TID;
  1211. }
  1212. }
  1213. if (msdu_info->frm_type == dp_tx_frm_me)
  1214. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1215. i = 0;
  1216. /* Print statement to track i and num_seg */
  1217. /*
  1218. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1219. * descriptors using information in msdu_info
  1220. */
  1221. while (i < msdu_info->num_seg) {
  1222. /*
  1223. * Setup Tx descriptor for an MSDU, and MSDU extension
  1224. * descriptor
  1225. */
  1226. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1227. tx_q->desc_pool_id);
  1228. if (!tx_desc) {
  1229. if (msdu_info->frm_type == dp_tx_frm_me) {
  1230. dp_tx_me_free_buf(pdev,
  1231. (void *)(msdu_info->u.sg_info
  1232. .curr_seg->frags[0].vaddr));
  1233. }
  1234. goto done;
  1235. }
  1236. if (msdu_info->frm_type == dp_tx_frm_me) {
  1237. tx_desc->me_buffer =
  1238. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1239. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1240. }
  1241. if (is_cce_classified)
  1242. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1243. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1244. if (msdu_info->exception_fw) {
  1245. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1246. }
  1247. /*
  1248. * Enqueue the Tx MSDU descriptor to HW for transmit
  1249. */
  1250. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  1251. htt_tcl_metadata, tx_q->ring_id, NULL);
  1252. if (status != QDF_STATUS_SUCCESS) {
  1253. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1254. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1255. __func__, tx_desc, tx_q->ring_id);
  1256. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  1257. dp_tx_me_free_buf(pdev, tx_desc->me_buffer);
  1258. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1259. goto done;
  1260. }
  1261. /*
  1262. * TODO
  1263. * if tso_info structure can be modified to have curr_seg
  1264. * as first element, following 2 blocks of code (for TSO and SG)
  1265. * can be combined into 1
  1266. */
  1267. /*
  1268. * For frames with multiple segments (TSO, ME), jump to next
  1269. * segment.
  1270. */
  1271. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1272. if (msdu_info->u.tso_info.curr_seg->next) {
  1273. msdu_info->u.tso_info.curr_seg =
  1274. msdu_info->u.tso_info.curr_seg->next;
  1275. /*
  1276. * If this is a jumbo nbuf, then increment the number of
  1277. * nbuf users for each additional segment of the msdu.
  1278. * This will ensure that the skb is freed only after
  1279. * receiving tx completion for all segments of an nbuf
  1280. */
  1281. qdf_nbuf_inc_users(nbuf);
  1282. /* Check with MCL if this is needed */
  1283. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1284. }
  1285. }
  1286. /*
  1287. * For Multicast-Unicast converted packets,
  1288. * each converted frame (for a client) is represented as
  1289. * 1 segment
  1290. */
  1291. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1292. (msdu_info->frm_type == dp_tx_frm_me)) {
  1293. if (msdu_info->u.sg_info.curr_seg->next) {
  1294. msdu_info->u.sg_info.curr_seg =
  1295. msdu_info->u.sg_info.curr_seg->next;
  1296. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1297. }
  1298. }
  1299. i++;
  1300. }
  1301. nbuf = NULL;
  1302. done:
  1303. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1304. hal_srng_access_end(soc->hal_soc, hal_srng);
  1305. hif_pm_runtime_put(soc->hif_handle);
  1306. } else {
  1307. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1308. }
  1309. return nbuf;
  1310. }
  1311. /**
  1312. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1313. * for SG frames
  1314. * @vdev: DP vdev handle
  1315. * @nbuf: skb
  1316. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1317. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1318. *
  1319. * Return: NULL on success,
  1320. * nbuf when it fails to send
  1321. */
  1322. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1323. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1324. {
  1325. uint32_t cur_frag, nr_frags;
  1326. qdf_dma_addr_t paddr;
  1327. struct dp_tx_sg_info_s *sg_info;
  1328. sg_info = &msdu_info->u.sg_info;
  1329. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1330. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, nbuf,
  1331. QDF_DMA_TO_DEVICE)) {
  1332. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1333. "dma map error");
  1334. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1335. qdf_nbuf_free(nbuf);
  1336. return NULL;
  1337. }
  1338. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1339. seg_info->frags[0].paddr_lo = paddr;
  1340. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  1341. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1342. seg_info->frags[0].vaddr = (void *) nbuf;
  1343. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1344. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1345. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1346. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1347. "frag dma map error");
  1348. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1349. qdf_nbuf_free(nbuf);
  1350. return NULL;
  1351. }
  1352. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1353. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1354. seg_info->frags[cur_frag + 1].paddr_hi =
  1355. ((uint64_t) paddr) >> 32;
  1356. seg_info->frags[cur_frag + 1].len =
  1357. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1358. }
  1359. seg_info->frag_cnt = (cur_frag + 1);
  1360. seg_info->total_len = qdf_nbuf_len(nbuf);
  1361. seg_info->next = NULL;
  1362. sg_info->curr_seg = seg_info;
  1363. msdu_info->frm_type = dp_tx_frm_sg;
  1364. msdu_info->num_seg = 1;
  1365. return nbuf;
  1366. }
  1367. #ifdef MESH_MODE_SUPPORT
  1368. /**
  1369. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1370. and prepare msdu_info for mesh frames.
  1371. * @vdev: DP vdev handle
  1372. * @nbuf: skb
  1373. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1374. *
  1375. * Return: NULL on failure,
  1376. * nbuf when extracted successfully
  1377. */
  1378. static
  1379. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1380. struct dp_tx_msdu_info_s *msdu_info)
  1381. {
  1382. struct meta_hdr_s *mhdr;
  1383. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1384. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1385. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1386. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  1387. msdu_info->exception_fw = 0;
  1388. goto remove_meta_hdr;
  1389. }
  1390. msdu_info->exception_fw = 1;
  1391. qdf_mem_set(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t), 0);
  1392. meta_data->host_tx_desc_pool = 1;
  1393. meta_data->update_peer_cache = 1;
  1394. meta_data->learning_frame = 1;
  1395. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1396. meta_data->power = mhdr->power;
  1397. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1398. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1399. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1400. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1401. meta_data->dyn_bw = 1;
  1402. meta_data->valid_pwr = 1;
  1403. meta_data->valid_mcs_mask = 1;
  1404. meta_data->valid_nss_mask = 1;
  1405. meta_data->valid_preamble_type = 1;
  1406. meta_data->valid_retries = 1;
  1407. meta_data->valid_bw_info = 1;
  1408. }
  1409. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1410. meta_data->encrypt_type = 0;
  1411. meta_data->valid_encrypt_type = 1;
  1412. meta_data->learning_frame = 0;
  1413. }
  1414. meta_data->valid_key_flags = 1;
  1415. meta_data->key_flags = (mhdr->keyix & 0x3);
  1416. remove_meta_hdr:
  1417. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1418. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1419. "qdf_nbuf_pull_head failed");
  1420. qdf_nbuf_free(nbuf);
  1421. return NULL;
  1422. }
  1423. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  1424. msdu_info->tid = HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST;
  1425. else
  1426. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1427. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1428. "%s , Meta hdr %0x %0x %0x %0x %0x %0x"
  1429. " tid %d to_fw %d",
  1430. __func__, msdu_info->meta_data[0],
  1431. msdu_info->meta_data[1],
  1432. msdu_info->meta_data[2],
  1433. msdu_info->meta_data[3],
  1434. msdu_info->meta_data[4],
  1435. msdu_info->meta_data[5],
  1436. msdu_info->tid, msdu_info->exception_fw);
  1437. return nbuf;
  1438. }
  1439. #else
  1440. static
  1441. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1442. struct dp_tx_msdu_info_s *msdu_info)
  1443. {
  1444. return nbuf;
  1445. }
  1446. #endif
  1447. #ifdef DP_FEATURE_NAWDS_TX
  1448. /**
  1449. * dp_tx_prepare_nawds(): Tramit NAWDS frames
  1450. * @vdev: dp_vdev handle
  1451. * @nbuf: skb
  1452. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1453. * @tx_q: Tx queue to be used for this Tx frame
  1454. * @meta_data: Meta date for mesh
  1455. * @peer_id: peer_id of the peer in case of NAWDS frames
  1456. *
  1457. * return: NULL on success nbuf on failure
  1458. */
  1459. static qdf_nbuf_t dp_tx_prepare_nawds(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1460. struct dp_tx_msdu_info_s *msdu_info)
  1461. {
  1462. struct dp_peer *peer = NULL;
  1463. struct dp_soc *soc = vdev->pdev->soc;
  1464. struct dp_ast_entry *ast_entry = NULL;
  1465. struct ether_header *eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1466. uint16_t peer_id = HTT_INVALID_PEER;
  1467. struct dp_peer *sa_peer = NULL;
  1468. qdf_nbuf_t nbuf_copy;
  1469. qdf_spin_lock_bh(&(soc->ast_lock));
  1470. ast_entry = dp_peer_ast_hash_find(soc, (uint8_t *)(eh->ether_shost));
  1471. if (ast_entry)
  1472. sa_peer = ast_entry->peer;
  1473. qdf_spin_unlock_bh(&(soc->ast_lock));
  1474. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1475. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1476. (peer->nawds_enabled)) {
  1477. if (sa_peer == peer) {
  1478. QDF_TRACE(QDF_MODULE_ID_DP,
  1479. QDF_TRACE_LEVEL_DEBUG,
  1480. " %s: broadcast multicast packet",
  1481. __func__);
  1482. DP_STATS_INC(peer, tx.nawds_mcast_drop, 1);
  1483. continue;
  1484. }
  1485. nbuf_copy = qdf_nbuf_copy(nbuf);
  1486. if (!nbuf_copy) {
  1487. QDF_TRACE(QDF_MODULE_ID_DP,
  1488. QDF_TRACE_LEVEL_ERROR,
  1489. "nbuf copy failed");
  1490. }
  1491. peer_id = peer->peer_ids[0];
  1492. nbuf_copy = dp_tx_send_msdu_single(vdev, nbuf_copy,
  1493. msdu_info, peer_id, NULL);
  1494. if (nbuf_copy != NULL) {
  1495. qdf_nbuf_free(nbuf_copy);
  1496. continue;
  1497. }
  1498. DP_STATS_INC_PKT(peer, tx.nawds_mcast,
  1499. 1, qdf_nbuf_len(nbuf));
  1500. }
  1501. }
  1502. if (peer_id == HTT_INVALID_PEER)
  1503. return nbuf;
  1504. return NULL;
  1505. }
  1506. #endif
  1507. /**
  1508. * dp_check_exc_metadata() - Checks if parameters are valid
  1509. * @tx_exc - holds all exception path parameters
  1510. *
  1511. * Returns true when all the parameters are valid else false
  1512. *
  1513. */
  1514. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  1515. {
  1516. if ((tx_exc->tid > DP_MAX_TIDS && tx_exc->tid != HTT_INVALID_TID) ||
  1517. tx_exc->tx_encap_type > htt_cmn_pkt_num_types ||
  1518. tx_exc->sec_type > cdp_num_sec_types) {
  1519. return false;
  1520. }
  1521. return true;
  1522. }
  1523. /**
  1524. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  1525. * @vap_dev: DP vdev handle
  1526. * @nbuf: skb
  1527. * @tx_exc_metadata: Handle that holds exception path meta data
  1528. *
  1529. * Entry point for Core Tx layer (DP_TX) invoked from
  1530. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  1531. *
  1532. * Return: NULL on success,
  1533. * nbuf when it fails to send
  1534. */
  1535. qdf_nbuf_t dp_tx_send_exception(void *vap_dev, qdf_nbuf_t nbuf,
  1536. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1537. {
  1538. struct ether_header *eh = NULL;
  1539. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1540. struct dp_tx_msdu_info_s msdu_info;
  1541. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1542. msdu_info.tid = tx_exc_metadata->tid;
  1543. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1544. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1545. "%s , skb %pM",
  1546. __func__, nbuf->data);
  1547. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1548. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  1549. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1550. "Invalid parameters in exception path");
  1551. goto fail;
  1552. }
  1553. /* Basic sanity checks for unsupported packets */
  1554. /* MESH mode */
  1555. if (qdf_unlikely(vdev->mesh_vdev)) {
  1556. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1557. "Mesh mode is not supported in exception path");
  1558. goto fail;
  1559. }
  1560. /* TSO or SG */
  1561. if (qdf_unlikely(qdf_nbuf_is_tso(nbuf)) ||
  1562. qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1563. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1564. "TSO and SG are not supported in exception path");
  1565. goto fail;
  1566. }
  1567. /* RAW */
  1568. if (qdf_unlikely(tx_exc_metadata->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1569. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1570. "Raw frame is not supported in exception path");
  1571. goto fail;
  1572. }
  1573. /* Mcast enhancement*/
  1574. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1575. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  1576. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1577. "Ignoring mcast_enhancement_en which is set and sending the mcast packet to the FW");
  1578. }
  1579. }
  1580. /*
  1581. * Get HW Queue to use for this frame.
  1582. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1583. * dedicated for data and 1 for command.
  1584. * "queue_id" maps to one hardware ring.
  1585. * With each ring, we also associate a unique Tx descriptor pool
  1586. * to minimize lock contention for these resources.
  1587. */
  1588. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1589. /* Single linear frame */
  1590. /*
  1591. * If nbuf is a simple linear frame, use send_single function to
  1592. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1593. * SRNG. There is no need to setup a MSDU extension descriptor.
  1594. */
  1595. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  1596. tx_exc_metadata->peer_id, tx_exc_metadata);
  1597. return nbuf;
  1598. fail:
  1599. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1600. "pkt send failed");
  1601. return nbuf;
  1602. }
  1603. /**
  1604. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  1605. * @vap_dev: DP vdev handle
  1606. * @nbuf: skb
  1607. *
  1608. * Entry point for Core Tx layer (DP_TX) invoked from
  1609. * hard_start_xmit in OSIF/HDD
  1610. *
  1611. * Return: NULL on success,
  1612. * nbuf when it fails to send
  1613. */
  1614. #ifdef MESH_MODE_SUPPORT
  1615. qdf_nbuf_t dp_tx_send_mesh(void *vap_dev, qdf_nbuf_t nbuf)
  1616. {
  1617. struct meta_hdr_s *mhdr;
  1618. qdf_nbuf_t nbuf_mesh = NULL;
  1619. qdf_nbuf_t nbuf_clone = NULL;
  1620. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1621. uint8_t no_enc_frame = 0;
  1622. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  1623. if (nbuf_mesh == NULL) {
  1624. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1625. "qdf_nbuf_unshare failed");
  1626. return nbuf;
  1627. }
  1628. nbuf = nbuf_mesh;
  1629. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1630. if ((vdev->sec_type != cdp_sec_type_none) &&
  1631. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  1632. no_enc_frame = 1;
  1633. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  1634. !no_enc_frame) {
  1635. nbuf_clone = qdf_nbuf_clone(nbuf);
  1636. if (nbuf_clone == NULL) {
  1637. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1638. "qdf_nbuf_clone failed");
  1639. return nbuf;
  1640. }
  1641. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  1642. }
  1643. if (nbuf_clone) {
  1644. if (!dp_tx_send(vap_dev, nbuf_clone)) {
  1645. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1646. } else {
  1647. qdf_nbuf_free(nbuf_clone);
  1648. }
  1649. }
  1650. if (no_enc_frame)
  1651. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  1652. else
  1653. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  1654. nbuf = dp_tx_send(vap_dev, nbuf);
  1655. if ((nbuf == NULL) && no_enc_frame) {
  1656. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1657. }
  1658. return nbuf;
  1659. }
  1660. #else
  1661. qdf_nbuf_t dp_tx_send_mesh(void *vap_dev, qdf_nbuf_t nbuf)
  1662. {
  1663. return dp_tx_send(vap_dev, nbuf);
  1664. }
  1665. #endif
  1666. /**
  1667. * dp_tx_send() - Transmit a frame on a given VAP
  1668. * @vap_dev: DP vdev handle
  1669. * @nbuf: skb
  1670. *
  1671. * Entry point for Core Tx layer (DP_TX) invoked from
  1672. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  1673. * cases
  1674. *
  1675. * Return: NULL on success,
  1676. * nbuf when it fails to send
  1677. */
  1678. qdf_nbuf_t dp_tx_send(void *vap_dev, qdf_nbuf_t nbuf)
  1679. {
  1680. struct ether_header *eh = NULL;
  1681. struct dp_tx_msdu_info_s msdu_info;
  1682. struct dp_tx_seg_info_s seg_info;
  1683. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1684. uint16_t peer_id = HTT_INVALID_PEER;
  1685. qdf_nbuf_t nbuf_mesh = NULL;
  1686. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1687. qdf_mem_set(&seg_info, sizeof(seg_info), 0x0);
  1688. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1689. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1690. "%s , skb %pM",
  1691. __func__, nbuf->data);
  1692. /*
  1693. * Set Default Host TID value to invalid TID
  1694. * (TID override disabled)
  1695. */
  1696. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  1697. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1698. if (qdf_unlikely(vdev->mesh_vdev)) {
  1699. nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  1700. &msdu_info);
  1701. if (nbuf_mesh == NULL) {
  1702. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1703. "Extracting mesh metadata failed");
  1704. return nbuf;
  1705. }
  1706. nbuf = nbuf_mesh;
  1707. }
  1708. /*
  1709. * Get HW Queue to use for this frame.
  1710. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1711. * dedicated for data and 1 for command.
  1712. * "queue_id" maps to one hardware ring.
  1713. * With each ring, we also associate a unique Tx descriptor pool
  1714. * to minimize lock contention for these resources.
  1715. */
  1716. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1717. /*
  1718. * TCL H/W supports 2 DSCP-TID mapping tables.
  1719. * Table 1 - Default DSCP-TID mapping table
  1720. * Table 2 - 1 DSCP-TID override table
  1721. *
  1722. * If we need a different DSCP-TID mapping for this vap,
  1723. * call tid_classify to extract DSCP/ToS from frame and
  1724. * map to a TID and store in msdu_info. This is later used
  1725. * to fill in TCL Input descriptor (per-packet TID override).
  1726. */
  1727. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  1728. /*
  1729. * Classify the frame and call corresponding
  1730. * "prepare" function which extracts the segment (TSO)
  1731. * and fragmentation information (for TSO , SG, ME, or Raw)
  1732. * into MSDU_INFO structure which is later used to fill
  1733. * SW and HW descriptors.
  1734. */
  1735. if (qdf_nbuf_is_tso(nbuf)) {
  1736. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1737. "%s TSO frame %pK", __func__, vdev);
  1738. DP_STATS_INC_PKT(vdev, tx_i.tso.tso_pkt, 1,
  1739. qdf_nbuf_len(nbuf));
  1740. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  1741. DP_STATS_INC_PKT(vdev, tx_i.tso.dropped_host, 1,
  1742. qdf_nbuf_len(nbuf));
  1743. return nbuf;
  1744. }
  1745. goto send_multiple;
  1746. }
  1747. /* SG */
  1748. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1749. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  1750. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1751. "%s non-TSO SG frame %pK", __func__, vdev);
  1752. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  1753. qdf_nbuf_len(nbuf));
  1754. goto send_multiple;
  1755. }
  1756. #ifdef ATH_SUPPORT_IQUE
  1757. /* Mcast to Ucast Conversion*/
  1758. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1759. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1760. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  1761. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1762. "%s Mcast frm for ME %pK", __func__, vdev);
  1763. DP_STATS_INC_PKT(vdev,
  1764. tx_i.mcast_en.mcast_pkt, 1,
  1765. qdf_nbuf_len(nbuf));
  1766. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  1767. QDF_STATUS_SUCCESS) {
  1768. return NULL;
  1769. }
  1770. }
  1771. }
  1772. #endif
  1773. /* RAW */
  1774. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1775. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  1776. if (nbuf == NULL)
  1777. return NULL;
  1778. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1779. "%s Raw frame %pK", __func__, vdev);
  1780. goto send_multiple;
  1781. }
  1782. /* Single linear frame */
  1783. /*
  1784. * If nbuf is a simple linear frame, use send_single function to
  1785. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1786. * SRNG. There is no need to setup a MSDU extension descriptor.
  1787. */
  1788. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  1789. return nbuf;
  1790. send_multiple:
  1791. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  1792. return nbuf;
  1793. }
  1794. /**
  1795. * dp_tx_reinject_handler() - Tx Reinject Handler
  1796. * @tx_desc: software descriptor head pointer
  1797. * @status : Tx completion status from HTT descriptor
  1798. *
  1799. * This function reinjects frames back to Target.
  1800. * Todo - Host queue needs to be added
  1801. *
  1802. * Return: none
  1803. */
  1804. static
  1805. void dp_tx_reinject_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1806. {
  1807. struct dp_vdev *vdev;
  1808. struct dp_peer *peer = NULL;
  1809. uint32_t peer_id = HTT_INVALID_PEER;
  1810. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1811. qdf_nbuf_t nbuf_copy = NULL;
  1812. struct dp_tx_msdu_info_s msdu_info;
  1813. struct dp_peer *sa_peer = NULL;
  1814. struct dp_ast_entry *ast_entry = NULL;
  1815. struct dp_soc *soc = NULL;
  1816. struct ether_header *eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1817. #ifdef WDS_VENDOR_EXTENSION
  1818. int is_mcast = 0, is_ucast = 0;
  1819. int num_peers_3addr = 0;
  1820. struct ether_header *eth_hdr = (struct ether_header *)(qdf_nbuf_data(nbuf));
  1821. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  1822. #endif
  1823. vdev = tx_desc->vdev;
  1824. soc = vdev->pdev->soc;
  1825. qdf_assert(vdev);
  1826. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1827. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1828. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1829. "%s Tx reinject path", __func__);
  1830. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  1831. qdf_nbuf_len(tx_desc->nbuf));
  1832. qdf_spin_lock_bh(&(soc->ast_lock));
  1833. ast_entry = dp_peer_ast_hash_find(soc, (uint8_t *)(eh->ether_shost));
  1834. if (ast_entry)
  1835. sa_peer = ast_entry->peer;
  1836. qdf_spin_unlock_bh(&(soc->ast_lock));
  1837. #ifdef WDS_VENDOR_EXTENSION
  1838. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1839. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  1840. } else {
  1841. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  1842. }
  1843. is_ucast = !is_mcast;
  1844. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1845. if (peer->bss_peer)
  1846. continue;
  1847. /* Detect wds peers that use 3-addr framing for mcast.
  1848. * if there are any, the bss_peer is used to send the
  1849. * the mcast frame using 3-addr format. all wds enabled
  1850. * peers that use 4-addr framing for mcast frames will
  1851. * be duplicated and sent as 4-addr frames below.
  1852. */
  1853. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  1854. num_peers_3addr = 1;
  1855. break;
  1856. }
  1857. }
  1858. #endif
  1859. if (qdf_unlikely(vdev->mesh_vdev)) {
  1860. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  1861. } else {
  1862. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1863. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1864. #ifdef WDS_VENDOR_EXTENSION
  1865. /*
  1866. * . if 3-addr STA, then send on BSS Peer
  1867. * . if Peer WDS enabled and accept 4-addr mcast,
  1868. * send mcast on that peer only
  1869. * . if Peer WDS enabled and accept 4-addr ucast,
  1870. * send ucast on that peer only
  1871. */
  1872. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  1873. (peer->wds_enabled &&
  1874. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  1875. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  1876. #else
  1877. ((peer->bss_peer &&
  1878. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))) ||
  1879. peer->nawds_enabled)) {
  1880. #endif
  1881. peer_id = DP_INVALID_PEER;
  1882. if (peer->nawds_enabled) {
  1883. peer_id = peer->peer_ids[0];
  1884. if (sa_peer == peer) {
  1885. QDF_TRACE(
  1886. QDF_MODULE_ID_DP,
  1887. QDF_TRACE_LEVEL_DEBUG,
  1888. " %s: multicast packet",
  1889. __func__);
  1890. DP_STATS_INC(peer,
  1891. tx.nawds_mcast_drop, 1);
  1892. continue;
  1893. }
  1894. }
  1895. nbuf_copy = qdf_nbuf_copy(nbuf);
  1896. if (!nbuf_copy) {
  1897. QDF_TRACE(QDF_MODULE_ID_DP,
  1898. QDF_TRACE_LEVEL_DEBUG,
  1899. FL("nbuf copy failed"));
  1900. break;
  1901. }
  1902. nbuf_copy = dp_tx_send_msdu_single(vdev,
  1903. nbuf_copy,
  1904. &msdu_info,
  1905. peer_id,
  1906. NULL);
  1907. if (nbuf_copy) {
  1908. QDF_TRACE(QDF_MODULE_ID_DP,
  1909. QDF_TRACE_LEVEL_DEBUG,
  1910. FL("pkt send failed"));
  1911. qdf_nbuf_free(nbuf_copy);
  1912. } else {
  1913. if (peer_id != DP_INVALID_PEER)
  1914. DP_STATS_INC_PKT(peer,
  1915. tx.nawds_mcast,
  1916. 1, qdf_nbuf_len(nbuf));
  1917. }
  1918. }
  1919. }
  1920. }
  1921. if (vdev->nawds_enabled) {
  1922. peer_id = DP_INVALID_PEER;
  1923. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  1924. 1, qdf_nbuf_len(nbuf));
  1925. nbuf = dp_tx_send_msdu_single(vdev,
  1926. nbuf,
  1927. &msdu_info,
  1928. peer_id, NULL);
  1929. if (nbuf) {
  1930. QDF_TRACE(QDF_MODULE_ID_DP,
  1931. QDF_TRACE_LEVEL_DEBUG,
  1932. FL("pkt send failed"));
  1933. qdf_nbuf_free(nbuf);
  1934. }
  1935. } else
  1936. qdf_nbuf_free(nbuf);
  1937. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  1938. }
  1939. /**
  1940. * dp_tx_inspect_handler() - Tx Inspect Handler
  1941. * @tx_desc: software descriptor head pointer
  1942. * @status : Tx completion status from HTT descriptor
  1943. *
  1944. * Handles Tx frames sent back to Host for inspection
  1945. * (ProxyARP)
  1946. *
  1947. * Return: none
  1948. */
  1949. static void dp_tx_inspect_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1950. {
  1951. struct dp_soc *soc;
  1952. struct dp_pdev *pdev = tx_desc->pdev;
  1953. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1954. "%s Tx inspect path",
  1955. __func__);
  1956. qdf_assert(pdev);
  1957. soc = pdev->soc;
  1958. DP_STATS_INC_PKT(tx_desc->vdev, tx_i.inspect_pkts, 1,
  1959. qdf_nbuf_len(tx_desc->nbuf));
  1960. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  1961. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  1962. }
  1963. #ifdef FEATURE_PERPKT_INFO
  1964. /**
  1965. * dp_get_completion_indication_for_stack() - send completion to stack
  1966. * @soc : dp_soc handle
  1967. * @pdev: dp_pdev handle
  1968. * @peer_id: peer_id of the peer for which completion came
  1969. * @ppdu_id: ppdu_id
  1970. * @first_msdu: first msdu
  1971. * @last_msdu: last msdu
  1972. * @netbuf: Buffer pointer for free
  1973. *
  1974. * This function is used for indication whether buffer needs to be
  1975. * send to stack for free or not
  1976. */
  1977. QDF_STATUS
  1978. dp_get_completion_indication_for_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  1979. uint16_t peer_id, uint32_t ppdu_id, uint8_t first_msdu,
  1980. uint8_t last_msdu, qdf_nbuf_t netbuf)
  1981. {
  1982. struct tx_capture_hdr *ppdu_hdr;
  1983. struct dp_peer *peer = NULL;
  1984. struct ether_header *eh;
  1985. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode))
  1986. return QDF_STATUS_E_NOSUPPORT;
  1987. peer = (peer_id == HTT_INVALID_PEER) ? NULL :
  1988. dp_peer_find_by_id(soc, peer_id);
  1989. if (!peer) {
  1990. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1991. FL("Peer Invalid"));
  1992. return QDF_STATUS_E_INVAL;
  1993. }
  1994. if (pdev->mcopy_mode) {
  1995. if ((pdev->m_copy_id.tx_ppdu_id == ppdu_id) &&
  1996. (pdev->m_copy_id.tx_peer_id == peer_id)) {
  1997. return QDF_STATUS_E_INVAL;
  1998. }
  1999. pdev->m_copy_id.tx_ppdu_id = ppdu_id;
  2000. pdev->m_copy_id.tx_peer_id = peer_id;
  2001. }
  2002. eh = (struct ether_header *)qdf_nbuf_data(netbuf);
  2003. if (!qdf_nbuf_push_head(netbuf, sizeof(struct tx_capture_hdr))) {
  2004. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2005. FL("No headroom"));
  2006. return QDF_STATUS_E_NOMEM;
  2007. }
  2008. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  2009. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  2010. IEEE80211_ADDR_LEN);
  2011. if (peer->bss_peer) {
  2012. qdf_mem_copy(ppdu_hdr->ra, eh->ether_dhost, IEEE80211_ADDR_LEN);
  2013. } else {
  2014. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  2015. IEEE80211_ADDR_LEN);
  2016. }
  2017. ppdu_hdr->ppdu_id = ppdu_id;
  2018. ppdu_hdr->peer_id = peer_id;
  2019. ppdu_hdr->first_msdu = first_msdu;
  2020. ppdu_hdr->last_msdu = last_msdu;
  2021. return QDF_STATUS_SUCCESS;
  2022. }
  2023. /**
  2024. * dp_send_completion_to_stack() - send completion to stack
  2025. * @soc : dp_soc handle
  2026. * @pdev: dp_pdev handle
  2027. * @peer_id: peer_id of the peer for which completion came
  2028. * @ppdu_id: ppdu_id
  2029. * @netbuf: Buffer pointer for free
  2030. *
  2031. * This function is used to send completion to stack
  2032. * to free buffer
  2033. */
  2034. void dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2035. uint16_t peer_id, uint32_t ppdu_id,
  2036. qdf_nbuf_t netbuf)
  2037. {
  2038. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  2039. netbuf, peer_id,
  2040. WDI_NO_VAL, pdev->pdev_id);
  2041. }
  2042. #else
  2043. static QDF_STATUS
  2044. dp_get_completion_indication_for_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2045. uint16_t peer_id, uint32_t ppdu_id, uint8_t first_msdu,
  2046. uint8_t last_msdu, qdf_nbuf_t netbuf)
  2047. {
  2048. return QDF_STATUS_E_NOSUPPORT;
  2049. }
  2050. static void
  2051. dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2052. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  2053. {
  2054. }
  2055. #endif
  2056. /**
  2057. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2058. * @soc: Soc handle
  2059. * @desc: software Tx descriptor to be processed
  2060. *
  2061. * Return: none
  2062. */
  2063. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  2064. struct dp_tx_desc_s *desc)
  2065. {
  2066. struct dp_vdev *vdev = desc->vdev;
  2067. qdf_nbuf_t nbuf = desc->nbuf;
  2068. /* If it is TDLS mgmt, don't unmap or free the frame */
  2069. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  2070. return dp_non_std_tx_comp_free_buff(desc, vdev);
  2071. /* 0 : MSDU buffer, 1 : MLE */
  2072. if (desc->msdu_ext_desc) {
  2073. /* TSO free */
  2074. if (hal_tx_ext_desc_get_tso_enable(
  2075. desc->msdu_ext_desc->vaddr)) {
  2076. /* unmap eash TSO seg before free the nbuf */
  2077. dp_tx_tso_unmap_segment(soc, desc);
  2078. qdf_nbuf_free(nbuf);
  2079. return;
  2080. }
  2081. }
  2082. qdf_nbuf_unmap(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  2083. if (qdf_likely(!vdev->mesh_vdev))
  2084. qdf_nbuf_free(nbuf);
  2085. else {
  2086. if (desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  2087. qdf_nbuf_free(nbuf);
  2088. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  2089. } else
  2090. vdev->osif_tx_free_ext((nbuf));
  2091. }
  2092. }
  2093. /**
  2094. * dp_tx_mec_handler() - Tx MEC Notify Handler
  2095. * @vdev: pointer to dp dev handler
  2096. * @status : Tx completion status from HTT descriptor
  2097. *
  2098. * Handles MEC notify event sent from fw to Host
  2099. *
  2100. * Return: none
  2101. */
  2102. #ifdef FEATURE_WDS
  2103. void dp_tx_mec_handler(struct dp_vdev *vdev, uint8_t *status)
  2104. {
  2105. struct dp_soc *soc;
  2106. uint32_t flags = IEEE80211_NODE_F_WDS_HM;
  2107. struct dp_peer *peer;
  2108. uint8_t mac_addr[DP_MAC_ADDR_LEN], i;
  2109. if (!vdev->wds_enabled)
  2110. return;
  2111. /* MEC required only in STA mode */
  2112. if (vdev->opmode != wlan_op_mode_sta)
  2113. return;
  2114. soc = vdev->pdev->soc;
  2115. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2116. peer = TAILQ_FIRST(&vdev->peer_list);
  2117. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2118. if (!peer) {
  2119. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2120. FL("peer is NULL"));
  2121. return;
  2122. }
  2123. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2124. "%s Tx MEC Handler",
  2125. __func__);
  2126. for (i = 0; i < DP_MAC_ADDR_LEN; i++)
  2127. mac_addr[(DP_MAC_ADDR_LEN - 1) - i] =
  2128. status[(DP_MAC_ADDR_LEN - 2) + i];
  2129. if (qdf_mem_cmp(mac_addr, vdev->mac_addr.raw, DP_MAC_ADDR_LEN))
  2130. dp_peer_add_ast(soc,
  2131. peer,
  2132. mac_addr,
  2133. CDP_TXRX_AST_TYPE_MEC,
  2134. flags);
  2135. }
  2136. #endif
  2137. /**
  2138. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  2139. * @tx_desc: software descriptor head pointer
  2140. * @status : Tx completion status from HTT descriptor
  2141. *
  2142. * This function will process HTT Tx indication messages from Target
  2143. *
  2144. * Return: none
  2145. */
  2146. static
  2147. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2148. {
  2149. uint8_t tx_status;
  2150. struct dp_pdev *pdev;
  2151. struct dp_vdev *vdev;
  2152. struct dp_soc *soc;
  2153. uint32_t *htt_status_word = (uint32_t *) status;
  2154. qdf_assert(tx_desc->pdev);
  2155. pdev = tx_desc->pdev;
  2156. vdev = tx_desc->vdev;
  2157. soc = pdev->soc;
  2158. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_status_word[0]);
  2159. switch (tx_status) {
  2160. case HTT_TX_FW2WBM_TX_STATUS_OK:
  2161. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  2162. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  2163. {
  2164. dp_tx_comp_free_buf(soc, tx_desc);
  2165. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2166. break;
  2167. }
  2168. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  2169. {
  2170. dp_tx_reinject_handler(tx_desc, status);
  2171. break;
  2172. }
  2173. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  2174. {
  2175. dp_tx_inspect_handler(tx_desc, status);
  2176. break;
  2177. }
  2178. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  2179. {
  2180. dp_tx_mec_handler(vdev, status);
  2181. break;
  2182. }
  2183. default:
  2184. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2185. "%s Invalid HTT tx_status %d",
  2186. __func__, tx_status);
  2187. break;
  2188. }
  2189. }
  2190. #ifdef MESH_MODE_SUPPORT
  2191. /**
  2192. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2193. * in mesh meta header
  2194. * @tx_desc: software descriptor head pointer
  2195. * @ts: pointer to tx completion stats
  2196. * Return: none
  2197. */
  2198. static
  2199. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2200. struct hal_tx_completion_status *ts)
  2201. {
  2202. struct meta_hdr_s *mhdr;
  2203. qdf_nbuf_t netbuf = tx_desc->nbuf;
  2204. if (!tx_desc->msdu_ext_desc) {
  2205. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  2206. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2207. "netbuf %pK offset %d",
  2208. netbuf, tx_desc->pkt_offset);
  2209. return;
  2210. }
  2211. }
  2212. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2213. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2214. "netbuf %pK offset %d", netbuf,
  2215. sizeof(struct meta_hdr_s));
  2216. return;
  2217. }
  2218. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  2219. mhdr->rssi = ts->ack_frame_rssi;
  2220. mhdr->channel = tx_desc->pdev->operating_channel;
  2221. }
  2222. #else
  2223. static
  2224. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2225. struct hal_tx_completion_status *ts)
  2226. {
  2227. }
  2228. #endif
  2229. /**
  2230. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  2231. * @peer: Handle to DP peer
  2232. * @ts: pointer to HAL Tx completion stats
  2233. * @length: MSDU length
  2234. *
  2235. * Return: None
  2236. */
  2237. static void dp_tx_update_peer_stats(struct dp_peer *peer,
  2238. struct hal_tx_completion_status *ts, uint32_t length)
  2239. {
  2240. struct dp_pdev *pdev = peer->vdev->pdev;
  2241. struct dp_soc *soc = pdev->soc;
  2242. uint8_t mcs, pkt_type;
  2243. mcs = ts->mcs;
  2244. pkt_type = ts->pkt_type;
  2245. if (!ts->release_src == HAL_TX_COMP_RELEASE_SOURCE_TQM)
  2246. return;
  2247. if (peer->bss_peer) {
  2248. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  2249. } else {
  2250. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  2251. }
  2252. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  2253. DP_STATS_INCC_PKT(peer, tx.tx_success, 1, length,
  2254. (ts->status == HAL_TX_TQM_RR_FRAME_ACKED));
  2255. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  2256. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  2257. DP_STATS_INCC(peer, tx.dropped.fw_rem, 1,
  2258. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2259. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  2260. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  2261. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  2262. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  2263. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  2264. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  2265. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  2266. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  2267. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  2268. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  2269. if (!ts->status == HAL_TX_TQM_RR_FRAME_ACKED)
  2270. return;
  2271. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  2272. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  2273. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  2274. if (!(soc->process_tx_status))
  2275. return;
  2276. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2277. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  2278. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2279. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  2280. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2281. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2282. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2283. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2284. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2285. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2286. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2287. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2288. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2289. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2290. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2291. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2292. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2293. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2294. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2295. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2296. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  2297. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  2298. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  2299. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  2300. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  2301. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  2302. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  2303. if (soc->cdp_soc.ol_ops->update_dp_stats) {
  2304. soc->cdp_soc.ol_ops->update_dp_stats(pdev->ctrl_pdev,
  2305. &peer->stats, ts->peer_id,
  2306. UPDATE_PEER_STATS);
  2307. }
  2308. }
  2309. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2310. /**
  2311. * dp_tx_flow_pool_lock() - take flow pool lock
  2312. * @soc: core txrx main context
  2313. * @tx_desc: tx desc
  2314. *
  2315. * Return: None
  2316. */
  2317. static inline
  2318. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  2319. struct dp_tx_desc_s *tx_desc)
  2320. {
  2321. struct dp_tx_desc_pool_s *pool;
  2322. uint8_t desc_pool_id;
  2323. desc_pool_id = tx_desc->pool_id;
  2324. pool = &soc->tx_desc[desc_pool_id];
  2325. qdf_spin_lock_bh(&pool->flow_pool_lock);
  2326. }
  2327. /**
  2328. * dp_tx_flow_pool_unlock() - release flow pool lock
  2329. * @soc: core txrx main context
  2330. * @tx_desc: tx desc
  2331. *
  2332. * Return: None
  2333. */
  2334. static inline
  2335. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  2336. struct dp_tx_desc_s *tx_desc)
  2337. {
  2338. struct dp_tx_desc_pool_s *pool;
  2339. uint8_t desc_pool_id;
  2340. desc_pool_id = tx_desc->pool_id;
  2341. pool = &soc->tx_desc[desc_pool_id];
  2342. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  2343. }
  2344. #else
  2345. static inline
  2346. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2347. {
  2348. }
  2349. static inline
  2350. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2351. {
  2352. }
  2353. #endif
  2354. /**
  2355. * dp_tx_notify_completion() - Notify tx completion for this desc
  2356. * @soc: core txrx main context
  2357. * @tx_desc: tx desc
  2358. * @netbuf: buffer
  2359. *
  2360. * Return: none
  2361. */
  2362. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  2363. struct dp_tx_desc_s *tx_desc,
  2364. qdf_nbuf_t netbuf)
  2365. {
  2366. void *osif_dev;
  2367. ol_txrx_completion_fp tx_compl_cbk = NULL;
  2368. qdf_assert(tx_desc);
  2369. dp_tx_flow_pool_lock(soc, tx_desc);
  2370. if (!tx_desc->vdev ||
  2371. !tx_desc->vdev->osif_vdev) {
  2372. dp_tx_flow_pool_unlock(soc, tx_desc);
  2373. return;
  2374. }
  2375. osif_dev = tx_desc->vdev->osif_vdev;
  2376. tx_compl_cbk = tx_desc->vdev->tx_comp;
  2377. dp_tx_flow_pool_unlock(soc, tx_desc);
  2378. if (tx_compl_cbk)
  2379. tx_compl_cbk(netbuf, osif_dev);
  2380. }
  2381. /**
  2382. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  2383. * @tx_desc: software descriptor head pointer
  2384. * @length: packet length
  2385. *
  2386. * Return: none
  2387. */
  2388. static inline void dp_tx_comp_process_tx_status(struct dp_tx_desc_s *tx_desc,
  2389. uint32_t length)
  2390. {
  2391. struct hal_tx_completion_status ts;
  2392. struct dp_soc *soc = NULL;
  2393. struct dp_vdev *vdev = tx_desc->vdev;
  2394. struct dp_peer *peer = NULL;
  2395. struct ether_header *eh =
  2396. (struct ether_header *)qdf_nbuf_data(tx_desc->nbuf);
  2397. hal_tx_comp_get_status(&tx_desc->comp, &ts);
  2398. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2399. "-------------------- \n"
  2400. "Tx Completion Stats: \n"
  2401. "-------------------- \n"
  2402. "ack_frame_rssi = %d \n"
  2403. "first_msdu = %d \n"
  2404. "last_msdu = %d \n"
  2405. "msdu_part_of_amsdu = %d \n"
  2406. "rate_stats valid = %d \n"
  2407. "bw = %d \n"
  2408. "pkt_type = %d \n"
  2409. "stbc = %d \n"
  2410. "ldpc = %d \n"
  2411. "sgi = %d \n"
  2412. "mcs = %d \n"
  2413. "ofdma = %d \n"
  2414. "tones_in_ru = %d \n"
  2415. "tsf = %d \n"
  2416. "ppdu_id = %d \n"
  2417. "transmit_cnt = %d \n"
  2418. "tid = %d \n"
  2419. "peer_id = %d ",
  2420. ts.ack_frame_rssi, ts.first_msdu, ts.last_msdu,
  2421. ts.msdu_part_of_amsdu, ts.valid, ts.bw,
  2422. ts.pkt_type, ts.stbc, ts.ldpc, ts.sgi,
  2423. ts.mcs, ts.ofdma, ts.tones_in_ru, ts.tsf,
  2424. ts.ppdu_id, ts.transmit_cnt, ts.tid,
  2425. ts.peer_id);
  2426. if (!vdev) {
  2427. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2428. "invalid vdev");
  2429. goto out;
  2430. }
  2431. soc = vdev->pdev->soc;
  2432. /* Update SoC level stats */
  2433. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  2434. (ts.status == HAL_TX_TQM_RR_REM_CMD_REM));
  2435. /* Update per-packet stats */
  2436. if (qdf_unlikely(vdev->mesh_vdev) &&
  2437. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  2438. dp_tx_comp_fill_tx_completion_stats(tx_desc, &ts);
  2439. /* Update peer level stats */
  2440. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2441. if (!peer) {
  2442. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2443. "invalid peer");
  2444. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  2445. goto out;
  2446. }
  2447. if (qdf_likely(peer->vdev->tx_encap_type ==
  2448. htt_cmn_pkt_type_ethernet)) {
  2449. if (peer->bss_peer && IEEE80211_IS_BROADCAST(eh->ether_dhost))
  2450. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  2451. }
  2452. dp_tx_update_peer_stats(peer, &ts, length);
  2453. out:
  2454. return;
  2455. }
  2456. /**
  2457. * dp_tx_comp_process_desc() - Tx complete software descriptor handler
  2458. * @soc: core txrx main context
  2459. * @comp_head: software descriptor head pointer
  2460. *
  2461. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  2462. * and release the software descriptors after processing is complete
  2463. *
  2464. * Return: none
  2465. */
  2466. static void dp_tx_comp_process_desc(struct dp_soc *soc,
  2467. struct dp_tx_desc_s *comp_head)
  2468. {
  2469. struct dp_tx_desc_s *desc;
  2470. struct dp_tx_desc_s *next;
  2471. struct hal_tx_completion_status ts = {0};
  2472. uint32_t length;
  2473. struct dp_peer *peer;
  2474. DP_HIST_INIT();
  2475. desc = comp_head;
  2476. while (desc) {
  2477. hal_tx_comp_get_status(&desc->comp, &ts);
  2478. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2479. length = qdf_nbuf_len(desc->nbuf);
  2480. /* check tx completion notification */
  2481. if (QDF_NBUF_CB_TX_EXTRA_FRAG_FLAGS_NOTIFY_COMP(desc->nbuf))
  2482. dp_tx_notify_completion(soc, desc, desc->nbuf);
  2483. dp_tx_comp_process_tx_status(desc, length);
  2484. DPTRACE(qdf_dp_trace_ptr
  2485. (desc->nbuf,
  2486. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  2487. QDF_TRACE_DEFAULT_PDEV_ID,
  2488. qdf_nbuf_data_addr(desc->nbuf),
  2489. sizeof(qdf_nbuf_data(desc->nbuf)),
  2490. desc->id, ts.status)
  2491. );
  2492. /*currently m_copy/tx_capture is not supported for scatter gather packets*/
  2493. if (!(desc->msdu_ext_desc) && (dp_get_completion_indication_for_stack(soc,
  2494. desc->pdev, ts.peer_id, ts.ppdu_id,
  2495. ts.first_msdu, ts.last_msdu,
  2496. desc->nbuf) == QDF_STATUS_SUCCESS)) {
  2497. qdf_nbuf_unmap(soc->osdev, desc->nbuf,
  2498. QDF_DMA_TO_DEVICE);
  2499. dp_send_completion_to_stack(soc, desc->pdev, ts.peer_id,
  2500. ts.ppdu_id, desc->nbuf);
  2501. } else {
  2502. dp_tx_comp_free_buf(soc, desc);
  2503. }
  2504. DP_HIST_PACKET_COUNT_INC(desc->pdev->pdev_id);
  2505. next = desc->next;
  2506. dp_tx_desc_release(desc, desc->pool_id);
  2507. desc = next;
  2508. }
  2509. DP_TX_HIST_STATS_PER_PDEV();
  2510. }
  2511. /**
  2512. * dp_tx_comp_handler() - Tx completion handler
  2513. * @soc: core txrx main context
  2514. * @ring_id: completion ring id
  2515. * @quota: No. of packets/descriptors that can be serviced in one loop
  2516. *
  2517. * This function will collect hardware release ring element contents and
  2518. * handle descriptor contents. Based on contents, free packet or handle error
  2519. * conditions
  2520. *
  2521. * Return: none
  2522. */
  2523. uint32_t dp_tx_comp_handler(struct dp_soc *soc, void *hal_srng, uint32_t quota)
  2524. {
  2525. void *tx_comp_hal_desc;
  2526. uint8_t buffer_src;
  2527. uint8_t pool_id;
  2528. uint32_t tx_desc_id;
  2529. struct dp_tx_desc_s *tx_desc = NULL;
  2530. struct dp_tx_desc_s *head_desc = NULL;
  2531. struct dp_tx_desc_s *tail_desc = NULL;
  2532. uint32_t num_processed;
  2533. uint32_t count;
  2534. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  2535. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2536. "%s %d : HAL RING Access Failed -- %pK",
  2537. __func__, __LINE__, hal_srng);
  2538. return 0;
  2539. }
  2540. num_processed = 0;
  2541. count = 0;
  2542. /* Find head descriptor from completion ring */
  2543. while (qdf_likely(tx_comp_hal_desc =
  2544. hal_srng_dst_get_next(soc->hal_soc, hal_srng))) {
  2545. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  2546. /* If this buffer was not released by TQM or FW, then it is not
  2547. * Tx completion indication, assert */
  2548. if ((buffer_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  2549. (buffer_src != HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2550. QDF_TRACE(QDF_MODULE_ID_DP,
  2551. QDF_TRACE_LEVEL_FATAL,
  2552. "Tx comp release_src != TQM | FW");
  2553. qdf_assert_always(0);
  2554. }
  2555. /* Get descriptor id */
  2556. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  2557. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  2558. DP_TX_DESC_ID_POOL_OS;
  2559. if (!dp_tx_is_desc_id_valid(soc, tx_desc_id))
  2560. continue;
  2561. /* Find Tx descriptor */
  2562. tx_desc = dp_tx_desc_find(soc, pool_id,
  2563. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  2564. DP_TX_DESC_ID_PAGE_OS,
  2565. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  2566. DP_TX_DESC_ID_OFFSET_OS);
  2567. /*
  2568. * If the release source is FW, process the HTT status
  2569. */
  2570. if (qdf_unlikely(buffer_src ==
  2571. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2572. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  2573. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  2574. htt_tx_status);
  2575. dp_tx_process_htt_completion(tx_desc,
  2576. htt_tx_status);
  2577. } else {
  2578. /* Pool id is not matching. Error */
  2579. if (tx_desc->pool_id != pool_id) {
  2580. QDF_TRACE(QDF_MODULE_ID_DP,
  2581. QDF_TRACE_LEVEL_FATAL,
  2582. "Tx Comp pool id %d not matched %d",
  2583. pool_id, tx_desc->pool_id);
  2584. qdf_assert_always(0);
  2585. }
  2586. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  2587. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  2588. QDF_TRACE(QDF_MODULE_ID_DP,
  2589. QDF_TRACE_LEVEL_FATAL,
  2590. "Txdesc invalid, flgs = %x,id = %d",
  2591. tx_desc->flags, tx_desc_id);
  2592. qdf_assert_always(0);
  2593. }
  2594. /* First ring descriptor on the cycle */
  2595. if (!head_desc) {
  2596. head_desc = tx_desc;
  2597. tail_desc = tx_desc;
  2598. }
  2599. tail_desc->next = tx_desc;
  2600. tx_desc->next = NULL;
  2601. tail_desc = tx_desc;
  2602. /* Collect hw completion contents */
  2603. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  2604. &tx_desc->comp, 1);
  2605. }
  2606. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  2607. /*
  2608. * Processed packet count is more than given quota
  2609. * stop to processing
  2610. */
  2611. if ((num_processed >= quota))
  2612. break;
  2613. count++;
  2614. }
  2615. hal_srng_access_end(soc->hal_soc, hal_srng);
  2616. /* Process the reaped descriptors */
  2617. if (head_desc)
  2618. dp_tx_comp_process_desc(soc, head_desc);
  2619. return num_processed;
  2620. }
  2621. #ifdef CONVERGED_TDLS_ENABLE
  2622. /**
  2623. * dp_tx_non_std() - Allow the control-path SW to send data frames
  2624. *
  2625. * @data_vdev - which vdev should transmit the tx data frames
  2626. * @tx_spec - what non-standard handling to apply to the tx data frames
  2627. * @msdu_list - NULL-terminated list of tx MSDUs
  2628. *
  2629. * Return: NULL on success,
  2630. * nbuf when it fails to send
  2631. */
  2632. qdf_nbuf_t dp_tx_non_std(struct cdp_vdev *vdev_handle,
  2633. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  2634. {
  2635. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  2636. if (tx_spec & OL_TX_SPEC_NO_FREE)
  2637. vdev->is_tdls_frame = true;
  2638. return dp_tx_send(vdev_handle, msdu_list);
  2639. }
  2640. #endif
  2641. /**
  2642. * dp_tx_vdev_attach() - attach vdev to dp tx
  2643. * @vdev: virtual device instance
  2644. *
  2645. * Return: QDF_STATUS_SUCCESS: success
  2646. * QDF_STATUS_E_RESOURCES: Error return
  2647. */
  2648. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  2649. {
  2650. /*
  2651. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  2652. */
  2653. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  2654. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  2655. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  2656. vdev->vdev_id);
  2657. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata,
  2658. DP_SW2HW_MACID(vdev->pdev->pdev_id));
  2659. /*
  2660. * Set HTT Extension Valid bit to 0 by default
  2661. */
  2662. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  2663. dp_tx_vdev_update_search_flags(vdev);
  2664. return QDF_STATUS_SUCCESS;
  2665. }
  2666. /**
  2667. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  2668. * @vdev: virtual device instance
  2669. *
  2670. * Return: void
  2671. *
  2672. */
  2673. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  2674. {
  2675. /*
  2676. * Enable both AddrY (SA based search) and AddrX (Da based search)
  2677. * for TDLS link
  2678. *
  2679. * Enable AddrY (SA based search) only for non-WDS STA and
  2680. * ProxySTA VAP modes.
  2681. *
  2682. * In all other VAP modes, only DA based search should be
  2683. * enabled
  2684. */
  2685. if (vdev->opmode == wlan_op_mode_sta &&
  2686. vdev->tdls_link_connected)
  2687. vdev->hal_desc_addr_search_flags =
  2688. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  2689. else if ((vdev->opmode == wlan_op_mode_sta &&
  2690. (!vdev->wds_enabled || vdev->proxysta_vdev)))
  2691. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  2692. else
  2693. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  2694. }
  2695. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2696. static void dp_tx_desc_flush(struct dp_vdev *vdev)
  2697. {
  2698. }
  2699. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  2700. /* dp_tx_desc_flush() - release resources associated
  2701. * to tx_desc
  2702. * @vdev: virtual device instance
  2703. *
  2704. * This function will free all outstanding Tx buffers,
  2705. * including ME buffer for which either free during
  2706. * completion didn't happened or completion is not
  2707. * received.
  2708. */
  2709. static void dp_tx_desc_flush(struct dp_vdev *vdev)
  2710. {
  2711. uint8_t i, num_pool;
  2712. uint32_t j;
  2713. uint32_t num_desc;
  2714. struct dp_soc *soc = vdev->pdev->soc;
  2715. struct dp_tx_desc_s *tx_desc = NULL;
  2716. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  2717. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2718. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2719. for (i = 0; i < num_pool; i++) {
  2720. for (j = 0; j < num_desc; j++) {
  2721. tx_desc_pool = &((soc)->tx_desc[(i)]);
  2722. if (tx_desc_pool &&
  2723. tx_desc_pool->desc_pages.cacheable_pages) {
  2724. tx_desc = dp_tx_desc_find(soc, i,
  2725. (j & DP_TX_DESC_ID_PAGE_MASK) >>
  2726. DP_TX_DESC_ID_PAGE_OS,
  2727. (j & DP_TX_DESC_ID_OFFSET_MASK) >>
  2728. DP_TX_DESC_ID_OFFSET_OS);
  2729. if (tx_desc && (tx_desc->vdev == vdev) &&
  2730. (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)) {
  2731. dp_tx_comp_free_buf(soc, tx_desc);
  2732. dp_tx_desc_release(tx_desc, i);
  2733. }
  2734. }
  2735. }
  2736. }
  2737. }
  2738. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  2739. /**
  2740. * dp_tx_vdev_detach() - detach vdev from dp tx
  2741. * @vdev: virtual device instance
  2742. *
  2743. * Return: QDF_STATUS_SUCCESS: success
  2744. * QDF_STATUS_E_RESOURCES: Error return
  2745. */
  2746. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  2747. {
  2748. dp_tx_desc_flush(vdev);
  2749. return QDF_STATUS_SUCCESS;
  2750. }
  2751. /**
  2752. * dp_tx_pdev_attach() - attach pdev to dp tx
  2753. * @pdev: physical device instance
  2754. *
  2755. * Return: QDF_STATUS_SUCCESS: success
  2756. * QDF_STATUS_E_RESOURCES: Error return
  2757. */
  2758. QDF_STATUS dp_tx_pdev_attach(struct dp_pdev *pdev)
  2759. {
  2760. struct dp_soc *soc = pdev->soc;
  2761. /* Initialize Flow control counters */
  2762. qdf_atomic_init(&pdev->num_tx_exception);
  2763. qdf_atomic_init(&pdev->num_tx_outstanding);
  2764. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2765. /* Initialize descriptors in TCL Ring */
  2766. hal_tx_init_data_ring(soc->hal_soc,
  2767. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  2768. }
  2769. return QDF_STATUS_SUCCESS;
  2770. }
  2771. /**
  2772. * dp_tx_pdev_detach() - detach pdev from dp tx
  2773. * @pdev: physical device instance
  2774. *
  2775. * Return: QDF_STATUS_SUCCESS: success
  2776. * QDF_STATUS_E_RESOURCES: Error return
  2777. */
  2778. QDF_STATUS dp_tx_pdev_detach(struct dp_pdev *pdev)
  2779. {
  2780. dp_tx_me_exit(pdev);
  2781. return QDF_STATUS_SUCCESS;
  2782. }
  2783. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2784. /* Pools will be allocated dynamically */
  2785. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  2786. int num_desc)
  2787. {
  2788. uint8_t i;
  2789. for (i = 0; i < num_pool; i++) {
  2790. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  2791. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  2792. }
  2793. return 0;
  2794. }
  2795. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  2796. {
  2797. uint8_t i;
  2798. for (i = 0; i < num_pool; i++)
  2799. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  2800. }
  2801. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  2802. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  2803. int num_desc)
  2804. {
  2805. uint8_t i;
  2806. /* Allocate software Tx descriptor pools */
  2807. for (i = 0; i < num_pool; i++) {
  2808. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  2809. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2810. "%s Tx Desc Pool alloc %d failed %pK",
  2811. __func__, i, soc);
  2812. return ENOMEM;
  2813. }
  2814. }
  2815. return 0;
  2816. }
  2817. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  2818. {
  2819. uint8_t i;
  2820. for (i = 0; i < num_pool; i++) {
  2821. qdf_assert_always(!soc->tx_desc[i].num_allocated);
  2822. if (dp_tx_desc_pool_free(soc, i)) {
  2823. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2824. "%s Tx Desc Pool Free failed", __func__);
  2825. }
  2826. }
  2827. }
  2828. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  2829. /**
  2830. * dp_tx_soc_detach() - detach soc from dp tx
  2831. * @soc: core txrx main context
  2832. *
  2833. * This function will detach dp tx into main device context
  2834. * will free dp tx resource and initialize resources
  2835. *
  2836. * Return: QDF_STATUS_SUCCESS: success
  2837. * QDF_STATUS_E_RESOURCES: Error return
  2838. */
  2839. QDF_STATUS dp_tx_soc_detach(struct dp_soc *soc)
  2840. {
  2841. uint8_t num_pool;
  2842. uint16_t num_desc;
  2843. uint16_t num_ext_desc;
  2844. uint8_t i;
  2845. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2846. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2847. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  2848. dp_tx_flow_control_deinit(soc);
  2849. dp_tx_delete_static_pools(soc, num_pool);
  2850. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2851. "%s Tx Desc Pool Free num_pool = %d, descs = %d",
  2852. __func__, num_pool, num_desc);
  2853. for (i = 0; i < num_pool; i++) {
  2854. if (dp_tx_ext_desc_pool_free(soc, i)) {
  2855. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2856. "%s Tx Ext Desc Pool Free failed",
  2857. __func__);
  2858. return QDF_STATUS_E_RESOURCES;
  2859. }
  2860. }
  2861. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2862. "%s MSDU Ext Desc Pool %d Free descs = %d",
  2863. __func__, num_pool, num_ext_desc);
  2864. for (i = 0; i < num_pool; i++) {
  2865. dp_tx_tso_desc_pool_free(soc, i);
  2866. }
  2867. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2868. "%s TSO Desc Pool %d Free descs = %d",
  2869. __func__, num_pool, num_desc);
  2870. for (i = 0; i < num_pool; i++)
  2871. dp_tx_tso_num_seg_pool_free(soc, i);
  2872. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2873. "%s TSO Num of seg Desc Pool %d Free descs = %d",
  2874. __func__, num_pool, num_desc);
  2875. return QDF_STATUS_SUCCESS;
  2876. }
  2877. /**
  2878. * dp_tx_soc_attach() - attach soc to dp tx
  2879. * @soc: core txrx main context
  2880. *
  2881. * This function will attach dp tx into main device context
  2882. * will allocate dp tx resource and initialize resources
  2883. *
  2884. * Return: QDF_STATUS_SUCCESS: success
  2885. * QDF_STATUS_E_RESOURCES: Error return
  2886. */
  2887. QDF_STATUS dp_tx_soc_attach(struct dp_soc *soc)
  2888. {
  2889. uint8_t i;
  2890. uint8_t num_pool;
  2891. uint32_t num_desc;
  2892. uint32_t num_ext_desc;
  2893. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2894. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2895. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  2896. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  2897. goto fail;
  2898. dp_tx_flow_control_init(soc);
  2899. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2900. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  2901. __func__, num_pool, num_desc);
  2902. /* Allocate extension tx descriptor pools */
  2903. for (i = 0; i < num_pool; i++) {
  2904. if (dp_tx_ext_desc_pool_alloc(soc, i, num_ext_desc)) {
  2905. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2906. "MSDU Ext Desc Pool alloc %d failed %pK",
  2907. i, soc);
  2908. goto fail;
  2909. }
  2910. }
  2911. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2912. "%s MSDU Ext Desc Alloc %d, descs = %d",
  2913. __func__, num_pool, num_ext_desc);
  2914. for (i = 0; i < num_pool; i++) {
  2915. if (dp_tx_tso_desc_pool_alloc(soc, i, num_desc)) {
  2916. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2917. "TSO Desc Pool alloc %d failed %pK",
  2918. i, soc);
  2919. goto fail;
  2920. }
  2921. }
  2922. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2923. "%s TSO Desc Alloc %d, descs = %d",
  2924. __func__, num_pool, num_desc);
  2925. for (i = 0; i < num_pool; i++) {
  2926. if (dp_tx_tso_num_seg_pool_alloc(soc, i, num_desc)) {
  2927. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2928. "TSO Num of seg Pool alloc %d failed %pK",
  2929. i, soc);
  2930. goto fail;
  2931. }
  2932. }
  2933. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2934. "%s TSO Num of seg pool Alloc %d, descs = %d",
  2935. __func__, num_pool, num_desc);
  2936. /* Initialize descriptors in TCL Rings */
  2937. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2938. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  2939. hal_tx_init_data_ring(soc->hal_soc,
  2940. soc->tcl_data_ring[i].hal_srng);
  2941. }
  2942. }
  2943. /*
  2944. * todo - Add a runtime config option to enable this.
  2945. */
  2946. /*
  2947. * Due to multiple issues on NPR EMU, enable it selectively
  2948. * only for NPR EMU, should be removed, once NPR platforms
  2949. * are stable.
  2950. */
  2951. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  2952. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2953. "%s HAL Tx init Success", __func__);
  2954. return QDF_STATUS_SUCCESS;
  2955. fail:
  2956. /* Detach will take care of freeing only allocated resources */
  2957. dp_tx_soc_detach(soc);
  2958. return QDF_STATUS_E_RESOURCES;
  2959. }
  2960. /*
  2961. * dp_tx_me_mem_free(): Function to free allocated memory in mcast enahncement
  2962. * pdev: pointer to DP PDEV structure
  2963. * seg_info_head: Pointer to the head of list
  2964. *
  2965. * return: void
  2966. */
  2967. static void dp_tx_me_mem_free(struct dp_pdev *pdev,
  2968. struct dp_tx_seg_info_s *seg_info_head)
  2969. {
  2970. struct dp_tx_me_buf_t *mc_uc_buf;
  2971. struct dp_tx_seg_info_s *seg_info_new = NULL;
  2972. qdf_nbuf_t nbuf = NULL;
  2973. uint64_t phy_addr;
  2974. while (seg_info_head) {
  2975. nbuf = seg_info_head->nbuf;
  2976. mc_uc_buf = (struct dp_tx_me_buf_t *)
  2977. seg_info_head->frags[0].vaddr;
  2978. phy_addr = seg_info_head->frags[0].paddr_hi;
  2979. phy_addr = (phy_addr << 32) | seg_info_head->frags[0].paddr_lo;
  2980. qdf_mem_unmap_nbytes_single(pdev->soc->osdev,
  2981. phy_addr,
  2982. QDF_DMA_TO_DEVICE , DP_MAC_ADDR_LEN);
  2983. dp_tx_me_free_buf(pdev, mc_uc_buf);
  2984. qdf_nbuf_free(nbuf);
  2985. seg_info_new = seg_info_head;
  2986. seg_info_head = seg_info_head->next;
  2987. qdf_mem_free(seg_info_new);
  2988. }
  2989. }
  2990. /**
  2991. * dp_tx_me_send_convert_ucast(): function to convert multicast to unicast
  2992. * @vdev: DP VDEV handle
  2993. * @nbuf: Multicast nbuf
  2994. * @newmac: Table of the clients to which packets have to be sent
  2995. * @new_mac_cnt: No of clients
  2996. *
  2997. * return: no of converted packets
  2998. */
  2999. uint16_t
  3000. dp_tx_me_send_convert_ucast(struct cdp_vdev *vdev_handle, qdf_nbuf_t nbuf,
  3001. uint8_t newmac[][DP_MAC_ADDR_LEN], uint8_t new_mac_cnt)
  3002. {
  3003. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  3004. struct dp_pdev *pdev = vdev->pdev;
  3005. struct ether_header *eh;
  3006. uint8_t *data;
  3007. uint16_t len;
  3008. /* reference to frame dst addr */
  3009. uint8_t *dstmac;
  3010. /* copy of original frame src addr */
  3011. uint8_t srcmac[DP_MAC_ADDR_LEN];
  3012. /* local index into newmac */
  3013. uint8_t new_mac_idx = 0;
  3014. struct dp_tx_me_buf_t *mc_uc_buf;
  3015. qdf_nbuf_t nbuf_clone;
  3016. struct dp_tx_msdu_info_s msdu_info;
  3017. struct dp_tx_seg_info_s *seg_info_head = NULL;
  3018. struct dp_tx_seg_info_s *seg_info_tail = NULL;
  3019. struct dp_tx_seg_info_s *seg_info_new;
  3020. struct dp_tx_frag_info_s data_frag;
  3021. qdf_dma_addr_t paddr_data;
  3022. qdf_dma_addr_t paddr_mcbuf = 0;
  3023. uint8_t empty_entry_mac[DP_MAC_ADDR_LEN] = {0};
  3024. QDF_STATUS status;
  3025. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  3026. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  3027. eh = (struct ether_header *) nbuf;
  3028. qdf_mem_copy(srcmac, eh->ether_shost, DP_MAC_ADDR_LEN);
  3029. len = qdf_nbuf_len(nbuf);
  3030. data = qdf_nbuf_data(nbuf);
  3031. status = qdf_nbuf_map(vdev->osdev, nbuf,
  3032. QDF_DMA_TO_DEVICE);
  3033. if (status) {
  3034. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3035. "Mapping failure Error:%d", status);
  3036. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  3037. qdf_nbuf_free(nbuf);
  3038. return 1;
  3039. }
  3040. paddr_data = qdf_nbuf_get_frag_paddr(nbuf, 0) + IEEE80211_ADDR_LEN;
  3041. /*preparing data fragment*/
  3042. data_frag.vaddr = qdf_nbuf_data(nbuf) + IEEE80211_ADDR_LEN;
  3043. data_frag.paddr_lo = (uint32_t)paddr_data;
  3044. data_frag.paddr_hi = (((uint64_t) paddr_data) >> 32);
  3045. data_frag.len = len - DP_MAC_ADDR_LEN;
  3046. for (new_mac_idx = 0; new_mac_idx < new_mac_cnt; new_mac_idx++) {
  3047. dstmac = newmac[new_mac_idx];
  3048. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3049. "added mac addr (%pM)", dstmac);
  3050. /* Check for NULL Mac Address */
  3051. if (!qdf_mem_cmp(dstmac, empty_entry_mac, DP_MAC_ADDR_LEN))
  3052. continue;
  3053. /* frame to self mac. skip */
  3054. if (!qdf_mem_cmp(dstmac, srcmac, DP_MAC_ADDR_LEN))
  3055. continue;
  3056. /*
  3057. * TODO: optimize to avoid malloc in per-packet path
  3058. * For eg. seg_pool can be made part of vdev structure
  3059. */
  3060. seg_info_new = qdf_mem_malloc(sizeof(*seg_info_new));
  3061. if (!seg_info_new) {
  3062. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3063. "alloc failed");
  3064. DP_STATS_INC(vdev, tx_i.mcast_en.fail_seg_alloc, 1);
  3065. goto fail_seg_alloc;
  3066. }
  3067. mc_uc_buf = dp_tx_me_alloc_buf(pdev);
  3068. if (mc_uc_buf == NULL)
  3069. goto fail_buf_alloc;
  3070. /*
  3071. * TODO: Check if we need to clone the nbuf
  3072. * Or can we just use the reference for all cases
  3073. */
  3074. if (new_mac_idx < (new_mac_cnt - 1)) {
  3075. nbuf_clone = qdf_nbuf_clone((qdf_nbuf_t)nbuf);
  3076. if (nbuf_clone == NULL) {
  3077. DP_STATS_INC(vdev, tx_i.mcast_en.clone_fail, 1);
  3078. goto fail_clone;
  3079. }
  3080. } else {
  3081. /*
  3082. * Update the ref
  3083. * to account for frame sent without cloning
  3084. */
  3085. qdf_nbuf_ref(nbuf);
  3086. nbuf_clone = nbuf;
  3087. }
  3088. qdf_mem_copy(mc_uc_buf->data, dstmac, DP_MAC_ADDR_LEN);
  3089. status = qdf_mem_map_nbytes_single(vdev->osdev, mc_uc_buf->data,
  3090. QDF_DMA_TO_DEVICE, DP_MAC_ADDR_LEN,
  3091. &paddr_mcbuf);
  3092. if (status) {
  3093. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3094. "Mapping failure Error:%d", status);
  3095. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  3096. goto fail_map;
  3097. }
  3098. seg_info_new->frags[0].vaddr = (uint8_t *)mc_uc_buf;
  3099. seg_info_new->frags[0].paddr_lo = (uint32_t) paddr_mcbuf;
  3100. seg_info_new->frags[0].paddr_hi =
  3101. ((uint64_t) paddr_mcbuf >> 32);
  3102. seg_info_new->frags[0].len = DP_MAC_ADDR_LEN;
  3103. seg_info_new->frags[1] = data_frag;
  3104. seg_info_new->nbuf = nbuf_clone;
  3105. seg_info_new->frag_cnt = 2;
  3106. seg_info_new->total_len = len;
  3107. seg_info_new->next = NULL;
  3108. if (seg_info_head == NULL)
  3109. seg_info_head = seg_info_new;
  3110. else
  3111. seg_info_tail->next = seg_info_new;
  3112. seg_info_tail = seg_info_new;
  3113. }
  3114. if (!seg_info_head) {
  3115. goto free_return;
  3116. }
  3117. msdu_info.u.sg_info.curr_seg = seg_info_head;
  3118. msdu_info.num_seg = new_mac_cnt;
  3119. msdu_info.frm_type = dp_tx_frm_me;
  3120. DP_STATS_INC(vdev, tx_i.mcast_en.ucast, new_mac_cnt);
  3121. dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  3122. while (seg_info_head->next) {
  3123. seg_info_new = seg_info_head;
  3124. seg_info_head = seg_info_head->next;
  3125. qdf_mem_free(seg_info_new);
  3126. }
  3127. qdf_mem_free(seg_info_head);
  3128. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  3129. qdf_nbuf_free(nbuf);
  3130. return new_mac_cnt;
  3131. fail_map:
  3132. qdf_nbuf_free(nbuf_clone);
  3133. fail_clone:
  3134. dp_tx_me_free_buf(pdev, mc_uc_buf);
  3135. fail_buf_alloc:
  3136. qdf_mem_free(seg_info_new);
  3137. fail_seg_alloc:
  3138. dp_tx_me_mem_free(pdev, seg_info_head);
  3139. free_return:
  3140. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  3141. qdf_nbuf_free(nbuf);
  3142. return 1;
  3143. }