36637cf177
Added ipq5332 target header files under qca5332 to make fw-api project compatible to host. Change-Id: Iee6b3f2a809f31e62b45a0f6e9a7cbb66e070fa0
652 wiersze
24 KiB
C
652 wiersze
24 KiB
C
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/* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _RX_MSDU_DETAILS_H_
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#define _RX_MSDU_DETAILS_H_
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#if !defined(__ASSEMBLER__)
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#endif
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#include "rx_msdu_desc_info.h"
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#include "rx_msdu_ext_desc_info.h"
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#include "buffer_addr_info.h"
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#define NUM_OF_DWORDS_RX_MSDU_DETAILS 4
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struct rx_msdu_details {
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#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
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struct buffer_addr_info buffer_addr_info_details;
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struct rx_msdu_desc_info rx_msdu_desc_info_details;
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struct rx_msdu_ext_desc_info rx_msdu_ext_desc_info_details;
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#else
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struct buffer_addr_info buffer_addr_info_details;
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struct rx_msdu_desc_info rx_msdu_desc_info_details;
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struct rx_msdu_ext_desc_info rx_msdu_ext_desc_info_details;
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#endif
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};
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/* Description BUFFER_ADDR_INFO_DETAILS
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Consumer: REO/SW
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Producer: RXDMA
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Details of the physical address of the buffer containing
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an MSDU (or entire MPDU)
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*/
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/* Description BUFFER_ADDR_31_0
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Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION
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descriptor OR Link Descriptor
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In case of 'NULL' pointer, this field is set to 0
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<legal all>
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*/
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#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000
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#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0
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#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31
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#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff
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/* Description BUFFER_ADDR_39_32
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Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION
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descriptor OR Link Descriptor
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In case of 'NULL' pointer, this field is set to 0
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<legal all>
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*/
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#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004
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#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0
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#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7
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#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff
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/* Description RETURN_BUFFER_MANAGER
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Consumer: WBM
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Producer: SW/FW
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In case of 'NULL' pointer, this field is set to 0
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Indicates to which buffer manager the buffer OR MSDU_EXTENSION
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descriptor OR link descriptor that is being pointed to
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shall be returned after the frame has been processed. It
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is used by WBM for routing purposes.
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<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
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to the WMB buffer idle list
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<enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned
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to the WBM idle link descriptor idle list, where the chip
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0 WBM is chosen in case of a multi-chip config
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<enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned
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to the chip 1 WBM idle link descriptor idle list
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<enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned
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to the chip 2 WBM idle link descriptor idle list
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<enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be
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returned to chip 3 WBM idle link descriptor idle list
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<enum 4 FW_BM> This buffer shall be returned to the FW
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<enum 5 SW0_BM> This buffer shall be returned to the SW,
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ring 0
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<enum 6 SW1_BM> This buffer shall be returned to the SW,
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ring 1
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<enum 7 SW2_BM> This buffer shall be returned to the SW,
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ring 2
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<enum 8 SW3_BM> This buffer shall be returned to the SW,
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ring 3
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<enum 9 SW4_BM> This buffer shall be returned to the SW,
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ring 4
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<enum 10 SW5_BM> This buffer shall be returned to the SW,
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ring 5
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<enum 11 SW6_BM> This buffer shall be returned to the SW,
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ring 6
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<legal 0-12>
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*/
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#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
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#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8
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#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11
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#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00
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/* Description SW_BUFFER_COOKIE
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Cookie field exclusively used by SW.
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In case of 'NULL' pointer, this field is set to 0
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HW ignores the contents, accept that it passes the programmed
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value on to other descriptors together with the physical
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address
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Field can be used by SW to for example associate the buffers
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physical address with the virtual address
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The bit definitions as used by SW are within SW HLD specification
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NOTE1:
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The three most significant bits can have a special meaning
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in case this struct is embedded in a TX_MPDU_DETAILS STRUCT,
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and field transmit_bw_restriction is set
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In case of NON punctured transmission:
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Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only
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Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only
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Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only
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Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only
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Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only
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Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only
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Sw_buffer_cookie[19:18] = 2'b11: reserved
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In case of punctured transmission:
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Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only
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Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only
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Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only
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Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only
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Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only
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Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only
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Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only
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Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only
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Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only
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Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only
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Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only
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Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only
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Sw_buffer_cookie[19:18] = 2'b11: reserved
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Note: a punctured transmission is indicated by the presence
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of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV
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<legal all>
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*/
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#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004
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#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12
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#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31
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#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000
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/* Description RX_MSDU_DESC_INFO_DETAILS
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Consumer: REO/SW
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Producer: RXDMA
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General information related to the MSDU that should be passed
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on from RXDMA all the way to to the REO destination ring.
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*/
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/* Description FIRST_MSDU_IN_MPDU_FLAG
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Parsed from RX_MSDU_END TLV . In the case MSDU spans over
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multiple buffers, this field will be valid in the Last
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buffer used by the MSDU
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<enum 0 Not_first_msdu> This is not the first MSDU in the
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MPDU.
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<enum 1 first_msdu> This MSDU is the first one in the MPDU.
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<legal all>
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*/
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
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/* Description LAST_MSDU_IN_MPDU_FLAG
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Consumer: WBM/REO/SW/FW
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Producer: RXDMA
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Parsed from RX_MSDU_END TLV . In the case MSDU spans over
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multiple buffers, this field will be valid in the Last
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buffer used by the MSDU
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<enum 0 Not_last_msdu> There are more MSDUs linked to this
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MSDU that belongs to this MPDU
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<enum 1 Last_msdu> this MSDU is the last one in the MPDU.
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This setting is only allowed in combination with 'Msdu_continuation'
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set to 0. This implies that when an msdu is spread out over
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multiple buffers and thus msdu_continuation is set, only
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for the very last buffer of the msdu, can the 'last_msdu_in_mpdu_flag'
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be set.
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When both first_msdu_in_mpdu_flag and last_msdu_in_mpdu_flag
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are set, the MPDU that this MSDU belongs to only contains
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a single MSDU.
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<legal all>
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*/
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
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/* Description MSDU_CONTINUATION
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When set, this MSDU buffer was not able to hold the entire
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MSDU. The next buffer will therefor contain additional
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information related to this MSDU.
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<legal all>
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*/
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000008
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
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/* Description MSDU_LENGTH
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Parsed from RX_MSDU_START TLV . In the case MSDU spans over
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multiple buffers, this field will be valid in the First
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buffer used by MSDU.
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Full MSDU length in bytes after decapsulation.
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This field is still valid for MPDU frames without A-MSDU.
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It still represents MSDU length after decapsulation
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Or in case of RAW MPDUs, it indicates the length of the
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entire MPDU (without FCS field)
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<legal all>
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*/
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000008
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8
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/* Description MSDU_DROP
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Parsed from RX_MSDU_END TLV . In the case MSDU spans over
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multiple buffers, this field will be valid in the Last
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buffer used by the MSDU
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When set, REO shall drop this MSDU and not forward it to
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any other ring...
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<legal all>
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*/
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000008
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000
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/* Description SA_IS_VALID
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Parsed from RX_MSDU_END TLV . In the case MSDU spans over
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multiple buffers, this field will be valid in the Last
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buffer used by the MSDU
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Indicates that OLE found a valid SA entry for this MSDU
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<legal all>
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*/
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000
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/* Description DA_IS_VALID
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Parsed from RX_MSDU_END TLV . In the case MSDU spans over
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multiple buffers, this field will be valid in the Last
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buffer used by the MSDU
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Indicates that OLE found a valid DA entry for this MSDU
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<legal all>
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*/
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000
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/* Description DA_IS_MCBC
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Field Only valid if "da_is_valid" is set
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Indicates the DA address was a Multicast of Broadcast address
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for this MSDU
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<legal all>
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*/
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000
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/* Description L3_HEADER_PADDING_MSB
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Passed on from 'RX_MSDU_END' TLV (only the MSB is reported
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as the LSB is always zero)
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Number of bytes padded to make sure that the L3 header will
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always start of a Dword boundary
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<legal all>
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*/
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000008
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000
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/* Description TCP_UDP_CHKSUM_FAIL
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Passed on from 'RX_ATTENTION' TLV
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Indicates that the computed checksum did not match the checksum
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in the TCP/UDP header.
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<legal all>
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*/
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000008
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000
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/* Description IP_CHKSUM_FAIL
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Passed on from 'RX_ATTENTION' TLV
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Indicates that the computed checksum did not match the checksum
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in the IP header.
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<legal all>
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*/
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000008
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000
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/* Description FR_DS
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Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START'
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TLV
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Set if the 'from DS' bit is set in the frame control.
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<legal all>
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*/
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000008
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000
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/* Description TO_DS
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Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START'
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TLV
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Set if the 'to DS' bit is set in the frame control.
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<legal all>
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*/
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000008
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000
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/* Description INTRA_BSS
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This packet needs intra-BSS routing by SW as the 'vdev_id'
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for the destination is the same as the 'vdev_id' (from 'RX_MPDU_PCU_START')
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that this MSDU was got in.
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<legal all>
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*/
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000008
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000
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/* Description DEST_CHIP_ID
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If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY'
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to support intra-BSS routing with multi-chip multi-link
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operation.
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This indicates into which chip's TCL the packet should be
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queued.
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<legal all>
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*/
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000008
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000
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/* Description DECAP_FORMAT
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Indicates the format after decapsulation:
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<enum 0 RAW> No encapsulation
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<enum 1 Native_WiFi>
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<enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC)
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<enum 3 802_3> Indicate Ethernet
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<legal all>
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*/
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000008
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000
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/* Description DEST_CHIP_PMAC_ID
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If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY'
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to support intra-BSS routing with multi-chip multi-link
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operation.
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This indicates into which link/'vdev' the packet should
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be queued in TCL.
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<legal all>
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*/
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_OFFSET 0x00000008
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_LSB 31
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MSB 31
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#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MASK 0x80000000
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/* Description RX_MSDU_EXT_DESC_INFO_DETAILS
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Consumer: REO/SW
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Producer: RXDMA
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Extended information related to the MSDU that is passed
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on from RXDMA to REO but not part of the REO destination
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ring. Some fields are passed on to PPE.
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*/
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/* Description REO_DESTINATION_INDICATION
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Parsed from RX_MSDU_END TLV . In the case MSDU spans over
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multiple buffers, this field will be valid in the Last
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buffer used by the MSDU
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The ID of the REO exit ring where the MSDU frame shall push
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after (MPDU level) reordering has finished.
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<enum 0 reo_destination_sw0> Reo will push the frame into
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the REO2SW0 ring
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<enum 1 reo_destination_sw1> Reo will push the frame into
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the REO2SW1 ring
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<enum 2 reo_destination_sw2> Reo will push the frame into
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the REO2SW2 ring
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<enum 3 reo_destination_sw3> Reo will push the frame into
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the REO2SW3 ring
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<enum 4 reo_destination_sw4> Reo will push the frame into
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the REO2SW4 ring
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<enum 5 reo_destination_release> Reo will push the frame
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into the REO_release ring
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<enum 6 reo_destination_fw> Reo will push the frame into
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the REO2FW ring
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<enum 7 reo_destination_sw5> Reo will push the frame into
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the REO2SW5 ring (REO remaps this in chips without REO2SW5
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ring, e.g. Pine)
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<enum 8 reo_destination_sw6> Reo will push the frame into
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the REO2SW6 ring (REO remaps this in chips without REO2SW6
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ring, e.g. Pine)
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<enum 9 reo_destination_sw7> Reo will push the frame into
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the REO2SW7 ring (REO remaps this in chips without REO2SW7
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ring)
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<enum 10 reo_destination_sw8> Reo will push the frame into
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the REO2SW8 ring (REO remaps this in chips without REO2SW8
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ring)
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<enum 11 reo_destination_11> REO remaps this
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<enum 12 reo_destination_12> REO remaps this <enum 13 reo_destination_13>
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REO remaps this
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<enum 14 reo_destination_14> REO remaps this
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<enum 15 reo_destination_15> REO remaps this
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<enum 16 reo_destination_16> REO remaps this
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<enum 17 reo_destination_17> REO remaps this
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<enum 18 reo_destination_18> REO remaps this
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<enum 19 reo_destination_19> REO remaps this
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<enum 20 reo_destination_20> REO remaps this
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<enum 21 reo_destination_21> REO remaps this
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<enum 22 reo_destination_22> REO remaps this
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<enum 23 reo_destination_23> REO remaps this
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<enum 24 reo_destination_24> REO remaps this
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<enum 25 reo_destination_25> REO remaps this
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<enum 26 reo_destination_26> REO remaps this
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<enum 27 reo_destination_27> REO remaps this
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<enum 28 reo_destination_28> REO remaps this
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<enum 29 reo_destination_29> REO remaps this
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<enum 30 reo_destination_30> REO remaps this
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<enum 31 reo_destination_31> REO remaps this
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<legal all>
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*/
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#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000000c
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#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
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#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
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#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
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/* Description SERVICE_CODE
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Opaque service code between PPE and Wi-Fi
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This field gets passed on by REO to PPE in the EDMA descriptor
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('REO_TO_PPE_RING').
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<legal all>
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*/
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#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000000c
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#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5
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#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13
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#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0
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/* Description PRIORITY_VALID
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This field gets passed on by REO to PPE in the EDMA descriptor
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('REO_TO_PPE_RING').
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<legal all>
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*/
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#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000000c
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#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14
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#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14
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#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000
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/* Description DATA_OFFSET
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The offset to Rx packet data within the buffer (including
|
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Rx DMA offset programming and L3 header padding inserted
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by Rx OLE).
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This field gets passed on by REO to PPE in the EDMA descriptor
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('REO_TO_PPE_RING').
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<legal all>
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*/
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#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000000c
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#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15
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#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26
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#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000
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/* Description SRC_LINK_ID
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Consumer: SW
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Producer: RXDMA
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Set to the link ID of the PMAC that received the frame
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<legal all>
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*/
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#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000000c
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#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27
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#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29
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#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000
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/* Description RESERVED_0A
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<legal 0>
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*/
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#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000c
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#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30
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#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31
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#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000
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#endif // RX_MSDU_DETAILS
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