sde_encoder.c 141 KB

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  1. /*
  2. * Copyright (c) 2014-2020, The Linux Foundation. All rights reserved.
  3. * Copyright (C) 2013 Red Hat
  4. * Author: Rob Clark <[email protected]>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  19. #include <linux/kthread.h>
  20. #include <linux/debugfs.h>
  21. #include <linux/input.h>
  22. #include <linux/seq_file.h>
  23. #include <linux/sde_rsc.h>
  24. #include "msm_drv.h"
  25. #include "sde_kms.h"
  26. #include <drm/drm_crtc.h>
  27. #include <drm/drm_probe_helper.h>
  28. #include "sde_hwio.h"
  29. #include "sde_hw_catalog.h"
  30. #include "sde_hw_intf.h"
  31. #include "sde_hw_ctl.h"
  32. #include "sde_formats.h"
  33. #include "sde_encoder.h"
  34. #include "sde_encoder_phys.h"
  35. #include "sde_hw_dsc.h"
  36. #include "sde_crtc.h"
  37. #include "sde_trace.h"
  38. #include "sde_core_irq.h"
  39. #include "sde_hw_top.h"
  40. #include "sde_hw_qdss.h"
  41. #include "sde_encoder_dce.h"
  42. #define SDE_DEBUG_ENC(e, fmt, ...) SDE_DEBUG("enc%d " fmt,\
  43. (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
  44. #define SDE_ERROR_ENC(e, fmt, ...) SDE_ERROR("enc%d " fmt,\
  45. (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
  46. #define SDE_DEBUG_PHYS(p, fmt, ...) SDE_DEBUG("enc%d intf%d pp%d " fmt,\
  47. (p) ? (p)->parent->base.id : -1, \
  48. (p) ? (p)->intf_idx - INTF_0 : -1, \
  49. (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \
  50. ##__VA_ARGS__)
  51. #define SDE_ERROR_PHYS(p, fmt, ...) SDE_ERROR("enc%d intf%d pp%d " fmt,\
  52. (p) ? (p)->parent->base.id : -1, \
  53. (p) ? (p)->intf_idx - INTF_0 : -1, \
  54. (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \
  55. ##__VA_ARGS__)
  56. #define MISR_BUFF_SIZE 256
  57. #define IDLE_SHORT_TIMEOUT 1
  58. #define EVT_TIME_OUT_SPLIT 2
  59. /* Maximum number of VSYNC wait attempts for RSC state transition */
  60. #define MAX_RSC_WAIT 5
  61. /**
  62. * enum sde_enc_rc_events - events for resource control state machine
  63. * @SDE_ENC_RC_EVENT_KICKOFF:
  64. * This event happens at NORMAL priority.
  65. * Event that signals the start of the transfer. When this event is
  66. * received, enable MDP/DSI core clocks and request RSC with CMD state.
  67. * Regardless of the previous state, the resource should be in ON state
  68. * at the end of this event. At the end of this event, a delayed work is
  69. * scheduled to go to IDLE_PC state after IDLE_POWERCOLLAPSE_DURATION
  70. * ktime.
  71. * @SDE_ENC_RC_EVENT_PRE_STOP:
  72. * This event happens at NORMAL priority.
  73. * This event, when received during the ON state, set RSC to IDLE, and
  74. * and leave the RC STATE in the PRE_OFF state.
  75. * It should be followed by the STOP event as part of encoder disable.
  76. * If received during IDLE or OFF states, it will do nothing.
  77. * @SDE_ENC_RC_EVENT_STOP:
  78. * This event happens at NORMAL priority.
  79. * When this event is received, disable all the MDP/DSI core clocks, and
  80. * disable IRQs. It should be called from the PRE_OFF or IDLE states.
  81. * IDLE is expected when IDLE_PC has run, and PRE_OFF did nothing.
  82. * PRE_OFF is expected when PRE_STOP was executed during the ON state.
  83. * Resource state should be in OFF at the end of the event.
  84. * @SDE_ENC_RC_EVENT_PRE_MODESET:
  85. * This event happens at NORMAL priority from a work item.
  86. * Event signals that there is a seamless mode switch is in prgoress. A
  87. * client needs to turn of only irq - leave clocks ON to reduce the mode
  88. * switch latency.
  89. * @SDE_ENC_RC_EVENT_POST_MODESET:
  90. * This event happens at NORMAL priority from a work item.
  91. * Event signals that seamless mode switch is complete and resources are
  92. * acquired. Clients wants to turn on the irq again and update the rsc
  93. * with new vtotal.
  94. * @SDE_ENC_RC_EVENT_ENTER_IDLE:
  95. * This event happens at NORMAL priority from a work item.
  96. * Event signals that there were no frame updates for
  97. * IDLE_POWERCOLLAPSE_DURATION time. This would disable MDP/DSI core clocks
  98. * and request RSC with IDLE state and change the resource state to IDLE.
  99. * @SDE_ENC_RC_EVENT_EARLY_WAKEUP:
  100. * This event is triggered from the input event thread when touch event is
  101. * received from the input device. On receiving this event,
  102. * - If the device is in SDE_ENC_RC_STATE_IDLE state, it turns ON the
  103. clocks and enable RSC.
  104. * - If the device is in SDE_ENC_RC_STATE_ON state, it resets the delayed
  105. * off work since a new commit is imminent.
  106. */
  107. enum sde_enc_rc_events {
  108. SDE_ENC_RC_EVENT_KICKOFF = 1,
  109. SDE_ENC_RC_EVENT_PRE_STOP,
  110. SDE_ENC_RC_EVENT_STOP,
  111. SDE_ENC_RC_EVENT_PRE_MODESET,
  112. SDE_ENC_RC_EVENT_POST_MODESET,
  113. SDE_ENC_RC_EVENT_ENTER_IDLE,
  114. SDE_ENC_RC_EVENT_EARLY_WAKEUP,
  115. };
  116. void sde_encoder_uidle_enable(struct drm_encoder *drm_enc, bool enable)
  117. {
  118. struct sde_encoder_virt *sde_enc;
  119. int i;
  120. sde_enc = to_sde_encoder_virt(drm_enc);
  121. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  122. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  123. if (phys && phys->hw_ctl && phys->hw_ctl->ops.uidle_enable) {
  124. SDE_EVT32(DRMID(drm_enc), enable);
  125. phys->hw_ctl->ops.uidle_enable(phys->hw_ctl, enable);
  126. }
  127. }
  128. }
  129. static void _sde_encoder_pm_qos_add_request(struct drm_encoder *drm_enc)
  130. {
  131. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  132. struct msm_drm_private *priv;
  133. struct sde_kms *sde_kms;
  134. struct device *cpu_dev;
  135. struct cpumask *cpu_mask = NULL;
  136. int cpu = 0;
  137. u32 cpu_dma_latency;
  138. priv = drm_enc->dev->dev_private;
  139. sde_kms = to_sde_kms(priv->kms);
  140. if (!sde_kms->catalog || !sde_kms->catalog->perf.cpu_mask)
  141. return;
  142. cpu_dma_latency = sde_kms->catalog->perf.cpu_dma_latency;
  143. cpumask_clear(&sde_enc->valid_cpu_mask);
  144. if (sde_enc->mode_info.frame_rate > DEFAULT_FPS)
  145. cpu_mask = to_cpumask(&sde_kms->catalog->perf.cpu_mask_perf);
  146. if (!cpu_mask &&
  147. sde_encoder_check_curr_mode(drm_enc,
  148. MSM_DISPLAY_CMD_MODE))
  149. cpu_mask = to_cpumask(&sde_kms->catalog->perf.cpu_mask);
  150. if (!cpu_mask)
  151. return;
  152. for_each_cpu(cpu, cpu_mask) {
  153. cpu_dev = get_cpu_device(cpu);
  154. if (!cpu_dev) {
  155. SDE_ERROR("%s: failed to get cpu%d device\n", __func__,
  156. cpu);
  157. return;
  158. }
  159. cpumask_set_cpu(cpu, &sde_enc->valid_cpu_mask);
  160. dev_pm_qos_add_request(cpu_dev,
  161. &sde_enc->pm_qos_cpu_req[cpu],
  162. DEV_PM_QOS_RESUME_LATENCY, cpu_dma_latency);
  163. SDE_EVT32_VERBOSE(DRMID(drm_enc), cpu_dma_latency, cpu);
  164. }
  165. }
  166. static void _sde_encoder_pm_qos_remove_request(struct drm_encoder *drm_enc)
  167. {
  168. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  169. struct device *cpu_dev;
  170. int cpu = 0;
  171. for_each_cpu(cpu, &sde_enc->valid_cpu_mask) {
  172. cpu_dev = get_cpu_device(cpu);
  173. if (!cpu_dev) {
  174. SDE_ERROR("%s: failed to get cpu%d device\n", __func__,
  175. cpu);
  176. continue;
  177. }
  178. dev_pm_qos_remove_request(&sde_enc->pm_qos_cpu_req[cpu]);
  179. SDE_EVT32_VERBOSE(DRMID(drm_enc), cpu);
  180. }
  181. cpumask_clear(&sde_enc->valid_cpu_mask);
  182. }
  183. static bool _sde_encoder_is_autorefresh_enabled(
  184. struct sde_encoder_virt *sde_enc)
  185. {
  186. struct drm_connector *drm_conn;
  187. if (!sde_enc->cur_master ||
  188. !(sde_enc->disp_info.capabilities & MSM_DISPLAY_CAP_CMD_MODE))
  189. return false;
  190. drm_conn = sde_enc->cur_master->connector;
  191. if (!drm_conn || !drm_conn->state)
  192. return false;
  193. return sde_connector_get_property(drm_conn->state,
  194. CONNECTOR_PROP_AUTOREFRESH) ? true : false;
  195. }
  196. static void sde_configure_qdss(struct sde_encoder_virt *sde_enc,
  197. struct sde_hw_qdss *hw_qdss,
  198. struct sde_encoder_phys *phys, bool enable)
  199. {
  200. if (sde_enc->qdss_status == enable)
  201. return;
  202. sde_enc->qdss_status = enable;
  203. phys->hw_mdptop->ops.set_mdp_hw_events(phys->hw_mdptop,
  204. sde_enc->qdss_status);
  205. hw_qdss->ops.enable_qdss_events(hw_qdss, sde_enc->qdss_status);
  206. }
  207. static int _sde_encoder_wait_timeout(int32_t drm_id, int32_t hw_id,
  208. s64 timeout_ms, struct sde_encoder_wait_info *info)
  209. {
  210. int rc = 0;
  211. s64 wait_time_jiffies = msecs_to_jiffies(timeout_ms);
  212. ktime_t cur_ktime;
  213. ktime_t exp_ktime = ktime_add_ms(ktime_get(), timeout_ms);
  214. do {
  215. rc = wait_event_timeout(*(info->wq),
  216. atomic_read(info->atomic_cnt) == info->count_check,
  217. wait_time_jiffies);
  218. cur_ktime = ktime_get();
  219. SDE_EVT32(drm_id, hw_id, rc, ktime_to_ms(cur_ktime),
  220. timeout_ms, atomic_read(info->atomic_cnt),
  221. info->count_check);
  222. /* If we timed out, counter is valid and time is less, wait again */
  223. } while ((atomic_read(info->atomic_cnt) != info->count_check) &&
  224. (rc == 0) &&
  225. (ktime_compare_safe(exp_ktime, cur_ktime) > 0));
  226. return rc;
  227. }
  228. bool sde_encoder_is_primary_display(struct drm_encoder *drm_enc)
  229. {
  230. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  231. return sde_enc &&
  232. (sde_enc->disp_info.display_type ==
  233. SDE_CONNECTOR_PRIMARY);
  234. }
  235. bool sde_encoder_is_dsi_display(struct drm_encoder *drm_enc)
  236. {
  237. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  238. return sde_enc &&
  239. (sde_enc->disp_info.intf_type == DRM_MODE_CONNECTOR_DSI);
  240. }
  241. int sde_encoder_in_cont_splash(struct drm_encoder *drm_enc)
  242. {
  243. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  244. return sde_enc && sde_enc->cur_master &&
  245. sde_enc->cur_master->cont_splash_enabled;
  246. }
  247. void sde_encoder_helper_report_irq_timeout(struct sde_encoder_phys *phys_enc,
  248. enum sde_intr_idx intr_idx)
  249. {
  250. SDE_EVT32(DRMID(phys_enc->parent),
  251. phys_enc->intf_idx - INTF_0,
  252. phys_enc->hw_pp->idx - PINGPONG_0,
  253. intr_idx);
  254. SDE_ERROR_PHYS(phys_enc, "irq %d timeout\n", intr_idx);
  255. if (phys_enc->parent_ops.handle_frame_done)
  256. phys_enc->parent_ops.handle_frame_done(
  257. phys_enc->parent, phys_enc,
  258. SDE_ENCODER_FRAME_EVENT_ERROR);
  259. }
  260. int sde_encoder_helper_wait_for_irq(struct sde_encoder_phys *phys_enc,
  261. enum sde_intr_idx intr_idx,
  262. struct sde_encoder_wait_info *wait_info)
  263. {
  264. struct sde_encoder_irq *irq;
  265. u32 irq_status;
  266. int ret, i;
  267. if (!phys_enc || !wait_info || intr_idx >= INTR_IDX_MAX) {
  268. SDE_ERROR("invalid params\n");
  269. return -EINVAL;
  270. }
  271. irq = &phys_enc->irq[intr_idx];
  272. /* note: do master / slave checking outside */
  273. /* return EWOULDBLOCK since we know the wait isn't necessary */
  274. if (phys_enc->enable_state == SDE_ENC_DISABLED) {
  275. SDE_ERROR_PHYS(phys_enc, "encoder is disabled\n");
  276. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  277. irq->irq_idx, intr_idx, SDE_EVTLOG_ERROR);
  278. return -EWOULDBLOCK;
  279. }
  280. if (irq->irq_idx < 0) {
  281. SDE_DEBUG_PHYS(phys_enc, "irq %s hw %d disabled, skip wait\n",
  282. irq->name, irq->hw_idx);
  283. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  284. irq->irq_idx);
  285. return 0;
  286. }
  287. SDE_DEBUG_PHYS(phys_enc, "pending_cnt %d\n",
  288. atomic_read(wait_info->atomic_cnt));
  289. SDE_EVT32_VERBOSE(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  290. irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0,
  291. atomic_read(wait_info->atomic_cnt), SDE_EVTLOG_FUNC_ENTRY);
  292. /*
  293. * Some module X may disable interrupt for longer duration
  294. * and it may trigger all interrupts including timer interrupt
  295. * when module X again enable the interrupt.
  296. * That may cause interrupt wait timeout API in this API.
  297. * It is handled by split the wait timer in two halves.
  298. */
  299. for (i = 0; i < EVT_TIME_OUT_SPLIT; i++) {
  300. ret = _sde_encoder_wait_timeout(DRMID(phys_enc->parent),
  301. irq->hw_idx,
  302. (wait_info->timeout_ms/EVT_TIME_OUT_SPLIT),
  303. wait_info);
  304. if (ret)
  305. break;
  306. }
  307. if (ret <= 0) {
  308. irq_status = sde_core_irq_read(phys_enc->sde_kms,
  309. irq->irq_idx, true);
  310. if (irq_status) {
  311. unsigned long flags;
  312. SDE_EVT32(DRMID(phys_enc->parent), intr_idx,
  313. irq->hw_idx, irq->irq_idx,
  314. phys_enc->hw_pp->idx - PINGPONG_0,
  315. atomic_read(wait_info->atomic_cnt));
  316. SDE_DEBUG_PHYS(phys_enc,
  317. "done but irq %d not triggered\n",
  318. irq->irq_idx);
  319. local_irq_save(flags);
  320. irq->cb.func(phys_enc, irq->irq_idx);
  321. local_irq_restore(flags);
  322. ret = 0;
  323. } else {
  324. ret = -ETIMEDOUT;
  325. SDE_EVT32(DRMID(phys_enc->parent), intr_idx,
  326. irq->hw_idx, irq->irq_idx,
  327. phys_enc->hw_pp->idx - PINGPONG_0,
  328. atomic_read(wait_info->atomic_cnt), irq_status,
  329. SDE_EVTLOG_ERROR);
  330. }
  331. } else {
  332. ret = 0;
  333. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  334. irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0,
  335. atomic_read(wait_info->atomic_cnt));
  336. }
  337. SDE_EVT32_VERBOSE(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  338. irq->irq_idx, ret, phys_enc->hw_pp->idx - PINGPONG_0,
  339. atomic_read(wait_info->atomic_cnt), SDE_EVTLOG_FUNC_EXIT);
  340. return ret;
  341. }
  342. int sde_encoder_helper_register_irq(struct sde_encoder_phys *phys_enc,
  343. enum sde_intr_idx intr_idx)
  344. {
  345. struct sde_encoder_irq *irq;
  346. int ret = 0;
  347. if (!phys_enc || intr_idx >= INTR_IDX_MAX) {
  348. SDE_ERROR("invalid params\n");
  349. return -EINVAL;
  350. }
  351. irq = &phys_enc->irq[intr_idx];
  352. if (irq->irq_idx >= 0) {
  353. SDE_DEBUG_PHYS(phys_enc,
  354. "skipping already registered irq %s type %d\n",
  355. irq->name, irq->intr_type);
  356. return 0;
  357. }
  358. irq->irq_idx = sde_core_irq_idx_lookup(phys_enc->sde_kms,
  359. irq->intr_type, irq->hw_idx);
  360. if (irq->irq_idx < 0) {
  361. SDE_ERROR_PHYS(phys_enc,
  362. "failed to lookup IRQ index for %s type:%d\n",
  363. irq->name, irq->intr_type);
  364. return -EINVAL;
  365. }
  366. ret = sde_core_irq_register_callback(phys_enc->sde_kms, irq->irq_idx,
  367. &irq->cb);
  368. if (ret) {
  369. SDE_ERROR_PHYS(phys_enc,
  370. "failed to register IRQ callback for %s\n",
  371. irq->name);
  372. irq->irq_idx = -EINVAL;
  373. return ret;
  374. }
  375. ret = sde_core_irq_enable(phys_enc->sde_kms, &irq->irq_idx, 1);
  376. if (ret) {
  377. SDE_ERROR_PHYS(phys_enc,
  378. "enable IRQ for intr:%s failed, irq_idx %d\n",
  379. irq->name, irq->irq_idx);
  380. sde_core_irq_unregister_callback(phys_enc->sde_kms,
  381. irq->irq_idx, &irq->cb);
  382. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  383. irq->irq_idx, SDE_EVTLOG_ERROR);
  384. irq->irq_idx = -EINVAL;
  385. return ret;
  386. }
  387. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx, irq->irq_idx);
  388. SDE_DEBUG_PHYS(phys_enc, "registered irq %s idx: %d\n",
  389. irq->name, irq->irq_idx);
  390. return ret;
  391. }
  392. int sde_encoder_helper_unregister_irq(struct sde_encoder_phys *phys_enc,
  393. enum sde_intr_idx intr_idx)
  394. {
  395. struct sde_encoder_irq *irq;
  396. int ret;
  397. if (!phys_enc) {
  398. SDE_ERROR("invalid encoder\n");
  399. return -EINVAL;
  400. }
  401. irq = &phys_enc->irq[intr_idx];
  402. /* silently skip irqs that weren't registered */
  403. if (irq->irq_idx < 0) {
  404. SDE_ERROR(
  405. "extra unregister irq, enc%d intr_idx:0x%x hw_idx:0x%x irq_idx:0x%x\n",
  406. DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  407. irq->irq_idx);
  408. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  409. irq->irq_idx, SDE_EVTLOG_ERROR);
  410. return 0;
  411. }
  412. ret = sde_core_irq_disable(phys_enc->sde_kms, &irq->irq_idx, 1);
  413. if (ret)
  414. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  415. irq->irq_idx, ret, SDE_EVTLOG_ERROR);
  416. ret = sde_core_irq_unregister_callback(phys_enc->sde_kms, irq->irq_idx,
  417. &irq->cb);
  418. if (ret)
  419. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  420. irq->irq_idx, ret, SDE_EVTLOG_ERROR);
  421. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx, irq->irq_idx);
  422. SDE_DEBUG_PHYS(phys_enc, "unregistered %d\n", irq->irq_idx);
  423. irq->irq_idx = -EINVAL;
  424. return 0;
  425. }
  426. void sde_encoder_get_hw_resources(struct drm_encoder *drm_enc,
  427. struct sde_encoder_hw_resources *hw_res,
  428. struct drm_connector_state *conn_state)
  429. {
  430. struct sde_encoder_virt *sde_enc = NULL;
  431. int ret, i = 0;
  432. if (!hw_res || !drm_enc || !conn_state || !hw_res->comp_info) {
  433. SDE_ERROR("rc %d, drm_enc %d, res %d, state %d, comp-info %d\n",
  434. -EINVAL, !drm_enc, !hw_res, !conn_state,
  435. hw_res ? !hw_res->comp_info : 0);
  436. return;
  437. }
  438. sde_enc = to_sde_encoder_virt(drm_enc);
  439. SDE_DEBUG_ENC(sde_enc, "\n");
  440. hw_res->display_num_of_h_tiles = sde_enc->display_num_of_h_tiles;
  441. hw_res->display_type = sde_enc->disp_info.display_type;
  442. /* Query resources used by phys encs, expected to be without overlap */
  443. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  444. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  445. if (phys && phys->ops.get_hw_resources)
  446. phys->ops.get_hw_resources(phys, hw_res, conn_state);
  447. }
  448. /*
  449. * NOTE: Do not use sde_encoder_get_mode_info here as this function is
  450. * called from atomic_check phase. Use the below API to get mode
  451. * information of the temporary conn_state passed
  452. */
  453. ret = sde_connector_state_get_topology(conn_state, &hw_res->topology);
  454. if (ret)
  455. SDE_ERROR("failed to get topology ret %d\n", ret);
  456. ret = sde_connector_state_get_compression_info(conn_state,
  457. hw_res->comp_info);
  458. if (ret)
  459. SDE_ERROR("failed to get compression info ret %d\n", ret);
  460. }
  461. void sde_encoder_destroy(struct drm_encoder *drm_enc)
  462. {
  463. struct sde_encoder_virt *sde_enc = NULL;
  464. int i = 0;
  465. if (!drm_enc) {
  466. SDE_ERROR("invalid encoder\n");
  467. return;
  468. }
  469. sde_enc = to_sde_encoder_virt(drm_enc);
  470. SDE_DEBUG_ENC(sde_enc, "\n");
  471. mutex_lock(&sde_enc->enc_lock);
  472. sde_rsc_client_destroy(sde_enc->rsc_client);
  473. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  474. struct sde_encoder_phys *phys;
  475. phys = sde_enc->phys_vid_encs[i];
  476. if (phys && phys->ops.destroy) {
  477. phys->ops.destroy(phys);
  478. --sde_enc->num_phys_encs;
  479. sde_enc->phys_encs[i] = NULL;
  480. }
  481. phys = sde_enc->phys_cmd_encs[i];
  482. if (phys && phys->ops.destroy) {
  483. phys->ops.destroy(phys);
  484. --sde_enc->num_phys_encs;
  485. sde_enc->phys_encs[i] = NULL;
  486. }
  487. }
  488. if (sde_enc->num_phys_encs)
  489. SDE_ERROR_ENC(sde_enc, "expected 0 num_phys_encs not %d\n",
  490. sde_enc->num_phys_encs);
  491. sde_enc->num_phys_encs = 0;
  492. mutex_unlock(&sde_enc->enc_lock);
  493. drm_encoder_cleanup(drm_enc);
  494. mutex_destroy(&sde_enc->enc_lock);
  495. kfree(sde_enc->input_handler);
  496. sde_enc->input_handler = NULL;
  497. kfree(sde_enc);
  498. }
  499. void sde_encoder_helper_update_intf_cfg(
  500. struct sde_encoder_phys *phys_enc)
  501. {
  502. struct sde_encoder_virt *sde_enc;
  503. struct sde_hw_intf_cfg_v1 *intf_cfg;
  504. enum sde_3d_blend_mode mode_3d;
  505. if (!phys_enc || !phys_enc->hw_pp) {
  506. SDE_ERROR("invalid args, encoder %d\n", !phys_enc);
  507. return;
  508. }
  509. sde_enc = to_sde_encoder_virt(phys_enc->parent);
  510. intf_cfg = &sde_enc->cur_master->intf_cfg_v1;
  511. SDE_DEBUG_ENC(sde_enc,
  512. "intf_cfg updated for %d at idx %d\n",
  513. phys_enc->intf_idx,
  514. intf_cfg->intf_count);
  515. /* setup interface configuration */
  516. if (intf_cfg->intf_count >= MAX_INTF_PER_CTL_V1) {
  517. pr_err("invalid inf_count %d\n", intf_cfg->intf_count);
  518. return;
  519. }
  520. intf_cfg->intf[intf_cfg->intf_count++] = phys_enc->intf_idx;
  521. if (phys_enc == sde_enc->cur_master) {
  522. if (sde_enc->cur_master->intf_mode == INTF_MODE_CMD)
  523. intf_cfg->intf_mode_sel = SDE_CTL_MODE_SEL_CMD;
  524. else
  525. intf_cfg->intf_mode_sel = SDE_CTL_MODE_SEL_VID;
  526. }
  527. /* configure this interface as master for split display */
  528. if (phys_enc->split_role == ENC_ROLE_MASTER)
  529. intf_cfg->intf_master = phys_enc->hw_intf->idx;
  530. /* setup which pp blk will connect to this intf */
  531. if (phys_enc->hw_intf->ops.bind_pingpong_blk)
  532. phys_enc->hw_intf->ops.bind_pingpong_blk(
  533. phys_enc->hw_intf,
  534. true,
  535. phys_enc->hw_pp->idx);
  536. /*setup merge_3d configuration */
  537. mode_3d = sde_encoder_helper_get_3d_blend_mode(phys_enc);
  538. if (mode_3d && phys_enc->hw_pp->merge_3d &&
  539. intf_cfg->merge_3d_count < MAX_MERGE_3D_PER_CTL_V1)
  540. intf_cfg->merge_3d[intf_cfg->merge_3d_count++] =
  541. phys_enc->hw_pp->merge_3d->idx;
  542. if (phys_enc->hw_pp->ops.setup_3d_mode)
  543. phys_enc->hw_pp->ops.setup_3d_mode(phys_enc->hw_pp,
  544. mode_3d);
  545. }
  546. void sde_encoder_helper_split_config(
  547. struct sde_encoder_phys *phys_enc,
  548. enum sde_intf interface)
  549. {
  550. struct sde_encoder_virt *sde_enc;
  551. struct split_pipe_cfg *cfg;
  552. struct sde_hw_mdp *hw_mdptop;
  553. enum sde_rm_topology_name topology;
  554. struct msm_display_info *disp_info;
  555. if (!phys_enc || !phys_enc->hw_mdptop || !phys_enc->parent) {
  556. SDE_ERROR("invalid arg(s), encoder %d\n", !phys_enc);
  557. return;
  558. }
  559. sde_enc = to_sde_encoder_virt(phys_enc->parent);
  560. hw_mdptop = phys_enc->hw_mdptop;
  561. disp_info = &sde_enc->disp_info;
  562. cfg = &phys_enc->hw_intf->cfg;
  563. memset(cfg, 0, sizeof(*cfg));
  564. if (disp_info->intf_type != DRM_MODE_CONNECTOR_DSI)
  565. return;
  566. if (disp_info->capabilities & MSM_DISPLAY_SPLIT_LINK)
  567. cfg->split_link_en = true;
  568. /**
  569. * disable split modes since encoder will be operating in as the only
  570. * encoder, either for the entire use case in the case of, for example,
  571. * single DSI, or for this frame in the case of left/right only partial
  572. * update.
  573. */
  574. if (phys_enc->split_role == ENC_ROLE_SOLO) {
  575. if (hw_mdptop->ops.setup_split_pipe)
  576. hw_mdptop->ops.setup_split_pipe(hw_mdptop, cfg);
  577. if (hw_mdptop->ops.setup_pp_split)
  578. hw_mdptop->ops.setup_pp_split(hw_mdptop, cfg);
  579. return;
  580. }
  581. cfg->en = true;
  582. cfg->mode = phys_enc->intf_mode;
  583. cfg->intf = interface;
  584. if (cfg->en && phys_enc->ops.needs_single_flush &&
  585. phys_enc->ops.needs_single_flush(phys_enc))
  586. cfg->split_flush_en = true;
  587. topology = sde_connector_get_topology_name(phys_enc->connector);
  588. if (topology == SDE_RM_TOPOLOGY_PPSPLIT)
  589. cfg->pp_split_slave = cfg->intf;
  590. else
  591. cfg->pp_split_slave = INTF_MAX;
  592. if (phys_enc->split_role == ENC_ROLE_MASTER) {
  593. SDE_DEBUG_ENC(sde_enc, "enable %d\n", cfg->en);
  594. if (hw_mdptop->ops.setup_split_pipe)
  595. hw_mdptop->ops.setup_split_pipe(hw_mdptop, cfg);
  596. } else if (sde_enc->hw_pp[0]) {
  597. /*
  598. * slave encoder
  599. * - determine split index from master index,
  600. * assume master is first pp
  601. */
  602. cfg->pp_split_index = sde_enc->hw_pp[0]->idx - PINGPONG_0;
  603. SDE_DEBUG_ENC(sde_enc, "master using pp%d\n",
  604. cfg->pp_split_index);
  605. if (hw_mdptop->ops.setup_pp_split)
  606. hw_mdptop->ops.setup_pp_split(hw_mdptop, cfg);
  607. }
  608. }
  609. bool sde_encoder_in_clone_mode(struct drm_encoder *drm_enc)
  610. {
  611. struct sde_encoder_virt *sde_enc;
  612. int i = 0;
  613. if (!drm_enc)
  614. return false;
  615. sde_enc = to_sde_encoder_virt(drm_enc);
  616. if (!sde_enc)
  617. return false;
  618. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  619. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  620. if (phys && phys->in_clone_mode)
  621. return true;
  622. }
  623. return false;
  624. }
  625. static int _sde_encoder_atomic_check_phys_enc(struct sde_encoder_virt *sde_enc,
  626. struct drm_crtc_state *crtc_state,
  627. struct drm_connector_state *conn_state)
  628. {
  629. const struct drm_display_mode *mode;
  630. struct drm_display_mode *adj_mode;
  631. int i = 0;
  632. int ret = 0;
  633. mode = &crtc_state->mode;
  634. adj_mode = &crtc_state->adjusted_mode;
  635. /* perform atomic check on the first physical encoder (master) */
  636. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  637. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  638. if (phys && phys->ops.atomic_check)
  639. ret = phys->ops.atomic_check(phys, crtc_state,
  640. conn_state);
  641. else if (phys && phys->ops.mode_fixup)
  642. if (!phys->ops.mode_fixup(phys, mode, adj_mode))
  643. ret = -EINVAL;
  644. if (ret) {
  645. SDE_ERROR_ENC(sde_enc,
  646. "mode unsupported, phys idx %d\n", i);
  647. break;
  648. }
  649. }
  650. return ret;
  651. }
  652. static int _sde_encoder_atomic_check_pu_roi(struct sde_encoder_virt *sde_enc,
  653. struct drm_crtc_state *crtc_state,
  654. struct drm_connector_state *conn_state,
  655. struct sde_connector_state *sde_conn_state,
  656. struct sde_crtc_state *sde_crtc_state)
  657. {
  658. int ret = 0;
  659. if (crtc_state->mode_changed || crtc_state->active_changed) {
  660. struct sde_rect mode_roi, roi;
  661. mode_roi.x = 0;
  662. mode_roi.y = 0;
  663. mode_roi.w = crtc_state->adjusted_mode.hdisplay;
  664. mode_roi.h = crtc_state->adjusted_mode.vdisplay;
  665. if (sde_conn_state->rois.num_rects) {
  666. sde_kms_rect_merge_rectangles(
  667. &sde_conn_state->rois, &roi);
  668. if (!sde_kms_rect_is_equal(&mode_roi, &roi)) {
  669. SDE_ERROR_ENC(sde_enc,
  670. "roi (%d,%d,%d,%d) on connector invalid during modeset\n",
  671. roi.x, roi.y, roi.w, roi.h);
  672. ret = -EINVAL;
  673. }
  674. }
  675. if (sde_crtc_state->user_roi_list.num_rects) {
  676. sde_kms_rect_merge_rectangles(
  677. &sde_crtc_state->user_roi_list, &roi);
  678. if (!sde_kms_rect_is_equal(&mode_roi, &roi)) {
  679. SDE_ERROR_ENC(sde_enc,
  680. "roi (%d,%d,%d,%d) on crtc invalid during modeset\n",
  681. roi.x, roi.y, roi.w, roi.h);
  682. ret = -EINVAL;
  683. }
  684. }
  685. }
  686. return ret;
  687. }
  688. static int _sde_encoder_atomic_check_reserve(struct drm_encoder *drm_enc,
  689. struct drm_crtc_state *crtc_state,
  690. struct drm_connector_state *conn_state,
  691. struct sde_encoder_virt *sde_enc, struct sde_kms *sde_kms,
  692. struct sde_connector *sde_conn,
  693. struct sde_connector_state *sde_conn_state)
  694. {
  695. int ret = 0;
  696. struct drm_display_mode *adj_mode = &crtc_state->adjusted_mode;
  697. if (sde_conn && drm_atomic_crtc_needs_modeset(crtc_state)) {
  698. struct msm_display_topology *topology = NULL;
  699. ret = sde_connector_get_mode_info(&sde_conn->base,
  700. adj_mode, &sde_conn_state->mode_info);
  701. if (ret) {
  702. SDE_ERROR_ENC(sde_enc,
  703. "failed to get mode info, rc = %d\n", ret);
  704. return ret;
  705. }
  706. if (sde_conn_state->mode_info.comp_info.comp_type &&
  707. sde_conn_state->mode_info.comp_info.comp_ratio >=
  708. MSM_DISPLAY_COMPRESSION_RATIO_MAX) {
  709. SDE_ERROR_ENC(sde_enc,
  710. "invalid compression ratio: %d\n",
  711. sde_conn_state->mode_info.comp_info.comp_ratio);
  712. ret = -EINVAL;
  713. return ret;
  714. }
  715. /* Reserve dynamic resources, indicating atomic_check phase */
  716. ret = sde_rm_reserve(&sde_kms->rm, drm_enc, crtc_state,
  717. conn_state, true);
  718. if (ret) {
  719. SDE_ERROR_ENC(sde_enc,
  720. "RM failed to reserve resources, rc = %d\n",
  721. ret);
  722. return ret;
  723. }
  724. /**
  725. * Update connector state with the topology selected for the
  726. * resource set validated. Reset the topology if we are
  727. * de-activating crtc.
  728. */
  729. if (crtc_state->active)
  730. topology = &sde_conn_state->mode_info.topology;
  731. ret = sde_rm_update_topology(&sde_kms->rm,
  732. conn_state, topology);
  733. if (ret) {
  734. SDE_ERROR_ENC(sde_enc,
  735. "RM failed to update topology, rc: %d\n", ret);
  736. return ret;
  737. }
  738. ret = sde_connector_set_blob_data(conn_state->connector,
  739. conn_state,
  740. CONNECTOR_PROP_SDE_INFO);
  741. if (ret) {
  742. SDE_ERROR_ENC(sde_enc,
  743. "connector failed to update info, rc: %d\n",
  744. ret);
  745. return ret;
  746. }
  747. }
  748. return ret;
  749. }
  750. static int sde_encoder_virt_atomic_check(
  751. struct drm_encoder *drm_enc, struct drm_crtc_state *crtc_state,
  752. struct drm_connector_state *conn_state)
  753. {
  754. struct sde_encoder_virt *sde_enc;
  755. struct sde_kms *sde_kms;
  756. const struct drm_display_mode *mode;
  757. struct drm_display_mode *adj_mode;
  758. struct sde_connector *sde_conn = NULL;
  759. struct sde_connector_state *sde_conn_state = NULL;
  760. struct sde_crtc_state *sde_crtc_state = NULL;
  761. enum sde_rm_topology_name old_top;
  762. int ret = 0;
  763. if (!drm_enc || !crtc_state || !conn_state) {
  764. SDE_ERROR("invalid arg(s), drm_enc %d, crtc/conn state %d/%d\n",
  765. !drm_enc, !crtc_state, !conn_state);
  766. return -EINVAL;
  767. }
  768. sde_enc = to_sde_encoder_virt(drm_enc);
  769. SDE_DEBUG_ENC(sde_enc, "\n");
  770. sde_kms = sde_encoder_get_kms(drm_enc);
  771. if (!sde_kms)
  772. return -EINVAL;
  773. mode = &crtc_state->mode;
  774. adj_mode = &crtc_state->adjusted_mode;
  775. sde_conn = to_sde_connector(conn_state->connector);
  776. sde_conn_state = to_sde_connector_state(conn_state);
  777. sde_crtc_state = to_sde_crtc_state(crtc_state);
  778. SDE_EVT32(DRMID(drm_enc), crtc_state->mode_changed,
  779. crtc_state->active_changed, crtc_state->connectors_changed);
  780. ret = _sde_encoder_atomic_check_phys_enc(sde_enc, crtc_state,
  781. conn_state);
  782. if (ret)
  783. return ret;
  784. ret = _sde_encoder_atomic_check_pu_roi(sde_enc, crtc_state,
  785. conn_state, sde_conn_state, sde_crtc_state);
  786. if (ret)
  787. return ret;
  788. /**
  789. * record topology in previous atomic state to be able to handle
  790. * topology transitions correctly.
  791. */
  792. old_top = sde_connector_get_property(conn_state,
  793. CONNECTOR_PROP_TOPOLOGY_NAME);
  794. ret = sde_connector_set_old_topology_name(conn_state, old_top);
  795. if (ret)
  796. return ret;
  797. ret = _sde_encoder_atomic_check_reserve(drm_enc, crtc_state,
  798. conn_state, sde_enc, sde_kms, sde_conn, sde_conn_state);
  799. if (ret)
  800. return ret;
  801. ret = sde_connector_roi_v1_check_roi(conn_state);
  802. if (ret) {
  803. SDE_ERROR_ENC(sde_enc, "connector roi check failed, rc: %d",
  804. ret);
  805. return ret;
  806. }
  807. drm_mode_set_crtcinfo(adj_mode, 0);
  808. SDE_EVT32(DRMID(drm_enc), adj_mode->flags, adj_mode->private_flags);
  809. return ret;
  810. }
  811. static void _sde_encoder_get_connector_roi(
  812. struct sde_encoder_virt *sde_enc,
  813. struct sde_rect *merged_conn_roi)
  814. {
  815. struct drm_connector *drm_conn;
  816. struct sde_connector_state *c_state;
  817. if (!sde_enc || !merged_conn_roi)
  818. return;
  819. drm_conn = sde_enc->phys_encs[0]->connector;
  820. if (!drm_conn || !drm_conn->state)
  821. return;
  822. c_state = to_sde_connector_state(drm_conn->state);
  823. sde_kms_rect_merge_rectangles(&c_state->rois, merged_conn_roi);
  824. }
  825. static int _sde_encoder_update_roi(struct drm_encoder *drm_enc)
  826. {
  827. struct sde_encoder_virt *sde_enc;
  828. struct drm_connector *drm_conn;
  829. struct drm_display_mode *adj_mode;
  830. struct sde_rect roi;
  831. if (!drm_enc) {
  832. SDE_ERROR("invalid encoder parameter\n");
  833. return -EINVAL;
  834. }
  835. sde_enc = to_sde_encoder_virt(drm_enc);
  836. if (!sde_enc->crtc || !sde_enc->crtc->state) {
  837. SDE_ERROR("invalid crtc parameter\n");
  838. return -EINVAL;
  839. }
  840. if (!sde_enc->cur_master) {
  841. SDE_ERROR("invalid cur_master parameter\n");
  842. return -EINVAL;
  843. }
  844. adj_mode = &sde_enc->cur_master->cached_mode;
  845. drm_conn = sde_enc->cur_master->connector;
  846. _sde_encoder_get_connector_roi(sde_enc, &roi);
  847. if (sde_kms_rect_is_null(&roi)) {
  848. roi.w = adj_mode->hdisplay;
  849. roi.h = adj_mode->vdisplay;
  850. }
  851. memcpy(&sde_enc->prv_conn_roi, &sde_enc->cur_conn_roi,
  852. sizeof(sde_enc->prv_conn_roi));
  853. memcpy(&sde_enc->cur_conn_roi, &roi, sizeof(sde_enc->cur_conn_roi));
  854. return 0;
  855. }
  856. void sde_encoder_helper_vsync_config(struct sde_encoder_phys *phys_enc,
  857. u32 vsync_source, bool is_dummy)
  858. {
  859. struct sde_vsync_source_cfg vsync_cfg = { 0 };
  860. struct sde_kms *sde_kms;
  861. struct sde_hw_mdp *hw_mdptop;
  862. struct sde_encoder_virt *sde_enc;
  863. int i;
  864. sde_enc = to_sde_encoder_virt(phys_enc->parent);
  865. if (!sde_enc) {
  866. SDE_ERROR("invalid param sde_enc:%d\n", sde_enc != NULL);
  867. return;
  868. } else if (sde_enc->num_phys_encs > ARRAY_SIZE(sde_enc->hw_pp)) {
  869. SDE_ERROR("invalid num phys enc %d/%d\n",
  870. sde_enc->num_phys_encs,
  871. (int) ARRAY_SIZE(sde_enc->hw_pp));
  872. return;
  873. }
  874. sde_kms = sde_encoder_get_kms(&sde_enc->base);
  875. if (!sde_kms) {
  876. SDE_ERROR("invalid sde_kms\n");
  877. return;
  878. }
  879. hw_mdptop = sde_kms->hw_mdp;
  880. if (!hw_mdptop) {
  881. SDE_ERROR("invalid mdptop\n");
  882. return;
  883. }
  884. if (hw_mdptop->ops.setup_vsync_source) {
  885. for (i = 0; i < sde_enc->num_phys_encs; i++)
  886. vsync_cfg.ppnumber[i] = sde_enc->hw_pp[i]->idx;
  887. vsync_cfg.pp_count = sde_enc->num_phys_encs;
  888. vsync_cfg.frame_rate = sde_enc->mode_info.frame_rate;
  889. vsync_cfg.vsync_source = vsync_source;
  890. vsync_cfg.is_dummy = is_dummy;
  891. hw_mdptop->ops.setup_vsync_source(hw_mdptop, &vsync_cfg);
  892. }
  893. }
  894. static void _sde_encoder_update_vsync_source(struct sde_encoder_virt *sde_enc,
  895. struct msm_display_info *disp_info, bool is_dummy)
  896. {
  897. struct sde_encoder_phys *phys;
  898. int i;
  899. u32 vsync_source;
  900. if (!sde_enc || !disp_info) {
  901. SDE_ERROR("invalid param sde_enc:%d or disp_info:%d\n",
  902. sde_enc != NULL, disp_info != NULL);
  903. return;
  904. } else if (sde_enc->num_phys_encs > ARRAY_SIZE(sde_enc->hw_pp)) {
  905. SDE_ERROR("invalid num phys enc %d/%d\n",
  906. sde_enc->num_phys_encs,
  907. (int) ARRAY_SIZE(sde_enc->hw_pp));
  908. return;
  909. }
  910. if (sde_encoder_check_curr_mode(&sde_enc->base, MSM_DISPLAY_CMD_MODE)) {
  911. if (is_dummy)
  912. vsync_source = SDE_VSYNC_SOURCE_WD_TIMER_0 -
  913. sde_enc->te_source;
  914. else if (disp_info->is_te_using_watchdog_timer)
  915. vsync_source = SDE_VSYNC_SOURCE_WD_TIMER_4 +
  916. sde_enc->te_source;
  917. else
  918. vsync_source = sde_enc->te_source;
  919. SDE_EVT32(DRMID(&sde_enc->base), vsync_source, is_dummy,
  920. disp_info->is_te_using_watchdog_timer);
  921. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  922. phys = sde_enc->phys_encs[i];
  923. if (phys && phys->ops.setup_vsync_source)
  924. phys->ops.setup_vsync_source(phys,
  925. vsync_source, is_dummy);
  926. }
  927. }
  928. }
  929. int sde_encoder_helper_switch_vsync(struct drm_encoder *drm_enc,
  930. bool watchdog_te)
  931. {
  932. struct sde_encoder_virt *sde_enc;
  933. struct msm_display_info disp_info;
  934. if (!drm_enc) {
  935. pr_err("invalid drm encoder\n");
  936. return -EINVAL;
  937. }
  938. sde_enc = to_sde_encoder_virt(drm_enc);
  939. sde_encoder_control_te(drm_enc, false);
  940. memcpy(&disp_info, &sde_enc->disp_info, sizeof(disp_info));
  941. disp_info.is_te_using_watchdog_timer = watchdog_te;
  942. _sde_encoder_update_vsync_source(sde_enc, &disp_info, false);
  943. sde_encoder_control_te(drm_enc, true);
  944. return 0;
  945. }
  946. static int _sde_encoder_rsc_client_update_vsync_wait(
  947. struct drm_encoder *drm_enc, struct sde_encoder_virt *sde_enc,
  948. int wait_vblank_crtc_id)
  949. {
  950. int wait_refcount = 0, ret = 0;
  951. int pipe = -1;
  952. int wait_count = 0;
  953. struct drm_crtc *primary_crtc;
  954. struct drm_crtc *crtc;
  955. crtc = sde_enc->crtc;
  956. if (wait_vblank_crtc_id)
  957. wait_refcount =
  958. sde_rsc_client_get_vsync_refcount(sde_enc->rsc_client);
  959. SDE_EVT32_VERBOSE(DRMID(drm_enc), wait_vblank_crtc_id, wait_refcount,
  960. SDE_EVTLOG_FUNC_ENTRY);
  961. if (crtc->base.id != wait_vblank_crtc_id) {
  962. primary_crtc = drm_crtc_find(drm_enc->dev,
  963. NULL, wait_vblank_crtc_id);
  964. if (!primary_crtc) {
  965. SDE_ERROR_ENC(sde_enc,
  966. "failed to find primary crtc id %d\n",
  967. wait_vblank_crtc_id);
  968. return -EINVAL;
  969. }
  970. pipe = drm_crtc_index(primary_crtc);
  971. }
  972. /**
  973. * note: VBLANK is expected to be enabled at this point in
  974. * resource control state machine if on primary CRTC
  975. */
  976. for (wait_count = 0; wait_count < MAX_RSC_WAIT; wait_count++) {
  977. if (sde_rsc_client_is_state_update_complete(
  978. sde_enc->rsc_client))
  979. break;
  980. if (crtc->base.id == wait_vblank_crtc_id)
  981. ret = sde_encoder_wait_for_event(drm_enc,
  982. MSM_ENC_VBLANK);
  983. else
  984. drm_wait_one_vblank(drm_enc->dev, pipe);
  985. if (ret) {
  986. SDE_ERROR_ENC(sde_enc,
  987. "wait for vblank failed ret:%d\n", ret);
  988. /**
  989. * rsc hardware may hang without vsync. avoid rsc hang
  990. * by generating the vsync from watchdog timer.
  991. */
  992. if (crtc->base.id == wait_vblank_crtc_id)
  993. sde_encoder_helper_switch_vsync(drm_enc, true);
  994. }
  995. }
  996. if (wait_count >= MAX_RSC_WAIT)
  997. SDE_EVT32(DRMID(drm_enc), wait_vblank_crtc_id, wait_count,
  998. SDE_EVTLOG_ERROR);
  999. if (wait_refcount)
  1000. sde_rsc_client_reset_vsync_refcount(sde_enc->rsc_client);
  1001. SDE_EVT32_VERBOSE(DRMID(drm_enc), wait_vblank_crtc_id, wait_refcount,
  1002. SDE_EVTLOG_FUNC_EXIT);
  1003. return ret;
  1004. }
  1005. static int _sde_encoder_update_rsc_client(
  1006. struct drm_encoder *drm_enc, bool enable)
  1007. {
  1008. struct sde_encoder_virt *sde_enc;
  1009. struct drm_crtc *crtc;
  1010. enum sde_rsc_state rsc_state = SDE_RSC_IDLE_STATE;
  1011. struct sde_rsc_cmd_config *rsc_config;
  1012. int ret;
  1013. struct msm_display_info *disp_info;
  1014. struct msm_mode_info *mode_info;
  1015. int wait_vblank_crtc_id = SDE_RSC_INVALID_CRTC_ID;
  1016. u32 qsync_mode = 0, v_front_porch;
  1017. struct drm_display_mode *mode;
  1018. bool is_vid_mode;
  1019. struct drm_encoder *enc;
  1020. if (!drm_enc || !drm_enc->dev) {
  1021. SDE_ERROR("invalid encoder arguments\n");
  1022. return -EINVAL;
  1023. }
  1024. sde_enc = to_sde_encoder_virt(drm_enc);
  1025. mode_info = &sde_enc->mode_info;
  1026. crtc = sde_enc->crtc;
  1027. if (!sde_enc->crtc) {
  1028. SDE_ERROR("invalid crtc parameter\n");
  1029. return -EINVAL;
  1030. }
  1031. disp_info = &sde_enc->disp_info;
  1032. rsc_config = &sde_enc->rsc_config;
  1033. if (!sde_enc->rsc_client) {
  1034. SDE_DEBUG_ENC(sde_enc, "rsc client not created\n");
  1035. return 0;
  1036. }
  1037. /**
  1038. * only primary command mode panel without Qsync can request CMD state.
  1039. * all other panels/displays can request for VID state including
  1040. * secondary command mode panel.
  1041. * Clone mode encoder can request CLK STATE only.
  1042. */
  1043. if (sde_enc->cur_master)
  1044. qsync_mode = sde_connector_get_qsync_mode(
  1045. sde_enc->cur_master->connector);
  1046. if (sde_encoder_in_clone_mode(drm_enc) ||
  1047. (disp_info->display_type != SDE_CONNECTOR_PRIMARY) ||
  1048. (disp_info->display_type && qsync_mode))
  1049. rsc_state = enable ? SDE_RSC_CLK_STATE : SDE_RSC_IDLE_STATE;
  1050. else if (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE))
  1051. rsc_state = enable ? SDE_RSC_CMD_STATE : SDE_RSC_IDLE_STATE;
  1052. else if (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_VIDEO_MODE))
  1053. rsc_state = enable ? SDE_RSC_VID_STATE : SDE_RSC_IDLE_STATE;
  1054. drm_for_each_encoder(enc, drm_enc->dev) {
  1055. if (enc->base.id != drm_enc->base.id &&
  1056. sde_encoder_in_cont_splash(enc))
  1057. rsc_state = SDE_RSC_CLK_STATE;
  1058. }
  1059. SDE_EVT32(rsc_state, qsync_mode);
  1060. is_vid_mode = sde_encoder_check_curr_mode(&sde_enc->base,
  1061. MSM_DISPLAY_VIDEO_MODE);
  1062. mode = &sde_enc->crtc->state->mode;
  1063. v_front_porch = mode->vsync_start - mode->vdisplay;
  1064. /* compare specific items and reconfigure the rsc */
  1065. if ((rsc_config->fps != mode_info->frame_rate) ||
  1066. (rsc_config->vtotal != mode_info->vtotal) ||
  1067. (rsc_config->prefill_lines != mode_info->prefill_lines) ||
  1068. (rsc_config->jitter_numer != mode_info->jitter_numer) ||
  1069. (rsc_config->jitter_denom != mode_info->jitter_denom)) {
  1070. rsc_config->fps = mode_info->frame_rate;
  1071. rsc_config->vtotal = mode_info->vtotal;
  1072. /*
  1073. * for video mode, prefill lines should not go beyond vertical
  1074. * front porch for RSCC configuration. This will ensure bw
  1075. * downvotes are not sent within the active region. Additional
  1076. * -1 is to give one line time for rscc mode min_threshold.
  1077. */
  1078. if (is_vid_mode && (mode_info->prefill_lines >= v_front_porch))
  1079. rsc_config->prefill_lines = v_front_porch - 1;
  1080. else
  1081. rsc_config->prefill_lines = mode_info->prefill_lines;
  1082. rsc_config->jitter_numer = mode_info->jitter_numer;
  1083. rsc_config->jitter_denom = mode_info->jitter_denom;
  1084. sde_enc->rsc_state_init = false;
  1085. }
  1086. if (rsc_state != SDE_RSC_IDLE_STATE && !sde_enc->rsc_state_init
  1087. && (disp_info->display_type == SDE_CONNECTOR_PRIMARY)) {
  1088. /* update it only once */
  1089. sde_enc->rsc_state_init = true;
  1090. ret = sde_rsc_client_state_update(sde_enc->rsc_client,
  1091. rsc_state, rsc_config, crtc->base.id,
  1092. &wait_vblank_crtc_id);
  1093. } else {
  1094. ret = sde_rsc_client_state_update(sde_enc->rsc_client,
  1095. rsc_state, NULL, crtc->base.id,
  1096. &wait_vblank_crtc_id);
  1097. }
  1098. /**
  1099. * if RSC performed a state change that requires a VBLANK wait, it will
  1100. * set wait_vblank_crtc_id to the CRTC whose VBLANK we must wait on.
  1101. *
  1102. * if we are the primary display, we will need to enable and wait
  1103. * locally since we hold the commit thread
  1104. *
  1105. * if we are an external display, we must send a signal to the primary
  1106. * to enable its VBLANK and wait one, since the RSC hardware is driven
  1107. * by the primary panel's VBLANK signals
  1108. */
  1109. SDE_EVT32_VERBOSE(DRMID(drm_enc), wait_vblank_crtc_id);
  1110. if (ret) {
  1111. SDE_ERROR_ENC(sde_enc,
  1112. "sde rsc client update failed ret:%d\n", ret);
  1113. return ret;
  1114. } else if (wait_vblank_crtc_id == SDE_RSC_INVALID_CRTC_ID) {
  1115. return ret;
  1116. }
  1117. ret = _sde_encoder_rsc_client_update_vsync_wait(drm_enc,
  1118. sde_enc, wait_vblank_crtc_id);
  1119. return ret;
  1120. }
  1121. void sde_encoder_irq_control(struct drm_encoder *drm_enc, bool enable)
  1122. {
  1123. struct sde_encoder_virt *sde_enc;
  1124. int i;
  1125. if (!drm_enc) {
  1126. SDE_ERROR("invalid encoder\n");
  1127. return;
  1128. }
  1129. sde_enc = to_sde_encoder_virt(drm_enc);
  1130. SDE_DEBUG_ENC(sde_enc, "enable:%d\n", enable);
  1131. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1132. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  1133. if (phys && phys->ops.irq_control)
  1134. phys->ops.irq_control(phys, enable);
  1135. }
  1136. sde_kms_cpu_vote_for_irq(sde_encoder_get_kms(drm_enc), enable);
  1137. }
  1138. /* keep track of the userspace vblank during modeset */
  1139. static void _sde_encoder_modeset_helper_locked(struct drm_encoder *drm_enc,
  1140. u32 sw_event)
  1141. {
  1142. struct sde_encoder_virt *sde_enc;
  1143. bool enable;
  1144. int i;
  1145. if (!drm_enc) {
  1146. SDE_ERROR("invalid encoder\n");
  1147. return;
  1148. }
  1149. sde_enc = to_sde_encoder_virt(drm_enc);
  1150. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, vblank_enabled:%d\n",
  1151. sw_event, sde_enc->vblank_enabled);
  1152. /* nothing to do if vblank not enabled by userspace */
  1153. if (!sde_enc->vblank_enabled)
  1154. return;
  1155. /* disable vblank on pre_modeset */
  1156. if (sw_event == SDE_ENC_RC_EVENT_PRE_MODESET)
  1157. enable = false;
  1158. /* enable vblank on post_modeset */
  1159. else if (sw_event == SDE_ENC_RC_EVENT_POST_MODESET)
  1160. enable = true;
  1161. else
  1162. return;
  1163. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1164. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  1165. if (phys && phys->ops.control_vblank_irq)
  1166. phys->ops.control_vblank_irq(phys, enable);
  1167. }
  1168. }
  1169. struct sde_rsc_client *sde_encoder_get_rsc_client(struct drm_encoder *drm_enc)
  1170. {
  1171. struct sde_encoder_virt *sde_enc;
  1172. if (!drm_enc)
  1173. return NULL;
  1174. sde_enc = to_sde_encoder_virt(drm_enc);
  1175. return sde_enc->rsc_client;
  1176. }
  1177. static int _sde_encoder_resource_control_helper(struct drm_encoder *drm_enc,
  1178. bool enable)
  1179. {
  1180. struct sde_kms *sde_kms;
  1181. struct sde_encoder_virt *sde_enc;
  1182. int rc;
  1183. sde_enc = to_sde_encoder_virt(drm_enc);
  1184. sde_kms = sde_encoder_get_kms(drm_enc);
  1185. if (!sde_kms)
  1186. return -EINVAL;
  1187. SDE_DEBUG_ENC(sde_enc, "enable:%d\n", enable);
  1188. SDE_EVT32(DRMID(drm_enc), enable);
  1189. if (!sde_enc->cur_master) {
  1190. SDE_ERROR("encoder master not set\n");
  1191. return -EINVAL;
  1192. }
  1193. if (enable) {
  1194. /* enable SDE core clks */
  1195. rc = pm_runtime_get_sync(drm_enc->dev->dev);
  1196. if (rc < 0) {
  1197. SDE_ERROR("failed to enable power resource %d\n", rc);
  1198. SDE_EVT32(rc, SDE_EVTLOG_ERROR);
  1199. return rc;
  1200. }
  1201. sde_enc->elevated_ahb_vote = true;
  1202. /* enable DSI clks */
  1203. rc = sde_connector_clk_ctrl(sde_enc->cur_master->connector,
  1204. true);
  1205. if (rc) {
  1206. SDE_ERROR("failed to enable clk control %d\n", rc);
  1207. pm_runtime_put_sync(drm_enc->dev->dev);
  1208. return rc;
  1209. }
  1210. /* enable all the irq */
  1211. sde_encoder_irq_control(drm_enc, true);
  1212. _sde_encoder_pm_qos_add_request(drm_enc);
  1213. } else {
  1214. _sde_encoder_pm_qos_remove_request(drm_enc);
  1215. /* disable all the irq */
  1216. sde_encoder_irq_control(drm_enc, false);
  1217. /* disable DSI clks */
  1218. sde_connector_clk_ctrl(sde_enc->cur_master->connector, false);
  1219. /* disable SDE core clks */
  1220. pm_runtime_put_sync(drm_enc->dev->dev);
  1221. }
  1222. return 0;
  1223. }
  1224. static void sde_encoder_misr_configure(struct drm_encoder *drm_enc,
  1225. bool enable, u32 frame_count)
  1226. {
  1227. struct sde_encoder_virt *sde_enc;
  1228. int i;
  1229. if (!drm_enc) {
  1230. SDE_ERROR("invalid encoder\n");
  1231. return;
  1232. }
  1233. sde_enc = to_sde_encoder_virt(drm_enc);
  1234. if (!sde_enc->misr_reconfigure)
  1235. return;
  1236. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1237. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  1238. if (!phys || !phys->ops.setup_misr)
  1239. continue;
  1240. phys->ops.setup_misr(phys, enable, frame_count);
  1241. }
  1242. sde_enc->misr_reconfigure = false;
  1243. }
  1244. static void sde_encoder_input_event_handler(struct input_handle *handle,
  1245. unsigned int type, unsigned int code, int value)
  1246. {
  1247. struct drm_encoder *drm_enc = NULL;
  1248. struct sde_encoder_virt *sde_enc = NULL;
  1249. struct msm_drm_thread *disp_thread = NULL;
  1250. struct msm_drm_private *priv = NULL;
  1251. if (!handle || !handle->handler || !handle->handler->private) {
  1252. SDE_ERROR("invalid encoder for the input event\n");
  1253. return;
  1254. }
  1255. drm_enc = (struct drm_encoder *)handle->handler->private;
  1256. if (!drm_enc->dev || !drm_enc->dev->dev_private) {
  1257. SDE_ERROR("invalid parameters\n");
  1258. return;
  1259. }
  1260. priv = drm_enc->dev->dev_private;
  1261. sde_enc = to_sde_encoder_virt(drm_enc);
  1262. if (!sde_enc->crtc || (sde_enc->crtc->index
  1263. >= ARRAY_SIZE(priv->disp_thread))) {
  1264. SDE_DEBUG_ENC(sde_enc,
  1265. "invalid cached CRTC: %d or crtc index: %d\n",
  1266. sde_enc->crtc == NULL,
  1267. sde_enc->crtc ? sde_enc->crtc->index : -EINVAL);
  1268. return;
  1269. }
  1270. SDE_EVT32_VERBOSE(DRMID(drm_enc));
  1271. disp_thread = &priv->disp_thread[sde_enc->crtc->index];
  1272. kthread_queue_work(&disp_thread->worker,
  1273. &sde_enc->input_event_work);
  1274. }
  1275. void sde_encoder_control_idle_pc(struct drm_encoder *drm_enc, bool enable)
  1276. {
  1277. struct sde_encoder_virt *sde_enc;
  1278. if (!drm_enc) {
  1279. SDE_ERROR("invalid encoder\n");
  1280. return;
  1281. }
  1282. sde_enc = to_sde_encoder_virt(drm_enc);
  1283. /* return early if there is no state change */
  1284. if (sde_enc->idle_pc_enabled == enable)
  1285. return;
  1286. sde_enc->idle_pc_enabled = enable;
  1287. SDE_DEBUG("idle-pc state:%d\n", sde_enc->idle_pc_enabled);
  1288. SDE_EVT32(sde_enc->idle_pc_enabled);
  1289. }
  1290. static void _sde_encoder_rc_restart_delayed(struct sde_encoder_virt *sde_enc,
  1291. u32 sw_event)
  1292. {
  1293. struct drm_encoder *drm_enc = &sde_enc->base;
  1294. struct msm_drm_private *priv;
  1295. unsigned int lp, idle_pc_duration;
  1296. struct msm_drm_thread *disp_thread;
  1297. /* set idle timeout based on master connector's lp value */
  1298. if (sde_enc->cur_master)
  1299. lp = sde_connector_get_lp(
  1300. sde_enc->cur_master->connector);
  1301. else
  1302. lp = SDE_MODE_DPMS_ON;
  1303. if (lp == SDE_MODE_DPMS_LP2)
  1304. idle_pc_duration = IDLE_SHORT_TIMEOUT;
  1305. else
  1306. idle_pc_duration = IDLE_POWERCOLLAPSE_DURATION;
  1307. priv = drm_enc->dev->dev_private;
  1308. disp_thread = &priv->disp_thread[sde_enc->crtc->index];
  1309. kthread_mod_delayed_work(
  1310. &disp_thread->worker,
  1311. &sde_enc->delayed_off_work,
  1312. msecs_to_jiffies(idle_pc_duration));
  1313. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1314. idle_pc_duration, SDE_EVTLOG_FUNC_CASE2);
  1315. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, work scheduled\n",
  1316. sw_event);
  1317. }
  1318. static void _sde_encoder_rc_cancel_delayed(struct sde_encoder_virt *sde_enc,
  1319. u32 sw_event)
  1320. {
  1321. if (kthread_cancel_delayed_work_sync(
  1322. &sde_enc->delayed_off_work))
  1323. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, work cancelled\n",
  1324. sw_event);
  1325. }
  1326. static void _sde_encoder_rc_kickoff_delayed(struct sde_encoder_virt *sde_enc,
  1327. u32 sw_event)
  1328. {
  1329. if (_sde_encoder_is_autorefresh_enabled(sde_enc))
  1330. _sde_encoder_rc_cancel_delayed(sde_enc, sw_event);
  1331. else
  1332. _sde_encoder_rc_restart_delayed(sde_enc, sw_event);
  1333. }
  1334. static int _sde_encoder_rc_kickoff(struct drm_encoder *drm_enc,
  1335. u32 sw_event, struct sde_encoder_virt *sde_enc, bool is_vid_mode)
  1336. {
  1337. int ret = 0;
  1338. mutex_lock(&sde_enc->rc_lock);
  1339. /* return if the resource control is already in ON state */
  1340. if (sde_enc->rc_state == SDE_ENC_RC_STATE_ON) {
  1341. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc in ON state\n",
  1342. sw_event);
  1343. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1344. SDE_EVTLOG_FUNC_CASE1);
  1345. goto end;
  1346. } else if (sde_enc->rc_state != SDE_ENC_RC_STATE_OFF &&
  1347. sde_enc->rc_state != SDE_ENC_RC_STATE_IDLE) {
  1348. SDE_ERROR_ENC(sde_enc, "sw_event:%d, rc in state %d\n",
  1349. sw_event, sde_enc->rc_state);
  1350. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1351. SDE_EVTLOG_ERROR);
  1352. goto end;
  1353. }
  1354. if (is_vid_mode && sde_enc->rc_state == SDE_ENC_RC_STATE_IDLE) {
  1355. sde_encoder_irq_control(drm_enc, true);
  1356. } else {
  1357. /* enable all the clks and resources */
  1358. ret = _sde_encoder_resource_control_helper(drm_enc,
  1359. true);
  1360. if (ret) {
  1361. SDE_ERROR_ENC(sde_enc,
  1362. "sw_event:%d, rc in state %d\n",
  1363. sw_event, sde_enc->rc_state);
  1364. SDE_EVT32(DRMID(drm_enc), sw_event,
  1365. sde_enc->rc_state,
  1366. SDE_EVTLOG_ERROR);
  1367. goto end;
  1368. }
  1369. _sde_encoder_update_rsc_client(drm_enc, true);
  1370. }
  1371. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1372. SDE_ENC_RC_STATE_ON, SDE_EVTLOG_FUNC_CASE1);
  1373. sde_enc->rc_state = SDE_ENC_RC_STATE_ON;
  1374. end:
  1375. _sde_encoder_rc_kickoff_delayed(sde_enc, sw_event);
  1376. mutex_unlock(&sde_enc->rc_lock);
  1377. return ret;
  1378. }
  1379. static int _sde_encoder_rc_pre_stop(struct drm_encoder *drm_enc,
  1380. u32 sw_event, struct sde_encoder_virt *sde_enc, bool is_vid_mode)
  1381. {
  1382. /* cancel delayed off work, if any */
  1383. _sde_encoder_rc_cancel_delayed(sde_enc, sw_event);
  1384. mutex_lock(&sde_enc->rc_lock);
  1385. if (is_vid_mode &&
  1386. sde_enc->rc_state == SDE_ENC_RC_STATE_IDLE) {
  1387. sde_encoder_irq_control(drm_enc, true);
  1388. }
  1389. /* skip if is already OFF or IDLE, resources are off already */
  1390. else if (sde_enc->rc_state == SDE_ENC_RC_STATE_OFF ||
  1391. sde_enc->rc_state == SDE_ENC_RC_STATE_IDLE) {
  1392. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc in %d state\n",
  1393. sw_event, sde_enc->rc_state);
  1394. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1395. SDE_EVTLOG_FUNC_CASE3);
  1396. goto end;
  1397. }
  1398. /**
  1399. * IRQs are still enabled currently, which allows wait for
  1400. * VBLANK which RSC may require to correctly transition to OFF
  1401. */
  1402. _sde_encoder_update_rsc_client(drm_enc, false);
  1403. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1404. SDE_ENC_RC_STATE_PRE_OFF,
  1405. SDE_EVTLOG_FUNC_CASE3);
  1406. sde_enc->rc_state = SDE_ENC_RC_STATE_PRE_OFF;
  1407. end:
  1408. mutex_unlock(&sde_enc->rc_lock);
  1409. return 0;
  1410. }
  1411. static int _sde_encoder_rc_stop(struct drm_encoder *drm_enc,
  1412. u32 sw_event, struct sde_encoder_virt *sde_enc)
  1413. {
  1414. int ret = 0;
  1415. mutex_lock(&sde_enc->rc_lock);
  1416. /* return if the resource control is already in OFF state */
  1417. if (sde_enc->rc_state == SDE_ENC_RC_STATE_OFF) {
  1418. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc in OFF state\n",
  1419. sw_event);
  1420. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1421. SDE_EVTLOG_FUNC_CASE4);
  1422. goto end;
  1423. } else if (sde_enc->rc_state == SDE_ENC_RC_STATE_ON ||
  1424. sde_enc->rc_state == SDE_ENC_RC_STATE_MODESET) {
  1425. SDE_ERROR_ENC(sde_enc, "sw_event:%d, rc in state %d\n",
  1426. sw_event, sde_enc->rc_state);
  1427. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1428. SDE_EVTLOG_ERROR);
  1429. ret = -EINVAL;
  1430. goto end;
  1431. }
  1432. /**
  1433. * expect to arrive here only if in either idle state or pre-off
  1434. * and in IDLE state the resources are already disabled
  1435. */
  1436. if (sde_enc->rc_state == SDE_ENC_RC_STATE_PRE_OFF)
  1437. _sde_encoder_resource_control_helper(drm_enc, false);
  1438. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1439. SDE_ENC_RC_STATE_OFF, SDE_EVTLOG_FUNC_CASE4);
  1440. sde_enc->rc_state = SDE_ENC_RC_STATE_OFF;
  1441. end:
  1442. mutex_unlock(&sde_enc->rc_lock);
  1443. return ret;
  1444. }
  1445. static int _sde_encoder_rc_pre_modeset(struct drm_encoder *drm_enc,
  1446. u32 sw_event, struct sde_encoder_virt *sde_enc)
  1447. {
  1448. int ret = 0;
  1449. /* cancel delayed off work, if any */
  1450. _sde_encoder_rc_cancel_delayed(sde_enc, sw_event);
  1451. mutex_lock(&sde_enc->rc_lock);
  1452. if (sde_enc->rc_state == SDE_ENC_RC_STATE_OFF) {
  1453. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc in OFF state\n",
  1454. sw_event);
  1455. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1456. SDE_EVTLOG_FUNC_CASE5);
  1457. goto end;
  1458. } else if (sde_enc->rc_state != SDE_ENC_RC_STATE_ON) {
  1459. /* enable all the clks and resources */
  1460. ret = _sde_encoder_resource_control_helper(drm_enc,
  1461. true);
  1462. if (ret) {
  1463. SDE_ERROR_ENC(sde_enc,
  1464. "sw_event:%d, rc in state %d\n",
  1465. sw_event, sde_enc->rc_state);
  1466. SDE_EVT32(DRMID(drm_enc), sw_event,
  1467. sde_enc->rc_state,
  1468. SDE_EVTLOG_ERROR);
  1469. goto end;
  1470. }
  1471. _sde_encoder_update_rsc_client(drm_enc, true);
  1472. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1473. SDE_ENC_RC_STATE_ON, SDE_EVTLOG_FUNC_CASE5);
  1474. sde_enc->rc_state = SDE_ENC_RC_STATE_ON;
  1475. }
  1476. ret = sde_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE);
  1477. if (ret && ret != -EWOULDBLOCK) {
  1478. SDE_ERROR_ENC(sde_enc,
  1479. "wait for commit done returned %d\n",
  1480. ret);
  1481. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1482. ret, SDE_EVTLOG_ERROR);
  1483. ret = -EINVAL;
  1484. goto end;
  1485. }
  1486. sde_encoder_irq_control(drm_enc, false);
  1487. _sde_encoder_modeset_helper_locked(drm_enc, sw_event);
  1488. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1489. SDE_ENC_RC_STATE_MODESET, SDE_EVTLOG_FUNC_CASE5);
  1490. sde_enc->rc_state = SDE_ENC_RC_STATE_MODESET;
  1491. _sde_encoder_pm_qos_remove_request(drm_enc);
  1492. end:
  1493. mutex_unlock(&sde_enc->rc_lock);
  1494. return ret;
  1495. }
  1496. static int _sde_encoder_rc_post_modeset(struct drm_encoder *drm_enc,
  1497. u32 sw_event, struct sde_encoder_virt *sde_enc)
  1498. {
  1499. int ret = 0;
  1500. mutex_lock(&sde_enc->rc_lock);
  1501. if (sde_enc->rc_state == SDE_ENC_RC_STATE_OFF) {
  1502. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc in OFF state\n",
  1503. sw_event);
  1504. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1505. SDE_EVTLOG_FUNC_CASE5);
  1506. goto end;
  1507. } else if (sde_enc->rc_state != SDE_ENC_RC_STATE_MODESET) {
  1508. SDE_ERROR_ENC(sde_enc,
  1509. "sw_event:%d, rc:%d !MODESET state\n",
  1510. sw_event, sde_enc->rc_state);
  1511. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1512. SDE_EVTLOG_ERROR);
  1513. ret = -EINVAL;
  1514. goto end;
  1515. }
  1516. _sde_encoder_modeset_helper_locked(drm_enc, sw_event);
  1517. sde_encoder_irq_control(drm_enc, true);
  1518. _sde_encoder_update_rsc_client(drm_enc, true);
  1519. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1520. SDE_ENC_RC_STATE_ON, SDE_EVTLOG_FUNC_CASE6);
  1521. sde_enc->rc_state = SDE_ENC_RC_STATE_ON;
  1522. _sde_encoder_pm_qos_add_request(drm_enc);
  1523. end:
  1524. mutex_unlock(&sde_enc->rc_lock);
  1525. return ret;
  1526. }
  1527. static int _sde_encoder_rc_idle(struct drm_encoder *drm_enc,
  1528. u32 sw_event, struct sde_encoder_virt *sde_enc, bool is_vid_mode)
  1529. {
  1530. struct msm_drm_private *priv;
  1531. struct sde_kms *sde_kms;
  1532. struct drm_crtc *crtc = drm_enc->crtc;
  1533. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  1534. priv = drm_enc->dev->dev_private;
  1535. sde_kms = to_sde_kms(priv->kms);
  1536. mutex_lock(&sde_enc->rc_lock);
  1537. if (sde_enc->rc_state != SDE_ENC_RC_STATE_ON) {
  1538. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc:%d !ON state\n",
  1539. sw_event, sde_enc->rc_state);
  1540. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1541. SDE_EVTLOG_ERROR);
  1542. goto end;
  1543. } else if (sde_crtc_frame_pending(sde_enc->crtc)) {
  1544. SDE_DEBUG_ENC(sde_enc, "skip idle entry");
  1545. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1546. sde_crtc_frame_pending(sde_enc->crtc),
  1547. SDE_EVTLOG_ERROR);
  1548. _sde_encoder_rc_kickoff_delayed(sde_enc, sw_event);
  1549. goto end;
  1550. }
  1551. if (is_vid_mode) {
  1552. sde_encoder_irq_control(drm_enc, false);
  1553. } else {
  1554. /* disable all the clks and resources */
  1555. _sde_encoder_update_rsc_client(drm_enc, false);
  1556. _sde_encoder_resource_control_helper(drm_enc, false);
  1557. if (!sde_kms->perf.bw_vote_mode)
  1558. memset(&sde_crtc->cur_perf, 0,
  1559. sizeof(struct sde_core_perf_params));
  1560. }
  1561. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1562. SDE_ENC_RC_STATE_IDLE, SDE_EVTLOG_FUNC_CASE7);
  1563. sde_enc->rc_state = SDE_ENC_RC_STATE_IDLE;
  1564. end:
  1565. mutex_unlock(&sde_enc->rc_lock);
  1566. return 0;
  1567. }
  1568. static int _sde_encoder_rc_early_wakeup(struct drm_encoder *drm_enc,
  1569. u32 sw_event, struct sde_encoder_virt *sde_enc,
  1570. struct msm_drm_private *priv, bool is_vid_mode)
  1571. {
  1572. bool autorefresh_enabled = false;
  1573. struct msm_drm_thread *disp_thread;
  1574. int ret = 0;
  1575. if (!sde_enc->crtc ||
  1576. sde_enc->crtc->index >= ARRAY_SIZE(priv->disp_thread)) {
  1577. SDE_DEBUG_ENC(sde_enc,
  1578. "invalid crtc:%d or crtc index:%d , sw_event:%u\n",
  1579. sde_enc->crtc == NULL,
  1580. sde_enc->crtc ? sde_enc->crtc->index : -EINVAL,
  1581. sw_event);
  1582. return -EINVAL;
  1583. }
  1584. disp_thread = &priv->disp_thread[sde_enc->crtc->index];
  1585. mutex_lock(&sde_enc->rc_lock);
  1586. if (sde_enc->rc_state == SDE_ENC_RC_STATE_ON) {
  1587. if (sde_enc->cur_master &&
  1588. sde_enc->cur_master->ops.is_autorefresh_enabled)
  1589. autorefresh_enabled =
  1590. sde_enc->cur_master->ops.is_autorefresh_enabled(
  1591. sde_enc->cur_master);
  1592. if (autorefresh_enabled) {
  1593. SDE_DEBUG_ENC(sde_enc,
  1594. "not handling early wakeup since auto refresh is enabled\n");
  1595. goto end;
  1596. }
  1597. if (!sde_crtc_frame_pending(sde_enc->crtc))
  1598. kthread_mod_delayed_work(&disp_thread->worker,
  1599. &sde_enc->delayed_off_work,
  1600. msecs_to_jiffies(
  1601. IDLE_POWERCOLLAPSE_DURATION));
  1602. } else if (sde_enc->rc_state == SDE_ENC_RC_STATE_IDLE) {
  1603. /* enable all the clks and resources */
  1604. ret = _sde_encoder_resource_control_helper(drm_enc,
  1605. true);
  1606. if (ret) {
  1607. SDE_ERROR_ENC(sde_enc,
  1608. "sw_event:%d, rc in state %d\n",
  1609. sw_event, sde_enc->rc_state);
  1610. SDE_EVT32(DRMID(drm_enc), sw_event,
  1611. sde_enc->rc_state,
  1612. SDE_EVTLOG_ERROR);
  1613. goto end;
  1614. }
  1615. _sde_encoder_update_rsc_client(drm_enc, true);
  1616. /*
  1617. * In some cases, commit comes with slight delay
  1618. * (> 80 ms)after early wake up, prevent clock switch
  1619. * off to avoid jank in next update. So, increase the
  1620. * command mode idle timeout sufficiently to prevent
  1621. * such case.
  1622. */
  1623. kthread_mod_delayed_work(&disp_thread->worker,
  1624. &sde_enc->delayed_off_work,
  1625. msecs_to_jiffies(
  1626. IDLE_POWERCOLLAPSE_IN_EARLY_WAKEUP));
  1627. sde_enc->rc_state = SDE_ENC_RC_STATE_ON;
  1628. }
  1629. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1630. SDE_ENC_RC_STATE_ON, SDE_EVTLOG_FUNC_CASE8);
  1631. end:
  1632. mutex_unlock(&sde_enc->rc_lock);
  1633. return ret;
  1634. }
  1635. static int sde_encoder_resource_control(struct drm_encoder *drm_enc,
  1636. u32 sw_event)
  1637. {
  1638. struct sde_encoder_virt *sde_enc;
  1639. struct msm_drm_private *priv;
  1640. int ret = 0;
  1641. bool is_vid_mode = false;
  1642. if (!drm_enc || !drm_enc->dev || !drm_enc->dev->dev_private) {
  1643. SDE_ERROR("invalid encoder parameters, sw_event:%u\n",
  1644. sw_event);
  1645. return -EINVAL;
  1646. }
  1647. sde_enc = to_sde_encoder_virt(drm_enc);
  1648. priv = drm_enc->dev->dev_private;
  1649. if (sde_encoder_check_curr_mode(&sde_enc->base, MSM_DISPLAY_VIDEO_MODE))
  1650. is_vid_mode = true;
  1651. /*
  1652. * when idle_pc is not supported, process only KICKOFF, STOP and MODESET
  1653. * events and return early for other events (ie wb display).
  1654. */
  1655. if (!sde_enc->idle_pc_enabled &&
  1656. (sw_event != SDE_ENC_RC_EVENT_KICKOFF &&
  1657. sw_event != SDE_ENC_RC_EVENT_PRE_MODESET &&
  1658. sw_event != SDE_ENC_RC_EVENT_POST_MODESET &&
  1659. sw_event != SDE_ENC_RC_EVENT_STOP &&
  1660. sw_event != SDE_ENC_RC_EVENT_PRE_STOP))
  1661. return 0;
  1662. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, idle_pc:%d\n",
  1663. sw_event, sde_enc->idle_pc_enabled);
  1664. SDE_EVT32_VERBOSE(DRMID(drm_enc), sw_event, sde_enc->idle_pc_enabled,
  1665. sde_enc->rc_state, SDE_EVTLOG_FUNC_ENTRY);
  1666. switch (sw_event) {
  1667. case SDE_ENC_RC_EVENT_KICKOFF:
  1668. ret = _sde_encoder_rc_kickoff(drm_enc, sw_event, sde_enc,
  1669. is_vid_mode);
  1670. break;
  1671. case SDE_ENC_RC_EVENT_PRE_STOP:
  1672. ret = _sde_encoder_rc_pre_stop(drm_enc, sw_event, sde_enc,
  1673. is_vid_mode);
  1674. break;
  1675. case SDE_ENC_RC_EVENT_STOP:
  1676. ret = _sde_encoder_rc_stop(drm_enc, sw_event, sde_enc);
  1677. break;
  1678. case SDE_ENC_RC_EVENT_PRE_MODESET:
  1679. ret = _sde_encoder_rc_pre_modeset(drm_enc, sw_event, sde_enc);
  1680. break;
  1681. case SDE_ENC_RC_EVENT_POST_MODESET:
  1682. ret = _sde_encoder_rc_post_modeset(drm_enc, sw_event, sde_enc);
  1683. break;
  1684. case SDE_ENC_RC_EVENT_ENTER_IDLE:
  1685. ret = _sde_encoder_rc_idle(drm_enc, sw_event, sde_enc,
  1686. is_vid_mode);
  1687. break;
  1688. case SDE_ENC_RC_EVENT_EARLY_WAKEUP:
  1689. ret = _sde_encoder_rc_early_wakeup(drm_enc, sw_event, sde_enc,
  1690. priv, is_vid_mode);
  1691. break;
  1692. default:
  1693. SDE_EVT32(DRMID(drm_enc), sw_event, SDE_EVTLOG_ERROR);
  1694. SDE_ERROR("unexpected sw_event: %d\n", sw_event);
  1695. break;
  1696. }
  1697. SDE_EVT32_VERBOSE(DRMID(drm_enc), sw_event, sde_enc->idle_pc_enabled,
  1698. sde_enc->rc_state, SDE_EVTLOG_FUNC_EXIT);
  1699. return ret;
  1700. }
  1701. static void sde_encoder_virt_mode_switch(struct drm_encoder *drm_enc,
  1702. enum sde_intf_mode intf_mode, struct drm_display_mode *adj_mode)
  1703. {
  1704. int i = 0;
  1705. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  1706. if (intf_mode == INTF_MODE_CMD)
  1707. sde_enc->disp_info.curr_panel_mode = MSM_DISPLAY_VIDEO_MODE;
  1708. else if (intf_mode == INTF_MODE_VIDEO)
  1709. sde_enc->disp_info.curr_panel_mode = MSM_DISPLAY_CMD_MODE;
  1710. _sde_encoder_update_rsc_client(drm_enc, true);
  1711. if (intf_mode == INTF_MODE_CMD) {
  1712. for (i = 0; i < sde_enc->num_phys_encs; i++)
  1713. sde_enc->phys_encs[i] = sde_enc->phys_vid_encs[i];
  1714. SDE_DEBUG_ENC(sde_enc, "switch to video physical encoder\n");
  1715. SDE_EVT32(DRMID(&sde_enc->base), intf_mode,
  1716. msm_is_mode_seamless_poms(adj_mode),
  1717. SDE_EVTLOG_FUNC_CASE1);
  1718. } else if (intf_mode == INTF_MODE_VIDEO) {
  1719. for (i = 0; i < sde_enc->num_phys_encs; i++)
  1720. sde_enc->phys_encs[i] = sde_enc->phys_cmd_encs[i];
  1721. SDE_EVT32(DRMID(&sde_enc->base), intf_mode,
  1722. msm_is_mode_seamless_poms(adj_mode),
  1723. SDE_EVTLOG_FUNC_CASE2);
  1724. SDE_DEBUG_ENC(sde_enc, "switch to command physical encoder\n");
  1725. }
  1726. }
  1727. static struct drm_connector *_sde_encoder_get_connector(
  1728. struct drm_device *dev, struct drm_encoder *drm_enc)
  1729. {
  1730. struct drm_connector_list_iter conn_iter;
  1731. struct drm_connector *conn = NULL, *conn_search;
  1732. drm_connector_list_iter_begin(dev, &conn_iter);
  1733. drm_for_each_connector_iter(conn_search, &conn_iter) {
  1734. if (conn_search->encoder == drm_enc) {
  1735. conn = conn_search;
  1736. break;
  1737. }
  1738. }
  1739. drm_connector_list_iter_end(&conn_iter);
  1740. return conn;
  1741. }
  1742. static void _sde_encoder_virt_populate_hw_res(struct drm_encoder *drm_enc)
  1743. {
  1744. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  1745. struct sde_kms *sde_kms = sde_encoder_get_kms(drm_enc);
  1746. struct sde_rm_hw_iter pp_iter, qdss_iter;
  1747. struct sde_rm_hw_iter dsc_iter, vdc_iter;
  1748. struct sde_rm_hw_request request_hw;
  1749. int i, j;
  1750. sde_rm_init_hw_iter(&pp_iter, drm_enc->base.id, SDE_HW_BLK_PINGPONG);
  1751. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  1752. sde_enc->hw_pp[i] = NULL;
  1753. if (!sde_rm_get_hw(&sde_kms->rm, &pp_iter))
  1754. break;
  1755. sde_enc->hw_pp[i] = (struct sde_hw_pingpong *) pp_iter.hw;
  1756. }
  1757. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1758. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  1759. if (phys) {
  1760. sde_rm_init_hw_iter(&qdss_iter, drm_enc->base.id,
  1761. SDE_HW_BLK_QDSS);
  1762. for (j = 0; j < QDSS_MAX; j++) {
  1763. if (sde_rm_get_hw(&sde_kms->rm, &qdss_iter)) {
  1764. phys->hw_qdss =
  1765. (struct sde_hw_qdss *)qdss_iter.hw;
  1766. break;
  1767. }
  1768. }
  1769. }
  1770. }
  1771. sde_rm_init_hw_iter(&dsc_iter, drm_enc->base.id, SDE_HW_BLK_DSC);
  1772. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  1773. sde_enc->hw_dsc[i] = NULL;
  1774. if (!sde_rm_get_hw(&sde_kms->rm, &dsc_iter))
  1775. break;
  1776. sde_enc->hw_dsc[i] = (struct sde_hw_dsc *) dsc_iter.hw;
  1777. }
  1778. sde_rm_init_hw_iter(&vdc_iter, drm_enc->base.id, SDE_HW_BLK_VDC);
  1779. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  1780. sde_enc->hw_vdc[i] = NULL;
  1781. if (!sde_rm_get_hw(&sde_kms->rm, &vdc_iter))
  1782. break;
  1783. sde_enc->hw_vdc[i] = (struct sde_hw_vdc *) vdc_iter.hw;
  1784. }
  1785. /* Get PP for DSC configuration */
  1786. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  1787. struct sde_hw_pingpong *pp = NULL;
  1788. unsigned long features = 0;
  1789. if (!sde_enc->hw_dsc[i])
  1790. continue;
  1791. request_hw.id = sde_enc->hw_dsc[i]->base.id;
  1792. request_hw.type = SDE_HW_BLK_PINGPONG;
  1793. if (!sde_rm_request_hw_blk(&sde_kms->rm, &request_hw))
  1794. break;
  1795. pp = (struct sde_hw_pingpong *) request_hw.hw;
  1796. features = pp->ops.get_hw_caps(pp);
  1797. if (test_bit(SDE_PINGPONG_DSC, &features))
  1798. sde_enc->hw_dsc_pp[i] = pp;
  1799. else
  1800. sde_enc->hw_dsc_pp[i] = NULL;
  1801. }
  1802. }
  1803. static int sde_encoder_virt_modeset_rc(struct drm_encoder *drm_enc,
  1804. struct drm_display_mode *adj_mode, bool pre_modeset)
  1805. {
  1806. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  1807. enum sde_intf_mode intf_mode;
  1808. int ret;
  1809. bool is_cmd_mode = false;
  1810. if (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE))
  1811. is_cmd_mode = true;
  1812. if (pre_modeset) {
  1813. intf_mode = sde_encoder_get_intf_mode(drm_enc);
  1814. if (msm_is_mode_seamless_dms(adj_mode) ||
  1815. (msm_is_mode_seamless_dyn_clk(adj_mode) &&
  1816. is_cmd_mode)) {
  1817. /* restore resource state before releasing them */
  1818. ret = sde_encoder_resource_control(drm_enc,
  1819. SDE_ENC_RC_EVENT_PRE_MODESET);
  1820. if (ret) {
  1821. SDE_ERROR_ENC(sde_enc,
  1822. "sde resource control failed: %d\n",
  1823. ret);
  1824. return ret;
  1825. }
  1826. /*
  1827. * Disable dce before switching the mode and after pre-
  1828. * modeset to guarantee previous kickoff has finished.
  1829. */
  1830. sde_encoder_dce_disable(sde_enc);
  1831. } else if (msm_is_mode_seamless_poms(adj_mode)) {
  1832. _sde_encoder_modeset_helper_locked(drm_enc,
  1833. SDE_ENC_RC_EVENT_PRE_MODESET);
  1834. sde_encoder_virt_mode_switch(drm_enc, intf_mode,
  1835. adj_mode);
  1836. }
  1837. } else {
  1838. if (msm_is_mode_seamless_dms(adj_mode) ||
  1839. (msm_is_mode_seamless_dyn_clk(adj_mode) &&
  1840. is_cmd_mode))
  1841. sde_encoder_resource_control(&sde_enc->base,
  1842. SDE_ENC_RC_EVENT_POST_MODESET);
  1843. else if (msm_is_mode_seamless_poms(adj_mode))
  1844. _sde_encoder_modeset_helper_locked(drm_enc,
  1845. SDE_ENC_RC_EVENT_POST_MODESET);
  1846. }
  1847. return 0;
  1848. }
  1849. static void sde_encoder_virt_mode_set(struct drm_encoder *drm_enc,
  1850. struct drm_display_mode *mode,
  1851. struct drm_display_mode *adj_mode)
  1852. {
  1853. struct sde_encoder_virt *sde_enc;
  1854. struct sde_kms *sde_kms;
  1855. struct drm_connector *conn;
  1856. int i = 0, ret;
  1857. int num_lm, num_intf, num_pp_per_intf;
  1858. if (!drm_enc) {
  1859. SDE_ERROR("invalid encoder\n");
  1860. return;
  1861. }
  1862. if (!sde_kms_power_resource_is_enabled(drm_enc->dev)) {
  1863. SDE_ERROR("power resource is not enabled\n");
  1864. return;
  1865. }
  1866. sde_kms = sde_encoder_get_kms(drm_enc);
  1867. if (!sde_kms)
  1868. return;
  1869. sde_enc = to_sde_encoder_virt(drm_enc);
  1870. SDE_DEBUG_ENC(sde_enc, "\n");
  1871. SDE_EVT32(DRMID(drm_enc));
  1872. /*
  1873. * cache the crtc in sde_enc on enable for duration of use case
  1874. * for correctly servicing asynchronous irq events and timers
  1875. */
  1876. if (!drm_enc->crtc) {
  1877. SDE_ERROR("invalid crtc\n");
  1878. return;
  1879. }
  1880. sde_enc->crtc = drm_enc->crtc;
  1881. sde_crtc_set_qos_dirty(drm_enc->crtc);
  1882. /* get and store the mode_info */
  1883. conn = _sde_encoder_get_connector(sde_kms->dev, drm_enc);
  1884. if (!conn) {
  1885. SDE_ERROR_ENC(sde_enc, "failed to find attached connector\n");
  1886. return;
  1887. } else if (!conn->state) {
  1888. SDE_ERROR_ENC(sde_enc, "invalid connector state\n");
  1889. return;
  1890. }
  1891. sde_connector_state_get_mode_info(conn->state, &sde_enc->mode_info);
  1892. sde_encoder_dce_set_bpp(sde_enc->mode_info, sde_enc->crtc);
  1893. /* release resources before seamless mode change */
  1894. ret = sde_encoder_virt_modeset_rc(drm_enc, adj_mode, true);
  1895. if (ret)
  1896. return;
  1897. /* reserve dynamic resources now, indicating non test-only */
  1898. ret = sde_rm_reserve(&sde_kms->rm, drm_enc, drm_enc->crtc->state,
  1899. conn->state, false);
  1900. if (ret) {
  1901. SDE_ERROR_ENC(sde_enc,
  1902. "failed to reserve hw resources, %d\n", ret);
  1903. return;
  1904. }
  1905. /* assign the reserved HW blocks to this encoder */
  1906. _sde_encoder_virt_populate_hw_res(drm_enc);
  1907. /* determine left HW PP block to map to INTF */
  1908. num_lm = sde_enc->mode_info.topology.num_lm;
  1909. num_intf = sde_enc->mode_info.topology.num_intf;
  1910. num_pp_per_intf = num_lm / num_intf;
  1911. if (!num_pp_per_intf)
  1912. num_pp_per_intf = 1;
  1913. /* perform mode_set on phys_encs */
  1914. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1915. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  1916. if (phys) {
  1917. if (!sde_enc->hw_pp[i * num_pp_per_intf] &&
  1918. sde_enc->topology.num_intf) {
  1919. SDE_ERROR_ENC(sde_enc, "invalid hw_pp[%d]\n",
  1920. i * num_pp_per_intf);
  1921. return;
  1922. }
  1923. phys->hw_pp = sde_enc->hw_pp[i * num_pp_per_intf];
  1924. phys->connector = conn->state->connector;
  1925. if (phys->ops.mode_set)
  1926. phys->ops.mode_set(phys, mode, adj_mode);
  1927. }
  1928. }
  1929. /* update resources after seamless mode change */
  1930. sde_encoder_virt_modeset_rc(drm_enc, adj_mode, false);
  1931. }
  1932. void sde_encoder_control_te(struct drm_encoder *drm_enc, bool enable)
  1933. {
  1934. struct sde_encoder_virt *sde_enc;
  1935. struct sde_encoder_phys *phys;
  1936. int i;
  1937. if (!drm_enc) {
  1938. SDE_ERROR("invalid parameters\n");
  1939. return;
  1940. }
  1941. sde_enc = to_sde_encoder_virt(drm_enc);
  1942. if (!sde_enc) {
  1943. SDE_ERROR("invalid sde encoder\n");
  1944. return;
  1945. }
  1946. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1947. phys = sde_enc->phys_encs[i];
  1948. if (phys && phys->ops.control_te)
  1949. phys->ops.control_te(phys, enable);
  1950. }
  1951. }
  1952. static int _sde_encoder_input_connect(struct input_handler *handler,
  1953. struct input_dev *dev, const struct input_device_id *id)
  1954. {
  1955. struct input_handle *handle;
  1956. int rc = 0;
  1957. handle = kzalloc(sizeof(*handle), GFP_KERNEL);
  1958. if (!handle)
  1959. return -ENOMEM;
  1960. handle->dev = dev;
  1961. handle->handler = handler;
  1962. handle->name = handler->name;
  1963. rc = input_register_handle(handle);
  1964. if (rc) {
  1965. pr_err("failed to register input handle\n");
  1966. goto error;
  1967. }
  1968. rc = input_open_device(handle);
  1969. if (rc) {
  1970. pr_err("failed to open input device\n");
  1971. goto error_unregister;
  1972. }
  1973. return 0;
  1974. error_unregister:
  1975. input_unregister_handle(handle);
  1976. error:
  1977. kfree(handle);
  1978. return rc;
  1979. }
  1980. static void _sde_encoder_input_disconnect(struct input_handle *handle)
  1981. {
  1982. input_close_device(handle);
  1983. input_unregister_handle(handle);
  1984. kfree(handle);
  1985. }
  1986. /**
  1987. * Structure for specifying event parameters on which to receive callbacks.
  1988. * This structure will trigger a callback in case of a touch event (specified by
  1989. * EV_ABS) where there is a change in X and Y coordinates,
  1990. */
  1991. static const struct input_device_id sde_input_ids[] = {
  1992. {
  1993. .flags = INPUT_DEVICE_ID_MATCH_EVBIT,
  1994. .evbit = { BIT_MASK(EV_ABS) },
  1995. .absbit = { [BIT_WORD(ABS_MT_POSITION_X)] =
  1996. BIT_MASK(ABS_MT_POSITION_X) |
  1997. BIT_MASK(ABS_MT_POSITION_Y) },
  1998. },
  1999. { },
  2000. };
  2001. static void _sde_encoder_input_handler_register(
  2002. struct drm_encoder *drm_enc)
  2003. {
  2004. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  2005. int rc;
  2006. if (!sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE))
  2007. return;
  2008. if (sde_enc->input_handler && !sde_enc->input_handler->private) {
  2009. sde_enc->input_handler->private = sde_enc;
  2010. /* register input handler if not already registered */
  2011. rc = input_register_handler(sde_enc->input_handler);
  2012. if (rc) {
  2013. SDE_ERROR("input_handler_register failed, rc= %d\n",
  2014. rc);
  2015. kfree(sde_enc->input_handler);
  2016. }
  2017. }
  2018. }
  2019. static void _sde_encoder_input_handler_unregister(
  2020. struct drm_encoder *drm_enc)
  2021. {
  2022. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  2023. if (!sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE))
  2024. return;
  2025. if (sde_enc->input_handler && sde_enc->input_handler->private) {
  2026. input_unregister_handler(sde_enc->input_handler);
  2027. sde_enc->input_handler->private = NULL;
  2028. }
  2029. }
  2030. static int _sde_encoder_input_handler(
  2031. struct sde_encoder_virt *sde_enc)
  2032. {
  2033. struct input_handler *input_handler = NULL;
  2034. int rc = 0;
  2035. if (sde_enc->input_handler) {
  2036. SDE_ERROR_ENC(sde_enc,
  2037. "input_handle is active. unexpected\n");
  2038. return -EINVAL;
  2039. }
  2040. input_handler = kzalloc(sizeof(*sde_enc->input_handler), GFP_KERNEL);
  2041. if (!input_handler)
  2042. return -ENOMEM;
  2043. input_handler->event = sde_encoder_input_event_handler;
  2044. input_handler->connect = _sde_encoder_input_connect;
  2045. input_handler->disconnect = _sde_encoder_input_disconnect;
  2046. input_handler->name = "sde";
  2047. input_handler->id_table = sde_input_ids;
  2048. sde_enc->input_handler = input_handler;
  2049. return rc;
  2050. }
  2051. static void _sde_encoder_virt_enable_helper(struct drm_encoder *drm_enc)
  2052. {
  2053. struct sde_encoder_virt *sde_enc = NULL;
  2054. struct sde_kms *sde_kms;
  2055. if (!drm_enc || !drm_enc->dev || !drm_enc->dev->dev_private) {
  2056. SDE_ERROR("invalid parameters\n");
  2057. return;
  2058. }
  2059. sde_kms = sde_encoder_get_kms(drm_enc);
  2060. if (!sde_kms)
  2061. return;
  2062. sde_enc = to_sde_encoder_virt(drm_enc);
  2063. if (!sde_enc || !sde_enc->cur_master) {
  2064. SDE_DEBUG("invalid sde encoder/master\n");
  2065. return;
  2066. }
  2067. if (sde_enc->disp_info.intf_type == DRM_MODE_CONNECTOR_DisplayPort &&
  2068. sde_enc->cur_master->hw_mdptop &&
  2069. sde_enc->cur_master->hw_mdptop->ops.intf_audio_select)
  2070. sde_enc->cur_master->hw_mdptop->ops.intf_audio_select(
  2071. sde_enc->cur_master->hw_mdptop);
  2072. if (sde_enc->cur_master->hw_mdptop &&
  2073. sde_enc->cur_master->hw_mdptop->ops.reset_ubwc)
  2074. sde_enc->cur_master->hw_mdptop->ops.reset_ubwc(
  2075. sde_enc->cur_master->hw_mdptop,
  2076. sde_kms->catalog);
  2077. if (sde_enc->cur_master->hw_ctl &&
  2078. sde_enc->cur_master->hw_ctl->ops.setup_intf_cfg_v1 &&
  2079. !sde_enc->cur_master->cont_splash_enabled)
  2080. sde_enc->cur_master->hw_ctl->ops.setup_intf_cfg_v1(
  2081. sde_enc->cur_master->hw_ctl,
  2082. &sde_enc->cur_master->intf_cfg_v1);
  2083. _sde_encoder_update_vsync_source(sde_enc, &sde_enc->disp_info, false);
  2084. sde_encoder_control_te(drm_enc, true);
  2085. memset(&sde_enc->prv_conn_roi, 0, sizeof(sde_enc->prv_conn_roi));
  2086. memset(&sde_enc->cur_conn_roi, 0, sizeof(sde_enc->cur_conn_roi));
  2087. }
  2088. static void _sde_encoder_setup_dither(struct sde_encoder_phys *phys)
  2089. {
  2090. struct sde_kms *sde_kms;
  2091. void *dither_cfg = NULL;
  2092. int ret = 0, i = 0;
  2093. size_t len = 0;
  2094. enum sde_rm_topology_name topology;
  2095. struct drm_encoder *drm_enc;
  2096. struct msm_display_dsc_info *dsc = NULL;
  2097. struct sde_encoder_virt *sde_enc;
  2098. struct sde_hw_pingpong *hw_pp;
  2099. u32 bpp, bpc;
  2100. int num_lm;
  2101. if (!phys || !phys->connector || !phys->hw_pp ||
  2102. !phys->hw_pp->ops.setup_dither || !phys->parent)
  2103. return;
  2104. sde_kms = sde_encoder_get_kms(phys->parent);
  2105. if (!sde_kms)
  2106. return;
  2107. topology = sde_connector_get_topology_name(phys->connector);
  2108. if ((topology == SDE_RM_TOPOLOGY_PPSPLIT) &&
  2109. (phys->split_role == ENC_ROLE_SLAVE))
  2110. return;
  2111. drm_enc = phys->parent;
  2112. sde_enc = to_sde_encoder_virt(drm_enc);
  2113. dsc = &sde_enc->mode_info.comp_info.dsc_info;
  2114. bpc = dsc->config.bits_per_component;
  2115. bpp = dsc->config.bits_per_pixel;
  2116. /* disable dither for 10 bpp or 10bpc dsc config */
  2117. if (bpp == 10 || bpc == 10) {
  2118. phys->hw_pp->ops.setup_dither(phys->hw_pp, NULL, 0);
  2119. return;
  2120. }
  2121. ret = sde_connector_get_dither_cfg(phys->connector,
  2122. phys->connector->state, &dither_cfg,
  2123. &len, sde_enc->idle_pc_restore);
  2124. /* skip reg writes when return values are invalid or no data */
  2125. if (ret && ret == -ENODATA)
  2126. return;
  2127. num_lm = sde_rm_topology_get_num_lm(&sde_kms->rm, topology);
  2128. for (i = 0; i < num_lm; i++) {
  2129. hw_pp = sde_enc->hw_pp[i];
  2130. phys->hw_pp->ops.setup_dither(hw_pp,
  2131. dither_cfg, len);
  2132. }
  2133. }
  2134. void sde_encoder_virt_restore(struct drm_encoder *drm_enc)
  2135. {
  2136. struct sde_encoder_virt *sde_enc = NULL;
  2137. int i;
  2138. if (!drm_enc) {
  2139. SDE_ERROR("invalid encoder\n");
  2140. return;
  2141. }
  2142. sde_enc = to_sde_encoder_virt(drm_enc);
  2143. if (!sde_enc->cur_master) {
  2144. SDE_DEBUG("virt encoder has no master\n");
  2145. return;
  2146. }
  2147. memset(&sde_enc->cur_master->intf_cfg_v1, 0,
  2148. sizeof(sde_enc->cur_master->intf_cfg_v1));
  2149. sde_enc->idle_pc_restore = true;
  2150. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2151. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2152. if (!phys)
  2153. continue;
  2154. if (phys->hw_ctl && phys->hw_ctl->ops.clear_pending_flush)
  2155. phys->hw_ctl->ops.clear_pending_flush(phys->hw_ctl);
  2156. if ((phys != sde_enc->cur_master) && phys->ops.restore)
  2157. phys->ops.restore(phys);
  2158. _sde_encoder_setup_dither(phys);
  2159. }
  2160. if (sde_enc->cur_master->ops.restore)
  2161. sde_enc->cur_master->ops.restore(sde_enc->cur_master);
  2162. _sde_encoder_virt_enable_helper(drm_enc);
  2163. }
  2164. static void sde_encoder_off_work(struct kthread_work *work)
  2165. {
  2166. struct sde_encoder_virt *sde_enc = container_of(work,
  2167. struct sde_encoder_virt, delayed_off_work.work);
  2168. struct drm_encoder *drm_enc;
  2169. if (!sde_enc) {
  2170. SDE_ERROR("invalid sde encoder\n");
  2171. return;
  2172. }
  2173. drm_enc = &sde_enc->base;
  2174. SDE_ATRACE_BEGIN("sde_encoder_off_work");
  2175. sde_encoder_idle_request(drm_enc);
  2176. SDE_ATRACE_END("sde_encoder_off_work");
  2177. }
  2178. static void sde_encoder_virt_enable(struct drm_encoder *drm_enc)
  2179. {
  2180. struct sde_encoder_virt *sde_enc = NULL;
  2181. int i, ret = 0;
  2182. struct msm_compression_info *comp_info = NULL;
  2183. struct drm_display_mode *cur_mode = NULL;
  2184. struct msm_display_info *disp_info;
  2185. if (!drm_enc || !drm_enc->crtc) {
  2186. SDE_ERROR("invalid encoder\n");
  2187. return;
  2188. }
  2189. sde_enc = to_sde_encoder_virt(drm_enc);
  2190. disp_info = &sde_enc->disp_info;
  2191. if (!sde_kms_power_resource_is_enabled(drm_enc->dev)) {
  2192. SDE_ERROR("power resource is not enabled\n");
  2193. return;
  2194. }
  2195. if (!sde_enc->crtc)
  2196. sde_enc->crtc = drm_enc->crtc;
  2197. comp_info = &sde_enc->mode_info.comp_info;
  2198. cur_mode = &sde_enc->base.crtc->state->adjusted_mode;
  2199. SDE_DEBUG_ENC(sde_enc, "\n");
  2200. SDE_EVT32(DRMID(drm_enc), cur_mode->hdisplay, cur_mode->vdisplay);
  2201. sde_enc->cur_master = NULL;
  2202. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2203. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2204. if (phys && phys->ops.is_master && phys->ops.is_master(phys)) {
  2205. SDE_DEBUG_ENC(sde_enc, "master is now idx %d\n", i);
  2206. sde_enc->cur_master = phys;
  2207. break;
  2208. }
  2209. }
  2210. if (!sde_enc->cur_master) {
  2211. SDE_ERROR("virt encoder has no master! num_phys %d\n", i);
  2212. return;
  2213. }
  2214. _sde_encoder_input_handler_register(drm_enc);
  2215. if ((drm_enc->crtc->state->connectors_changed &&
  2216. sde_encoder_in_clone_mode(drm_enc)) ||
  2217. !(msm_is_mode_seamless_vrr(cur_mode)
  2218. || msm_is_mode_seamless_dms(cur_mode)
  2219. || msm_is_mode_seamless_dyn_clk(cur_mode)))
  2220. kthread_init_delayed_work(&sde_enc->delayed_off_work,
  2221. sde_encoder_off_work);
  2222. ret = sde_encoder_resource_control(drm_enc, SDE_ENC_RC_EVENT_KICKOFF);
  2223. if (ret) {
  2224. SDE_ERROR_ENC(sde_enc, "sde resource control failed: %d\n",
  2225. ret);
  2226. return;
  2227. }
  2228. memset(&sde_enc->cur_master->intf_cfg_v1, 0,
  2229. sizeof(sde_enc->cur_master->intf_cfg_v1));
  2230. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2231. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2232. if (!phys)
  2233. continue;
  2234. phys->comp_type = comp_info->comp_type;
  2235. phys->comp_ratio = comp_info->comp_ratio;
  2236. phys->frame_trigger_mode = sde_enc->frame_trigger_mode;
  2237. phys->poms_align_vsync = disp_info->poms_align_vsync;
  2238. if (phys->comp_type == MSM_DISPLAY_COMPRESSION_DSC) {
  2239. phys->dsc_extra_pclk_cycle_cnt =
  2240. comp_info->dsc_info.pclk_per_line;
  2241. phys->dsc_extra_disp_width =
  2242. comp_info->dsc_info.extra_width;
  2243. phys->dce_bytes_per_line =
  2244. comp_info->dsc_info.bytes_per_pkt *
  2245. comp_info->dsc_info.pkt_per_line;
  2246. } else if (phys->comp_type == MSM_DISPLAY_COMPRESSION_VDC) {
  2247. phys->dce_bytes_per_line =
  2248. comp_info->vdc_info.bytes_per_pkt *
  2249. comp_info->vdc_info.pkt_per_line;
  2250. }
  2251. if (phys != sde_enc->cur_master) {
  2252. /**
  2253. * on DMS request, the encoder will be enabled
  2254. * already. Invoke restore to reconfigure the
  2255. * new mode.
  2256. */
  2257. if ((msm_is_mode_seamless_dms(cur_mode) ||
  2258. msm_is_mode_seamless_dyn_clk(cur_mode)) &&
  2259. phys->ops.restore)
  2260. phys->ops.restore(phys);
  2261. else if (phys->ops.enable)
  2262. phys->ops.enable(phys);
  2263. }
  2264. if (sde_enc->misr_enable && phys->ops.setup_misr &&
  2265. (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_VIDEO_MODE)))
  2266. phys->ops.setup_misr(phys, true,
  2267. sde_enc->misr_frame_count);
  2268. }
  2269. if ((msm_is_mode_seamless_dms(cur_mode) ||
  2270. msm_is_mode_seamless_dyn_clk(cur_mode)) &&
  2271. sde_enc->cur_master->ops.restore)
  2272. sde_enc->cur_master->ops.restore(sde_enc->cur_master);
  2273. else if (sde_enc->cur_master->ops.enable)
  2274. sde_enc->cur_master->ops.enable(sde_enc->cur_master);
  2275. _sde_encoder_virt_enable_helper(drm_enc);
  2276. }
  2277. static void sde_encoder_virt_disable(struct drm_encoder *drm_enc)
  2278. {
  2279. struct sde_encoder_virt *sde_enc = NULL;
  2280. struct sde_kms *sde_kms;
  2281. enum sde_intf_mode intf_mode;
  2282. int i = 0;
  2283. if (!drm_enc) {
  2284. SDE_ERROR("invalid encoder\n");
  2285. return;
  2286. } else if (!drm_enc->dev) {
  2287. SDE_ERROR("invalid dev\n");
  2288. return;
  2289. } else if (!drm_enc->dev->dev_private) {
  2290. SDE_ERROR("invalid dev_private\n");
  2291. return;
  2292. }
  2293. if (!sde_kms_power_resource_is_enabled(drm_enc->dev)) {
  2294. SDE_ERROR("power resource is not enabled\n");
  2295. return;
  2296. }
  2297. sde_enc = to_sde_encoder_virt(drm_enc);
  2298. SDE_DEBUG_ENC(sde_enc, "\n");
  2299. sde_kms = sde_encoder_get_kms(&sde_enc->base);
  2300. if (!sde_kms)
  2301. return;
  2302. intf_mode = sde_encoder_get_intf_mode(drm_enc);
  2303. SDE_EVT32(DRMID(drm_enc));
  2304. /* wait for idle */
  2305. sde_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE);
  2306. _sde_encoder_input_handler_unregister(drm_enc);
  2307. /*
  2308. * For primary command mode and video mode encoders, execute the
  2309. * resource control pre-stop operations before the physical encoders
  2310. * are disabled, to allow the rsc to transition its states properly.
  2311. *
  2312. * For other encoder types, rsc should not be enabled until after
  2313. * they have been fully disabled, so delay the pre-stop operations
  2314. * until after the physical disable calls have returned.
  2315. */
  2316. if (sde_enc->disp_info.display_type == SDE_CONNECTOR_PRIMARY &&
  2317. (intf_mode == INTF_MODE_CMD || intf_mode == INTF_MODE_VIDEO)) {
  2318. sde_encoder_resource_control(drm_enc,
  2319. SDE_ENC_RC_EVENT_PRE_STOP);
  2320. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2321. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2322. if (phys && phys->ops.disable)
  2323. phys->ops.disable(phys);
  2324. }
  2325. } else {
  2326. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2327. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2328. if (phys && phys->ops.disable)
  2329. phys->ops.disable(phys);
  2330. }
  2331. sde_encoder_resource_control(drm_enc,
  2332. SDE_ENC_RC_EVENT_PRE_STOP);
  2333. }
  2334. /*
  2335. * disable dce after the transfer is complete (for command mode)
  2336. * and after physical encoder is disabled, to make sure timing
  2337. * engine is already disabled (for video mode).
  2338. */
  2339. if (!sde_in_trusted_vm(sde_kms))
  2340. sde_encoder_dce_disable(sde_enc);
  2341. sde_encoder_resource_control(drm_enc, SDE_ENC_RC_EVENT_STOP);
  2342. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2343. if (sde_enc->phys_encs[i]) {
  2344. sde_enc->phys_encs[i]->cont_splash_enabled = false;
  2345. sde_enc->phys_encs[i]->connector = NULL;
  2346. }
  2347. atomic_set(&sde_enc->frame_done_cnt[i], 0);
  2348. }
  2349. sde_enc->cur_master = NULL;
  2350. /*
  2351. * clear the cached crtc in sde_enc on use case finish, after all the
  2352. * outstanding events and timers have been completed
  2353. */
  2354. sde_enc->crtc = NULL;
  2355. memset(&sde_enc->mode_info, 0, sizeof(sde_enc->mode_info));
  2356. SDE_DEBUG_ENC(sde_enc, "encoder disabled\n");
  2357. sde_rm_release(&sde_kms->rm, drm_enc, false);
  2358. }
  2359. void sde_encoder_helper_phys_disable(struct sde_encoder_phys *phys_enc,
  2360. struct sde_encoder_phys_wb *wb_enc)
  2361. {
  2362. struct sde_encoder_virt *sde_enc;
  2363. phys_enc->hw_ctl->ops.reset(phys_enc->hw_ctl);
  2364. sde_encoder_helper_reset_mixers(phys_enc, NULL);
  2365. if (wb_enc) {
  2366. if (wb_enc->hw_wb->ops.bind_pingpong_blk) {
  2367. wb_enc->hw_wb->ops.bind_pingpong_blk(wb_enc->hw_wb,
  2368. false, phys_enc->hw_pp->idx);
  2369. if (phys_enc->hw_ctl->ops.update_bitmask)
  2370. phys_enc->hw_ctl->ops.update_bitmask(
  2371. phys_enc->hw_ctl,
  2372. SDE_HW_FLUSH_WB,
  2373. wb_enc->hw_wb->idx, true);
  2374. }
  2375. } else {
  2376. if (phys_enc->hw_intf->ops.bind_pingpong_blk) {
  2377. phys_enc->hw_intf->ops.bind_pingpong_blk(
  2378. phys_enc->hw_intf, false,
  2379. phys_enc->hw_pp->idx);
  2380. if (phys_enc->hw_ctl->ops.update_bitmask)
  2381. phys_enc->hw_ctl->ops.update_bitmask(
  2382. phys_enc->hw_ctl,
  2383. SDE_HW_FLUSH_INTF,
  2384. phys_enc->hw_intf->idx, true);
  2385. }
  2386. }
  2387. if (phys_enc->hw_pp && phys_enc->hw_pp->ops.reset_3d_mode) {
  2388. phys_enc->hw_pp->ops.reset_3d_mode(phys_enc->hw_pp);
  2389. if (phys_enc->hw_ctl->ops.update_bitmask &&
  2390. phys_enc->hw_pp->merge_3d)
  2391. phys_enc->hw_ctl->ops.update_bitmask(
  2392. phys_enc->hw_ctl, SDE_HW_FLUSH_MERGE_3D,
  2393. phys_enc->hw_pp->merge_3d->idx, true);
  2394. }
  2395. if (phys_enc->hw_cdm && phys_enc->hw_cdm->ops.bind_pingpong_blk &&
  2396. phys_enc->hw_pp) {
  2397. phys_enc->hw_cdm->ops.bind_pingpong_blk(phys_enc->hw_cdm,
  2398. false, phys_enc->hw_pp->idx);
  2399. if (phys_enc->hw_ctl->ops.update_bitmask)
  2400. phys_enc->hw_ctl->ops.update_bitmask(
  2401. phys_enc->hw_ctl, SDE_HW_FLUSH_CDM,
  2402. phys_enc->hw_cdm->idx, true);
  2403. }
  2404. sde_enc = to_sde_encoder_virt(phys_enc->parent);
  2405. if (phys_enc == sde_enc->cur_master && phys_enc->hw_pp &&
  2406. phys_enc->hw_ctl->ops.reset_post_disable)
  2407. phys_enc->hw_ctl->ops.reset_post_disable(
  2408. phys_enc->hw_ctl, &phys_enc->intf_cfg_v1,
  2409. phys_enc->hw_pp->merge_3d ?
  2410. phys_enc->hw_pp->merge_3d->idx : 0);
  2411. phys_enc->hw_ctl->ops.trigger_flush(phys_enc->hw_ctl);
  2412. phys_enc->hw_ctl->ops.trigger_start(phys_enc->hw_ctl);
  2413. }
  2414. static enum sde_intf sde_encoder_get_intf(struct sde_mdss_cfg *catalog,
  2415. enum sde_intf_type type, u32 controller_id)
  2416. {
  2417. int i = 0;
  2418. for (i = 0; i < catalog->intf_count; i++) {
  2419. if (catalog->intf[i].type == type
  2420. && catalog->intf[i].controller_id == controller_id) {
  2421. return catalog->intf[i].id;
  2422. }
  2423. }
  2424. return INTF_MAX;
  2425. }
  2426. static enum sde_wb sde_encoder_get_wb(struct sde_mdss_cfg *catalog,
  2427. enum sde_intf_type type, u32 controller_id)
  2428. {
  2429. if (controller_id < catalog->wb_count)
  2430. return catalog->wb[controller_id].id;
  2431. return WB_MAX;
  2432. }
  2433. void sde_encoder_perf_uidle_status(struct sde_kms *sde_kms,
  2434. struct drm_crtc *crtc)
  2435. {
  2436. struct sde_hw_uidle *uidle;
  2437. struct sde_uidle_cntr cntr;
  2438. struct sde_uidle_status status;
  2439. if (!sde_kms || !crtc || !sde_kms->hw_uidle) {
  2440. pr_err("invalid params %d %d\n",
  2441. !sde_kms, !crtc);
  2442. return;
  2443. }
  2444. /* check if perf counters are enabled and setup */
  2445. if (!sde_kms->catalog->uidle_cfg.perf_cntr_en)
  2446. return;
  2447. uidle = sde_kms->hw_uidle;
  2448. if ((sde_kms->catalog->uidle_cfg.debugfs_perf & SDE_PERF_UIDLE_STATUS)
  2449. && uidle->ops.uidle_get_status) {
  2450. uidle->ops.uidle_get_status(uidle, &status);
  2451. trace_sde_perf_uidle_status(
  2452. crtc->base.id,
  2453. status.uidle_danger_status_0,
  2454. status.uidle_danger_status_1,
  2455. status.uidle_safe_status_0,
  2456. status.uidle_safe_status_1,
  2457. status.uidle_idle_status_0,
  2458. status.uidle_idle_status_1,
  2459. status.uidle_fal_status_0,
  2460. status.uidle_fal_status_1,
  2461. status.uidle_status,
  2462. status.uidle_en_fal10);
  2463. }
  2464. if ((sde_kms->catalog->uidle_cfg.debugfs_perf & SDE_PERF_UIDLE_CNT)
  2465. && uidle->ops.uidle_get_cntr) {
  2466. uidle->ops.uidle_get_cntr(uidle, &cntr);
  2467. trace_sde_perf_uidle_cntr(
  2468. crtc->base.id,
  2469. cntr.fal1_gate_cntr,
  2470. cntr.fal10_gate_cntr,
  2471. cntr.fal_wait_gate_cntr,
  2472. cntr.fal1_num_transitions_cntr,
  2473. cntr.fal10_num_transitions_cntr,
  2474. cntr.min_gate_cntr,
  2475. cntr.max_gate_cntr);
  2476. }
  2477. }
  2478. static void sde_encoder_vblank_callback(struct drm_encoder *drm_enc,
  2479. struct sde_encoder_phys *phy_enc)
  2480. {
  2481. struct sde_encoder_virt *sde_enc = NULL;
  2482. unsigned long lock_flags;
  2483. if (!drm_enc || !phy_enc)
  2484. return;
  2485. SDE_ATRACE_BEGIN("encoder_vblank_callback");
  2486. sde_enc = to_sde_encoder_virt(drm_enc);
  2487. spin_lock_irqsave(&sde_enc->enc_spinlock, lock_flags);
  2488. if (sde_enc->crtc_vblank_cb)
  2489. sde_enc->crtc_vblank_cb(sde_enc->crtc_vblank_cb_data);
  2490. spin_unlock_irqrestore(&sde_enc->enc_spinlock, lock_flags);
  2491. if (phy_enc->sde_kms &&
  2492. phy_enc->sde_kms->catalog->uidle_cfg.debugfs_perf)
  2493. sde_encoder_perf_uidle_status(phy_enc->sde_kms, sde_enc->crtc);
  2494. atomic_inc(&phy_enc->vsync_cnt);
  2495. SDE_ATRACE_END("encoder_vblank_callback");
  2496. }
  2497. static void sde_encoder_underrun_callback(struct drm_encoder *drm_enc,
  2498. struct sde_encoder_phys *phy_enc)
  2499. {
  2500. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  2501. if (!phy_enc)
  2502. return;
  2503. SDE_ATRACE_BEGIN("encoder_underrun_callback");
  2504. atomic_inc(&phy_enc->underrun_cnt);
  2505. SDE_EVT32(DRMID(drm_enc), atomic_read(&phy_enc->underrun_cnt));
  2506. if (sde_enc->cur_master->ops.get_underrun_line_count)
  2507. sde_enc->cur_master->ops.get_underrun_line_count(
  2508. sde_enc->cur_master);
  2509. trace_sde_encoder_underrun(DRMID(drm_enc),
  2510. atomic_read(&phy_enc->underrun_cnt));
  2511. SDE_DBG_CTRL("stop_ftrace");
  2512. SDE_DBG_CTRL("panic_underrun");
  2513. SDE_ATRACE_END("encoder_underrun_callback");
  2514. }
  2515. void sde_encoder_register_vblank_callback(struct drm_encoder *drm_enc,
  2516. void (*vbl_cb)(void *), void *vbl_data)
  2517. {
  2518. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  2519. unsigned long lock_flags;
  2520. bool enable;
  2521. int i;
  2522. enable = vbl_cb ? true : false;
  2523. if (!drm_enc) {
  2524. SDE_ERROR("invalid encoder\n");
  2525. return;
  2526. }
  2527. SDE_DEBUG_ENC(sde_enc, "\n");
  2528. SDE_EVT32(DRMID(drm_enc), enable);
  2529. if (sde_encoder_in_clone_mode(drm_enc)) {
  2530. SDE_EVT32(DRMID(drm_enc), SDE_EVTLOG_ERROR);
  2531. return;
  2532. }
  2533. spin_lock_irqsave(&sde_enc->enc_spinlock, lock_flags);
  2534. sde_enc->crtc_vblank_cb = vbl_cb;
  2535. sde_enc->crtc_vblank_cb_data = vbl_data;
  2536. spin_unlock_irqrestore(&sde_enc->enc_spinlock, lock_flags);
  2537. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2538. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2539. if (phys && phys->ops.control_vblank_irq)
  2540. phys->ops.control_vblank_irq(phys, enable);
  2541. }
  2542. sde_enc->vblank_enabled = enable;
  2543. }
  2544. void sde_encoder_register_frame_event_callback(struct drm_encoder *drm_enc,
  2545. void (*frame_event_cb)(void *, u32 event),
  2546. struct drm_crtc *crtc)
  2547. {
  2548. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  2549. unsigned long lock_flags;
  2550. bool enable;
  2551. enable = frame_event_cb ? true : false;
  2552. if (!drm_enc) {
  2553. SDE_ERROR("invalid encoder\n");
  2554. return;
  2555. }
  2556. SDE_DEBUG_ENC(sde_enc, "\n");
  2557. SDE_EVT32(DRMID(drm_enc), enable, 0);
  2558. spin_lock_irqsave(&sde_enc->enc_spinlock, lock_flags);
  2559. sde_enc->crtc_frame_event_cb = frame_event_cb;
  2560. sde_enc->crtc_frame_event_cb_data.crtc = crtc;
  2561. spin_unlock_irqrestore(&sde_enc->enc_spinlock, lock_flags);
  2562. }
  2563. static void sde_encoder_frame_done_callback(
  2564. struct drm_encoder *drm_enc,
  2565. struct sde_encoder_phys *ready_phys, u32 event)
  2566. {
  2567. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  2568. unsigned int i;
  2569. bool trigger = true;
  2570. bool is_cmd_mode = false;
  2571. enum sde_rm_topology_name topology = SDE_RM_TOPOLOGY_NONE;
  2572. if (!drm_enc || !sde_enc->cur_master) {
  2573. SDE_ERROR("invalid param: drm_enc %pK, cur_master %pK\n",
  2574. drm_enc, drm_enc ? sde_enc->cur_master : 0);
  2575. return;
  2576. }
  2577. sde_enc->crtc_frame_event_cb_data.connector =
  2578. sde_enc->cur_master->connector;
  2579. if (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE))
  2580. is_cmd_mode = true;
  2581. if (event & (SDE_ENCODER_FRAME_EVENT_DONE
  2582. | SDE_ENCODER_FRAME_EVENT_ERROR
  2583. | SDE_ENCODER_FRAME_EVENT_PANEL_DEAD) && is_cmd_mode) {
  2584. if (ready_phys->connector)
  2585. topology = sde_connector_get_topology_name(
  2586. ready_phys->connector);
  2587. /* One of the physical encoders has become idle */
  2588. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2589. if (sde_enc->phys_encs[i] == ready_phys) {
  2590. SDE_EVT32_VERBOSE(DRMID(drm_enc), i,
  2591. atomic_read(&sde_enc->frame_done_cnt[i]));
  2592. if (!atomic_add_unless(
  2593. &sde_enc->frame_done_cnt[i], 1, 2)) {
  2594. SDE_EVT32(DRMID(drm_enc), event,
  2595. ready_phys->intf_idx,
  2596. SDE_EVTLOG_ERROR);
  2597. SDE_ERROR_ENC(sde_enc,
  2598. "intf idx:%d, event:%d\n",
  2599. ready_phys->intf_idx, event);
  2600. return;
  2601. }
  2602. }
  2603. if (topology != SDE_RM_TOPOLOGY_PPSPLIT &&
  2604. atomic_read(&sde_enc->frame_done_cnt[i]) == 0)
  2605. trigger = false;
  2606. }
  2607. if (trigger) {
  2608. if (sde_enc->crtc_frame_event_cb)
  2609. sde_enc->crtc_frame_event_cb(
  2610. &sde_enc->crtc_frame_event_cb_data,
  2611. event);
  2612. for (i = 0; i < sde_enc->num_phys_encs; i++)
  2613. atomic_add_unless(&sde_enc->frame_done_cnt[i],
  2614. -1, 0);
  2615. }
  2616. } else if (sde_enc->crtc_frame_event_cb) {
  2617. sde_enc->crtc_frame_event_cb(
  2618. &sde_enc->crtc_frame_event_cb_data, event);
  2619. }
  2620. }
  2621. static void sde_encoder_get_qsync_fps_callback(
  2622. struct drm_encoder *drm_enc,
  2623. u32 *qsync_fps)
  2624. {
  2625. struct msm_display_info *disp_info;
  2626. struct sde_encoder_virt *sde_enc;
  2627. if (!qsync_fps)
  2628. return;
  2629. *qsync_fps = 0;
  2630. if (!drm_enc) {
  2631. SDE_ERROR("invalid drm encoder\n");
  2632. return;
  2633. }
  2634. sde_enc = to_sde_encoder_virt(drm_enc);
  2635. disp_info = &sde_enc->disp_info;
  2636. *qsync_fps = disp_info->qsync_min_fps;
  2637. }
  2638. int sde_encoder_idle_request(struct drm_encoder *drm_enc)
  2639. {
  2640. struct sde_encoder_virt *sde_enc;
  2641. if (!drm_enc) {
  2642. SDE_ERROR("invalid drm encoder\n");
  2643. return -EINVAL;
  2644. }
  2645. sde_enc = to_sde_encoder_virt(drm_enc);
  2646. sde_encoder_resource_control(&sde_enc->base,
  2647. SDE_ENC_RC_EVENT_ENTER_IDLE);
  2648. return 0;
  2649. }
  2650. /**
  2651. * _sde_encoder_trigger_flush - trigger flush for a physical encoder
  2652. * drm_enc: Pointer to drm encoder structure
  2653. * phys: Pointer to physical encoder structure
  2654. * extra_flush: Additional bit mask to include in flush trigger
  2655. */
  2656. static inline void _sde_encoder_trigger_flush(struct drm_encoder *drm_enc,
  2657. struct sde_encoder_phys *phys,
  2658. struct sde_ctl_flush_cfg *extra_flush)
  2659. {
  2660. struct sde_hw_ctl *ctl;
  2661. unsigned long lock_flags;
  2662. struct sde_encoder_virt *sde_enc;
  2663. int pend_ret_fence_cnt;
  2664. struct sde_connector *c_conn;
  2665. if (!drm_enc || !phys) {
  2666. SDE_ERROR("invalid argument(s), drm_enc %d, phys_enc %d\n",
  2667. !drm_enc, !phys);
  2668. return;
  2669. }
  2670. sde_enc = to_sde_encoder_virt(drm_enc);
  2671. c_conn = to_sde_connector(phys->connector);
  2672. if (!phys->hw_pp) {
  2673. SDE_ERROR("invalid pingpong hw\n");
  2674. return;
  2675. }
  2676. ctl = phys->hw_ctl;
  2677. if (!ctl || !phys->ops.trigger_flush) {
  2678. SDE_ERROR("missing ctl/trigger cb\n");
  2679. return;
  2680. }
  2681. if (phys->split_role == ENC_ROLE_SKIP) {
  2682. SDE_DEBUG_ENC(to_sde_encoder_virt(phys->parent),
  2683. "skip flush pp%d ctl%d\n",
  2684. phys->hw_pp->idx - PINGPONG_0,
  2685. ctl->idx - CTL_0);
  2686. return;
  2687. }
  2688. /* update pending counts and trigger kickoff ctl flush atomically */
  2689. spin_lock_irqsave(&sde_enc->enc_spinlock, lock_flags);
  2690. if (phys->ops.is_master && phys->ops.is_master(phys))
  2691. atomic_inc(&phys->pending_retire_fence_cnt);
  2692. pend_ret_fence_cnt = atomic_read(&phys->pending_retire_fence_cnt);
  2693. if (phys->hw_intf && phys->hw_intf->cap->type == INTF_DP &&
  2694. ctl->ops.update_bitmask) {
  2695. /* perform peripheral flush on every frame update for dp dsc */
  2696. if (phys->comp_type == MSM_DISPLAY_COMPRESSION_DSC &&
  2697. phys->comp_ratio && c_conn->ops.update_pps) {
  2698. c_conn->ops.update_pps(phys->connector, NULL,
  2699. c_conn->display);
  2700. ctl->ops.update_bitmask(ctl, SDE_HW_FLUSH_PERIPH,
  2701. phys->hw_intf->idx, 1);
  2702. }
  2703. if (sde_enc->dynamic_hdr_updated)
  2704. ctl->ops.update_bitmask(ctl, SDE_HW_FLUSH_PERIPH,
  2705. phys->hw_intf->idx, 1);
  2706. }
  2707. if ((extra_flush && extra_flush->pending_flush_mask)
  2708. && ctl->ops.update_pending_flush)
  2709. ctl->ops.update_pending_flush(ctl, extra_flush);
  2710. phys->ops.trigger_flush(phys);
  2711. spin_unlock_irqrestore(&sde_enc->enc_spinlock, lock_flags);
  2712. if (ctl->ops.get_pending_flush) {
  2713. struct sde_ctl_flush_cfg pending_flush = {0,};
  2714. ctl->ops.get_pending_flush(ctl, &pending_flush);
  2715. SDE_EVT32(DRMID(drm_enc), phys->intf_idx - INTF_0,
  2716. ctl->idx - CTL_0,
  2717. pending_flush.pending_flush_mask,
  2718. pend_ret_fence_cnt);
  2719. } else {
  2720. SDE_EVT32(DRMID(drm_enc), phys->intf_idx - INTF_0,
  2721. ctl->idx - CTL_0,
  2722. pend_ret_fence_cnt);
  2723. }
  2724. }
  2725. /**
  2726. * _sde_encoder_trigger_start - trigger start for a physical encoder
  2727. * phys: Pointer to physical encoder structure
  2728. */
  2729. static inline void _sde_encoder_trigger_start(struct sde_encoder_phys *phys)
  2730. {
  2731. struct sde_hw_ctl *ctl;
  2732. struct sde_encoder_virt *sde_enc;
  2733. if (!phys) {
  2734. SDE_ERROR("invalid argument(s)\n");
  2735. return;
  2736. }
  2737. if (!phys->hw_pp) {
  2738. SDE_ERROR("invalid pingpong hw\n");
  2739. return;
  2740. }
  2741. if (!phys->parent) {
  2742. SDE_ERROR("invalid parent\n");
  2743. return;
  2744. }
  2745. /* avoid ctrl start for encoder in clone mode */
  2746. if (phys->in_clone_mode)
  2747. return;
  2748. ctl = phys->hw_ctl;
  2749. sde_enc = to_sde_encoder_virt(phys->parent);
  2750. if (phys->split_role == ENC_ROLE_SKIP) {
  2751. SDE_DEBUG_ENC(sde_enc,
  2752. "skip start pp%d ctl%d\n",
  2753. phys->hw_pp->idx - PINGPONG_0,
  2754. ctl->idx - CTL_0);
  2755. return;
  2756. }
  2757. if (phys->ops.trigger_start && phys->enable_state != SDE_ENC_DISABLED)
  2758. phys->ops.trigger_start(phys);
  2759. }
  2760. void sde_encoder_helper_trigger_flush(struct sde_encoder_phys *phys_enc)
  2761. {
  2762. struct sde_hw_ctl *ctl;
  2763. if (!phys_enc) {
  2764. SDE_ERROR("invalid encoder\n");
  2765. return;
  2766. }
  2767. ctl = phys_enc->hw_ctl;
  2768. if (ctl && ctl->ops.trigger_flush)
  2769. ctl->ops.trigger_flush(ctl);
  2770. }
  2771. void sde_encoder_helper_trigger_start(struct sde_encoder_phys *phys_enc)
  2772. {
  2773. struct sde_hw_ctl *ctl;
  2774. if (!phys_enc) {
  2775. SDE_ERROR("invalid encoder\n");
  2776. return;
  2777. }
  2778. ctl = phys_enc->hw_ctl;
  2779. if (ctl && ctl->ops.trigger_start) {
  2780. ctl->ops.trigger_start(ctl);
  2781. SDE_EVT32(DRMID(phys_enc->parent), ctl->idx - CTL_0);
  2782. }
  2783. }
  2784. void sde_encoder_helper_hw_reset(struct sde_encoder_phys *phys_enc)
  2785. {
  2786. struct sde_encoder_virt *sde_enc;
  2787. struct sde_connector *sde_con;
  2788. void *sde_con_disp;
  2789. struct sde_hw_ctl *ctl;
  2790. int rc;
  2791. if (!phys_enc) {
  2792. SDE_ERROR("invalid encoder\n");
  2793. return;
  2794. }
  2795. sde_enc = to_sde_encoder_virt(phys_enc->parent);
  2796. ctl = phys_enc->hw_ctl;
  2797. if (!ctl || !ctl->ops.reset)
  2798. return;
  2799. SDE_DEBUG_ENC(sde_enc, "ctl %d reset\n", ctl->idx);
  2800. SDE_EVT32(DRMID(phys_enc->parent), ctl->idx);
  2801. if (phys_enc->ops.is_master && phys_enc->ops.is_master(phys_enc) &&
  2802. phys_enc->connector) {
  2803. sde_con = to_sde_connector(phys_enc->connector);
  2804. sde_con_disp = sde_connector_get_display(phys_enc->connector);
  2805. if (sde_con->ops.soft_reset) {
  2806. rc = sde_con->ops.soft_reset(sde_con_disp);
  2807. if (rc) {
  2808. SDE_ERROR_ENC(sde_enc,
  2809. "connector soft reset failure\n");
  2810. SDE_DBG_DUMP("all", "dbg_bus", "vbif_dbg_bus",
  2811. "panic");
  2812. }
  2813. }
  2814. }
  2815. phys_enc->enable_state = SDE_ENC_ENABLED;
  2816. }
  2817. /**
  2818. * _sde_encoder_kickoff_phys - handle physical encoder kickoff
  2819. * Iterate through the physical encoders and perform consolidated flush
  2820. * and/or control start triggering as needed. This is done in the virtual
  2821. * encoder rather than the individual physical ones in order to handle
  2822. * use cases that require visibility into multiple physical encoders at
  2823. * a time.
  2824. * sde_enc: Pointer to virtual encoder structure
  2825. */
  2826. static void _sde_encoder_kickoff_phys(struct sde_encoder_virt *sde_enc)
  2827. {
  2828. struct sde_hw_ctl *ctl;
  2829. uint32_t i;
  2830. struct sde_ctl_flush_cfg pending_flush = {0,};
  2831. u32 pending_kickoff_cnt;
  2832. struct msm_drm_private *priv = NULL;
  2833. struct sde_kms *sde_kms = NULL;
  2834. struct sde_crtc_misr_info crtc_misr_info = {false, 0};
  2835. bool is_regdma_blocking = false, is_vid_mode = false;
  2836. if (!sde_enc) {
  2837. SDE_ERROR("invalid encoder\n");
  2838. return;
  2839. }
  2840. if (sde_encoder_check_curr_mode(&sde_enc->base, MSM_DISPLAY_VIDEO_MODE))
  2841. is_vid_mode = true;
  2842. is_regdma_blocking = (is_vid_mode ||
  2843. _sde_encoder_is_autorefresh_enabled(sde_enc));
  2844. /* don't perform flush/start operations for slave encoders */
  2845. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2846. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2847. enum sde_rm_topology_name topology = SDE_RM_TOPOLOGY_NONE;
  2848. if (!phys || phys->enable_state == SDE_ENC_DISABLED)
  2849. continue;
  2850. ctl = phys->hw_ctl;
  2851. if (!ctl)
  2852. continue;
  2853. if (phys->connector)
  2854. topology = sde_connector_get_topology_name(
  2855. phys->connector);
  2856. if (!phys->ops.needs_single_flush ||
  2857. !phys->ops.needs_single_flush(phys)) {
  2858. if (ctl->ops.reg_dma_flush)
  2859. ctl->ops.reg_dma_flush(ctl, is_regdma_blocking);
  2860. _sde_encoder_trigger_flush(&sde_enc->base, phys, 0x0);
  2861. } else if (ctl->ops.get_pending_flush) {
  2862. ctl->ops.get_pending_flush(ctl, &pending_flush);
  2863. }
  2864. }
  2865. /* for split flush, combine pending flush masks and send to master */
  2866. if (pending_flush.pending_flush_mask && sde_enc->cur_master) {
  2867. ctl = sde_enc->cur_master->hw_ctl;
  2868. if (ctl->ops.reg_dma_flush)
  2869. ctl->ops.reg_dma_flush(ctl, is_regdma_blocking);
  2870. _sde_encoder_trigger_flush(&sde_enc->base, sde_enc->cur_master,
  2871. &pending_flush);
  2872. }
  2873. /* update pending_kickoff_cnt AFTER flush but before trigger start */
  2874. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2875. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2876. if (!phys || phys->enable_state == SDE_ENC_DISABLED)
  2877. continue;
  2878. if (!phys->ops.needs_single_flush ||
  2879. !phys->ops.needs_single_flush(phys)) {
  2880. pending_kickoff_cnt =
  2881. sde_encoder_phys_inc_pending(phys);
  2882. SDE_EVT32(pending_kickoff_cnt, SDE_EVTLOG_FUNC_CASE1);
  2883. } else {
  2884. pending_kickoff_cnt =
  2885. sde_encoder_phys_inc_pending(phys);
  2886. SDE_EVT32(pending_kickoff_cnt,
  2887. pending_flush.pending_flush_mask,
  2888. SDE_EVTLOG_FUNC_CASE2);
  2889. }
  2890. }
  2891. if (sde_enc->misr_enable)
  2892. sde_encoder_misr_configure(&sde_enc->base, true,
  2893. sde_enc->misr_frame_count);
  2894. sde_crtc_get_misr_info(sde_enc->crtc, &crtc_misr_info);
  2895. if (crtc_misr_info.misr_enable)
  2896. sde_crtc_misr_setup(sde_enc->crtc, true,
  2897. crtc_misr_info.misr_frame_count);
  2898. _sde_encoder_trigger_start(sde_enc->cur_master);
  2899. if (sde_enc->elevated_ahb_vote) {
  2900. sde_kms = sde_encoder_get_kms(&sde_enc->base);
  2901. priv = sde_enc->base.dev->dev_private;
  2902. if (sde_kms != NULL) {
  2903. sde_power_scale_reg_bus(&priv->phandle,
  2904. VOTE_INDEX_LOW,
  2905. false);
  2906. }
  2907. sde_enc->elevated_ahb_vote = false;
  2908. }
  2909. }
  2910. static void _sde_encoder_ppsplit_swap_intf_for_right_only_update(
  2911. struct drm_encoder *drm_enc,
  2912. unsigned long *affected_displays,
  2913. int num_active_phys)
  2914. {
  2915. struct sde_encoder_virt *sde_enc;
  2916. struct sde_encoder_phys *master;
  2917. enum sde_rm_topology_name topology;
  2918. bool is_right_only;
  2919. if (!drm_enc || !affected_displays)
  2920. return;
  2921. sde_enc = to_sde_encoder_virt(drm_enc);
  2922. master = sde_enc->cur_master;
  2923. if (!master || !master->connector)
  2924. return;
  2925. topology = sde_connector_get_topology_name(master->connector);
  2926. if (topology != SDE_RM_TOPOLOGY_PPSPLIT)
  2927. return;
  2928. /*
  2929. * For pingpong split, the slave pingpong won't generate IRQs. For
  2930. * right-only updates, we can't swap pingpongs, or simply swap the
  2931. * master/slave assignment, we actually have to swap the interfaces
  2932. * so that the master physical encoder will use a pingpong/interface
  2933. * that generates irqs on which to wait.
  2934. */
  2935. is_right_only = !test_bit(0, affected_displays) &&
  2936. test_bit(1, affected_displays);
  2937. if (is_right_only && !sde_enc->intfs_swapped) {
  2938. /* right-only update swap interfaces */
  2939. swap(sde_enc->phys_encs[0]->intf_idx,
  2940. sde_enc->phys_encs[1]->intf_idx);
  2941. sde_enc->intfs_swapped = true;
  2942. } else if (!is_right_only && sde_enc->intfs_swapped) {
  2943. /* left-only or full update, swap back */
  2944. swap(sde_enc->phys_encs[0]->intf_idx,
  2945. sde_enc->phys_encs[1]->intf_idx);
  2946. sde_enc->intfs_swapped = false;
  2947. }
  2948. SDE_DEBUG_ENC(sde_enc,
  2949. "right_only %d swapped %d phys0->intf%d, phys1->intf%d\n",
  2950. is_right_only, sde_enc->intfs_swapped,
  2951. sde_enc->phys_encs[0]->intf_idx - INTF_0,
  2952. sde_enc->phys_encs[1]->intf_idx - INTF_0);
  2953. SDE_EVT32(DRMID(drm_enc), is_right_only, sde_enc->intfs_swapped,
  2954. sde_enc->phys_encs[0]->intf_idx - INTF_0,
  2955. sde_enc->phys_encs[1]->intf_idx - INTF_0,
  2956. *affected_displays);
  2957. /* ppsplit always uses master since ppslave invalid for irqs*/
  2958. if (num_active_phys == 1)
  2959. *affected_displays = BIT(0);
  2960. }
  2961. static void _sde_encoder_update_master(struct drm_encoder *drm_enc,
  2962. struct sde_encoder_kickoff_params *params)
  2963. {
  2964. struct sde_encoder_virt *sde_enc;
  2965. struct sde_encoder_phys *phys;
  2966. int i, num_active_phys;
  2967. bool master_assigned = false;
  2968. if (!drm_enc || !params)
  2969. return;
  2970. sde_enc = to_sde_encoder_virt(drm_enc);
  2971. if (sde_enc->num_phys_encs <= 1)
  2972. return;
  2973. /* count bits set */
  2974. num_active_phys = hweight_long(params->affected_displays);
  2975. SDE_DEBUG_ENC(sde_enc, "affected_displays 0x%lx num_active_phys %d\n",
  2976. params->affected_displays, num_active_phys);
  2977. SDE_EVT32_VERBOSE(DRMID(drm_enc), params->affected_displays,
  2978. num_active_phys);
  2979. /* for left/right only update, ppsplit master switches interface */
  2980. _sde_encoder_ppsplit_swap_intf_for_right_only_update(drm_enc,
  2981. &params->affected_displays, num_active_phys);
  2982. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2983. enum sde_enc_split_role prv_role, new_role;
  2984. bool active = false;
  2985. phys = sde_enc->phys_encs[i];
  2986. if (!phys || !phys->ops.update_split_role || !phys->hw_pp)
  2987. continue;
  2988. active = test_bit(i, &params->affected_displays);
  2989. prv_role = phys->split_role;
  2990. if (active && num_active_phys == 1)
  2991. new_role = ENC_ROLE_SOLO;
  2992. else if (active && !master_assigned)
  2993. new_role = ENC_ROLE_MASTER;
  2994. else if (active)
  2995. new_role = ENC_ROLE_SLAVE;
  2996. else
  2997. new_role = ENC_ROLE_SKIP;
  2998. phys->ops.update_split_role(phys, new_role);
  2999. if (new_role == ENC_ROLE_SOLO || new_role == ENC_ROLE_MASTER) {
  3000. sde_enc->cur_master = phys;
  3001. master_assigned = true;
  3002. }
  3003. SDE_DEBUG_ENC(sde_enc, "pp %d role prv %d new %d active %d\n",
  3004. phys->hw_pp->idx - PINGPONG_0, prv_role,
  3005. phys->split_role, active);
  3006. SDE_EVT32(DRMID(drm_enc), params->affected_displays,
  3007. phys->hw_pp->idx - PINGPONG_0, prv_role,
  3008. phys->split_role, active, num_active_phys);
  3009. }
  3010. }
  3011. bool sde_encoder_check_curr_mode(struct drm_encoder *drm_enc, u32 mode)
  3012. {
  3013. struct sde_encoder_virt *sde_enc;
  3014. struct msm_display_info *disp_info;
  3015. if (!drm_enc) {
  3016. SDE_ERROR("invalid encoder\n");
  3017. return false;
  3018. }
  3019. sde_enc = to_sde_encoder_virt(drm_enc);
  3020. disp_info = &sde_enc->disp_info;
  3021. return (disp_info->curr_panel_mode == mode);
  3022. }
  3023. void sde_encoder_trigger_kickoff_pending(struct drm_encoder *drm_enc)
  3024. {
  3025. struct sde_encoder_virt *sde_enc;
  3026. struct sde_encoder_phys *phys;
  3027. unsigned int i;
  3028. struct sde_hw_ctl *ctl;
  3029. if (!drm_enc) {
  3030. SDE_ERROR("invalid encoder\n");
  3031. return;
  3032. }
  3033. sde_enc = to_sde_encoder_virt(drm_enc);
  3034. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3035. phys = sde_enc->phys_encs[i];
  3036. if (phys && phys->hw_ctl && (phys == sde_enc->cur_master) &&
  3037. sde_encoder_check_curr_mode(drm_enc,
  3038. MSM_DISPLAY_CMD_MODE)) {
  3039. ctl = phys->hw_ctl;
  3040. if (ctl->ops.trigger_pending)
  3041. /* update only for command mode primary ctl */
  3042. ctl->ops.trigger_pending(ctl);
  3043. }
  3044. }
  3045. sde_enc->idle_pc_restore = false;
  3046. }
  3047. static void sde_encoder_esd_trigger_work_handler(struct kthread_work *work)
  3048. {
  3049. struct sde_encoder_virt *sde_enc = container_of(work,
  3050. struct sde_encoder_virt, esd_trigger_work);
  3051. if (!sde_enc) {
  3052. SDE_ERROR("invalid sde encoder\n");
  3053. return;
  3054. }
  3055. sde_encoder_resource_control(&sde_enc->base,
  3056. SDE_ENC_RC_EVENT_KICKOFF);
  3057. }
  3058. static void sde_encoder_input_event_work_handler(struct kthread_work *work)
  3059. {
  3060. struct sde_encoder_virt *sde_enc = container_of(work,
  3061. struct sde_encoder_virt, input_event_work);
  3062. if (!sde_enc) {
  3063. SDE_ERROR("invalid sde encoder\n");
  3064. return;
  3065. }
  3066. sde_encoder_resource_control(&sde_enc->base,
  3067. SDE_ENC_RC_EVENT_EARLY_WAKEUP);
  3068. }
  3069. static void sde_encoder_early_wakeup_work_handler(struct kthread_work *work)
  3070. {
  3071. struct sde_encoder_virt *sde_enc = container_of(work,
  3072. struct sde_encoder_virt, early_wakeup_work);
  3073. if (!sde_enc) {
  3074. SDE_ERROR("invalid sde encoder\n");
  3075. return;
  3076. }
  3077. SDE_ATRACE_BEGIN("encoder_early_wakeup");
  3078. sde_encoder_resource_control(&sde_enc->base,
  3079. SDE_ENC_RC_EVENT_EARLY_WAKEUP);
  3080. SDE_ATRACE_END("encoder_early_wakeup");
  3081. }
  3082. void sde_encoder_early_wakeup(struct drm_encoder *drm_enc)
  3083. {
  3084. struct sde_encoder_virt *sde_enc = NULL;
  3085. struct msm_drm_thread *disp_thread = NULL;
  3086. struct msm_drm_private *priv = NULL;
  3087. priv = drm_enc->dev->dev_private;
  3088. sde_enc = to_sde_encoder_virt(drm_enc);
  3089. if (!sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE)) {
  3090. SDE_DEBUG_ENC(sde_enc,
  3091. "should only early wake up command mode display\n");
  3092. return;
  3093. }
  3094. if (!sde_enc->crtc || (sde_enc->crtc->index
  3095. >= ARRAY_SIZE(priv->event_thread))) {
  3096. SDE_ERROR("invalid CRTC: %d or crtc index: %d\n",
  3097. sde_enc->crtc == NULL,
  3098. sde_enc->crtc ? sde_enc->crtc->index : -EINVAL);
  3099. return;
  3100. }
  3101. disp_thread = &priv->disp_thread[sde_enc->crtc->index];
  3102. SDE_ATRACE_BEGIN("queue_early_wakeup_work");
  3103. kthread_queue_work(&disp_thread->worker,
  3104. &sde_enc->early_wakeup_work);
  3105. SDE_ATRACE_END("queue_early_wakeup_work");
  3106. }
  3107. int sde_encoder_poll_line_counts(struct drm_encoder *drm_enc)
  3108. {
  3109. static const uint64_t timeout_us = 50000;
  3110. static const uint64_t sleep_us = 20;
  3111. struct sde_encoder_virt *sde_enc;
  3112. ktime_t cur_ktime, exp_ktime;
  3113. uint32_t line_count, tmp, i;
  3114. if (!drm_enc) {
  3115. SDE_ERROR("invalid encoder\n");
  3116. return -EINVAL;
  3117. }
  3118. sde_enc = to_sde_encoder_virt(drm_enc);
  3119. if (!sde_enc->cur_master ||
  3120. !sde_enc->cur_master->ops.get_line_count) {
  3121. SDE_DEBUG_ENC(sde_enc, "can't get master line count\n");
  3122. SDE_EVT32(DRMID(drm_enc), SDE_EVTLOG_ERROR);
  3123. return -EINVAL;
  3124. }
  3125. exp_ktime = ktime_add_ms(ktime_get(), timeout_us / 1000);
  3126. line_count = sde_enc->cur_master->ops.get_line_count(
  3127. sde_enc->cur_master);
  3128. for (i = 0; i < (timeout_us * 2 / sleep_us); ++i) {
  3129. tmp = line_count;
  3130. line_count = sde_enc->cur_master->ops.get_line_count(
  3131. sde_enc->cur_master);
  3132. if (line_count < tmp) {
  3133. SDE_EVT32(DRMID(drm_enc), line_count);
  3134. return 0;
  3135. }
  3136. cur_ktime = ktime_get();
  3137. if (ktime_compare_safe(exp_ktime, cur_ktime) <= 0)
  3138. break;
  3139. usleep_range(sleep_us / 2, sleep_us);
  3140. }
  3141. SDE_EVT32(DRMID(drm_enc), line_count, SDE_EVTLOG_ERROR);
  3142. return -ETIMEDOUT;
  3143. }
  3144. static int _helper_flush_qsync(struct sde_encoder_phys *phys_enc)
  3145. {
  3146. struct drm_encoder *drm_enc;
  3147. struct sde_rm_hw_iter rm_iter;
  3148. bool lm_valid = false;
  3149. bool intf_valid = false;
  3150. if (!phys_enc || !phys_enc->parent) {
  3151. SDE_ERROR("invalid encoder\n");
  3152. return -EINVAL;
  3153. }
  3154. drm_enc = phys_enc->parent;
  3155. /* Flush the interfaces for AVR update or Qsync with INTF TE */
  3156. if (phys_enc->intf_mode == INTF_MODE_VIDEO ||
  3157. (phys_enc->intf_mode == INTF_MODE_CMD &&
  3158. phys_enc->has_intf_te)) {
  3159. sde_rm_init_hw_iter(&rm_iter, drm_enc->base.id,
  3160. SDE_HW_BLK_INTF);
  3161. while (sde_rm_get_hw(&phys_enc->sde_kms->rm, &rm_iter)) {
  3162. struct sde_hw_intf *hw_intf =
  3163. (struct sde_hw_intf *)rm_iter.hw;
  3164. if (!hw_intf)
  3165. continue;
  3166. if (phys_enc->hw_ctl->ops.update_bitmask)
  3167. phys_enc->hw_ctl->ops.update_bitmask(
  3168. phys_enc->hw_ctl,
  3169. SDE_HW_FLUSH_INTF,
  3170. hw_intf->idx, 1);
  3171. intf_valid = true;
  3172. }
  3173. if (!intf_valid) {
  3174. SDE_ERROR_ENC(to_sde_encoder_virt(drm_enc),
  3175. "intf not found to flush\n");
  3176. return -EFAULT;
  3177. }
  3178. } else {
  3179. sde_rm_init_hw_iter(&rm_iter, drm_enc->base.id, SDE_HW_BLK_LM);
  3180. while (sde_rm_get_hw(&phys_enc->sde_kms->rm, &rm_iter)) {
  3181. struct sde_hw_mixer *hw_lm =
  3182. (struct sde_hw_mixer *)rm_iter.hw;
  3183. if (!hw_lm)
  3184. continue;
  3185. /* update LM flush for HW without INTF TE */
  3186. if (phys_enc->hw_ctl->ops.update_bitmask_mixer)
  3187. phys_enc->hw_ctl->ops.update_bitmask_mixer(
  3188. phys_enc->hw_ctl,
  3189. hw_lm->idx, 1);
  3190. lm_valid = true;
  3191. }
  3192. if (!lm_valid) {
  3193. SDE_ERROR_ENC(to_sde_encoder_virt(drm_enc),
  3194. "lm not found to flush\n");
  3195. return -EFAULT;
  3196. }
  3197. }
  3198. return 0;
  3199. }
  3200. static void _sde_encoder_helper_hdr_plus_mempool_update(
  3201. struct sde_encoder_virt *sde_enc)
  3202. {
  3203. struct sde_connector_dyn_hdr_metadata *dhdr_meta = NULL;
  3204. struct sde_hw_mdp *mdptop = NULL;
  3205. sde_enc->dynamic_hdr_updated = false;
  3206. if (sde_enc->cur_master) {
  3207. mdptop = sde_enc->cur_master->hw_mdptop;
  3208. dhdr_meta = sde_connector_get_dyn_hdr_meta(
  3209. sde_enc->cur_master->connector);
  3210. }
  3211. if (!mdptop || !dhdr_meta || !dhdr_meta->dynamic_hdr_update)
  3212. return;
  3213. if (mdptop->ops.set_hdr_plus_metadata) {
  3214. sde_enc->dynamic_hdr_updated = true;
  3215. mdptop->ops.set_hdr_plus_metadata(
  3216. mdptop, dhdr_meta->dynamic_hdr_payload,
  3217. dhdr_meta->dynamic_hdr_payload_size,
  3218. sde_enc->cur_master->intf_idx == INTF_0 ?
  3219. 0 : 1);
  3220. }
  3221. }
  3222. void sde_encoder_needs_hw_reset(struct drm_encoder *drm_enc)
  3223. {
  3224. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  3225. struct sde_encoder_phys *phys;
  3226. int i;
  3227. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3228. phys = sde_enc->phys_encs[i];
  3229. if (phys && phys->ops.hw_reset)
  3230. phys->ops.hw_reset(phys);
  3231. }
  3232. }
  3233. int sde_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc,
  3234. struct sde_encoder_kickoff_params *params)
  3235. {
  3236. struct sde_encoder_virt *sde_enc;
  3237. struct sde_encoder_phys *phys;
  3238. struct sde_kms *sde_kms = NULL;
  3239. struct sde_crtc *sde_crtc;
  3240. bool needs_hw_reset = false, is_cmd_mode;
  3241. int i, rc, ret = 0;
  3242. struct msm_display_info *disp_info;
  3243. if (!drm_enc || !params || !drm_enc->dev ||
  3244. !drm_enc->dev->dev_private) {
  3245. SDE_ERROR("invalid args\n");
  3246. return -EINVAL;
  3247. }
  3248. sde_enc = to_sde_encoder_virt(drm_enc);
  3249. sde_kms = sde_encoder_get_kms(drm_enc);
  3250. if (!sde_kms)
  3251. return -EINVAL;
  3252. disp_info = &sde_enc->disp_info;
  3253. sde_crtc = to_sde_crtc(sde_enc->crtc);
  3254. SDE_DEBUG_ENC(sde_enc, "\n");
  3255. SDE_EVT32(DRMID(drm_enc));
  3256. is_cmd_mode = sde_encoder_check_curr_mode(drm_enc,
  3257. MSM_DISPLAY_CMD_MODE);
  3258. if (sde_enc->cur_master && sde_enc->cur_master->connector
  3259. && is_cmd_mode)
  3260. sde_enc->frame_trigger_mode = sde_connector_get_property(
  3261. sde_enc->cur_master->connector->state,
  3262. CONNECTOR_PROP_CMD_FRAME_TRIGGER_MODE);
  3263. _sde_encoder_helper_hdr_plus_mempool_update(sde_enc);
  3264. /* prepare for next kickoff, may include waiting on previous kickoff */
  3265. SDE_ATRACE_BEGIN("sde_encoder_prepare_for_kickoff");
  3266. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3267. phys = sde_enc->phys_encs[i];
  3268. params->frame_trigger_mode = sde_enc->frame_trigger_mode;
  3269. params->recovery_events_enabled =
  3270. sde_enc->recovery_events_enabled;
  3271. if (phys) {
  3272. if (phys->ops.prepare_for_kickoff) {
  3273. rc = phys->ops.prepare_for_kickoff(
  3274. phys, params);
  3275. if (rc)
  3276. ret = rc;
  3277. }
  3278. if (phys->enable_state == SDE_ENC_ERR_NEEDS_HW_RESET)
  3279. needs_hw_reset = true;
  3280. _sde_encoder_setup_dither(phys);
  3281. if (sde_enc->cur_master &&
  3282. sde_connector_is_qsync_updated(
  3283. sde_enc->cur_master->connector)) {
  3284. _helper_flush_qsync(phys);
  3285. }
  3286. }
  3287. }
  3288. rc = sde_encoder_resource_control(drm_enc, SDE_ENC_RC_EVENT_KICKOFF);
  3289. if (rc) {
  3290. SDE_ERROR_ENC(sde_enc, "resource kickoff failed rc %d\n", rc);
  3291. ret = rc;
  3292. goto end;
  3293. }
  3294. /* if any phys needs reset, reset all phys, in-order */
  3295. if (needs_hw_reset)
  3296. sde_encoder_needs_hw_reset(drm_enc);
  3297. _sde_encoder_update_master(drm_enc, params);
  3298. _sde_encoder_update_roi(drm_enc);
  3299. if (sde_enc->cur_master && sde_enc->cur_master->connector) {
  3300. rc = sde_connector_pre_kickoff(sde_enc->cur_master->connector);
  3301. if (rc) {
  3302. SDE_ERROR_ENC(sde_enc, "kickoff conn%d failed rc %d\n",
  3303. sde_enc->cur_master->connector->base.id,
  3304. rc);
  3305. ret = rc;
  3306. }
  3307. }
  3308. if (sde_enc->cur_master &&
  3309. ((is_cmd_mode && sde_enc->cur_master->cont_splash_enabled) ||
  3310. !sde_enc->cur_master->cont_splash_enabled)) {
  3311. rc = sde_encoder_dce_setup(sde_enc, params);
  3312. if (rc) {
  3313. SDE_ERROR_ENC(sde_enc, "failed to setup DSC: %d\n", rc);
  3314. ret = rc;
  3315. }
  3316. }
  3317. sde_encoder_dce_flush(sde_enc);
  3318. if (sde_enc->cur_master && !sde_enc->cur_master->cont_splash_enabled)
  3319. sde_configure_qdss(sde_enc, sde_enc->cur_master->hw_qdss,
  3320. sde_enc->cur_master, sde_kms->qdss_enabled);
  3321. end:
  3322. SDE_ATRACE_END("sde_encoder_prepare_for_kickoff");
  3323. return ret;
  3324. }
  3325. /**
  3326. * _sde_encoder_reset_ctl_hw - reset h/w configuration for all ctl's associated
  3327. * with the specified encoder, and unstage all pipes from it
  3328. * @encoder: encoder pointer
  3329. * Returns: 0 on success
  3330. */
  3331. static int _sde_encoder_reset_ctl_hw(struct drm_encoder *drm_enc)
  3332. {
  3333. struct sde_encoder_virt *sde_enc;
  3334. struct sde_encoder_phys *phys;
  3335. unsigned int i;
  3336. int rc = 0;
  3337. if (!drm_enc) {
  3338. SDE_ERROR("invalid encoder\n");
  3339. return -EINVAL;
  3340. }
  3341. sde_enc = to_sde_encoder_virt(drm_enc);
  3342. SDE_ATRACE_BEGIN("encoder_release_lm");
  3343. SDE_DEBUG_ENC(sde_enc, "\n");
  3344. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3345. phys = sde_enc->phys_encs[i];
  3346. if (!phys)
  3347. continue;
  3348. SDE_EVT32(DRMID(drm_enc), phys->intf_idx - INTF_0);
  3349. rc = sde_encoder_helper_reset_mixers(phys, NULL);
  3350. if (rc)
  3351. SDE_EVT32(DRMID(drm_enc), rc, SDE_EVTLOG_ERROR);
  3352. }
  3353. SDE_ATRACE_END("encoder_release_lm");
  3354. return rc;
  3355. }
  3356. void sde_encoder_kickoff(struct drm_encoder *drm_enc, bool is_error)
  3357. {
  3358. struct sde_encoder_virt *sde_enc;
  3359. struct sde_encoder_phys *phys;
  3360. unsigned int i;
  3361. if (!drm_enc) {
  3362. SDE_ERROR("invalid encoder\n");
  3363. return;
  3364. }
  3365. SDE_ATRACE_BEGIN("encoder_kickoff");
  3366. sde_enc = to_sde_encoder_virt(drm_enc);
  3367. SDE_DEBUG_ENC(sde_enc, "\n");
  3368. /* create a 'no pipes' commit to release buffers on errors */
  3369. if (is_error)
  3370. _sde_encoder_reset_ctl_hw(drm_enc);
  3371. /* All phys encs are ready to go, trigger the kickoff */
  3372. _sde_encoder_kickoff_phys(sde_enc);
  3373. /* allow phys encs to handle any post-kickoff business */
  3374. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3375. phys = sde_enc->phys_encs[i];
  3376. if (phys && phys->ops.handle_post_kickoff)
  3377. phys->ops.handle_post_kickoff(phys);
  3378. }
  3379. SDE_ATRACE_END("encoder_kickoff");
  3380. }
  3381. void sde_encoder_helper_get_pp_line_count(struct drm_encoder *drm_enc,
  3382. struct sde_hw_pp_vsync_info *info)
  3383. {
  3384. struct sde_encoder_virt *sde_enc;
  3385. struct sde_encoder_phys *phys;
  3386. int i, ret;
  3387. if (!drm_enc || !info)
  3388. return;
  3389. sde_enc = to_sde_encoder_virt(drm_enc);
  3390. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3391. phys = sde_enc->phys_encs[i];
  3392. if (phys && phys->hw_intf && phys->hw_pp
  3393. && phys->hw_intf->ops.get_vsync_info) {
  3394. ret = phys->hw_intf->ops.get_vsync_info(
  3395. phys->hw_intf, &info[i]);
  3396. if (!ret) {
  3397. info[i].pp_idx = phys->hw_pp->idx - PINGPONG_0;
  3398. info[i].intf_idx = phys->hw_intf->idx - INTF_0;
  3399. }
  3400. }
  3401. }
  3402. }
  3403. void sde_encoder_helper_get_transfer_time(struct drm_encoder *drm_enc,
  3404. u32 *transfer_time_us)
  3405. {
  3406. struct sde_encoder_virt *sde_enc;
  3407. struct msm_mode_info *info;
  3408. if (!drm_enc || !transfer_time_us) {
  3409. SDE_ERROR("bad arg: encoder:%d transfer_time:%d\n", !drm_enc,
  3410. !transfer_time_us);
  3411. return;
  3412. }
  3413. sde_enc = to_sde_encoder_virt(drm_enc);
  3414. info = &sde_enc->mode_info;
  3415. *transfer_time_us = info->mdp_transfer_time_us;
  3416. }
  3417. int sde_encoder_helper_reset_mixers(struct sde_encoder_phys *phys_enc,
  3418. struct drm_framebuffer *fb)
  3419. {
  3420. struct drm_encoder *drm_enc;
  3421. struct sde_hw_mixer_cfg mixer;
  3422. struct sde_rm_hw_iter lm_iter;
  3423. bool lm_valid = false;
  3424. if (!phys_enc || !phys_enc->parent) {
  3425. SDE_ERROR("invalid encoder\n");
  3426. return -EINVAL;
  3427. }
  3428. drm_enc = phys_enc->parent;
  3429. memset(&mixer, 0, sizeof(mixer));
  3430. /* reset associated CTL/LMs */
  3431. if (phys_enc->hw_ctl->ops.clear_all_blendstages)
  3432. phys_enc->hw_ctl->ops.clear_all_blendstages(phys_enc->hw_ctl);
  3433. sde_rm_init_hw_iter(&lm_iter, drm_enc->base.id, SDE_HW_BLK_LM);
  3434. while (sde_rm_get_hw(&phys_enc->sde_kms->rm, &lm_iter)) {
  3435. struct sde_hw_mixer *hw_lm = (struct sde_hw_mixer *)lm_iter.hw;
  3436. if (!hw_lm)
  3437. continue;
  3438. /* need to flush LM to remove it */
  3439. if (phys_enc->hw_ctl->ops.update_bitmask_mixer)
  3440. phys_enc->hw_ctl->ops.update_bitmask_mixer(
  3441. phys_enc->hw_ctl,
  3442. hw_lm->idx, 1);
  3443. if (fb) {
  3444. /* assume a single LM if targeting a frame buffer */
  3445. if (lm_valid)
  3446. continue;
  3447. mixer.out_height = fb->height;
  3448. mixer.out_width = fb->width;
  3449. if (hw_lm->ops.setup_mixer_out)
  3450. hw_lm->ops.setup_mixer_out(hw_lm, &mixer);
  3451. }
  3452. lm_valid = true;
  3453. /* only enable border color on LM */
  3454. if (phys_enc->hw_ctl->ops.setup_blendstage)
  3455. phys_enc->hw_ctl->ops.setup_blendstage(
  3456. phys_enc->hw_ctl, hw_lm->idx, NULL);
  3457. }
  3458. if (!lm_valid) {
  3459. SDE_ERROR_ENC(to_sde_encoder_virt(drm_enc), "lm not found\n");
  3460. return -EFAULT;
  3461. }
  3462. return 0;
  3463. }
  3464. int sde_encoder_prepare_commit(struct drm_encoder *drm_enc)
  3465. {
  3466. struct sde_encoder_virt *sde_enc;
  3467. struct sde_encoder_phys *phys;
  3468. int i, rc = 0, ret = 0;
  3469. struct sde_hw_ctl *ctl;
  3470. if (!drm_enc) {
  3471. SDE_ERROR("invalid encoder\n");
  3472. return -EINVAL;
  3473. }
  3474. sde_enc = to_sde_encoder_virt(drm_enc);
  3475. /* update the qsync parameters for the current frame */
  3476. if (sde_enc->cur_master)
  3477. sde_connector_set_qsync_params(
  3478. sde_enc->cur_master->connector);
  3479. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3480. phys = sde_enc->phys_encs[i];
  3481. if (phys && phys->ops.prepare_commit)
  3482. phys->ops.prepare_commit(phys);
  3483. if (phys && phys->enable_state == SDE_ENC_ERR_NEEDS_HW_RESET)
  3484. ret = -ETIMEDOUT;
  3485. if (phys && phys->hw_ctl) {
  3486. ctl = phys->hw_ctl;
  3487. /*
  3488. * avoid clearing the pending flush during the first
  3489. * frame update after idle power collpase as the
  3490. * restore path would have updated the pending flush
  3491. */
  3492. if (!sde_enc->idle_pc_restore &&
  3493. ctl->ops.clear_pending_flush)
  3494. ctl->ops.clear_pending_flush(ctl);
  3495. }
  3496. }
  3497. if (sde_enc->cur_master && sde_enc->cur_master->connector) {
  3498. rc = sde_connector_prepare_commit(
  3499. sde_enc->cur_master->connector);
  3500. if (rc)
  3501. SDE_ERROR_ENC(sde_enc,
  3502. "prepare commit failed conn %d rc %d\n",
  3503. sde_enc->cur_master->connector->base.id,
  3504. rc);
  3505. }
  3506. return ret;
  3507. }
  3508. void sde_encoder_helper_setup_misr(struct sde_encoder_phys *phys_enc,
  3509. bool enable, u32 frame_count)
  3510. {
  3511. if (!phys_enc)
  3512. return;
  3513. if (phys_enc->hw_intf && phys_enc->hw_intf->ops.setup_misr)
  3514. phys_enc->hw_intf->ops.setup_misr(phys_enc->hw_intf,
  3515. enable, frame_count);
  3516. }
  3517. int sde_encoder_helper_collect_misr(struct sde_encoder_phys *phys_enc,
  3518. bool nonblock, u32 *misr_value)
  3519. {
  3520. if (!phys_enc)
  3521. return -EINVAL;
  3522. return phys_enc->hw_intf && phys_enc->hw_intf->ops.collect_misr ?
  3523. phys_enc->hw_intf->ops.collect_misr(phys_enc->hw_intf,
  3524. nonblock, misr_value) : -ENOTSUPP;
  3525. }
  3526. #ifdef CONFIG_DEBUG_FS
  3527. static int _sde_encoder_status_show(struct seq_file *s, void *data)
  3528. {
  3529. struct sde_encoder_virt *sde_enc;
  3530. int i;
  3531. if (!s || !s->private)
  3532. return -EINVAL;
  3533. sde_enc = s->private;
  3534. mutex_lock(&sde_enc->enc_lock);
  3535. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3536. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  3537. if (!phys)
  3538. continue;
  3539. seq_printf(s, "intf:%d vsync:%8d underrun:%8d ",
  3540. phys->intf_idx - INTF_0,
  3541. atomic_read(&phys->vsync_cnt),
  3542. atomic_read(&phys->underrun_cnt));
  3543. switch (phys->intf_mode) {
  3544. case INTF_MODE_VIDEO:
  3545. seq_puts(s, "mode: video\n");
  3546. break;
  3547. case INTF_MODE_CMD:
  3548. seq_puts(s, "mode: command\n");
  3549. break;
  3550. case INTF_MODE_WB_BLOCK:
  3551. seq_puts(s, "mode: wb block\n");
  3552. break;
  3553. case INTF_MODE_WB_LINE:
  3554. seq_puts(s, "mode: wb line\n");
  3555. break;
  3556. default:
  3557. seq_puts(s, "mode: ???\n");
  3558. break;
  3559. }
  3560. }
  3561. mutex_unlock(&sde_enc->enc_lock);
  3562. return 0;
  3563. }
  3564. static int _sde_encoder_debugfs_status_open(struct inode *inode,
  3565. struct file *file)
  3566. {
  3567. return single_open(file, _sde_encoder_status_show, inode->i_private);
  3568. }
  3569. static ssize_t _sde_encoder_misr_setup(struct file *file,
  3570. const char __user *user_buf, size_t count, loff_t *ppos)
  3571. {
  3572. struct sde_encoder_virt *sde_enc;
  3573. int rc;
  3574. char buf[MISR_BUFF_SIZE + 1];
  3575. size_t buff_copy;
  3576. u32 frame_count, enable;
  3577. struct sde_kms *sde_kms = NULL;
  3578. struct drm_encoder *drm_enc;
  3579. if (!file || !file->private_data)
  3580. return -EINVAL;
  3581. sde_enc = file->private_data;
  3582. if (!sde_enc)
  3583. return -EINVAL;
  3584. sde_kms = sde_encoder_get_kms(&sde_enc->base);
  3585. if (!sde_kms)
  3586. return -EINVAL;
  3587. drm_enc = &sde_enc->base;
  3588. if (sde_kms_is_secure_session_inprogress(sde_kms)) {
  3589. SDE_DEBUG_ENC(sde_enc, "misr enable/disable not allowed\n");
  3590. return -ENOTSUPP;
  3591. }
  3592. buff_copy = min_t(size_t, count, MISR_BUFF_SIZE);
  3593. if (copy_from_user(buf, user_buf, buff_copy))
  3594. return -EINVAL;
  3595. buf[buff_copy] = 0; /* end of string */
  3596. if (sscanf(buf, "%u %u", &enable, &frame_count) != 2)
  3597. return -EINVAL;
  3598. rc = pm_runtime_get_sync(drm_enc->dev->dev);
  3599. if (rc < 0)
  3600. return rc;
  3601. sde_enc->misr_enable = enable;
  3602. sde_enc->misr_reconfigure = true;
  3603. sde_enc->misr_frame_count = frame_count;
  3604. sde_encoder_misr_configure(&sde_enc->base, enable, frame_count);
  3605. pm_runtime_put_sync(drm_enc->dev->dev);
  3606. return count;
  3607. }
  3608. static ssize_t _sde_encoder_misr_read(struct file *file,
  3609. char __user *user_buff, size_t count, loff_t *ppos)
  3610. {
  3611. struct sde_encoder_virt *sde_enc;
  3612. struct sde_kms *sde_kms = NULL;
  3613. struct drm_encoder *drm_enc;
  3614. int i = 0, len = 0;
  3615. char buf[MISR_BUFF_SIZE + 1] = {'\0'};
  3616. int rc;
  3617. if (*ppos)
  3618. return 0;
  3619. if (!file || !file->private_data)
  3620. return -EINVAL;
  3621. sde_enc = file->private_data;
  3622. sde_kms = sde_encoder_get_kms(&sde_enc->base);
  3623. if (!sde_kms)
  3624. return -EINVAL;
  3625. if (sde_kms_is_secure_session_inprogress(sde_kms)) {
  3626. SDE_DEBUG_ENC(sde_enc, "misr read not allowed\n");
  3627. return -ENOTSUPP;
  3628. }
  3629. drm_enc = &sde_enc->base;
  3630. rc = pm_runtime_get_sync(drm_enc->dev->dev);
  3631. if (rc < 0)
  3632. return rc;
  3633. if (!sde_enc->misr_enable) {
  3634. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  3635. "disabled\n");
  3636. goto buff_check;
  3637. }
  3638. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3639. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  3640. u32 misr_value = 0;
  3641. if (!phys || !phys->ops.collect_misr) {
  3642. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  3643. "invalid\n");
  3644. SDE_ERROR_ENC(sde_enc, "invalid misr ops\n");
  3645. continue;
  3646. }
  3647. rc = phys->ops.collect_misr(phys, false, &misr_value);
  3648. if (rc) {
  3649. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  3650. "invalid\n");
  3651. SDE_ERROR_ENC(sde_enc, "failed to collect misr %d\n",
  3652. rc);
  3653. continue;
  3654. } else {
  3655. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  3656. "Intf idx:%d\n",
  3657. phys->intf_idx - INTF_0);
  3658. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  3659. "0x%x\n", misr_value);
  3660. }
  3661. }
  3662. buff_check:
  3663. if (count <= len) {
  3664. len = 0;
  3665. goto end;
  3666. }
  3667. if (copy_to_user(user_buff, buf, len)) {
  3668. len = -EFAULT;
  3669. goto end;
  3670. }
  3671. *ppos += len; /* increase offset */
  3672. end:
  3673. pm_runtime_put_sync(drm_enc->dev->dev);
  3674. return len;
  3675. }
  3676. static int _sde_encoder_init_debugfs(struct drm_encoder *drm_enc)
  3677. {
  3678. struct sde_encoder_virt *sde_enc;
  3679. struct sde_kms *sde_kms;
  3680. int i;
  3681. static const struct file_operations debugfs_status_fops = {
  3682. .open = _sde_encoder_debugfs_status_open,
  3683. .read = seq_read,
  3684. .llseek = seq_lseek,
  3685. .release = single_release,
  3686. };
  3687. static const struct file_operations debugfs_misr_fops = {
  3688. .open = simple_open,
  3689. .read = _sde_encoder_misr_read,
  3690. .write = _sde_encoder_misr_setup,
  3691. };
  3692. char name[SDE_NAME_SIZE];
  3693. if (!drm_enc) {
  3694. SDE_ERROR("invalid encoder\n");
  3695. return -EINVAL;
  3696. }
  3697. sde_enc = to_sde_encoder_virt(drm_enc);
  3698. sde_kms = sde_encoder_get_kms(drm_enc);
  3699. if (!sde_kms) {
  3700. SDE_ERROR("invalid sde_kms\n");
  3701. return -EINVAL;
  3702. }
  3703. snprintf(name, SDE_NAME_SIZE, "encoder%u", drm_enc->base.id);
  3704. /* create overall sub-directory for the encoder */
  3705. sde_enc->debugfs_root = debugfs_create_dir(name,
  3706. drm_enc->dev->primary->debugfs_root);
  3707. if (!sde_enc->debugfs_root)
  3708. return -ENOMEM;
  3709. /* don't error check these */
  3710. debugfs_create_file("status", 0400,
  3711. sde_enc->debugfs_root, sde_enc, &debugfs_status_fops);
  3712. debugfs_create_file("misr_data", 0600,
  3713. sde_enc->debugfs_root, sde_enc, &debugfs_misr_fops);
  3714. debugfs_create_bool("idle_power_collapse", 0600, sde_enc->debugfs_root,
  3715. &sde_enc->idle_pc_enabled);
  3716. debugfs_create_u32("frame_trigger_mode", 0400, sde_enc->debugfs_root,
  3717. &sde_enc->frame_trigger_mode);
  3718. for (i = 0; i < sde_enc->num_phys_encs; i++)
  3719. if (sde_enc->phys_encs[i] &&
  3720. sde_enc->phys_encs[i]->ops.late_register)
  3721. sde_enc->phys_encs[i]->ops.late_register(
  3722. sde_enc->phys_encs[i],
  3723. sde_enc->debugfs_root);
  3724. return 0;
  3725. }
  3726. static void _sde_encoder_destroy_debugfs(struct drm_encoder *drm_enc)
  3727. {
  3728. struct sde_encoder_virt *sde_enc;
  3729. if (!drm_enc)
  3730. return;
  3731. sde_enc = to_sde_encoder_virt(drm_enc);
  3732. debugfs_remove_recursive(sde_enc->debugfs_root);
  3733. }
  3734. #else
  3735. static int _sde_encoder_init_debugfs(struct drm_encoder *drm_enc)
  3736. {
  3737. return 0;
  3738. }
  3739. static void _sde_encoder_destroy_debugfs(struct drm_encoder *drm_enc)
  3740. {
  3741. }
  3742. #endif
  3743. static int sde_encoder_late_register(struct drm_encoder *encoder)
  3744. {
  3745. return _sde_encoder_init_debugfs(encoder);
  3746. }
  3747. static void sde_encoder_early_unregister(struct drm_encoder *encoder)
  3748. {
  3749. _sde_encoder_destroy_debugfs(encoder);
  3750. }
  3751. static int sde_encoder_virt_add_phys_encs(
  3752. struct msm_display_info *disp_info,
  3753. struct sde_encoder_virt *sde_enc,
  3754. struct sde_enc_phys_init_params *params)
  3755. {
  3756. struct sde_encoder_phys *enc = NULL;
  3757. u32 display_caps = disp_info->capabilities;
  3758. SDE_DEBUG_ENC(sde_enc, "\n");
  3759. /*
  3760. * We may create up to NUM_PHYS_ENCODER_TYPES physical encoder types
  3761. * in this function, check up-front.
  3762. */
  3763. if (sde_enc->num_phys_encs + NUM_PHYS_ENCODER_TYPES >=
  3764. ARRAY_SIZE(sde_enc->phys_encs)) {
  3765. SDE_ERROR_ENC(sde_enc, "too many physical encoders %d\n",
  3766. sde_enc->num_phys_encs);
  3767. return -EINVAL;
  3768. }
  3769. if (display_caps & MSM_DISPLAY_CAP_VID_MODE) {
  3770. enc = sde_encoder_phys_vid_init(params);
  3771. if (IS_ERR_OR_NULL(enc)) {
  3772. SDE_ERROR_ENC(sde_enc, "failed to init vid enc: %ld\n",
  3773. PTR_ERR(enc));
  3774. return !enc ? -EINVAL : PTR_ERR(enc);
  3775. }
  3776. sde_enc->phys_vid_encs[sde_enc->num_phys_encs] = enc;
  3777. }
  3778. if (display_caps & MSM_DISPLAY_CAP_CMD_MODE) {
  3779. enc = sde_encoder_phys_cmd_init(params);
  3780. if (IS_ERR_OR_NULL(enc)) {
  3781. SDE_ERROR_ENC(sde_enc, "failed to init cmd enc: %ld\n",
  3782. PTR_ERR(enc));
  3783. return !enc ? -EINVAL : PTR_ERR(enc);
  3784. }
  3785. sde_enc->phys_cmd_encs[sde_enc->num_phys_encs] = enc;
  3786. }
  3787. if (disp_info->curr_panel_mode == MSM_DISPLAY_VIDEO_MODE)
  3788. sde_enc->phys_encs[sde_enc->num_phys_encs] =
  3789. sde_enc->phys_vid_encs[sde_enc->num_phys_encs];
  3790. else
  3791. sde_enc->phys_encs[sde_enc->num_phys_encs] =
  3792. sde_enc->phys_cmd_encs[sde_enc->num_phys_encs];
  3793. ++sde_enc->num_phys_encs;
  3794. return 0;
  3795. }
  3796. static int sde_encoder_virt_add_phys_enc_wb(struct sde_encoder_virt *sde_enc,
  3797. struct sde_enc_phys_init_params *params)
  3798. {
  3799. struct sde_encoder_phys *enc = NULL;
  3800. if (!sde_enc) {
  3801. SDE_ERROR("invalid encoder\n");
  3802. return -EINVAL;
  3803. }
  3804. SDE_DEBUG_ENC(sde_enc, "\n");
  3805. if (sde_enc->num_phys_encs + 1 >= ARRAY_SIZE(sde_enc->phys_encs)) {
  3806. SDE_ERROR_ENC(sde_enc, "too many physical encoders %d\n",
  3807. sde_enc->num_phys_encs);
  3808. return -EINVAL;
  3809. }
  3810. enc = sde_encoder_phys_wb_init(params);
  3811. if (IS_ERR_OR_NULL(enc)) {
  3812. SDE_ERROR_ENC(sde_enc, "failed to init wb enc: %ld\n",
  3813. PTR_ERR(enc));
  3814. return !enc ? -EINVAL : PTR_ERR(enc);
  3815. }
  3816. sde_enc->phys_encs[sde_enc->num_phys_encs] = enc;
  3817. ++sde_enc->num_phys_encs;
  3818. return 0;
  3819. }
  3820. static int sde_encoder_setup_display(struct sde_encoder_virt *sde_enc,
  3821. struct sde_kms *sde_kms,
  3822. struct msm_display_info *disp_info,
  3823. int *drm_enc_mode)
  3824. {
  3825. int ret = 0;
  3826. int i = 0;
  3827. enum sde_intf_type intf_type;
  3828. struct sde_encoder_virt_ops parent_ops = {
  3829. sde_encoder_vblank_callback,
  3830. sde_encoder_underrun_callback,
  3831. sde_encoder_frame_done_callback,
  3832. sde_encoder_get_qsync_fps_callback,
  3833. };
  3834. struct sde_enc_phys_init_params phys_params;
  3835. if (!sde_enc || !sde_kms) {
  3836. SDE_ERROR("invalid arg(s), enc %d kms %d\n",
  3837. !sde_enc, !sde_kms);
  3838. return -EINVAL;
  3839. }
  3840. memset(&phys_params, 0, sizeof(phys_params));
  3841. phys_params.sde_kms = sde_kms;
  3842. phys_params.parent = &sde_enc->base;
  3843. phys_params.parent_ops = parent_ops;
  3844. phys_params.enc_spinlock = &sde_enc->enc_spinlock;
  3845. phys_params.vblank_ctl_lock = &sde_enc->vblank_ctl_lock;
  3846. SDE_DEBUG("\n");
  3847. if (disp_info->intf_type == DRM_MODE_CONNECTOR_DSI) {
  3848. *drm_enc_mode = DRM_MODE_ENCODER_DSI;
  3849. intf_type = INTF_DSI;
  3850. } else if (disp_info->intf_type == DRM_MODE_CONNECTOR_HDMIA) {
  3851. *drm_enc_mode = DRM_MODE_ENCODER_TMDS;
  3852. intf_type = INTF_HDMI;
  3853. } else if (disp_info->intf_type == DRM_MODE_CONNECTOR_DisplayPort) {
  3854. if (disp_info->capabilities & MSM_DISPLAY_CAP_MST_MODE)
  3855. *drm_enc_mode = DRM_MODE_ENCODER_DPMST;
  3856. else
  3857. *drm_enc_mode = DRM_MODE_ENCODER_TMDS;
  3858. intf_type = INTF_DP;
  3859. } else if (disp_info->intf_type == DRM_MODE_CONNECTOR_VIRTUAL) {
  3860. *drm_enc_mode = DRM_MODE_ENCODER_VIRTUAL;
  3861. intf_type = INTF_WB;
  3862. } else {
  3863. SDE_ERROR_ENC(sde_enc, "unsupported display interface type\n");
  3864. return -EINVAL;
  3865. }
  3866. WARN_ON(disp_info->num_of_h_tiles < 1);
  3867. sde_enc->display_num_of_h_tiles = disp_info->num_of_h_tiles;
  3868. sde_enc->te_source = disp_info->te_source;
  3869. SDE_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles);
  3870. if ((disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) ||
  3871. (disp_info->capabilities & MSM_DISPLAY_CAP_VID_MODE))
  3872. sde_enc->idle_pc_enabled = sde_kms->catalog->has_idle_pc;
  3873. mutex_lock(&sde_enc->enc_lock);
  3874. for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) {
  3875. /*
  3876. * Left-most tile is at index 0, content is controller id
  3877. * h_tile_instance_ids[2] = {0, 1}; DSI0 = left, DSI1 = right
  3878. * h_tile_instance_ids[2] = {1, 0}; DSI1 = left, DSI0 = right
  3879. */
  3880. u32 controller_id = disp_info->h_tile_instance[i];
  3881. if (disp_info->num_of_h_tiles > 1) {
  3882. if (i == 0)
  3883. phys_params.split_role = ENC_ROLE_MASTER;
  3884. else
  3885. phys_params.split_role = ENC_ROLE_SLAVE;
  3886. } else {
  3887. phys_params.split_role = ENC_ROLE_SOLO;
  3888. }
  3889. SDE_DEBUG("h_tile_instance %d = %d, split_role %d\n",
  3890. i, controller_id, phys_params.split_role);
  3891. if (sde_enc->ops.phys_init) {
  3892. struct sde_encoder_phys *enc;
  3893. enc = sde_enc->ops.phys_init(intf_type,
  3894. controller_id,
  3895. &phys_params);
  3896. if (enc) {
  3897. sde_enc->phys_encs[sde_enc->num_phys_encs] =
  3898. enc;
  3899. ++sde_enc->num_phys_encs;
  3900. } else
  3901. SDE_ERROR_ENC(sde_enc,
  3902. "failed to add phys encs\n");
  3903. continue;
  3904. }
  3905. if (intf_type == INTF_WB) {
  3906. phys_params.intf_idx = INTF_MAX;
  3907. phys_params.wb_idx = sde_encoder_get_wb(
  3908. sde_kms->catalog,
  3909. intf_type, controller_id);
  3910. if (phys_params.wb_idx == WB_MAX) {
  3911. SDE_ERROR_ENC(sde_enc,
  3912. "could not get wb: type %d, id %d\n",
  3913. intf_type, controller_id);
  3914. ret = -EINVAL;
  3915. }
  3916. } else {
  3917. phys_params.wb_idx = WB_MAX;
  3918. phys_params.intf_idx = sde_encoder_get_intf(
  3919. sde_kms->catalog, intf_type,
  3920. controller_id);
  3921. if (phys_params.intf_idx == INTF_MAX) {
  3922. SDE_ERROR_ENC(sde_enc,
  3923. "could not get wb: type %d, id %d\n",
  3924. intf_type, controller_id);
  3925. ret = -EINVAL;
  3926. }
  3927. }
  3928. if (!ret) {
  3929. if (intf_type == INTF_WB)
  3930. ret = sde_encoder_virt_add_phys_enc_wb(sde_enc,
  3931. &phys_params);
  3932. else
  3933. ret = sde_encoder_virt_add_phys_encs(
  3934. disp_info,
  3935. sde_enc,
  3936. &phys_params);
  3937. if (ret)
  3938. SDE_ERROR_ENC(sde_enc,
  3939. "failed to add phys encs\n");
  3940. }
  3941. }
  3942. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3943. struct sde_encoder_phys *vid_phys = sde_enc->phys_vid_encs[i];
  3944. struct sde_encoder_phys *cmd_phys = sde_enc->phys_cmd_encs[i];
  3945. if (vid_phys) {
  3946. atomic_set(&vid_phys->vsync_cnt, 0);
  3947. atomic_set(&vid_phys->underrun_cnt, 0);
  3948. }
  3949. if (cmd_phys) {
  3950. atomic_set(&cmd_phys->vsync_cnt, 0);
  3951. atomic_set(&cmd_phys->underrun_cnt, 0);
  3952. }
  3953. }
  3954. mutex_unlock(&sde_enc->enc_lock);
  3955. return ret;
  3956. }
  3957. static const struct drm_encoder_helper_funcs sde_encoder_helper_funcs = {
  3958. .mode_set = sde_encoder_virt_mode_set,
  3959. .disable = sde_encoder_virt_disable,
  3960. .enable = sde_encoder_virt_enable,
  3961. .atomic_check = sde_encoder_virt_atomic_check,
  3962. };
  3963. static const struct drm_encoder_funcs sde_encoder_funcs = {
  3964. .destroy = sde_encoder_destroy,
  3965. .late_register = sde_encoder_late_register,
  3966. .early_unregister = sde_encoder_early_unregister,
  3967. };
  3968. struct drm_encoder *sde_encoder_init_with_ops(
  3969. struct drm_device *dev,
  3970. struct msm_display_info *disp_info,
  3971. const struct sde_encoder_ops *ops)
  3972. {
  3973. struct msm_drm_private *priv = dev->dev_private;
  3974. struct sde_kms *sde_kms = to_sde_kms(priv->kms);
  3975. struct drm_encoder *drm_enc = NULL;
  3976. struct sde_encoder_virt *sde_enc = NULL;
  3977. int drm_enc_mode = DRM_MODE_ENCODER_NONE;
  3978. char name[SDE_NAME_SIZE];
  3979. int ret = 0, i, intf_index = INTF_MAX;
  3980. struct sde_encoder_phys *phys = NULL;
  3981. sde_enc = kzalloc(sizeof(*sde_enc), GFP_KERNEL);
  3982. if (!sde_enc) {
  3983. ret = -ENOMEM;
  3984. goto fail;
  3985. }
  3986. if (ops)
  3987. sde_enc->ops = *ops;
  3988. mutex_init(&sde_enc->enc_lock);
  3989. ret = sde_encoder_setup_display(sde_enc, sde_kms, disp_info,
  3990. &drm_enc_mode);
  3991. if (ret)
  3992. goto fail;
  3993. sde_enc->cur_master = NULL;
  3994. spin_lock_init(&sde_enc->enc_spinlock);
  3995. mutex_init(&sde_enc->vblank_ctl_lock);
  3996. for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++)
  3997. atomic_set(&sde_enc->frame_done_cnt[i], 0);
  3998. drm_enc = &sde_enc->base;
  3999. drm_encoder_init(dev, drm_enc, &sde_encoder_funcs, drm_enc_mode, NULL);
  4000. drm_encoder_helper_add(drm_enc, &sde_encoder_helper_funcs);
  4001. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4002. phys = sde_enc->phys_encs[i];
  4003. if (!phys)
  4004. continue;
  4005. if (phys->ops.is_master && phys->ops.is_master(phys))
  4006. intf_index = phys->intf_idx - INTF_0;
  4007. }
  4008. snprintf(name, SDE_NAME_SIZE, "rsc_enc%u", drm_enc->base.id);
  4009. sde_enc->rsc_client = sde_rsc_client_create(SDE_RSC_INDEX, name,
  4010. (disp_info->display_type == SDE_CONNECTOR_PRIMARY) ?
  4011. SDE_RSC_PRIMARY_DISP_CLIENT :
  4012. SDE_RSC_EXTERNAL_DISP_CLIENT, intf_index + 1);
  4013. if (IS_ERR_OR_NULL(sde_enc->rsc_client)) {
  4014. SDE_DEBUG("sde rsc client create failed :%ld\n",
  4015. PTR_ERR(sde_enc->rsc_client));
  4016. sde_enc->rsc_client = NULL;
  4017. }
  4018. if (disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) {
  4019. ret = _sde_encoder_input_handler(sde_enc);
  4020. if (ret)
  4021. SDE_ERROR(
  4022. "input handler registration failed, rc = %d\n", ret);
  4023. }
  4024. mutex_init(&sde_enc->rc_lock);
  4025. kthread_init_delayed_work(&sde_enc->delayed_off_work,
  4026. sde_encoder_off_work);
  4027. sde_enc->vblank_enabled = false;
  4028. sde_enc->qdss_status = false;
  4029. kthread_init_work(&sde_enc->input_event_work,
  4030. sde_encoder_input_event_work_handler);
  4031. kthread_init_work(&sde_enc->early_wakeup_work,
  4032. sde_encoder_early_wakeup_work_handler);
  4033. kthread_init_work(&sde_enc->esd_trigger_work,
  4034. sde_encoder_esd_trigger_work_handler);
  4035. memcpy(&sde_enc->disp_info, disp_info, sizeof(*disp_info));
  4036. SDE_DEBUG_ENC(sde_enc, "created\n");
  4037. return drm_enc;
  4038. fail:
  4039. SDE_ERROR("failed to create encoder\n");
  4040. if (drm_enc)
  4041. sde_encoder_destroy(drm_enc);
  4042. return ERR_PTR(ret);
  4043. }
  4044. struct drm_encoder *sde_encoder_init(
  4045. struct drm_device *dev,
  4046. struct msm_display_info *disp_info)
  4047. {
  4048. return sde_encoder_init_with_ops(dev, disp_info, NULL);
  4049. }
  4050. int sde_encoder_wait_for_event(struct drm_encoder *drm_enc,
  4051. enum msm_event_wait event)
  4052. {
  4053. int (*fn_wait)(struct sde_encoder_phys *phys_enc) = NULL;
  4054. struct sde_encoder_virt *sde_enc = NULL;
  4055. int i, ret = 0;
  4056. char atrace_buf[32];
  4057. if (!drm_enc) {
  4058. SDE_ERROR("invalid encoder\n");
  4059. return -EINVAL;
  4060. }
  4061. sde_enc = to_sde_encoder_virt(drm_enc);
  4062. SDE_DEBUG_ENC(sde_enc, "\n");
  4063. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4064. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  4065. switch (event) {
  4066. case MSM_ENC_COMMIT_DONE:
  4067. fn_wait = phys->ops.wait_for_commit_done;
  4068. break;
  4069. case MSM_ENC_TX_COMPLETE:
  4070. fn_wait = phys->ops.wait_for_tx_complete;
  4071. break;
  4072. case MSM_ENC_VBLANK:
  4073. fn_wait = phys->ops.wait_for_vblank;
  4074. break;
  4075. case MSM_ENC_ACTIVE_REGION:
  4076. fn_wait = phys->ops.wait_for_active;
  4077. break;
  4078. default:
  4079. SDE_ERROR_ENC(sde_enc, "unknown wait event %d\n",
  4080. event);
  4081. return -EINVAL;
  4082. }
  4083. if (phys && fn_wait) {
  4084. snprintf(atrace_buf, sizeof(atrace_buf),
  4085. "wait_completion_event_%d", event);
  4086. SDE_ATRACE_BEGIN(atrace_buf);
  4087. ret = fn_wait(phys);
  4088. SDE_ATRACE_END(atrace_buf);
  4089. if (ret)
  4090. return ret;
  4091. }
  4092. }
  4093. return ret;
  4094. }
  4095. void sde_encoder_helper_get_jitter_bounds_ns(struct drm_encoder *drm_enc,
  4096. u64 *l_bound, u64 *u_bound)
  4097. {
  4098. struct sde_encoder_virt *sde_enc;
  4099. u64 jitter_ns, frametime_ns;
  4100. struct msm_mode_info *info;
  4101. if (!drm_enc) {
  4102. SDE_ERROR("invalid encoder\n");
  4103. return;
  4104. }
  4105. sde_enc = to_sde_encoder_virt(drm_enc);
  4106. info = &sde_enc->mode_info;
  4107. frametime_ns = (1 * 1000000000) / info->frame_rate;
  4108. jitter_ns = info->jitter_numer * frametime_ns;
  4109. do_div(jitter_ns, info->jitter_denom * 100);
  4110. *l_bound = frametime_ns - jitter_ns;
  4111. *u_bound = frametime_ns + jitter_ns;
  4112. }
  4113. u32 sde_encoder_get_fps(struct drm_encoder *drm_enc)
  4114. {
  4115. struct sde_encoder_virt *sde_enc;
  4116. if (!drm_enc) {
  4117. SDE_ERROR("invalid encoder\n");
  4118. return 0;
  4119. }
  4120. sde_enc = to_sde_encoder_virt(drm_enc);
  4121. return sde_enc->mode_info.frame_rate;
  4122. }
  4123. enum sde_intf_mode sde_encoder_get_intf_mode(struct drm_encoder *encoder)
  4124. {
  4125. struct sde_encoder_virt *sde_enc = NULL;
  4126. int i;
  4127. if (!encoder) {
  4128. SDE_ERROR("invalid encoder\n");
  4129. return INTF_MODE_NONE;
  4130. }
  4131. sde_enc = to_sde_encoder_virt(encoder);
  4132. if (sde_enc->cur_master)
  4133. return sde_enc->cur_master->intf_mode;
  4134. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4135. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  4136. if (phys)
  4137. return phys->intf_mode;
  4138. }
  4139. return INTF_MODE_NONE;
  4140. }
  4141. static void _sde_encoder_cache_hw_res_cont_splash(
  4142. struct drm_encoder *encoder,
  4143. struct sde_kms *sde_kms)
  4144. {
  4145. int i, idx;
  4146. struct sde_encoder_virt *sde_enc;
  4147. struct sde_encoder_phys *phys_enc;
  4148. struct sde_rm_hw_iter dsc_iter, pp_iter, ctl_iter, intf_iter;
  4149. sde_enc = to_sde_encoder_virt(encoder);
  4150. sde_rm_init_hw_iter(&pp_iter, encoder->base.id, SDE_HW_BLK_PINGPONG);
  4151. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  4152. sde_enc->hw_pp[i] = NULL;
  4153. if (!sde_rm_get_hw(&sde_kms->rm, &pp_iter))
  4154. break;
  4155. sde_enc->hw_pp[i] = (struct sde_hw_pingpong *) pp_iter.hw;
  4156. }
  4157. sde_rm_init_hw_iter(&dsc_iter, encoder->base.id, SDE_HW_BLK_DSC);
  4158. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  4159. sde_enc->hw_dsc[i] = NULL;
  4160. if (!sde_rm_get_hw(&sde_kms->rm, &dsc_iter))
  4161. break;
  4162. sde_enc->hw_dsc[i] = (struct sde_hw_dsc *) dsc_iter.hw;
  4163. }
  4164. /*
  4165. * If we have multiple phys encoders with one controller, make
  4166. * sure to populate the controller pointer in both phys encoders.
  4167. */
  4168. for (idx = 0; idx < sde_enc->num_phys_encs; idx++) {
  4169. phys_enc = sde_enc->phys_encs[idx];
  4170. phys_enc->hw_ctl = NULL;
  4171. sde_rm_init_hw_iter(&ctl_iter, encoder->base.id,
  4172. SDE_HW_BLK_CTL);
  4173. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4174. if (sde_rm_get_hw(&sde_kms->rm, &ctl_iter)) {
  4175. phys_enc->hw_ctl =
  4176. (struct sde_hw_ctl *) ctl_iter.hw;
  4177. pr_debug("HW CTL intf_idx:%d hw_ctl:[0x%pK]\n",
  4178. phys_enc->intf_idx, phys_enc->hw_ctl);
  4179. }
  4180. }
  4181. }
  4182. sde_rm_init_hw_iter(&intf_iter, encoder->base.id, SDE_HW_BLK_INTF);
  4183. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4184. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  4185. phys->hw_intf = NULL;
  4186. if (!sde_rm_get_hw(&sde_kms->rm, &intf_iter))
  4187. break;
  4188. phys->hw_intf = (struct sde_hw_intf *) intf_iter.hw;
  4189. }
  4190. }
  4191. /**
  4192. * sde_encoder_update_caps_for_cont_splash - update encoder settings during
  4193. * device bootup when cont_splash is enabled
  4194. * @drm_enc: Pointer to drm encoder structure
  4195. * @splash_display: Pointer to sde_splash_display corresponding to this encoder
  4196. * @enable: boolean indicates enable or displae state of splash
  4197. * @Return: true if successful in updating the encoder structure
  4198. */
  4199. int sde_encoder_update_caps_for_cont_splash(struct drm_encoder *encoder,
  4200. struct sde_splash_display *splash_display, bool enable)
  4201. {
  4202. struct sde_encoder_virt *sde_enc;
  4203. struct msm_drm_private *priv;
  4204. struct sde_kms *sde_kms;
  4205. struct drm_connector *conn = NULL;
  4206. struct sde_connector *sde_conn = NULL;
  4207. struct sde_connector_state *sde_conn_state = NULL;
  4208. struct drm_display_mode *drm_mode = NULL;
  4209. struct sde_encoder_phys *phys_enc;
  4210. int ret = 0, i;
  4211. if (!encoder) {
  4212. SDE_ERROR("invalid drm enc\n");
  4213. return -EINVAL;
  4214. }
  4215. sde_enc = to_sde_encoder_virt(encoder);
  4216. sde_kms = sde_encoder_get_kms(&sde_enc->base);
  4217. if (!sde_kms) {
  4218. SDE_ERROR("invalid sde_kms\n");
  4219. return -EINVAL;
  4220. }
  4221. priv = encoder->dev->dev_private;
  4222. if (!priv->num_connectors) {
  4223. SDE_ERROR_ENC(sde_enc, "No connectors registered\n");
  4224. return -EINVAL;
  4225. }
  4226. SDE_DEBUG_ENC(sde_enc,
  4227. "num of connectors: %d\n", priv->num_connectors);
  4228. SDE_DEBUG_ENC(sde_enc, "enable: %d\n", enable);
  4229. if (!enable) {
  4230. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4231. phys_enc = sde_enc->phys_encs[i];
  4232. if (phys_enc)
  4233. phys_enc->cont_splash_enabled = false;
  4234. }
  4235. return ret;
  4236. }
  4237. if (!splash_display) {
  4238. SDE_ERROR_ENC(sde_enc, "invalid splash data\n");
  4239. return -EINVAL;
  4240. }
  4241. for (i = 0; i < priv->num_connectors; i++) {
  4242. SDE_DEBUG_ENC(sde_enc, "connector id: %d\n",
  4243. priv->connectors[i]->base.id);
  4244. sde_conn = to_sde_connector(priv->connectors[i]);
  4245. if (!sde_conn->encoder) {
  4246. SDE_DEBUG_ENC(sde_enc,
  4247. "encoder not attached to connector\n");
  4248. continue;
  4249. }
  4250. if (sde_conn->encoder->base.id
  4251. == encoder->base.id) {
  4252. conn = (priv->connectors[i]);
  4253. break;
  4254. }
  4255. }
  4256. if (!conn || !conn->state) {
  4257. SDE_ERROR_ENC(sde_enc, "connector not found\n");
  4258. return -EINVAL;
  4259. }
  4260. sde_conn_state = to_sde_connector_state(conn->state);
  4261. if (!sde_conn->ops.get_mode_info) {
  4262. SDE_ERROR_ENC(sde_enc, "conn: get_mode_info ops not found\n");
  4263. return -EINVAL;
  4264. }
  4265. ret = sde_connector_get_mode_info(&sde_conn->base,
  4266. &encoder->crtc->state->adjusted_mode,
  4267. &sde_conn_state->mode_info);
  4268. if (ret) {
  4269. SDE_ERROR_ENC(sde_enc,
  4270. "conn: ->get_mode_info failed. ret=%d\n", ret);
  4271. return ret;
  4272. }
  4273. if (sde_conn->encoder) {
  4274. conn->state->best_encoder = sde_conn->encoder;
  4275. SDE_DEBUG_ENC(sde_enc,
  4276. "configured cstate->best_encoder to ID = %d\n",
  4277. conn->state->best_encoder->base.id);
  4278. } else {
  4279. SDE_ERROR_ENC(sde_enc, "No encoder mapped to connector=%d\n",
  4280. conn->base.id);
  4281. }
  4282. ret = sde_rm_reserve(&sde_kms->rm, encoder, encoder->crtc->state,
  4283. conn->state, false);
  4284. if (ret) {
  4285. SDE_ERROR_ENC(sde_enc,
  4286. "failed to reserve hw resources, %d\n", ret);
  4287. return ret;
  4288. }
  4289. SDE_DEBUG_ENC(sde_enc, "connector topology = %llu\n",
  4290. sde_connector_get_topology_name(conn));
  4291. drm_mode = &encoder->crtc->state->adjusted_mode;
  4292. SDE_DEBUG_ENC(sde_enc, "hdisplay = %d, vdisplay = %d\n",
  4293. drm_mode->hdisplay, drm_mode->vdisplay);
  4294. drm_set_preferred_mode(conn, drm_mode->hdisplay, drm_mode->vdisplay);
  4295. if (encoder->bridge) {
  4296. SDE_DEBUG_ENC(sde_enc, "Bridge mapped to encoder\n");
  4297. /*
  4298. * For cont-splash use case, we update the mode
  4299. * configurations manually. This will skip the
  4300. * usually mode set call when actual frame is
  4301. * pushed from framework. The bridge needs to
  4302. * be updated with the current drm mode by
  4303. * calling the bridge mode set ops.
  4304. */
  4305. if (encoder->bridge->funcs) {
  4306. SDE_DEBUG_ENC(sde_enc, "calling mode_set\n");
  4307. encoder->bridge->funcs->mode_set(encoder->bridge,
  4308. drm_mode, drm_mode);
  4309. }
  4310. } else {
  4311. SDE_ERROR_ENC(sde_enc, "No bridge attached to encoder\n");
  4312. }
  4313. _sde_encoder_cache_hw_res_cont_splash(encoder, sde_kms);
  4314. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4315. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  4316. if (!phys) {
  4317. SDE_ERROR_ENC(sde_enc,
  4318. "phys encoders not initialized\n");
  4319. return -EINVAL;
  4320. }
  4321. /* update connector for master and slave phys encoders */
  4322. phys->connector = conn;
  4323. phys->cont_splash_enabled = true;
  4324. phys->hw_pp = sde_enc->hw_pp[i];
  4325. if (phys->ops.cont_splash_mode_set)
  4326. phys->ops.cont_splash_mode_set(phys, drm_mode);
  4327. if (phys->ops.is_master && phys->ops.is_master(phys))
  4328. sde_enc->cur_master = phys;
  4329. }
  4330. return ret;
  4331. }
  4332. int sde_encoder_display_failure_notification(struct drm_encoder *enc,
  4333. bool skip_pre_kickoff)
  4334. {
  4335. struct msm_drm_thread *event_thread = NULL;
  4336. struct msm_drm_private *priv = NULL;
  4337. struct sde_encoder_virt *sde_enc = NULL;
  4338. if (!enc || !enc->dev || !enc->dev->dev_private) {
  4339. SDE_ERROR("invalid parameters\n");
  4340. return -EINVAL;
  4341. }
  4342. priv = enc->dev->dev_private;
  4343. sde_enc = to_sde_encoder_virt(enc);
  4344. if (!sde_enc->crtc || (sde_enc->crtc->index
  4345. >= ARRAY_SIZE(priv->event_thread))) {
  4346. SDE_DEBUG_ENC(sde_enc,
  4347. "invalid cached CRTC: %d or crtc index: %d\n",
  4348. sde_enc->crtc == NULL,
  4349. sde_enc->crtc ? sde_enc->crtc->index : -EINVAL);
  4350. return -EINVAL;
  4351. }
  4352. SDE_EVT32_VERBOSE(DRMID(enc));
  4353. event_thread = &priv->event_thread[sde_enc->crtc->index];
  4354. if (!skip_pre_kickoff) {
  4355. kthread_queue_work(&event_thread->worker,
  4356. &sde_enc->esd_trigger_work);
  4357. kthread_flush_work(&sde_enc->esd_trigger_work);
  4358. }
  4359. /*
  4360. * panel may stop generating te signal (vsync) during esd failure. rsc
  4361. * hardware may hang without vsync. Avoid rsc hang by generating the
  4362. * vsync from watchdog timer instead of panel.
  4363. */
  4364. sde_encoder_helper_switch_vsync(enc, true);
  4365. if (!skip_pre_kickoff)
  4366. sde_encoder_wait_for_event(enc, MSM_ENC_TX_COMPLETE);
  4367. return 0;
  4368. }
  4369. bool sde_encoder_recovery_events_enabled(struct drm_encoder *encoder)
  4370. {
  4371. struct sde_encoder_virt *sde_enc;
  4372. if (!encoder) {
  4373. SDE_ERROR("invalid drm enc\n");
  4374. return false;
  4375. }
  4376. sde_enc = to_sde_encoder_virt(encoder);
  4377. return sde_enc->recovery_events_enabled;
  4378. }
  4379. void sde_encoder_recovery_events_handler(struct drm_encoder *encoder,
  4380. bool enabled)
  4381. {
  4382. struct sde_encoder_virt *sde_enc;
  4383. if (!encoder) {
  4384. SDE_ERROR("invalid drm enc\n");
  4385. return;
  4386. }
  4387. sde_enc = to_sde_encoder_virt(encoder);
  4388. sde_enc->recovery_events_enabled = enabled;
  4389. }