dp_htt.h 28 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #ifndef _DP_HTT_H_
  20. #define _DP_HTT_H_
  21. #include <qdf_types.h>
  22. #include <qdf_lock.h>
  23. #include <qdf_nbuf.h>
  24. #include <htc_api.h>
  25. #include "cdp_txrx_cmn_struct.h"
  26. #include "dp_types.h"
  27. #ifdef HTT_LOGGER
  28. #include "dp_htt_logger.h"
  29. #else
  30. struct htt_logger;
  31. static inline
  32. void htt_interface_logging_init(struct htt_logger **htt_logger_handle,
  33. struct cdp_ctrl_objmgr_psoc *ctrl_psoc)
  34. {
  35. }
  36. static inline
  37. void htt_interface_logging_deinit(struct htt_logger *htt_logger_handle)
  38. {
  39. }
  40. static inline
  41. int htt_command_record(struct htt_logger *h, uint8_t msg_type,
  42. uint8_t *msg_data)
  43. {
  44. return 0;
  45. }
  46. static inline
  47. int htt_event_record(struct htt_logger *h, uint8_t msg_type,
  48. uint8_t *msg_data)
  49. {
  50. return 0;
  51. }
  52. static inline
  53. int htt_wbm_event_record(struct htt_logger *h, uint8_t tx_status,
  54. uint8_t *msg_data)
  55. {
  56. return 0;
  57. }
  58. #endif
  59. void htt_htc_pkt_pool_free(struct htt_soc *soc);
  60. #define HTT_TX_MUTEX_TYPE qdf_spinlock_t
  61. #define HTT_TX_MUTEX_INIT(_mutex) \
  62. qdf_spinlock_create(_mutex)
  63. #define HTT_TX_MUTEX_ACQUIRE(_mutex) \
  64. qdf_spin_lock_bh(_mutex)
  65. #define HTT_TX_MUTEX_RELEASE(_mutex) \
  66. qdf_spin_unlock_bh(_mutex)
  67. #define HTT_TX_MUTEX_DESTROY(_mutex) \
  68. qdf_spinlock_destroy(_mutex)
  69. #define DP_HTT_MAX_SEND_QUEUE_DEPTH 64
  70. #ifndef HTT_MAC_ADDR_LEN
  71. #define HTT_MAC_ADDR_LEN 6
  72. #endif
  73. #define HTT_FRAMECTRL_TYPE_MASK 0x0C
  74. #define HTT_GET_FRAME_CTRL_TYPE(_val) \
  75. (((_val) & HTT_FRAMECTRL_TYPE_MASK) >> 2)
  76. #define FRAME_CTRL_TYPE_MGMT 0x0
  77. #define FRAME_CTRL_TYPE_CTRL 0x1
  78. #define FRAME_CTRL_TYPE_DATA 0x2
  79. #define FRAME_CTRL_TYPE_RESV 0x3
  80. #define HTT_FRAMECTRL_DATATYPE 0x08
  81. #define HTT_PPDU_DESC_MAX_DEPTH 16
  82. #define DP_SCAN_PEER_ID 0xFFFF
  83. #define HTT_RX_DELBA_WIN_SIZE_M 0x0000FC00
  84. #define HTT_RX_DELBA_WIN_SIZE_S 10
  85. #define HTT_RX_DELBA_WIN_SIZE_GET(word) \
  86. (((word) & HTT_RX_DELBA_WIN_SIZE_M) >> HTT_RX_DELBA_WIN_SIZE_S)
  87. /*
  88. * Set the base misclist size to HTT copy engine source ring size
  89. * to guarantee that a packet on the misclist wont be freed while it
  90. * is sitting in the copy engine.
  91. */
  92. #define DP_HTT_HTC_PKT_MISCLIST_SIZE 2048
  93. #define HTT_T2H_MAX_MSG_SIZE 2048
  94. #define HTT_T2H_EXT_STATS_TLV_START_OFFSET 3
  95. /*
  96. * Below offset are based on htt_ppdu_stats_common_tlv
  97. * defined in htt_ppdu_stats.h
  98. */
  99. #define HTT_PPDU_STATS_COMMON_TLV_TLV_HDR_OFFSET 0
  100. #define HTT_PPDU_STATS_COMMON_TLV_PPDU_ID_OFFSET 1
  101. #define HTT_PPDU_STATS_COMMON_TLV_RING_ID_SCH_CMD_ID_OFFSET 2
  102. #define HTT_PPDU_STATS_COMMON_TLV_QTYPE_FRM_TYPE_OFFSET 3
  103. #define HTT_PPDU_STATS_COMMON_TLV_CHAIN_MASK_OFFSET 4
  104. #define HTT_PPDU_STATS_COMMON_TLV_FES_DUR_US_OFFSET 5
  105. #define HTT_PPDU_STATS_COMMON_TLV_SCH_EVAL_START_TSTMP_L32_US_OFFSET 6
  106. #define HTT_PPDU_STATS_COMMON_TLV_SCH_END_TSTMP_US_OFFSET 7
  107. #define HTT_PPDU_STATS_COMMON_TLV_START_TSTMP_L32_US_OFFSET 8
  108. #define HTT_PPDU_STATS_COMMON_TLV_CHAN_MHZ_PHY_MODE_OFFSET 9
  109. #define HTT_PPDU_STATS_COMMON_TLV_CCA_DELTA_TIME_US_OFFSET 10
  110. #define HTT_PPDU_STATS_COMMON_TLV_RXFRM_DELTA_TIME_US_OFFSET 11
  111. #define HTT_PPDU_STATS_COMMON_TLV_TXFRM_DELTA_TIME_US_OFFSET 12
  112. #define HTT_PPDU_STATS_COMMON_TLV_RESV_NUM_UL_BEAM_OFFSET 13
  113. #define HTT_PPDU_STATS_COMMON_TLV_START_TSTMP_U32_US_OFFSET 14
  114. #define HTT_PPDU_STATS_COMMON_TLV_BSSCOLOR_OBSS_PSR_OFFSET 15
  115. /* get index for field in htt_ppdu_stats_common_tlv */
  116. #define HTT_GET_STATS_CMN_INDEX(index) \
  117. HTT_PPDU_STATS_COMMON_TLV_##index##_OFFSET
  118. #define HTT_VDEV_STATS_TLV_SOC_DROP_CNT_OFFSET 1
  119. #define HTT_VDEV_STATS_TLV_HDR_OFFSET 0
  120. #define HTT_VDEV_STATS_TLV_VDEV_ID_OFFSET 1
  121. #define HTT_VDEV_STATS_TLV_RX_BYTE_CNT_OFFSET 2
  122. #define HTT_VDEV_STATS_TLV_RX_PKT_CNT_OFFSET 4
  123. #define HTT_VDEV_STATS_TLV_TX_SUCCESS_BYTE_CNT_OFFSET 6
  124. #define HTT_VDEV_STATS_TLV_TX_SUCCESS_PKT_CNT_OFFSET 8
  125. #define HTT_VDEV_STATS_TLV_TX_RETRY_PKT_CNT_OFFSET 10
  126. #define HTT_VDEV_STATS_TLV_TX_DROP_PKT_CNT_OFFSET 12
  127. #define HTT_VDEV_STATS_TLV_TX_AGE_OUT_PKT_CNT_OFFSET 14
  128. #define HTT_VDEV_STATS_TLV_TX_RETRY_BYTE_CNT_OFFSET 16
  129. #define HTT_VDEV_STATS_TLV_TX_DROP_BYTE_CNT_OFFSET 18
  130. #define HTT_VDEV_STATS_TLV_TX_AGE_OUT_BYTE_CNT_OFFSET 20
  131. #define HTT_VDEV_STATS_GET_INDEX(index) \
  132. HTT_VDEV_STATS_TLV_##index##_OFFSET
  133. #define HTT_VDEV_STATS_U32_SHIFT 0x20
  134. #define HTT_VDEV_STATS_U32_MASK 0xFFFFFFFF00000000
  135. #define HTT_VDEV_STATS_L32_MASK 0x00000000FFFFFFFF
  136. #define HTT_VDEV_GET_STATS_U64(msg_word) \
  137. (((((uint64_t)(*(((uint32_t *)msg_word) + 1))) & HTT_VDEV_STATS_L32_MASK) << \
  138. HTT_VDEV_STATS_U32_SHIFT) | ((*(uint32_t *)msg_word) & HTT_VDEV_STATS_L32_MASK))
  139. #define HTT_VDEV_GET_STATS_U32(msg_word) \
  140. ((*(uint32_t *)msg_word) & HTT_VDEV_STATS_L32_MASK)
  141. #define MAX_SCHED_STARVE 100000
  142. #define WRAP_DROP_TSF_DELTA 10000
  143. #define MAX_TSF_32 0xFFFFFFFF
  144. #define dp_htt_alert(params...) QDF_TRACE_FATAL(QDF_MODULE_ID_DP_HTT, params)
  145. #define dp_htt_err(params...) QDF_TRACE_ERROR(QDF_MODULE_ID_DP_HTT, params)
  146. #define dp_htt_warn(params...) QDF_TRACE_WARN(QDF_MODULE_ID_DP_HTT, params)
  147. #define dp_htt_info(params...) \
  148. __QDF_TRACE_FL(QDF_TRACE_LEVEL_INFO_HIGH, QDF_MODULE_ID_DP_HTT, ## params)
  149. #define dp_htt_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_DP_HTT, params)
  150. #define dp_htt_tx_stats_alert(params...) QDF_TRACE_FATAL(QDF_MODULE_ID_DP_HTT_TX_STATS, params)
  151. #define dp_htt_tx_stats_err(params...) QDF_TRACE_ERROR(QDF_MODULE_ID_DP_HTT_TX_STATS, params)
  152. #define dp_htt_tx_stats_warn(params...) QDF_TRACE_WARN(QDF_MODULE_ID_DP_HTT_TX_STATS, params)
  153. #define dp_htt_tx_stats_info(params...) \
  154. __QDF_TRACE_FL(QDF_TRACE_LEVEL_INFO_HIGH, QDF_MODULE_ID_DP_HTT_TX_STATS, ## params)
  155. #define dp_htt_tx_stats_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_DP_HTT_TX_STATS, params)
  156. /**
  157. * enum dp_full_mon_config - enum to enable/disable full monitor mode
  158. *
  159. * @DP_FULL_MON_DISABLE: Disable full monitor mode
  160. * @DP_FULL_MON_ENABLE: Enable full monitor mode
  161. */
  162. enum dp_full_mon_config {
  163. DP_FULL_MON_DISABLE,
  164. DP_FULL_MON_ENABLE,
  165. };
  166. struct dp_htt_htc_pkt {
  167. void *soc_ctxt;
  168. qdf_dma_addr_t nbuf_paddr;
  169. HTC_PACKET htc_pkt;
  170. };
  171. struct dp_htt_htc_pkt_union {
  172. union {
  173. struct dp_htt_htc_pkt pkt;
  174. struct dp_htt_htc_pkt_union *next;
  175. } u;
  176. };
  177. struct dp_htt_timestamp {
  178. long *umac_ttt;
  179. long *lmac_ttt;
  180. };
  181. struct htt_soc {
  182. struct cdp_ctrl_objmgr_psoc *ctrl_psoc;
  183. struct dp_soc *dp_soc;
  184. hal_soc_handle_t hal_soc;
  185. struct dp_htt_timestamp pdevid_tt[MAX_PDEV_CNT];
  186. /* htt_logger handle */
  187. struct htt_logger *htt_logger_handle;
  188. HTC_HANDLE htc_soc;
  189. qdf_device_t osdev;
  190. HTC_ENDPOINT_ID htc_endpoint;
  191. struct dp_htt_htc_pkt_union *htt_htc_pkt_freelist;
  192. struct dp_htt_htc_pkt_union *htt_htc_pkt_misclist;
  193. struct {
  194. u_int8_t major;
  195. u_int8_t minor;
  196. } tgt_ver;
  197. struct {
  198. u_int8_t major;
  199. u_int8_t minor;
  200. } wifi_ip_ver;
  201. struct {
  202. int htc_err_cnt;
  203. int htc_pkt_free;
  204. int skip_count;
  205. int fail_count;
  206. /* rtpm put skip count for ver req msg */
  207. int htt_ver_req_put_skip;
  208. } stats;
  209. HTT_TX_MUTEX_TYPE htt_tx_mutex;
  210. };
  211. #ifdef QCA_MONITOR_2_0_SUPPORT
  212. /**
  213. * struct dp_tx_mon_downstream_tlv_config - Enable/Disable TxMon
  214. * downstream TLVs
  215. * tx_fes_setup: TX_FES_SETUP TLV
  216. * tx_peer_entry: TX_PEER_ENTRY TLV
  217. * tx_queue_extension: TX_QUEUE_EXTENSION TLV
  218. * tx_last_mpdu_end: TX_LAST_MPDU_END TLV
  219. * tx_last_mpdu_fetched: TX_LAST_MPDU_FETCHED TLV
  220. * tx_data_sync: TX_DATA_SYNC TLV
  221. * pcu_ppdu_setup_init: PCU_PPDU_SETUP_INIT TLV
  222. * fw2s_mon: FW2S_MON TLV
  223. * tx_loopback_setup: TX_LOOPBACK_SETUP TLV
  224. * sch_critical_tlv_ref: SCH_CRITICAL_TLV_REF TLV
  225. * ndp_preamble_done: NDP_PREAMBLE_DONE TLV
  226. * tx_raw_frame_setup: TX_RAW_OR_NATIVE_FRAME_SETUP TLV
  227. * txpcu_user_setup: TXPCU_USER_SETUP TLV
  228. * rxpcu_setup: RXPCU_SETUP TLV
  229. * rxpcu_setup_complete: RXPCU_SETUP_COMPLETE TLV
  230. * coex_tx_req: COEX_TX_REQ TLV
  231. * rxpcu_user_setup: RXPCU_USER_SETUP TLV
  232. * rxpcu_user_setup_ext: RXPCU_USER_SETUP_EXT TLV
  233. * wur_data: WUR_DATA TLV
  234. * tqm_mpdu_global_start: TQM_MPDU_GLOBAL_START
  235. * tx_fes_setup_complete: TX_FES_SETUP_COMPLETE TLV
  236. * scheduler_end: SCHEDULER_END TLV
  237. * sch_wait_instr_tx_path: SCH_WAIT_INSTR_TX_PATH TLV
  238. *
  239. */
  240. struct dp_tx_mon_downstream_tlv_config {
  241. uint32_t tx_fes_setup:1,
  242. tx_peer_entry:1,
  243. tx_queue_extension:1,
  244. tx_last_mpdu_end:1,
  245. tx_last_mpdu_fetched:1,
  246. tx_data_sync:1,
  247. pcu_ppdu_setup_init:1,
  248. fw2s_mon:1,
  249. tx_loopback_setup:1,
  250. sch_critical_tlv_ref:1,
  251. ndp_preamble_done:1,
  252. tx_raw_frame_setup:1,
  253. txpcu_user_setup:1,
  254. rxpcu_setup:1,
  255. rxpcu_setup_complete:1,
  256. coex_tx_req:1,
  257. rxpcu_user_setup:1,
  258. rxpcu_user_setup_ext:1,
  259. wur_data:1,
  260. tqm_mpdu_global_start:1,
  261. tx_fes_setup_complete:1,
  262. scheduler_end:1,
  263. sch_wait_instr_tx_path:1;
  264. };
  265. /**
  266. * struct dp_tx_mon_upstream_tlv_config - Enable/Disable TxMon
  267. * upstream TLVs
  268. * rx_response_required_info: RX_RESPONSE_REQUIRED_INFO
  269. * TLV
  270. * response_start_status: RESPONSE_START_STATUS TLV
  271. * response_end_status: RESPONSE_END_STATUS TLV
  272. * tx_fes_status_start: TX_FES_STATUS_START TLV
  273. * tx_fes_status_start_ppdu: TX_FES_STATUS_START_PPDU TLV
  274. * tx_fes_status_user_ppdu: TX_FES_STATUS_USER_PPDU TLV
  275. * tx_fes_status_ack_or_ba: TX_FES_STATUS_ACK_OR_BA TLV
  276. * tx_fes_status_1k_ba: TX_FES_STATUS_1K_BA TLV
  277. * tx_fes_status_start_prot: TX_FES_STATUS_START_PROTO TLV
  278. * tx_fes_status_user_response: TX_FES_STATUS_USER_RESPONSE TLV
  279. * rx_frame_bitmap_ack: RX_FRAME_BITMAP_ACK TLV
  280. * rx_frame_1k_bitmap_ack: RX_FRAME_1K_BITMAP_ACK TLV
  281. * coex_tx_status: COEX_TX_STATUS TLV
  282. * recevied_response_info: RECEIVED_RESPONSE_INFO TLV
  283. * recevied_response_info_p2: RECEIVED_RESPONSE_INFO_PART2 TLV
  284. * ofdma_trigger_details: OFDMA_TRIGGER_DETAILS
  285. * recevied_trigger_info: RECEIVED_TRIGGER_INFO
  286. * pdg_tx_request: PDG_TX_REQUEST
  287. * pdg_response: PDG_RESPONSE
  288. * pdg_trig_response: PDG_TRIG_RESPONSE
  289. * trigger_response_tx_done: TRIGGER_RESPONSE_TX_DONE
  290. * prot_tx_end: PROT_TX_END
  291. * ppdu_tx_end: PPDU_TX_END
  292. * r2r_status_end: R2R_STATUS_END
  293. * flush_req: FLUSH_REQ
  294. * mactx_phy_desc: MACTX_PHY_DESC
  295. * mactx_user_desc_cmn: MACTX_USER_DESC_COMMON
  296. * mactx_user_desc_per_usr: MACTX_USER_DESC_PER_USER
  297. * tqm_acked_1k_mpdu: TQM_ACKED_1K_MPDU
  298. * tqm_acked_mpdu: TQM_ACKED_MPDU
  299. * tqm_update_tx_mpdu_count: TQM_UPDATE_TX_MPDU_COUNT
  300. * phytx_ppdu_header_info_request: PHYTX_PPDU_HEADER_INFO_REQUEST
  301. * u_sig_eht_su_mu: U_SIG_EHT_SU_MU
  302. * u_sig_eht_su: U_SIG_EHT_SU
  303. * eht_sig_usr_su: EHT_SIG_USR_SU
  304. * eht_sig_usr_mu_mimo: EHT_SIG_USR_MU_MIMO
  305. * eht_sig_usr_ofdma: EHT_SIG_USR_MU_MIMO
  306. * he_sig_a_su: HE_SIG_A_SU
  307. * he_sig_a_mu_dl: HE_SIG_A_MU_DL
  308. * he_sig_a_mu_ul: HE_SIG_A_MU_UL
  309. * he_sig_b1_mu: HE_SIG_B1_MU
  310. * he_sig_b2_mu: HE_SIG_B2_MU
  311. * he_sig_b2_ofdma: HE_SIG_B2_OFDMA
  312. * vht_sig_b_mu160: VHT_SIG_B_MU160
  313. * vht_sig_b_mu80: VHT_SIG_B_MU80
  314. * vht_sig_b_mu40: VHT_SIG_B_MU40
  315. * vht_sig_b_mu20: VHT_SIG_B_MU20
  316. * vht_sig_b_su160: VHT_SIG_B_SU160
  317. * vht_sig_b_su80: VHT_SIG_B_SU80
  318. * vht_sig_b_su40: VHT_SIG_B_SU40
  319. * vht_sig_b_su20: VHT_SIG_B_SU20
  320. * vht_sig_a: VHT_SIG_A
  321. * ht_sig: HT_SIG
  322. * l_sig_b: L_SIG_B
  323. * l_sig_a: L_SIG_A
  324. * tx_service: TX_SERVICE
  325. * txpcu_buf_status: TXPCU_BUFFER_STATUS
  326. * txpcu_user_buf_status: TXPCU_USER_BUFFER_STATUS
  327. * txdma_stop_request: TXDMA_STOP_REQUEST
  328. * expected_response: EXPECTED_RESPONSE
  329. * tx_mpdu_count_transfer_end: TX_MPDU_COUNT_TRANSFER_END
  330. * rx_trig_info: RX_TRIG_INFO
  331. * rxpcu_tx_setup_clear: RXPCU_TX_SETUP_CLEAR
  332. * rx_frame_bitmap_req: RX_FRAME_BITMAP_REQ
  333. * rx_phy_sleep: RX_PHY_SLEEP
  334. * txpcu_preamble_done: TXPCU_PREAMBLE_DONE
  335. * txpcu_phytx_debug32: TXPCU_PHYTX_DEBUG32
  336. * txpcu_phytx_other_transmit_info32: TXPCU_PHYTX_OTHER_TRANSMIT_INFO32
  337. * rx_ppdu_noack_report: RX_PPDU_NO_ACK_REPORT
  338. * rx_ppdu_ack_report: RX_PPDU_ACK_REPORT
  339. * coex_rx_status: COEX_RX_STATUS
  340. * rx_start_param: RX_START_PARAM
  341. * tx_cbf_info: TX_CBF_INFO
  342. * rxpcu_early_rx_indication: RXPCU_EARLY_RX_INDICATION
  343. * received_response_user_7_0: RECEIVED_RESPONSE_USER_7_0
  344. * received_response_user_15_8: RECEIVED_RESPONSE_USER_15_8
  345. * received_response_user_23_16: RECEIVED_RESPONSE_USER_23_16
  346. * received_response_user_31_24: RECEIVED_RESPONSE_USER_31_24
  347. * received_response_user_36_32: RECEIVED_RESPONSE_USER_36_32
  348. * rx_pm_info: RX_PM_INFO
  349. * rx_preamble: RX_PREAMBLE
  350. * others: OTHERS
  351. * mactx_pre_phy_desc: MACTX_PRE_PHY_DESC
  352. *
  353. */
  354. struct dp_tx_mon_upstream_tlv_config {
  355. uint32_t rx_response_required_info:1,
  356. response_start_status:1,
  357. response_end_status:1,
  358. tx_fes_status_start:1,
  359. tx_fes_status_end:1,
  360. tx_fes_status_start_ppdu:1,
  361. tx_fes_status_user_ppdu:1,
  362. tx_fes_status_ack_or_ba:1,
  363. tx_fes_status_1k_ba:1,
  364. tx_fes_status_start_prot:1,
  365. tx_fes_status_prot:1,
  366. tx_fes_status_user_response:1,
  367. rx_frame_bitmap_ack:1,
  368. rx_frame_1k_bitmap_ack:1,
  369. coex_tx_status:1,
  370. recevied_response_info:1,
  371. recevied_response_info_p2:1,
  372. ofdma_trigger_details:1,
  373. recevied_trigger_info:1,
  374. pdg_tx_request:1,
  375. pdg_response:1,
  376. pdg_trig_response:1,
  377. trigger_response_tx_done:1,
  378. prot_tx_end:1,
  379. ppdu_tx_end:1,
  380. r2r_status_end:1,
  381. flush_req:1,
  382. mactx_phy_desc:1,
  383. mactx_user_desc_cmn:1,
  384. mactx_user_desc_per_usr:1;
  385. uint32_t tqm_acked_1k_mpdu:1,
  386. tqm_acked_mpdu:1,
  387. tqm_update_tx_mpdu_count:1,
  388. phytx_ppdu_header_info_request:1,
  389. u_sig_eht_su_mu:1,
  390. u_sig_eht_su:1,
  391. u_sig_eht_tb:1,
  392. eht_sig_usr_su:1,
  393. eht_sig_usr_mu_mimo:1,
  394. eht_sig_usr_ofdma:1,
  395. he_sig_a_su:1,
  396. he_sig_a_mu_dl:1,
  397. he_sig_a_mu_ul:1,
  398. he_sig_b1_mu:1,
  399. he_sig_b2_mu:1,
  400. he_sig_b2_ofdma:1,
  401. vht_sig_b_mu160:1,
  402. vht_sig_b_mu80:1,
  403. vht_sig_b_mu40:1,
  404. vht_sig_b_mu20:1,
  405. vht_sig_b_su160:1,
  406. vht_sig_b_su80:1,
  407. vht_sig_b_su40:1,
  408. vht_sig_b_su20:1,
  409. vht_sig_a:1,
  410. ht_sig:1,
  411. l_sig_b:1,
  412. l_sig_a:1,
  413. tx_service:1;
  414. uint32_t txpcu_buf_status:1,
  415. txpcu_user_buf_status:1,
  416. txdma_stop_request:1,
  417. expected_response:1,
  418. tx_mpdu_count_transfer_end:1,
  419. rx_trig_info:1,
  420. rxpcu_tx_setup_clear:1,
  421. rx_frame_bitmap_req:1,
  422. rx_phy_sleep:1,
  423. txpcu_preamble_done:1,
  424. txpcu_phytx_debug32:1,
  425. txpcu_phytx_other_transmit_info32:1,
  426. rx_ppdu_noack_report:1,
  427. rx_ppdu_ack_report:1,
  428. coex_rx_status:1,
  429. rx_start_param:1,
  430. tx_cbf_info:1,
  431. rxpcu_early_rx_indication:1,
  432. received_response_user_7_0:1,
  433. received_response_user_15_8:1,
  434. received_response_user_23_16:1,
  435. received_response_user_31_24:1,
  436. received_response_user_36_32:1,
  437. rx_pm_info:1,
  438. rx_preamble:1,
  439. others:1,
  440. mactx_pre_phy_desc:1;
  441. };
  442. /**
  443. * struct dp_tx_mon_wordmask_config - Tx monitor word mask
  444. * tx_fes_setup: TX_FES_SETUP TLV word mask
  445. * tx_peer_entry: TX_PEER_ENTRY TLV word mask
  446. * tx_queue_ext: TX_QUEUE_EXTENSION TLV word mask
  447. * tx_msdu_start: TX_MSDU_START TLV word mask
  448. * tx_mpdu_start: TX_MPDU_START TLV word mask
  449. * pcu_ppdu_setup_init: PCU_PPDU_SETUP TLV word mask
  450. * rxpcu_user_setup: RXPCU_USER_SETUP TLV word mask
  451. */
  452. struct dp_tx_mon_wordmask_config {
  453. uint16_t tx_fes_setup;
  454. uint16_t tx_peer_entry;
  455. uint16_t tx_queue_ext;
  456. uint16_t tx_msdu_start;
  457. uint16_t tx_mpdu_start;
  458. uint16_t pcu_ppdu_setup_init;
  459. uint16_t rxpcu_user_setup;
  460. };
  461. /**
  462. * struct htt_tx_ring_tlv_filter - Tx ring TLV filter
  463. * enable/disable.
  464. * @dtlvs: enable/disable downstream TLVs
  465. * @utlvs: enable/disable upstream TLVs
  466. * @wmask: enable/disbale word mask subscription
  467. * @mgmt_filter: enable/disable mgmt packets
  468. * @data_filter: enable/disable data packets
  469. * @ctrl_filter: enable/disable ctrl packets
  470. * @mgmt_dma_length: configure length for mgmt packet
  471. * @ctrl_dma_length: configure length for ctrl packet
  472. * @data_dma_length: configure length for data packet
  473. * @mgmt_mpdu_end: enable mpdu end tlv for mgmt
  474. * @mgmt_msdu_end: enable msdu end tlv for mgmt
  475. * @mgmt_msdu_start: enable msdu start tlv for mgmt
  476. * @mgmt_mpdu_start: enable mpdu start tlv for mgmt
  477. * @ctrl_mpdu_end: enable mpdu end tlv for ctrl
  478. * @ctrl_msdu_end: enable msdu end tlv for ctrl
  479. * @ctrl_msdu_start: enable msdu start tlv for ctrl
  480. * @ctrl_mpdu_start: enable mpdu start tlv for ctrl
  481. * @data_mpdu_end: enable mpdu end tlv for data
  482. * @data_msdu_end: enable msdu end tlv for data
  483. * @data_msdu_start: enable msdu start tlv for data
  484. * @data_mpdu_start: enable mpdu start tlv for data
  485. * @mgmt_mpdu_log: enable mgmt mpdu level logging
  486. * @ctrl_mpdu_log: enable ctrl mpdu level logging
  487. * @data_mpdu_log: enable data mpdu level logging
  488. *
  489. * NOTE: Do not change the layout of this structure
  490. */
  491. struct htt_tx_ring_tlv_filter {
  492. struct dp_tx_mon_downstream_tlv_config dtlvs;
  493. struct dp_tx_mon_upstream_tlv_config utlvs;
  494. struct dp_tx_mon_wordmask_config wmask;
  495. uint16_t mgmt_filter;
  496. uint16_t data_filter;
  497. uint16_t ctrl_filter;
  498. uint16_t mgmt_dma_length:3,
  499. ctrl_dma_length:3,
  500. data_dma_length:3;
  501. uint16_t mgmt_mpdu_end:1,
  502. mgmt_msdu_end:1,
  503. mgmt_msdu_start:1,
  504. mgmt_mpdu_start:1,
  505. ctrl_mpdu_end:1,
  506. ctrl_msdu_end:1,
  507. ctrl_msdu_start:1,
  508. ctrl_mpdu_start:1,
  509. data_mpdu_end:1,
  510. data_msdu_end:1,
  511. data_msdu_start:1,
  512. data_mpdu_start:1;
  513. uint8_t mgmt_mpdu_log:1,
  514. ctrl_mpdu_log:1,
  515. data_mpdu_log:1;
  516. };
  517. #endif /* QCA_MONITOR_2_0_SUPPORT */
  518. /**
  519. * struct htt_rx_ring_tlv_filter - Rx ring TLV filter
  520. * enable/disable.
  521. * @mpdu_start: enable/disable MPDU start TLV
  522. * @msdu_start: enable/disable MSDU start TLV
  523. * @packet: enable/disable PACKET TLV
  524. * @msdu_end: enable/disable MSDU end TLV
  525. * @mpdu_end: enable/disable MPDU end TLV
  526. * @packet_header: enable/disable PACKET header TLV
  527. * @attention: enable/disable ATTENTION TLV
  528. * @ppdu_start: enable/disable PPDU start TLV
  529. * @ppdu_end: enable/disable PPDU end TLV
  530. * @ppdu_end_user_stats: enable/disable PPDU user stats TLV
  531. * @ppdu_end_user_stats_ext: enable/disable PPDU user stats ext TLV
  532. * @ppdu_end_status_done: enable/disable PPDU end status done TLV
  533. * @enable_fp: enable/disable FP packet
  534. * @enable_md: enable/disable MD packet
  535. * @enable_mo: enable/disable MO packet
  536. * @enable_mgmt: enable/disable MGMT packet
  537. * @enable_ctrl: enable/disable CTRL packet
  538. * @enable_data: enable/disable DATA packet
  539. * @offset_valid: Flag to indicate if below offsets are valid
  540. * @rx_packet_offset: Offset of packet payload
  541. * @rx_header_offset: Offset of rx_header tlv
  542. * @rx_mpdu_end_offset: Offset of rx_mpdu_end tlv
  543. * @rx_mpdu_start_offset: Offset of rx_mpdu_start tlv
  544. * @rx_msdu_end_offset: Offset of rx_msdu_end tlv
  545. * @rx_msdu_start_offset: Offset of rx_msdu_start tlv
  546. * @rx_attn_offset: Offset of rx_attention tlv
  547. * @rx_mpdu_start_wmask: word mask for mpdu start tlv
  548. * @rx_mpdu_end_wmask: word mask for mpdu end tlv
  549. * @rx_msdu_end_tlv: word mask for msdu end tlv
  550. * @rx_pkt_tlv_offset: rx pkt tlv offset
  551. * @mgmt_dma_length: configure length for mgmt packet
  552. * @ctrl_dma_length: configure length for ctrl packet
  553. * @data_dma_length: configure length for data packet
  554. * @mgmt_mpdu_log: enable mgmt mpdu level logging
  555. * @ctrl_mpdu_log: enable ctrl mpdu level logging
  556. * @data_mpdu_log: enable data mpdu level logging
  557. *
  558. * NOTE: Do not change the layout of this structure
  559. */
  560. struct htt_rx_ring_tlv_filter {
  561. u_int32_t mpdu_start:1,
  562. msdu_start:1,
  563. packet:1,
  564. msdu_end:1,
  565. mpdu_end:1,
  566. packet_header:1,
  567. attention:1,
  568. ppdu_start:1,
  569. ppdu_end:1,
  570. ppdu_end_user_stats:1,
  571. ppdu_end_user_stats_ext:1,
  572. ppdu_end_status_done:1,
  573. header_per_msdu:1,
  574. enable_fp:1,
  575. enable_md:1,
  576. enable_mo:1;
  577. u_int32_t fp_mgmt_filter:16,
  578. mo_mgmt_filter:16;
  579. u_int32_t fp_ctrl_filter:16,
  580. mo_ctrl_filter:16;
  581. u_int32_t fp_data_filter:16,
  582. mo_data_filter:16;
  583. u_int16_t md_data_filter;
  584. u_int16_t md_mgmt_filter;
  585. u_int16_t md_ctrl_filter;
  586. bool offset_valid;
  587. uint16_t rx_packet_offset;
  588. uint16_t rx_header_offset;
  589. uint16_t rx_mpdu_end_offset;
  590. uint16_t rx_mpdu_start_offset;
  591. uint16_t rx_msdu_end_offset;
  592. uint16_t rx_msdu_start_offset;
  593. uint16_t rx_attn_offset;
  594. #ifdef QCA_MONITOR_2_0_SUPPORT
  595. uint16_t rx_mpdu_start_wmask;
  596. uint16_t rx_mpdu_end_wmask;
  597. uint16_t rx_msdu_end_wmask;
  598. uint16_t rx_pkt_tlv_offset;
  599. uint16_t mgmt_dma_length:3,
  600. ctrl_dma_length:3,
  601. data_dma_lepngth:3,
  602. mgmt_mpdu_log:1,
  603. ctrl_mpdu_log:1,
  604. data_mpdu_log:1;
  605. #endif
  606. };
  607. /**
  608. * struct dp_htt_rx_flow_fst_setup - Rx FST setup message
  609. * @pdev_id: DP Pdev identifier
  610. * @max_entries: Size of Rx FST in number of entries
  611. * @max_search: Number of collisions allowed
  612. * @base_addr_lo: lower 32-bit physical address
  613. * @base_addr_hi: upper 32-bit physical address
  614. * @ip_da_sa_prefix: IPv4 prefix to map to IPv6 address scheme
  615. * @hash_key_len: Rx FST hash key size
  616. * @hash_key: Rx FST Toeplitz hash key
  617. */
  618. struct dp_htt_rx_flow_fst_setup {
  619. uint8_t pdev_id;
  620. uint32_t max_entries;
  621. uint32_t max_search;
  622. uint32_t base_addr_lo;
  623. uint32_t base_addr_hi;
  624. uint32_t ip_da_sa_prefix;
  625. uint32_t hash_key_len;
  626. uint8_t *hash_key;
  627. };
  628. /**
  629. * enum dp_htt_flow_fst_operation - FST related operations allowed
  630. * @DP_HTT_FST_CACHE_OP_NONE: Cache no-op
  631. * @DP_HTT_FST_CACHE_INVALIDATE_ENTRY: Invalidate single cache entry
  632. * @DP_HTT_FST_CACHE_INVALIDATE_FULL: Invalidate entire cache
  633. * @DP_HTT_FST_ENABLE: Bypass FST is enabled
  634. * @DP_HTT_FST_DISABLE: Disable bypass FST
  635. */
  636. enum dp_htt_flow_fst_operation {
  637. DP_HTT_FST_CACHE_OP_NONE,
  638. DP_HTT_FST_CACHE_INVALIDATE_ENTRY,
  639. DP_HTT_FST_CACHE_INVALIDATE_FULL,
  640. DP_HTT_FST_ENABLE,
  641. DP_HTT_FST_DISABLE
  642. };
  643. /**
  644. * struct dp_htt_rx_flow_fst_setup - Rx FST setup message
  645. * @pdev_id: DP Pdev identifier
  646. * @op_code: FST operation to be performed by FW/HW
  647. * @rx_flow: Rx Flow information on which operation is to be performed
  648. */
  649. struct dp_htt_rx_flow_fst_operation {
  650. uint8_t pdev_id;
  651. enum dp_htt_flow_fst_operation op_code;
  652. struct cdp_rx_flow_info *rx_flow;
  653. };
  654. /**
  655. * struct dp_htt_rx_fisa_config - Rx fisa config
  656. * @pdev_id: DP Pdev identifier
  657. * @fisa_timeout: fisa aggregation timeout
  658. */
  659. struct dp_htt_rx_fisa_cfg {
  660. uint8_t pdev_id;
  661. uint32_t fisa_timeout;
  662. };
  663. /*
  664. * htt_htc_pkt_alloc() - Allocate HTC packet buffer
  665. * @htt_soc: HTT SOC handle
  666. *
  667. * Return: Pointer to htc packet buffer
  668. */
  669. struct dp_htt_htc_pkt *htt_htc_pkt_alloc(struct htt_soc *soc);
  670. /*
  671. * htt_htc_pkt_free() - Free HTC packet buffer
  672. * @htt_soc: HTT SOC handle
  673. */
  674. void
  675. htt_htc_pkt_free(struct htt_soc *soc, struct dp_htt_htc_pkt *pkt);
  676. #define HTT_HTC_PKT_STATUS_SUCCESS \
  677. ((pkt->htc_pkt.Status != QDF_STATUS_E_CANCELED) && \
  678. (pkt->htc_pkt.Status != QDF_STATUS_E_RESOURCES))
  679. #ifdef ENABLE_CE4_COMP_DISABLE_HTT_HTC_MISC_LIST
  680. static void
  681. htt_htc_misc_pkt_list_add(struct htt_soc *soc, struct dp_htt_htc_pkt *pkt)
  682. {
  683. }
  684. #else /* ENABLE_CE4_COMP_DISABLE_HTT_HTC_MISC_LIST */
  685. /*
  686. * htt_htc_misc_pkt_list_add() - Add pkt to misc list
  687. * @htt_soc: HTT SOC handle
  688. * @dp_htt_htc_pkt: pkt to be added to list
  689. */
  690. void
  691. htt_htc_misc_pkt_list_add(struct htt_soc *soc, struct dp_htt_htc_pkt *pkt);
  692. #endif /* ENABLE_CE4_COMP_DISABLE_HTT_HTC_MISC_LIST */
  693. /**
  694. * DP_HTT_SEND_HTC_PKT() - Send htt packet from host
  695. * @soc : HTT SOC handle
  696. * @pkt: pkt to be send
  697. * @cmd : command to be recorded in dp htt logger
  698. * @buf : Pointer to buffer needs to be recored for above cmd
  699. *
  700. * Return: None
  701. */
  702. static inline QDF_STATUS DP_HTT_SEND_HTC_PKT(struct htt_soc *soc,
  703. struct dp_htt_htc_pkt *pkt,
  704. uint8_t cmd, uint8_t *buf)
  705. {
  706. QDF_STATUS status;
  707. htt_command_record(soc->htt_logger_handle, cmd, buf);
  708. status = htc_send_pkt(soc->htc_soc, &pkt->htc_pkt);
  709. if (status == QDF_STATUS_SUCCESS && HTT_HTC_PKT_STATUS_SUCCESS)
  710. htt_htc_misc_pkt_list_add(soc, pkt);
  711. else
  712. soc->stats.fail_count++;
  713. return status;
  714. }
  715. QDF_STATUS dp_htt_rx_fisa_config(struct dp_pdev *pdev,
  716. struct dp_htt_rx_fisa_cfg *fisa_config);
  717. /*
  718. * htt_soc_initialize() - SOC level HTT initialization
  719. * @htt_soc: Opaque htt SOC handle
  720. * @ctrl_psoc: Opaque ctrl SOC handle
  721. * @htc_soc: SOC level HTC handle
  722. * @hal_soc: Opaque HAL SOC handle
  723. * @osdev: QDF device
  724. *
  725. * Return: HTT handle on success; NULL on failure
  726. */
  727. void *
  728. htt_soc_initialize(struct htt_soc *htt_soc,
  729. struct cdp_ctrl_objmgr_psoc *ctrl_psoc,
  730. HTC_HANDLE htc_soc,
  731. hal_soc_handle_t hal_soc_hdl, qdf_device_t osdev);
  732. /*
  733. * htt_soc_attach() - attach DP and HTT SOC
  734. * @soc: DP SOC handle
  735. * @htc_hdl: HTC handle
  736. *
  737. * Return: htt_soc handle on Success, NULL on Failure
  738. */
  739. struct htt_soc *htt_soc_attach(struct dp_soc *soc, HTC_HANDLE htc_hdl);
  740. /*
  741. * htt_set_htc_handle_() - set HTC handle
  742. * @htt_hdl: HTT handle/SOC
  743. * @htc_soc: HTC handle
  744. *
  745. * Return: None
  746. */
  747. void htt_set_htc_handle(struct htt_soc *htt_hdl, HTC_HANDLE htc_soc);
  748. /*
  749. * htt_get_htc_handle_() - set HTC handle
  750. * @htt_hdl: HTT handle/SOC
  751. *
  752. * Return: HTC_HANDLE
  753. */
  754. HTC_HANDLE htt_get_htc_handle(struct htt_soc *htt_hdl);
  755. /*
  756. * htt_soc_htc_dealloc() - HTC memory de-alloc
  757. * @htt_soc: SOC level HTT handle
  758. *
  759. * Return: None
  760. */
  761. void htt_soc_htc_dealloc(struct htt_soc *htt_handle);
  762. /*
  763. * htt_soc_htc_prealloc() - HTC memory prealloc
  764. * @htt_soc: SOC level HTT handle
  765. *
  766. * Return: QDF_STATUS_SUCCESS on success or
  767. * QDF_STATUS_E_NO_MEM on allocation failure
  768. */
  769. QDF_STATUS htt_soc_htc_prealloc(struct htt_soc *htt_soc);
  770. void htt_soc_detach(struct htt_soc *soc);
  771. int htt_srng_setup(struct htt_soc *htt_soc, int pdev_id,
  772. hal_ring_handle_t hal_ring_hdl,
  773. int hal_ring_type);
  774. int htt_soc_attach_target(struct htt_soc *htt_soc);
  775. /*
  776. * htt_h2t_rx_ring_cfg() - Send SRNG packet and TLV filter
  777. * config message to target
  778. * @htt_soc: HTT SOC handle
  779. * @pdev_id: PDEV Id
  780. * @hal_srng: Opaque HAL SRNG pointer
  781. * @hal_ring_type: SRNG ring type
  782. * @ring_buf_size: SRNG buffer size
  783. * @htt_tlv_filter: Rx SRNG TLV and filter setting
  784. *
  785. * Return: 0 on success; error code on failure
  786. */
  787. int htt_h2t_rx_ring_cfg(struct htt_soc *htt_soc, int pdev_id,
  788. hal_ring_handle_t hal_ring_hdl,
  789. int hal_ring_type, int ring_buf_size,
  790. struct htt_rx_ring_tlv_filter *htt_tlv_filter);
  791. /*
  792. * htt_t2h_stats_handler() - target to host stats work handler
  793. * @context: context (dp soc context)
  794. *
  795. * Return: void
  796. */
  797. void htt_t2h_stats_handler(void *context);
  798. /**
  799. * struct htt_stats_context - htt stats information
  800. * @soc: Size of each descriptor in the pool
  801. * @msg: T2H Ext stats message queue
  802. * @msg_len: T2H Ext stats message length
  803. */
  804. struct htt_stats_context {
  805. struct dp_soc *soc;
  806. qdf_nbuf_queue_t msg;
  807. uint32_t msg_len;
  808. };
  809. /**
  810. * dp_htt_rx_flow_fst_setup(): Send HTT Rx FST setup message to FW
  811. * @pdev: DP pdev handle
  812. * @fse_setup_info: FST setup parameters
  813. *
  814. * Return: Success when HTT message is sent, error on failure
  815. */
  816. QDF_STATUS
  817. dp_htt_rx_flow_fst_setup(struct dp_pdev *pdev,
  818. struct dp_htt_rx_flow_fst_setup *setup_info);
  819. /**
  820. * dp_htt_rx_flow_fse_operation(): Send HTT Flow Search Entry msg to
  821. * add/del a flow in HW
  822. * @pdev: DP pdev handle
  823. * @fse_op_info: Flow entry parameters
  824. *
  825. * Return: Success when HTT message is sent, error on failure
  826. */
  827. QDF_STATUS
  828. dp_htt_rx_flow_fse_operation(struct dp_pdev *pdev,
  829. struct dp_htt_rx_flow_fst_operation *op_info);
  830. /**
  831. * htt_h2t_full_mon_cfg() - Send full monitor configuarion msg to FW
  832. *
  833. * @htt_soc: HTT Soc handle
  834. * @pdev_id: Radio id
  835. * @dp_full_mon_config: enabled/disable configuration
  836. *
  837. * Return: Success when HTT message is sent, error on failure
  838. */
  839. int htt_h2t_full_mon_cfg(struct htt_soc *htt_soc,
  840. uint8_t pdev_id,
  841. enum dp_full_mon_config);
  842. /**
  843. * dp_h2t_hw_vdev_stats_config_send: Send HTT command to FW for config
  844. of HW vdev stats
  845. * @dpsoc: Datapath soc handle
  846. * @pdev_id: INVALID_PDEV_ID for all pdevs or 0,1,2 for individual pdev
  847. * @enable: flag to specify enable/disable of stats
  848. * @reset: flag to specify if command is for reset of stats
  849. * @reset_bitmask: bitmask of vdev_id(s) for reset of HW stats
  850. *
  851. * Return: QDF_STATUS
  852. */
  853. QDF_STATUS dp_h2t_hw_vdev_stats_config_send(struct dp_soc *dpsoc,
  854. uint8_t pdev_id, bool enable,
  855. bool reset, uint64_t reset_bitmask);
  856. #endif /* _DP_HTT_H_ */