sde_kms.c 134 KB

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  1. /*
  2. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  3. * Copyright (c) 2014-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (C) 2013 Red Hat
  5. * Author: Rob Clark <[email protected]>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License version 2 as published by
  9. * the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along with
  17. * this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  20. #include <drm/drm_crtc.h>
  21. #include <drm/drm_fixed.h>
  22. #include <drm/drm_panel.h>
  23. #include <linux/debugfs.h>
  24. #include <linux/of_address.h>
  25. #include <linux/of_irq.h>
  26. #include <linux/dma-buf.h>
  27. #include <linux/memblock.h>
  28. #include <linux/soc/qcom/panel_event_notifier.h>
  29. #include <drm/drm_atomic_uapi.h>
  30. #include <drm/drm_probe_helper.h>
  31. #include "msm_drv.h"
  32. #include "msm_mmu.h"
  33. #include "msm_gem.h"
  34. #include "dsi_display.h"
  35. #include "dsi_drm.h"
  36. #include "sde_wb.h"
  37. #include "dp_display.h"
  38. #include "dp_drm.h"
  39. #include "dp_mst_drm.h"
  40. #include "sde_kms.h"
  41. #include "sde_core_irq.h"
  42. #include "sde_formats.h"
  43. #include "sde_hw_vbif.h"
  44. #include "sde_vbif.h"
  45. #include "sde_encoder.h"
  46. #include "sde_plane.h"
  47. #include "sde_crtc.h"
  48. #include "sde_color_processing.h"
  49. #include "sde_reg_dma.h"
  50. #include "sde_connector.h"
  51. #include "sde_vm.h"
  52. #include "sde_fence.h"
  53. #include <linux/qcom_scm.h>
  54. #include <linux/qcom-iommu-util.h>
  55. #include "soc/qcom/secure_buffer.h"
  56. #include <linux/qtee_shmbridge.h>
  57. #ifdef CONFIG_DRM_SDE_VM
  58. #include <linux/gunyah/gh_irq_lend.h>
  59. #endif
  60. #define CREATE_TRACE_POINTS
  61. #include "sde_trace.h"
  62. /* defines for secure channel call */
  63. #define MEM_PROTECT_SD_CTRL_SWITCH 0x18
  64. #define MDP_DEVICE_ID 0x1A
  65. #define DEMURA_REGION_NAME_MAX 32
  66. EXPORT_TRACEPOINT_SYMBOL(tracing_mark_write);
  67. static const char * const iommu_ports[] = {
  68. "mdp_0",
  69. };
  70. /**
  71. * Controls size of event log buffer. Specified as a power of 2.
  72. */
  73. #define SDE_EVTLOG_SIZE 1024
  74. /*
  75. * To enable overall DRM driver logging
  76. * # echo 0x2 > /sys/module/drm/parameters/debug
  77. *
  78. * To enable DRM driver h/w logging
  79. * # echo <mask> > /sys/kernel/debug/dri/0/debug/hw_log_mask
  80. *
  81. * See sde_hw_mdss.h for h/w logging mask definitions (search for SDE_DBG_MASK_)
  82. */
  83. #define SDE_DEBUGFS_DIR "msm_sde"
  84. #define SDE_DEBUGFS_HWMASKNAME "hw_log_mask"
  85. #define SDE_KMS_MODESET_LOCK_TIMEOUT_US 500
  86. #define SDE_KMS_MODESET_LOCK_MAX_TRIALS 20
  87. /**
  88. * sdecustom - enable certain driver customizations for sde clients
  89. * Enabling this modifies the standard DRM behavior slightly and assumes
  90. * that the clients have specific knowledge about the modifications that
  91. * are involved, so don't enable this unless you know what you're doing.
  92. *
  93. * Parts of the driver that are affected by this setting may be located by
  94. * searching for invocations of the 'sde_is_custom_client()' function.
  95. *
  96. * This is disabled by default.
  97. */
  98. static bool sdecustom = true;
  99. module_param(sdecustom, bool, 0400);
  100. MODULE_PARM_DESC(sdecustom, "Enable customizations for sde clients");
  101. static int sde_kms_hw_init(struct msm_kms *kms);
  102. static int _sde_kms_mmu_destroy(struct sde_kms *sde_kms);
  103. static int _sde_kms_mmu_init(struct sde_kms *sde_kms);
  104. static int _sde_kms_register_events(struct msm_kms *kms,
  105. struct drm_mode_object *obj, u32 event, bool en);
  106. static void sde_kms_handle_power_event(u32 event_type, void *usr);
  107. bool sde_is_custom_client(void)
  108. {
  109. return sdecustom;
  110. }
  111. #if IS_ENABLED(CONFIG_DEBUG_FS)
  112. void *sde_debugfs_get_root(struct sde_kms *sde_kms)
  113. {
  114. struct msm_drm_private *priv;
  115. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private)
  116. return NULL;
  117. priv = sde_kms->dev->dev_private;
  118. return priv->debug_root;
  119. }
  120. static int _sde_debugfs_init(struct sde_kms *sde_kms)
  121. {
  122. void *p;
  123. int rc;
  124. void *debugfs_root;
  125. p = sde_hw_util_get_log_mask_ptr();
  126. if (!sde_kms || !p)
  127. return -EINVAL;
  128. debugfs_root = sde_debugfs_get_root(sde_kms);
  129. if (!debugfs_root)
  130. return -EINVAL;
  131. /* allow debugfs_root to be NULL */
  132. debugfs_create_x32(SDE_DEBUGFS_HWMASKNAME, 0600, debugfs_root, p);
  133. (void) sde_debugfs_vbif_init(sde_kms, debugfs_root);
  134. (void) sde_debugfs_core_irq_init(sde_kms, debugfs_root);
  135. rc = sde_core_perf_debugfs_init(&sde_kms->perf, debugfs_root);
  136. if (rc) {
  137. SDE_ERROR("failed to init perf %d\n", rc);
  138. return rc;
  139. }
  140. sde_rm_debugfs_init(&sde_kms->rm, debugfs_root);
  141. if (sde_kms->catalog->qdss_count)
  142. debugfs_create_u32("qdss", 0600, debugfs_root,
  143. (u32 *)&sde_kms->qdss_enabled);
  144. debugfs_create_u32("pm_suspend_clk_dump", 0600, debugfs_root,
  145. (u32 *)&sde_kms->pm_suspend_clk_dump);
  146. debugfs_create_u32("hw_fence_status", 0600, debugfs_root,
  147. (u32 *)&sde_kms->debugfs_hw_fence);
  148. return 0;
  149. }
  150. static void sde_kms_debugfs_destroy(struct msm_kms *kms)
  151. {
  152. struct sde_kms *sde_kms = to_sde_kms(kms);
  153. /* don't need to NULL check debugfs_root */
  154. if (sde_kms) {
  155. sde_debugfs_vbif_destroy(sde_kms);
  156. sde_debugfs_core_irq_destroy(sde_kms);
  157. }
  158. }
  159. static int _sde_kms_dump_clks_state(struct sde_kms *sde_kms)
  160. {
  161. int i;
  162. struct device *dev = sde_kms->dev->dev;
  163. SDE_INFO("runtime PM suspended:%d", pm_runtime_suspended(dev));
  164. for (i = 0; i < sde_kms->dsi_display_count; i++)
  165. dsi_display_dump_clks_state(sde_kms->dsi_displays[i]);
  166. return 0;
  167. }
  168. #else
  169. static int _sde_debugfs_init(struct sde_kms *sde_kms)
  170. {
  171. return 0;
  172. }
  173. static void sde_kms_debugfs_destroy(struct msm_kms *kms)
  174. {
  175. }
  176. static int _sde_kms_dump_clks_state(struct sde_kms *sde_kms)
  177. {
  178. return 0;
  179. }
  180. #endif /* CONFIG_DEBUG_FS */
  181. static void sde_kms_wait_for_frame_transfer_complete(struct msm_kms *kms,
  182. struct drm_crtc *crtc)
  183. {
  184. struct drm_encoder *encoder;
  185. struct drm_device *dev;
  186. int ret;
  187. if (!kms || !crtc || !crtc->state || !crtc->dev) {
  188. SDE_ERROR("invalid params\n");
  189. return;
  190. }
  191. if (!crtc->state->enable) {
  192. SDE_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
  193. return;
  194. }
  195. if (!crtc->state->active) {
  196. SDE_DEBUG("[crtc:%d] not active\n", crtc->base.id);
  197. return;
  198. }
  199. dev = crtc->dev;
  200. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  201. if (encoder->crtc != crtc)
  202. continue;
  203. /*
  204. * Video Mode - Wait for VSYNC
  205. * Cmd Mode - Wait for PP_DONE. Will be no-op if transfer is
  206. * complete
  207. */
  208. SDE_EVT32_VERBOSE(DRMID(crtc));
  209. ret = sde_encoder_wait_for_event(encoder, MSM_ENC_TX_COMPLETE);
  210. if (ret && ret != -EWOULDBLOCK) {
  211. SDE_ERROR(
  212. "[crtc: %d][enc: %d] wait for commit done returned %d\n",
  213. crtc->base.id, encoder->base.id, ret);
  214. break;
  215. }
  216. }
  217. }
  218. static int _sde_kms_secure_ctrl_xin_clients(struct sde_kms *sde_kms,
  219. struct drm_crtc *crtc, bool enable)
  220. {
  221. struct drm_device *dev;
  222. struct msm_drm_private *priv;
  223. struct sde_mdss_cfg *sde_cfg;
  224. struct drm_plane *plane;
  225. int i, ret;
  226. dev = sde_kms->dev;
  227. priv = dev->dev_private;
  228. sde_cfg = sde_kms->catalog;
  229. ret = sde_vbif_halt_xin_mask(sde_kms,
  230. sde_cfg->sui_block_xin_mask, enable);
  231. if (ret) {
  232. SDE_ERROR("failed to halt some xin-clients, ret:%d\n", ret);
  233. return ret;
  234. }
  235. if (enable) {
  236. for (i = 0; i < priv->num_planes; i++) {
  237. plane = priv->planes[i];
  238. sde_plane_secure_ctrl_xin_client(plane, crtc);
  239. }
  240. }
  241. return 0;
  242. }
  243. /**
  244. * _sde_kms_scm_call - makes secure channel call to switch the VMIDs
  245. * @sde_kms: Pointer to sde_kms struct
  246. * @vimd: switch the stage 2 translation to this VMID
  247. */
  248. static int _sde_kms_scm_call(struct sde_kms *sde_kms, int vmid)
  249. {
  250. struct device dummy = {};
  251. dma_addr_t dma_handle;
  252. uint32_t num_sids;
  253. uint32_t *sec_sid;
  254. struct sde_mdss_cfg *sde_cfg = sde_kms->catalog;
  255. int ret = 0, i;
  256. struct qtee_shm shm;
  257. bool qtee_en = qtee_shmbridge_is_enabled();
  258. phys_addr_t mem_addr;
  259. u64 mem_size;
  260. num_sids = sde_cfg->sec_sid_mask_count;
  261. if (!num_sids) {
  262. SDE_ERROR("secure SID masks not configured, vmid 0x%x\n", vmid);
  263. return -EINVAL;
  264. }
  265. if (qtee_en) {
  266. ret = qtee_shmbridge_allocate_shm(num_sids * sizeof(uint32_t),
  267. &shm);
  268. if (ret)
  269. return -ENOMEM;
  270. sec_sid = (uint32_t *) shm.vaddr;
  271. mem_addr = shm.paddr;
  272. /**
  273. * SMMUSecureModeSwitch requires the size to be number of SID's
  274. * but shm allocates size in pages. Modify the args as per
  275. * client requirement.
  276. */
  277. mem_size = sizeof(uint32_t) * num_sids;
  278. } else {
  279. sec_sid = kcalloc(num_sids, sizeof(uint32_t), GFP_KERNEL);
  280. if (!sec_sid)
  281. return -ENOMEM;
  282. mem_addr = virt_to_phys(sec_sid);
  283. mem_size = sizeof(uint32_t) * num_sids;
  284. }
  285. for (i = 0; i < num_sids; i++) {
  286. sec_sid[i] = sde_cfg->sec_sid_mask[i];
  287. SDE_DEBUG("sid_mask[%d]: %d\n", i, sec_sid[i]);
  288. }
  289. ret = dma_coerce_mask_and_coherent(&dummy, DMA_BIT_MASK(64));
  290. if (ret) {
  291. SDE_ERROR("Failed to set dma mask for dummy dev %d\n", ret);
  292. goto map_error;
  293. }
  294. set_dma_ops(&dummy, NULL);
  295. dma_handle = dma_map_single(&dummy, sec_sid,
  296. num_sids * sizeof(uint32_t), DMA_TO_DEVICE);
  297. if (dma_mapping_error(&dummy, dma_handle)) {
  298. SDE_ERROR("dma_map_single for dummy dev failed vmid 0x%x\n",
  299. vmid);
  300. goto map_error;
  301. }
  302. SDE_DEBUG("calling scm_call for vmid 0x%x, num_sids %d, qtee_en %d",
  303. vmid, num_sids, qtee_en);
  304. ret = qcom_scm_mem_protect_sd_ctrl(MDP_DEVICE_ID, mem_addr,
  305. mem_size, vmid);
  306. if (ret)
  307. SDE_ERROR("Error:scm_call2, vmid %d, ret%d\n",
  308. vmid, ret);
  309. SDE_EVT32(MEM_PROTECT_SD_CTRL_SWITCH, MDP_DEVICE_ID, mem_size,
  310. vmid, qtee_en, num_sids, ret);
  311. dma_unmap_single(&dummy, dma_handle,
  312. num_sids * sizeof(uint32_t), DMA_TO_DEVICE);
  313. map_error:
  314. if (qtee_en)
  315. qtee_shmbridge_free_shm(&shm);
  316. else
  317. kfree(sec_sid);
  318. return ret;
  319. }
  320. static int _sde_kms_detach_all_cb(struct sde_kms *sde_kms, u32 vmid)
  321. {
  322. u32 ret;
  323. if (atomic_inc_return(&sde_kms->detach_all_cb) > 1)
  324. return 0;
  325. /* detach_all_contexts */
  326. ret = sde_kms_mmu_detach(sde_kms, false);
  327. if (ret) {
  328. SDE_ERROR("failed to detach all cb ret:%d\n", ret);
  329. goto mmu_error;
  330. }
  331. ret = _sde_kms_scm_call(sde_kms, vmid);
  332. if (ret) {
  333. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  334. goto scm_error;
  335. }
  336. return 0;
  337. scm_error:
  338. sde_kms_mmu_attach(sde_kms, false);
  339. mmu_error:
  340. atomic_dec(&sde_kms->detach_all_cb);
  341. return ret;
  342. }
  343. static int _sde_kms_attach_all_cb(struct sde_kms *sde_kms, u32 vmid,
  344. u32 old_vmid)
  345. {
  346. u32 ret;
  347. if (atomic_dec_return(&sde_kms->detach_all_cb) != 0)
  348. return 0;
  349. ret = _sde_kms_scm_call(sde_kms, vmid);
  350. if (ret) {
  351. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  352. goto scm_error;
  353. }
  354. /* attach_all_contexts */
  355. ret = sde_kms_mmu_attach(sde_kms, false);
  356. if (ret) {
  357. SDE_ERROR("failed to attach all cb ret:%d\n", ret);
  358. goto mmu_error;
  359. }
  360. return 0;
  361. mmu_error:
  362. _sde_kms_scm_call(sde_kms, old_vmid);
  363. scm_error:
  364. atomic_inc(&sde_kms->detach_all_cb);
  365. return ret;
  366. }
  367. static int _sde_kms_detach_sec_cb(struct sde_kms *sde_kms, int vmid)
  368. {
  369. u32 ret;
  370. if (atomic_inc_return(&sde_kms->detach_sec_cb) > 1)
  371. return 0;
  372. /* detach secure_context */
  373. ret = sde_kms_mmu_detach(sde_kms, true);
  374. if (ret) {
  375. SDE_ERROR("failed to detach sec cb ret:%d\n", ret);
  376. goto mmu_error;
  377. }
  378. ret = _sde_kms_scm_call(sde_kms, vmid);
  379. if (ret) {
  380. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  381. goto scm_error;
  382. }
  383. return 0;
  384. scm_error:
  385. sde_kms_mmu_attach(sde_kms, true);
  386. mmu_error:
  387. atomic_dec(&sde_kms->detach_sec_cb);
  388. return ret;
  389. }
  390. static int _sde_kms_attach_sec_cb(struct sde_kms *sde_kms, u32 vmid,
  391. u32 old_vmid)
  392. {
  393. u32 ret;
  394. if (atomic_dec_return(&sde_kms->detach_sec_cb) != 0)
  395. return 0;
  396. ret = _sde_kms_scm_call(sde_kms, vmid);
  397. if (ret) {
  398. goto scm_error;
  399. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  400. }
  401. ret = sde_kms_mmu_attach(sde_kms, true);
  402. if (ret) {
  403. SDE_ERROR("failed to attach sec cb ret:%d\n", ret);
  404. goto mmu_error;
  405. }
  406. return 0;
  407. mmu_error:
  408. _sde_kms_scm_call(sde_kms, old_vmid);
  409. scm_error:
  410. atomic_inc(&sde_kms->detach_sec_cb);
  411. return ret;
  412. }
  413. static int _sde_kms_sui_misr_ctrl(struct sde_kms *sde_kms,
  414. struct drm_crtc *crtc, bool enable)
  415. {
  416. int ret;
  417. if (enable) {
  418. ret = pm_runtime_resume_and_get(sde_kms->dev->dev);
  419. if (ret < 0) {
  420. SDE_ERROR("failed to enable power resource %d\n", ret);
  421. SDE_EVT32(ret, SDE_EVTLOG_ERROR);
  422. return ret;
  423. }
  424. sde_crtc_misr_setup(crtc, true, 1);
  425. ret = _sde_kms_secure_ctrl_xin_clients(sde_kms, crtc, true);
  426. if (ret) {
  427. sde_crtc_misr_setup(crtc, false, 0);
  428. pm_runtime_put_sync(sde_kms->dev->dev);
  429. return ret;
  430. }
  431. } else {
  432. _sde_kms_secure_ctrl_xin_clients(sde_kms, crtc, false);
  433. sde_crtc_misr_setup(crtc, false, 0);
  434. pm_runtime_put_sync(sde_kms->dev->dev);
  435. }
  436. return 0;
  437. }
  438. static int _sde_kms_secure_ctrl(struct sde_kms *sde_kms, struct drm_crtc *crtc,
  439. bool post_commit)
  440. {
  441. struct sde_kms_smmu_state_data *smmu_state = &sde_kms->smmu_state;
  442. int old_smmu_state = smmu_state->state;
  443. int ret = 0;
  444. u32 vmid;
  445. if (!sde_kms || !crtc) {
  446. SDE_ERROR("invalid argument(s)\n");
  447. return -EINVAL;
  448. }
  449. SDE_EVT32(DRMID(crtc), smmu_state->state, smmu_state->transition_type,
  450. post_commit, smmu_state->sui_misr_state,
  451. smmu_state->secure_level, SDE_EVTLOG_FUNC_ENTRY);
  452. if ((!smmu_state->transition_type) ||
  453. ((smmu_state->transition_type == POST_COMMIT) && !post_commit))
  454. /* Bail out */
  455. return 0;
  456. /* enable sui misr if requested, before the transition */
  457. if (smmu_state->sui_misr_state == SUI_MISR_ENABLE_REQ) {
  458. ret = _sde_kms_sui_misr_ctrl(sde_kms, crtc, true);
  459. if (ret) {
  460. smmu_state->sui_misr_state = NONE;
  461. goto end;
  462. }
  463. }
  464. mutex_lock(&sde_kms->secure_transition_lock);
  465. switch (smmu_state->state) {
  466. case DETACH_ALL_REQ:
  467. ret = _sde_kms_detach_all_cb(sde_kms, VMID_CP_SEC_DISPLAY);
  468. if (!ret)
  469. smmu_state->state = DETACHED;
  470. break;
  471. case ATTACH_ALL_REQ:
  472. ret = _sde_kms_attach_all_cb(sde_kms, VMID_CP_PIXEL,
  473. VMID_CP_SEC_DISPLAY);
  474. if (!ret) {
  475. smmu_state->state = ATTACHED;
  476. smmu_state->secure_level = SDE_DRM_SEC_NON_SEC;
  477. }
  478. break;
  479. case DETACH_SEC_REQ:
  480. vmid = (smmu_state->secure_level == SDE_DRM_SEC_ONLY) ?
  481. VMID_CP_SEC_DISPLAY : VMID_CP_CAMERA_PREVIEW;
  482. ret = _sde_kms_detach_sec_cb(sde_kms, vmid);
  483. if (!ret)
  484. smmu_state->state = DETACHED_SEC;
  485. break;
  486. case ATTACH_SEC_REQ:
  487. vmid = (smmu_state->secure_level == SDE_DRM_SEC_ONLY) ?
  488. VMID_CP_SEC_DISPLAY : VMID_CP_CAMERA_PREVIEW;
  489. ret = _sde_kms_attach_sec_cb(sde_kms, VMID_CP_PIXEL, vmid);
  490. if (!ret) {
  491. smmu_state->state = ATTACHED;
  492. smmu_state->secure_level = SDE_DRM_SEC_NON_SEC;
  493. }
  494. break;
  495. default:
  496. SDE_ERROR("crtc%d: invalid smmu state %d transition type %d\n",
  497. DRMID(crtc), smmu_state->state,
  498. smmu_state->transition_type);
  499. ret = -EINVAL;
  500. break;
  501. }
  502. mutex_unlock(&sde_kms->secure_transition_lock);
  503. /* disable sui misr if requested, after the transition */
  504. if (!ret && (smmu_state->sui_misr_state == SUI_MISR_DISABLE_REQ)) {
  505. ret = _sde_kms_sui_misr_ctrl(sde_kms, crtc, false);
  506. if (ret)
  507. goto end;
  508. }
  509. end:
  510. smmu_state->transition_error = false;
  511. if (ret) {
  512. smmu_state->transition_error = true;
  513. SDE_ERROR(
  514. "crtc%d: req_state %d, new_state %d, sec_lvl %d, ret %d\n",
  515. DRMID(crtc), old_smmu_state, smmu_state->state,
  516. smmu_state->secure_level, ret);
  517. smmu_state->state = smmu_state->prev_state;
  518. smmu_state->secure_level = smmu_state->prev_secure_level;
  519. if (smmu_state->sui_misr_state == SUI_MISR_ENABLE_REQ)
  520. _sde_kms_sui_misr_ctrl(sde_kms, crtc, false);
  521. }
  522. SDE_DEBUG("crtc %d: req_state %d, new_state %d, sec_lvl %d, ret %d\n",
  523. DRMID(crtc), old_smmu_state, smmu_state->state,
  524. smmu_state->secure_level, ret);
  525. SDE_EVT32(DRMID(crtc), smmu_state->state, smmu_state->prev_state,
  526. smmu_state->transition_type,
  527. smmu_state->transition_error,
  528. smmu_state->secure_level, smmu_state->prev_secure_level,
  529. smmu_state->sui_misr_state, ret, SDE_EVTLOG_FUNC_EXIT);
  530. smmu_state->sui_misr_state = NONE;
  531. smmu_state->transition_type = NONE;
  532. return ret;
  533. }
  534. static int sde_kms_prepare_secure_transition(struct msm_kms *kms,
  535. struct drm_atomic_state *state)
  536. {
  537. struct drm_crtc *crtc;
  538. struct drm_crtc_state *old_crtc_state;
  539. struct drm_plane_state *old_plane_state, *new_plane_state;
  540. struct drm_plane *plane;
  541. struct drm_plane_state *plane_state;
  542. struct sde_kms *sde_kms = to_sde_kms(kms);
  543. struct drm_device *dev = sde_kms->dev;
  544. int i, ops = 0, ret = 0;
  545. bool old_valid_fb = false;
  546. struct sde_kms_smmu_state_data *smmu_state = &sde_kms->smmu_state;
  547. for_each_old_crtc_in_state(state, crtc, old_crtc_state, i) {
  548. if (!crtc->state || !crtc->state->active)
  549. continue;
  550. /*
  551. * It is safe to assume only one active crtc,
  552. * and compatible translation modes on the
  553. * planes staged on this crtc.
  554. * otherwise validation would have failed.
  555. * For this CRTC,
  556. */
  557. /*
  558. * 1. Check if old state on the CRTC has planes
  559. * staged with valid fbs
  560. */
  561. for_each_old_plane_in_state(state, plane, plane_state, i) {
  562. if (!plane_state->crtc)
  563. continue;
  564. if (plane_state->fb) {
  565. old_valid_fb = true;
  566. break;
  567. }
  568. }
  569. /*
  570. * 2.Get the operations needed to be performed before
  571. * secure transition can be initiated.
  572. */
  573. ops = sde_crtc_get_secure_transition_ops(crtc,
  574. old_crtc_state, old_valid_fb);
  575. if (ops < 0) {
  576. SDE_ERROR("invalid secure operations %x\n", ops);
  577. return ops;
  578. }
  579. if (!ops) {
  580. smmu_state->transition_error = false;
  581. goto no_ops;
  582. }
  583. SDE_DEBUG("%d:secure operations(%x) started on state:%pK\n",
  584. crtc->base.id, ops, crtc->state);
  585. SDE_EVT32(DRMID(crtc), ops, crtc->state, old_valid_fb);
  586. /* 3. Perform operations needed for secure transition */
  587. if (ops & SDE_KMS_OPS_WAIT_FOR_TX_DONE) {
  588. SDE_DEBUG("wait_for_transfer_done\n");
  589. sde_kms_wait_for_frame_transfer_complete(kms, crtc);
  590. }
  591. if (ops & SDE_KMS_OPS_CLEANUP_PLANE_FB) {
  592. SDE_DEBUG("cleanup planes\n");
  593. drm_atomic_helper_cleanup_planes(dev, state);
  594. for_each_oldnew_plane_in_state(state, plane,
  595. old_plane_state, new_plane_state, i)
  596. sde_plane_destroy_fb(old_plane_state);
  597. }
  598. if (ops & SDE_KMS_OPS_SECURE_STATE_CHANGE) {
  599. SDE_DEBUG("secure ctrl\n");
  600. _sde_kms_secure_ctrl(sde_kms, crtc, false);
  601. }
  602. if (ops & SDE_KMS_OPS_PREPARE_PLANE_FB) {
  603. SDE_DEBUG("prepare planes %d",
  604. crtc->state->plane_mask);
  605. drm_atomic_crtc_for_each_plane(plane,
  606. crtc) {
  607. const struct drm_plane_helper_funcs *funcs;
  608. plane_state = plane->state;
  609. funcs = plane->helper_private;
  610. SDE_DEBUG("psde:%d FB[%u]\n",
  611. plane->base.id,
  612. plane->fb->base.id);
  613. if (!funcs)
  614. continue;
  615. if (funcs->prepare_fb(plane, plane_state)) {
  616. ret = funcs->prepare_fb(plane,
  617. plane_state);
  618. if (ret)
  619. return ret;
  620. }
  621. }
  622. }
  623. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_EXIT);
  624. SDE_DEBUG("secure operations completed\n");
  625. }
  626. no_ops:
  627. return 0;
  628. }
  629. static int _sde_kms_release_shared_buffer(unsigned int mem_addr,
  630. unsigned int splash_buffer_size,
  631. unsigned int ramdump_base,
  632. unsigned int ramdump_buffer_size)
  633. {
  634. unsigned long pfn_start, pfn_end, pfn_idx;
  635. int ret = 0;
  636. if (!mem_addr || !splash_buffer_size) {
  637. SDE_ERROR("invalid params\n");
  638. return -EINVAL;
  639. }
  640. /* leave ramdump memory only if base address matches */
  641. if (ramdump_base == mem_addr &&
  642. ramdump_buffer_size <= splash_buffer_size) {
  643. mem_addr += ramdump_buffer_size;
  644. splash_buffer_size -= ramdump_buffer_size;
  645. }
  646. pfn_start = mem_addr >> PAGE_SHIFT;
  647. pfn_end = (mem_addr + splash_buffer_size) >> PAGE_SHIFT;
  648. ret = memblock_free(mem_addr, splash_buffer_size);
  649. if (ret) {
  650. SDE_ERROR("continuous splash memory free failed:%d\n", ret);
  651. return ret;
  652. }
  653. for (pfn_idx = pfn_start; pfn_idx < pfn_end; pfn_idx++)
  654. free_reserved_page(pfn_to_page(pfn_idx));
  655. return ret;
  656. }
  657. static int _sde_kms_one2one_mem_map_ipcc_reg(struct sde_kms *sde_kms, u32 buf_size,
  658. unsigned long buf_base)
  659. {
  660. struct msm_mmu *mmu = NULL;
  661. int ret = 0;
  662. if (!sde_kms->aspace[MSM_SMMU_DOMAIN_UNSECURE]
  663. || !sde_kms->aspace[MSM_SMMU_DOMAIN_UNSECURE]->mmu) {
  664. SDE_ERROR("aspace not found for sde kms node\n");
  665. return -EINVAL;
  666. }
  667. mmu = sde_kms->aspace[MSM_SMMU_DOMAIN_UNSECURE]->mmu;
  668. if (!mmu) {
  669. SDE_ERROR("mmu not found for aspace\n");
  670. return -EINVAL;
  671. }
  672. if (!mmu->funcs || !mmu->funcs->one_to_one_map) {
  673. SDE_ERROR("invalid input params for map\n");
  674. return -EINVAL;
  675. }
  676. ret = mmu->funcs->one_to_one_map(mmu, buf_base, buf_base, buf_size,
  677. IOMMU_READ | IOMMU_WRITE);
  678. if (ret)
  679. SDE_ERROR("one2one memory smmu map failed:%d\n", ret);
  680. return ret;
  681. }
  682. static int _sde_kms_splash_mem_get(struct sde_kms *sde_kms,
  683. struct sde_splash_mem *splash)
  684. {
  685. struct msm_mmu *mmu = NULL;
  686. int ret = 0;
  687. if (!sde_kms->aspace[0]) {
  688. SDE_ERROR("aspace not found for sde kms node\n");
  689. return -EINVAL;
  690. }
  691. mmu = sde_kms->aspace[0]->mmu;
  692. if (!mmu) {
  693. SDE_ERROR("mmu not found for aspace\n");
  694. return -EINVAL;
  695. }
  696. if (!splash || !mmu->funcs || !mmu->funcs->one_to_one_map) {
  697. SDE_ERROR("invalid input params for map\n");
  698. return -EINVAL;
  699. }
  700. if (!splash->ref_cnt) {
  701. ret = mmu->funcs->one_to_one_map(mmu, splash->splash_buf_base,
  702. splash->splash_buf_base,
  703. splash->splash_buf_size,
  704. IOMMU_READ | IOMMU_NOEXEC);
  705. if (ret)
  706. SDE_ERROR("splash memory smmu map failed:%d\n", ret);
  707. }
  708. splash->ref_cnt++;
  709. SDE_DEBUG("one2one mapping done for base:%lx size:%x ref_cnt:%d\n",
  710. splash->splash_buf_base,
  711. splash->splash_buf_size,
  712. splash->ref_cnt);
  713. return ret;
  714. }
  715. static int _sde_kms_map_all_splash_regions(struct sde_kms *sde_kms)
  716. {
  717. int i = 0;
  718. int ret = 0;
  719. struct sde_splash_mem *region;
  720. if (!sde_kms)
  721. return -EINVAL;
  722. for (i = 0; i < sde_kms->splash_data.num_splash_displays; i++) {
  723. region = sde_kms->splash_data.splash_display[i].splash;
  724. ret = _sde_kms_splash_mem_get(sde_kms, region);
  725. if (ret)
  726. return ret;
  727. /* Demura is optional and need not exist */
  728. region = sde_kms->splash_data.splash_display[i].demura;
  729. if (region) {
  730. ret = _sde_kms_splash_mem_get(sde_kms, region);
  731. if (ret)
  732. return ret;
  733. }
  734. }
  735. return ret;
  736. }
  737. static int _sde_kms_splash_mem_put(struct sde_kms *sde_kms,
  738. struct sde_splash_mem *splash)
  739. {
  740. struct msm_mmu *mmu = NULL;
  741. int rc = 0;
  742. if (!sde_kms || !sde_kms->aspace[0] || !sde_kms->aspace[0]->mmu) {
  743. SDE_ERROR("invalid params\n");
  744. return -EINVAL;
  745. }
  746. mmu = sde_kms->aspace[0]->mmu;
  747. if (!splash || !splash->ref_cnt ||
  748. !mmu || !mmu->funcs || !mmu->funcs->one_to_one_unmap)
  749. return -EINVAL;
  750. splash->ref_cnt--;
  751. SDE_DEBUG("splash base:%lx refcnt:%d\n",
  752. splash->splash_buf_base, splash->ref_cnt);
  753. if (!splash->ref_cnt) {
  754. mmu->funcs->one_to_one_unmap(mmu, splash->splash_buf_base,
  755. splash->splash_buf_size);
  756. rc = _sde_kms_release_shared_buffer(splash->splash_buf_base,
  757. splash->splash_buf_size, splash->ramdump_base,
  758. splash->ramdump_size);
  759. splash->splash_buf_base = 0;
  760. splash->splash_buf_size = 0;
  761. }
  762. return rc;
  763. }
  764. static int _sde_kms_unmap_all_splash_regions(struct sde_kms *sde_kms)
  765. {
  766. int i = 0;
  767. int ret = 0, failure = 0;
  768. struct sde_splash_mem *region;
  769. if (!sde_kms || !sde_kms->splash_data.num_splash_regions)
  770. return -EINVAL;
  771. for (i = 0; i < sde_kms->splash_data.num_splash_displays; i++) {
  772. region = sde_kms->splash_data.splash_display[i].splash;
  773. ret = _sde_kms_splash_mem_put(sde_kms, region);
  774. if (ret) {
  775. failure = 1;
  776. pr_err("Error unmapping splash mem for display %d\n",
  777. i);
  778. }
  779. /* Demura is optional and need not exist */
  780. region = sde_kms->splash_data.splash_display[i].demura;
  781. if (region) {
  782. ret = _sde_kms_splash_mem_put(sde_kms, region);
  783. if (ret) {
  784. failure = 1;
  785. pr_err("Error unmapping demura mem for display %d\n",
  786. i);
  787. }
  788. }
  789. }
  790. if (failure)
  791. ret = -EINVAL;
  792. return ret;
  793. }
  794. static int _sde_kms_get_blank(struct drm_crtc_state *crtc_state,
  795. struct drm_connector_state *conn_state)
  796. {
  797. int lp_mode, blank;
  798. if (crtc_state->active)
  799. lp_mode = sde_connector_get_property(conn_state,
  800. CONNECTOR_PROP_LP);
  801. else
  802. lp_mode = SDE_MODE_DPMS_OFF;
  803. switch (lp_mode) {
  804. case SDE_MODE_DPMS_ON:
  805. blank = DRM_PANEL_EVENT_UNBLANK;
  806. break;
  807. case SDE_MODE_DPMS_LP1:
  808. case SDE_MODE_DPMS_LP2:
  809. blank = DRM_PANEL_EVENT_BLANK_LP;
  810. break;
  811. case SDE_MODE_DPMS_OFF:
  812. default:
  813. blank = DRM_PANEL_EVENT_BLANK;
  814. break;
  815. }
  816. return blank;
  817. }
  818. static void _sde_kms_drm_check_dpms(struct drm_atomic_state *old_state,
  819. bool is_pre_commit)
  820. {
  821. struct panel_event_notification notification;
  822. struct drm_connector *connector;
  823. struct drm_connector_state *old_conn_state;
  824. struct drm_crtc_state *old_crtc_state;
  825. struct drm_crtc *crtc;
  826. struct sde_connector *c_conn;
  827. int i, old_mode, new_mode, old_fps, new_fps;
  828. enum panel_event_notifier_tag panel_type;
  829. for_each_old_connector_in_state(old_state, connector,
  830. old_conn_state, i) {
  831. crtc = connector->state->crtc ? connector->state->crtc :
  832. old_conn_state->crtc;
  833. if (!crtc)
  834. continue;
  835. new_fps = drm_mode_vrefresh(&crtc->state->mode);
  836. new_mode = _sde_kms_get_blank(crtc->state, connector->state);
  837. if (old_conn_state->crtc) {
  838. old_crtc_state = drm_atomic_get_existing_crtc_state(
  839. old_state, old_conn_state->crtc);
  840. old_fps = drm_mode_vrefresh(&old_crtc_state->mode);
  841. old_mode = _sde_kms_get_blank(old_crtc_state,
  842. old_conn_state);
  843. } else {
  844. old_fps = 0;
  845. old_mode = DRM_PANEL_EVENT_BLANK;
  846. }
  847. if ((old_mode != new_mode) || (old_fps != new_fps)) {
  848. c_conn = to_sde_connector(connector);
  849. SDE_EVT32(old_mode, new_mode, old_fps, new_fps,
  850. c_conn->panel, crtc->state->active,
  851. old_conn_state->crtc);
  852. pr_debug("change detected for connector:%s (power mode %d->%d, fps %d->%d)\n",
  853. c_conn->name, old_mode, new_mode, old_fps, new_fps);
  854. /* If suspend resume and fps change are happening
  855. * at the same time, give preference to power mode
  856. * changes rather than fps change.
  857. */
  858. if ((old_mode == new_mode) && (old_fps != new_fps))
  859. new_mode = DRM_PANEL_EVENT_FPS_CHANGE;
  860. if (!c_conn->panel)
  861. continue;
  862. panel_type = sde_encoder_is_primary_display(
  863. connector->encoder) ?
  864. PANEL_EVENT_NOTIFICATION_PRIMARY :
  865. PANEL_EVENT_NOTIFICATION_SECONDARY;
  866. notification.notif_type = new_mode;
  867. notification.panel = c_conn->panel;
  868. notification.notif_data.old_fps = old_fps;
  869. notification.notif_data.new_fps = new_fps;
  870. notification.notif_data.early_trigger = is_pre_commit;
  871. panel_event_notification_trigger(panel_type,
  872. &notification);
  873. }
  874. }
  875. }
  876. static struct drm_crtc *sde_kms_vm_get_vm_crtc(
  877. struct drm_atomic_state *state)
  878. {
  879. int i;
  880. enum sde_crtc_vm_req vm_req = VM_REQ_NONE;
  881. struct drm_crtc *crtc, *vm_crtc = NULL;
  882. struct drm_crtc_state *new_cstate, *old_cstate;
  883. struct sde_crtc_state *vm_cstate;
  884. for_each_oldnew_crtc_in_state(state, crtc, old_cstate, new_cstate, i) {
  885. if (!new_cstate->active && !old_cstate->active)
  886. continue;
  887. vm_cstate = to_sde_crtc_state(new_cstate);
  888. vm_req = sde_crtc_get_property(vm_cstate,
  889. CRTC_PROP_VM_REQ_STATE);
  890. if (vm_req != VM_REQ_NONE) {
  891. SDE_DEBUG("valid vm request:%d found on crtc-%d\n",
  892. vm_req, crtc->base.id);
  893. vm_crtc = crtc;
  894. break;
  895. }
  896. }
  897. return vm_crtc;
  898. }
  899. int sde_kms_vm_primary_prepare_commit(struct sde_kms *sde_kms,
  900. struct drm_atomic_state *state)
  901. {
  902. struct drm_device *ddev;
  903. struct drm_crtc *crtc;
  904. struct drm_crtc_state *new_cstate;
  905. struct drm_encoder *encoder;
  906. struct drm_connector *connector;
  907. struct sde_vm_ops *vm_ops;
  908. struct sde_crtc_state *cstate;
  909. struct drm_connector_list_iter iter;
  910. enum sde_crtc_vm_req vm_req;
  911. int rc = 0;
  912. ddev = sde_kms->dev;
  913. vm_ops = sde_vm_get_ops(sde_kms);
  914. if (!vm_ops)
  915. return -EINVAL;
  916. crtc = sde_kms_vm_get_vm_crtc(state);
  917. if (!crtc)
  918. return 0;
  919. new_cstate = drm_atomic_get_new_crtc_state(state, crtc);
  920. cstate = to_sde_crtc_state(new_cstate);
  921. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  922. if (vm_req != VM_REQ_ACQUIRE)
  923. return 0;
  924. /* enable MDSS irq line */
  925. sde_irq_update(&sde_kms->base, true);
  926. /* clear the stale IRQ status bits */
  927. if (sde_kms->hw_intr && sde_kms->hw_intr->ops.clear_all_irqs)
  928. sde_kms->hw_intr->ops.clear_all_irqs(sde_kms->hw_intr);
  929. /* enable the display path IRQ's */
  930. drm_for_each_encoder_mask(encoder, crtc->dev,
  931. crtc->state->encoder_mask) {
  932. if (sde_encoder_in_clone_mode(encoder))
  933. continue;
  934. sde_encoder_irq_control(encoder, true);
  935. }
  936. /* Schedule ESD work */
  937. drm_connector_list_iter_begin(ddev, &iter);
  938. drm_for_each_connector_iter(connector, &iter)
  939. if (drm_connector_mask(connector) & crtc->state->connector_mask)
  940. sde_connector_schedule_status_work(connector, true);
  941. drm_connector_list_iter_end(&iter);
  942. /* enable vblank events */
  943. drm_crtc_vblank_on(crtc);
  944. sde_dbg_set_hw_ownership_status(true);
  945. /* handle non-SDE pre_acquire */
  946. if (vm_ops->vm_client_post_acquire)
  947. rc = vm_ops->vm_client_post_acquire(sde_kms);
  948. return rc;
  949. }
  950. void sde_kms_vm_set_sid(struct sde_kms *sde_kms, u32 vm)
  951. {
  952. struct drm_plane *plane;
  953. struct drm_device *ddev;
  954. struct sde_mdss_cfg *sde_cfg;
  955. ddev = sde_kms->dev;
  956. sde_cfg = sde_kms->catalog;
  957. list_for_each_entry(plane, &ddev->mode_config.plane_list, head)
  958. sde_plane_set_sid(plane, vm);
  959. if (sde_kms->hw_sid && sde_kms->hw_sid->ops.set_vm_sid)
  960. sde_kms->hw_sid->ops.set_vm_sid(sde_kms->hw_sid, vm, sde_kms->catalog);
  961. }
  962. int sde_kms_vm_trusted_prepare_commit(struct sde_kms *sde_kms,
  963. struct drm_atomic_state *state)
  964. {
  965. struct drm_crtc *crtc;
  966. struct drm_crtc_state *new_cstate;
  967. struct sde_crtc_state *cstate;
  968. enum sde_crtc_vm_req vm_req;
  969. crtc = sde_kms_vm_get_vm_crtc(state);
  970. if (!crtc)
  971. return 0;
  972. new_cstate = drm_atomic_get_new_crtc_state(state, crtc);
  973. cstate = to_sde_crtc_state(new_cstate);
  974. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  975. if (vm_req != VM_REQ_ACQUIRE)
  976. return 0;
  977. /* Clear the stale IRQ status bits */
  978. if (sde_kms->hw_intr && sde_kms->hw_intr->ops.clear_all_irqs)
  979. sde_kms->hw_intr->ops.clear_all_irqs(sde_kms->hw_intr);
  980. /* Program the SID's for the trusted VM */
  981. sde_kms_vm_set_sid(sde_kms, 1);
  982. sde_dbg_set_hw_ownership_status(true);
  983. return 0;
  984. }
  985. static void sde_kms_prepare_commit(struct msm_kms *kms,
  986. struct drm_atomic_state *state)
  987. {
  988. struct sde_kms *sde_kms;
  989. struct msm_drm_private *priv;
  990. struct drm_device *dev;
  991. struct drm_encoder *encoder;
  992. struct drm_crtc *crtc;
  993. struct drm_crtc_state *cstate;
  994. struct sde_vm_ops *vm_ops;
  995. int i, rc;
  996. if (!kms)
  997. return;
  998. sde_kms = to_sde_kms(kms);
  999. dev = sde_kms->dev;
  1000. if (!dev || !dev->dev_private)
  1001. return;
  1002. priv = dev->dev_private;
  1003. SDE_ATRACE_BEGIN("prepare_commit");
  1004. rc = pm_runtime_resume_and_get(sde_kms->dev->dev);
  1005. if (rc < 0) {
  1006. SDE_ERROR("failed to enable power resources %d\n", rc);
  1007. SDE_EVT32(rc, SDE_EVTLOG_ERROR);
  1008. goto end;
  1009. }
  1010. if (sde_kms->first_kickoff) {
  1011. sde_power_scale_reg_bus(&priv->phandle, VOTE_INDEX_HIGH, false);
  1012. sde_kms->first_kickoff = false;
  1013. }
  1014. for_each_new_crtc_in_state(state, crtc, cstate, i) {
  1015. drm_for_each_encoder_mask(encoder, dev, cstate->encoder_mask) {
  1016. if (sde_encoder_prepare_commit(encoder) == -ETIMEDOUT) {
  1017. SDE_ERROR("crtc:%d, initiating hw reset\n",
  1018. DRMID(crtc));
  1019. sde_encoder_needs_hw_reset(encoder);
  1020. sde_crtc_set_needs_hw_reset(crtc);
  1021. }
  1022. }
  1023. }
  1024. /*
  1025. * NOTE: for secure use cases we want to apply the new HW
  1026. * configuration only after completing preparation for secure
  1027. * transitions prepare below if any transtions is required.
  1028. */
  1029. sde_kms_prepare_secure_transition(kms, state);
  1030. vm_ops = sde_vm_get_ops(sde_kms);
  1031. if (!vm_ops)
  1032. goto end_vm;
  1033. if (vm_ops->vm_prepare_commit)
  1034. vm_ops->vm_prepare_commit(sde_kms, state);
  1035. end_vm:
  1036. _sde_kms_drm_check_dpms(state, true);
  1037. end:
  1038. SDE_ATRACE_END("prepare_commit");
  1039. }
  1040. static void sde_kms_commit(struct msm_kms *kms,
  1041. struct drm_atomic_state *old_state)
  1042. {
  1043. struct sde_kms *sde_kms;
  1044. struct drm_crtc *crtc;
  1045. struct drm_crtc_state *old_crtc_state;
  1046. int i;
  1047. if (!kms || !old_state)
  1048. return;
  1049. sde_kms = to_sde_kms(kms);
  1050. if (!sde_kms_power_resource_is_enabled(sde_kms->dev)) {
  1051. SDE_ERROR("power resource is not enabled\n");
  1052. return;
  1053. }
  1054. SDE_ATRACE_BEGIN("sde_kms_commit");
  1055. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  1056. if (crtc->state->active) {
  1057. SDE_EVT32(DRMID(crtc), old_state);
  1058. sde_crtc_commit_kickoff(crtc, old_crtc_state);
  1059. }
  1060. }
  1061. SDE_ATRACE_END("sde_kms_commit");
  1062. }
  1063. static void _sde_kms_free_splash_display_data(struct sde_kms *sde_kms,
  1064. struct sde_splash_display *splash_display)
  1065. {
  1066. if (!sde_kms || !splash_display ||
  1067. !sde_kms->splash_data.num_splash_displays)
  1068. return;
  1069. if (sde_kms->splash_data.num_splash_regions) {
  1070. _sde_kms_splash_mem_put(sde_kms, splash_display->splash);
  1071. if (splash_display->demura)
  1072. _sde_kms_splash_mem_put(sde_kms,
  1073. splash_display->demura);
  1074. }
  1075. sde_kms->splash_data.num_splash_displays--;
  1076. SDE_DEBUG("cont_splash handoff done, remaining:%d\n",
  1077. sde_kms->splash_data.num_splash_displays);
  1078. memset(splash_display, 0x0, sizeof(struct sde_splash_display));
  1079. }
  1080. static void _sde_kms_release_splash_resource(struct sde_kms *sde_kms,
  1081. struct drm_crtc *crtc)
  1082. {
  1083. struct msm_drm_private *priv;
  1084. struct sde_splash_display *splash_display;
  1085. int i;
  1086. if (!sde_kms || !crtc)
  1087. return;
  1088. priv = sde_kms->dev->dev_private;
  1089. if (!crtc->state->active || !sde_kms->splash_data.num_splash_displays)
  1090. return;
  1091. SDE_EVT32(DRMID(crtc), crtc->state->active,
  1092. sde_kms->splash_data.num_splash_displays);
  1093. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  1094. splash_display = &sde_kms->splash_data.splash_display[i];
  1095. if (splash_display->encoder &&
  1096. crtc == splash_display->encoder->crtc)
  1097. break;
  1098. }
  1099. if (i >= MAX_DSI_DISPLAYS)
  1100. return;
  1101. if (splash_display->cont_splash_enabled) {
  1102. sde_encoder_update_caps_for_cont_splash(splash_display->encoder,
  1103. splash_display, false);
  1104. _sde_kms_free_splash_display_data(sde_kms, splash_display);
  1105. }
  1106. /* remove the votes if all displays are done with splash */
  1107. if (!sde_kms->splash_data.num_splash_displays) {
  1108. for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++)
  1109. sde_power_data_bus_set_quota(&priv->phandle, i,
  1110. SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA,
  1111. priv->phandle.ib_quota[i] ? priv->phandle.ib_quota[i] :
  1112. SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA);
  1113. pm_runtime_put_sync(sde_kms->dev->dev);
  1114. }
  1115. }
  1116. static void sde_kms_cancel_delayed_work(struct drm_crtc *crtc)
  1117. {
  1118. struct drm_connector *connector;
  1119. struct drm_connector_list_iter iter;
  1120. struct drm_encoder *encoder;
  1121. /* Cancel CRTC work */
  1122. sde_crtc_cancel_delayed_work(crtc);
  1123. /* Cancel ESD work */
  1124. drm_connector_list_iter_begin(crtc->dev, &iter);
  1125. drm_for_each_connector_iter(connector, &iter)
  1126. if (drm_connector_mask(connector) & crtc->state->connector_mask)
  1127. sde_connector_schedule_status_work(connector, false);
  1128. drm_connector_list_iter_end(&iter);
  1129. /* Cancel Idle-PC work */
  1130. drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) {
  1131. if (sde_encoder_in_clone_mode(encoder))
  1132. continue;
  1133. sde_encoder_cancel_delayed_work(encoder);
  1134. }
  1135. }
  1136. int sde_kms_vm_pre_release(struct sde_kms *sde_kms,
  1137. struct drm_atomic_state *state, bool is_primary)
  1138. {
  1139. struct drm_crtc *crtc;
  1140. struct drm_encoder *encoder;
  1141. int rc = 0;
  1142. crtc = sde_kms_vm_get_vm_crtc(state);
  1143. if (!crtc)
  1144. return 0;
  1145. /* if vm_req is enabled, once CRTC on the commit is guaranteed */
  1146. sde_kms_wait_for_frame_transfer_complete(&sde_kms->base, crtc);
  1147. sde_dbg_set_hw_ownership_status(false);
  1148. sde_kms_cancel_delayed_work(crtc);
  1149. /* disable SDE encoder irq's */
  1150. drm_for_each_encoder_mask(encoder, crtc->dev,
  1151. crtc->state->encoder_mask) {
  1152. if (sde_encoder_in_clone_mode(encoder))
  1153. continue;
  1154. sde_encoder_irq_control(encoder, false);
  1155. }
  1156. if (is_primary) {
  1157. /* disable vblank events */
  1158. drm_crtc_vblank_off(crtc);
  1159. /* reset sw state */
  1160. sde_crtc_reset_sw_state(crtc);
  1161. }
  1162. return rc;
  1163. }
  1164. int sde_kms_vm_trusted_post_commit(struct sde_kms *sde_kms,
  1165. struct drm_atomic_state *state)
  1166. {
  1167. struct sde_vm_ops *vm_ops;
  1168. struct drm_crtc *crtc;
  1169. struct sde_crtc_state *cstate;
  1170. struct drm_crtc_state *new_cstate;
  1171. enum sde_crtc_vm_req vm_req;
  1172. int rc = 0;
  1173. if (!sde_kms || !sde_vm_is_enabled(sde_kms))
  1174. return -EINVAL;
  1175. vm_ops = sde_vm_get_ops(sde_kms);
  1176. crtc = sde_kms_vm_get_vm_crtc(state);
  1177. if (!crtc)
  1178. return 0;
  1179. new_cstate = drm_atomic_get_new_crtc_state(state, crtc);
  1180. cstate = to_sde_crtc_state(new_cstate);
  1181. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  1182. if (vm_req != VM_REQ_RELEASE)
  1183. return 0;
  1184. sde_kms_vm_pre_release(sde_kms, state, false);
  1185. sde_kms_vm_set_sid(sde_kms, 0);
  1186. sde_vm_lock(sde_kms);
  1187. if (vm_ops->vm_release)
  1188. rc = vm_ops->vm_release(sde_kms);
  1189. sde_vm_unlock(sde_kms);
  1190. return rc;
  1191. }
  1192. int sde_kms_vm_primary_post_commit(struct sde_kms *sde_kms,
  1193. struct drm_atomic_state *state)
  1194. {
  1195. struct sde_vm_ops *vm_ops;
  1196. struct sde_crtc_state *cstate;
  1197. struct drm_crtc *crtc;
  1198. struct drm_crtc_state *new_cstate;
  1199. enum sde_crtc_vm_req vm_req;
  1200. int rc = 0;
  1201. if (!sde_kms || !sde_vm_is_enabled(sde_kms))
  1202. return -EINVAL;
  1203. vm_ops = sde_vm_get_ops(sde_kms);
  1204. crtc = sde_kms_vm_get_vm_crtc(state);
  1205. if (!crtc)
  1206. return 0;
  1207. new_cstate = drm_atomic_get_new_crtc_state(state, crtc);
  1208. cstate = to_sde_crtc_state(new_cstate);
  1209. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  1210. if (vm_req != VM_REQ_RELEASE)
  1211. return 0;
  1212. /* handle SDE pre-release */
  1213. rc = sde_kms_vm_pre_release(sde_kms, state, true);
  1214. if (rc) {
  1215. SDE_ERROR("sde vm pre_release failed, rc=%d\n", rc);
  1216. goto exit;
  1217. }
  1218. /* properly handoff color processing features */
  1219. sde_cp_crtc_vm_primary_handoff(crtc);
  1220. sde_vm_lock(sde_kms);
  1221. /* handle non-SDE clients pre-release */
  1222. if (vm_ops->vm_client_pre_release) {
  1223. rc = vm_ops->vm_client_pre_release(sde_kms);
  1224. if (rc) {
  1225. SDE_ERROR("sde vm client pre_release failed, rc=%d\n",
  1226. rc);
  1227. sde_vm_unlock(sde_kms);
  1228. goto exit;
  1229. }
  1230. }
  1231. /* disable IRQ line */
  1232. sde_irq_update(&sde_kms->base, false);
  1233. /* release HW */
  1234. if (vm_ops->vm_release) {
  1235. rc = vm_ops->vm_release(sde_kms);
  1236. if (rc)
  1237. SDE_ERROR("sde vm assign failed, rc=%d\n", rc);
  1238. }
  1239. sde_vm_unlock(sde_kms);
  1240. _sde_crtc_vm_release_notify(crtc);
  1241. exit:
  1242. return rc;
  1243. }
  1244. static void sde_kms_complete_commit(struct msm_kms *kms,
  1245. struct drm_atomic_state *old_state)
  1246. {
  1247. struct sde_kms *sde_kms;
  1248. struct msm_drm_private *priv;
  1249. struct drm_crtc *crtc;
  1250. struct drm_crtc_state *old_crtc_state;
  1251. struct drm_connector *connector;
  1252. struct drm_connector_state *old_conn_state;
  1253. struct msm_display_conn_params params;
  1254. struct sde_vm_ops *vm_ops;
  1255. int i, rc = 0;
  1256. if (!kms || !old_state)
  1257. return;
  1258. sde_kms = to_sde_kms(kms);
  1259. if (!sde_kms->dev || !sde_kms->dev->dev_private)
  1260. return;
  1261. priv = sde_kms->dev->dev_private;
  1262. if (!sde_kms_power_resource_is_enabled(sde_kms->dev)) {
  1263. SDE_ERROR("power resource is not enabled\n");
  1264. return;
  1265. }
  1266. SDE_ATRACE_BEGIN("sde_kms_complete_commit");
  1267. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  1268. sde_crtc_complete_commit(crtc, old_crtc_state);
  1269. /* complete secure transitions if any */
  1270. if (sde_kms->smmu_state.transition_type == POST_COMMIT)
  1271. _sde_kms_secure_ctrl(sde_kms, crtc, true);
  1272. }
  1273. for_each_old_connector_in_state(old_state, connector,
  1274. old_conn_state, i) {
  1275. struct sde_connector *c_conn;
  1276. c_conn = to_sde_connector(connector);
  1277. if (!c_conn->ops.post_kickoff)
  1278. continue;
  1279. memset(&params, 0, sizeof(params));
  1280. sde_connector_complete_qsync_commit(connector, &params);
  1281. rc = c_conn->ops.post_kickoff(connector, &params);
  1282. if (rc) {
  1283. pr_err("Connector Post kickoff failed rc=%d\n",
  1284. rc);
  1285. }
  1286. }
  1287. vm_ops = sde_vm_get_ops(sde_kms);
  1288. if (vm_ops && vm_ops->vm_post_commit) {
  1289. rc = vm_ops->vm_post_commit(sde_kms, old_state);
  1290. if (rc)
  1291. SDE_ERROR("vm post commit failed, rc = %d\n",
  1292. rc);
  1293. }
  1294. _sde_kms_drm_check_dpms(old_state, false);
  1295. pm_runtime_put_sync(sde_kms->dev->dev);
  1296. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i)
  1297. _sde_kms_release_splash_resource(sde_kms, crtc);
  1298. SDE_EVT32_VERBOSE(SDE_EVTLOG_FUNC_EXIT);
  1299. SDE_ATRACE_END("sde_kms_complete_commit");
  1300. }
  1301. static void sde_kms_wait_for_commit_done(struct msm_kms *kms,
  1302. struct drm_crtc *crtc)
  1303. {
  1304. struct sde_kms *sde_kms;
  1305. struct drm_encoder *encoder;
  1306. struct drm_device *dev;
  1307. int ret;
  1308. bool cwb_disabling;
  1309. if (!kms || !crtc || !crtc->state) {
  1310. SDE_ERROR("invalid params\n");
  1311. return;
  1312. }
  1313. dev = crtc->dev;
  1314. sde_kms = to_sde_kms(kms);
  1315. if (!crtc->state->enable) {
  1316. SDE_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
  1317. return;
  1318. }
  1319. if (!crtc->state->active) {
  1320. SDE_DEBUG("[crtc:%d] not active\n", crtc->base.id);
  1321. return;
  1322. }
  1323. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  1324. SDE_ERROR("power resource is not enabled\n");
  1325. return;
  1326. }
  1327. SDE_ATRACE_BEGIN("sde_kms_wait_for_commit_done");
  1328. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  1329. cwb_disabling = false;
  1330. if (encoder->crtc != crtc) {
  1331. cwb_disabling = sde_encoder_is_cwb_disabling(encoder,
  1332. crtc);
  1333. if (!cwb_disabling)
  1334. continue;
  1335. }
  1336. /*
  1337. * Wait for post-flush if necessary to delay before
  1338. * plane_cleanup. For example, wait for vsync in case of video
  1339. * mode panels. This may be a no-op for command mode panels.
  1340. */
  1341. SDE_EVT32_VERBOSE(DRMID(crtc));
  1342. ret = sde_encoder_wait_for_event(encoder, cwb_disabling ?
  1343. MSM_ENC_TX_COMPLETE : MSM_ENC_COMMIT_DONE);
  1344. if (ret && ret != -EWOULDBLOCK) {
  1345. SDE_ERROR("wait for commit done returned %d\n", ret);
  1346. sde_crtc_request_frame_reset(crtc, encoder);
  1347. break;
  1348. }
  1349. sde_crtc_complete_flip(crtc, NULL);
  1350. if (cwb_disabling)
  1351. sde_encoder_virt_reset(encoder);
  1352. }
  1353. /* avoid system cache update to set rd-noalloc bit when NSE feature is enabled */
  1354. if (!test_bit(SDE_FEATURE_SYS_CACHE_NSE, sde_kms->catalog->features))
  1355. sde_crtc_static_cache_read_kickoff(crtc);
  1356. SDE_ATRACE_END("sde_ksm_wait_for_commit_done");
  1357. }
  1358. static void sde_kms_prepare_fence(struct msm_kms *kms,
  1359. struct drm_atomic_state *old_state)
  1360. {
  1361. struct drm_crtc *crtc;
  1362. struct drm_crtc_state *old_crtc_state;
  1363. int i;
  1364. if (!kms || !old_state || !old_state->dev || !old_state->acquire_ctx) {
  1365. SDE_ERROR("invalid argument(s)\n");
  1366. return;
  1367. }
  1368. SDE_ATRACE_BEGIN("sde_kms_prepare_fence");
  1369. /* old_state actually contains updated crtc pointers */
  1370. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  1371. if (crtc->state->active || crtc->state->active_changed)
  1372. sde_crtc_prepare_commit(crtc, old_crtc_state);
  1373. }
  1374. SDE_ATRACE_END("sde_kms_prepare_fence");
  1375. }
  1376. /**
  1377. * _sde_kms_get_displays - query for underlying display handles and cache them
  1378. * @sde_kms: Pointer to sde kms structure
  1379. * Returns: Zero on success
  1380. */
  1381. static int _sde_kms_get_displays(struct sde_kms *sde_kms)
  1382. {
  1383. int rc = -ENOMEM;
  1384. if (!sde_kms) {
  1385. SDE_ERROR("invalid sde kms\n");
  1386. return -EINVAL;
  1387. }
  1388. /* dsi */
  1389. sde_kms->dsi_displays = NULL;
  1390. sde_kms->dsi_display_count = dsi_display_get_num_of_displays();
  1391. if (sde_kms->dsi_display_count) {
  1392. sde_kms->dsi_displays = kcalloc(sde_kms->dsi_display_count,
  1393. sizeof(void *),
  1394. GFP_KERNEL);
  1395. if (!sde_kms->dsi_displays) {
  1396. SDE_ERROR("failed to allocate dsi displays\n");
  1397. goto exit_deinit_dsi;
  1398. }
  1399. sde_kms->dsi_display_count =
  1400. dsi_display_get_active_displays(sde_kms->dsi_displays,
  1401. sde_kms->dsi_display_count);
  1402. }
  1403. /* wb */
  1404. sde_kms->wb_displays = NULL;
  1405. sde_kms->wb_display_count = sde_wb_get_num_of_displays();
  1406. if (sde_kms->wb_display_count) {
  1407. sde_kms->wb_displays = kcalloc(sde_kms->wb_display_count,
  1408. sizeof(void *),
  1409. GFP_KERNEL);
  1410. if (!sde_kms->wb_displays) {
  1411. SDE_ERROR("failed to allocate wb displays\n");
  1412. goto exit_deinit_wb;
  1413. }
  1414. sde_kms->wb_display_count =
  1415. wb_display_get_displays(sde_kms->wb_displays,
  1416. sde_kms->wb_display_count);
  1417. }
  1418. /* dp */
  1419. sde_kms->dp_displays = NULL;
  1420. sde_kms->dp_display_count = dp_display_get_num_of_displays();
  1421. if (sde_kms->dp_display_count) {
  1422. sde_kms->dp_displays = kcalloc(sde_kms->dp_display_count,
  1423. sizeof(void *), GFP_KERNEL);
  1424. if (!sde_kms->dp_displays) {
  1425. SDE_ERROR("failed to allocate dp displays\n");
  1426. goto exit_deinit_dp;
  1427. }
  1428. sde_kms->dp_display_count =
  1429. dp_display_get_displays(sde_kms->dp_displays,
  1430. sde_kms->dp_display_count);
  1431. sde_kms->dp_stream_count = dp_display_get_num_of_streams();
  1432. }
  1433. return 0;
  1434. exit_deinit_dp:
  1435. kfree(sde_kms->dp_displays);
  1436. sde_kms->dp_stream_count = 0;
  1437. sde_kms->dp_display_count = 0;
  1438. sde_kms->dp_displays = NULL;
  1439. exit_deinit_wb:
  1440. kfree(sde_kms->wb_displays);
  1441. sde_kms->wb_display_count = 0;
  1442. sde_kms->wb_displays = NULL;
  1443. exit_deinit_dsi:
  1444. kfree(sde_kms->dsi_displays);
  1445. sde_kms->dsi_display_count = 0;
  1446. sde_kms->dsi_displays = NULL;
  1447. return rc;
  1448. }
  1449. /**
  1450. * _sde_kms_release_displays - release cache of underlying display handles
  1451. * @sde_kms: Pointer to sde kms structure
  1452. */
  1453. static void _sde_kms_release_displays(struct sde_kms *sde_kms)
  1454. {
  1455. if (!sde_kms) {
  1456. SDE_ERROR("invalid sde kms\n");
  1457. return;
  1458. }
  1459. kfree(sde_kms->wb_displays);
  1460. sde_kms->wb_displays = NULL;
  1461. sde_kms->wb_display_count = 0;
  1462. kfree(sde_kms->dsi_displays);
  1463. sde_kms->dsi_displays = NULL;
  1464. sde_kms->dsi_display_count = 0;
  1465. }
  1466. /**
  1467. * _sde_kms_setup_displays - create encoders, bridges and connectors
  1468. * for underlying displays
  1469. * @dev: Pointer to drm device structure
  1470. * @priv: Pointer to private drm device data
  1471. * @sde_kms: Pointer to sde kms structure
  1472. * Returns: Zero on success
  1473. */
  1474. static int _sde_kms_setup_displays(struct drm_device *dev,
  1475. struct msm_drm_private *priv,
  1476. struct sde_kms *sde_kms)
  1477. {
  1478. static const struct sde_connector_ops dsi_ops = {
  1479. .set_info_blob = dsi_conn_set_info_blob,
  1480. .detect = dsi_conn_detect,
  1481. .get_modes = dsi_connector_get_modes,
  1482. .pre_destroy = dsi_connector_put_modes,
  1483. .mode_valid = dsi_conn_mode_valid,
  1484. .get_info = dsi_display_get_info,
  1485. .set_backlight = dsi_display_set_backlight,
  1486. .soft_reset = dsi_display_soft_reset,
  1487. .pre_kickoff = dsi_conn_pre_kickoff,
  1488. .clk_ctrl = dsi_display_clk_ctrl,
  1489. .set_power = dsi_display_set_power,
  1490. .get_mode_info = dsi_conn_get_mode_info,
  1491. .get_dst_format = dsi_display_get_dst_format,
  1492. .post_kickoff = dsi_conn_post_kickoff,
  1493. .check_status = dsi_display_check_status,
  1494. .enable_event = dsi_conn_enable_event,
  1495. .cmd_transfer = dsi_display_cmd_transfer,
  1496. .cont_splash_config = dsi_display_cont_splash_config,
  1497. .cont_splash_res_disable = dsi_display_cont_splash_res_disable,
  1498. .get_panel_vfp = dsi_display_get_panel_vfp,
  1499. .get_default_lms = dsi_display_get_default_lms,
  1500. .cmd_receive = dsi_display_cmd_receive,
  1501. .install_properties = NULL,
  1502. .set_allowed_mode_switch = dsi_conn_set_allowed_mode_switch,
  1503. .set_dyn_bit_clk = dsi_conn_set_dyn_bit_clk,
  1504. .get_qsync_min_fps = dsi_conn_get_qsync_min_fps,
  1505. .get_avr_step_req = dsi_display_get_avr_step_req_fps,
  1506. .prepare_commit = dsi_conn_prepare_commit,
  1507. .set_submode_info = dsi_conn_set_submode_blob_info,
  1508. .get_num_lm_from_mode = dsi_conn_get_lm_from_mode,
  1509. .update_transfer_time = dsi_display_update_transfer_time,
  1510. };
  1511. static const struct sde_connector_ops wb_ops = {
  1512. .post_init = sde_wb_connector_post_init,
  1513. .set_info_blob = sde_wb_connector_set_info_blob,
  1514. .detect = sde_wb_connector_detect,
  1515. .get_modes = sde_wb_connector_get_modes,
  1516. .set_property = sde_wb_connector_set_property,
  1517. .get_info = sde_wb_get_info,
  1518. .soft_reset = NULL,
  1519. .get_mode_info = sde_wb_get_mode_info,
  1520. .get_dst_format = NULL,
  1521. .check_status = NULL,
  1522. .cmd_transfer = NULL,
  1523. .cont_splash_config = NULL,
  1524. .cont_splash_res_disable = NULL,
  1525. .get_panel_vfp = NULL,
  1526. .cmd_receive = NULL,
  1527. .install_properties = NULL,
  1528. .set_dyn_bit_clk = NULL,
  1529. .set_allowed_mode_switch = NULL,
  1530. .update_transfer_time = NULL,
  1531. };
  1532. static const struct sde_connector_ops dp_ops = {
  1533. .post_init = dp_connector_post_init,
  1534. .detect = dp_connector_detect,
  1535. .get_modes = dp_connector_get_modes,
  1536. .atomic_check = dp_connector_atomic_check,
  1537. .mode_valid = dp_connector_mode_valid,
  1538. .get_info = dp_connector_get_info,
  1539. .get_mode_info = dp_connector_get_mode_info,
  1540. .post_open = dp_connector_post_open,
  1541. .check_status = NULL,
  1542. .set_colorspace = dp_connector_set_colorspace,
  1543. .config_hdr = dp_connector_config_hdr,
  1544. .cmd_transfer = NULL,
  1545. .cont_splash_config = NULL,
  1546. .cont_splash_res_disable = NULL,
  1547. .get_panel_vfp = NULL,
  1548. .update_pps = dp_connector_update_pps,
  1549. .cmd_receive = NULL,
  1550. .install_properties = dp_connector_install_properties,
  1551. .set_allowed_mode_switch = NULL,
  1552. .set_dyn_bit_clk = NULL,
  1553. .update_transfer_time = NULL,
  1554. };
  1555. struct msm_display_info info;
  1556. struct drm_encoder *encoder;
  1557. void *display, *connector;
  1558. int i, max_encoders;
  1559. int rc = 0;
  1560. u32 dsc_count = 0, mixer_count = 0;
  1561. u32 max_dp_dsc_count, max_dp_mixer_count;
  1562. if (!dev || !priv || !sde_kms) {
  1563. SDE_ERROR("invalid argument(s)\n");
  1564. return -EINVAL;
  1565. }
  1566. max_encoders = sde_kms->dsi_display_count + sde_kms->wb_display_count +
  1567. sde_kms->dp_display_count +
  1568. sde_kms->dp_stream_count;
  1569. if (max_encoders > ARRAY_SIZE(priv->encoders)) {
  1570. max_encoders = ARRAY_SIZE(priv->encoders);
  1571. SDE_ERROR("capping number of displays to %d", max_encoders);
  1572. }
  1573. /* wb */
  1574. for (i = 0; i < sde_kms->wb_display_count &&
  1575. priv->num_encoders < max_encoders; ++i) {
  1576. display = sde_kms->wb_displays[i];
  1577. encoder = NULL;
  1578. memset(&info, 0x0, sizeof(info));
  1579. rc = sde_wb_get_info(NULL, &info, display);
  1580. if (rc) {
  1581. SDE_ERROR("wb get_info %d failed\n", i);
  1582. continue;
  1583. }
  1584. encoder = sde_encoder_init(dev, &info);
  1585. if (IS_ERR_OR_NULL(encoder)) {
  1586. SDE_ERROR("encoder init failed for wb %d\n", i);
  1587. continue;
  1588. }
  1589. rc = sde_wb_drm_init(display, encoder);
  1590. if (rc) {
  1591. SDE_ERROR("wb bridge %d init failed, %d\n", i, rc);
  1592. sde_encoder_destroy(encoder);
  1593. continue;
  1594. }
  1595. connector = sde_connector_init(dev,
  1596. encoder,
  1597. 0,
  1598. display,
  1599. &wb_ops,
  1600. DRM_CONNECTOR_POLL_HPD,
  1601. DRM_MODE_CONNECTOR_VIRTUAL);
  1602. if (connector) {
  1603. priv->encoders[priv->num_encoders++] = encoder;
  1604. priv->connectors[priv->num_connectors++] = connector;
  1605. } else {
  1606. SDE_ERROR("wb %d connector init failed\n", i);
  1607. sde_wb_drm_deinit(display);
  1608. sde_encoder_destroy(encoder);
  1609. }
  1610. }
  1611. /* dsi */
  1612. for (i = 0; i < sde_kms->dsi_display_count &&
  1613. priv->num_encoders < max_encoders; ++i) {
  1614. display = sde_kms->dsi_displays[i];
  1615. encoder = NULL;
  1616. memset(&info, 0x0, sizeof(info));
  1617. rc = dsi_display_get_info(NULL, &info, display);
  1618. if (rc) {
  1619. SDE_ERROR("dsi get_info %d failed\n", i);
  1620. continue;
  1621. }
  1622. encoder = sde_encoder_init(dev, &info);
  1623. if (IS_ERR_OR_NULL(encoder)) {
  1624. SDE_ERROR("encoder init failed for dsi %d\n", i);
  1625. continue;
  1626. }
  1627. rc = dsi_display_drm_bridge_init(display, encoder);
  1628. if (rc) {
  1629. SDE_ERROR("dsi bridge %d init failed, %d\n", i, rc);
  1630. sde_encoder_destroy(encoder);
  1631. continue;
  1632. }
  1633. connector = sde_connector_init(dev,
  1634. encoder,
  1635. dsi_display_get_drm_panel(display),
  1636. display,
  1637. &dsi_ops,
  1638. DRM_CONNECTOR_POLL_HPD,
  1639. DRM_MODE_CONNECTOR_DSI);
  1640. if (connector) {
  1641. priv->encoders[priv->num_encoders++] = encoder;
  1642. priv->connectors[priv->num_connectors++] = connector;
  1643. } else {
  1644. SDE_ERROR("dsi %d connector init failed\n", i);
  1645. dsi_display_drm_bridge_deinit(display);
  1646. sde_encoder_destroy(encoder);
  1647. continue;
  1648. }
  1649. rc = dsi_display_drm_ext_bridge_init(display,
  1650. encoder, connector);
  1651. if (rc) {
  1652. SDE_ERROR("dsi %d ext bridge init failed\n", rc);
  1653. dsi_display_drm_bridge_deinit(display);
  1654. sde_connector_destroy(connector);
  1655. sde_encoder_destroy(encoder);
  1656. }
  1657. dsc_count += info.dsc_count;
  1658. mixer_count += info.lm_count;
  1659. if (dsi_display_has_dsc_switch_support(display))
  1660. sde_kms->dsc_switch_support = true;
  1661. }
  1662. if (sde_kms->catalog->allowed_dsc_reservation_switch &&
  1663. !sde_kms->dsc_switch_support) {
  1664. SDE_DEBUG("dsc switch not supported\n");
  1665. sde_kms->catalog->allowed_dsc_reservation_switch = 0;
  1666. }
  1667. max_dp_mixer_count = sde_kms->catalog->mixer_count > mixer_count ?
  1668. sde_kms->catalog->mixer_count - mixer_count : 0;
  1669. max_dp_dsc_count = sde_kms->catalog->dsc_count > dsc_count ?
  1670. sde_kms->catalog->dsc_count - dsc_count : 0;
  1671. if (sde_kms->catalog->allowed_dsc_reservation_switch &
  1672. SDE_DP_DSC_RESERVATION_SWITCH)
  1673. max_dp_dsc_count = sde_kms->catalog->dsc_count;
  1674. /* dp */
  1675. for (i = 0; i < sde_kms->dp_display_count &&
  1676. priv->num_encoders < max_encoders; ++i) {
  1677. int idx;
  1678. display = sde_kms->dp_displays[i];
  1679. encoder = NULL;
  1680. memset(&info, 0x0, sizeof(info));
  1681. rc = dp_connector_get_info(NULL, &info, display);
  1682. if (rc) {
  1683. SDE_ERROR("dp get_info %d failed\n", i);
  1684. continue;
  1685. }
  1686. encoder = sde_encoder_init(dev, &info);
  1687. if (IS_ERR_OR_NULL(encoder)) {
  1688. SDE_ERROR("dp encoder init failed %d\n", i);
  1689. continue;
  1690. }
  1691. rc = dp_drm_bridge_init(display, encoder,
  1692. max_dp_mixer_count, max_dp_dsc_count);
  1693. if (rc) {
  1694. SDE_ERROR("dp bridge %d init failed, %d\n", i, rc);
  1695. sde_encoder_destroy(encoder);
  1696. continue;
  1697. }
  1698. connector = sde_connector_init(dev,
  1699. encoder,
  1700. NULL,
  1701. display,
  1702. &dp_ops,
  1703. DRM_CONNECTOR_POLL_HPD,
  1704. DRM_MODE_CONNECTOR_DisplayPort);
  1705. if (connector) {
  1706. priv->encoders[priv->num_encoders++] = encoder;
  1707. priv->connectors[priv->num_connectors++] = connector;
  1708. } else {
  1709. SDE_ERROR("dp %d connector init failed\n", i);
  1710. dp_drm_bridge_deinit(display);
  1711. sde_encoder_destroy(encoder);
  1712. }
  1713. /* update display cap to MST_MODE for DP MST encoders */
  1714. info.capabilities |= MSM_DISPLAY_CAP_MST_MODE;
  1715. for (idx = 0; idx < sde_kms->dp_stream_count &&
  1716. priv->num_encoders < max_encoders; idx++) {
  1717. info.h_tile_instance[0] = idx;
  1718. encoder = sde_encoder_init(dev, &info);
  1719. if (IS_ERR_OR_NULL(encoder)) {
  1720. SDE_ERROR("dp mst encoder init failed %d\n", i);
  1721. continue;
  1722. }
  1723. rc = dp_mst_drm_bridge_init(display, encoder);
  1724. if (rc) {
  1725. SDE_ERROR("dp mst bridge %d init failed, %d\n",
  1726. i, rc);
  1727. sde_encoder_destroy(encoder);
  1728. continue;
  1729. }
  1730. priv->encoders[priv->num_encoders++] = encoder;
  1731. }
  1732. }
  1733. return 0;
  1734. }
  1735. static void _sde_kms_drm_obj_destroy(struct sde_kms *sde_kms)
  1736. {
  1737. struct msm_drm_private *priv;
  1738. int i;
  1739. if (!sde_kms) {
  1740. SDE_ERROR("invalid sde_kms\n");
  1741. return;
  1742. } else if (!sde_kms->dev) {
  1743. SDE_ERROR("invalid dev\n");
  1744. return;
  1745. } else if (!sde_kms->dev->dev_private) {
  1746. SDE_ERROR("invalid dev_private\n");
  1747. return;
  1748. }
  1749. priv = sde_kms->dev->dev_private;
  1750. for (i = 0; i < priv->num_crtcs; i++)
  1751. priv->crtcs[i]->funcs->destroy(priv->crtcs[i]);
  1752. priv->num_crtcs = 0;
  1753. for (i = 0; i < priv->num_planes; i++)
  1754. priv->planes[i]->funcs->destroy(priv->planes[i]);
  1755. priv->num_planes = 0;
  1756. for (i = 0; i < priv->num_connectors; i++)
  1757. priv->connectors[i]->funcs->destroy(priv->connectors[i]);
  1758. priv->num_connectors = 0;
  1759. for (i = 0; i < priv->num_encoders; i++)
  1760. priv->encoders[i]->funcs->destroy(priv->encoders[i]);
  1761. priv->num_encoders = 0;
  1762. _sde_kms_release_displays(sde_kms);
  1763. }
  1764. static int _sde_kms_drm_obj_init(struct sde_kms *sde_kms)
  1765. {
  1766. struct drm_device *dev;
  1767. struct drm_plane *primary_planes[MAX_PLANES], *plane;
  1768. struct drm_crtc *crtc;
  1769. struct msm_drm_private *priv;
  1770. struct sde_mdss_cfg *catalog;
  1771. int primary_planes_idx = 0, i, ret;
  1772. int max_crtc_count;
  1773. u32 sspp_id[MAX_PLANES];
  1774. u32 master_plane_id[MAX_PLANES];
  1775. u32 num_virt_planes = 0;
  1776. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  1777. SDE_ERROR("invalid sde_kms\n");
  1778. return -EINVAL;
  1779. }
  1780. dev = sde_kms->dev;
  1781. priv = dev->dev_private;
  1782. catalog = sde_kms->catalog;
  1783. ret = sde_core_irq_domain_add(sde_kms);
  1784. if (ret)
  1785. goto fail_irq;
  1786. /*
  1787. * Query for underlying display drivers, and create connectors,
  1788. * bridges and encoders for them.
  1789. */
  1790. if (!_sde_kms_get_displays(sde_kms))
  1791. (void)_sde_kms_setup_displays(dev, priv, sde_kms);
  1792. max_crtc_count = min(catalog->mixer_count, priv->num_encoders);
  1793. /* Create the planes */
  1794. for (i = 0; i < catalog->sspp_count; i++) {
  1795. bool primary = true;
  1796. if (primary_planes_idx >= max_crtc_count)
  1797. primary = false;
  1798. plane = sde_plane_init(dev, catalog->sspp[i].id, primary,
  1799. (1UL << max_crtc_count) - 1, 0);
  1800. if (IS_ERR(plane)) {
  1801. SDE_ERROR("sde_plane_init failed\n");
  1802. ret = PTR_ERR(plane);
  1803. goto fail;
  1804. }
  1805. priv->planes[priv->num_planes++] = plane;
  1806. if (primary)
  1807. primary_planes[primary_planes_idx++] = plane;
  1808. if (sde_hw_sspp_multirect_enabled(&catalog->sspp[i]) &&
  1809. sde_is_custom_client()) {
  1810. int priority =
  1811. catalog->sspp[i].sblk->smart_dma_priority;
  1812. sspp_id[priority - 1] = catalog->sspp[i].id;
  1813. master_plane_id[priority - 1] = plane->base.id;
  1814. num_virt_planes++;
  1815. }
  1816. }
  1817. /* Initialize smart DMA virtual planes */
  1818. for (i = 0; i < num_virt_planes; i++) {
  1819. plane = sde_plane_init(dev, sspp_id[i], false,
  1820. (1UL << max_crtc_count) - 1, master_plane_id[i]);
  1821. if (IS_ERR(plane)) {
  1822. SDE_ERROR("sde_plane for virtual SSPP init failed\n");
  1823. ret = PTR_ERR(plane);
  1824. goto fail;
  1825. }
  1826. priv->planes[priv->num_planes++] = plane;
  1827. }
  1828. max_crtc_count = min(max_crtc_count, primary_planes_idx);
  1829. /* Create one CRTC per encoder */
  1830. for (i = 0; i < max_crtc_count; i++) {
  1831. crtc = sde_crtc_init(dev, primary_planes[i]);
  1832. if (IS_ERR(crtc)) {
  1833. ret = PTR_ERR(crtc);
  1834. goto fail;
  1835. }
  1836. priv->crtcs[priv->num_crtcs++] = crtc;
  1837. }
  1838. if (sde_is_custom_client()) {
  1839. /* All CRTCs are compatible with all planes */
  1840. for (i = 0; i < priv->num_planes; i++)
  1841. priv->planes[i]->possible_crtcs =
  1842. (1 << priv->num_crtcs) - 1;
  1843. }
  1844. /* All CRTCs are compatible with all encoders */
  1845. for (i = 0; i < priv->num_encoders; i++)
  1846. priv->encoders[i]->possible_crtcs = (1 << priv->num_crtcs) - 1;
  1847. return 0;
  1848. fail:
  1849. _sde_kms_drm_obj_destroy(sde_kms);
  1850. fail_irq:
  1851. sde_core_irq_domain_fini(sde_kms);
  1852. return ret;
  1853. }
  1854. /**
  1855. * sde_kms_timeline_status - provides current timeline status
  1856. * This API should be called without mode config lock.
  1857. * @dev: Pointer to drm device
  1858. */
  1859. void sde_kms_timeline_status(struct drm_device *dev)
  1860. {
  1861. struct drm_crtc *crtc;
  1862. struct drm_connector *conn;
  1863. struct drm_connector_list_iter conn_iter;
  1864. if (!dev) {
  1865. SDE_ERROR("invalid drm device node\n");
  1866. return;
  1867. }
  1868. drm_for_each_crtc(crtc, dev)
  1869. sde_crtc_timeline_status(crtc);
  1870. if (mutex_is_locked(&dev->mode_config.mutex)) {
  1871. /*
  1872. *Probably locked from last close dumping status anyway
  1873. */
  1874. SDE_ERROR("dumping conn_timeline without mode_config lock\n");
  1875. drm_connector_list_iter_begin(dev, &conn_iter);
  1876. drm_for_each_connector_iter(conn, &conn_iter)
  1877. sde_conn_timeline_status(conn);
  1878. drm_connector_list_iter_end(&conn_iter);
  1879. return;
  1880. }
  1881. mutex_lock(&dev->mode_config.mutex);
  1882. drm_connector_list_iter_begin(dev, &conn_iter);
  1883. drm_for_each_connector_iter(conn, &conn_iter)
  1884. sde_conn_timeline_status(conn);
  1885. drm_connector_list_iter_end(&conn_iter);
  1886. mutex_unlock(&dev->mode_config.mutex);
  1887. }
  1888. static int sde_kms_postinit(struct msm_kms *kms)
  1889. {
  1890. struct sde_kms *sde_kms = to_sde_kms(kms);
  1891. struct drm_device *dev;
  1892. struct drm_crtc *crtc;
  1893. struct msm_drm_private *priv;
  1894. int i, rc;
  1895. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev ||
  1896. !sde_kms->dev->dev_private) {
  1897. SDE_ERROR("invalid sde_kms\n");
  1898. return -EINVAL;
  1899. }
  1900. dev = sde_kms->dev;
  1901. priv = sde_kms->dev->dev_private;
  1902. /*
  1903. * Handle (re)initializations during power enable, the sde power
  1904. * event call has to be after drm_irq_install to handle irq update.
  1905. */
  1906. sde_kms_handle_power_event(SDE_POWER_EVENT_POST_ENABLE, sde_kms);
  1907. sde_kms->power_event = sde_power_handle_register_event(&priv->phandle,
  1908. SDE_POWER_EVENT_POST_ENABLE |
  1909. SDE_POWER_EVENT_PRE_DISABLE,
  1910. sde_kms_handle_power_event, sde_kms, "kms");
  1911. if (sde_kms->splash_data.num_splash_displays) {
  1912. SDE_DEBUG("Skipping MDP Resources disable\n");
  1913. } else {
  1914. for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++)
  1915. sde_power_data_bus_set_quota(&priv->phandle, i,
  1916. SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA,
  1917. SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA);
  1918. pm_runtime_put_sync(sde_kms->dev->dev);
  1919. }
  1920. rc = _sde_debugfs_init(sde_kms);
  1921. if (rc)
  1922. SDE_ERROR("sde_debugfs init failed: %d\n", rc);
  1923. drm_for_each_crtc(crtc, dev)
  1924. sde_crtc_post_init(dev, crtc);
  1925. return rc;
  1926. }
  1927. static long sde_kms_round_pixclk(struct msm_kms *kms, unsigned long rate,
  1928. struct drm_encoder *encoder)
  1929. {
  1930. return rate;
  1931. }
  1932. static void _sde_kms_hw_destroy(struct sde_kms *sde_kms,
  1933. struct platform_device *pdev)
  1934. {
  1935. struct drm_device *dev;
  1936. struct msm_drm_private *priv;
  1937. struct sde_vm_ops *vm_ops;
  1938. int i;
  1939. if (!sde_kms || !pdev)
  1940. return;
  1941. dev = sde_kms->dev;
  1942. if (!dev)
  1943. return;
  1944. priv = dev->dev_private;
  1945. if (!priv)
  1946. return;
  1947. if (sde_kms->genpd_init) {
  1948. sde_kms->genpd_init = false;
  1949. pm_genpd_remove(&sde_kms->genpd);
  1950. of_genpd_del_provider(pdev->dev.of_node);
  1951. }
  1952. vm_ops = sde_vm_get_ops(sde_kms);
  1953. if (vm_ops && vm_ops->vm_deinit)
  1954. vm_ops->vm_deinit(sde_kms, vm_ops);
  1955. if (sde_kms->hw_intr)
  1956. sde_hw_intr_destroy(sde_kms->hw_intr);
  1957. sde_kms->hw_intr = NULL;
  1958. if (sde_kms->power_event)
  1959. sde_power_handle_unregister_event(
  1960. &priv->phandle, sde_kms->power_event);
  1961. _sde_kms_release_displays(sde_kms);
  1962. _sde_kms_unmap_all_splash_regions(sde_kms);
  1963. if (sde_kms->catalog) {
  1964. for (i = 0; i < sde_kms->catalog->vbif_count; i++) {
  1965. u32 vbif_idx = sde_kms->catalog->vbif[i].id;
  1966. if ((vbif_idx < VBIF_MAX) && sde_kms->hw_vbif[vbif_idx])
  1967. sde_hw_vbif_destroy(sde_kms->hw_vbif[vbif_idx]);
  1968. }
  1969. }
  1970. if (sde_kms->rm_init)
  1971. sde_rm_destroy(&sde_kms->rm);
  1972. sde_kms->rm_init = false;
  1973. if (sde_kms->catalog)
  1974. sde_hw_catalog_deinit(sde_kms->catalog);
  1975. sde_kms->catalog = NULL;
  1976. if (sde_kms->sid)
  1977. msm_iounmap(pdev, sde_kms->sid);
  1978. sde_kms->sid = NULL;
  1979. if (sde_kms->reg_dma)
  1980. msm_iounmap(pdev, sde_kms->reg_dma);
  1981. sde_kms->reg_dma = NULL;
  1982. if (sde_kms->vbif[VBIF_NRT])
  1983. msm_iounmap(pdev, sde_kms->vbif[VBIF_NRT]);
  1984. sde_kms->vbif[VBIF_NRT] = NULL;
  1985. if (sde_kms->vbif[VBIF_RT])
  1986. msm_iounmap(pdev, sde_kms->vbif[VBIF_RT]);
  1987. sde_kms->vbif[VBIF_RT] = NULL;
  1988. if (sde_kms->mmio)
  1989. msm_iounmap(pdev, sde_kms->mmio);
  1990. sde_kms->mmio = NULL;
  1991. sde_reg_dma_deinit();
  1992. _sde_kms_mmu_destroy(sde_kms);
  1993. }
  1994. int sde_kms_mmu_detach(struct sde_kms *sde_kms, bool secure_only)
  1995. {
  1996. int i;
  1997. if (!sde_kms)
  1998. return -EINVAL;
  1999. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  2000. struct msm_mmu *mmu;
  2001. struct msm_gem_address_space *aspace = sde_kms->aspace[i];
  2002. if (!aspace)
  2003. continue;
  2004. mmu = sde_kms->aspace[i]->mmu;
  2005. if (secure_only &&
  2006. !aspace->mmu->funcs->is_domain_secure(mmu))
  2007. continue;
  2008. /* cleanup aspace before detaching */
  2009. msm_gem_aspace_domain_attach_detach_update(aspace, true);
  2010. SDE_DEBUG("Detaching domain:%d\n", i);
  2011. aspace->mmu->funcs->detach(mmu, (const char **)iommu_ports,
  2012. ARRAY_SIZE(iommu_ports));
  2013. aspace->domain_attached = false;
  2014. }
  2015. return 0;
  2016. }
  2017. int sde_kms_mmu_attach(struct sde_kms *sde_kms, bool secure_only)
  2018. {
  2019. int i;
  2020. if (!sde_kms)
  2021. return -EINVAL;
  2022. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  2023. struct msm_mmu *mmu;
  2024. struct msm_gem_address_space *aspace = sde_kms->aspace[i];
  2025. if (!aspace)
  2026. continue;
  2027. mmu = sde_kms->aspace[i]->mmu;
  2028. if (secure_only &&
  2029. !aspace->mmu->funcs->is_domain_secure(mmu))
  2030. continue;
  2031. SDE_DEBUG("Attaching domain:%d\n", i);
  2032. aspace->mmu->funcs->attach(mmu, (const char **)iommu_ports,
  2033. ARRAY_SIZE(iommu_ports));
  2034. aspace->domain_attached = true;
  2035. msm_gem_aspace_domain_attach_detach_update(aspace, false);
  2036. }
  2037. return 0;
  2038. }
  2039. static void sde_kms_destroy(struct msm_kms *kms)
  2040. {
  2041. struct sde_kms *sde_kms;
  2042. struct drm_device *dev;
  2043. if (!kms) {
  2044. SDE_ERROR("invalid kms\n");
  2045. return;
  2046. }
  2047. sde_kms = to_sde_kms(kms);
  2048. dev = sde_kms->dev;
  2049. if (!dev || !dev->dev) {
  2050. SDE_ERROR("invalid device\n");
  2051. return;
  2052. }
  2053. _sde_kms_hw_destroy(sde_kms, to_platform_device(dev->dev));
  2054. kfree(sde_kms);
  2055. }
  2056. static void sde_kms_helper_clear_dim_layers(struct drm_atomic_state *state, struct drm_crtc *crtc)
  2057. {
  2058. struct drm_crtc_state *crtc_state = NULL;
  2059. struct sde_crtc_state *c_state;
  2060. if (!state || !crtc) {
  2061. SDE_ERROR("invalid params\n");
  2062. return;
  2063. }
  2064. crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
  2065. c_state = to_sde_crtc_state(crtc_state);
  2066. _sde_crtc_clear_dim_layers_v1(crtc_state);
  2067. set_bit(SDE_CRTC_DIRTY_DIM_LAYERS, c_state->dirty);
  2068. }
  2069. static int sde_kms_set_crtc_for_conn(struct drm_device *dev,
  2070. struct drm_encoder *enc, struct drm_atomic_state *state)
  2071. {
  2072. struct drm_connector *conn = NULL;
  2073. struct drm_connector *tmp_conn = NULL;
  2074. struct drm_connector_list_iter conn_iter;
  2075. struct drm_crtc_state *crtc_state = NULL;
  2076. struct drm_connector_state *conn_state = NULL;
  2077. int ret = 0;
  2078. drm_connector_list_iter_begin(dev, &conn_iter);
  2079. drm_for_each_connector_iter(tmp_conn, &conn_iter) {
  2080. if (enc == tmp_conn->state->best_encoder) {
  2081. conn = tmp_conn;
  2082. break;
  2083. }
  2084. }
  2085. drm_connector_list_iter_end(&conn_iter);
  2086. if (!conn || !enc->crtc) {
  2087. SDE_ERROR("invalid params for enc:%d\n", DRMID(enc));
  2088. return -EINVAL;
  2089. }
  2090. crtc_state = drm_atomic_get_crtc_state(state, enc->crtc);
  2091. if (IS_ERR(crtc_state)) {
  2092. ret = PTR_ERR(crtc_state);
  2093. SDE_ERROR("error %d getting crtc %d state\n",
  2094. ret, DRMID(enc->crtc));
  2095. return ret;
  2096. }
  2097. conn_state = drm_atomic_get_connector_state(state, conn);
  2098. if (IS_ERR(conn_state)) {
  2099. ret = PTR_ERR(conn_state);
  2100. SDE_ERROR("error %d getting connector %d state\n",
  2101. ret, DRMID(conn));
  2102. return ret;
  2103. }
  2104. crtc_state->active = true;
  2105. ret = drm_atomic_set_crtc_for_connector(conn_state, enc->crtc);
  2106. if (ret)
  2107. SDE_ERROR("error %d setting the crtc\n", ret);
  2108. return ret;
  2109. }
  2110. static void _sde_kms_plane_force_remove(struct drm_plane *plane,
  2111. struct drm_atomic_state *state)
  2112. {
  2113. struct drm_plane_state *plane_state;
  2114. int ret = 0;
  2115. plane_state = drm_atomic_get_plane_state(state, plane);
  2116. if (IS_ERR(plane_state)) {
  2117. ret = PTR_ERR(plane_state);
  2118. SDE_ERROR("error %d getting plane %d state\n",
  2119. ret, plane->base.id);
  2120. return;
  2121. }
  2122. plane->old_fb = plane->fb;
  2123. SDE_DEBUG("disabling plane %d\n", plane->base.id);
  2124. ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
  2125. if (ret != 0)
  2126. SDE_ERROR("error %d disabling plane %d\n", ret,
  2127. plane->base.id);
  2128. drm_atomic_set_fb_for_plane(plane_state, NULL);
  2129. }
  2130. static int _sde_kms_remove_fbs(struct sde_kms *sde_kms, struct drm_file *file,
  2131. struct drm_atomic_state *state)
  2132. {
  2133. struct drm_device *dev = sde_kms->dev;
  2134. struct drm_framebuffer *fb, *tfb;
  2135. struct list_head fbs;
  2136. struct drm_plane *plane;
  2137. struct drm_crtc *crtc = NULL;
  2138. unsigned int crtc_mask = 0;
  2139. int ret = 0;
  2140. INIT_LIST_HEAD(&fbs);
  2141. list_for_each_entry_safe(fb, tfb, &file->fbs, filp_head) {
  2142. if (drm_framebuffer_read_refcount(fb) > 1) {
  2143. list_move_tail(&fb->filp_head, &fbs);
  2144. drm_for_each_plane(plane, dev) {
  2145. if (plane->state && plane->state->fb == fb) {
  2146. if (plane->state->crtc)
  2147. crtc_mask |= drm_crtc_mask(plane->state->crtc);
  2148. _sde_kms_plane_force_remove(plane, state);
  2149. }
  2150. }
  2151. } else {
  2152. list_del_init(&fb->filp_head);
  2153. drm_framebuffer_put(fb);
  2154. }
  2155. }
  2156. if (list_empty(&fbs)) {
  2157. SDE_DEBUG("skip commit as no fb(s)\n");
  2158. return 0;
  2159. }
  2160. drm_for_each_crtc(crtc, dev) {
  2161. if ((crtc_mask & drm_crtc_mask(crtc)) && crtc->state->active) {
  2162. struct drm_encoder *drm_enc;
  2163. drm_for_each_encoder_mask(drm_enc, crtc->dev,
  2164. crtc->state->encoder_mask) {
  2165. ret = sde_kms_set_crtc_for_conn(dev, drm_enc, state);
  2166. if (ret)
  2167. goto error;
  2168. }
  2169. sde_kms_helper_clear_dim_layers(state, crtc);
  2170. }
  2171. }
  2172. SDE_EVT32(state, crtc_mask);
  2173. SDE_DEBUG("null commit after removing all the pipes\n");
  2174. ret = drm_atomic_commit(state);
  2175. error:
  2176. if (ret) {
  2177. /*
  2178. * move the fbs back to original list, so it would be
  2179. * handled during drm_release
  2180. */
  2181. list_for_each_entry_safe(fb, tfb, &fbs, filp_head)
  2182. list_move_tail(&fb->filp_head, &file->fbs);
  2183. if (ret == -EDEADLK || ret == -ERESTARTSYS)
  2184. SDE_DEBUG("atomic commit failed in preclose, ret:%d\n", ret);
  2185. else
  2186. SDE_ERROR("atomic commit failed in preclose, ret:%d\n", ret);
  2187. goto end;
  2188. }
  2189. while (!list_empty(&fbs)) {
  2190. fb = list_first_entry(&fbs, typeof(*fb), filp_head);
  2191. list_del_init(&fb->filp_head);
  2192. drm_framebuffer_put(fb);
  2193. }
  2194. end:
  2195. return ret;
  2196. }
  2197. static void sde_kms_preclose(struct msm_kms *kms, struct drm_file *file)
  2198. {
  2199. struct sde_kms *sde_kms = to_sde_kms(kms);
  2200. struct drm_device *dev = sde_kms->dev;
  2201. struct msm_drm_private *priv = dev->dev_private;
  2202. unsigned int i;
  2203. struct drm_atomic_state *state = NULL;
  2204. struct drm_modeset_acquire_ctx ctx;
  2205. int ret = 0;
  2206. /* cancel pending flip event */
  2207. for (i = 0; i < priv->num_crtcs; i++)
  2208. sde_crtc_complete_flip(priv->crtcs[i], file);
  2209. drm_modeset_acquire_init(&ctx, 0);
  2210. retry:
  2211. ret = drm_modeset_lock_all_ctx(dev, &ctx);
  2212. if (ret == -EDEADLK) {
  2213. drm_modeset_backoff(&ctx);
  2214. goto retry;
  2215. } else if (WARN_ON(ret)) {
  2216. goto end;
  2217. }
  2218. state = drm_atomic_state_alloc(dev);
  2219. if (!state) {
  2220. ret = -ENOMEM;
  2221. goto end;
  2222. }
  2223. state->acquire_ctx = &ctx;
  2224. for (i = 0; i < TEARDOWN_DEADLOCK_RETRY_MAX; i++) {
  2225. ret = _sde_kms_remove_fbs(sde_kms, file, state);
  2226. if (ret != -EDEADLK && ret != -ERESTARTSYS)
  2227. break;
  2228. drm_atomic_state_clear(state);
  2229. drm_modeset_backoff(&ctx);
  2230. }
  2231. end:
  2232. if (state)
  2233. drm_atomic_state_put(state);
  2234. SDE_DEBUG("sde preclose done, ret:%d\n", ret);
  2235. drm_modeset_drop_locks(&ctx);
  2236. drm_modeset_acquire_fini(&ctx);
  2237. }
  2238. static int _sde_kms_helper_reset_custom_properties(struct sde_kms *sde_kms,
  2239. struct drm_atomic_state *state)
  2240. {
  2241. struct drm_device *dev = sde_kms->dev;
  2242. struct drm_plane *plane;
  2243. struct drm_plane_state *plane_state;
  2244. struct drm_crtc *crtc;
  2245. struct drm_crtc_state *crtc_state;
  2246. struct drm_connector *conn;
  2247. struct drm_connector_state *conn_state;
  2248. struct drm_connector_list_iter conn_iter;
  2249. int ret = 0;
  2250. drm_for_each_plane(plane, dev) {
  2251. plane_state = drm_atomic_get_plane_state(state, plane);
  2252. if (IS_ERR(plane_state)) {
  2253. ret = PTR_ERR(plane_state);
  2254. SDE_ERROR("error %d getting plane %d state\n",
  2255. ret, DRMID(plane));
  2256. return ret;
  2257. }
  2258. ret = sde_plane_helper_reset_custom_properties(plane,
  2259. plane_state);
  2260. if (ret) {
  2261. SDE_ERROR("error %d resetting plane props %d\n",
  2262. ret, DRMID(plane));
  2263. return ret;
  2264. }
  2265. }
  2266. drm_for_each_crtc(crtc, dev) {
  2267. crtc_state = drm_atomic_get_crtc_state(state, crtc);
  2268. if (IS_ERR(crtc_state)) {
  2269. ret = PTR_ERR(crtc_state);
  2270. SDE_ERROR("error %d getting crtc %d state\n",
  2271. ret, DRMID(crtc));
  2272. return ret;
  2273. }
  2274. ret = sde_crtc_helper_reset_custom_properties(crtc, crtc_state);
  2275. if (ret) {
  2276. SDE_ERROR("error %d resetting crtc props %d\n",
  2277. ret, DRMID(crtc));
  2278. return ret;
  2279. }
  2280. }
  2281. drm_connector_list_iter_begin(dev, &conn_iter);
  2282. drm_for_each_connector_iter(conn, &conn_iter) {
  2283. conn_state = drm_atomic_get_connector_state(state, conn);
  2284. if (IS_ERR(conn_state)) {
  2285. ret = PTR_ERR(conn_state);
  2286. SDE_ERROR("error %d getting connector %d state\n",
  2287. ret, DRMID(conn));
  2288. return ret;
  2289. }
  2290. ret = sde_connector_helper_reset_custom_properties(conn,
  2291. conn_state);
  2292. if (ret) {
  2293. SDE_ERROR("error %d resetting connector props %d\n",
  2294. ret, DRMID(conn));
  2295. return ret;
  2296. }
  2297. }
  2298. drm_connector_list_iter_end(&conn_iter);
  2299. return ret;
  2300. }
  2301. static void sde_kms_lastclose(struct msm_kms *kms)
  2302. {
  2303. struct sde_kms *sde_kms;
  2304. struct drm_device *dev;
  2305. struct drm_atomic_state *state;
  2306. struct drm_modeset_acquire_ctx ctx;
  2307. int ret;
  2308. if (!kms) {
  2309. SDE_ERROR("invalid argument\n");
  2310. return;
  2311. }
  2312. sde_kms = to_sde_kms(kms);
  2313. dev = sde_kms->dev;
  2314. drm_modeset_acquire_init(&ctx, 0);
  2315. state = drm_atomic_state_alloc(dev);
  2316. if (!state) {
  2317. ret = -ENOMEM;
  2318. goto out_ctx;
  2319. }
  2320. state->acquire_ctx = &ctx;
  2321. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  2322. retry:
  2323. ret = drm_modeset_lock_all_ctx(dev, &ctx);
  2324. if (ret)
  2325. goto out_state;
  2326. ret = _sde_kms_helper_reset_custom_properties(sde_kms, state);
  2327. if (ret)
  2328. goto out_state;
  2329. ret = drm_atomic_commit(state);
  2330. out_state:
  2331. if (ret == -EDEADLK)
  2332. goto backoff;
  2333. drm_atomic_state_put(state);
  2334. out_ctx:
  2335. drm_modeset_drop_locks(&ctx);
  2336. drm_modeset_acquire_fini(&ctx);
  2337. if (ret)
  2338. SDE_ERROR("kms lastclose failed: %d\n", ret);
  2339. SDE_EVT32(ret, SDE_EVTLOG_FUNC_EXIT);
  2340. return;
  2341. backoff:
  2342. drm_atomic_state_clear(state);
  2343. drm_modeset_backoff(&ctx);
  2344. SDE_EVT32(ret, SDE_EVTLOG_FUNC_CASE1);
  2345. goto retry;
  2346. }
  2347. static int _sde_kms_validate_vm_request(struct drm_atomic_state *state, struct sde_kms *sde_kms,
  2348. enum sde_crtc_vm_req vm_req, bool vm_owns_hw)
  2349. {
  2350. struct drm_crtc *crtc, *active_crtc = NULL, *global_active_crtc = NULL;
  2351. struct drm_crtc_state *new_cstate, *old_cstate, *active_cstate;
  2352. struct drm_encoder *encoder;
  2353. struct drm_connector *connector;
  2354. struct drm_connector_state *new_connstate;
  2355. struct sde_vm_ops *vm_ops = sde_vm_get_ops(sde_kms);
  2356. struct sde_mdss_cfg *catalog = sde_kms->catalog;
  2357. struct sde_connector *sde_conn;
  2358. struct dsi_display *dsi_display;
  2359. uint32_t i, commit_crtc_cnt = 0, global_crtc_cnt = 0;
  2360. uint32_t crtc_encoder_cnt = 0;
  2361. enum sde_crtc_idle_pc_state idle_pc_state;
  2362. int rc = 0;
  2363. for_each_oldnew_crtc_in_state(state, crtc, old_cstate, new_cstate, i) {
  2364. struct sde_crtc_state *new_state = NULL;
  2365. if (!new_cstate->active && !old_cstate->active)
  2366. continue;
  2367. new_state = to_sde_crtc_state(new_cstate);
  2368. idle_pc_state = sde_crtc_get_property(new_state, CRTC_PROP_IDLE_PC_STATE);
  2369. active_crtc = crtc;
  2370. active_cstate = new_cstate;
  2371. commit_crtc_cnt++;
  2372. }
  2373. list_for_each_entry(crtc, &sde_kms->dev->mode_config.crtc_list, head) {
  2374. if (!crtc->state->active)
  2375. continue;
  2376. global_crtc_cnt++;
  2377. global_active_crtc = crtc;
  2378. }
  2379. if (active_crtc) {
  2380. drm_for_each_encoder_mask(encoder, active_crtc->dev, active_cstate->encoder_mask)
  2381. crtc_encoder_cnt++;
  2382. }
  2383. for_each_new_connector_in_state(state, connector, new_connstate, i) {
  2384. int conn_mask = active_cstate->connector_mask;
  2385. if (drm_connector_mask(connector) & conn_mask) {
  2386. sde_conn = to_sde_connector(connector);
  2387. dsi_display = (struct dsi_display *) sde_conn->display;
  2388. SDE_EVT32(DRMID(connector), DRMID(active_crtc), i, dsi_display->type,
  2389. dsi_display->trusted_vm_env);
  2390. SDE_DEBUG("VM display:%s, conn:%d, crtc:%d, type:%d, tvm:%d\n",
  2391. dsi_display->name, DRMID(connector), DRMID(active_crtc),
  2392. dsi_display->type, dsi_display->trusted_vm_env);
  2393. break;
  2394. }
  2395. }
  2396. /* Check for single crtc commits only on valid VM requests */
  2397. if (active_crtc && global_active_crtc &&
  2398. (commit_crtc_cnt > catalog->max_trusted_vm_displays ||
  2399. global_crtc_cnt > catalog->max_trusted_vm_displays ||
  2400. active_crtc != global_active_crtc)) {
  2401. SDE_ERROR("VM switch failed; MAX:%d a_cnt:%d g_cnt:%d a_crtc:%d g_crtc:%d\n",
  2402. catalog->max_trusted_vm_displays, commit_crtc_cnt, global_crtc_cnt,
  2403. DRMID(active_crtc), DRMID(global_active_crtc));
  2404. return -E2BIG;
  2405. } else if ((vm_req == VM_REQ_RELEASE) &&
  2406. ((idle_pc_state == IDLE_PC_ENABLE) ||
  2407. (crtc_encoder_cnt > TRUSTED_VM_MAX_ENCODER_PER_CRTC))) {
  2408. /*
  2409. * disable idle-pc before releasing the HW
  2410. * allow only specified number of encoders on a given crtc
  2411. */
  2412. SDE_ERROR("VM switch failed; idle-pc:%d max:%d encoder_cnt:%d\n",
  2413. idle_pc_state, TRUSTED_VM_MAX_ENCODER_PER_CRTC, crtc_encoder_cnt);
  2414. return -EINVAL;
  2415. }
  2416. if ((vm_req == VM_REQ_ACQUIRE) && !vm_owns_hw) {
  2417. rc = vm_ops->vm_acquire(sde_kms);
  2418. if (rc) {
  2419. SDE_ERROR("VM acquire failed; hw_owner:%d, rc:%d\n", vm_owns_hw, rc);
  2420. return rc;
  2421. }
  2422. if (vm_ops->vm_resource_init)
  2423. rc = vm_ops->vm_resource_init(sde_kms, state);
  2424. }
  2425. return rc;
  2426. }
  2427. static int sde_kms_check_vm_request(struct msm_kms *kms,
  2428. struct drm_atomic_state *state)
  2429. {
  2430. struct sde_kms *sde_kms;
  2431. struct drm_crtc *crtc;
  2432. struct drm_crtc_state *new_cstate, *old_cstate;
  2433. struct sde_vm_ops *vm_ops;
  2434. enum sde_crtc_vm_req old_vm_req = VM_REQ_NONE, new_vm_req = VM_REQ_NONE;
  2435. int i, rc = 0;
  2436. bool vm_req_active = false, prev_vm_req = false;
  2437. bool vm_owns_hw;
  2438. if (!kms || !state)
  2439. return -EINVAL;
  2440. sde_kms = to_sde_kms(kms);
  2441. vm_ops = sde_vm_get_ops(sde_kms);
  2442. if (!vm_ops)
  2443. return 0;
  2444. if (!vm_ops->vm_request_valid || !vm_ops->vm_owns_hw || !vm_ops->vm_acquire)
  2445. return -EINVAL;
  2446. drm_for_each_crtc(crtc, state->dev) {
  2447. if (crtc->state && (sde_crtc_get_property(to_sde_crtc_state(crtc->state),
  2448. CRTC_PROP_VM_REQ_STATE) == VM_REQ_RELEASE)) {
  2449. prev_vm_req = true;
  2450. break;
  2451. }
  2452. }
  2453. /* check for an active vm request */
  2454. for_each_oldnew_crtc_in_state(state, crtc, old_cstate, new_cstate, i) {
  2455. struct sde_crtc_state *old_state = NULL, *new_state = NULL;
  2456. if (!new_cstate->active && !old_cstate->active)
  2457. continue;
  2458. new_state = to_sde_crtc_state(new_cstate);
  2459. new_vm_req = sde_crtc_get_property(new_state, CRTC_PROP_VM_REQ_STATE);
  2460. old_state = to_sde_crtc_state(old_cstate);
  2461. old_vm_req = sde_crtc_get_property(old_state, CRTC_PROP_VM_REQ_STATE);
  2462. /*
  2463. * VM request should be validated in the following usecases
  2464. * - There is a vm request(other than VM_REQ_NONE) on current/prev crtc state.
  2465. * - Previously, vm transition has taken place on one of the crtc's.
  2466. */
  2467. if (old_vm_req || new_vm_req || prev_vm_req) {
  2468. if (!vm_req_active) {
  2469. sde_vm_lock(sde_kms);
  2470. vm_owns_hw = sde_vm_owns_hw(sde_kms);
  2471. }
  2472. rc = vm_ops->vm_request_valid(sde_kms, old_vm_req, new_vm_req);
  2473. if (rc) {
  2474. SDE_ERROR(
  2475. "VM transition check failed; o_state:%d, n_state:%d, hw_owner:%d, rc:%d\n",
  2476. old_vm_req, new_vm_req, vm_owns_hw, rc);
  2477. sde_vm_unlock(sde_kms);
  2478. vm_req_active = false;
  2479. break;
  2480. } else if (old_vm_req == VM_REQ_ACQUIRE && new_vm_req == VM_REQ_NONE) {
  2481. SDE_DEBUG("VM transition valid; ignore further checks\n");
  2482. if (!vm_req_active)
  2483. sde_vm_unlock(sde_kms);
  2484. } else {
  2485. vm_req_active = true;
  2486. }
  2487. }
  2488. }
  2489. /* validate active requests and perform acquire if necessary */
  2490. if (vm_req_active) {
  2491. rc = _sde_kms_validate_vm_request(state, sde_kms, new_vm_req, vm_owns_hw);
  2492. sde_vm_unlock(sde_kms);
  2493. SDE_EVT32(old_vm_req, new_vm_req, vm_req_active, vm_owns_hw, rc);
  2494. SDE_DEBUG("VM o_state:%d, n_state:%d, hw_owner:%d, rc:%d\n", old_vm_req, new_vm_req,
  2495. vm_req_active ? vm_owns_hw : -1, rc);
  2496. }
  2497. return rc;
  2498. }
  2499. static int sde_kms_check_secure_transition(struct msm_kms *kms,
  2500. struct drm_atomic_state *state)
  2501. {
  2502. struct sde_kms *sde_kms;
  2503. struct drm_device *dev;
  2504. struct drm_crtc *crtc;
  2505. struct drm_crtc *cur_crtc = NULL, *global_crtc = NULL;
  2506. struct drm_crtc_state *crtc_state;
  2507. int active_crtc_cnt = 0, global_active_crtc_cnt = 0;
  2508. bool sec_session = false, global_sec_session = false;
  2509. uint32_t fb_ns = 0, fb_sec = 0, fb_sec_dir = 0;
  2510. int i;
  2511. if (!kms || !state) {
  2512. return -EINVAL;
  2513. SDE_ERROR("invalid arguments\n");
  2514. }
  2515. sde_kms = to_sde_kms(kms);
  2516. dev = sde_kms->dev;
  2517. /* iterate state object for active secure/non-secure crtc */
  2518. for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
  2519. if (!crtc_state->active)
  2520. continue;
  2521. active_crtc_cnt++;
  2522. sde_crtc_state_find_plane_fb_modes(crtc_state, &fb_ns,
  2523. &fb_sec, &fb_sec_dir);
  2524. if (fb_sec_dir)
  2525. sec_session = true;
  2526. cur_crtc = crtc;
  2527. }
  2528. /* iterate global list for active and secure/non-secure crtc */
  2529. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  2530. if (!crtc->state->active)
  2531. continue;
  2532. global_active_crtc_cnt++;
  2533. /* update only when crtc is not the same as current crtc */
  2534. if (crtc != cur_crtc) {
  2535. fb_ns = fb_sec = fb_sec_dir = 0;
  2536. sde_crtc_find_plane_fb_modes(crtc, &fb_ns,
  2537. &fb_sec, &fb_sec_dir);
  2538. if (fb_sec_dir)
  2539. global_sec_session = true;
  2540. global_crtc = crtc;
  2541. }
  2542. }
  2543. if (!global_sec_session && !sec_session)
  2544. return 0;
  2545. /*
  2546. * - fail crtc commit, if secure-camera/secure-ui session is
  2547. * in-progress in any other display
  2548. * - fail secure-camera/secure-ui crtc commit, if any other display
  2549. * session is in-progress
  2550. */
  2551. if ((global_active_crtc_cnt > MAX_ALLOWED_CRTC_CNT_DURING_SECURE) ||
  2552. (active_crtc_cnt > MAX_ALLOWED_CRTC_CNT_DURING_SECURE)) {
  2553. SDE_ERROR(
  2554. "crtc%d secure check failed global_active:%d active:%d\n",
  2555. cur_crtc ? cur_crtc->base.id : -1,
  2556. global_active_crtc_cnt, active_crtc_cnt);
  2557. return -EPERM;
  2558. /*
  2559. * As only one crtc is allowed during secure session, the crtc
  2560. * in this commit should match with the global crtc
  2561. */
  2562. } else if (global_crtc && cur_crtc && (global_crtc != cur_crtc)) {
  2563. SDE_ERROR("crtc%d-sec%d not allowed during crtc%d-sec%d\n",
  2564. cur_crtc->base.id, sec_session,
  2565. global_crtc->base.id, global_sec_session);
  2566. return -EPERM;
  2567. }
  2568. return 0;
  2569. }
  2570. static void sde_kms_vm_res_release(struct msm_kms *kms,
  2571. struct drm_atomic_state *state)
  2572. {
  2573. struct drm_crtc *crtc;
  2574. struct drm_crtc_state *new_cstate;
  2575. struct sde_crtc_state *cstate;
  2576. struct sde_vm_ops *vm_ops;
  2577. enum sde_crtc_vm_req vm_req;
  2578. struct sde_kms *sde_kms = to_sde_kms(kms);
  2579. vm_ops = sde_vm_get_ops(sde_kms);
  2580. if (!vm_ops)
  2581. return;
  2582. crtc = sde_kms_vm_get_vm_crtc(state);
  2583. if (!crtc)
  2584. return;
  2585. new_cstate = drm_atomic_get_new_crtc_state(state, crtc);
  2586. cstate = to_sde_crtc_state(new_cstate);
  2587. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  2588. if (vm_req != VM_REQ_ACQUIRE)
  2589. return;
  2590. sde_vm_lock(sde_kms);
  2591. if (vm_ops->vm_acquire_fail_handler)
  2592. vm_ops->vm_acquire_fail_handler(sde_kms);
  2593. sde_vm_unlock(sde_kms);
  2594. }
  2595. static int sde_kms_check_cwb_concurreny(struct msm_kms *kms,
  2596. struct drm_atomic_state *state)
  2597. {
  2598. struct sde_kms *sde_kms;
  2599. struct drm_crtc *crtc;
  2600. struct drm_crtc_state *old_crtc_state, *new_crtc_state;
  2601. struct drm_encoder *encoder;
  2602. struct sde_crtc_state *cstate;
  2603. int i = 0, cnt = 0, max_cwb = 0;
  2604. if (!kms || !state) {
  2605. SDE_ERROR("invalid arguments\n");
  2606. return -EINVAL;
  2607. }
  2608. sde_kms = to_sde_kms(kms);
  2609. max_cwb = sde_kms->catalog->max_cwb;
  2610. if (!max_cwb)
  2611. return 0;
  2612. for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
  2613. cstate = to_sde_crtc_state(new_crtc_state);
  2614. drm_for_each_encoder_mask(encoder, crtc->dev, cstate->cwb_enc_mask) {
  2615. cnt++;
  2616. SDE_DEBUG("crtc%d has cwb%d attached to it\n", crtc->base.id,
  2617. encoder->base.id);
  2618. }
  2619. if (cnt > max_cwb) {
  2620. SDE_ERROR("found %d cwb in the atomic state, max supported %d\n",
  2621. cnt, max_cwb);
  2622. return -EOPNOTSUPP;
  2623. }
  2624. }
  2625. return 0;
  2626. }
  2627. static int sde_kms_atomic_check(struct msm_kms *kms,
  2628. struct drm_atomic_state *state)
  2629. {
  2630. struct sde_kms *sde_kms;
  2631. struct drm_device *dev;
  2632. int ret;
  2633. if (!kms || !state)
  2634. return -EINVAL;
  2635. sde_kms = to_sde_kms(kms);
  2636. dev = sde_kms->dev;
  2637. SDE_ATRACE_BEGIN("atomic_check");
  2638. if (sde_kms_is_suspend_blocked(dev)) {
  2639. SDE_DEBUG("suspended, skip atomic_check\n");
  2640. ret = -EBUSY;
  2641. goto end;
  2642. }
  2643. ret = sde_kms_check_vm_request(kms, state);
  2644. if (ret) {
  2645. SDE_ERROR("vm switch request checks failed\n");
  2646. goto end;
  2647. }
  2648. ret = drm_atomic_helper_check(dev, state);
  2649. if (ret)
  2650. goto vm_clean_up;
  2651. /*
  2652. * Check if any secure transition(moving CRTC between secure and
  2653. * non-secure state and vice-versa) is allowed or not. when moving
  2654. * to secure state, planes with fb_mode set to dir_translated only can
  2655. * be staged on the CRTC, and only one CRTC can be active during
  2656. * Secure state
  2657. */
  2658. ret = sde_kms_check_secure_transition(kms, state);
  2659. if (ret)
  2660. goto vm_clean_up;
  2661. ret = sde_kms_check_cwb_concurreny(kms, state);
  2662. if (ret)
  2663. goto vm_clean_up;
  2664. goto end;
  2665. vm_clean_up:
  2666. sde_kms_vm_res_release(kms, state);
  2667. end:
  2668. SDE_ATRACE_END("atomic_check");
  2669. return ret;
  2670. }
  2671. static struct msm_gem_address_space*
  2672. _sde_kms_get_address_space(struct msm_kms *kms,
  2673. unsigned int domain)
  2674. {
  2675. struct sde_kms *sde_kms;
  2676. if (!kms) {
  2677. SDE_ERROR("invalid kms\n");
  2678. return NULL;
  2679. }
  2680. sde_kms = to_sde_kms(kms);
  2681. if (!sde_kms) {
  2682. SDE_ERROR("invalid sde_kms\n");
  2683. return NULL;
  2684. }
  2685. if (domain >= MSM_SMMU_DOMAIN_MAX)
  2686. return NULL;
  2687. return (sde_kms->aspace[domain] &&
  2688. sde_kms->aspace[domain]->domain_attached) ?
  2689. sde_kms->aspace[domain] : NULL;
  2690. }
  2691. static struct device *_sde_kms_get_address_space_device(struct msm_kms *kms,
  2692. unsigned int domain)
  2693. {
  2694. struct sde_kms *sde_kms;
  2695. struct msm_gem_address_space *aspace;
  2696. if (!kms) {
  2697. SDE_ERROR("invalid kms\n");
  2698. return NULL;
  2699. }
  2700. sde_kms = to_sde_kms(kms);
  2701. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  2702. SDE_ERROR("invalid params\n");
  2703. return NULL;
  2704. }
  2705. aspace = _sde_kms_get_address_space(kms, domain);
  2706. return (aspace && aspace->domain_attached) ?
  2707. msm_gem_get_aspace_device(aspace) : NULL;
  2708. }
  2709. static void _sde_kms_post_open(struct msm_kms *kms, struct drm_file *file)
  2710. {
  2711. struct drm_device *dev = NULL;
  2712. struct sde_kms *sde_kms = NULL;
  2713. struct drm_connector *connector = NULL;
  2714. struct drm_connector_list_iter conn_iter;
  2715. struct sde_connector *sde_conn = NULL;
  2716. if (!kms) {
  2717. SDE_ERROR("invalid kms\n");
  2718. return;
  2719. }
  2720. sde_kms = to_sde_kms(kms);
  2721. dev = sde_kms->dev;
  2722. if (!dev) {
  2723. SDE_ERROR("invalid device\n");
  2724. return;
  2725. }
  2726. if (!dev->mode_config.poll_enabled)
  2727. return;
  2728. mutex_lock(&dev->mode_config.mutex);
  2729. drm_connector_list_iter_begin(dev, &conn_iter);
  2730. drm_for_each_connector_iter(connector, &conn_iter) {
  2731. /* Only handle HPD capable connectors. */
  2732. if (!(connector->polled & DRM_CONNECTOR_POLL_HPD))
  2733. continue;
  2734. sde_conn = to_sde_connector(connector);
  2735. if (sde_conn->ops.post_open)
  2736. sde_conn->ops.post_open(&sde_conn->base,
  2737. sde_conn->display);
  2738. }
  2739. drm_connector_list_iter_end(&conn_iter);
  2740. mutex_unlock(&dev->mode_config.mutex);
  2741. }
  2742. static int _sde_kms_update_planes_for_cont_splash(struct sde_kms *sde_kms,
  2743. struct sde_splash_display *splash_display,
  2744. struct drm_crtc *crtc)
  2745. {
  2746. struct msm_drm_private *priv;
  2747. struct drm_plane *plane;
  2748. struct sde_splash_mem *splash;
  2749. struct sde_splash_mem *demura;
  2750. struct sde_plane_state *pstate;
  2751. struct sde_sspp_index_info *pipe_info;
  2752. enum sde_sspp pipe_id;
  2753. bool is_virtual;
  2754. int i;
  2755. if (!sde_kms || !splash_display || !crtc) {
  2756. SDE_ERROR("invalid input args\n");
  2757. return -EINVAL;
  2758. }
  2759. priv = sde_kms->dev->dev_private;
  2760. pipe_info = &splash_display->pipe_info;
  2761. splash = splash_display->splash;
  2762. demura = splash_display->demura;
  2763. for (i = 0; i < priv->num_planes; i++) {
  2764. plane = priv->planes[i];
  2765. pipe_id = sde_plane_pipe(plane);
  2766. is_virtual = is_sde_plane_virtual(plane);
  2767. if ((is_virtual && test_bit(pipe_id, pipe_info->virt_pipes)) ||
  2768. (!is_virtual && test_bit(pipe_id, pipe_info->pipes))) {
  2769. if (splash && sde_plane_validate_src_addr(plane,
  2770. splash->splash_buf_base,
  2771. splash->splash_buf_size)) {
  2772. if (!demura || sde_plane_validate_src_addr(
  2773. plane, demura->splash_buf_base,
  2774. demura->splash_buf_size)) {
  2775. SDE_ERROR("invalid adr on pipe:%d crtc:%d\n",
  2776. pipe_id, DRMID(crtc));
  2777. continue;
  2778. }
  2779. }
  2780. plane->state->crtc = crtc;
  2781. crtc->state->plane_mask |= drm_plane_mask(plane);
  2782. pstate = to_sde_plane_state(plane->state);
  2783. pstate->cont_splash_populated = true;
  2784. SDE_DEBUG("set crtc:%d for plane:%d rect:%d\n",
  2785. DRMID(crtc), DRMID(plane), is_virtual);
  2786. }
  2787. }
  2788. return 0;
  2789. }
  2790. static int sde_kms_inform_cont_splash_res_disable(struct msm_kms *kms,
  2791. struct dsi_display *dsi_display)
  2792. {
  2793. void *display;
  2794. struct drm_encoder *encoder = NULL;
  2795. struct msm_display_info info;
  2796. struct drm_device *dev;
  2797. struct sde_kms *sde_kms;
  2798. struct drm_connector_list_iter conn_iter;
  2799. struct drm_connector *connector = NULL;
  2800. struct sde_connector *sde_conn = NULL;
  2801. int rc = 0;
  2802. sde_kms = to_sde_kms(kms);
  2803. dev = sde_kms->dev;
  2804. display = dsi_display;
  2805. if (dsi_display) {
  2806. if (dsi_display->bridge->base.encoder) {
  2807. encoder = dsi_display->bridge->base.encoder;
  2808. SDE_DEBUG("encoder name = %s\n", encoder->name);
  2809. }
  2810. memset(&info, 0x0, sizeof(info));
  2811. rc = dsi_display_get_info(NULL, &info, display);
  2812. if (rc) {
  2813. SDE_ERROR("%s: dsi get_info failed: %d\n",
  2814. __func__, rc);
  2815. encoder = NULL;
  2816. }
  2817. }
  2818. drm_connector_list_iter_begin(dev, &conn_iter);
  2819. drm_for_each_connector_iter(connector, &conn_iter) {
  2820. struct drm_encoder *c_encoder;
  2821. drm_connector_for_each_possible_encoder(connector,
  2822. c_encoder)
  2823. break;
  2824. if (!c_encoder) {
  2825. SDE_ERROR("c_encoder not found\n");
  2826. return -EINVAL;
  2827. }
  2828. /**
  2829. * Inform cont_splash is disabled to each interface/connector.
  2830. * This is currently supported for DSI interface.
  2831. */
  2832. sde_conn = to_sde_connector(connector);
  2833. if (sde_conn && sde_conn->ops.cont_splash_res_disable) {
  2834. if (!dsi_display || !encoder) {
  2835. sde_conn->ops.cont_splash_res_disable
  2836. (sde_conn->display);
  2837. } else if (c_encoder->base.id == encoder->base.id) {
  2838. /**
  2839. * This handles dual DSI
  2840. * configuration where one DSI
  2841. * interface has cont_splash
  2842. * enabled and the other doesn't.
  2843. */
  2844. sde_conn->ops.cont_splash_res_disable
  2845. (sde_conn->display);
  2846. break;
  2847. }
  2848. }
  2849. }
  2850. drm_connector_list_iter_end(&conn_iter);
  2851. return 0;
  2852. }
  2853. static int sde_kms_vm_trusted_cont_splash_res_init(struct sde_kms *sde_kms)
  2854. {
  2855. int i;
  2856. void *display;
  2857. struct dsi_display *dsi_display;
  2858. struct drm_encoder *encoder;
  2859. if (!sde_kms)
  2860. return -EINVAL;
  2861. if (!sde_in_trusted_vm(sde_kms))
  2862. return 0;
  2863. for (i = 0; i < sde_kms->dsi_display_count; i++) {
  2864. display = sde_kms->dsi_displays[i];
  2865. dsi_display = (struct dsi_display *)display;
  2866. if (!dsi_display->bridge->base.encoder) {
  2867. SDE_ERROR("no encoder on dsi display:%d", i);
  2868. return -EINVAL;
  2869. }
  2870. encoder = dsi_display->bridge->base.encoder;
  2871. encoder->possible_crtcs = 1 << i;
  2872. SDE_DEBUG(
  2873. "dsi-display:%d encoder id[%d]=%d name=%s crtcs=%x\n", i,
  2874. encoder->index, encoder->base.id,
  2875. encoder->name, encoder->possible_crtcs);
  2876. }
  2877. return 0;
  2878. }
  2879. static struct drm_display_mode *_sde_kms_get_splash_mode(
  2880. struct sde_kms *sde_kms, struct drm_connector *connector,
  2881. struct drm_atomic_state *state)
  2882. {
  2883. struct drm_display_mode *mode, *cur_mode = NULL;
  2884. struct drm_crtc *crtc;
  2885. struct drm_crtc_state *new_cstate, *old_cstate;
  2886. u32 i = 0;
  2887. if (sde_kms->splash_data.type == SDE_SPLASH_HANDOFF) {
  2888. list_for_each_entry(mode, &connector->modes, head) {
  2889. if (mode->type & DRM_MODE_TYPE_PREFERRED) {
  2890. cur_mode = mode;
  2891. break;
  2892. }
  2893. }
  2894. } else if (state) {
  2895. /* get the mode from first atomic_check phase for trusted_vm*/
  2896. for_each_oldnew_crtc_in_state(state, crtc, old_cstate,
  2897. new_cstate, i) {
  2898. if (!new_cstate->active && !old_cstate->active)
  2899. continue;
  2900. list_for_each_entry(mode, &connector->modes, head) {
  2901. if (drm_mode_equal(&new_cstate->mode, mode)) {
  2902. cur_mode = mode;
  2903. break;
  2904. }
  2905. }
  2906. }
  2907. }
  2908. return cur_mode;
  2909. }
  2910. static int sde_kms_cont_splash_config(struct msm_kms *kms,
  2911. struct drm_atomic_state *state)
  2912. {
  2913. void *display;
  2914. struct dsi_display *dsi_display;
  2915. struct msm_display_info info;
  2916. struct drm_encoder *encoder = NULL;
  2917. struct drm_crtc *crtc = NULL;
  2918. int i, rc = 0;
  2919. struct drm_display_mode *drm_mode = NULL;
  2920. struct drm_device *dev;
  2921. struct msm_drm_private *priv;
  2922. struct sde_kms *sde_kms;
  2923. struct drm_connector_list_iter conn_iter;
  2924. struct drm_connector *connector = NULL;
  2925. struct sde_connector *sde_conn = NULL;
  2926. struct sde_splash_display *splash_display;
  2927. if (!kms) {
  2928. SDE_ERROR("invalid kms\n");
  2929. return -EINVAL;
  2930. }
  2931. sde_kms = to_sde_kms(kms);
  2932. dev = sde_kms->dev;
  2933. if (!dev) {
  2934. SDE_ERROR("invalid device\n");
  2935. return -EINVAL;
  2936. }
  2937. rc = sde_kms_vm_trusted_cont_splash_res_init(sde_kms);
  2938. if (rc) {
  2939. SDE_ERROR("failed vm cont splash resource init, rc=%d", rc);
  2940. return -EINVAL;
  2941. }
  2942. if (((sde_kms->splash_data.type == SDE_SPLASH_HANDOFF)
  2943. && (!sde_kms->splash_data.num_splash_regions)) ||
  2944. !sde_kms->splash_data.num_splash_displays) {
  2945. DRM_INFO("cont_splash feature not enabled\n");
  2946. sde_kms_inform_cont_splash_res_disable(kms, NULL);
  2947. return rc;
  2948. }
  2949. DRM_INFO("cont_splash enabled in %d of %d display(s)\n",
  2950. sde_kms->splash_data.num_splash_displays,
  2951. sde_kms->dsi_display_count);
  2952. /* dsi */
  2953. for (i = 0; i < sde_kms->dsi_display_count; ++i) {
  2954. struct sde_crtc_state *cstate;
  2955. struct sde_connector_state *conn_state;
  2956. display = sde_kms->dsi_displays[i];
  2957. dsi_display = (struct dsi_display *)display;
  2958. splash_display = &sde_kms->splash_data.splash_display[i];
  2959. if (!splash_display->cont_splash_enabled) {
  2960. SDE_DEBUG("display->name = %s splash not enabled\n",
  2961. dsi_display->name);
  2962. sde_kms_inform_cont_splash_res_disable(kms,
  2963. dsi_display);
  2964. continue;
  2965. }
  2966. SDE_DEBUG("display->name = %s\n", dsi_display->name);
  2967. if (dsi_display->bridge->base.encoder) {
  2968. encoder = dsi_display->bridge->base.encoder;
  2969. SDE_DEBUG("encoder name = %s\n", encoder->name);
  2970. }
  2971. memset(&info, 0x0, sizeof(info));
  2972. rc = dsi_display_get_info(NULL, &info, display);
  2973. if (rc) {
  2974. SDE_ERROR("dsi get_info %d failed\n", i);
  2975. encoder = NULL;
  2976. continue;
  2977. }
  2978. SDE_DEBUG("info.is_connected = %s, info.display_type = %d\n",
  2979. ((info.is_connected) ? "true" : "false"),
  2980. info.display_type);
  2981. if (!encoder) {
  2982. SDE_ERROR("encoder not initialized\n");
  2983. return -EINVAL;
  2984. }
  2985. priv = sde_kms->dev->dev_private;
  2986. encoder->crtc = priv->crtcs[i];
  2987. crtc = encoder->crtc;
  2988. splash_display->encoder = encoder;
  2989. SDE_DEBUG("for dsi-display:%d crtc id[%d]:%d enc id[%d]:%d\n",
  2990. i, crtc->index, crtc->base.id, encoder->index,
  2991. encoder->base.id);
  2992. mutex_lock(&dev->mode_config.mutex);
  2993. drm_connector_list_iter_begin(dev, &conn_iter);
  2994. drm_for_each_connector_iter(connector, &conn_iter) {
  2995. struct drm_encoder *c_encoder;
  2996. drm_connector_for_each_possible_encoder(connector,
  2997. c_encoder)
  2998. break;
  2999. if (!c_encoder) {
  3000. SDE_ERROR("c_encoder not found\n");
  3001. mutex_unlock(&dev->mode_config.mutex);
  3002. return -EINVAL;
  3003. }
  3004. /**
  3005. * SDE_KMS doesn't attach more than one encoder to
  3006. * a DSI connector. So it is safe to check only with
  3007. * the first encoder entry. Revisit this logic if we
  3008. * ever have to support continuous splash for
  3009. * external displays in MST configuration.
  3010. */
  3011. if (c_encoder->base.id == encoder->base.id)
  3012. break;
  3013. }
  3014. drm_connector_list_iter_end(&conn_iter);
  3015. if (!connector) {
  3016. SDE_ERROR("connector not initialized\n");
  3017. mutex_unlock(&dev->mode_config.mutex);
  3018. return -EINVAL;
  3019. }
  3020. mutex_unlock(&dev->mode_config.mutex);
  3021. crtc->state->encoder_mask = drm_encoder_mask(encoder);
  3022. crtc->state->connector_mask = drm_connector_mask(connector);
  3023. connector->state->crtc = crtc;
  3024. drm_mode = _sde_kms_get_splash_mode(sde_kms, connector, state);
  3025. if (!drm_mode) {
  3026. SDE_ERROR("drm_mode not found; handoff_type:%d\n",
  3027. sde_kms->splash_data.type);
  3028. return -EINVAL;
  3029. }
  3030. SDE_DEBUG(
  3031. "drm_mode->name:%s, type:0x%x, flags:0x%x, handoff_type:%d\n",
  3032. drm_mode->name, drm_mode->type,
  3033. drm_mode->flags, sde_kms->splash_data.type);
  3034. /* Update CRTC drm structure */
  3035. crtc->state->active = true;
  3036. rc = drm_atomic_set_mode_for_crtc(crtc->state, drm_mode);
  3037. if (rc) {
  3038. SDE_ERROR("Failed: set mode for crtc. rc = %d\n", rc);
  3039. return rc;
  3040. }
  3041. drm_mode_copy(&crtc->state->adjusted_mode, drm_mode);
  3042. drm_mode_copy(&crtc->mode, drm_mode);
  3043. cstate = to_sde_crtc_state(crtc->state);
  3044. cstate->cont_splash_populated = true;
  3045. /* Update encoder structure */
  3046. sde_encoder_update_caps_for_cont_splash(encoder,
  3047. splash_display, true);
  3048. sde_crtc_update_cont_splash_settings(crtc);
  3049. sde_conn = to_sde_connector(connector);
  3050. if (sde_conn && sde_conn->ops.cont_splash_config)
  3051. sde_conn->ops.cont_splash_config(sde_conn->display);
  3052. conn_state = to_sde_connector_state(connector->state);
  3053. conn_state->cont_splash_populated = true;
  3054. rc = _sde_kms_update_planes_for_cont_splash(sde_kms,
  3055. splash_display, crtc);
  3056. if (rc) {
  3057. SDE_ERROR("Failed: updating plane status rc=%d\n", rc);
  3058. return rc;
  3059. }
  3060. }
  3061. return rc;
  3062. }
  3063. static bool sde_kms_check_for_splash(struct msm_kms *kms)
  3064. {
  3065. struct sde_kms *sde_kms;
  3066. if (!kms) {
  3067. SDE_ERROR("invalid kms\n");
  3068. return false;
  3069. }
  3070. sde_kms = to_sde_kms(kms);
  3071. return sde_kms->splash_data.num_splash_displays;
  3072. }
  3073. static int sde_kms_get_mixer_count(const struct msm_kms *kms,
  3074. const struct drm_display_mode *mode,
  3075. const struct msm_resource_caps_info *res, u32 *num_lm)
  3076. {
  3077. struct sde_kms *sde_kms;
  3078. s64 mode_clock_hz = 0;
  3079. s64 max_mdp_clock_hz = 0;
  3080. s64 max_lm_width = 0;
  3081. s64 hdisplay_fp = 0;
  3082. s64 htotal_fp = 0;
  3083. s64 vtotal_fp = 0;
  3084. s64 vrefresh_fp = 0;
  3085. s64 mdp_fudge_factor = 0;
  3086. s64 num_lm_fp = 0;
  3087. s64 lm_clk_fp = 0;
  3088. s64 lm_width_fp = 0;
  3089. int rc = 0;
  3090. if (!num_lm) {
  3091. SDE_ERROR("invalid num_lm pointer\n");
  3092. return -EINVAL;
  3093. }
  3094. /* default to 1 layer mixer */
  3095. *num_lm = 1;
  3096. if (!kms || !mode || !res) {
  3097. SDE_ERROR("invalid input args\n");
  3098. return -EINVAL;
  3099. }
  3100. sde_kms = to_sde_kms(kms);
  3101. max_mdp_clock_hz = drm_int2fixp(sde_kms->perf.max_core_clk_rate);
  3102. max_lm_width = drm_int2fixp(res->max_mixer_width);
  3103. hdisplay_fp = drm_int2fixp(mode->hdisplay);
  3104. htotal_fp = drm_int2fixp(mode->htotal);
  3105. vtotal_fp = drm_int2fixp(mode->vtotal);
  3106. vrefresh_fp = drm_int2fixp(drm_mode_vrefresh(mode));
  3107. mdp_fudge_factor = drm_fixp_from_fraction(105, 100);
  3108. /* mode clock = [(h * v * fps * 1.05) / (num_lm)] */
  3109. mode_clock_hz = drm_fixp_mul(htotal_fp, vtotal_fp);
  3110. mode_clock_hz = drm_fixp_mul(mode_clock_hz, vrefresh_fp);
  3111. mode_clock_hz = drm_fixp_mul(mode_clock_hz, mdp_fudge_factor);
  3112. if (mode_clock_hz > max_mdp_clock_hz ||
  3113. hdisplay_fp > max_lm_width) {
  3114. *num_lm = 0;
  3115. do {
  3116. *num_lm += 2;
  3117. num_lm_fp = drm_int2fixp(*num_lm);
  3118. lm_clk_fp = drm_fixp_div(mode_clock_hz, num_lm_fp);
  3119. lm_width_fp = drm_fixp_div(hdisplay_fp, num_lm_fp);
  3120. if (*num_lm > 4) {
  3121. rc = -EINVAL;
  3122. goto error;
  3123. }
  3124. } while (lm_clk_fp > max_mdp_clock_hz ||
  3125. lm_width_fp > max_lm_width);
  3126. mode_clock_hz = lm_clk_fp;
  3127. }
  3128. SDE_DEBUG("[%s] h=%d v=%d fps=%d lm=%d mode_clk=%u max_clk=%llu\n",
  3129. mode->name, mode->htotal, mode->vtotal, drm_mode_vrefresh(mode),
  3130. *num_lm, drm_fixp2int(mode_clock_hz),
  3131. sde_kms->perf.max_core_clk_rate);
  3132. return 0;
  3133. error:
  3134. SDE_ERROR("required mode clk exceeds max mdp clk\n");
  3135. SDE_ERROR("[%s] h=%d v=%d fps=%d lm=%d mode_clk=%u max_clk=%llu\n",
  3136. mode->name, mode->htotal, mode->vtotal, drm_mode_vrefresh(mode),
  3137. *num_lm, drm_fixp2int(mode_clock_hz),
  3138. sde_kms->perf.max_core_clk_rate);
  3139. return rc;
  3140. }
  3141. static int sde_kms_get_dsc_count(const struct msm_kms *kms,
  3142. u32 hdisplay, u32 *num_dsc)
  3143. {
  3144. struct sde_kms *sde_kms;
  3145. uint32_t max_dsc_width;
  3146. if (!num_dsc) {
  3147. SDE_ERROR("invalid num_dsc pointer\n");
  3148. return -EINVAL;
  3149. }
  3150. *num_dsc = 0;
  3151. if (!kms || !hdisplay) {
  3152. SDE_ERROR("invalid input args\n");
  3153. return -EINVAL;
  3154. }
  3155. sde_kms = to_sde_kms(kms);
  3156. max_dsc_width = sde_kms->catalog->max_dsc_width;
  3157. *num_dsc = DIV_ROUND_UP(hdisplay, max_dsc_width);
  3158. SDE_DEBUG("h=%d, max_dsc_width=%d, num_dsc=%d\n",
  3159. hdisplay, max_dsc_width,
  3160. *num_dsc);
  3161. return 0;
  3162. }
  3163. static void _sde_kms_null_commit(struct drm_device *dev,
  3164. struct drm_encoder *enc)
  3165. {
  3166. struct drm_modeset_acquire_ctx ctx;
  3167. struct drm_atomic_state *state = NULL;
  3168. int retry_cnt = 0;
  3169. int ret = 0;
  3170. drm_modeset_acquire_init(&ctx, 0);
  3171. retry:
  3172. ret = drm_modeset_lock_all_ctx(dev, &ctx);
  3173. if (ret == -EDEADLK && retry_cnt < SDE_KMS_MODESET_LOCK_MAX_TRIALS) {
  3174. drm_modeset_backoff(&ctx);
  3175. retry_cnt++;
  3176. udelay(SDE_KMS_MODESET_LOCK_TIMEOUT_US);
  3177. goto retry;
  3178. } else if (WARN_ON(ret)) {
  3179. goto end;
  3180. }
  3181. state = drm_atomic_state_alloc(dev);
  3182. if (!state) {
  3183. DRM_ERROR("failed to allocate atomic state, %d\n", ret);
  3184. goto end;
  3185. }
  3186. state->acquire_ctx = &ctx;
  3187. ret = sde_kms_set_crtc_for_conn(dev, enc, state);
  3188. if (ret)
  3189. goto end;
  3190. ret = drm_atomic_commit(state);
  3191. if (ret)
  3192. SDE_ERROR("Error %d doing the atomic commit\n", ret);
  3193. end:
  3194. if (state)
  3195. drm_atomic_state_put(state);
  3196. drm_modeset_drop_locks(&ctx);
  3197. drm_modeset_acquire_fini(&ctx);
  3198. }
  3199. void sde_kms_display_early_wakeup(struct drm_device *dev,
  3200. const int32_t connector_id)
  3201. {
  3202. struct drm_connector_list_iter conn_iter;
  3203. struct drm_connector *conn;
  3204. struct drm_encoder *drm_enc;
  3205. drm_connector_list_iter_begin(dev, &conn_iter);
  3206. drm_for_each_connector_iter(conn, &conn_iter) {
  3207. if (connector_id != DRM_MSM_WAKE_UP_ALL_DISPLAYS &&
  3208. connector_id != conn->base.id)
  3209. continue;
  3210. if (conn->state && conn->state->best_encoder)
  3211. drm_enc = conn->state->best_encoder;
  3212. else
  3213. drm_enc = conn->encoder;
  3214. if (drm_enc)
  3215. sde_encoder_early_wakeup(drm_enc);
  3216. }
  3217. drm_connector_list_iter_end(&conn_iter);
  3218. }
  3219. static void _sde_kms_pm_suspend_idle_helper(struct sde_kms *sde_kms,
  3220. struct device *dev)
  3221. {
  3222. int i, ret, crtc_id = 0;
  3223. struct drm_device *ddev = dev_get_drvdata(dev);
  3224. struct drm_connector *conn;
  3225. struct drm_connector_list_iter conn_iter;
  3226. struct msm_drm_private *priv = sde_kms->dev->dev_private;
  3227. drm_connector_list_iter_begin(ddev, &conn_iter);
  3228. drm_for_each_connector_iter(conn, &conn_iter) {
  3229. uint64_t lp;
  3230. lp = sde_connector_get_lp(conn);
  3231. if (lp != SDE_MODE_DPMS_LP2)
  3232. continue;
  3233. if (sde_encoder_in_clone_mode(conn->encoder))
  3234. continue;
  3235. crtc_id = drm_crtc_index(conn->state->crtc);
  3236. if (priv->disp_thread[crtc_id].thread)
  3237. kthread_flush_worker(
  3238. &priv->disp_thread[crtc_id].worker);
  3239. ret = sde_encoder_wait_for_event(conn->encoder,
  3240. MSM_ENC_TX_COMPLETE);
  3241. if (ret && ret != -EWOULDBLOCK) {
  3242. SDE_ERROR(
  3243. "[conn: %d] wait for commit done returned %d\n",
  3244. conn->base.id, ret);
  3245. } else if (!ret) {
  3246. if (priv->event_thread[crtc_id].thread)
  3247. kthread_flush_worker(
  3248. &priv->event_thread[crtc_id].worker);
  3249. sde_encoder_idle_request(conn->encoder);
  3250. }
  3251. }
  3252. drm_connector_list_iter_end(&conn_iter);
  3253. for (i = 0; i < priv->num_crtcs; i++) {
  3254. if (priv->disp_thread[i].thread)
  3255. kthread_flush_worker(
  3256. &priv->disp_thread[i].worker);
  3257. if (priv->event_thread[i].thread)
  3258. kthread_flush_worker(
  3259. &priv->event_thread[i].worker);
  3260. }
  3261. kthread_flush_worker(&priv->pp_event_worker);
  3262. }
  3263. struct msm_display_mode *sde_kms_get_msm_mode(struct drm_connector_state *conn_state)
  3264. {
  3265. struct sde_connector_state *sde_conn_state;
  3266. if (!conn_state)
  3267. return NULL;
  3268. sde_conn_state = to_sde_connector_state(conn_state);
  3269. return &sde_conn_state->msm_mode;
  3270. }
  3271. static int sde_kms_pm_suspend(struct device *dev)
  3272. {
  3273. struct drm_device *ddev;
  3274. struct drm_modeset_acquire_ctx ctx;
  3275. struct drm_connector *conn;
  3276. struct drm_encoder *enc;
  3277. struct drm_connector_list_iter conn_iter;
  3278. struct drm_atomic_state *state = NULL;
  3279. struct sde_kms *sde_kms;
  3280. int ret = 0, num_crtcs = 0;
  3281. if (!dev)
  3282. return -EINVAL;
  3283. ddev = dev_get_drvdata(dev);
  3284. if (!ddev || !ddev_to_msm_kms(ddev))
  3285. return -EINVAL;
  3286. sde_kms = to_sde_kms(ddev_to_msm_kms(ddev));
  3287. SDE_EVT32(0);
  3288. /* disable hot-plug polling */
  3289. drm_kms_helper_poll_disable(ddev);
  3290. /* if a display stuck in CS trigger a null commit to complete handoff */
  3291. drm_for_each_encoder(enc, ddev) {
  3292. if (sde_encoder_in_cont_splash(enc) && enc->crtc)
  3293. _sde_kms_null_commit(ddev, enc);
  3294. }
  3295. /* acquire modeset lock(s) */
  3296. drm_modeset_acquire_init(&ctx, 0);
  3297. retry:
  3298. ret = drm_modeset_lock_all_ctx(ddev, &ctx);
  3299. if (ret)
  3300. goto unlock;
  3301. /* save current state for resume */
  3302. if (sde_kms->suspend_state)
  3303. drm_atomic_state_put(sde_kms->suspend_state);
  3304. sde_kms->suspend_state = drm_atomic_helper_duplicate_state(ddev, &ctx);
  3305. if (IS_ERR_OR_NULL(sde_kms->suspend_state)) {
  3306. ret = PTR_ERR(sde_kms->suspend_state);
  3307. DRM_ERROR("failed to back up suspend state, %d\n", ret);
  3308. sde_kms->suspend_state = NULL;
  3309. goto unlock;
  3310. }
  3311. /* create atomic state to disable all CRTCs */
  3312. state = drm_atomic_state_alloc(ddev);
  3313. if (!state) {
  3314. ret = -ENOMEM;
  3315. DRM_ERROR("failed to allocate crtc disable state, %d\n", ret);
  3316. goto unlock;
  3317. }
  3318. state->acquire_ctx = &ctx;
  3319. drm_connector_list_iter_begin(ddev, &conn_iter);
  3320. drm_for_each_connector_iter(conn, &conn_iter) {
  3321. struct drm_crtc_state *crtc_state;
  3322. uint64_t lp;
  3323. if (!conn->state || !conn->state->crtc ||
  3324. conn->dpms != DRM_MODE_DPMS_ON ||
  3325. sde_encoder_in_clone_mode(conn->encoder))
  3326. continue;
  3327. lp = sde_connector_get_lp(conn);
  3328. if (lp == SDE_MODE_DPMS_LP1) {
  3329. /* transition LP1->LP2 on pm suspend */
  3330. ret = sde_connector_set_property_for_commit(conn, state,
  3331. CONNECTOR_PROP_LP, SDE_MODE_DPMS_LP2);
  3332. if (ret) {
  3333. DRM_ERROR("failed to set lp2 for conn %d\n",
  3334. conn->base.id);
  3335. drm_connector_list_iter_end(&conn_iter);
  3336. goto unlock;
  3337. }
  3338. }
  3339. if (lp != SDE_MODE_DPMS_LP2) {
  3340. /* force CRTC to be inactive */
  3341. crtc_state = drm_atomic_get_crtc_state(state,
  3342. conn->state->crtc);
  3343. if (IS_ERR_OR_NULL(crtc_state)) {
  3344. DRM_ERROR("failed to get crtc %d state\n",
  3345. conn->state->crtc->base.id);
  3346. drm_connector_list_iter_end(&conn_iter);
  3347. ret = -EINVAL;
  3348. goto unlock;
  3349. }
  3350. if (lp != SDE_MODE_DPMS_LP1)
  3351. crtc_state->active = false;
  3352. ++num_crtcs;
  3353. }
  3354. }
  3355. drm_connector_list_iter_end(&conn_iter);
  3356. /* check for nothing to do */
  3357. if (num_crtcs == 0) {
  3358. DRM_DEBUG("all crtcs are already in the off state\n");
  3359. sde_kms->suspend_block = true;
  3360. _sde_kms_pm_suspend_idle_helper(sde_kms, dev);
  3361. goto unlock;
  3362. }
  3363. /* commit the "disable all" state */
  3364. ret = drm_atomic_commit(state);
  3365. if (ret < 0) {
  3366. DRM_ERROR("failed to disable crtcs, %d\n", ret);
  3367. goto unlock;
  3368. }
  3369. sde_kms->suspend_block = true;
  3370. _sde_kms_pm_suspend_idle_helper(sde_kms, dev);
  3371. unlock:
  3372. if (state) {
  3373. drm_atomic_state_put(state);
  3374. state = NULL;
  3375. }
  3376. if (ret == -EDEADLK) {
  3377. drm_modeset_backoff(&ctx);
  3378. goto retry;
  3379. }
  3380. if ((ret || !num_crtcs) && sde_kms->suspend_state) {
  3381. drm_atomic_state_put(sde_kms->suspend_state);
  3382. sde_kms->suspend_state = NULL;
  3383. }
  3384. drm_modeset_drop_locks(&ctx);
  3385. drm_modeset_acquire_fini(&ctx);
  3386. /*
  3387. * pm runtime driver avoids multiple runtime_suspend API call by
  3388. * checking runtime_status. However, this call helps when there is a
  3389. * race condition between pm_suspend call and doze_suspend/power_off
  3390. * commit. It removes the extra vote from suspend and adds it back
  3391. * later to allow power collapse during pm_suspend call
  3392. */
  3393. pm_runtime_put_sync(dev);
  3394. pm_runtime_get_noresume(dev);
  3395. /* dump clock state before entering suspend */
  3396. if (sde_kms->pm_suspend_clk_dump)
  3397. _sde_kms_dump_clks_state(sde_kms);
  3398. return ret;
  3399. }
  3400. static int sde_kms_pm_resume(struct device *dev)
  3401. {
  3402. struct drm_device *ddev;
  3403. struct sde_kms *sde_kms;
  3404. struct drm_modeset_acquire_ctx ctx;
  3405. int ret, i;
  3406. if (!dev)
  3407. return -EINVAL;
  3408. ddev = dev_get_drvdata(dev);
  3409. if (!ddev || !ddev_to_msm_kms(ddev))
  3410. return -EINVAL;
  3411. sde_kms = to_sde_kms(ddev_to_msm_kms(ddev));
  3412. SDE_EVT32(sde_kms->suspend_state != NULL);
  3413. if (sde_kms->suspend_state)
  3414. drm_mode_config_reset(ddev);
  3415. drm_modeset_acquire_init(&ctx, 0);
  3416. retry:
  3417. ret = drm_modeset_lock_all_ctx(ddev, &ctx);
  3418. if (ret == -EDEADLK) {
  3419. drm_modeset_backoff(&ctx);
  3420. goto retry;
  3421. } else if (WARN_ON(ret)) {
  3422. goto end;
  3423. }
  3424. sde_kms->suspend_block = false;
  3425. if (sde_kms->suspend_state) {
  3426. sde_kms->suspend_state->acquire_ctx = &ctx;
  3427. for (i = 0; i < TEARDOWN_DEADLOCK_RETRY_MAX; i++) {
  3428. ret = drm_atomic_helper_commit_duplicated_state(
  3429. sde_kms->suspend_state, &ctx);
  3430. if (ret != -EDEADLK)
  3431. break;
  3432. drm_modeset_backoff(&ctx);
  3433. }
  3434. if (ret < 0)
  3435. DRM_ERROR("failed to restore state, %d\n", ret);
  3436. drm_atomic_state_put(sde_kms->suspend_state);
  3437. sde_kms->suspend_state = NULL;
  3438. }
  3439. end:
  3440. drm_modeset_drop_locks(&ctx);
  3441. drm_modeset_acquire_fini(&ctx);
  3442. /* enable hot-plug polling */
  3443. drm_kms_helper_poll_enable(ddev);
  3444. return 0;
  3445. }
  3446. static const struct msm_kms_funcs kms_funcs = {
  3447. .hw_init = sde_kms_hw_init,
  3448. .postinit = sde_kms_postinit,
  3449. .irq_preinstall = sde_irq_preinstall,
  3450. .irq_postinstall = sde_irq_postinstall,
  3451. .irq_uninstall = sde_irq_uninstall,
  3452. .irq = sde_irq,
  3453. .preclose = sde_kms_preclose,
  3454. .lastclose = sde_kms_lastclose,
  3455. .prepare_fence = sde_kms_prepare_fence,
  3456. .prepare_commit = sde_kms_prepare_commit,
  3457. .commit = sde_kms_commit,
  3458. .complete_commit = sde_kms_complete_commit,
  3459. .get_msm_mode = sde_kms_get_msm_mode,
  3460. .wait_for_crtc_commit_done = sde_kms_wait_for_commit_done,
  3461. .wait_for_tx_complete = sde_kms_wait_for_frame_transfer_complete,
  3462. .check_modified_format = sde_format_check_modified_format,
  3463. .atomic_check = sde_kms_atomic_check,
  3464. .get_format = sde_get_msm_format,
  3465. .round_pixclk = sde_kms_round_pixclk,
  3466. .display_early_wakeup = sde_kms_display_early_wakeup,
  3467. .pm_suspend = sde_kms_pm_suspend,
  3468. .pm_resume = sde_kms_pm_resume,
  3469. .destroy = sde_kms_destroy,
  3470. .debugfs_destroy = sde_kms_debugfs_destroy,
  3471. .cont_splash_config = sde_kms_cont_splash_config,
  3472. .register_events = _sde_kms_register_events,
  3473. .get_address_space = _sde_kms_get_address_space,
  3474. .get_address_space_device = _sde_kms_get_address_space_device,
  3475. .postopen = _sde_kms_post_open,
  3476. .check_for_splash = sde_kms_check_for_splash,
  3477. .get_mixer_count = sde_kms_get_mixer_count,
  3478. .get_dsc_count = sde_kms_get_dsc_count,
  3479. };
  3480. static int _sde_kms_mmu_destroy(struct sde_kms *sde_kms)
  3481. {
  3482. int i;
  3483. for (i = ARRAY_SIZE(sde_kms->aspace) - 1; i >= 0; i--) {
  3484. if (!sde_kms->aspace[i])
  3485. continue;
  3486. msm_gem_address_space_put(sde_kms->aspace[i]);
  3487. sde_kms->aspace[i] = NULL;
  3488. }
  3489. return 0;
  3490. }
  3491. static int _sde_kms_mmu_init(struct sde_kms *sde_kms)
  3492. {
  3493. struct msm_mmu *mmu;
  3494. struct resource *res;
  3495. struct platform_device *pdev;
  3496. int i, ret;
  3497. #if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 15, 0))
  3498. int early_map = 0;
  3499. #endif
  3500. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev)
  3501. return -EINVAL;
  3502. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  3503. struct msm_gem_address_space *aspace;
  3504. mmu = msm_smmu_new(sde_kms->dev->dev, i);
  3505. if (IS_ERR(mmu)) {
  3506. ret = PTR_ERR(mmu);
  3507. SDE_DEBUG("failed to init iommu id %d: rc:%d\n",
  3508. i, ret);
  3509. continue;
  3510. }
  3511. aspace = msm_gem_smmu_address_space_create(sde_kms->dev,
  3512. mmu, "sde");
  3513. if (IS_ERR(aspace)) {
  3514. ret = PTR_ERR(aspace);
  3515. mmu->funcs->destroy(mmu);
  3516. goto fail;
  3517. }
  3518. sde_kms->aspace[i] = aspace;
  3519. aspace->domain_attached = true;
  3520. /* Mapping splash memory block */
  3521. if ((i == MSM_SMMU_DOMAIN_UNSECURE) &&
  3522. sde_kms->splash_data.num_splash_regions) {
  3523. ret = _sde_kms_map_all_splash_regions(sde_kms);
  3524. if (ret) {
  3525. SDE_ERROR("failed to map ret:%d\n", ret);
  3526. goto enable_trans_fail;
  3527. }
  3528. }
  3529. if (i == MSM_SMMU_DOMAIN_UNSECURE && sde_kms->catalog->hw_fence_rev) {
  3530. pdev = to_platform_device(sde_kms->dev->dev);
  3531. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ipcc_reg");
  3532. if (!res) {
  3533. SDE_DEBUG("failed to get resource ipcc_reg, cannot map ipcc\n");
  3534. sde_kms->catalog->hw_fence_rev = 0;
  3535. } else {
  3536. sde_kms->ipcc_base_addr = res->start;
  3537. ret = _sde_kms_one2one_mem_map_ipcc_reg(sde_kms, resource_size(res),
  3538. HW_FENCE_IPCC_PROTOCOLp_CLIENTc(res->start,
  3539. sde_kms->catalog->ipcc_protocol_id,
  3540. HW_FENCE_IPCC_CLIENT_DPU));
  3541. /* if mapping fails disable hw-fences */
  3542. if (ret)
  3543. sde_kms->catalog->hw_fence_rev = 0;
  3544. }
  3545. }
  3546. /*
  3547. * disable early-map which would have been enabled during
  3548. * bootup by smmu through the device-tree hint for cont-spash
  3549. */
  3550. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  3551. ret = mmu->funcs->enable_smmu_translations(mmu);
  3552. if (ret) {
  3553. SDE_ERROR("failed to enable_s1_translations ret:%d\n", ret);
  3554. goto enable_trans_fail;
  3555. }
  3556. #else
  3557. ret = mmu->funcs->set_attribute(mmu, DOMAIN_ATTR_EARLY_MAP,
  3558. &early_map);
  3559. if (ret) {
  3560. SDE_ERROR("failed to set_att ret:%d, early_map:%d\n",
  3561. ret, early_map);
  3562. goto enable_trans_fail;
  3563. }
  3564. #endif
  3565. }
  3566. sde_kms->base.aspace = sde_kms->aspace[0];
  3567. return 0;
  3568. enable_trans_fail:
  3569. _sde_kms_unmap_all_splash_regions(sde_kms);
  3570. fail:
  3571. _sde_kms_mmu_destroy(sde_kms);
  3572. return ret;
  3573. }
  3574. static void sde_kms_init_rot_sid_hw(struct sde_kms *sde_kms)
  3575. {
  3576. if (!sde_kms || !sde_kms->hw_sid || sde_in_trusted_vm(sde_kms))
  3577. return;
  3578. sde_hw_set_rotator_sid(sde_kms->hw_sid);
  3579. }
  3580. static void sde_kms_init_hw_fences(struct sde_kms *sde_kms)
  3581. {
  3582. if (!sde_kms || !sde_kms->hw_mdp)
  3583. return;
  3584. if (sde_kms->hw_mdp->ops.setup_hw_fences)
  3585. sde_kms->hw_mdp->ops.setup_hw_fences(sde_kms->hw_mdp,
  3586. sde_kms->catalog->ipcc_protocol_id, sde_kms->ipcc_base_addr);
  3587. }
  3588. static void sde_kms_init_shared_hw(struct sde_kms *sde_kms)
  3589. {
  3590. if (!sde_kms || !sde_kms->hw_mdp || !sde_kms->catalog)
  3591. return;
  3592. if (sde_kms->hw_mdp->ops.reset_ubwc)
  3593. sde_kms->hw_mdp->ops.reset_ubwc(sde_kms->hw_mdp,
  3594. sde_kms->catalog);
  3595. }
  3596. static void _sde_kms_set_lutdma_vbif_remap(struct sde_kms *sde_kms)
  3597. {
  3598. struct sde_vbif_set_qos_params qos_params;
  3599. struct sde_mdss_cfg *catalog;
  3600. if (!sde_kms->catalog)
  3601. return;
  3602. catalog = sde_kms->catalog;
  3603. memset(&qos_params, 0, sizeof(qos_params));
  3604. qos_params.vbif_idx = catalog->dma_cfg.vbif_idx;
  3605. qos_params.xin_id = catalog->dma_cfg.xin_id;
  3606. qos_params.clk_ctrl = catalog->dma_cfg.clk_ctrl;
  3607. qos_params.client_type = VBIF_LUTDMA_CLIENT;
  3608. sde_vbif_set_qos_remap(sde_kms, &qos_params);
  3609. }
  3610. static int _sde_kms_active_override(struct sde_kms *sde_kms, bool enable)
  3611. {
  3612. struct sde_hw_uidle *uidle;
  3613. if (!sde_kms) {
  3614. SDE_ERROR("invalid kms\n");
  3615. return -EINVAL;
  3616. }
  3617. uidle = sde_kms->hw_uidle;
  3618. if (uidle && uidle->ops.active_override_enable)
  3619. uidle->ops.active_override_enable(uidle, enable);
  3620. return 0;
  3621. }
  3622. static void _sde_kms_update_pm_qos_irq_request(struct sde_kms *sde_kms)
  3623. {
  3624. struct device *cpu_dev;
  3625. int cpu = 0;
  3626. u32 cpu_irq_latency = sde_kms->catalog->perf.cpu_irq_latency;
  3627. if (cpumask_empty(&sde_kms->irq_cpu_mask)) {
  3628. SDE_DEBUG("%s: irq_cpu_mask is empty\n", __func__);
  3629. return;
  3630. }
  3631. for_each_cpu(cpu, &sde_kms->irq_cpu_mask) {
  3632. cpu_dev = get_cpu_device(cpu);
  3633. if (!cpu_dev) {
  3634. SDE_DEBUG("%s: failed to get cpu%d device\n", __func__,
  3635. cpu);
  3636. continue;
  3637. }
  3638. if (dev_pm_qos_request_active(&sde_kms->pm_qos_irq_req[cpu]))
  3639. dev_pm_qos_update_request(&sde_kms->pm_qos_irq_req[cpu],
  3640. cpu_irq_latency);
  3641. else
  3642. dev_pm_qos_add_request(cpu_dev,
  3643. &sde_kms->pm_qos_irq_req[cpu],
  3644. DEV_PM_QOS_RESUME_LATENCY,
  3645. cpu_irq_latency);
  3646. }
  3647. }
  3648. static void _sde_kms_remove_pm_qos_irq_request(struct sde_kms *sde_kms)
  3649. {
  3650. struct device *cpu_dev;
  3651. int cpu = 0;
  3652. if (cpumask_empty(&sde_kms->irq_cpu_mask)) {
  3653. SDE_DEBUG("%s: irq_cpu_mask is empty\n", __func__);
  3654. return;
  3655. }
  3656. for_each_cpu(cpu, &sde_kms->irq_cpu_mask) {
  3657. cpu_dev = get_cpu_device(cpu);
  3658. if (!cpu_dev) {
  3659. SDE_DEBUG("%s: failed to get cpu%d device\n", __func__,
  3660. cpu);
  3661. continue;
  3662. }
  3663. if (dev_pm_qos_request_active(&sde_kms->pm_qos_irq_req[cpu]))
  3664. dev_pm_qos_remove_request(
  3665. &sde_kms->pm_qos_irq_req[cpu]);
  3666. }
  3667. }
  3668. void sde_kms_cpu_vote_for_irq(struct sde_kms *sde_kms, bool enable)
  3669. {
  3670. struct msm_drm_private *priv = sde_kms->dev->dev_private;
  3671. mutex_lock(&priv->phandle.phandle_lock);
  3672. if (enable && atomic_inc_return(&sde_kms->irq_vote_count) == 1)
  3673. _sde_kms_update_pm_qos_irq_request(sde_kms);
  3674. else if (!enable && atomic_dec_return(&sde_kms->irq_vote_count) == 0)
  3675. _sde_kms_remove_pm_qos_irq_request(sde_kms);
  3676. mutex_unlock(&priv->phandle.phandle_lock);
  3677. }
  3678. static void sde_kms_irq_affinity_notify(
  3679. struct irq_affinity_notify *affinity_notify,
  3680. const cpumask_t *mask)
  3681. {
  3682. struct msm_drm_private *priv;
  3683. struct sde_kms *sde_kms = container_of(affinity_notify,
  3684. struct sde_kms, affinity_notify);
  3685. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private)
  3686. return;
  3687. priv = sde_kms->dev->dev_private;
  3688. mutex_lock(&priv->phandle.phandle_lock);
  3689. _sde_kms_remove_pm_qos_irq_request(sde_kms);
  3690. // save irq cpu mask
  3691. sde_kms->irq_cpu_mask = *mask;
  3692. // request vote with updated irq cpu mask
  3693. if (atomic_read(&sde_kms->irq_vote_count))
  3694. _sde_kms_update_pm_qos_irq_request(sde_kms);
  3695. mutex_unlock(&priv->phandle.phandle_lock);
  3696. }
  3697. static void sde_kms_irq_affinity_release(struct kref *ref) {}
  3698. static void sde_kms_handle_power_event(u32 event_type, void *usr)
  3699. {
  3700. struct sde_kms *sde_kms = usr;
  3701. struct msm_kms *msm_kms;
  3702. msm_kms = &sde_kms->base;
  3703. if (!sde_kms)
  3704. return;
  3705. SDE_DEBUG("event_type:%d\n", event_type);
  3706. SDE_EVT32_VERBOSE(event_type);
  3707. if (event_type == SDE_POWER_EVENT_POST_ENABLE) {
  3708. sde_irq_update(msm_kms, true);
  3709. sde_kms->first_kickoff = true;
  3710. /**
  3711. * Rotator sid and hw fences need to be programmed since uefi doesn't
  3712. * configure them during continuous splash
  3713. */
  3714. sde_kms_init_rot_sid_hw(sde_kms);
  3715. sde_kms_init_hw_fences(sde_kms);
  3716. if (sde_kms->splash_data.num_splash_displays ||
  3717. sde_in_trusted_vm(sde_kms))
  3718. return;
  3719. sde_vbif_init_memtypes(sde_kms);
  3720. sde_kms_init_shared_hw(sde_kms);
  3721. _sde_kms_set_lutdma_vbif_remap(sde_kms);
  3722. } else if (event_type == SDE_POWER_EVENT_PRE_DISABLE) {
  3723. sde_irq_update(msm_kms, false);
  3724. sde_kms->first_kickoff = false;
  3725. if (sde_in_trusted_vm(sde_kms))
  3726. return;
  3727. _sde_kms_active_override(sde_kms, true);
  3728. if (!is_sde_rsc_available(SDE_RSC_INDEX))
  3729. sde_vbif_axi_halt_request(sde_kms);
  3730. }
  3731. }
  3732. #define genpd_to_sde_kms(domain) container_of(domain, struct sde_kms, genpd)
  3733. static int sde_kms_pd_enable(struct generic_pm_domain *genpd)
  3734. {
  3735. struct sde_kms *sde_kms = genpd_to_sde_kms(genpd);
  3736. int rc = -EINVAL;
  3737. SDE_DEBUG("\n");
  3738. rc = pm_runtime_resume_and_get(sde_kms->dev->dev);
  3739. rc = (rc > 0) ? 0 : rc;
  3740. SDE_EVT32(rc, genpd->device_count);
  3741. return rc;
  3742. }
  3743. static int sde_kms_pd_disable(struct generic_pm_domain *genpd)
  3744. {
  3745. struct sde_kms *sde_kms = genpd_to_sde_kms(genpd);
  3746. SDE_DEBUG("\n");
  3747. pm_runtime_put_sync(sde_kms->dev->dev);
  3748. SDE_EVT32(genpd->device_count);
  3749. return 0;
  3750. }
  3751. static int _sde_kms_get_demura_plane_data(struct sde_splash_data *data)
  3752. {
  3753. int i = 0;
  3754. int ret = 0;
  3755. int count = 0;
  3756. struct device_node *parent, *node;
  3757. struct resource r;
  3758. char node_name[DEMURA_REGION_NAME_MAX];
  3759. struct sde_splash_mem *mem;
  3760. struct sde_splash_display *splash_display;
  3761. if (!data->num_splash_displays) {
  3762. SDE_DEBUG("no splash displays. skipping\n");
  3763. return 0;
  3764. }
  3765. /**
  3766. * It is expected that each active demura block will have
  3767. * its own memory region defined.
  3768. */
  3769. parent = of_find_node_by_path("/reserved-memory");
  3770. for (i = 0; i < data->num_splash_displays; i++) {
  3771. splash_display = &data->splash_display[i];
  3772. snprintf(&node_name[0], DEMURA_REGION_NAME_MAX,
  3773. "demura_region_%d", i);
  3774. splash_display->demura = NULL;
  3775. node = of_find_node_by_name(parent, node_name);
  3776. if (!node) {
  3777. SDE_DEBUG("no Demura node %s! disp count: %d\n",
  3778. node_name, data->num_splash_displays);
  3779. continue;
  3780. } else if (of_address_to_resource(node, 0, &r)) {
  3781. SDE_ERROR("invalid data for:%s\n", node_name);
  3782. ret = -EINVAL;
  3783. break;
  3784. }
  3785. mem = &data->demura_mem[i];
  3786. mem->splash_buf_base = (unsigned long)r.start;
  3787. mem->splash_buf_size = (r.end - r.start) + 1;
  3788. if (!mem->splash_buf_base && !mem->splash_buf_size) {
  3789. SDE_DEBUG("dummy splash mem for disp %d. Skipping\n",
  3790. (i+1));
  3791. continue;
  3792. } else if (!mem->splash_buf_base || !mem->splash_buf_size) {
  3793. SDE_ERROR("mem for disp %d invalid: add:%lx size:%lx\n",
  3794. (i+1), mem->splash_buf_base,
  3795. mem->splash_buf_size);
  3796. continue;
  3797. }
  3798. mem->ref_cnt = 0;
  3799. splash_display->demura = mem;
  3800. count++;
  3801. SDE_DEBUG("demura mem for disp:%d add:%lx size:%x\n", (i + 1),
  3802. mem->splash_buf_base,
  3803. mem->splash_buf_size);
  3804. }
  3805. if (!ret && !count)
  3806. SDE_DEBUG("no demura regions for cont. splash found!\n");
  3807. return ret;
  3808. }
  3809. static int _sde_kms_get_splash_data(struct sde_splash_data *data)
  3810. {
  3811. int i = 0;
  3812. int ret = 0;
  3813. struct device_node *parent, *node, *node1;
  3814. struct resource r, r1;
  3815. const char *node_name = "splash_region";
  3816. struct sde_splash_mem *mem;
  3817. bool share_splash_mem = false;
  3818. int num_displays, num_regions;
  3819. struct sde_splash_display *splash_display;
  3820. if (!data)
  3821. return -EINVAL;
  3822. memset(data, 0, sizeof(*data));
  3823. parent = of_find_node_by_path("/reserved-memory");
  3824. if (!parent) {
  3825. SDE_ERROR("failed to find reserved-memory node\n");
  3826. return -EINVAL;
  3827. }
  3828. node = of_find_node_by_name(parent, node_name);
  3829. if (!node) {
  3830. SDE_DEBUG("failed to find node %s\n", node_name);
  3831. return -EINVAL;
  3832. }
  3833. node1 = of_find_node_by_name(NULL, "disp_rdump_region");
  3834. if (!node1)
  3835. SDE_DEBUG("failed to find disp ramdump memory reservation\n");
  3836. /**
  3837. * Support sharing a single splash memory for all the built in displays
  3838. * and also independent splash region per displays. Incase of
  3839. * independent splash region for each connected display, dtsi node of
  3840. * cont_splash_region should be collection of all memory regions
  3841. * Ex: <r1.start r1.end r2.start r2.end ... rn.start, rn.end>
  3842. */
  3843. num_displays = dsi_display_get_num_of_displays();
  3844. num_regions = of_property_count_u64_elems(node, "reg") / 2;
  3845. data->num_splash_displays = num_displays;
  3846. SDE_DEBUG("splash mem num_regions:%d\n", num_regions);
  3847. if (num_displays > num_regions) {
  3848. share_splash_mem = true;
  3849. pr_info(":%d displays share same splash buf\n", num_displays);
  3850. }
  3851. for (i = 0; i < num_displays; i++) {
  3852. splash_display = &data->splash_display[i];
  3853. if (!i || !share_splash_mem) {
  3854. if (of_address_to_resource(node, i, &r)) {
  3855. SDE_ERROR("invalid data for:%s\n", node_name);
  3856. return -EINVAL;
  3857. }
  3858. mem = &data->splash_mem[i];
  3859. if (!node1 || of_address_to_resource(node1, i, &r1)) {
  3860. SDE_DEBUG("failed to find ramdump memory\n");
  3861. mem->ramdump_base = 0;
  3862. mem->ramdump_size = 0;
  3863. } else {
  3864. mem->ramdump_base = (unsigned long)r1.start;
  3865. mem->ramdump_size = (r1.end - r1.start) + 1;
  3866. }
  3867. mem->splash_buf_base = (unsigned long)r.start;
  3868. mem->splash_buf_size = (r.end - r.start) + 1;
  3869. mem->ref_cnt = 0;
  3870. splash_display->splash = mem;
  3871. data->num_splash_regions++;
  3872. } else {
  3873. data->splash_display[i].splash = &data->splash_mem[0];
  3874. }
  3875. SDE_DEBUG("splash mem for disp:%d add:%lx size:%x\n", (i + 1),
  3876. splash_display->splash->splash_buf_base,
  3877. splash_display->splash->splash_buf_size);
  3878. }
  3879. data->type = SDE_SPLASH_HANDOFF;
  3880. ret = _sde_kms_get_demura_plane_data(data);
  3881. return ret;
  3882. }
  3883. static int _sde_kms_hw_init_ioremap(struct sde_kms *sde_kms,
  3884. struct platform_device *platformdev)
  3885. {
  3886. int rc = -EINVAL;
  3887. sde_kms->mmio = msm_ioremap(platformdev, "mdp_phys", "mdp_phys");
  3888. if (IS_ERR(sde_kms->mmio)) {
  3889. rc = PTR_ERR(sde_kms->mmio);
  3890. SDE_ERROR("mdp register memory map failed: %d\n", rc);
  3891. sde_kms->mmio = NULL;
  3892. goto error;
  3893. }
  3894. DRM_INFO("mapped mdp address space @%pK\n", sde_kms->mmio);
  3895. sde_kms->mmio_len = msm_iomap_size(platformdev, "mdp_phys");
  3896. rc = sde_dbg_reg_register_base(SDE_DBG_NAME, sde_kms->mmio,
  3897. sde_kms->mmio_len,
  3898. msm_get_phys_addr(platformdev, "mdp_phys"),
  3899. SDE_DBG_SDE);
  3900. if (rc)
  3901. SDE_ERROR("dbg base register kms failed: %d\n", rc);
  3902. sde_kms->vbif[VBIF_RT] = msm_ioremap(platformdev, "vbif_phys", "vbif_phys");
  3903. if (IS_ERR(sde_kms->vbif[VBIF_RT])) {
  3904. rc = PTR_ERR(sde_kms->vbif[VBIF_RT]);
  3905. SDE_ERROR("vbif register memory map failed: %d\n", rc);
  3906. sde_kms->vbif[VBIF_RT] = NULL;
  3907. goto error;
  3908. }
  3909. sde_kms->vbif_len[VBIF_RT] = msm_iomap_size(platformdev, "vbif_phys");
  3910. rc = sde_dbg_reg_register_base("vbif_rt", sde_kms->vbif[VBIF_RT],
  3911. sde_kms->vbif_len[VBIF_RT],
  3912. msm_get_phys_addr(platformdev, "vbif_phys"),
  3913. SDE_DBG_VBIF_RT);
  3914. if (rc)
  3915. SDE_ERROR("dbg base register vbif_rt failed: %d\n", rc);
  3916. sde_kms->vbif[VBIF_NRT] = msm_ioremap(platformdev, "vbif_nrt_phys", "vbif_nrt_phys");
  3917. if (IS_ERR(sde_kms->vbif[VBIF_NRT])) {
  3918. sde_kms->vbif[VBIF_NRT] = NULL;
  3919. SDE_DEBUG("VBIF NRT is not defined");
  3920. } else {
  3921. sde_kms->vbif_len[VBIF_NRT] = msm_iomap_size(platformdev, "vbif_nrt_phys");
  3922. }
  3923. sde_kms->reg_dma = msm_ioremap(platformdev, "regdma_phys", "regdma_phys");
  3924. if (IS_ERR(sde_kms->reg_dma)) {
  3925. sde_kms->reg_dma = NULL;
  3926. SDE_DEBUG("REG_DMA is not defined");
  3927. } else {
  3928. unsigned long mdp_addr = msm_get_phys_addr(platformdev, "mdp_phys");
  3929. sde_kms->reg_dma_len = msm_iomap_size(platformdev, "regdma_phys");
  3930. sde_kms->reg_dma_off = msm_get_phys_addr(platformdev, "regdma_phys") - mdp_addr;
  3931. rc = sde_dbg_reg_register_base("reg_dma", sde_kms->reg_dma,
  3932. sde_kms->reg_dma_len,
  3933. msm_get_phys_addr(platformdev, "regdma_phys"),
  3934. SDE_DBG_LUTDMA);
  3935. if (rc)
  3936. SDE_ERROR("dbg base register reg_dma failed: %d\n", rc);
  3937. }
  3938. sde_kms->sid = msm_ioremap(platformdev, "sid_phys", "sid_phys");
  3939. if (IS_ERR(sde_kms->sid)) {
  3940. SDE_DEBUG("sid register is not defined: %d\n", rc);
  3941. sde_kms->sid = NULL;
  3942. } else {
  3943. sde_kms->sid_len = msm_iomap_size(platformdev, "sid_phys");
  3944. rc = sde_dbg_reg_register_base("sid", sde_kms->sid,
  3945. sde_kms->sid_len,
  3946. msm_get_phys_addr(platformdev, "sid_phys"),
  3947. SDE_DBG_SID);
  3948. if (rc)
  3949. SDE_ERROR("dbg base register sid failed: %d\n", rc);
  3950. }
  3951. error:
  3952. return rc;
  3953. }
  3954. static int _sde_kms_hw_init_power_helper(struct drm_device *dev,
  3955. struct sde_kms *sde_kms)
  3956. {
  3957. int rc = 0;
  3958. if (of_find_property(dev->dev->of_node, "#power-domain-cells", NULL)) {
  3959. sde_kms->genpd.name = dev->unique;
  3960. sde_kms->genpd.power_off = sde_kms_pd_disable;
  3961. sde_kms->genpd.power_on = sde_kms_pd_enable;
  3962. rc = pm_genpd_init(&sde_kms->genpd, NULL, true);
  3963. if (rc < 0) {
  3964. SDE_ERROR("failed to init genpd provider %s: %d\n",
  3965. sde_kms->genpd.name, rc);
  3966. return rc;
  3967. }
  3968. rc = of_genpd_add_provider_simple(dev->dev->of_node,
  3969. &sde_kms->genpd);
  3970. if (rc < 0) {
  3971. SDE_ERROR("failed to add genpd provider %s: %d\n",
  3972. sde_kms->genpd.name, rc);
  3973. pm_genpd_remove(&sde_kms->genpd);
  3974. return rc;
  3975. }
  3976. sde_kms->genpd_init = true;
  3977. SDE_DEBUG("added genpd provider %s\n", sde_kms->genpd.name);
  3978. }
  3979. return rc;
  3980. }
  3981. static int _sde_kms_hw_init_blocks(struct sde_kms *sde_kms,
  3982. struct drm_device *dev,
  3983. struct msm_drm_private *priv)
  3984. {
  3985. struct sde_rm *rm = NULL;
  3986. int i, rc = -EINVAL;
  3987. sde_kms->catalog = sde_hw_catalog_init(dev);
  3988. if (IS_ERR_OR_NULL(sde_kms->catalog)) {
  3989. rc = PTR_ERR(sde_kms->catalog);
  3990. if (!sde_kms->catalog)
  3991. rc = -EINVAL;
  3992. SDE_ERROR("catalog init failed: %d\n", rc);
  3993. sde_kms->catalog = NULL;
  3994. goto power_error;
  3995. }
  3996. sde_kms->core_rev = sde_kms->catalog->hw_rev;
  3997. pr_info("sde hardware revision:0x%x\n", sde_kms->core_rev);
  3998. /* initialize power domain if defined */
  3999. rc = _sde_kms_hw_init_power_helper(dev, sde_kms);
  4000. if (rc) {
  4001. SDE_ERROR("_sde_kms_hw_init_power_helper failed: %d\n", rc);
  4002. goto genpd_err;
  4003. }
  4004. rc = _sde_kms_mmu_init(sde_kms);
  4005. if (rc) {
  4006. SDE_ERROR("sde_kms_mmu_init failed: %d\n", rc);
  4007. goto power_error;
  4008. }
  4009. /* Initialize reg dma block which is a singleton */
  4010. sde_kms->catalog->dma_cfg.base_off = sde_kms->reg_dma_off;
  4011. rc = sde_reg_dma_init(sde_kms->reg_dma, sde_kms->catalog,
  4012. sde_kms->dev);
  4013. if (rc) {
  4014. SDE_ERROR("failed: reg dma init failed\n");
  4015. goto power_error;
  4016. }
  4017. sde_dbg_init_dbg_buses(sde_kms->core_rev);
  4018. rm = &sde_kms->rm;
  4019. rc = sde_rm_init(rm, sde_kms->catalog, sde_kms->mmio,
  4020. sde_kms->dev);
  4021. if (rc) {
  4022. SDE_ERROR("rm init failed: %d\n", rc);
  4023. goto power_error;
  4024. }
  4025. sde_kms->rm_init = true;
  4026. sde_kms->hw_intr = sde_hw_intr_init(sde_kms->mmio, sde_kms->catalog);
  4027. if (IS_ERR_OR_NULL(sde_kms->hw_intr)) {
  4028. rc = PTR_ERR(sde_kms->hw_intr);
  4029. SDE_ERROR("hw_intr init failed: %d\n", rc);
  4030. sde_kms->hw_intr = NULL;
  4031. goto hw_intr_init_err;
  4032. }
  4033. /*
  4034. * Attempt continuous splash handoff only if reserved
  4035. * splash memory is found & release resources on any error
  4036. * in finding display hw config in splash
  4037. */
  4038. if (sde_kms->splash_data.num_splash_regions) {
  4039. struct sde_splash_display *display;
  4040. int ret, display_count =
  4041. sde_kms->splash_data.num_splash_displays;
  4042. ret = sde_rm_cont_splash_res_init(priv, &sde_kms->rm,
  4043. &sde_kms->splash_data, sde_kms->catalog);
  4044. for (i = 0; i < display_count; i++) {
  4045. display = &sde_kms->splash_data.splash_display[i];
  4046. /*
  4047. * free splash region on resource init failure and
  4048. * cont-splash disabled case
  4049. */
  4050. if (!display->cont_splash_enabled || ret)
  4051. _sde_kms_free_splash_display_data(
  4052. sde_kms, display);
  4053. }
  4054. }
  4055. sde_kms->hw_mdp = sde_rm_get_mdp(&sde_kms->rm);
  4056. if (IS_ERR_OR_NULL(sde_kms->hw_mdp)) {
  4057. rc = PTR_ERR(sde_kms->hw_mdp);
  4058. if (!sde_kms->hw_mdp)
  4059. rc = -EINVAL;
  4060. SDE_ERROR("failed to get hw_mdp: %d\n", rc);
  4061. sde_kms->hw_mdp = NULL;
  4062. goto power_error;
  4063. }
  4064. for (i = 0; i < sde_kms->catalog->vbif_count; i++) {
  4065. u32 vbif_idx = sde_kms->catalog->vbif[i].id;
  4066. sde_kms->hw_vbif[i] = sde_hw_vbif_init(vbif_idx,
  4067. sde_kms->vbif[vbif_idx], sde_kms->catalog);
  4068. if (IS_ERR_OR_NULL(sde_kms->hw_vbif[vbif_idx])) {
  4069. rc = PTR_ERR(sde_kms->hw_vbif[vbif_idx]);
  4070. if (!sde_kms->hw_vbif[vbif_idx])
  4071. rc = -EINVAL;
  4072. SDE_ERROR("failed to init vbif %d: %d\n", vbif_idx, rc);
  4073. sde_kms->hw_vbif[vbif_idx] = NULL;
  4074. goto power_error;
  4075. }
  4076. }
  4077. if (sde_kms->catalog->uidle_cfg.uidle_rev) {
  4078. sde_kms->hw_uidle = sde_hw_uidle_init(UIDLE, sde_kms->mmio,
  4079. sde_kms->mmio_len, sde_kms->catalog);
  4080. if (IS_ERR_OR_NULL(sde_kms->hw_uidle)) {
  4081. rc = PTR_ERR(sde_kms->hw_uidle);
  4082. if (!sde_kms->hw_uidle)
  4083. rc = -EINVAL;
  4084. /* uidle is optional, so do not make it a fatal error */
  4085. SDE_ERROR("failed to init uidle rc:%d\n", rc);
  4086. sde_kms->hw_uidle = NULL;
  4087. rc = 0;
  4088. }
  4089. } else {
  4090. sde_kms->hw_uidle = NULL;
  4091. }
  4092. if (sde_kms->sid) {
  4093. sde_kms->hw_sid = sde_hw_sid_init(sde_kms->sid,
  4094. sde_kms->sid_len, sde_kms->catalog);
  4095. if (IS_ERR_OR_NULL(sde_kms->hw_sid)) {
  4096. rc = PTR_ERR(sde_kms->hw_sid);
  4097. SDE_ERROR("failed to init sid %d\n", rc);
  4098. sde_kms->hw_sid = NULL;
  4099. goto power_error;
  4100. }
  4101. }
  4102. rc = sde_core_perf_init(&sde_kms->perf, dev, sde_kms->catalog,
  4103. &priv->phandle, "core_clk");
  4104. if (rc) {
  4105. SDE_ERROR("failed to init perf %d\n", rc);
  4106. goto perf_err;
  4107. }
  4108. /*
  4109. * set the disable_immediate flag when driver supports the precise vsync
  4110. * timestamp as the DRM hooks for vblank timestamp/counters would be set
  4111. * based on the feature
  4112. */
  4113. if (test_bit(SDE_FEATURE_HW_VSYNC_TS, sde_kms->catalog->features))
  4114. dev->vblank_disable_immediate = true;
  4115. /*
  4116. * _sde_kms_drm_obj_init should create the DRM related objects
  4117. * i.e. CRTCs, planes, encoders, connectors and so forth
  4118. */
  4119. rc = _sde_kms_drm_obj_init(sde_kms);
  4120. if (rc) {
  4121. SDE_ERROR("modeset init failed: %d\n", rc);
  4122. goto drm_obj_init_err;
  4123. }
  4124. return 0;
  4125. genpd_err:
  4126. drm_obj_init_err:
  4127. sde_core_perf_destroy(&sde_kms->perf);
  4128. hw_intr_init_err:
  4129. perf_err:
  4130. power_error:
  4131. return rc;
  4132. }
  4133. int _sde_kms_get_tvm_inclusion_mem(struct sde_mdss_cfg *catalog, struct list_head *mem_list)
  4134. {
  4135. struct list_head temp_head;
  4136. struct msm_io_mem_entry *io_mem;
  4137. int rc, i = 0;
  4138. INIT_LIST_HEAD(&temp_head);
  4139. for (i = 0; i < catalog->tvm_reg_count; i++) {
  4140. struct resource *res = &catalog->tvm_reg[i];
  4141. io_mem = kzalloc(sizeof(struct msm_io_mem_entry), GFP_KERNEL);
  4142. if (!io_mem) {
  4143. rc = -ENOMEM;
  4144. goto parse_fail;
  4145. }
  4146. io_mem->base = res->start;
  4147. io_mem->size = resource_size(res);
  4148. list_add(&io_mem->list, &temp_head);
  4149. }
  4150. list_splice(&temp_head, mem_list);
  4151. return 0;
  4152. parse_fail:
  4153. msm_dss_clean_io_mem(&temp_head);
  4154. return rc;
  4155. }
  4156. #ifdef CONFIG_DRM_SDE_VM
  4157. int sde_kms_get_io_resources(struct sde_kms *sde_kms, struct msm_io_res *io_res)
  4158. {
  4159. struct platform_device *pdev = to_platform_device(sde_kms->dev->dev);
  4160. int rc = 0;
  4161. rc = msm_dss_get_io_mem(pdev, &io_res->mem);
  4162. if (rc) {
  4163. SDE_ERROR("failed to get io mem for KMS, rc = %d\n", rc);
  4164. return rc;
  4165. }
  4166. rc = msm_dss_get_pmic_io_mem(pdev, &io_res->mem);
  4167. if (rc) {
  4168. SDE_ERROR("failed to get io mem for pmic, rc:%d\n", rc);
  4169. return rc;
  4170. }
  4171. rc = msm_dss_get_io_irq(pdev, &io_res->irq, GH_IRQ_LABEL_SDE);
  4172. if (rc) {
  4173. SDE_ERROR("failed to get io irq for KMS");
  4174. return rc;
  4175. }
  4176. rc = _sde_kms_get_tvm_inclusion_mem(sde_kms->catalog, &io_res->mem);
  4177. if (rc) {
  4178. SDE_ERROR("failed to get tvm inclusion mem ranges");
  4179. return rc;
  4180. }
  4181. return rc;
  4182. }
  4183. #endif
  4184. static int sde_kms_hw_init(struct msm_kms *kms)
  4185. {
  4186. struct sde_kms *sde_kms;
  4187. struct drm_device *dev;
  4188. struct msm_drm_private *priv;
  4189. struct platform_device *platformdev;
  4190. int irq_num, rc = -EINVAL;
  4191. if (!kms) {
  4192. SDE_ERROR("invalid kms\n");
  4193. goto end;
  4194. }
  4195. sde_kms = to_sde_kms(kms);
  4196. dev = sde_kms->dev;
  4197. if (!dev || !dev->dev) {
  4198. SDE_ERROR("invalid device\n");
  4199. goto end;
  4200. }
  4201. platformdev = to_platform_device(dev->dev);
  4202. priv = dev->dev_private;
  4203. if (!priv) {
  4204. SDE_ERROR("invalid private data\n");
  4205. goto end;
  4206. }
  4207. rc = _sde_kms_hw_init_ioremap(sde_kms, platformdev);
  4208. if (rc)
  4209. goto error;
  4210. rc = _sde_kms_get_splash_data(&sde_kms->splash_data);
  4211. if (rc)
  4212. SDE_DEBUG("sde splash data fetch failed: %d\n", rc);
  4213. rc = _sde_kms_hw_init_blocks(sde_kms, dev, priv);
  4214. if (rc)
  4215. goto error;
  4216. dev->mode_config.min_width = sde_kms->catalog->min_display_width;
  4217. dev->mode_config.min_height = sde_kms->catalog->min_display_height;
  4218. dev->mode_config.max_width = sde_kms->catalog->max_display_width;
  4219. dev->mode_config.max_height = sde_kms->catalog->max_display_height;
  4220. mutex_init(&sde_kms->secure_transition_lock);
  4221. atomic_set(&sde_kms->detach_sec_cb, 0);
  4222. atomic_set(&sde_kms->detach_all_cb, 0);
  4223. atomic_set(&sde_kms->irq_vote_count, 0);
  4224. /*
  4225. * Support format modifiers for compression etc.
  4226. */
  4227. dev->mode_config.allow_fb_modifiers = true;
  4228. sde_kms->affinity_notify.notify = sde_kms_irq_affinity_notify;
  4229. sde_kms->affinity_notify.release = sde_kms_irq_affinity_release;
  4230. irq_num = platform_get_irq(to_platform_device(sde_kms->dev->dev), 0);
  4231. SDE_DEBUG("Registering for notification of irq_num: %d\n", irq_num);
  4232. irq_set_affinity_notifier(irq_num, &sde_kms->affinity_notify);
  4233. if (sde_in_trusted_vm(sde_kms)) {
  4234. rc = sde_vm_trusted_init(sde_kms);
  4235. sde_dbg_set_hw_ownership_status(false);
  4236. } else {
  4237. rc = sde_vm_primary_init(sde_kms);
  4238. sde_dbg_set_hw_ownership_status(true);
  4239. }
  4240. if (rc) {
  4241. SDE_ERROR("failed to initialize VM ops, rc: %d\n", rc);
  4242. goto error;
  4243. }
  4244. return 0;
  4245. error:
  4246. _sde_kms_hw_destroy(sde_kms, platformdev);
  4247. end:
  4248. return rc;
  4249. }
  4250. struct msm_kms *sde_kms_init(struct drm_device *dev)
  4251. {
  4252. struct msm_drm_private *priv;
  4253. struct sde_kms *sde_kms;
  4254. if (!dev || !dev->dev_private) {
  4255. SDE_ERROR("drm device node invalid\n");
  4256. return ERR_PTR(-EINVAL);
  4257. }
  4258. priv = dev->dev_private;
  4259. sde_kms = kzalloc(sizeof(*sde_kms), GFP_KERNEL);
  4260. if (!sde_kms) {
  4261. SDE_ERROR("failed to allocate sde kms\n");
  4262. return ERR_PTR(-ENOMEM);
  4263. }
  4264. msm_kms_init(&sde_kms->base, &kms_funcs);
  4265. sde_kms->dev = dev;
  4266. return &sde_kms->base;
  4267. }
  4268. void sde_kms_vm_trusted_resource_deinit(struct sde_kms *sde_kms)
  4269. {
  4270. struct dsi_display *display;
  4271. struct sde_splash_display *handoff_display;
  4272. int i;
  4273. for (i = 0; i < sde_kms->dsi_display_count; i++) {
  4274. handoff_display = &sde_kms->splash_data.splash_display[i];
  4275. display = (struct dsi_display *)sde_kms->dsi_displays[i];
  4276. if (handoff_display->cont_splash_enabled)
  4277. _sde_kms_free_splash_display_data(sde_kms,
  4278. handoff_display);
  4279. dsi_display_set_active_state(display, false);
  4280. }
  4281. memset(&sde_kms->splash_data, 0, sizeof(struct sde_splash_data));
  4282. }
  4283. int sde_kms_vm_trusted_resource_init(struct sde_kms *sde_kms,
  4284. struct drm_atomic_state *state)
  4285. {
  4286. struct drm_device *dev;
  4287. struct msm_drm_private *priv;
  4288. struct sde_splash_display *handoff_display;
  4289. struct dsi_display *display;
  4290. int ret, i;
  4291. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private) {
  4292. SDE_ERROR("invalid params\n");
  4293. return -EINVAL;
  4294. }
  4295. dev = sde_kms->dev;
  4296. priv = dev->dev_private;
  4297. sde_kms->splash_data.type = SDE_VM_HANDOFF;
  4298. sde_kms->splash_data.num_splash_displays = sde_kms->dsi_display_count;
  4299. ret = sde_rm_cont_splash_res_init(priv, &sde_kms->rm,
  4300. &sde_kms->splash_data, sde_kms->catalog);
  4301. if (ret) {
  4302. SDE_ERROR("invalid cont splash init, ret:%d\n", ret);
  4303. return -EINVAL;
  4304. }
  4305. for (i = 0; i < sde_kms->dsi_display_count; i++) {
  4306. handoff_display = &sde_kms->splash_data.splash_display[i];
  4307. display = (struct dsi_display *)sde_kms->dsi_displays[i];
  4308. if (!handoff_display->cont_splash_enabled || ret)
  4309. _sde_kms_free_splash_display_data(sde_kms,
  4310. handoff_display);
  4311. else
  4312. dsi_display_set_active_state(display, true);
  4313. }
  4314. if (sde_kms->splash_data.num_splash_displays != 1) {
  4315. SDE_ERROR("no. of displays not supported:%d\n",
  4316. sde_kms->splash_data.num_splash_displays);
  4317. goto error;
  4318. }
  4319. ret = sde_kms_cont_splash_config(&sde_kms->base, state);
  4320. if (ret) {
  4321. SDE_ERROR("error in setting handoff configs\n");
  4322. goto error;
  4323. }
  4324. /**
  4325. * fill-in vote for the continuous splash hanodff path, which will be
  4326. * removed on the successful first commit.
  4327. */
  4328. ret = pm_runtime_resume_and_get(sde_kms->dev->dev);
  4329. if (ret < 0) {
  4330. SDE_ERROR("failed to enable power resource %d\n", ret);
  4331. SDE_EVT32(ret, SDE_EVTLOG_ERROR);
  4332. goto error;
  4333. }
  4334. return 0;
  4335. error:
  4336. return ret;
  4337. }
  4338. static int _sde_kms_register_events(struct msm_kms *kms,
  4339. struct drm_mode_object *obj, u32 event, bool en)
  4340. {
  4341. int ret = 0;
  4342. struct drm_crtc *crtc;
  4343. struct drm_connector *conn;
  4344. struct sde_kms *sde_kms;
  4345. if (!kms || !obj) {
  4346. SDE_ERROR("invalid argument kms %pK obj %pK\n", kms, obj);
  4347. return -EINVAL;
  4348. }
  4349. sde_kms = to_sde_kms(kms);
  4350. sde_vm_lock(sde_kms);
  4351. if (!sde_vm_owns_hw(sde_kms)) {
  4352. sde_vm_unlock(sde_kms);
  4353. SDE_DEBUG("HW is owned by other VM\n");
  4354. return -EACCES;
  4355. }
  4356. /* check vm ownership, if event registration requires HW access */
  4357. switch (obj->type) {
  4358. case DRM_MODE_OBJECT_CRTC:
  4359. crtc = obj_to_crtc(obj);
  4360. ret = sde_crtc_register_custom_event(sde_kms, crtc, event, en);
  4361. break;
  4362. case DRM_MODE_OBJECT_CONNECTOR:
  4363. conn = obj_to_connector(obj);
  4364. ret = sde_connector_register_custom_event(sde_kms, conn, event,
  4365. en);
  4366. break;
  4367. }
  4368. sde_vm_unlock(sde_kms);
  4369. return ret;
  4370. }
  4371. int sde_kms_handle_recovery(struct drm_encoder *encoder)
  4372. {
  4373. SDE_EVT32(DRMID(encoder), MSM_ENC_ACTIVE_REGION);
  4374. return sde_encoder_wait_for_event(encoder, MSM_ENC_ACTIVE_REGION);
  4375. }
  4376. void sde_kms_add_data_to_minidump_va(struct sde_kms *sde_kms)
  4377. {
  4378. struct msm_drm_private *priv;
  4379. struct sde_crtc *sde_crtc;
  4380. struct sde_crtc_state *cstate;
  4381. struct sde_connector *sde_conn;
  4382. struct sde_connector_state *conn_state;
  4383. u32 i;
  4384. priv = sde_kms->dev->dev_private;
  4385. sde_mini_dump_add_va_region("sde_kms", sizeof(*sde_kms), sde_kms);
  4386. for (i = 0; i < priv->num_crtcs; i++) {
  4387. sde_crtc = to_sde_crtc(priv->crtcs[i]);
  4388. cstate = to_sde_crtc_state(priv->crtcs[i]->state);
  4389. sde_mini_dump_add_va_region("sde_crtc", sizeof(*sde_crtc), sde_crtc);
  4390. sde_mini_dump_add_va_region("crtc_state", sizeof(*cstate), cstate);
  4391. }
  4392. for (i = 0; i < priv->num_planes; i++)
  4393. sde_plane_add_data_to_minidump_va(priv->planes[i]);
  4394. for (i = 0; i < priv->num_encoders; i++)
  4395. sde_encoder_add_data_to_minidump_va(priv->encoders[i]);
  4396. for (i = 0; i < priv->num_connectors; i++) {
  4397. sde_conn = to_sde_connector(priv->connectors[i]);
  4398. conn_state = to_sde_connector_state(priv->connectors[i]->state);
  4399. sde_mini_dump_add_va_region("sde_conn", sizeof(*sde_conn), sde_conn);
  4400. sde_mini_dump_add_va_region("conn_state", sizeof(*conn_state), conn_state);
  4401. }
  4402. }