dp_tx.c 132 KB

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  1. /*
  2. * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "dp_htt.h"
  20. #include "hal_hw_headers.h"
  21. #include "dp_tx.h"
  22. #include "dp_tx_desc.h"
  23. #include "dp_peer.h"
  24. #include "dp_types.h"
  25. #include "hal_tx.h"
  26. #include "qdf_mem.h"
  27. #include "qdf_nbuf.h"
  28. #include "qdf_net_types.h"
  29. #include <wlan_cfg.h>
  30. #include "dp_ipa.h"
  31. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  32. #include "if_meta_hdr.h"
  33. #endif
  34. #include "enet.h"
  35. #include "dp_internal.h"
  36. #ifdef FEATURE_WDS
  37. #include "dp_txrx_wds.h"
  38. #endif
  39. #ifdef ATH_SUPPORT_IQUE
  40. #include "dp_txrx_me.h"
  41. #endif
  42. #include "dp_hist.h"
  43. /* Flag to skip CCE classify when mesh or tid override enabled */
  44. #define DP_TX_SKIP_CCE_CLASSIFY \
  45. (DP_TXRX_HLOS_TID_OVERRIDE_ENABLED | DP_TX_MESH_ENABLED)
  46. /* TODO Add support in TSO */
  47. #define DP_DESC_NUM_FRAG(x) 0
  48. /* disable TQM_BYPASS */
  49. #define TQM_BYPASS_WAR 0
  50. /* invalid peer id for reinject*/
  51. #define DP_INVALID_PEER 0XFFFE
  52. /*mapping between hal encrypt type and cdp_sec_type*/
  53. #define MAX_CDP_SEC_TYPE 12
  54. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  55. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  56. HAL_TX_ENCRYPT_TYPE_WEP_128,
  57. HAL_TX_ENCRYPT_TYPE_WEP_104,
  58. HAL_TX_ENCRYPT_TYPE_WEP_40,
  59. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  60. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  61. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  62. HAL_TX_ENCRYPT_TYPE_WAPI,
  63. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  64. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  65. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  66. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  67. #ifdef QCA_TX_LIMIT_CHECK
  68. /**
  69. * dp_tx_limit_check - Check if allocated tx descriptors reached
  70. * soc max limit and pdev max limit
  71. * @vdev: DP vdev handle
  72. *
  73. * Return: true if allocated tx descriptors reached max configured value, else
  74. * false
  75. */
  76. static inline bool
  77. dp_tx_limit_check(struct dp_vdev *vdev)
  78. {
  79. struct dp_pdev *pdev = vdev->pdev;
  80. struct dp_soc *soc = pdev->soc;
  81. if (qdf_atomic_read(&soc->num_tx_outstanding) >=
  82. soc->num_tx_allowed) {
  83. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  84. "%s: queued packets are more than max tx, drop the frame",
  85. __func__);
  86. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  87. return true;
  88. }
  89. if (qdf_atomic_read(&pdev->num_tx_outstanding) >=
  90. pdev->num_tx_allowed) {
  91. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  92. "%s: queued packets are more than max tx, drop the frame",
  93. __func__);
  94. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  95. return true;
  96. }
  97. return false;
  98. }
  99. /**
  100. * dp_tx_exception_limit_check - Check if allocated tx exception descriptors
  101. * reached soc max limit
  102. * @vdev: DP vdev handle
  103. *
  104. * Return: true if allocated tx descriptors reached max configured value, else
  105. * false
  106. */
  107. static inline bool
  108. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  109. {
  110. struct dp_pdev *pdev = vdev->pdev;
  111. struct dp_soc *soc = pdev->soc;
  112. if (qdf_atomic_read(&soc->num_tx_exception) >=
  113. soc->num_msdu_exception_desc) {
  114. dp_info("exc packets are more than max drop the exc pkt");
  115. DP_STATS_INC(vdev, tx_i.dropped.exc_desc_na.num, 1);
  116. return true;
  117. }
  118. return false;
  119. }
  120. /**
  121. * dp_tx_outstanding_inc - Increment outstanding tx desc values on pdev and soc
  122. * @vdev: DP pdev handle
  123. *
  124. * Return: void
  125. */
  126. static inline void
  127. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  128. {
  129. struct dp_soc *soc = pdev->soc;
  130. qdf_atomic_inc(&pdev->num_tx_outstanding);
  131. qdf_atomic_inc(&soc->num_tx_outstanding);
  132. }
  133. /**
  134. * dp_tx_outstanding__dec - Decrement outstanding tx desc values on pdev and soc
  135. * @vdev: DP pdev handle
  136. *
  137. * Return: void
  138. */
  139. static inline void
  140. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  141. {
  142. struct dp_soc *soc = pdev->soc;
  143. qdf_atomic_dec(&pdev->num_tx_outstanding);
  144. qdf_atomic_dec(&soc->num_tx_outstanding);
  145. }
  146. #else //QCA_TX_LIMIT_CHECK
  147. static inline bool
  148. dp_tx_limit_check(struct dp_vdev *vdev)
  149. {
  150. return false;
  151. }
  152. static inline bool
  153. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  154. {
  155. return false;
  156. }
  157. static inline void
  158. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  159. {
  160. qdf_atomic_inc(&pdev->num_tx_outstanding);
  161. }
  162. static inline void
  163. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  164. {
  165. qdf_atomic_dec(&pdev->num_tx_outstanding);
  166. }
  167. #endif //QCA_TX_LIMIT_CHECK
  168. #if defined(FEATURE_TSO)
  169. /**
  170. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  171. *
  172. * @soc - core txrx main context
  173. * @seg_desc - tso segment descriptor
  174. * @num_seg_desc - tso number segment descriptor
  175. */
  176. static void dp_tx_tso_unmap_segment(
  177. struct dp_soc *soc,
  178. struct qdf_tso_seg_elem_t *seg_desc,
  179. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  180. {
  181. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  182. if (qdf_unlikely(!seg_desc)) {
  183. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  184. __func__, __LINE__);
  185. qdf_assert(0);
  186. } else if (qdf_unlikely(!num_seg_desc)) {
  187. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  188. __func__, __LINE__);
  189. qdf_assert(0);
  190. } else {
  191. bool is_last_seg;
  192. /* no tso segment left to do dma unmap */
  193. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  194. return;
  195. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  196. true : false;
  197. qdf_nbuf_unmap_tso_segment(soc->osdev,
  198. seg_desc, is_last_seg);
  199. num_seg_desc->num_seg.tso_cmn_num_seg--;
  200. }
  201. }
  202. /**
  203. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  204. * back to the freelist
  205. *
  206. * @soc - soc device handle
  207. * @tx_desc - Tx software descriptor
  208. */
  209. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  210. struct dp_tx_desc_s *tx_desc)
  211. {
  212. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  213. if (qdf_unlikely(!tx_desc->tso_desc)) {
  214. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  215. "%s %d TSO desc is NULL!",
  216. __func__, __LINE__);
  217. qdf_assert(0);
  218. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  219. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  220. "%s %d TSO num desc is NULL!",
  221. __func__, __LINE__);
  222. qdf_assert(0);
  223. } else {
  224. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  225. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  226. /* Add the tso num segment into the free list */
  227. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  228. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  229. tx_desc->tso_num_desc);
  230. tx_desc->tso_num_desc = NULL;
  231. DP_STATS_INC(tx_desc->pdev, tso_stats.tso_comp, 1);
  232. }
  233. /* Add the tso segment into the free list*/
  234. dp_tx_tso_desc_free(soc,
  235. tx_desc->pool_id, tx_desc->tso_desc);
  236. tx_desc->tso_desc = NULL;
  237. }
  238. }
  239. #else
  240. static void dp_tx_tso_unmap_segment(
  241. struct dp_soc *soc,
  242. struct qdf_tso_seg_elem_t *seg_desc,
  243. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  244. {
  245. }
  246. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  247. struct dp_tx_desc_s *tx_desc)
  248. {
  249. }
  250. #endif
  251. /**
  252. * dp_tx_desc_release() - Release Tx Descriptor
  253. * @tx_desc : Tx Descriptor
  254. * @desc_pool_id: Descriptor Pool ID
  255. *
  256. * Deallocate all resources attached to Tx descriptor and free the Tx
  257. * descriptor.
  258. *
  259. * Return:
  260. */
  261. static void
  262. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  263. {
  264. struct dp_pdev *pdev = tx_desc->pdev;
  265. struct dp_soc *soc;
  266. uint8_t comp_status = 0;
  267. qdf_assert(pdev);
  268. soc = pdev->soc;
  269. dp_tx_outstanding_dec(pdev);
  270. if (tx_desc->frm_type == dp_tx_frm_tso)
  271. dp_tx_tso_desc_release(soc, tx_desc);
  272. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  273. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  274. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  275. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  276. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  277. qdf_atomic_dec(&soc->num_tx_exception);
  278. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  279. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  280. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  281. soc->hal_soc);
  282. else
  283. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  284. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  285. "Tx Completion Release desc %d status %d outstanding %d",
  286. tx_desc->id, comp_status,
  287. qdf_atomic_read(&pdev->num_tx_outstanding));
  288. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  289. return;
  290. }
  291. /**
  292. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  293. * @vdev: DP vdev Handle
  294. * @nbuf: skb
  295. * @msdu_info: msdu_info required to create HTT metadata
  296. *
  297. * Prepares and fills HTT metadata in the frame pre-header for special frames
  298. * that should be transmitted using varying transmit parameters.
  299. * There are 2 VDEV modes that currently needs this special metadata -
  300. * 1) Mesh Mode
  301. * 2) DSRC Mode
  302. *
  303. * Return: HTT metadata size
  304. *
  305. */
  306. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  307. struct dp_tx_msdu_info_s *msdu_info)
  308. {
  309. uint32_t *meta_data = msdu_info->meta_data;
  310. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  311. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  312. uint8_t htt_desc_size;
  313. /* Size rounded of multiple of 8 bytes */
  314. uint8_t htt_desc_size_aligned;
  315. uint8_t *hdr = NULL;
  316. /*
  317. * Metadata - HTT MSDU Extension header
  318. */
  319. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  320. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  321. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  322. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  323. meta_data[0])) {
  324. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  325. htt_desc_size_aligned)) {
  326. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  327. htt_desc_size_aligned);
  328. if (!nbuf) {
  329. /*
  330. * qdf_nbuf_realloc_headroom won't do skb_clone
  331. * as skb_realloc_headroom does. so, no free is
  332. * needed here.
  333. */
  334. DP_STATS_INC(vdev,
  335. tx_i.dropped.headroom_insufficient,
  336. 1);
  337. qdf_print(" %s[%d] skb_realloc_headroom failed",
  338. __func__, __LINE__);
  339. return 0;
  340. }
  341. }
  342. /* Fill and add HTT metaheader */
  343. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  344. if (!hdr) {
  345. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  346. "Error in filling HTT metadata");
  347. return 0;
  348. }
  349. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  350. } else if (vdev->opmode == wlan_op_mode_ocb) {
  351. /* Todo - Add support for DSRC */
  352. }
  353. return htt_desc_size_aligned;
  354. }
  355. /**
  356. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  357. * @tso_seg: TSO segment to process
  358. * @ext_desc: Pointer to MSDU extension descriptor
  359. *
  360. * Return: void
  361. */
  362. #if defined(FEATURE_TSO)
  363. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  364. void *ext_desc)
  365. {
  366. uint8_t num_frag;
  367. uint32_t tso_flags;
  368. /*
  369. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  370. * tcp_flag_mask
  371. *
  372. * Checksum enable flags are set in TCL descriptor and not in Extension
  373. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  374. */
  375. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  376. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  377. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  378. tso_seg->tso_flags.ip_len);
  379. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  380. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  381. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  382. uint32_t lo = 0;
  383. uint32_t hi = 0;
  384. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  385. (tso_seg->tso_frags[num_frag].length));
  386. qdf_dmaaddr_to_32s(
  387. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  388. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  389. tso_seg->tso_frags[num_frag].length);
  390. }
  391. return;
  392. }
  393. #else
  394. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  395. void *ext_desc)
  396. {
  397. return;
  398. }
  399. #endif
  400. #if defined(FEATURE_TSO)
  401. /**
  402. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  403. * allocated and free them
  404. *
  405. * @soc: soc handle
  406. * @free_seg: list of tso segments
  407. * @msdu_info: msdu descriptor
  408. *
  409. * Return - void
  410. */
  411. static void dp_tx_free_tso_seg_list(
  412. struct dp_soc *soc,
  413. struct qdf_tso_seg_elem_t *free_seg,
  414. struct dp_tx_msdu_info_s *msdu_info)
  415. {
  416. struct qdf_tso_seg_elem_t *next_seg;
  417. while (free_seg) {
  418. next_seg = free_seg->next;
  419. dp_tx_tso_desc_free(soc,
  420. msdu_info->tx_queue.desc_pool_id,
  421. free_seg);
  422. free_seg = next_seg;
  423. }
  424. }
  425. /**
  426. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  427. * allocated and free them
  428. *
  429. * @soc: soc handle
  430. * @free_num_seg: list of tso number segments
  431. * @msdu_info: msdu descriptor
  432. * Return - void
  433. */
  434. static void dp_tx_free_tso_num_seg_list(
  435. struct dp_soc *soc,
  436. struct qdf_tso_num_seg_elem_t *free_num_seg,
  437. struct dp_tx_msdu_info_s *msdu_info)
  438. {
  439. struct qdf_tso_num_seg_elem_t *next_num_seg;
  440. while (free_num_seg) {
  441. next_num_seg = free_num_seg->next;
  442. dp_tso_num_seg_free(soc,
  443. msdu_info->tx_queue.desc_pool_id,
  444. free_num_seg);
  445. free_num_seg = next_num_seg;
  446. }
  447. }
  448. /**
  449. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  450. * do dma unmap for each segment
  451. *
  452. * @soc: soc handle
  453. * @free_seg: list of tso segments
  454. * @num_seg_desc: tso number segment descriptor
  455. *
  456. * Return - void
  457. */
  458. static void dp_tx_unmap_tso_seg_list(
  459. struct dp_soc *soc,
  460. struct qdf_tso_seg_elem_t *free_seg,
  461. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  462. {
  463. struct qdf_tso_seg_elem_t *next_seg;
  464. if (qdf_unlikely(!num_seg_desc)) {
  465. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  466. return;
  467. }
  468. while (free_seg) {
  469. next_seg = free_seg->next;
  470. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  471. free_seg = next_seg;
  472. }
  473. }
  474. #ifdef FEATURE_TSO_STATS
  475. /**
  476. * dp_tso_get_stats_idx: Retrieve the tso packet id
  477. * @pdev - pdev handle
  478. *
  479. * Return: id
  480. */
  481. static uint32_t dp_tso_get_stats_idx(struct dp_pdev *pdev)
  482. {
  483. uint32_t stats_idx;
  484. stats_idx = (((uint32_t)qdf_atomic_inc_return(&pdev->tso_idx))
  485. % CDP_MAX_TSO_PACKETS);
  486. return stats_idx;
  487. }
  488. #else
  489. static int dp_tso_get_stats_idx(struct dp_pdev *pdev)
  490. {
  491. return 0;
  492. }
  493. #endif /* FEATURE_TSO_STATS */
  494. /**
  495. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  496. * free the tso segments descriptor and
  497. * tso num segments descriptor
  498. *
  499. * @soc: soc handle
  500. * @msdu_info: msdu descriptor
  501. * @tso_seg_unmap: flag to show if dma unmap is necessary
  502. *
  503. * Return - void
  504. */
  505. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  506. struct dp_tx_msdu_info_s *msdu_info,
  507. bool tso_seg_unmap)
  508. {
  509. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  510. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  511. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  512. tso_info->tso_num_seg_list;
  513. /* do dma unmap for each segment */
  514. if (tso_seg_unmap)
  515. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  516. /* free all tso number segment descriptor though looks only have 1 */
  517. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  518. /* free all tso segment descriptor */
  519. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  520. }
  521. /**
  522. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  523. * @vdev: virtual device handle
  524. * @msdu: network buffer
  525. * @msdu_info: meta data associated with the msdu
  526. *
  527. * Return: QDF_STATUS_SUCCESS success
  528. */
  529. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  530. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  531. {
  532. struct qdf_tso_seg_elem_t *tso_seg;
  533. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  534. struct dp_soc *soc = vdev->pdev->soc;
  535. struct dp_pdev *pdev = vdev->pdev;
  536. struct qdf_tso_info_t *tso_info;
  537. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  538. tso_info = &msdu_info->u.tso_info;
  539. tso_info->curr_seg = NULL;
  540. tso_info->tso_seg_list = NULL;
  541. tso_info->num_segs = num_seg;
  542. msdu_info->frm_type = dp_tx_frm_tso;
  543. tso_info->tso_num_seg_list = NULL;
  544. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  545. while (num_seg) {
  546. tso_seg = dp_tx_tso_desc_alloc(
  547. soc, msdu_info->tx_queue.desc_pool_id);
  548. if (tso_seg) {
  549. tso_seg->next = tso_info->tso_seg_list;
  550. tso_info->tso_seg_list = tso_seg;
  551. num_seg--;
  552. } else {
  553. dp_err_rl("Failed to alloc tso seg desc");
  554. DP_STATS_INC_PKT(vdev->pdev,
  555. tso_stats.tso_no_mem_dropped, 1,
  556. qdf_nbuf_len(msdu));
  557. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  558. return QDF_STATUS_E_NOMEM;
  559. }
  560. }
  561. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  562. tso_num_seg = dp_tso_num_seg_alloc(soc,
  563. msdu_info->tx_queue.desc_pool_id);
  564. if (tso_num_seg) {
  565. tso_num_seg->next = tso_info->tso_num_seg_list;
  566. tso_info->tso_num_seg_list = tso_num_seg;
  567. } else {
  568. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  569. __func__);
  570. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  571. return QDF_STATUS_E_NOMEM;
  572. }
  573. msdu_info->num_seg =
  574. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  575. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  576. msdu_info->num_seg);
  577. if (!(msdu_info->num_seg)) {
  578. /*
  579. * Free allocated TSO seg desc and number seg desc,
  580. * do unmap for segments if dma map has done.
  581. */
  582. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  583. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  584. return QDF_STATUS_E_INVAL;
  585. }
  586. tso_info->curr_seg = tso_info->tso_seg_list;
  587. tso_info->msdu_stats_idx = dp_tso_get_stats_idx(pdev);
  588. dp_tso_packet_update(pdev, tso_info->msdu_stats_idx,
  589. msdu, msdu_info->num_seg);
  590. dp_tso_segment_stats_update(pdev, tso_info->tso_seg_list,
  591. tso_info->msdu_stats_idx);
  592. dp_stats_tso_segment_histogram_update(pdev, msdu_info->num_seg);
  593. return QDF_STATUS_SUCCESS;
  594. }
  595. #else
  596. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  597. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  598. {
  599. return QDF_STATUS_E_NOMEM;
  600. }
  601. #endif
  602. QDF_COMPILE_TIME_ASSERT(dp_tx_htt_metadata_len_check,
  603. (DP_TX_MSDU_INFO_META_DATA_DWORDS * 4 >=
  604. sizeof(struct htt_tx_msdu_desc_ext2_t)));
  605. /**
  606. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  607. * @vdev: DP Vdev handle
  608. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  609. * @desc_pool_id: Descriptor Pool ID
  610. *
  611. * Return:
  612. */
  613. static
  614. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  615. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  616. {
  617. uint8_t i;
  618. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  619. struct dp_tx_seg_info_s *seg_info;
  620. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  621. struct dp_soc *soc = vdev->pdev->soc;
  622. /* Allocate an extension descriptor */
  623. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  624. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  625. if (!msdu_ext_desc) {
  626. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  627. return NULL;
  628. }
  629. if (msdu_info->exception_fw &&
  630. qdf_unlikely(vdev->mesh_vdev)) {
  631. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  632. &msdu_info->meta_data[0],
  633. sizeof(struct htt_tx_msdu_desc_ext2_t));
  634. qdf_atomic_inc(&soc->num_tx_exception);
  635. msdu_ext_desc->flags |= DP_TX_EXT_DESC_FLAG_METADATA_VALID;
  636. }
  637. switch (msdu_info->frm_type) {
  638. case dp_tx_frm_sg:
  639. case dp_tx_frm_me:
  640. case dp_tx_frm_raw:
  641. seg_info = msdu_info->u.sg_info.curr_seg;
  642. /* Update the buffer pointers in MSDU Extension Descriptor */
  643. for (i = 0; i < seg_info->frag_cnt; i++) {
  644. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  645. seg_info->frags[i].paddr_lo,
  646. seg_info->frags[i].paddr_hi,
  647. seg_info->frags[i].len);
  648. }
  649. break;
  650. case dp_tx_frm_tso:
  651. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  652. &cached_ext_desc[0]);
  653. break;
  654. default:
  655. break;
  656. }
  657. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  658. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  659. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  660. msdu_ext_desc->vaddr);
  661. return msdu_ext_desc;
  662. }
  663. /**
  664. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  665. *
  666. * @skb: skb to be traced
  667. * @msdu_id: msdu_id of the packet
  668. * @vdev_id: vdev_id of the packet
  669. *
  670. * Return: None
  671. */
  672. #ifdef DP_DISABLE_TX_PKT_TRACE
  673. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  674. uint8_t vdev_id)
  675. {
  676. }
  677. #else
  678. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  679. uint8_t vdev_id)
  680. {
  681. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  682. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  683. DPTRACE(qdf_dp_trace_ptr(skb,
  684. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  685. QDF_TRACE_DEFAULT_PDEV_ID,
  686. qdf_nbuf_data_addr(skb),
  687. sizeof(qdf_nbuf_data(skb)),
  688. msdu_id, vdev_id));
  689. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  690. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  691. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  692. msdu_id, QDF_TX));
  693. }
  694. #endif
  695. /**
  696. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  697. * @vdev: DP vdev handle
  698. * @nbuf: skb
  699. * @desc_pool_id: Descriptor pool ID
  700. * @meta_data: Metadata to the fw
  701. * @tx_exc_metadata: Handle that holds exception path metadata
  702. * Allocate and prepare Tx descriptor with msdu information.
  703. *
  704. * Return: Pointer to Tx Descriptor on success,
  705. * NULL on failure
  706. */
  707. static
  708. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  709. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  710. struct dp_tx_msdu_info_s *msdu_info,
  711. struct cdp_tx_exception_metadata *tx_exc_metadata)
  712. {
  713. uint8_t align_pad;
  714. uint8_t is_exception = 0;
  715. uint8_t htt_hdr_size;
  716. struct dp_tx_desc_s *tx_desc;
  717. struct dp_pdev *pdev = vdev->pdev;
  718. struct dp_soc *soc = pdev->soc;
  719. if (dp_tx_limit_check(vdev))
  720. return NULL;
  721. /* Allocate software Tx descriptor */
  722. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  723. if (qdf_unlikely(!tx_desc)) {
  724. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  725. return NULL;
  726. }
  727. dp_tx_outstanding_inc(pdev);
  728. /* Initialize the SW tx descriptor */
  729. tx_desc->nbuf = nbuf;
  730. tx_desc->frm_type = dp_tx_frm_std;
  731. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  732. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  733. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  734. tx_desc->vdev_id = vdev->vdev_id;
  735. tx_desc->pdev = pdev;
  736. tx_desc->msdu_ext_desc = NULL;
  737. tx_desc->pkt_offset = 0;
  738. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  739. if (qdf_unlikely(vdev->multipass_en)) {
  740. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  741. goto failure;
  742. }
  743. /*
  744. * For special modes (vdev_type == ocb or mesh), data frames should be
  745. * transmitted using varying transmit parameters (tx spec) which include
  746. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  747. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  748. * These frames are sent as exception packets to firmware.
  749. *
  750. * HW requirement is that metadata should always point to a
  751. * 8-byte aligned address. So we add alignment pad to start of buffer.
  752. * HTT Metadata should be ensured to be multiple of 8-bytes,
  753. * to get 8-byte aligned start address along with align_pad added
  754. *
  755. * |-----------------------------|
  756. * | |
  757. * |-----------------------------| <-----Buffer Pointer Address given
  758. * | | ^ in HW descriptor (aligned)
  759. * | HTT Metadata | |
  760. * | | |
  761. * | | | Packet Offset given in descriptor
  762. * | | |
  763. * |-----------------------------| |
  764. * | Alignment Pad | v
  765. * |-----------------------------| <----- Actual buffer start address
  766. * | SKB Data | (Unaligned)
  767. * | |
  768. * | |
  769. * | |
  770. * | |
  771. * | |
  772. * |-----------------------------|
  773. */
  774. if (qdf_unlikely((msdu_info->exception_fw)) ||
  775. (vdev->opmode == wlan_op_mode_ocb) ||
  776. (tx_exc_metadata &&
  777. tx_exc_metadata->is_tx_sniffer)) {
  778. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  779. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  780. DP_STATS_INC(vdev,
  781. tx_i.dropped.headroom_insufficient, 1);
  782. goto failure;
  783. }
  784. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  785. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  786. "qdf_nbuf_push_head failed");
  787. goto failure;
  788. }
  789. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  790. msdu_info);
  791. if (htt_hdr_size == 0)
  792. goto failure;
  793. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  794. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  795. is_exception = 1;
  796. }
  797. #if !TQM_BYPASS_WAR
  798. if (is_exception || tx_exc_metadata)
  799. #endif
  800. {
  801. /* Temporary WAR due to TQM VP issues */
  802. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  803. qdf_atomic_inc(&soc->num_tx_exception);
  804. }
  805. return tx_desc;
  806. failure:
  807. dp_tx_desc_release(tx_desc, desc_pool_id);
  808. return NULL;
  809. }
  810. /**
  811. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  812. * @vdev: DP vdev handle
  813. * @nbuf: skb
  814. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  815. * @desc_pool_id : Descriptor Pool ID
  816. *
  817. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  818. * information. For frames wth fragments, allocate and prepare
  819. * an MSDU extension descriptor
  820. *
  821. * Return: Pointer to Tx Descriptor on success,
  822. * NULL on failure
  823. */
  824. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  825. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  826. uint8_t desc_pool_id)
  827. {
  828. struct dp_tx_desc_s *tx_desc;
  829. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  830. struct dp_pdev *pdev = vdev->pdev;
  831. struct dp_soc *soc = pdev->soc;
  832. if (dp_tx_limit_check(vdev))
  833. return NULL;
  834. /* Allocate software Tx descriptor */
  835. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  836. if (!tx_desc) {
  837. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  838. return NULL;
  839. }
  840. dp_tx_outstanding_inc(pdev);
  841. /* Initialize the SW tx descriptor */
  842. tx_desc->nbuf = nbuf;
  843. tx_desc->frm_type = msdu_info->frm_type;
  844. tx_desc->tx_encap_type = vdev->tx_encap_type;
  845. tx_desc->vdev_id = vdev->vdev_id;
  846. tx_desc->pdev = pdev;
  847. tx_desc->pkt_offset = 0;
  848. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  849. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  850. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  851. /* Handle scattered frames - TSO/SG/ME */
  852. /* Allocate and prepare an extension descriptor for scattered frames */
  853. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  854. if (!msdu_ext_desc) {
  855. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  856. "%s Tx Extension Descriptor Alloc Fail",
  857. __func__);
  858. goto failure;
  859. }
  860. #if TQM_BYPASS_WAR
  861. /* Temporary WAR due to TQM VP issues */
  862. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  863. qdf_atomic_inc(&soc->num_tx_exception);
  864. #endif
  865. if (qdf_unlikely(msdu_info->exception_fw))
  866. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  867. tx_desc->msdu_ext_desc = msdu_ext_desc;
  868. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  869. return tx_desc;
  870. failure:
  871. dp_tx_desc_release(tx_desc, desc_pool_id);
  872. return NULL;
  873. }
  874. /**
  875. * dp_tx_prepare_raw() - Prepare RAW packet TX
  876. * @vdev: DP vdev handle
  877. * @nbuf: buffer pointer
  878. * @seg_info: Pointer to Segment info Descriptor to be prepared
  879. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  880. * descriptor
  881. *
  882. * Return:
  883. */
  884. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  885. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  886. {
  887. qdf_nbuf_t curr_nbuf = NULL;
  888. uint16_t total_len = 0;
  889. qdf_dma_addr_t paddr;
  890. int32_t i;
  891. int32_t mapped_buf_num = 0;
  892. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  893. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  894. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  895. /* Continue only if frames are of DATA type */
  896. if (!DP_FRAME_IS_DATA(qos_wh)) {
  897. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  898. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  899. "Pkt. recd is of not data type");
  900. goto error;
  901. }
  902. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  903. if (vdev->raw_mode_war &&
  904. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  905. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  906. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  907. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  908. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  909. if (QDF_STATUS_SUCCESS !=
  910. qdf_nbuf_map_nbytes_single(vdev->osdev,
  911. curr_nbuf,
  912. QDF_DMA_TO_DEVICE,
  913. curr_nbuf->len)) {
  914. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  915. "%s dma map error ", __func__);
  916. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  917. mapped_buf_num = i;
  918. goto error;
  919. }
  920. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  921. seg_info->frags[i].paddr_lo = paddr;
  922. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  923. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  924. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  925. total_len += qdf_nbuf_len(curr_nbuf);
  926. }
  927. seg_info->frag_cnt = i;
  928. seg_info->total_len = total_len;
  929. seg_info->next = NULL;
  930. sg_info->curr_seg = seg_info;
  931. msdu_info->frm_type = dp_tx_frm_raw;
  932. msdu_info->num_seg = 1;
  933. return nbuf;
  934. error:
  935. i = 0;
  936. while (nbuf) {
  937. curr_nbuf = nbuf;
  938. if (i < mapped_buf_num) {
  939. qdf_nbuf_unmap_nbytes_single(vdev->osdev, curr_nbuf,
  940. QDF_DMA_TO_DEVICE,
  941. curr_nbuf->len);
  942. i++;
  943. }
  944. nbuf = qdf_nbuf_next(nbuf);
  945. qdf_nbuf_free(curr_nbuf);
  946. }
  947. return NULL;
  948. }
  949. /**
  950. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  951. * @soc: DP soc handle
  952. * @nbuf: Buffer pointer
  953. *
  954. * unmap the chain of nbufs that belong to this RAW frame.
  955. *
  956. * Return: None
  957. */
  958. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  959. qdf_nbuf_t nbuf)
  960. {
  961. qdf_nbuf_t cur_nbuf = nbuf;
  962. do {
  963. qdf_nbuf_unmap_nbytes_single(soc->osdev, cur_nbuf,
  964. QDF_DMA_TO_DEVICE,
  965. cur_nbuf->len);
  966. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  967. } while (cur_nbuf);
  968. }
  969. #ifdef VDEV_PEER_PROTOCOL_COUNT
  970. #define dp_vdev_peer_stats_update_protocol_cnt_tx(vdev_hdl, nbuf) \
  971. { \
  972. qdf_nbuf_t nbuf_local; \
  973. struct dp_vdev *vdev_local = vdev_hdl; \
  974. do { \
  975. if (qdf_likely(!((vdev_local)->peer_protocol_count_track))) \
  976. break; \
  977. nbuf_local = nbuf; \
  978. if (qdf_unlikely(((vdev_local)->tx_encap_type) == \
  979. htt_cmn_pkt_type_raw)) \
  980. break; \
  981. else if (qdf_unlikely(qdf_nbuf_is_nonlinear((nbuf_local)))) \
  982. break; \
  983. else if (qdf_nbuf_is_tso((nbuf_local))) \
  984. break; \
  985. dp_vdev_peer_stats_update_protocol_cnt((vdev_local), \
  986. (nbuf_local), \
  987. NULL, 1, 0); \
  988. } while (0); \
  989. }
  990. #else
  991. #define dp_vdev_peer_stats_update_protocol_cnt_tx(vdev_hdl, skb)
  992. #endif
  993. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  994. /**
  995. * dp_tx_update_stats() - Update soc level tx stats
  996. * @soc: DP soc handle
  997. * @nbuf: packet being transmitted
  998. *
  999. * Returns: none
  1000. */
  1001. static inline void dp_tx_update_stats(struct dp_soc *soc,
  1002. qdf_nbuf_t nbuf)
  1003. {
  1004. DP_STATS_INC_PKT(soc, tx.egress, 1, qdf_nbuf_len(nbuf));
  1005. }
  1006. #else
  1007. static inline void dp_tx_update_stats(struct dp_soc *soc,
  1008. qdf_nbuf_t nbuf)
  1009. {
  1010. }
  1011. #endif
  1012. /**
  1013. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  1014. * @soc: DP Soc Handle
  1015. * @vdev: DP vdev handle
  1016. * @tx_desc: Tx Descriptor Handle
  1017. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1018. * @fw_metadata: Metadata to send to Target Firmware along with frame
  1019. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  1020. * @tx_exc_metadata: Handle that holds exception path meta data
  1021. *
  1022. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  1023. * from software Tx descriptor
  1024. *
  1025. * Return: QDF_STATUS_SUCCESS: success
  1026. * QDF_STATUS_E_RESOURCES: Error return
  1027. */
  1028. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  1029. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  1030. uint16_t fw_metadata, uint8_t ring_id,
  1031. struct cdp_tx_exception_metadata
  1032. *tx_exc_metadata)
  1033. {
  1034. uint8_t type;
  1035. void *hal_tx_desc;
  1036. uint32_t *hal_tx_desc_cached;
  1037. /*
  1038. * Setting it initialization statically here to avoid
  1039. * a memset call jump with qdf_mem_set call
  1040. */
  1041. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES] = { 0 };
  1042. enum cdp_sec_type sec_type = ((tx_exc_metadata &&
  1043. tx_exc_metadata->sec_type != CDP_INVALID_SEC_TYPE) ?
  1044. tx_exc_metadata->sec_type : vdev->sec_type);
  1045. /* Return Buffer Manager ID */
  1046. uint8_t bm_id = dp_tx_get_rbm_id(soc, ring_id);
  1047. hal_ring_handle_t hal_ring_hdl = NULL;
  1048. QDF_STATUS status = QDF_STATUS_E_RESOURCES;
  1049. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id)) {
  1050. dp_err_rl("Invalid tx desc id:%d", tx_desc->id);
  1051. return QDF_STATUS_E_RESOURCES;
  1052. }
  1053. hal_tx_desc_cached = (void *) cached_desc;
  1054. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  1055. type = HAL_TX_BUF_TYPE_EXT_DESC;
  1056. tx_desc->dma_addr = tx_desc->msdu_ext_desc->paddr;
  1057. if (tx_desc->msdu_ext_desc->flags &
  1058. DP_TX_EXT_DESC_FLAG_METADATA_VALID)
  1059. tx_desc->length = HAL_TX_EXT_DESC_WITH_META_DATA;
  1060. else
  1061. tx_desc->length = HAL_TX_EXTENSION_DESC_LEN_BYTES;
  1062. } else {
  1063. tx_desc->length = qdf_nbuf_len(tx_desc->nbuf) -
  1064. tx_desc->pkt_offset;
  1065. type = HAL_TX_BUF_TYPE_BUFFER;
  1066. tx_desc->dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  1067. }
  1068. qdf_assert_always(tx_desc->dma_addr);
  1069. hal_tx_desc_set_buf_addr(soc->hal_soc, hal_tx_desc_cached,
  1070. tx_desc->dma_addr, bm_id, tx_desc->id,
  1071. type);
  1072. hal_tx_desc_set_lmac_id(soc->hal_soc, hal_tx_desc_cached,
  1073. vdev->lmac_id);
  1074. hal_tx_desc_set_search_type(soc->hal_soc, hal_tx_desc_cached,
  1075. vdev->search_type);
  1076. hal_tx_desc_set_search_index(soc->hal_soc, hal_tx_desc_cached,
  1077. vdev->bss_ast_idx);
  1078. hal_tx_desc_set_dscp_tid_table_id(soc->hal_soc, hal_tx_desc_cached,
  1079. vdev->dscp_tid_map_id);
  1080. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  1081. sec_type_map[sec_type]);
  1082. hal_tx_desc_set_cache_set_num(soc->hal_soc, hal_tx_desc_cached,
  1083. (vdev->bss_ast_hash & 0xF));
  1084. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  1085. hal_tx_desc_set_buf_length(hal_tx_desc_cached, tx_desc->length);
  1086. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  1087. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  1088. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  1089. vdev->hal_desc_addr_search_flags);
  1090. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  1091. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  1092. /* verify checksum offload configuration*/
  1093. if (vdev->csum_enabled &&
  1094. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  1095. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  1096. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  1097. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  1098. }
  1099. if (tid != HTT_TX_EXT_TID_INVALID)
  1100. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  1101. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  1102. hal_tx_desc_set_mesh_en(soc->hal_soc, hal_tx_desc_cached, 1);
  1103. if (qdf_unlikely(vdev->pdev->delay_stats_flag) ||
  1104. qdf_unlikely(wlan_cfg_is_peer_ext_stats_enabled(
  1105. soc->wlan_cfg_ctx)))
  1106. tx_desc->timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  1107. dp_verbose_debug("length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  1108. tx_desc->length, type, (uint64_t)tx_desc->dma_addr,
  1109. tx_desc->pkt_offset, tx_desc->id);
  1110. hal_ring_hdl = dp_tx_get_hal_ring_hdl(soc, ring_id);
  1111. if (qdf_unlikely(dp_tx_hal_ring_access_start(soc, hal_ring_hdl))) {
  1112. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1113. "%s %d : HAL RING Access Failed -- %pK",
  1114. __func__, __LINE__, hal_ring_hdl);
  1115. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  1116. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  1117. return status;
  1118. }
  1119. /* Sync cached descriptor with HW */
  1120. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_ring_hdl);
  1121. if (qdf_unlikely(!hal_tx_desc)) {
  1122. dp_verbose_debug("TCL ring full ring_id:%d", ring_id);
  1123. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  1124. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  1125. goto ring_access_fail;
  1126. }
  1127. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  1128. dp_vdev_peer_stats_update_protocol_cnt_tx(vdev, tx_desc->nbuf);
  1129. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  1130. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, tx_desc->length);
  1131. dp_tx_update_stats(soc, tx_desc->nbuf);
  1132. status = QDF_STATUS_SUCCESS;
  1133. ring_access_fail:
  1134. if (hif_pm_runtime_get(soc->hif_handle,
  1135. RTPM_ID_DW_TX_HW_ENQUEUE) == 0) {
  1136. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1137. hif_pm_runtime_put(soc->hif_handle,
  1138. RTPM_ID_DW_TX_HW_ENQUEUE);
  1139. } else {
  1140. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1141. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1142. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1143. }
  1144. return status;
  1145. }
  1146. /**
  1147. * dp_cce_classify() - Classify the frame based on CCE rules
  1148. * @vdev: DP vdev handle
  1149. * @nbuf: skb
  1150. *
  1151. * Classify frames based on CCE rules
  1152. * Return: bool( true if classified,
  1153. * else false)
  1154. */
  1155. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  1156. {
  1157. qdf_ether_header_t *eh = NULL;
  1158. uint16_t ether_type;
  1159. qdf_llc_t *llcHdr;
  1160. qdf_nbuf_t nbuf_clone = NULL;
  1161. qdf_dot3_qosframe_t *qos_wh = NULL;
  1162. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1163. /*
  1164. * In case of mesh packets or hlos tid override enabled,
  1165. * don't do any classification
  1166. */
  1167. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1168. & DP_TX_SKIP_CCE_CLASSIFY))
  1169. return false;
  1170. }
  1171. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1172. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1173. ether_type = eh->ether_type;
  1174. llcHdr = (qdf_llc_t *)(nbuf->data +
  1175. sizeof(qdf_ether_header_t));
  1176. } else {
  1177. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1178. /* For encrypted packets don't do any classification */
  1179. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  1180. return false;
  1181. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  1182. if (qdf_unlikely(
  1183. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  1184. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  1185. ether_type = *(uint16_t *)(nbuf->data
  1186. + QDF_IEEE80211_4ADDR_HDR_LEN
  1187. + sizeof(qdf_llc_t)
  1188. - sizeof(ether_type));
  1189. llcHdr = (qdf_llc_t *)(nbuf->data +
  1190. QDF_IEEE80211_4ADDR_HDR_LEN);
  1191. } else {
  1192. ether_type = *(uint16_t *)(nbuf->data
  1193. + QDF_IEEE80211_3ADDR_HDR_LEN
  1194. + sizeof(qdf_llc_t)
  1195. - sizeof(ether_type));
  1196. llcHdr = (qdf_llc_t *)(nbuf->data +
  1197. QDF_IEEE80211_3ADDR_HDR_LEN);
  1198. }
  1199. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  1200. && (ether_type ==
  1201. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  1202. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  1203. return true;
  1204. }
  1205. }
  1206. return false;
  1207. }
  1208. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  1209. ether_type = *(uint16_t *)(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1210. sizeof(*llcHdr));
  1211. nbuf_clone = qdf_nbuf_clone(nbuf);
  1212. if (qdf_unlikely(nbuf_clone)) {
  1213. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  1214. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1215. qdf_nbuf_pull_head(nbuf_clone,
  1216. sizeof(qdf_net_vlanhdr_t));
  1217. }
  1218. }
  1219. } else {
  1220. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1221. nbuf_clone = qdf_nbuf_clone(nbuf);
  1222. if (qdf_unlikely(nbuf_clone)) {
  1223. qdf_nbuf_pull_head(nbuf_clone,
  1224. sizeof(qdf_net_vlanhdr_t));
  1225. }
  1226. }
  1227. }
  1228. if (qdf_unlikely(nbuf_clone))
  1229. nbuf = nbuf_clone;
  1230. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  1231. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  1232. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  1233. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  1234. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  1235. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  1236. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  1237. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  1238. if (qdf_unlikely(nbuf_clone))
  1239. qdf_nbuf_free(nbuf_clone);
  1240. return true;
  1241. }
  1242. if (qdf_unlikely(nbuf_clone))
  1243. qdf_nbuf_free(nbuf_clone);
  1244. return false;
  1245. }
  1246. /**
  1247. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1248. * @vdev: DP vdev handle
  1249. * @nbuf: skb
  1250. *
  1251. * Extract the DSCP or PCP information from frame and map into TID value.
  1252. *
  1253. * Return: void
  1254. */
  1255. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1256. struct dp_tx_msdu_info_s *msdu_info)
  1257. {
  1258. uint8_t tos = 0, dscp_tid_override = 0;
  1259. uint8_t *hdr_ptr, *L3datap;
  1260. uint8_t is_mcast = 0;
  1261. qdf_ether_header_t *eh = NULL;
  1262. qdf_ethervlan_header_t *evh = NULL;
  1263. uint16_t ether_type;
  1264. qdf_llc_t *llcHdr;
  1265. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1266. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1267. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1268. eh = (qdf_ether_header_t *)nbuf->data;
  1269. hdr_ptr = (uint8_t *)(eh->ether_dhost);
  1270. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1271. } else {
  1272. qdf_dot3_qosframe_t *qos_wh =
  1273. (qdf_dot3_qosframe_t *) nbuf->data;
  1274. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1275. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1276. return;
  1277. }
  1278. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1279. ether_type = eh->ether_type;
  1280. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1281. /*
  1282. * Check if packet is dot3 or eth2 type.
  1283. */
  1284. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1285. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1286. sizeof(*llcHdr));
  1287. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1288. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1289. sizeof(*llcHdr);
  1290. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1291. + sizeof(*llcHdr) +
  1292. sizeof(qdf_net_vlanhdr_t));
  1293. } else {
  1294. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1295. sizeof(*llcHdr);
  1296. }
  1297. } else {
  1298. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1299. evh = (qdf_ethervlan_header_t *) eh;
  1300. ether_type = evh->ether_type;
  1301. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1302. }
  1303. }
  1304. /*
  1305. * Find priority from IP TOS DSCP field
  1306. */
  1307. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1308. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1309. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1310. /* Only for unicast frames */
  1311. if (!is_mcast) {
  1312. /* send it on VO queue */
  1313. msdu_info->tid = DP_VO_TID;
  1314. }
  1315. } else {
  1316. /*
  1317. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1318. * from TOS byte.
  1319. */
  1320. tos = ip->ip_tos;
  1321. dscp_tid_override = 1;
  1322. }
  1323. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1324. /* TODO
  1325. * use flowlabel
  1326. *igmpmld cases to be handled in phase 2
  1327. */
  1328. unsigned long ver_pri_flowlabel;
  1329. unsigned long pri;
  1330. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1331. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1332. DP_IPV6_PRIORITY_SHIFT;
  1333. tos = pri;
  1334. dscp_tid_override = 1;
  1335. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1336. msdu_info->tid = DP_VO_TID;
  1337. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1338. /* Only for unicast frames */
  1339. if (!is_mcast) {
  1340. /* send ucast arp on VO queue */
  1341. msdu_info->tid = DP_VO_TID;
  1342. }
  1343. }
  1344. /*
  1345. * Assign all MCAST packets to BE
  1346. */
  1347. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1348. if (is_mcast) {
  1349. tos = 0;
  1350. dscp_tid_override = 1;
  1351. }
  1352. }
  1353. if (dscp_tid_override == 1) {
  1354. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1355. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1356. }
  1357. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1358. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1359. return;
  1360. }
  1361. /**
  1362. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1363. * @vdev: DP vdev handle
  1364. * @nbuf: skb
  1365. *
  1366. * Software based TID classification is required when more than 2 DSCP-TID
  1367. * mapping tables are needed.
  1368. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1369. *
  1370. * Return: void
  1371. */
  1372. static inline void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1373. struct dp_tx_msdu_info_s *msdu_info)
  1374. {
  1375. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1376. /*
  1377. * skip_sw_tid_classification flag will set in below cases-
  1378. * 1. vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map
  1379. * 2. hlos_tid_override enabled for vdev
  1380. * 3. mesh mode enabled for vdev
  1381. */
  1382. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1383. /* Update tid in msdu_info from skb priority */
  1384. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1385. & DP_TXRX_HLOS_TID_OVERRIDE_ENABLED)) {
  1386. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1387. return;
  1388. }
  1389. return;
  1390. }
  1391. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1392. }
  1393. #ifdef FEATURE_WLAN_TDLS
  1394. /**
  1395. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1396. * @soc: datapath SOC
  1397. * @vdev: datapath vdev
  1398. * @tx_desc: TX descriptor
  1399. *
  1400. * Return: None
  1401. */
  1402. static void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1403. struct dp_vdev *vdev,
  1404. struct dp_tx_desc_s *tx_desc)
  1405. {
  1406. if (vdev) {
  1407. if (vdev->is_tdls_frame) {
  1408. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1409. vdev->is_tdls_frame = false;
  1410. }
  1411. }
  1412. }
  1413. /**
  1414. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1415. * @soc: dp_soc handle
  1416. * @tx_desc: TX descriptor
  1417. * @vdev: datapath vdev handle
  1418. *
  1419. * Return: None
  1420. */
  1421. static void dp_non_std_tx_comp_free_buff(struct dp_soc *soc,
  1422. struct dp_tx_desc_s *tx_desc)
  1423. {
  1424. struct hal_tx_completion_status ts = {0};
  1425. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1426. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1427. DP_MOD_ID_TDLS);
  1428. if (qdf_unlikely(!vdev)) {
  1429. dp_err_rl("vdev is null!");
  1430. goto error;
  1431. }
  1432. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  1433. if (vdev->tx_non_std_data_callback.func) {
  1434. qdf_nbuf_set_next(nbuf, NULL);
  1435. vdev->tx_non_std_data_callback.func(
  1436. vdev->tx_non_std_data_callback.ctxt,
  1437. nbuf, ts.status);
  1438. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1439. return;
  1440. } else {
  1441. dp_err_rl("callback func is null");
  1442. }
  1443. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1444. error:
  1445. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1446. qdf_nbuf_free(nbuf);
  1447. }
  1448. /**
  1449. * dp_tx_msdu_single_map() - do nbuf map
  1450. * @vdev: DP vdev handle
  1451. * @tx_desc: DP TX descriptor pointer
  1452. * @nbuf: skb pointer
  1453. *
  1454. * For TDLS frame, use qdf_nbuf_map_single() to align with the unmap
  1455. * operation done in other component.
  1456. *
  1457. * Return: QDF_STATUS
  1458. */
  1459. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1460. struct dp_tx_desc_s *tx_desc,
  1461. qdf_nbuf_t nbuf)
  1462. {
  1463. if (qdf_likely(!(tx_desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)))
  1464. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1465. nbuf,
  1466. QDF_DMA_TO_DEVICE,
  1467. nbuf->len);
  1468. else
  1469. return qdf_nbuf_map_single(vdev->osdev, nbuf,
  1470. QDF_DMA_TO_DEVICE);
  1471. }
  1472. #else
  1473. static inline void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1474. struct dp_vdev *vdev,
  1475. struct dp_tx_desc_s *tx_desc)
  1476. {
  1477. }
  1478. static inline void dp_non_std_tx_comp_free_buff(struct dp_soc *soc,
  1479. struct dp_tx_desc_s *tx_desc)
  1480. {
  1481. }
  1482. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1483. struct dp_tx_desc_s *tx_desc,
  1484. qdf_nbuf_t nbuf)
  1485. {
  1486. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1487. nbuf,
  1488. QDF_DMA_TO_DEVICE,
  1489. nbuf->len);
  1490. }
  1491. #endif
  1492. #ifdef MESH_MODE_SUPPORT
  1493. /**
  1494. * dp_tx_update_mesh_flags() - Update descriptor flags for mesh VAP
  1495. * @soc: datapath SOC
  1496. * @vdev: datapath vdev
  1497. * @tx_desc: TX descriptor
  1498. *
  1499. * Return: None
  1500. */
  1501. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1502. struct dp_vdev *vdev,
  1503. struct dp_tx_desc_s *tx_desc)
  1504. {
  1505. if (qdf_unlikely(vdev->mesh_vdev))
  1506. tx_desc->flags |= DP_TX_DESC_FLAG_MESH_MODE;
  1507. }
  1508. /**
  1509. * dp_mesh_tx_comp_free_buff() - Free the mesh tx packet buffer
  1510. * @soc: dp_soc handle
  1511. * @tx_desc: TX descriptor
  1512. * @vdev: datapath vdev handle
  1513. *
  1514. * Return: None
  1515. */
  1516. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1517. struct dp_tx_desc_s *tx_desc)
  1518. {
  1519. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1520. struct dp_vdev *vdev = NULL;
  1521. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  1522. qdf_nbuf_free(nbuf);
  1523. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  1524. } else {
  1525. vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1526. DP_MOD_ID_MESH);
  1527. if (vdev && vdev->osif_tx_free_ext)
  1528. vdev->osif_tx_free_ext((nbuf));
  1529. else
  1530. qdf_nbuf_free(nbuf);
  1531. if (vdev)
  1532. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  1533. }
  1534. }
  1535. #else
  1536. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1537. struct dp_vdev *vdev,
  1538. struct dp_tx_desc_s *tx_desc)
  1539. {
  1540. }
  1541. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1542. struct dp_tx_desc_s *tx_desc)
  1543. {
  1544. }
  1545. #endif
  1546. /**
  1547. * dp_tx_frame_is_drop() - checks if the packet is loopback
  1548. * @vdev: DP vdev handle
  1549. * @nbuf: skb
  1550. *
  1551. * Return: 1 if frame needs to be dropped else 0
  1552. */
  1553. int dp_tx_frame_is_drop(struct dp_vdev *vdev, uint8_t *srcmac, uint8_t *dstmac)
  1554. {
  1555. struct dp_pdev *pdev = NULL;
  1556. struct dp_ast_entry *src_ast_entry = NULL;
  1557. struct dp_ast_entry *dst_ast_entry = NULL;
  1558. struct dp_soc *soc = NULL;
  1559. qdf_assert(vdev);
  1560. pdev = vdev->pdev;
  1561. qdf_assert(pdev);
  1562. soc = pdev->soc;
  1563. dst_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1564. (soc, dstmac, vdev->pdev->pdev_id);
  1565. src_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1566. (soc, srcmac, vdev->pdev->pdev_id);
  1567. if (dst_ast_entry && src_ast_entry) {
  1568. if (dst_ast_entry->peer_id ==
  1569. src_ast_entry->peer_id)
  1570. return 1;
  1571. }
  1572. return 0;
  1573. }
  1574. /**
  1575. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1576. * @vdev: DP vdev handle
  1577. * @nbuf: skb
  1578. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1579. * @meta_data: Metadata to the fw
  1580. * @tx_q: Tx queue to be used for this Tx frame
  1581. * @peer_id: peer_id of the peer in case of NAWDS frames
  1582. * @tx_exc_metadata: Handle that holds exception path metadata
  1583. *
  1584. * Return: NULL on success,
  1585. * nbuf when it fails to send
  1586. */
  1587. qdf_nbuf_t
  1588. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1589. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1590. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1591. {
  1592. struct dp_pdev *pdev = vdev->pdev;
  1593. struct dp_soc *soc = pdev->soc;
  1594. struct dp_tx_desc_s *tx_desc;
  1595. QDF_STATUS status;
  1596. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1597. uint16_t htt_tcl_metadata = 0;
  1598. enum cdp_tx_sw_drop drop_code = TX_MAX_DROP;
  1599. uint8_t tid = msdu_info->tid;
  1600. struct cdp_tid_tx_stats *tid_stats = NULL;
  1601. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1602. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1603. msdu_info, tx_exc_metadata);
  1604. if (!tx_desc) {
  1605. dp_err_rl("Tx_desc prepare Fail vdev %pK queue %d",
  1606. vdev, tx_q->desc_pool_id);
  1607. drop_code = TX_DESC_ERR;
  1608. goto fail_return;
  1609. }
  1610. if (qdf_unlikely(soc->cce_disable)) {
  1611. if (dp_cce_classify(vdev, nbuf) == true) {
  1612. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1613. tid = DP_VO_TID;
  1614. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1615. }
  1616. }
  1617. dp_tx_update_tdls_flags(soc, vdev, tx_desc);
  1618. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1619. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1620. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1621. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1622. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1623. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1624. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1625. peer_id);
  1626. } else
  1627. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1628. if (msdu_info->exception_fw)
  1629. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1630. dp_tx_desc_update_fast_comp_flag(soc, tx_desc,
  1631. !pdev->enhanced_stats_en);
  1632. dp_tx_update_mesh_flags(soc, vdev, tx_desc);
  1633. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  1634. dp_tx_msdu_single_map(vdev, tx_desc, nbuf))) {
  1635. /* Handle failure */
  1636. dp_err("qdf_nbuf_map failed");
  1637. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  1638. drop_code = TX_DMA_MAP_ERR;
  1639. goto release_desc;
  1640. }
  1641. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1642. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  1643. htt_tcl_metadata, tx_q->ring_id, tx_exc_metadata);
  1644. if (status != QDF_STATUS_SUCCESS) {
  1645. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1646. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1647. __func__, tx_desc, tx_q->ring_id);
  1648. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  1649. QDF_DMA_TO_DEVICE,
  1650. nbuf->len);
  1651. drop_code = TX_HW_ENQUEUE;
  1652. goto release_desc;
  1653. }
  1654. return NULL;
  1655. release_desc:
  1656. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1657. fail_return:
  1658. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1659. tid_stats = &pdev->stats.tid_stats.
  1660. tid_tx_stats[tx_q->ring_id][tid];
  1661. tid_stats->swdrop_cnt[drop_code]++;
  1662. return nbuf;
  1663. }
  1664. /**
  1665. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1666. * @vdev: DP vdev handle
  1667. * @nbuf: skb
  1668. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1669. *
  1670. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1671. *
  1672. * Return: NULL on success,
  1673. * nbuf when it fails to send
  1674. */
  1675. #if QDF_LOCK_STATS
  1676. noinline
  1677. #else
  1678. #endif
  1679. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1680. struct dp_tx_msdu_info_s *msdu_info)
  1681. {
  1682. uint32_t i;
  1683. struct dp_pdev *pdev = vdev->pdev;
  1684. struct dp_soc *soc = pdev->soc;
  1685. struct dp_tx_desc_s *tx_desc;
  1686. bool is_cce_classified = false;
  1687. QDF_STATUS status;
  1688. uint16_t htt_tcl_metadata = 0;
  1689. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1690. struct cdp_tid_tx_stats *tid_stats = NULL;
  1691. if (qdf_unlikely(soc->cce_disable)) {
  1692. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1693. if (is_cce_classified) {
  1694. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1695. msdu_info->tid = DP_VO_TID;
  1696. }
  1697. }
  1698. if (msdu_info->frm_type == dp_tx_frm_me)
  1699. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1700. i = 0;
  1701. /* Print statement to track i and num_seg */
  1702. /*
  1703. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1704. * descriptors using information in msdu_info
  1705. */
  1706. while (i < msdu_info->num_seg) {
  1707. /*
  1708. * Setup Tx descriptor for an MSDU, and MSDU extension
  1709. * descriptor
  1710. */
  1711. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1712. tx_q->desc_pool_id);
  1713. if (!tx_desc) {
  1714. if (msdu_info->frm_type == dp_tx_frm_me) {
  1715. dp_tx_me_free_buf(pdev,
  1716. (void *)(msdu_info->u.sg_info
  1717. .curr_seg->frags[0].vaddr));
  1718. i++;
  1719. continue;
  1720. }
  1721. goto done;
  1722. }
  1723. if (msdu_info->frm_type == dp_tx_frm_me) {
  1724. tx_desc->me_buffer =
  1725. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1726. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1727. }
  1728. if (is_cce_classified)
  1729. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1730. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1731. if (msdu_info->exception_fw) {
  1732. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1733. }
  1734. /*
  1735. * Enqueue the Tx MSDU descriptor to HW for transmit
  1736. */
  1737. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  1738. htt_tcl_metadata, tx_q->ring_id, NULL);
  1739. if (status != QDF_STATUS_SUCCESS) {
  1740. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1741. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1742. __func__, tx_desc, tx_q->ring_id);
  1743. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1744. tid_stats = &pdev->stats.tid_stats.
  1745. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1746. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1747. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1748. if (msdu_info->frm_type == dp_tx_frm_me) {
  1749. i++;
  1750. continue;
  1751. }
  1752. goto done;
  1753. }
  1754. /*
  1755. * TODO
  1756. * if tso_info structure can be modified to have curr_seg
  1757. * as first element, following 2 blocks of code (for TSO and SG)
  1758. * can be combined into 1
  1759. */
  1760. /*
  1761. * For frames with multiple segments (TSO, ME), jump to next
  1762. * segment.
  1763. */
  1764. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1765. if (msdu_info->u.tso_info.curr_seg->next) {
  1766. msdu_info->u.tso_info.curr_seg =
  1767. msdu_info->u.tso_info.curr_seg->next;
  1768. /*
  1769. * If this is a jumbo nbuf, then increment the number of
  1770. * nbuf users for each additional segment of the msdu.
  1771. * This will ensure that the skb is freed only after
  1772. * receiving tx completion for all segments of an nbuf
  1773. */
  1774. qdf_nbuf_inc_users(nbuf);
  1775. /* Check with MCL if this is needed */
  1776. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1777. }
  1778. }
  1779. /*
  1780. * For Multicast-Unicast converted packets,
  1781. * each converted frame (for a client) is represented as
  1782. * 1 segment
  1783. */
  1784. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1785. (msdu_info->frm_type == dp_tx_frm_me)) {
  1786. if (msdu_info->u.sg_info.curr_seg->next) {
  1787. msdu_info->u.sg_info.curr_seg =
  1788. msdu_info->u.sg_info.curr_seg->next;
  1789. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1790. }
  1791. }
  1792. i++;
  1793. }
  1794. nbuf = NULL;
  1795. done:
  1796. return nbuf;
  1797. }
  1798. /**
  1799. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1800. * for SG frames
  1801. * @vdev: DP vdev handle
  1802. * @nbuf: skb
  1803. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1804. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1805. *
  1806. * Return: NULL on success,
  1807. * nbuf when it fails to send
  1808. */
  1809. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1810. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1811. {
  1812. uint32_t cur_frag, nr_frags;
  1813. qdf_dma_addr_t paddr;
  1814. struct dp_tx_sg_info_s *sg_info;
  1815. sg_info = &msdu_info->u.sg_info;
  1816. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1817. if (QDF_STATUS_SUCCESS !=
  1818. qdf_nbuf_map_nbytes_single(vdev->osdev, nbuf,
  1819. QDF_DMA_TO_DEVICE, nbuf->len)) {
  1820. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1821. "dma map error");
  1822. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1823. qdf_nbuf_free(nbuf);
  1824. return NULL;
  1825. }
  1826. paddr = qdf_nbuf_mapped_paddr_get(nbuf);
  1827. seg_info->frags[0].paddr_lo = paddr;
  1828. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  1829. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1830. seg_info->frags[0].vaddr = (void *) nbuf;
  1831. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1832. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1833. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1834. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1835. "frag dma map error");
  1836. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1837. qdf_nbuf_free(nbuf);
  1838. return NULL;
  1839. }
  1840. paddr = qdf_nbuf_get_tx_frag_paddr(nbuf);
  1841. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1842. seg_info->frags[cur_frag + 1].paddr_hi =
  1843. ((uint64_t) paddr) >> 32;
  1844. seg_info->frags[cur_frag + 1].len =
  1845. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1846. }
  1847. seg_info->frag_cnt = (cur_frag + 1);
  1848. seg_info->total_len = qdf_nbuf_len(nbuf);
  1849. seg_info->next = NULL;
  1850. sg_info->curr_seg = seg_info;
  1851. msdu_info->frm_type = dp_tx_frm_sg;
  1852. msdu_info->num_seg = 1;
  1853. return nbuf;
  1854. }
  1855. /**
  1856. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  1857. * @vdev: DP vdev handle
  1858. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1859. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  1860. *
  1861. * Return: NULL on failure,
  1862. * nbuf when extracted successfully
  1863. */
  1864. static
  1865. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  1866. struct dp_tx_msdu_info_s *msdu_info,
  1867. uint16_t ppdu_cookie)
  1868. {
  1869. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1870. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1871. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1872. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  1873. (msdu_info->meta_data[5], 1);
  1874. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  1875. (msdu_info->meta_data[5], 1);
  1876. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  1877. (msdu_info->meta_data[6], ppdu_cookie);
  1878. msdu_info->exception_fw = 1;
  1879. msdu_info->is_tx_sniffer = 1;
  1880. }
  1881. #ifdef MESH_MODE_SUPPORT
  1882. /**
  1883. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1884. and prepare msdu_info for mesh frames.
  1885. * @vdev: DP vdev handle
  1886. * @nbuf: skb
  1887. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1888. *
  1889. * Return: NULL on failure,
  1890. * nbuf when extracted successfully
  1891. */
  1892. static
  1893. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1894. struct dp_tx_msdu_info_s *msdu_info)
  1895. {
  1896. struct meta_hdr_s *mhdr;
  1897. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1898. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1899. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1900. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  1901. msdu_info->exception_fw = 0;
  1902. goto remove_meta_hdr;
  1903. }
  1904. msdu_info->exception_fw = 1;
  1905. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1906. meta_data->host_tx_desc_pool = 1;
  1907. meta_data->update_peer_cache = 1;
  1908. meta_data->learning_frame = 1;
  1909. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1910. meta_data->power = mhdr->power;
  1911. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1912. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1913. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1914. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1915. meta_data->dyn_bw = 1;
  1916. meta_data->valid_pwr = 1;
  1917. meta_data->valid_mcs_mask = 1;
  1918. meta_data->valid_nss_mask = 1;
  1919. meta_data->valid_preamble_type = 1;
  1920. meta_data->valid_retries = 1;
  1921. meta_data->valid_bw_info = 1;
  1922. }
  1923. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1924. meta_data->encrypt_type = 0;
  1925. meta_data->valid_encrypt_type = 1;
  1926. meta_data->learning_frame = 0;
  1927. }
  1928. meta_data->valid_key_flags = 1;
  1929. meta_data->key_flags = (mhdr->keyix & 0x3);
  1930. remove_meta_hdr:
  1931. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1932. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1933. "qdf_nbuf_pull_head failed");
  1934. qdf_nbuf_free(nbuf);
  1935. return NULL;
  1936. }
  1937. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1938. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1939. "%s , Meta hdr %0x %0x %0x %0x %0x %0x"
  1940. " tid %d to_fw %d",
  1941. __func__, msdu_info->meta_data[0],
  1942. msdu_info->meta_data[1],
  1943. msdu_info->meta_data[2],
  1944. msdu_info->meta_data[3],
  1945. msdu_info->meta_data[4],
  1946. msdu_info->meta_data[5],
  1947. msdu_info->tid, msdu_info->exception_fw);
  1948. return nbuf;
  1949. }
  1950. #else
  1951. static
  1952. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1953. struct dp_tx_msdu_info_s *msdu_info)
  1954. {
  1955. return nbuf;
  1956. }
  1957. #endif
  1958. /**
  1959. * dp_check_exc_metadata() - Checks if parameters are valid
  1960. * @tx_exc - holds all exception path parameters
  1961. *
  1962. * Returns true when all the parameters are valid else false
  1963. *
  1964. */
  1965. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  1966. {
  1967. bool invalid_tid = (tx_exc->tid > DP_MAX_TIDS && tx_exc->tid !=
  1968. HTT_INVALID_TID);
  1969. bool invalid_encap_type =
  1970. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  1971. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  1972. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  1973. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  1974. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  1975. tx_exc->ppdu_cookie == 0);
  1976. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  1977. invalid_cookie) {
  1978. return false;
  1979. }
  1980. return true;
  1981. }
  1982. /**
  1983. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  1984. * @soc: DP soc handle
  1985. * @vdev_id: id of DP vdev handle
  1986. * @nbuf: skb
  1987. * @tx_exc_metadata: Handle that holds exception path meta data
  1988. *
  1989. * Entry point for Core Tx layer (DP_TX) invoked from
  1990. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  1991. *
  1992. * Return: NULL on success,
  1993. * nbuf when it fails to send
  1994. */
  1995. qdf_nbuf_t
  1996. dp_tx_send_exception(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  1997. qdf_nbuf_t nbuf,
  1998. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1999. {
  2000. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2001. qdf_ether_header_t *eh = NULL;
  2002. struct dp_tx_msdu_info_s msdu_info;
  2003. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2004. DP_MOD_ID_TX_EXCEPTION);
  2005. if (qdf_unlikely(!vdev))
  2006. goto fail;
  2007. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2008. if (!tx_exc_metadata)
  2009. goto fail;
  2010. msdu_info.tid = tx_exc_metadata->tid;
  2011. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2012. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2013. QDF_MAC_ADDR_REF(nbuf->data));
  2014. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2015. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  2016. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2017. "Invalid parameters in exception path");
  2018. goto fail;
  2019. }
  2020. /* Basic sanity checks for unsupported packets */
  2021. /* MESH mode */
  2022. if (qdf_unlikely(vdev->mesh_vdev)) {
  2023. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2024. "Mesh mode is not supported in exception path");
  2025. goto fail;
  2026. }
  2027. /* TSO or SG */
  2028. if (qdf_unlikely(qdf_nbuf_is_tso(nbuf)) ||
  2029. qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2030. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2031. "TSO and SG are not supported in exception path");
  2032. goto fail;
  2033. }
  2034. /* RAW */
  2035. if (qdf_unlikely(tx_exc_metadata->tx_encap_type == htt_cmn_pkt_type_raw)) {
  2036. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2037. "Raw frame is not supported in exception path");
  2038. goto fail;
  2039. }
  2040. /* Mcast enhancement*/
  2041. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  2042. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2043. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2044. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2045. "Ignoring mcast_enhancement_en which is set and sending the mcast packet to the FW");
  2046. }
  2047. }
  2048. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  2049. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  2050. qdf_nbuf_len(nbuf));
  2051. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  2052. tx_exc_metadata->ppdu_cookie);
  2053. }
  2054. /*
  2055. * Get HW Queue to use for this frame.
  2056. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2057. * dedicated for data and 1 for command.
  2058. * "queue_id" maps to one hardware ring.
  2059. * With each ring, we also associate a unique Tx descriptor pool
  2060. * to minimize lock contention for these resources.
  2061. */
  2062. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2063. /*
  2064. * Check exception descriptors
  2065. */
  2066. if (dp_tx_exception_limit_check(vdev))
  2067. goto fail;
  2068. /* Single linear frame */
  2069. /*
  2070. * If nbuf is a simple linear frame, use send_single function to
  2071. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2072. * SRNG. There is no need to setup a MSDU extension descriptor.
  2073. */
  2074. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2075. tx_exc_metadata->peer_id, tx_exc_metadata);
  2076. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2077. return nbuf;
  2078. fail:
  2079. if (vdev)
  2080. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2081. dp_verbose_debug("pkt send failed");
  2082. return nbuf;
  2083. }
  2084. /**
  2085. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  2086. * @soc: DP soc handle
  2087. * @vdev_id: DP vdev handle
  2088. * @nbuf: skb
  2089. *
  2090. * Entry point for Core Tx layer (DP_TX) invoked from
  2091. * hard_start_xmit in OSIF/HDD
  2092. *
  2093. * Return: NULL on success,
  2094. * nbuf when it fails to send
  2095. */
  2096. #ifdef MESH_MODE_SUPPORT
  2097. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2098. qdf_nbuf_t nbuf)
  2099. {
  2100. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2101. struct meta_hdr_s *mhdr;
  2102. qdf_nbuf_t nbuf_mesh = NULL;
  2103. qdf_nbuf_t nbuf_clone = NULL;
  2104. struct dp_vdev *vdev;
  2105. uint8_t no_enc_frame = 0;
  2106. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  2107. if (!nbuf_mesh) {
  2108. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2109. "qdf_nbuf_unshare failed");
  2110. return nbuf;
  2111. }
  2112. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_MESH);
  2113. if (!vdev) {
  2114. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2115. "vdev is NULL for vdev_id %d", vdev_id);
  2116. return nbuf;
  2117. }
  2118. nbuf = nbuf_mesh;
  2119. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2120. if ((vdev->sec_type != cdp_sec_type_none) &&
  2121. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  2122. no_enc_frame = 1;
  2123. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  2124. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  2125. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  2126. !no_enc_frame) {
  2127. nbuf_clone = qdf_nbuf_clone(nbuf);
  2128. if (!nbuf_clone) {
  2129. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2130. "qdf_nbuf_clone failed");
  2131. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2132. return nbuf;
  2133. }
  2134. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  2135. }
  2136. if (nbuf_clone) {
  2137. if (!dp_tx_send(soc_hdl, vdev_id, nbuf_clone)) {
  2138. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2139. } else {
  2140. qdf_nbuf_free(nbuf_clone);
  2141. }
  2142. }
  2143. if (no_enc_frame)
  2144. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  2145. else
  2146. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  2147. nbuf = dp_tx_send(soc_hdl, vdev_id, nbuf);
  2148. if ((!nbuf) && no_enc_frame) {
  2149. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2150. }
  2151. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2152. return nbuf;
  2153. }
  2154. #else
  2155. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc, uint8_t vdev_id,
  2156. qdf_nbuf_t nbuf)
  2157. {
  2158. return dp_tx_send(soc, vdev_id, nbuf);
  2159. }
  2160. #endif
  2161. /**
  2162. * dp_tx_nawds_handler() - NAWDS handler
  2163. *
  2164. * @soc: DP soc handle
  2165. * @vdev_id: id of DP vdev handle
  2166. * @msdu_info: msdu_info required to create HTT metadata
  2167. * @nbuf: skb
  2168. *
  2169. * This API transfers the multicast frames with the peer id
  2170. * on NAWDS enabled peer.
  2171. * Return: none
  2172. */
  2173. static inline
  2174. void dp_tx_nawds_handler(struct dp_soc *soc, struct dp_vdev *vdev,
  2175. struct dp_tx_msdu_info_s *msdu_info, qdf_nbuf_t nbuf)
  2176. {
  2177. struct dp_peer *peer = NULL;
  2178. qdf_nbuf_t nbuf_clone = NULL;
  2179. uint16_t peer_id = DP_INVALID_PEER;
  2180. uint16_t sa_peer_id = DP_INVALID_PEER;
  2181. struct dp_ast_entry *ast_entry = NULL;
  2182. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2183. if (qdf_nbuf_get_tx_ftype(nbuf) == CB_FTYPE_INTRABSS_FWD) {
  2184. qdf_spin_lock_bh(&soc->ast_lock);
  2185. ast_entry = dp_peer_ast_hash_find_by_pdevid
  2186. (soc,
  2187. (uint8_t *)(eh->ether_shost),
  2188. vdev->pdev->pdev_id);
  2189. if (ast_entry)
  2190. sa_peer_id = ast_entry->peer_id;
  2191. qdf_spin_unlock_bh(&soc->ast_lock);
  2192. }
  2193. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2194. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2195. if (!peer->bss_peer && peer->nawds_enabled) {
  2196. peer_id = peer->peer_id;
  2197. /* Multicast packets needs to be
  2198. * dropped in case of intra bss forwarding
  2199. */
  2200. if (sa_peer_id == peer->peer_id) {
  2201. QDF_TRACE(QDF_MODULE_ID_DP,
  2202. QDF_TRACE_LEVEL_DEBUG,
  2203. " %s: multicast packet", __func__);
  2204. DP_STATS_INC(peer, tx.nawds_mcast_drop, 1);
  2205. continue;
  2206. }
  2207. nbuf_clone = qdf_nbuf_clone(nbuf);
  2208. if (!nbuf_clone) {
  2209. QDF_TRACE(QDF_MODULE_ID_DP,
  2210. QDF_TRACE_LEVEL_ERROR,
  2211. FL("nbuf clone failed"));
  2212. break;
  2213. }
  2214. nbuf_clone = dp_tx_send_msdu_single(vdev, nbuf_clone,
  2215. msdu_info, peer_id,
  2216. NULL);
  2217. if (nbuf_clone) {
  2218. QDF_TRACE(QDF_MODULE_ID_DP,
  2219. QDF_TRACE_LEVEL_DEBUG,
  2220. FL("pkt send failed"));
  2221. qdf_nbuf_free(nbuf_clone);
  2222. } else {
  2223. if (peer_id != DP_INVALID_PEER)
  2224. DP_STATS_INC_PKT(peer, tx.nawds_mcast,
  2225. 1, qdf_nbuf_len(nbuf));
  2226. }
  2227. }
  2228. }
  2229. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2230. }
  2231. /**
  2232. * dp_tx_send() - Transmit a frame on a given VAP
  2233. * @soc: DP soc handle
  2234. * @vdev_id: id of DP vdev handle
  2235. * @nbuf: skb
  2236. *
  2237. * Entry point for Core Tx layer (DP_TX) invoked from
  2238. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  2239. * cases
  2240. *
  2241. * Return: NULL on success,
  2242. * nbuf when it fails to send
  2243. */
  2244. qdf_nbuf_t dp_tx_send(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2245. qdf_nbuf_t nbuf)
  2246. {
  2247. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2248. uint16_t peer_id = HTT_INVALID_PEER;
  2249. /*
  2250. * doing a memzero is causing additional function call overhead
  2251. * so doing static stack clearing
  2252. */
  2253. struct dp_tx_msdu_info_s msdu_info = {0};
  2254. struct dp_vdev *vdev = NULL;
  2255. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  2256. return nbuf;
  2257. /*
  2258. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  2259. * this in per packet path.
  2260. *
  2261. * As in this path vdev memory is already protected with netdev
  2262. * tx lock
  2263. */
  2264. vdev = soc->vdev_id_map[vdev_id];
  2265. if (qdf_unlikely(!vdev))
  2266. return nbuf;
  2267. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2268. QDF_MAC_ADDR_REF(nbuf->data));
  2269. /*
  2270. * Set Default Host TID value to invalid TID
  2271. * (TID override disabled)
  2272. */
  2273. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  2274. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2275. if (qdf_unlikely(vdev->mesh_vdev)) {
  2276. qdf_nbuf_t nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  2277. &msdu_info);
  2278. if (!nbuf_mesh) {
  2279. dp_verbose_debug("Extracting mesh metadata failed");
  2280. return nbuf;
  2281. }
  2282. nbuf = nbuf_mesh;
  2283. }
  2284. /*
  2285. * Get HW Queue to use for this frame.
  2286. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2287. * dedicated for data and 1 for command.
  2288. * "queue_id" maps to one hardware ring.
  2289. * With each ring, we also associate a unique Tx descriptor pool
  2290. * to minimize lock contention for these resources.
  2291. */
  2292. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2293. /*
  2294. * TCL H/W supports 2 DSCP-TID mapping tables.
  2295. * Table 1 - Default DSCP-TID mapping table
  2296. * Table 2 - 1 DSCP-TID override table
  2297. *
  2298. * If we need a different DSCP-TID mapping for this vap,
  2299. * call tid_classify to extract DSCP/ToS from frame and
  2300. * map to a TID and store in msdu_info. This is later used
  2301. * to fill in TCL Input descriptor (per-packet TID override).
  2302. */
  2303. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  2304. /*
  2305. * Classify the frame and call corresponding
  2306. * "prepare" function which extracts the segment (TSO)
  2307. * and fragmentation information (for TSO , SG, ME, or Raw)
  2308. * into MSDU_INFO structure which is later used to fill
  2309. * SW and HW descriptors.
  2310. */
  2311. if (qdf_nbuf_is_tso(nbuf)) {
  2312. dp_verbose_debug("TSO frame %pK", vdev);
  2313. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2314. qdf_nbuf_len(nbuf));
  2315. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2316. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2317. qdf_nbuf_len(nbuf));
  2318. return nbuf;
  2319. }
  2320. goto send_multiple;
  2321. }
  2322. /* SG */
  2323. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2324. struct dp_tx_seg_info_s seg_info = {0};
  2325. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2326. if (!nbuf)
  2327. return NULL;
  2328. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2329. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2330. qdf_nbuf_len(nbuf));
  2331. goto send_multiple;
  2332. }
  2333. #ifdef ATH_SUPPORT_IQUE
  2334. /* Mcast to Ucast Conversion*/
  2335. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  2336. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  2337. qdf_nbuf_data(nbuf);
  2338. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2339. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2340. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  2341. DP_STATS_INC_PKT(vdev,
  2342. tx_i.mcast_en.mcast_pkt, 1,
  2343. qdf_nbuf_len(nbuf));
  2344. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  2345. QDF_STATUS_SUCCESS) {
  2346. return NULL;
  2347. }
  2348. if (qdf_unlikely(vdev->igmp_mcast_enhanc_en > 0)) {
  2349. if (dp_tx_prepare_send_igmp_me(vdev, nbuf) ==
  2350. QDF_STATUS_SUCCESS) {
  2351. return NULL;
  2352. }
  2353. }
  2354. }
  2355. }
  2356. #endif
  2357. /* RAW */
  2358. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  2359. struct dp_tx_seg_info_s seg_info = {0};
  2360. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  2361. if (!nbuf)
  2362. return NULL;
  2363. dp_verbose_debug("Raw frame %pK", vdev);
  2364. goto send_multiple;
  2365. }
  2366. if (qdf_unlikely(vdev->nawds_enabled)) {
  2367. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  2368. qdf_nbuf_data(nbuf);
  2369. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost))
  2370. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf);
  2371. peer_id = DP_INVALID_PEER;
  2372. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2373. 1, qdf_nbuf_len(nbuf));
  2374. }
  2375. /* Single linear frame */
  2376. /*
  2377. * If nbuf is a simple linear frame, use send_single function to
  2378. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2379. * SRNG. There is no need to setup a MSDU extension descriptor.
  2380. */
  2381. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  2382. return nbuf;
  2383. send_multiple:
  2384. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2385. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  2386. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  2387. return nbuf;
  2388. }
  2389. /**
  2390. * dp_tx_reinject_handler() - Tx Reinject Handler
  2391. * @soc: datapath soc handle
  2392. * @vdev: datapath vdev handle
  2393. * @tx_desc: software descriptor head pointer
  2394. * @status : Tx completion status from HTT descriptor
  2395. *
  2396. * This function reinjects frames back to Target.
  2397. * Todo - Host queue needs to be added
  2398. *
  2399. * Return: none
  2400. */
  2401. static
  2402. void dp_tx_reinject_handler(struct dp_soc *soc,
  2403. struct dp_vdev *vdev,
  2404. struct dp_tx_desc_s *tx_desc,
  2405. uint8_t *status)
  2406. {
  2407. struct dp_peer *peer = NULL;
  2408. uint32_t peer_id = HTT_INVALID_PEER;
  2409. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2410. qdf_nbuf_t nbuf_copy = NULL;
  2411. struct dp_tx_msdu_info_s msdu_info;
  2412. #ifdef WDS_VENDOR_EXTENSION
  2413. int is_mcast = 0, is_ucast = 0;
  2414. int num_peers_3addr = 0;
  2415. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  2416. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  2417. #endif
  2418. qdf_assert(vdev);
  2419. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2420. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2421. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2422. "%s Tx reinject path", __func__);
  2423. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  2424. qdf_nbuf_len(tx_desc->nbuf));
  2425. #ifdef WDS_VENDOR_EXTENSION
  2426. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  2427. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  2428. } else {
  2429. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  2430. }
  2431. is_ucast = !is_mcast;
  2432. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2433. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2434. if (peer->bss_peer)
  2435. continue;
  2436. /* Detect wds peers that use 3-addr framing for mcast.
  2437. * if there are any, the bss_peer is used to send the
  2438. * the mcast frame using 3-addr format. all wds enabled
  2439. * peers that use 4-addr framing for mcast frames will
  2440. * be duplicated and sent as 4-addr frames below.
  2441. */
  2442. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  2443. num_peers_3addr = 1;
  2444. break;
  2445. }
  2446. }
  2447. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2448. #endif
  2449. if (qdf_unlikely(vdev->mesh_vdev)) {
  2450. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  2451. } else {
  2452. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2453. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2454. if ((peer->peer_id != HTT_INVALID_PEER) &&
  2455. #ifdef WDS_VENDOR_EXTENSION
  2456. /*
  2457. * . if 3-addr STA, then send on BSS Peer
  2458. * . if Peer WDS enabled and accept 4-addr mcast,
  2459. * send mcast on that peer only
  2460. * . if Peer WDS enabled and accept 4-addr ucast,
  2461. * send ucast on that peer only
  2462. */
  2463. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  2464. (peer->wds_enabled &&
  2465. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  2466. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  2467. #else
  2468. ((peer->bss_peer &&
  2469. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))))) {
  2470. #endif
  2471. peer_id = DP_INVALID_PEER;
  2472. nbuf_copy = qdf_nbuf_copy(nbuf);
  2473. if (!nbuf_copy) {
  2474. QDF_TRACE(QDF_MODULE_ID_DP,
  2475. QDF_TRACE_LEVEL_DEBUG,
  2476. FL("nbuf copy failed"));
  2477. break;
  2478. }
  2479. nbuf_copy = dp_tx_send_msdu_single(vdev,
  2480. nbuf_copy,
  2481. &msdu_info,
  2482. peer_id,
  2483. NULL);
  2484. if (nbuf_copy) {
  2485. QDF_TRACE(QDF_MODULE_ID_DP,
  2486. QDF_TRACE_LEVEL_DEBUG,
  2487. FL("pkt send failed"));
  2488. qdf_nbuf_free(nbuf_copy);
  2489. }
  2490. }
  2491. }
  2492. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2493. }
  2494. qdf_nbuf_free(nbuf);
  2495. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2496. }
  2497. /**
  2498. * dp_tx_inspect_handler() - Tx Inspect Handler
  2499. * @soc: datapath soc handle
  2500. * @vdev: datapath vdev handle
  2501. * @tx_desc: software descriptor head pointer
  2502. * @status : Tx completion status from HTT descriptor
  2503. *
  2504. * Handles Tx frames sent back to Host for inspection
  2505. * (ProxyARP)
  2506. *
  2507. * Return: none
  2508. */
  2509. static void dp_tx_inspect_handler(struct dp_soc *soc,
  2510. struct dp_vdev *vdev,
  2511. struct dp_tx_desc_s *tx_desc,
  2512. uint8_t *status)
  2513. {
  2514. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2515. "%s Tx inspect path",
  2516. __func__);
  2517. DP_STATS_INC_PKT(vdev, tx_i.inspect_pkts, 1,
  2518. qdf_nbuf_len(tx_desc->nbuf));
  2519. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  2520. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2521. }
  2522. #ifdef FEATURE_PERPKT_INFO
  2523. /**
  2524. * dp_get_completion_indication_for_stack() - send completion to stack
  2525. * @soc : dp_soc handle
  2526. * @pdev: dp_pdev handle
  2527. * @peer: dp peer handle
  2528. * @ts: transmit completion status structure
  2529. * @netbuf: Buffer pointer for free
  2530. *
  2531. * This function is used for indication whether buffer needs to be
  2532. * sent to stack for freeing or not
  2533. */
  2534. QDF_STATUS
  2535. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2536. struct dp_pdev *pdev,
  2537. struct dp_peer *peer,
  2538. struct hal_tx_completion_status *ts,
  2539. qdf_nbuf_t netbuf,
  2540. uint64_t time_latency)
  2541. {
  2542. struct tx_capture_hdr *ppdu_hdr;
  2543. uint16_t peer_id = ts->peer_id;
  2544. uint32_t ppdu_id = ts->ppdu_id;
  2545. uint8_t first_msdu = ts->first_msdu;
  2546. uint8_t last_msdu = ts->last_msdu;
  2547. uint32_t txcap_hdr_size = sizeof(struct tx_capture_hdr);
  2548. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode &&
  2549. !pdev->latency_capture_enable))
  2550. return QDF_STATUS_E_NOSUPPORT;
  2551. if (!peer) {
  2552. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2553. FL("Peer Invalid"));
  2554. return QDF_STATUS_E_INVAL;
  2555. }
  2556. if (pdev->mcopy_mode) {
  2557. /* If mcopy is enabled and mcopy_mode is M_COPY deliver 1st MSDU
  2558. * per PPDU. If mcopy_mode is M_COPY_EXTENDED deliver 1st MSDU
  2559. * for each MPDU
  2560. */
  2561. if (pdev->mcopy_mode == M_COPY) {
  2562. if ((pdev->m_copy_id.tx_ppdu_id == ppdu_id) &&
  2563. (pdev->m_copy_id.tx_peer_id == peer_id)) {
  2564. return QDF_STATUS_E_INVAL;
  2565. }
  2566. }
  2567. if (!first_msdu)
  2568. return QDF_STATUS_E_INVAL;
  2569. pdev->m_copy_id.tx_ppdu_id = ppdu_id;
  2570. pdev->m_copy_id.tx_peer_id = peer_id;
  2571. }
  2572. if (qdf_unlikely(qdf_nbuf_headroom(netbuf) < txcap_hdr_size)) {
  2573. netbuf = qdf_nbuf_realloc_headroom(netbuf, txcap_hdr_size);
  2574. if (!netbuf) {
  2575. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2576. FL("No headroom"));
  2577. return QDF_STATUS_E_NOMEM;
  2578. }
  2579. }
  2580. if (!qdf_nbuf_push_head(netbuf, txcap_hdr_size)) {
  2581. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2582. FL("No headroom"));
  2583. return QDF_STATUS_E_NOMEM;
  2584. }
  2585. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  2586. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  2587. QDF_MAC_ADDR_SIZE);
  2588. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  2589. QDF_MAC_ADDR_SIZE);
  2590. ppdu_hdr->ppdu_id = ppdu_id;
  2591. ppdu_hdr->peer_id = peer_id;
  2592. ppdu_hdr->first_msdu = first_msdu;
  2593. ppdu_hdr->last_msdu = last_msdu;
  2594. if (qdf_unlikely(pdev->latency_capture_enable)) {
  2595. ppdu_hdr->tsf = ts->tsf;
  2596. ppdu_hdr->time_latency = time_latency;
  2597. }
  2598. return QDF_STATUS_SUCCESS;
  2599. }
  2600. /**
  2601. * dp_send_completion_to_stack() - send completion to stack
  2602. * @soc : dp_soc handle
  2603. * @pdev: dp_pdev handle
  2604. * @peer_id: peer_id of the peer for which completion came
  2605. * @ppdu_id: ppdu_id
  2606. * @netbuf: Buffer pointer for free
  2607. *
  2608. * This function is used to send completion to stack
  2609. * to free buffer
  2610. */
  2611. void dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2612. uint16_t peer_id, uint32_t ppdu_id,
  2613. qdf_nbuf_t netbuf)
  2614. {
  2615. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  2616. netbuf, peer_id,
  2617. WDI_NO_VAL, pdev->pdev_id);
  2618. }
  2619. #else
  2620. static QDF_STATUS
  2621. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2622. struct dp_pdev *pdev,
  2623. struct dp_peer *peer,
  2624. struct hal_tx_completion_status *ts,
  2625. qdf_nbuf_t netbuf,
  2626. uint64_t time_latency)
  2627. {
  2628. return QDF_STATUS_E_NOSUPPORT;
  2629. }
  2630. static void
  2631. dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2632. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  2633. {
  2634. }
  2635. #endif
  2636. /**
  2637. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2638. * @soc: Soc handle
  2639. * @desc: software Tx descriptor to be processed
  2640. *
  2641. * Return: none
  2642. */
  2643. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  2644. struct dp_tx_desc_s *desc)
  2645. {
  2646. qdf_nbuf_t nbuf = desc->nbuf;
  2647. /* nbuf already freed in vdev detach path */
  2648. if (!nbuf)
  2649. return;
  2650. /* If it is TDLS mgmt, don't unmap or free the frame */
  2651. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  2652. return dp_non_std_tx_comp_free_buff(soc, desc);
  2653. /* 0 : MSDU buffer, 1 : MLE */
  2654. if (desc->msdu_ext_desc) {
  2655. /* TSO free */
  2656. if (hal_tx_ext_desc_get_tso_enable(
  2657. desc->msdu_ext_desc->vaddr)) {
  2658. /* unmap eash TSO seg before free the nbuf */
  2659. dp_tx_tso_unmap_segment(soc, desc->tso_desc,
  2660. desc->tso_num_desc);
  2661. qdf_nbuf_free(nbuf);
  2662. return;
  2663. }
  2664. }
  2665. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf,
  2666. QDF_DMA_TO_DEVICE, nbuf->len);
  2667. if (desc->flags & DP_TX_DESC_FLAG_MESH_MODE)
  2668. return dp_mesh_tx_comp_free_buff(soc, desc);
  2669. qdf_nbuf_free(nbuf);
  2670. }
  2671. #ifdef MESH_MODE_SUPPORT
  2672. /**
  2673. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2674. * in mesh meta header
  2675. * @tx_desc: software descriptor head pointer
  2676. * @ts: pointer to tx completion stats
  2677. * Return: none
  2678. */
  2679. static
  2680. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2681. struct hal_tx_completion_status *ts)
  2682. {
  2683. struct meta_hdr_s *mhdr;
  2684. qdf_nbuf_t netbuf = tx_desc->nbuf;
  2685. if (!tx_desc->msdu_ext_desc) {
  2686. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  2687. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2688. "netbuf %pK offset %d",
  2689. netbuf, tx_desc->pkt_offset);
  2690. return;
  2691. }
  2692. }
  2693. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2694. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2695. "netbuf %pK offset %lu", netbuf,
  2696. sizeof(struct meta_hdr_s));
  2697. return;
  2698. }
  2699. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  2700. mhdr->rssi = ts->ack_frame_rssi;
  2701. mhdr->band = tx_desc->pdev->operating_channel.band;
  2702. mhdr->channel = tx_desc->pdev->operating_channel.num;
  2703. }
  2704. #else
  2705. static
  2706. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2707. struct hal_tx_completion_status *ts)
  2708. {
  2709. }
  2710. #endif
  2711. #ifdef QCA_PEER_EXT_STATS
  2712. /*
  2713. * dp_tx_compute_tid_delay() - Compute per TID delay
  2714. * @stats: Per TID delay stats
  2715. * @tx_desc: Software Tx descriptor
  2716. *
  2717. * Compute the software enqueue and hw enqueue delays and
  2718. * update the respective histograms
  2719. *
  2720. * Return: void
  2721. */
  2722. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  2723. struct dp_tx_desc_s *tx_desc)
  2724. {
  2725. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  2726. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  2727. uint32_t sw_enqueue_delay, fwhw_transmit_delay;
  2728. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  2729. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  2730. timestamp_hw_enqueue = tx_desc->timestamp;
  2731. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  2732. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  2733. timestamp_hw_enqueue);
  2734. /*
  2735. * Update the Tx software enqueue delay and HW enque-Completion delay.
  2736. */
  2737. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  2738. dp_hist_update_stats(&tx_delay->hwtx_delay, fwhw_transmit_delay);
  2739. }
  2740. /*
  2741. * dp_tx_update_peer_ext_stats() - Update the peer extended stats
  2742. * @peer: DP peer context
  2743. * @tx_desc: Tx software descriptor
  2744. * @tid: Transmission ID
  2745. * @ring_id: Rx CPU context ID/CPU_ID
  2746. *
  2747. * Update the peer extended stats. These are enhanced other
  2748. * delay stats per msdu level.
  2749. *
  2750. * Return: void
  2751. */
  2752. static void dp_tx_update_peer_ext_stats(struct dp_peer *peer,
  2753. struct dp_tx_desc_s *tx_desc,
  2754. uint8_t tid, uint8_t ring_id)
  2755. {
  2756. struct dp_pdev *pdev = peer->vdev->pdev;
  2757. struct dp_soc *soc = NULL;
  2758. struct cdp_peer_ext_stats *pext_stats = NULL;
  2759. soc = pdev->soc;
  2760. if (qdf_likely(!wlan_cfg_is_peer_ext_stats_enabled(soc->wlan_cfg_ctx)))
  2761. return;
  2762. pext_stats = peer->pext_stats;
  2763. qdf_assert(pext_stats);
  2764. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  2765. /*
  2766. * For non-TID packets use the TID 9
  2767. */
  2768. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2769. tid = CDP_MAX_DATA_TIDS - 1;
  2770. dp_tx_compute_tid_delay(&pext_stats->delay_stats[tid][ring_id],
  2771. tx_desc);
  2772. }
  2773. #else
  2774. static inline void dp_tx_update_peer_ext_stats(struct dp_peer *peer,
  2775. struct dp_tx_desc_s *tx_desc,
  2776. uint8_t tid, uint8_t ring_id)
  2777. {
  2778. }
  2779. #endif
  2780. /**
  2781. * dp_tx_compute_delay() - Compute and fill in all timestamps
  2782. * to pass in correct fields
  2783. *
  2784. * @vdev: pdev handle
  2785. * @tx_desc: tx descriptor
  2786. * @tid: tid value
  2787. * @ring_id: TCL or WBM ring number for transmit path
  2788. * Return: none
  2789. */
  2790. static void dp_tx_compute_delay(struct dp_vdev *vdev,
  2791. struct dp_tx_desc_s *tx_desc,
  2792. uint8_t tid, uint8_t ring_id)
  2793. {
  2794. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  2795. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  2796. if (qdf_likely(!vdev->pdev->delay_stats_flag))
  2797. return;
  2798. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  2799. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  2800. timestamp_hw_enqueue = tx_desc->timestamp;
  2801. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  2802. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  2803. timestamp_hw_enqueue);
  2804. interframe_delay = (uint32_t)(timestamp_ingress -
  2805. vdev->prev_tx_enq_tstamp);
  2806. /*
  2807. * Delay in software enqueue
  2808. */
  2809. dp_update_delay_stats(vdev->pdev, sw_enqueue_delay, tid,
  2810. CDP_DELAY_STATS_SW_ENQ, ring_id);
  2811. /*
  2812. * Delay between packet enqueued to HW and Tx completion
  2813. */
  2814. dp_update_delay_stats(vdev->pdev, fwhw_transmit_delay, tid,
  2815. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id);
  2816. /*
  2817. * Update interframe delay stats calculated at hardstart receive point.
  2818. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  2819. * interframe delay will not be calculate correctly for 1st frame.
  2820. * On the other side, this will help in avoiding extra per packet check
  2821. * of !vdev->prev_tx_enq_tstamp.
  2822. */
  2823. dp_update_delay_stats(vdev->pdev, interframe_delay, tid,
  2824. CDP_DELAY_STATS_TX_INTERFRAME, ring_id);
  2825. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  2826. }
  2827. #ifdef DISABLE_DP_STATS
  2828. static
  2829. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_peer *peer)
  2830. {
  2831. }
  2832. #else
  2833. static
  2834. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_peer *peer)
  2835. {
  2836. enum qdf_proto_subtype subtype = QDF_PROTO_INVALID;
  2837. DPTRACE(qdf_dp_track_noack_check(nbuf, &subtype));
  2838. if (subtype != QDF_PROTO_INVALID)
  2839. DP_STATS_INC(peer, tx.no_ack_count[subtype], 1);
  2840. }
  2841. #endif
  2842. /**
  2843. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  2844. * per wbm ring
  2845. *
  2846. * @tx_desc: software descriptor head pointer
  2847. * @ts: Tx completion status
  2848. * @peer: peer handle
  2849. * @ring_id: ring number
  2850. *
  2851. * Return: None
  2852. */
  2853. static inline void
  2854. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  2855. struct hal_tx_completion_status *ts,
  2856. struct dp_peer *peer, uint8_t ring_id)
  2857. {
  2858. struct dp_pdev *pdev = peer->vdev->pdev;
  2859. struct dp_soc *soc = NULL;
  2860. uint8_t mcs, pkt_type;
  2861. uint8_t tid = ts->tid;
  2862. uint32_t length;
  2863. struct cdp_tid_tx_stats *tid_stats;
  2864. if (!pdev)
  2865. return;
  2866. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2867. tid = CDP_MAX_DATA_TIDS - 1;
  2868. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  2869. soc = pdev->soc;
  2870. mcs = ts->mcs;
  2871. pkt_type = ts->pkt_type;
  2872. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  2873. dp_err("Release source is not from TQM");
  2874. return;
  2875. }
  2876. length = qdf_nbuf_len(tx_desc->nbuf);
  2877. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  2878. if (qdf_unlikely(pdev->delay_stats_flag))
  2879. dp_tx_compute_delay(peer->vdev, tx_desc, tid, ring_id);
  2880. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  2881. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  2882. DP_STATS_INCC_PKT(peer, tx.dropped.fw_rem, 1, length,
  2883. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2884. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  2885. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  2886. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  2887. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  2888. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  2889. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  2890. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  2891. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  2892. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  2893. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  2894. /*
  2895. * tx_failed is ideally supposed to be updated from HTT ppdu completion
  2896. * stats. But in IPQ807X/IPQ6018 chipsets owing to hw limitation there
  2897. * are no completions for failed cases. Hence updating tx_failed from
  2898. * data path. Please note that if tx_failed is fixed to be from ppdu,
  2899. * then this has to be removed
  2900. */
  2901. peer->stats.tx.tx_failed = peer->stats.tx.dropped.fw_rem.num +
  2902. peer->stats.tx.dropped.fw_rem_notx +
  2903. peer->stats.tx.dropped.fw_rem_tx +
  2904. peer->stats.tx.dropped.age_out +
  2905. peer->stats.tx.dropped.fw_reason1 +
  2906. peer->stats.tx.dropped.fw_reason2 +
  2907. peer->stats.tx.dropped.fw_reason3;
  2908. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  2909. tid_stats->tqm_status_cnt[ts->status]++;
  2910. }
  2911. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  2912. dp_update_no_ack_stats(tx_desc->nbuf, peer);
  2913. return;
  2914. }
  2915. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  2916. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  2917. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  2918. /*
  2919. * Following Rate Statistics are updated from HTT PPDU events from FW.
  2920. * Return from here if HTT PPDU events are enabled.
  2921. */
  2922. if (!(soc->process_tx_status))
  2923. return;
  2924. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2925. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  2926. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2927. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  2928. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2929. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2930. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2931. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2932. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2933. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2934. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2935. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2936. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2937. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2938. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2939. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2940. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2941. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2942. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2943. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2944. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  2945. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  2946. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  2947. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  2948. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  2949. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  2950. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  2951. #if defined(FEATURE_PERPKT_INFO) && WDI_EVENT_ENABLE
  2952. dp_wdi_event_handler(WDI_EVENT_UPDATE_DP_STATS, pdev->soc,
  2953. &peer->stats, ts->peer_id,
  2954. UPDATE_PEER_STATS, pdev->pdev_id);
  2955. #endif
  2956. }
  2957. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2958. /**
  2959. * dp_tx_flow_pool_lock() - take flow pool lock
  2960. * @soc: core txrx main context
  2961. * @tx_desc: tx desc
  2962. *
  2963. * Return: None
  2964. */
  2965. static inline
  2966. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  2967. struct dp_tx_desc_s *tx_desc)
  2968. {
  2969. struct dp_tx_desc_pool_s *pool;
  2970. uint8_t desc_pool_id;
  2971. desc_pool_id = tx_desc->pool_id;
  2972. pool = &soc->tx_desc[desc_pool_id];
  2973. qdf_spin_lock_bh(&pool->flow_pool_lock);
  2974. }
  2975. /**
  2976. * dp_tx_flow_pool_unlock() - release flow pool lock
  2977. * @soc: core txrx main context
  2978. * @tx_desc: tx desc
  2979. *
  2980. * Return: None
  2981. */
  2982. static inline
  2983. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  2984. struct dp_tx_desc_s *tx_desc)
  2985. {
  2986. struct dp_tx_desc_pool_s *pool;
  2987. uint8_t desc_pool_id;
  2988. desc_pool_id = tx_desc->pool_id;
  2989. pool = &soc->tx_desc[desc_pool_id];
  2990. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  2991. }
  2992. #else
  2993. static inline
  2994. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2995. {
  2996. }
  2997. static inline
  2998. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2999. {
  3000. }
  3001. #endif
  3002. /**
  3003. * dp_tx_notify_completion() - Notify tx completion for this desc
  3004. * @soc: core txrx main context
  3005. * @vdev: datapath vdev handle
  3006. * @tx_desc: tx desc
  3007. * @netbuf: buffer
  3008. * @status: tx status
  3009. *
  3010. * Return: none
  3011. */
  3012. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  3013. struct dp_vdev *vdev,
  3014. struct dp_tx_desc_s *tx_desc,
  3015. qdf_nbuf_t netbuf,
  3016. uint8_t status)
  3017. {
  3018. void *osif_dev;
  3019. ol_txrx_completion_fp tx_compl_cbk = NULL;
  3020. uint16_t flag = BIT(QDF_TX_RX_STATUS_DOWNLOAD_SUCC);
  3021. qdf_assert(tx_desc);
  3022. dp_tx_flow_pool_lock(soc, tx_desc);
  3023. if (!vdev ||
  3024. !vdev->osif_vdev) {
  3025. dp_tx_flow_pool_unlock(soc, tx_desc);
  3026. return;
  3027. }
  3028. osif_dev = vdev->osif_vdev;
  3029. tx_compl_cbk = vdev->tx_comp;
  3030. dp_tx_flow_pool_unlock(soc, tx_desc);
  3031. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3032. flag |= BIT(QDF_TX_RX_STATUS_OK);
  3033. if (tx_compl_cbk)
  3034. tx_compl_cbk(netbuf, osif_dev, flag);
  3035. }
  3036. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  3037. * @pdev: pdev handle
  3038. * @tid: tid value
  3039. * @txdesc_ts: timestamp from txdesc
  3040. * @ppdu_id: ppdu id
  3041. *
  3042. * Return: none
  3043. */
  3044. #ifdef FEATURE_PERPKT_INFO
  3045. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3046. struct dp_peer *peer,
  3047. uint8_t tid,
  3048. uint64_t txdesc_ts,
  3049. uint32_t ppdu_id)
  3050. {
  3051. uint64_t delta_ms;
  3052. struct cdp_tx_sojourn_stats *sojourn_stats;
  3053. if (qdf_unlikely(pdev->enhanced_stats_en == 0))
  3054. return;
  3055. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  3056. tid >= CDP_DATA_TID_MAX))
  3057. return;
  3058. if (qdf_unlikely(!pdev->sojourn_buf))
  3059. return;
  3060. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  3061. qdf_nbuf_data(pdev->sojourn_buf);
  3062. sojourn_stats->cookie = (void *)peer->rdkstats_ctx;
  3063. delta_ms = qdf_ktime_to_ms(qdf_ktime_get()) -
  3064. txdesc_ts;
  3065. qdf_ewma_tx_lag_add(&peer->avg_sojourn_msdu[tid],
  3066. delta_ms);
  3067. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  3068. sojourn_stats->num_msdus[tid] = 1;
  3069. sojourn_stats->avg_sojourn_msdu[tid].internal =
  3070. peer->avg_sojourn_msdu[tid].internal;
  3071. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  3072. pdev->sojourn_buf, HTT_INVALID_PEER,
  3073. WDI_NO_VAL, pdev->pdev_id);
  3074. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  3075. sojourn_stats->num_msdus[tid] = 0;
  3076. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  3077. }
  3078. #else
  3079. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3080. struct dp_peer *peer,
  3081. uint8_t tid,
  3082. uint64_t txdesc_ts,
  3083. uint32_t ppdu_id)
  3084. {
  3085. }
  3086. #endif
  3087. /**
  3088. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  3089. * @soc: DP Soc handle
  3090. * @tx_desc: software Tx descriptor
  3091. * @ts : Tx completion status from HAL/HTT descriptor
  3092. *
  3093. * Return: none
  3094. */
  3095. static inline void
  3096. dp_tx_comp_process_desc(struct dp_soc *soc,
  3097. struct dp_tx_desc_s *desc,
  3098. struct hal_tx_completion_status *ts,
  3099. struct dp_peer *peer)
  3100. {
  3101. uint64_t time_latency = 0;
  3102. /*
  3103. * m_copy/tx_capture modes are not supported for
  3104. * scatter gather packets
  3105. */
  3106. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  3107. time_latency = (qdf_ktime_to_ms(qdf_ktime_real_get()) -
  3108. desc->timestamp);
  3109. }
  3110. if (!(desc->msdu_ext_desc)) {
  3111. if (QDF_STATUS_SUCCESS ==
  3112. dp_tx_add_to_comp_queue(soc, desc, ts, peer)) {
  3113. return;
  3114. }
  3115. if (QDF_STATUS_SUCCESS ==
  3116. dp_get_completion_indication_for_stack(soc,
  3117. desc->pdev,
  3118. peer, ts,
  3119. desc->nbuf,
  3120. time_latency)) {
  3121. qdf_nbuf_unmap_nbytes_single(soc->osdev, desc->nbuf,
  3122. QDF_DMA_TO_DEVICE,
  3123. desc->nbuf->len);
  3124. dp_send_completion_to_stack(soc,
  3125. desc->pdev,
  3126. ts->peer_id,
  3127. ts->ppdu_id,
  3128. desc->nbuf);
  3129. return;
  3130. }
  3131. }
  3132. dp_tx_comp_free_buf(soc, desc);
  3133. }
  3134. #ifdef DISABLE_DP_STATS
  3135. /**
  3136. * dp_tx_update_connectivity_stats() - update tx connectivity stats
  3137. * @soc: core txrx main context
  3138. * @tx_desc: tx desc
  3139. * @status: tx status
  3140. *
  3141. * Return: none
  3142. */
  3143. static inline
  3144. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3145. struct dp_vdev *vdev,
  3146. struct dp_tx_desc_s *tx_desc,
  3147. uint8_t status)
  3148. {
  3149. }
  3150. #else
  3151. static inline
  3152. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3153. struct dp_vdev *vdev,
  3154. struct dp_tx_desc_s *tx_desc,
  3155. uint8_t status)
  3156. {
  3157. void *osif_dev;
  3158. ol_txrx_stats_rx_fp stats_cbk;
  3159. uint8_t pkt_type;
  3160. qdf_assert(tx_desc);
  3161. if (!vdev ||
  3162. !vdev->osif_vdev ||
  3163. !vdev->stats_cb)
  3164. return;
  3165. osif_dev = vdev->osif_vdev;
  3166. stats_cbk = vdev->stats_cb;
  3167. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_HOST_FW_SENT, &pkt_type);
  3168. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3169. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_ACK_CNT,
  3170. &pkt_type);
  3171. }
  3172. #endif
  3173. /**
  3174. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  3175. * @soc: DP soc handle
  3176. * @tx_desc: software descriptor head pointer
  3177. * @ts: Tx completion status
  3178. * @peer: peer handle
  3179. * @ring_id: ring number
  3180. *
  3181. * Return: none
  3182. */
  3183. static inline
  3184. void dp_tx_comp_process_tx_status(struct dp_soc *soc,
  3185. struct dp_tx_desc_s *tx_desc,
  3186. struct hal_tx_completion_status *ts,
  3187. struct dp_peer *peer, uint8_t ring_id)
  3188. {
  3189. uint32_t length;
  3190. qdf_ether_header_t *eh;
  3191. struct dp_vdev *vdev = NULL;
  3192. qdf_nbuf_t nbuf = tx_desc->nbuf;
  3193. uint8_t dp_status;
  3194. if (!nbuf) {
  3195. dp_info_rl("invalid tx descriptor. nbuf NULL");
  3196. goto out;
  3197. }
  3198. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  3199. length = qdf_nbuf_len(nbuf);
  3200. dp_status = qdf_dp_get_status_from_htt(ts->status);
  3201. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  3202. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  3203. QDF_TRACE_DEFAULT_PDEV_ID,
  3204. qdf_nbuf_data_addr(nbuf),
  3205. sizeof(qdf_nbuf_data(nbuf)),
  3206. tx_desc->id,
  3207. dp_status));
  3208. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  3209. "-------------------- \n"
  3210. "Tx Completion Stats: \n"
  3211. "-------------------- \n"
  3212. "ack_frame_rssi = %d \n"
  3213. "first_msdu = %d \n"
  3214. "last_msdu = %d \n"
  3215. "msdu_part_of_amsdu = %d \n"
  3216. "rate_stats valid = %d \n"
  3217. "bw = %d \n"
  3218. "pkt_type = %d \n"
  3219. "stbc = %d \n"
  3220. "ldpc = %d \n"
  3221. "sgi = %d \n"
  3222. "mcs = %d \n"
  3223. "ofdma = %d \n"
  3224. "tones_in_ru = %d \n"
  3225. "tsf = %d \n"
  3226. "ppdu_id = %d \n"
  3227. "transmit_cnt = %d \n"
  3228. "tid = %d \n"
  3229. "peer_id = %d\n",
  3230. ts->ack_frame_rssi, ts->first_msdu,
  3231. ts->last_msdu, ts->msdu_part_of_amsdu,
  3232. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  3233. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  3234. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  3235. ts->transmit_cnt, ts->tid, ts->peer_id);
  3236. /* Update SoC level stats */
  3237. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  3238. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  3239. if (!peer) {
  3240. dp_err_rl("peer is null or deletion in progress");
  3241. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  3242. goto out;
  3243. }
  3244. vdev = peer->vdev;
  3245. dp_tx_update_connectivity_stats(soc, vdev, tx_desc, ts->status);
  3246. /* Update per-packet stats for mesh mode */
  3247. if (qdf_unlikely(vdev->mesh_vdev) &&
  3248. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  3249. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  3250. /* Update peer level stats */
  3251. if (qdf_unlikely(peer->bss_peer && vdev->opmode == wlan_op_mode_ap)) {
  3252. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  3253. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  3254. if ((peer->vdev->tx_encap_type ==
  3255. htt_cmn_pkt_type_ethernet) &&
  3256. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  3257. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  3258. }
  3259. }
  3260. } else {
  3261. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  3262. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED) {
  3263. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  3264. if (qdf_unlikely(peer->in_twt)) {
  3265. DP_STATS_INC_PKT(peer,
  3266. tx.tx_success_twt,
  3267. 1, length);
  3268. }
  3269. }
  3270. }
  3271. dp_tx_update_peer_stats(tx_desc, ts, peer, ring_id);
  3272. dp_tx_update_peer_ext_stats(peer, tx_desc, ts->tid, ring_id);
  3273. #ifdef QCA_SUPPORT_RDK_STATS
  3274. if (soc->rdkstats_enabled)
  3275. dp_tx_sojourn_stats_process(vdev->pdev, peer, ts->tid,
  3276. tx_desc->timestamp,
  3277. ts->ppdu_id);
  3278. #endif
  3279. out:
  3280. return;
  3281. }
  3282. /**
  3283. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  3284. * @soc: core txrx main context
  3285. * @comp_head: software descriptor head pointer
  3286. * @ring_id: ring number
  3287. *
  3288. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  3289. * and release the software descriptors after processing is complete
  3290. *
  3291. * Return: none
  3292. */
  3293. static void
  3294. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  3295. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  3296. {
  3297. struct dp_tx_desc_s *desc;
  3298. struct dp_tx_desc_s *next;
  3299. struct hal_tx_completion_status ts;
  3300. struct dp_peer *peer = NULL;
  3301. uint16_t peer_id = DP_INVALID_PEER;
  3302. qdf_nbuf_t netbuf;
  3303. desc = comp_head;
  3304. while (desc) {
  3305. if (peer_id != desc->peer_id) {
  3306. if (peer)
  3307. dp_peer_unref_delete(peer,
  3308. DP_MOD_ID_TX_COMP);
  3309. peer_id = desc->peer_id;
  3310. peer = dp_peer_get_ref_by_id(soc, peer_id,
  3311. DP_MOD_ID_TX_COMP);
  3312. }
  3313. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  3314. struct dp_pdev *pdev = desc->pdev;
  3315. if (qdf_likely(peer)) {
  3316. /*
  3317. * Increment peer statistics
  3318. * Minimal statistics update done here
  3319. */
  3320. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1,
  3321. desc->length);
  3322. if (desc->tx_status !=
  3323. HAL_TX_TQM_RR_FRAME_ACKED)
  3324. DP_STATS_INC(peer, tx.tx_failed, 1);
  3325. }
  3326. qdf_assert(pdev);
  3327. dp_tx_outstanding_dec(pdev);
  3328. /*
  3329. * Calling a QDF WRAPPER here is creating signifcant
  3330. * performance impact so avoided the wrapper call here
  3331. */
  3332. next = desc->next;
  3333. qdf_mem_unmap_nbytes_single(soc->osdev,
  3334. desc->dma_addr,
  3335. QDF_DMA_TO_DEVICE,
  3336. desc->length);
  3337. qdf_nbuf_free(desc->nbuf);
  3338. dp_tx_desc_free(soc, desc, desc->pool_id);
  3339. desc = next;
  3340. continue;
  3341. }
  3342. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  3343. dp_tx_comp_process_tx_status(soc, desc, &ts, peer, ring_id);
  3344. netbuf = desc->nbuf;
  3345. /* check tx complete notification */
  3346. if (peer &&
  3347. QDF_NBUF_CB_TX_EXTRA_FRAG_FLAGS_NOTIFY_COMP(netbuf))
  3348. dp_tx_notify_completion(soc, peer->vdev, desc,
  3349. netbuf, ts.status);
  3350. dp_tx_comp_process_desc(soc, desc, &ts, peer);
  3351. next = desc->next;
  3352. dp_tx_desc_release(desc, desc->pool_id);
  3353. desc = next;
  3354. }
  3355. if (peer)
  3356. dp_peer_unref_delete(peer, DP_MOD_ID_TX_COMP);
  3357. }
  3358. /**
  3359. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  3360. * @tx_desc: software descriptor head pointer
  3361. * @status : Tx completion status from HTT descriptor
  3362. * @ring_id: ring number
  3363. *
  3364. * This function will process HTT Tx indication messages from Target
  3365. *
  3366. * Return: none
  3367. */
  3368. static
  3369. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status,
  3370. uint8_t ring_id)
  3371. {
  3372. uint8_t tx_status;
  3373. struct dp_pdev *pdev;
  3374. struct dp_vdev *vdev;
  3375. struct dp_soc *soc;
  3376. struct hal_tx_completion_status ts = {0};
  3377. uint32_t *htt_desc = (uint32_t *)status;
  3378. struct dp_peer *peer;
  3379. struct cdp_tid_tx_stats *tid_stats = NULL;
  3380. struct htt_soc *htt_handle;
  3381. /*
  3382. * If the descriptor is already freed in vdev_detach,
  3383. * continue to next descriptor
  3384. */
  3385. if ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) && !tx_desc->flags) {
  3386. QDF_TRACE(QDF_MODULE_ID_DP,
  3387. QDF_TRACE_LEVEL_INFO,
  3388. "Descriptor freed in vdev_detach %d",
  3389. tx_desc->id);
  3390. return;
  3391. }
  3392. pdev = tx_desc->pdev;
  3393. soc = pdev->soc;
  3394. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  3395. QDF_TRACE(QDF_MODULE_ID_DP,
  3396. QDF_TRACE_LEVEL_INFO,
  3397. "pdev in down state %d",
  3398. tx_desc->id);
  3399. dp_tx_comp_free_buf(soc, tx_desc);
  3400. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3401. return;
  3402. }
  3403. qdf_assert(tx_desc->pdev);
  3404. vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  3405. DP_MOD_ID_HTT_COMP);
  3406. if (!vdev)
  3407. return;
  3408. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  3409. htt_handle = (struct htt_soc *)soc->htt_handle;
  3410. htt_wbm_event_record(htt_handle->htt_logger_handle, tx_status, status);
  3411. switch (tx_status) {
  3412. case HTT_TX_FW2WBM_TX_STATUS_OK:
  3413. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  3414. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  3415. {
  3416. uint8_t tid;
  3417. if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
  3418. ts.peer_id =
  3419. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
  3420. htt_desc[2]);
  3421. ts.tid =
  3422. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
  3423. htt_desc[2]);
  3424. } else {
  3425. ts.peer_id = HTT_INVALID_PEER;
  3426. ts.tid = HTT_INVALID_TID;
  3427. }
  3428. ts.ppdu_id =
  3429. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
  3430. htt_desc[1]);
  3431. ts.ack_frame_rssi =
  3432. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
  3433. htt_desc[1]);
  3434. ts.tsf = htt_desc[3];
  3435. ts.first_msdu = 1;
  3436. ts.last_msdu = 1;
  3437. tid = ts.tid;
  3438. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3439. tid = CDP_MAX_DATA_TIDS - 1;
  3440. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3441. if (qdf_unlikely(pdev->delay_stats_flag))
  3442. dp_tx_compute_delay(vdev, tx_desc, tid, ring_id);
  3443. if (tx_status < CDP_MAX_TX_HTT_STATUS) {
  3444. tid_stats->htt_status_cnt[tx_status]++;
  3445. }
  3446. peer = dp_peer_get_ref_by_id(soc, ts.peer_id,
  3447. DP_MOD_ID_HTT_COMP);
  3448. dp_tx_comp_process_tx_status(soc, tx_desc, &ts, peer, ring_id);
  3449. dp_tx_comp_process_desc(soc, tx_desc, &ts, peer);
  3450. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3451. if (qdf_likely(peer))
  3452. dp_peer_unref_delete(peer, DP_MOD_ID_HTT_COMP);
  3453. break;
  3454. }
  3455. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  3456. {
  3457. dp_tx_reinject_handler(soc, vdev, tx_desc, status);
  3458. break;
  3459. }
  3460. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  3461. {
  3462. dp_tx_inspect_handler(soc, vdev, tx_desc, status);
  3463. break;
  3464. }
  3465. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  3466. {
  3467. dp_tx_mec_handler(vdev, status);
  3468. break;
  3469. }
  3470. default:
  3471. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  3472. "%s Invalid HTT tx_status %d\n",
  3473. __func__, tx_status);
  3474. break;
  3475. }
  3476. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  3477. }
  3478. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  3479. static inline
  3480. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  3481. {
  3482. bool limit_hit = false;
  3483. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  3484. limit_hit =
  3485. (num_reaped >= cfg->tx_comp_loop_pkt_limit) ? true : false;
  3486. if (limit_hit)
  3487. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  3488. return limit_hit;
  3489. }
  3490. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  3491. {
  3492. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  3493. }
  3494. #else
  3495. static inline
  3496. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  3497. {
  3498. return false;
  3499. }
  3500. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  3501. {
  3502. return false;
  3503. }
  3504. #endif
  3505. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  3506. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  3507. uint32_t quota)
  3508. {
  3509. void *tx_comp_hal_desc;
  3510. uint8_t buffer_src;
  3511. uint8_t pool_id;
  3512. uint32_t tx_desc_id;
  3513. struct dp_tx_desc_s *tx_desc = NULL;
  3514. struct dp_tx_desc_s *head_desc = NULL;
  3515. struct dp_tx_desc_s *tail_desc = NULL;
  3516. uint32_t num_processed = 0;
  3517. uint32_t count;
  3518. uint32_t num_avail_for_reap = 0;
  3519. bool force_break = false;
  3520. DP_HIST_INIT();
  3521. more_data:
  3522. /* Re-initialize local variables to be re-used */
  3523. head_desc = NULL;
  3524. tail_desc = NULL;
  3525. count = 0;
  3526. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  3527. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  3528. return 0;
  3529. }
  3530. num_avail_for_reap = hal_srng_dst_num_valid(soc->hal_soc, hal_ring_hdl, 0);
  3531. if (num_avail_for_reap >= quota)
  3532. num_avail_for_reap = quota;
  3533. dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap);
  3534. /* Find head descriptor from completion ring */
  3535. while (qdf_likely(num_avail_for_reap)) {
  3536. tx_comp_hal_desc = dp_srng_dst_get_next(soc, hal_ring_hdl);
  3537. if (qdf_unlikely(!tx_comp_hal_desc))
  3538. break;
  3539. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  3540. /* If this buffer was not released by TQM or FW, then it is not
  3541. * Tx completion indication, assert */
  3542. if (qdf_unlikely(buffer_src !=
  3543. HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  3544. (qdf_unlikely(buffer_src !=
  3545. HAL_TX_COMP_RELEASE_SOURCE_FW))) {
  3546. uint8_t wbm_internal_error;
  3547. dp_err_rl(
  3548. "Tx comp release_src != TQM | FW but from %d",
  3549. buffer_src);
  3550. hal_dump_comp_desc(tx_comp_hal_desc);
  3551. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  3552. /* When WBM sees NULL buffer_addr_info in any of
  3553. * ingress rings it sends an error indication,
  3554. * with wbm_internal_error=1, to a specific ring.
  3555. * The WBM2SW ring used to indicate these errors is
  3556. * fixed in HW, and that ring is being used as Tx
  3557. * completion ring. These errors are not related to
  3558. * Tx completions, and should just be ignored
  3559. */
  3560. wbm_internal_error = hal_get_wbm_internal_error(
  3561. soc->hal_soc,
  3562. tx_comp_hal_desc);
  3563. if (wbm_internal_error) {
  3564. dp_err_rl("Tx comp wbm_internal_error!!");
  3565. DP_STATS_INC(soc, tx.wbm_internal_error[WBM_INT_ERROR_ALL], 1);
  3566. if (HAL_TX_COMP_RELEASE_SOURCE_REO ==
  3567. buffer_src)
  3568. dp_handle_wbm_internal_error(
  3569. soc,
  3570. tx_comp_hal_desc,
  3571. hal_tx_comp_get_buffer_type(
  3572. tx_comp_hal_desc));
  3573. } else {
  3574. dp_err_rl("Tx comp wbm_internal_error false");
  3575. DP_STATS_INC(soc, tx.non_wbm_internal_err, 1);
  3576. }
  3577. continue;
  3578. }
  3579. /* Get descriptor id */
  3580. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  3581. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  3582. DP_TX_DESC_ID_POOL_OS;
  3583. /* Find Tx descriptor */
  3584. tx_desc = dp_tx_desc_find(soc, pool_id,
  3585. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  3586. DP_TX_DESC_ID_PAGE_OS,
  3587. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  3588. DP_TX_DESC_ID_OFFSET_OS);
  3589. /*
  3590. * If the release source is FW, process the HTT status
  3591. */
  3592. if (qdf_unlikely(buffer_src ==
  3593. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  3594. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  3595. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  3596. htt_tx_status);
  3597. dp_tx_process_htt_completion(tx_desc,
  3598. htt_tx_status, ring_id);
  3599. } else {
  3600. tx_desc->peer_id =
  3601. hal_tx_comp_get_peer_id(tx_comp_hal_desc);
  3602. tx_desc->tx_status =
  3603. hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  3604. /*
  3605. * If the fast completion mode is enabled extended
  3606. * metadata from descriptor is not copied
  3607. */
  3608. if (qdf_likely(tx_desc->flags &
  3609. DP_TX_DESC_FLAG_SIMPLE))
  3610. goto add_to_pool;
  3611. /*
  3612. * If the descriptor is already freed in vdev_detach,
  3613. * continue to next descriptor
  3614. */
  3615. if (qdf_unlikely
  3616. ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) &&
  3617. !tx_desc->flags)) {
  3618. QDF_TRACE(QDF_MODULE_ID_DP,
  3619. QDF_TRACE_LEVEL_INFO,
  3620. "Descriptor freed in vdev_detach %d",
  3621. tx_desc_id);
  3622. continue;
  3623. }
  3624. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  3625. QDF_TRACE(QDF_MODULE_ID_DP,
  3626. QDF_TRACE_LEVEL_INFO,
  3627. "pdev in down state %d",
  3628. tx_desc_id);
  3629. dp_tx_comp_free_buf(soc, tx_desc);
  3630. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3631. goto next_desc;
  3632. }
  3633. /* Pool id is not matching. Error */
  3634. if (tx_desc->pool_id != pool_id) {
  3635. QDF_TRACE(QDF_MODULE_ID_DP,
  3636. QDF_TRACE_LEVEL_FATAL,
  3637. "Tx Comp pool id %d not matched %d",
  3638. pool_id, tx_desc->pool_id);
  3639. qdf_assert_always(0);
  3640. }
  3641. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  3642. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  3643. QDF_TRACE(QDF_MODULE_ID_DP,
  3644. QDF_TRACE_LEVEL_FATAL,
  3645. "Txdesc invalid, flgs = %x,id = %d",
  3646. tx_desc->flags, tx_desc_id);
  3647. qdf_assert_always(0);
  3648. }
  3649. /* Collect hw completion contents */
  3650. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  3651. &tx_desc->comp, 1);
  3652. add_to_pool:
  3653. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  3654. /* First ring descriptor on the cycle */
  3655. if (!head_desc) {
  3656. head_desc = tx_desc;
  3657. tail_desc = tx_desc;
  3658. }
  3659. tail_desc->next = tx_desc;
  3660. tx_desc->next = NULL;
  3661. tail_desc = tx_desc;
  3662. }
  3663. next_desc:
  3664. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  3665. /*
  3666. * Processed packet count is more than given quota
  3667. * stop to processing
  3668. */
  3669. count++;
  3670. if (dp_tx_comp_loop_pkt_limit_hit(soc, count))
  3671. break;
  3672. }
  3673. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  3674. /* Process the reaped descriptors */
  3675. if (head_desc)
  3676. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  3677. if (dp_tx_comp_enable_eol_data_check(soc)) {
  3678. if (num_processed >= quota)
  3679. force_break = true;
  3680. if (!force_break &&
  3681. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  3682. hal_ring_hdl)) {
  3683. DP_STATS_INC(soc, tx.hp_oos2, 1);
  3684. if (!hif_exec_should_yield(soc->hif_handle,
  3685. int_ctx->dp_intr_id))
  3686. goto more_data;
  3687. }
  3688. }
  3689. DP_TX_HIST_STATS_PER_PDEV();
  3690. return num_processed;
  3691. }
  3692. #ifdef FEATURE_WLAN_TDLS
  3693. qdf_nbuf_t dp_tx_non_std(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3694. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  3695. {
  3696. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3697. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3698. DP_MOD_ID_TDLS);
  3699. if (!vdev) {
  3700. dp_err("vdev handle for id %d is NULL", vdev_id);
  3701. return NULL;
  3702. }
  3703. if (tx_spec & OL_TX_SPEC_NO_FREE)
  3704. vdev->is_tdls_frame = true;
  3705. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  3706. return dp_tx_send(soc_hdl, vdev_id, msdu_list);
  3707. }
  3708. #endif
  3709. static void dp_tx_vdev_update_feature_flags(struct dp_vdev *vdev)
  3710. {
  3711. struct wlan_cfg_dp_soc_ctxt *cfg;
  3712. struct dp_soc *soc;
  3713. soc = vdev->pdev->soc;
  3714. if (!soc)
  3715. return;
  3716. cfg = soc->wlan_cfg_ctx;
  3717. if (!cfg)
  3718. return;
  3719. if (vdev->opmode == wlan_op_mode_ndi)
  3720. vdev->csum_enabled = wlan_cfg_get_nan_checksum_offload(cfg);
  3721. else if ((vdev->subtype == wlan_op_subtype_p2p_device) ||
  3722. (vdev->subtype == wlan_op_subtype_p2p_cli) ||
  3723. (vdev->subtype == wlan_op_subtype_p2p_go))
  3724. vdev->csum_enabled = wlan_cfg_get_p2p_checksum_offload(cfg);
  3725. else
  3726. vdev->csum_enabled = wlan_cfg_get_checksum_offload(cfg);
  3727. }
  3728. /**
  3729. * dp_tx_vdev_attach() - attach vdev to dp tx
  3730. * @vdev: virtual device instance
  3731. *
  3732. * Return: QDF_STATUS_SUCCESS: success
  3733. * QDF_STATUS_E_RESOURCES: Error return
  3734. */
  3735. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  3736. {
  3737. int pdev_id;
  3738. /*
  3739. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  3740. */
  3741. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  3742. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  3743. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  3744. vdev->vdev_id);
  3745. pdev_id =
  3746. dp_get_target_pdev_id_for_host_pdev_id(vdev->pdev->soc,
  3747. vdev->pdev->pdev_id);
  3748. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata, pdev_id);
  3749. /*
  3750. * Set HTT Extension Valid bit to 0 by default
  3751. */
  3752. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  3753. dp_tx_vdev_update_search_flags(vdev);
  3754. dp_tx_vdev_update_feature_flags(vdev);
  3755. return QDF_STATUS_SUCCESS;
  3756. }
  3757. #ifndef FEATURE_WDS
  3758. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  3759. {
  3760. return false;
  3761. }
  3762. #endif
  3763. /**
  3764. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  3765. * @vdev: virtual device instance
  3766. *
  3767. * Return: void
  3768. *
  3769. */
  3770. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  3771. {
  3772. struct dp_soc *soc = vdev->pdev->soc;
  3773. /*
  3774. * Enable both AddrY (SA based search) and AddrX (Da based search)
  3775. * for TDLS link
  3776. *
  3777. * Enable AddrY (SA based search) only for non-WDS STA and
  3778. * ProxySTA VAP (in HKv1) modes.
  3779. *
  3780. * In all other VAP modes, only DA based search should be
  3781. * enabled
  3782. */
  3783. if (vdev->opmode == wlan_op_mode_sta &&
  3784. vdev->tdls_link_connected)
  3785. vdev->hal_desc_addr_search_flags =
  3786. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  3787. else if ((vdev->opmode == wlan_op_mode_sta) &&
  3788. !dp_tx_da_search_override(vdev))
  3789. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  3790. else
  3791. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  3792. /* Set search type only when peer map v2 messaging is enabled
  3793. * as we will have the search index (AST hash) only when v2 is
  3794. * enabled
  3795. */
  3796. if (soc->is_peer_map_unmap_v2 && vdev->opmode == wlan_op_mode_sta)
  3797. vdev->search_type = HAL_TX_ADDR_INDEX_SEARCH;
  3798. else
  3799. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  3800. }
  3801. static inline bool
  3802. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  3803. struct dp_vdev *vdev,
  3804. struct dp_tx_desc_s *tx_desc)
  3805. {
  3806. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  3807. return false;
  3808. /*
  3809. * if vdev is given, then only check whether desc
  3810. * vdev match. if vdev is NULL, then check whether
  3811. * desc pdev match.
  3812. */
  3813. return vdev ? (tx_desc->vdev_id == vdev->vdev_id) :
  3814. (tx_desc->pdev == pdev);
  3815. }
  3816. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3817. /**
  3818. * dp_tx_desc_flush() - release resources associated
  3819. * to TX Desc
  3820. *
  3821. * @dp_pdev: Handle to DP pdev structure
  3822. * @vdev: virtual device instance
  3823. * NULL: no specific Vdev is required and check all allcated TX desc
  3824. * on this pdev.
  3825. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  3826. *
  3827. * @force_free:
  3828. * true: flush the TX desc.
  3829. * false: only reset the Vdev in each allocated TX desc
  3830. * that associated to current Vdev.
  3831. *
  3832. * This function will go through the TX desc pool to flush
  3833. * the outstanding TX data or reset Vdev to NULL in associated TX
  3834. * Desc.
  3835. */
  3836. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  3837. bool force_free)
  3838. {
  3839. uint8_t i;
  3840. uint32_t j;
  3841. uint32_t num_desc, page_id, offset;
  3842. uint16_t num_desc_per_page;
  3843. struct dp_soc *soc = pdev->soc;
  3844. struct dp_tx_desc_s *tx_desc = NULL;
  3845. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3846. if (!vdev && !force_free) {
  3847. dp_err("Reset TX desc vdev, Vdev param is required!");
  3848. return;
  3849. }
  3850. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  3851. tx_desc_pool = &soc->tx_desc[i];
  3852. if (!(tx_desc_pool->pool_size) ||
  3853. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  3854. !(tx_desc_pool->desc_pages.cacheable_pages))
  3855. continue;
  3856. /*
  3857. * Add flow pool lock protection in case pool is freed
  3858. * due to all tx_desc is recycled when handle TX completion.
  3859. * this is not necessary when do force flush as:
  3860. * a. double lock will happen if dp_tx_desc_release is
  3861. * also trying to acquire it.
  3862. * b. dp interrupt has been disabled before do force TX desc
  3863. * flush in dp_pdev_deinit().
  3864. */
  3865. if (!force_free)
  3866. qdf_spin_lock_bh(&tx_desc_pool->flow_pool_lock);
  3867. num_desc = tx_desc_pool->pool_size;
  3868. num_desc_per_page =
  3869. tx_desc_pool->desc_pages.num_element_per_page;
  3870. for (j = 0; j < num_desc; j++) {
  3871. page_id = j / num_desc_per_page;
  3872. offset = j % num_desc_per_page;
  3873. if (qdf_unlikely(!(tx_desc_pool->
  3874. desc_pages.cacheable_pages)))
  3875. break;
  3876. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3877. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  3878. /*
  3879. * Free TX desc if force free is
  3880. * required, otherwise only reset vdev
  3881. * in this TX desc.
  3882. */
  3883. if (force_free) {
  3884. dp_tx_comp_free_buf(soc, tx_desc);
  3885. dp_tx_desc_release(tx_desc, i);
  3886. } else {
  3887. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  3888. }
  3889. }
  3890. }
  3891. if (!force_free)
  3892. qdf_spin_unlock_bh(&tx_desc_pool->flow_pool_lock);
  3893. }
  3894. }
  3895. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3896. /**
  3897. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  3898. *
  3899. * @soc: Handle to DP soc structure
  3900. * @tx_desc: pointer of one TX desc
  3901. * @desc_pool_id: TX Desc pool id
  3902. */
  3903. static inline void
  3904. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  3905. uint8_t desc_pool_id)
  3906. {
  3907. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  3908. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  3909. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  3910. }
  3911. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  3912. bool force_free)
  3913. {
  3914. uint8_t i, num_pool;
  3915. uint32_t j;
  3916. uint32_t num_desc, page_id, offset;
  3917. uint16_t num_desc_per_page;
  3918. struct dp_soc *soc = pdev->soc;
  3919. struct dp_tx_desc_s *tx_desc = NULL;
  3920. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3921. if (!vdev && !force_free) {
  3922. dp_err("Reset TX desc vdev, Vdev param is required!");
  3923. return;
  3924. }
  3925. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3926. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3927. for (i = 0; i < num_pool; i++) {
  3928. tx_desc_pool = &soc->tx_desc[i];
  3929. if (!tx_desc_pool->desc_pages.cacheable_pages)
  3930. continue;
  3931. num_desc_per_page =
  3932. tx_desc_pool->desc_pages.num_element_per_page;
  3933. for (j = 0; j < num_desc; j++) {
  3934. page_id = j / num_desc_per_page;
  3935. offset = j % num_desc_per_page;
  3936. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3937. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  3938. if (force_free) {
  3939. dp_tx_comp_free_buf(soc, tx_desc);
  3940. dp_tx_desc_release(tx_desc, i);
  3941. } else {
  3942. dp_tx_desc_reset_vdev(soc, tx_desc,
  3943. i);
  3944. }
  3945. }
  3946. }
  3947. }
  3948. }
  3949. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3950. /**
  3951. * dp_tx_vdev_detach() - detach vdev from dp tx
  3952. * @vdev: virtual device instance
  3953. *
  3954. * Return: QDF_STATUS_SUCCESS: success
  3955. * QDF_STATUS_E_RESOURCES: Error return
  3956. */
  3957. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  3958. {
  3959. struct dp_pdev *pdev = vdev->pdev;
  3960. /* Reset TX desc associated to this Vdev as NULL */
  3961. dp_tx_desc_flush(pdev, vdev, false);
  3962. dp_tx_vdev_multipass_deinit(vdev);
  3963. return QDF_STATUS_SUCCESS;
  3964. }
  3965. /**
  3966. * dp_tx_pdev_attach() - attach pdev to dp tx
  3967. * @pdev: physical device instance
  3968. *
  3969. * Return: QDF_STATUS_SUCCESS: success
  3970. * QDF_STATUS_E_RESOURCES: Error return
  3971. */
  3972. QDF_STATUS dp_tx_pdev_init(struct dp_pdev *pdev)
  3973. {
  3974. struct dp_soc *soc = pdev->soc;
  3975. /* Initialize Flow control counters */
  3976. qdf_atomic_init(&pdev->num_tx_outstanding);
  3977. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3978. /* Initialize descriptors in TCL Ring */
  3979. hal_tx_init_data_ring(soc->hal_soc,
  3980. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  3981. }
  3982. return QDF_STATUS_SUCCESS;
  3983. }
  3984. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3985. /* Pools will be allocated dynamically */
  3986. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3987. int num_desc)
  3988. {
  3989. uint8_t i;
  3990. for (i = 0; i < num_pool; i++) {
  3991. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  3992. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  3993. }
  3994. return QDF_STATUS_SUCCESS;
  3995. }
  3996. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  3997. int num_desc)
  3998. {
  3999. return QDF_STATUS_SUCCESS;
  4000. }
  4001. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  4002. {
  4003. }
  4004. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  4005. {
  4006. uint8_t i;
  4007. for (i = 0; i < num_pool; i++)
  4008. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  4009. }
  4010. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  4011. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  4012. int num_desc)
  4013. {
  4014. uint8_t i, count;
  4015. /* Allocate software Tx descriptor pools */
  4016. for (i = 0; i < num_pool; i++) {
  4017. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  4018. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4019. FL("Tx Desc Pool alloc %d failed %pK"),
  4020. i, soc);
  4021. goto fail;
  4022. }
  4023. }
  4024. return QDF_STATUS_SUCCESS;
  4025. fail:
  4026. for (count = 0; count < i; count++)
  4027. dp_tx_desc_pool_free(soc, count);
  4028. return QDF_STATUS_E_NOMEM;
  4029. }
  4030. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  4031. int num_desc)
  4032. {
  4033. uint8_t i;
  4034. for (i = 0; i < num_pool; i++) {
  4035. if (dp_tx_desc_pool_init(soc, i, num_desc)) {
  4036. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4037. FL("Tx Desc Pool init %d failed %pK"),
  4038. i, soc);
  4039. return QDF_STATUS_E_NOMEM;
  4040. }
  4041. }
  4042. return QDF_STATUS_SUCCESS;
  4043. }
  4044. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  4045. {
  4046. uint8_t i;
  4047. for (i = 0; i < num_pool; i++)
  4048. dp_tx_desc_pool_deinit(soc, i);
  4049. }
  4050. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  4051. {
  4052. uint8_t i;
  4053. for (i = 0; i < num_pool; i++)
  4054. dp_tx_desc_pool_free(soc, i);
  4055. }
  4056. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  4057. /**
  4058. * dp_tx_tso_cmn_desc_pool_deinit() - de-initialize TSO descriptors
  4059. * @soc: core txrx main context
  4060. * @num_pool: number of pools
  4061. *
  4062. */
  4063. void dp_tx_tso_cmn_desc_pool_deinit(struct dp_soc *soc, uint8_t num_pool)
  4064. {
  4065. dp_tx_tso_desc_pool_deinit(soc, num_pool);
  4066. dp_tx_tso_num_seg_pool_deinit(soc, num_pool);
  4067. }
  4068. /**
  4069. * dp_tx_tso_cmn_desc_pool_free() - free TSO descriptors
  4070. * @soc: core txrx main context
  4071. * @num_pool: number of pools
  4072. *
  4073. */
  4074. void dp_tx_tso_cmn_desc_pool_free(struct dp_soc *soc, uint8_t num_pool)
  4075. {
  4076. dp_tx_tso_desc_pool_free(soc, num_pool);
  4077. dp_tx_tso_num_seg_pool_free(soc, num_pool);
  4078. }
  4079. /**
  4080. * dp_soc_tx_desc_sw_pools_free() - free all TX descriptors
  4081. * @soc: core txrx main context
  4082. *
  4083. * This function frees all tx related descriptors as below
  4084. * 1. Regular TX descriptors (static pools)
  4085. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  4086. * 3. TSO descriptors
  4087. *
  4088. */
  4089. void dp_soc_tx_desc_sw_pools_free(struct dp_soc *soc)
  4090. {
  4091. uint8_t num_pool;
  4092. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4093. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  4094. dp_tx_ext_desc_pool_free(soc, num_pool);
  4095. dp_tx_delete_static_pools(soc, num_pool);
  4096. }
  4097. /**
  4098. * dp_soc_tx_desc_sw_pools_deinit() - de-initialize all TX descriptors
  4099. * @soc: core txrx main context
  4100. *
  4101. * This function de-initializes all tx related descriptors as below
  4102. * 1. Regular TX descriptors (static pools)
  4103. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  4104. * 3. TSO descriptors
  4105. *
  4106. */
  4107. void dp_soc_tx_desc_sw_pools_deinit(struct dp_soc *soc)
  4108. {
  4109. uint8_t num_pool;
  4110. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4111. dp_tx_flow_control_deinit(soc);
  4112. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  4113. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  4114. dp_tx_deinit_static_pools(soc, num_pool);
  4115. }
  4116. /**
  4117. * dp_tso_attach() - TSO attach handler
  4118. * @txrx_soc: Opaque Dp handle
  4119. *
  4120. * Reserve TSO descriptor buffers
  4121. *
  4122. * Return: QDF_STATUS_E_FAILURE on failure or
  4123. * QDF_STATUS_SUCCESS on success
  4124. */
  4125. QDF_STATUS dp_tx_tso_cmn_desc_pool_alloc(struct dp_soc *soc,
  4126. uint8_t num_pool,
  4127. uint16_t num_desc)
  4128. {
  4129. if (dp_tx_tso_desc_pool_alloc(soc, num_pool, num_desc)) {
  4130. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  4131. return QDF_STATUS_E_FAILURE;
  4132. }
  4133. if (dp_tx_tso_num_seg_pool_alloc(soc, num_pool, num_desc)) {
  4134. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  4135. num_pool, soc);
  4136. return QDF_STATUS_E_FAILURE;
  4137. }
  4138. return QDF_STATUS_SUCCESS;
  4139. }
  4140. /**
  4141. * dp_tx_tso_cmn_desc_pool_init() - TSO cmn desc pool init
  4142. * @soc: DP soc handle
  4143. * @num_pool: Number of pools
  4144. * @num_desc: Number of descriptors
  4145. *
  4146. * Initialize TSO descriptor pools
  4147. *
  4148. * Return: QDF_STATUS_E_FAILURE on failure or
  4149. * QDF_STATUS_SUCCESS on success
  4150. */
  4151. QDF_STATUS dp_tx_tso_cmn_desc_pool_init(struct dp_soc *soc,
  4152. uint8_t num_pool,
  4153. uint16_t num_desc)
  4154. {
  4155. if (dp_tx_tso_desc_pool_init(soc, num_pool, num_desc)) {
  4156. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  4157. return QDF_STATUS_E_FAILURE;
  4158. }
  4159. if (dp_tx_tso_num_seg_pool_init(soc, num_pool, num_desc)) {
  4160. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  4161. num_pool, soc);
  4162. return QDF_STATUS_E_FAILURE;
  4163. }
  4164. return QDF_STATUS_SUCCESS;
  4165. }
  4166. /**
  4167. * dp_soc_tx_desc_sw_pools_alloc() - Allocate tx descriptor pool memory
  4168. * @soc: core txrx main context
  4169. *
  4170. * This function allocates memory for following descriptor pools
  4171. * 1. regular sw tx descriptor pools (static pools)
  4172. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  4173. * 3. TSO descriptor pools
  4174. *
  4175. * Return: QDF_STATUS_SUCCESS: success
  4176. * QDF_STATUS_E_RESOURCES: Error return
  4177. */
  4178. QDF_STATUS dp_soc_tx_desc_sw_pools_alloc(struct dp_soc *soc)
  4179. {
  4180. uint8_t num_pool;
  4181. uint32_t num_desc;
  4182. uint32_t num_ext_desc;
  4183. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4184. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4185. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4186. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4187. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  4188. __func__, num_pool, num_desc);
  4189. if ((num_pool > MAX_TXDESC_POOLS) ||
  4190. (num_desc > WLAN_CFG_NUM_TX_DESC_MAX))
  4191. goto fail1;
  4192. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  4193. goto fail1;
  4194. if (dp_tx_ext_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4195. goto fail2;
  4196. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  4197. return QDF_STATUS_SUCCESS;
  4198. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4199. goto fail3;
  4200. return QDF_STATUS_SUCCESS;
  4201. fail3:
  4202. dp_tx_ext_desc_pool_free(soc, num_pool);
  4203. fail2:
  4204. dp_tx_delete_static_pools(soc, num_pool);
  4205. fail1:
  4206. return QDF_STATUS_E_RESOURCES;
  4207. }
  4208. /**
  4209. * dp_soc_tx_desc_sw_pools_init() - Initialise TX descriptor pools
  4210. * @soc: core txrx main context
  4211. *
  4212. * This function initializes the following TX descriptor pools
  4213. * 1. regular sw tx descriptor pools (static pools)
  4214. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  4215. * 3. TSO descriptor pools
  4216. *
  4217. * Return: QDF_STATUS_SUCCESS: success
  4218. * QDF_STATUS_E_RESOURCES: Error return
  4219. */
  4220. QDF_STATUS dp_soc_tx_desc_sw_pools_init(struct dp_soc *soc)
  4221. {
  4222. uint8_t num_pool;
  4223. uint32_t num_desc;
  4224. uint32_t num_ext_desc;
  4225. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4226. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4227. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4228. if (dp_tx_init_static_pools(soc, num_pool, num_desc))
  4229. goto fail1;
  4230. if (dp_tx_ext_desc_pool_init(soc, num_pool, num_ext_desc))
  4231. goto fail2;
  4232. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  4233. return QDF_STATUS_SUCCESS;
  4234. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  4235. goto fail3;
  4236. dp_tx_flow_control_init(soc);
  4237. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  4238. return QDF_STATUS_SUCCESS;
  4239. fail3:
  4240. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  4241. fail2:
  4242. dp_tx_deinit_static_pools(soc, num_pool);
  4243. fail1:
  4244. return QDF_STATUS_E_RESOURCES;
  4245. }
  4246. /**
  4247. * dp_tso_soc_attach() - Allocate and initialize TSO descriptors
  4248. * @txrx_soc: dp soc handle
  4249. *
  4250. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  4251. * QDF_STATUS_E_FAILURE
  4252. */
  4253. QDF_STATUS dp_tso_soc_attach(struct cdp_soc_t *txrx_soc)
  4254. {
  4255. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  4256. uint8_t num_pool;
  4257. uint32_t num_desc;
  4258. uint32_t num_ext_desc;
  4259. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4260. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4261. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4262. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4263. return QDF_STATUS_E_FAILURE;
  4264. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  4265. return QDF_STATUS_E_FAILURE;
  4266. return QDF_STATUS_SUCCESS;
  4267. }
  4268. /**
  4269. * dp_tso_soc_detach() - de-initialize and free the TSO descriptors
  4270. * @txrx_soc: dp soc handle
  4271. *
  4272. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  4273. */
  4274. QDF_STATUS dp_tso_soc_detach(struct cdp_soc_t *txrx_soc)
  4275. {
  4276. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  4277. uint8_t num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4278. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  4279. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  4280. return QDF_STATUS_SUCCESS;
  4281. }