wcd938x.c 122 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/slab.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/device.h>
  9. #include <linux/delay.h>
  10. #include <linux/kernel.h>
  11. #include <linux/component.h>
  12. #include <sound/soc.h>
  13. #include <sound/tlv.h>
  14. #include <soc/soundwire.h>
  15. #include <linux/regmap.h>
  16. #include <sound/soc.h>
  17. #include <sound/soc-dapm.h>
  18. #include <asoc/wcdcal-hwdep.h>
  19. #include <asoc/msm-cdc-pinctrl.h>
  20. #include <asoc/msm-cdc-supply.h>
  21. #include <dt-bindings/sound/audio-codec-port-types.h>
  22. #include "wcd938x-registers.h"
  23. #include "wcd938x.h"
  24. #include "internal.h"
  25. #define NUM_SWRS_DT_PARAMS 5
  26. #define WCD938X_VARIANT_ENTRY_SIZE 32
  27. #define WCD938X_VERSION_1_0 1
  28. #define WCD938X_VERSION_ENTRY_SIZE 32
  29. #define EAR_RX_PATH_AUX 1
  30. #define ADC_MODE_VAL_HIFI 0x01
  31. #define ADC_MODE_VAL_LO_HIF 0x02
  32. #define ADC_MODE_VAL_NORMAL 0x03
  33. #define ADC_MODE_VAL_LP 0x05
  34. #define ADC_MODE_VAL_ULP1 0x09
  35. #define ADC_MODE_VAL_ULP2 0x0B
  36. #define NUM_ATTEMPTS 5
  37. #define DAPM_MICBIAS1_STANDALONE "MIC BIAS1 Standalone"
  38. #define DAPM_MICBIAS2_STANDALONE "MIC BIAS2 Standalone"
  39. #define DAPM_MICBIAS3_STANDALONE "MIC BIAS3 Standalone"
  40. #define DAPM_MICBIAS4_STANDALONE "MIC BIAS4 Standalone"
  41. #define WCD938X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  42. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  43. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
  44. SNDRV_PCM_RATE_384000)
  45. /* Fractional Rates */
  46. #define WCD938X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  47. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
  48. #define WCD938X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  49. SNDRV_PCM_FMTBIT_S24_LE |\
  50. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
  51. enum {
  52. CODEC_TX = 0,
  53. CODEC_RX,
  54. };
  55. enum {
  56. WCD_ADC1 = 0,
  57. WCD_ADC2,
  58. WCD_ADC3,
  59. WCD_ADC4,
  60. ALLOW_BUCK_DISABLE,
  61. HPH_COMP_DELAY,
  62. HPH_PA_DELAY,
  63. AMIC2_BCS_ENABLE,
  64. };
  65. enum {
  66. ADC_MODE_INVALID = 0,
  67. ADC_MODE_HIFI,
  68. ADC_MODE_LO_HIF,
  69. ADC_MODE_NORMAL,
  70. ADC_MODE_LP,
  71. ADC_MODE_ULP1,
  72. ADC_MODE_ULP2,
  73. };
  74. static u8 tx_mode_bit[] = {
  75. [ADC_MODE_INVALID] = 0x00,
  76. [ADC_MODE_HIFI] = 0x01,
  77. [ADC_MODE_LO_HIF] = 0x02,
  78. [ADC_MODE_NORMAL] = 0x04,
  79. [ADC_MODE_LP] = 0x08,
  80. [ADC_MODE_ULP1] = 0x10,
  81. [ADC_MODE_ULP2] = 0x20,
  82. };
  83. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  84. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  85. static int wcd938x_handle_post_irq(void *data);
  86. static int wcd938x_reset(struct device *dev);
  87. static int wcd938x_reset_low(struct device *dev);
  88. static const struct regmap_irq wcd938x_irqs[WCD938X_NUM_IRQS] = {
  89. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  90. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  91. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  92. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  93. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_SW_DET, 0, 0x10),
  94. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_OCP_INT, 0, 0x20),
  95. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_CNP_INT, 0, 0x40),
  96. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_OCP_INT, 0, 0x80),
  97. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_CNP_INT, 1, 0x01),
  98. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_CNP_INT, 1, 0x02),
  99. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_SCD_INT, 1, 0x04),
  100. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_CNP_INT, 1, 0x08),
  101. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_SCD_INT, 1, 0x10),
  102. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  103. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  104. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  105. REGMAP_IRQ_REG(WCD938X_IRQ_LDORT_SCD_INT, 2, 0x01),
  106. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  107. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  108. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  109. };
  110. static struct regmap_irq_chip wcd938x_regmap_irq_chip = {
  111. .name = "wcd938x",
  112. .irqs = wcd938x_irqs,
  113. .num_irqs = ARRAY_SIZE(wcd938x_irqs),
  114. .num_regs = 3,
  115. .status_base = WCD938X_DIGITAL_INTR_STATUS_0,
  116. .mask_base = WCD938X_DIGITAL_INTR_MASK_0,
  117. .type_base = WCD938X_DIGITAL_INTR_LEVEL_0,
  118. .ack_base = WCD938X_DIGITAL_INTR_CLEAR_0,
  119. .use_ack = 1,
  120. .runtime_pm = false,
  121. .handle_post_irq = wcd938x_handle_post_irq,
  122. .irq_drv_data = NULL,
  123. };
  124. static int wcd938x_handle_post_irq(void *data)
  125. {
  126. struct wcd938x_priv *wcd938x = data;
  127. u32 sts1 = 0, sts2 = 0, sts3 = 0;
  128. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_0, &sts1);
  129. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_1, &sts2);
  130. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_2, &sts3);
  131. wcd938x->tx_swr_dev->slave_irq_pending =
  132. ((sts1 || sts2 || sts3) ? true : false);
  133. return IRQ_HANDLED;
  134. }
  135. static int wcd938x_swr_slv_get_current_bank(struct swr_device *dev, u8 devnum)
  136. {
  137. int ret = 0;
  138. int bank = 0;
  139. ret = swr_read(dev, devnum, SWR_SCP_CONTROL, &bank, 1);
  140. if (ret)
  141. return -EINVAL;
  142. return ((bank & 0x40) ? 1: 0);
  143. }
  144. static int wcd938x_get_clk_rate(int mode)
  145. {
  146. int rate;
  147. switch (mode) {
  148. case ADC_MODE_ULP2:
  149. rate = SWR_CLK_RATE_0P6MHZ;
  150. break;
  151. case ADC_MODE_ULP1:
  152. rate = SWR_CLK_RATE_1P2MHZ;
  153. break;
  154. case ADC_MODE_LP:
  155. rate = SWR_CLK_RATE_4P8MHZ;
  156. break;
  157. case ADC_MODE_NORMAL:
  158. case ADC_MODE_LO_HIF:
  159. case ADC_MODE_HIFI:
  160. case ADC_MODE_INVALID:
  161. default:
  162. rate = SWR_CLK_RATE_9P6MHZ;
  163. break;
  164. }
  165. return rate;
  166. }
  167. static int wcd938x_set_swr_clk_rate(struct snd_soc_component *component,
  168. int rate, int bank)
  169. {
  170. u8 mask = (bank ? 0xF0 : 0x0F);
  171. u8 val = 0;
  172. switch (rate) {
  173. case SWR_CLK_RATE_0P6MHZ:
  174. val = (bank ? 0x60 : 0x06);
  175. break;
  176. case SWR_CLK_RATE_1P2MHZ:
  177. val = (bank ? 0x50 : 0x05);
  178. break;
  179. case SWR_CLK_RATE_2P4MHZ:
  180. val = (bank ? 0x30 : 0x03);
  181. break;
  182. case SWR_CLK_RATE_4P8MHZ:
  183. val = (bank ? 0x10 : 0x01);
  184. break;
  185. case SWR_CLK_RATE_9P6MHZ:
  186. default:
  187. val = 0x00;
  188. break;
  189. }
  190. snd_soc_component_update_bits(component,
  191. WCD938X_DIGITAL_SWR_TX_CLK_RATE,
  192. mask, val);
  193. return 0;
  194. }
  195. static int wcd938x_init_reg(struct snd_soc_component *component)
  196. {
  197. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x0E, 0x0E);
  198. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x80, 0x80);
  199. /* 1 msec delay as per HW requirement */
  200. usleep_range(1000, 1010);
  201. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x40, 0x40);
  202. /* 1 msec delay as per HW requirement */
  203. usleep_range(1000, 1010);
  204. snd_soc_component_update_bits(component, WCD938X_LDORXTX_CONFIG,
  205. 0x10, 0x00);
  206. snd_soc_component_update_bits(component, WCD938X_BIAS_VBG_FINE_ADJ,
  207. 0xF0, 0x80);
  208. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x80, 0x80);
  209. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x40);
  210. /* 10 msec delay as per HW requirement */
  211. usleep_range(10000, 10010);
  212. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x00);
  213. snd_soc_component_update_bits(component,
  214. WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL,
  215. 0xF0, 0x00);
  216. snd_soc_component_update_bits(component,
  217. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW,
  218. 0x1F, 0x15);
  219. snd_soc_component_update_bits(component,
  220. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW,
  221. 0x1F, 0x15);
  222. snd_soc_component_update_bits(component, WCD938X_HPH_REFBUFF_UHQA_CTL,
  223. 0xC0, 0x80);
  224. snd_soc_component_update_bits(component, WCD938X_DIGITAL_CDC_DMIC_CTL,
  225. 0x02, 0x02);
  226. snd_soc_component_update_bits(component,
  227. WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP,
  228. 0xFF, 0x14);
  229. snd_soc_component_update_bits(component,
  230. WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP,
  231. 0x1F, 0x08);
  232. snd_soc_component_update_bits(component,
  233. WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0xFF, 0x55);
  234. snd_soc_component_update_bits(component,
  235. WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0xFF, 0x44);
  236. snd_soc_component_update_bits(component,
  237. WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0xFF, 0x11);
  238. snd_soc_component_update_bits(component,
  239. WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0xFF, 0x00);
  240. snd_soc_component_update_bits(component,
  241. WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0xFF, 0x00);
  242. snd_soc_component_update_bits(component,
  243. WCD938X_MICB1_TEST_CTL_1, 0xE0, 0xE0);
  244. snd_soc_component_update_bits(component,
  245. WCD938X_MICB2_TEST_CTL_1, 0xE0, 0xE0);
  246. snd_soc_component_update_bits(component,
  247. WCD938X_MICB3_TEST_CTL_1, 0xE0, 0xE0);
  248. snd_soc_component_update_bits(component,
  249. WCD938X_MICB4_TEST_CTL_1, 0xE0, 0xE0);
  250. snd_soc_component_update_bits(component,
  251. WCD938X_TX_3_4_TEST_BLK_EN2, 0x01, 0x00);
  252. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x0E,
  253. ((snd_soc_component_read32(component,
  254. WCD938X_DIGITAL_EFUSE_REG_30) & 0x07) << 1));
  255. snd_soc_component_update_bits(component,
  256. WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0xC0);
  257. return 0;
  258. }
  259. static int wcd938x_set_port_params(struct snd_soc_component *component,
  260. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  261. u8 *ch_mask, u32 *ch_rate,
  262. u8 *port_type, u8 path)
  263. {
  264. int i, j;
  265. u8 num_ports = 0;
  266. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  267. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  268. switch (path) {
  269. case CODEC_RX:
  270. map = &wcd938x->rx_port_mapping;
  271. num_ports = wcd938x->num_rx_ports;
  272. break;
  273. case CODEC_TX:
  274. map = &wcd938x->tx_port_mapping;
  275. num_ports = wcd938x->num_tx_ports;
  276. break;
  277. default:
  278. dev_err(component->dev, "%s Invalid path selected %u\n",
  279. __func__, path);
  280. return -EINVAL;
  281. }
  282. for (i = 0; i <= num_ports; i++) {
  283. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  284. if ((*map)[i][j].slave_port_type == slv_prt_type)
  285. goto found;
  286. }
  287. }
  288. found:
  289. if (i > num_ports || j == MAX_CH_PER_PORT) {
  290. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  291. __func__, slv_prt_type);
  292. return -EINVAL;
  293. }
  294. *port_id = i;
  295. *num_ch = (*map)[i][j].num_ch;
  296. *ch_mask = (*map)[i][j].ch_mask;
  297. *ch_rate = (*map)[i][j].ch_rate;
  298. *port_type = (*map)[i][j].master_port_type;
  299. return 0;
  300. }
  301. static int wcd938x_parse_port_mapping(struct device *dev,
  302. char *prop, u8 path)
  303. {
  304. u32 *dt_array, map_size, map_length;
  305. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  306. u32 slave_port_type, master_port_type;
  307. u32 i, ch_iter = 0;
  308. int ret = 0;
  309. u8 *num_ports = NULL;
  310. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  311. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  312. switch (path) {
  313. case CODEC_RX:
  314. map = &wcd938x->rx_port_mapping;
  315. num_ports = &wcd938x->num_rx_ports;
  316. break;
  317. case CODEC_TX:
  318. map = &wcd938x->tx_port_mapping;
  319. num_ports = &wcd938x->num_tx_ports;
  320. break;
  321. default:
  322. dev_err(dev, "%s Invalid path selected %u\n",
  323. __func__, path);
  324. return -EINVAL;
  325. }
  326. if (!of_find_property(dev->of_node, prop,
  327. &map_size)) {
  328. dev_err(dev, "missing port mapping prop %s\n", prop);
  329. ret = -EINVAL;
  330. goto err_port_map;
  331. }
  332. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  333. dt_array = kzalloc(map_size, GFP_KERNEL);
  334. if (!dt_array) {
  335. ret = -ENOMEM;
  336. goto err_alloc;
  337. }
  338. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  339. NUM_SWRS_DT_PARAMS * map_length);
  340. if (ret) {
  341. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  342. __func__, prop);
  343. goto err_pdata_fail;
  344. }
  345. for (i = 0; i < map_length; i++) {
  346. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  347. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  348. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  349. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  350. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  351. if (port_num != old_port_num)
  352. ch_iter = 0;
  353. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  354. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  355. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  356. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  357. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  358. old_port_num = port_num;
  359. }
  360. *num_ports = port_num;
  361. kfree(dt_array);
  362. return 0;
  363. err_pdata_fail:
  364. kfree(dt_array);
  365. err_alloc:
  366. err_port_map:
  367. return ret;
  368. }
  369. static int wcd938x_tx_connect_port(struct snd_soc_component *component,
  370. u8 slv_port_type, int clk_rate,
  371. u8 enable)
  372. {
  373. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  374. u8 port_id, num_ch, ch_mask;
  375. u8 ch_type = 0;
  376. u32 ch_rate;
  377. int slave_ch_idx;
  378. u8 num_port = 1;
  379. int ret = 0;
  380. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  381. &num_ch, &ch_mask, &ch_rate,
  382. &ch_type, CODEC_TX);
  383. if (ret)
  384. return ret;
  385. if (clk_rate)
  386. ch_rate = clk_rate;
  387. slave_ch_idx = wcd938x_slave_get_slave_ch_val(slv_port_type);
  388. if (slave_ch_idx != -EINVAL)
  389. ch_type = wcd938x->tx_master_ch_map[slave_ch_idx];
  390. dev_dbg(component->dev, "%s slv_ch_idx: %d, mstr_ch_type: %d\n",
  391. __func__, slave_ch_idx, ch_type);
  392. if (enable)
  393. ret = swr_connect_port(wcd938x->tx_swr_dev, &port_id,
  394. num_port, &ch_mask, &ch_rate,
  395. &num_ch, &ch_type);
  396. else
  397. ret = swr_disconnect_port(wcd938x->tx_swr_dev, &port_id,
  398. num_port, &ch_mask, &ch_type);
  399. return ret;
  400. }
  401. static int wcd938x_rx_connect_port(struct snd_soc_component *component,
  402. u8 slv_port_type, u8 enable)
  403. {
  404. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  405. u8 port_id, num_ch, ch_mask, port_type;
  406. u32 ch_rate;
  407. u8 num_port = 1;
  408. int ret = 0;
  409. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  410. &num_ch, &ch_mask, &ch_rate,
  411. &port_type, CODEC_RX);
  412. if (ret)
  413. return ret;
  414. if (enable)
  415. ret = swr_connect_port(wcd938x->rx_swr_dev, &port_id,
  416. num_port, &ch_mask, &ch_rate,
  417. &num_ch, &port_type);
  418. else
  419. ret = swr_disconnect_port(wcd938x->rx_swr_dev, &port_id,
  420. num_port, &ch_mask, &port_type);
  421. return ret;
  422. }
  423. static int wcd938x_rx_clk_enable(struct snd_soc_component *component)
  424. {
  425. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  426. if (wcd938x->rx_clk_cnt == 0) {
  427. snd_soc_component_update_bits(component,
  428. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
  429. snd_soc_component_update_bits(component,
  430. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x01);
  431. snd_soc_component_update_bits(component,
  432. WCD938X_DIGITAL_CDC_RX0_CTL, 0x40, 0x00);
  433. snd_soc_component_update_bits(component,
  434. WCD938X_DIGITAL_CDC_RX1_CTL, 0x40, 0x00);
  435. snd_soc_component_update_bits(component,
  436. WCD938X_DIGITAL_CDC_RX2_CTL, 0x40, 0x00);
  437. snd_soc_component_update_bits(component,
  438. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
  439. snd_soc_component_update_bits(component,
  440. WCD938X_AUX_AUXPA, 0x10, 0x10);
  441. }
  442. wcd938x->rx_clk_cnt++;
  443. return 0;
  444. }
  445. static int wcd938x_rx_clk_disable(struct snd_soc_component *component)
  446. {
  447. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  448. wcd938x->rx_clk_cnt--;
  449. if (wcd938x->rx_clk_cnt == 0) {
  450. snd_soc_component_update_bits(component,
  451. WCD938X_ANA_RX_SUPPLIES, 0x40, 0x00);
  452. snd_soc_component_update_bits(component,
  453. WCD938X_ANA_RX_SUPPLIES, 0x80, 0x00);
  454. snd_soc_component_update_bits(component,
  455. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x00);
  456. snd_soc_component_update_bits(component,
  457. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x00);
  458. snd_soc_component_update_bits(component,
  459. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x00);
  460. }
  461. return 0;
  462. }
  463. /*
  464. * wcd938x_soc_get_mbhc: get wcd938x_mbhc handle of corresponding component
  465. * @component: handle to snd_soc_component *
  466. *
  467. * return wcd938x_mbhc handle or error code in case of failure
  468. */
  469. struct wcd938x_mbhc *wcd938x_soc_get_mbhc(struct snd_soc_component *component)
  470. {
  471. struct wcd938x_priv *wcd938x;
  472. if (!component) {
  473. pr_err("%s: Invalid params, NULL component\n", __func__);
  474. return NULL;
  475. }
  476. wcd938x = snd_soc_component_get_drvdata(component);
  477. if (!wcd938x) {
  478. pr_err("%s: wcd938x is NULL\n", __func__);
  479. return NULL;
  480. }
  481. return wcd938x->mbhc;
  482. }
  483. EXPORT_SYMBOL(wcd938x_soc_get_mbhc);
  484. static int wcd938x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  485. struct snd_kcontrol *kcontrol,
  486. int event)
  487. {
  488. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  489. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  490. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  491. w->name, event);
  492. switch (event) {
  493. case SND_SOC_DAPM_PRE_PMU:
  494. wcd938x_rx_clk_enable(component);
  495. snd_soc_component_update_bits(component,
  496. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  497. snd_soc_component_update_bits(component,
  498. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  499. snd_soc_component_update_bits(component,
  500. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  501. break;
  502. case SND_SOC_DAPM_POST_PMU:
  503. snd_soc_component_update_bits(component,
  504. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x0F, 0x02);
  505. if (wcd938x->comp1_enable) {
  506. snd_soc_component_update_bits(component,
  507. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x02);
  508. /* 5msec compander delay as per HW requirement */
  509. if (!wcd938x->comp2_enable ||
  510. (snd_soc_component_read32(component,
  511. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x01))
  512. usleep_range(5000, 5010);
  513. snd_soc_component_update_bits(component,
  514. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  515. } else {
  516. snd_soc_component_update_bits(component,
  517. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  518. 0x02, 0x00);
  519. snd_soc_component_update_bits(component,
  520. WCD938X_HPH_L_EN, 0x20, 0x20);
  521. }
  522. break;
  523. case SND_SOC_DAPM_POST_PMD:
  524. snd_soc_component_update_bits(component,
  525. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  526. 0x0F, 0x01);
  527. break;
  528. }
  529. return 0;
  530. }
  531. static int wcd938x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  532. struct snd_kcontrol *kcontrol,
  533. int event)
  534. {
  535. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  536. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  537. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  538. w->name, event);
  539. switch (event) {
  540. case SND_SOC_DAPM_PRE_PMU:
  541. wcd938x_rx_clk_enable(component);
  542. snd_soc_component_update_bits(component,
  543. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
  544. snd_soc_component_update_bits(component,
  545. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x08, 0x08);
  546. snd_soc_component_update_bits(component,
  547. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  548. break;
  549. case SND_SOC_DAPM_POST_PMU:
  550. snd_soc_component_update_bits(component,
  551. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x0F, 0x02);
  552. if (wcd938x->comp2_enable) {
  553. snd_soc_component_update_bits(component,
  554. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x01, 0x01);
  555. /* 5msec compander delay as per HW requirement */
  556. if (!wcd938x->comp1_enable ||
  557. (snd_soc_component_read32(component,
  558. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x02))
  559. usleep_range(5000, 5010);
  560. snd_soc_component_update_bits(component,
  561. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  562. } else {
  563. snd_soc_component_update_bits(component,
  564. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  565. 0x01, 0x00);
  566. snd_soc_component_update_bits(component,
  567. WCD938X_HPH_R_EN, 0x20, 0x20);
  568. }
  569. break;
  570. case SND_SOC_DAPM_POST_PMD:
  571. snd_soc_component_update_bits(component,
  572. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  573. 0x0F, 0x01);
  574. break;
  575. }
  576. return 0;
  577. }
  578. static int wcd938x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  579. struct snd_kcontrol *kcontrol,
  580. int event)
  581. {
  582. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  583. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  584. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  585. w->name, event);
  586. switch (event) {
  587. case SND_SOC_DAPM_PRE_PMU:
  588. wcd938x_rx_clk_enable(component);
  589. wcd938x->ear_rx_path =
  590. snd_soc_component_read32(
  591. component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
  592. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  593. snd_soc_component_update_bits(component,
  594. WCD938X_EAR_EAR_DAC_CON, 0x80, 0x00);
  595. snd_soc_component_update_bits(component,
  596. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x01);
  597. snd_soc_component_update_bits(component,
  598. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x04);
  599. snd_soc_component_update_bits(component,
  600. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  601. } else {
  602. snd_soc_component_update_bits(component,
  603. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  604. snd_soc_component_update_bits(component,
  605. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  606. if (wcd938x->comp1_enable)
  607. snd_soc_component_update_bits(component,
  608. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  609. 0x02, 0x02);
  610. }
  611. /* 5 msec delay as per HW requirement */
  612. usleep_range(5000, 5010);
  613. if (wcd938x->flyback_cur_det_disable == 0)
  614. snd_soc_component_update_bits(component,
  615. WCD938X_FLYBACK_EN,
  616. 0x04, 0x00);
  617. wcd938x->flyback_cur_det_disable++;
  618. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  619. WCD_CLSH_EVENT_PRE_DAC,
  620. WCD_CLSH_STATE_EAR,
  621. wcd938x->hph_mode);
  622. break;
  623. case SND_SOC_DAPM_POST_PMD:
  624. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  625. snd_soc_component_update_bits(component,
  626. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x00);
  627. snd_soc_component_update_bits(component,
  628. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  629. } else {
  630. snd_soc_component_update_bits(component,
  631. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x00);
  632. snd_soc_component_update_bits(component,
  633. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x00);
  634. if (wcd938x->comp1_enable)
  635. snd_soc_component_update_bits(component,
  636. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  637. 0x02, 0x00);
  638. }
  639. snd_soc_component_update_bits(component,
  640. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  641. snd_soc_component_update_bits(component,
  642. WCD938X_EAR_EAR_DAC_CON, 0x80, 0x80);
  643. break;
  644. };
  645. return 0;
  646. }
  647. static int wcd938x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  648. struct snd_kcontrol *kcontrol,
  649. int event)
  650. {
  651. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  652. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  653. int ret = 0;
  654. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  655. w->name, event);
  656. switch (event) {
  657. case SND_SOC_DAPM_PRE_PMU:
  658. wcd938x_rx_clk_enable(component);
  659. snd_soc_component_update_bits(component,
  660. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x04);
  661. snd_soc_component_update_bits(component,
  662. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x04);
  663. snd_soc_component_update_bits(component,
  664. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x01);
  665. if (wcd938x->flyback_cur_det_disable == 0)
  666. snd_soc_component_update_bits(component,
  667. WCD938X_FLYBACK_EN,
  668. 0x04, 0x00);
  669. wcd938x->flyback_cur_det_disable++;
  670. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  671. WCD_CLSH_EVENT_PRE_DAC,
  672. WCD_CLSH_STATE_AUX,
  673. wcd938x->hph_mode);
  674. break;
  675. case SND_SOC_DAPM_POST_PMD:
  676. snd_soc_component_update_bits(component,
  677. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x00);
  678. break;
  679. };
  680. return ret;
  681. }
  682. static int wcd938x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  683. struct snd_kcontrol *kcontrol,
  684. int event)
  685. {
  686. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  687. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  688. int ret = 0;
  689. int hph_mode = wcd938x->hph_mode;
  690. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  691. w->name, event);
  692. switch (event) {
  693. case SND_SOC_DAPM_PRE_PMU:
  694. if (wcd938x->ldoh)
  695. snd_soc_component_update_bits(component,
  696. WCD938X_LDOH_MODE,
  697. 0x80, 0x80);
  698. if (wcd938x->update_wcd_event)
  699. wcd938x->update_wcd_event(wcd938x->handle,
  700. WCD_BOLERO_EVT_RX_MUTE,
  701. (WCD_RX2 << 0x10 | 0x1));
  702. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  703. wcd938x->rx_swr_dev->dev_num,
  704. true);
  705. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  706. WCD_CLSH_EVENT_PRE_DAC,
  707. WCD_CLSH_STATE_HPHR,
  708. hph_mode);
  709. wcd_clsh_set_hph_mode(component, CLS_H_HIFI);
  710. if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
  711. hph_mode == CLS_H_ULP) {
  712. snd_soc_component_update_bits(component,
  713. WCD938X_HPH_REFBUFF_LP_CTL, 0x01, 0x01);
  714. }
  715. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  716. 0x10, 0x10);
  717. wcd_clsh_set_hph_mode(component, hph_mode);
  718. /* 100 usec delay as per HW requirement */
  719. usleep_range(100, 110);
  720. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  721. snd_soc_component_update_bits(component,
  722. WCD938X_DIGITAL_PDM_WD_CTL1, 0x07, 0x03);
  723. break;
  724. case SND_SOC_DAPM_POST_PMU:
  725. /*
  726. * 7ms sleep is required if compander is enabled as per
  727. * HW requirement. If compander is disabled, then
  728. * 20ms delay is required.
  729. */
  730. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  731. if (!wcd938x->comp2_enable)
  732. usleep_range(20000, 20100);
  733. else
  734. usleep_range(7000, 7100);
  735. if (hph_mode == CLS_H_LP ||
  736. hph_mode == CLS_H_LOHIFI ||
  737. hph_mode == CLS_H_ULP)
  738. snd_soc_component_update_bits(component,
  739. WCD938X_HPH_REFBUFF_LP_CTL, 0x01,
  740. 0x00);
  741. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  742. }
  743. snd_soc_component_update_bits(component,
  744. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  745. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  746. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  747. snd_soc_component_update_bits(component,
  748. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  749. if (wcd938x->update_wcd_event)
  750. wcd938x->update_wcd_event(wcd938x->handle,
  751. WCD_BOLERO_EVT_RX_MUTE,
  752. (WCD_RX2 << 0x10));
  753. wcd_enable_irq(&wcd938x->irq_info,
  754. WCD938X_IRQ_HPHR_PDM_WD_INT);
  755. break;
  756. case SND_SOC_DAPM_PRE_PMD:
  757. if (wcd938x->update_wcd_event)
  758. wcd938x->update_wcd_event(wcd938x->handle,
  759. WCD_BOLERO_EVT_RX_MUTE,
  760. (WCD_RX2 << 0x10 | 0x1));
  761. wcd_disable_irq(&wcd938x->irq_info,
  762. WCD938X_IRQ_HPHR_PDM_WD_INT);
  763. if (wcd938x->update_wcd_event && wcd938x->comp2_enable)
  764. wcd938x->update_wcd_event(wcd938x->handle,
  765. WCD_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  766. (WCD_RX2 << 0x10));
  767. /*
  768. * 7ms sleep is required if compander is enabled as per
  769. * HW requirement. If compander is disabled, then
  770. * 20ms delay is required.
  771. */
  772. if (!wcd938x->comp2_enable)
  773. usleep_range(20000, 20100);
  774. else
  775. usleep_range(7000, 7100);
  776. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  777. 0x40, 0x00);
  778. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  779. WCD_EVENT_PRE_HPHR_PA_OFF,
  780. &wcd938x->mbhc->wcd_mbhc);
  781. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  782. break;
  783. case SND_SOC_DAPM_POST_PMD:
  784. /*
  785. * 7ms sleep is required if compander is enabled as per
  786. * HW requirement. If compander is disabled, then
  787. * 20ms delay is required.
  788. */
  789. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  790. if (!wcd938x->comp2_enable)
  791. usleep_range(20000, 20100);
  792. else
  793. usleep_range(7000, 7100);
  794. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  795. }
  796. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  797. WCD_EVENT_POST_HPHR_PA_OFF,
  798. &wcd938x->mbhc->wcd_mbhc);
  799. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  800. 0x10, 0x00);
  801. snd_soc_component_update_bits(component,
  802. WCD938X_DIGITAL_PDM_WD_CTL1, 0x07, 0x00);
  803. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  804. WCD_CLSH_EVENT_POST_PA,
  805. WCD_CLSH_STATE_HPHR,
  806. hph_mode);
  807. if (wcd938x->ldoh)
  808. snd_soc_component_update_bits(component,
  809. WCD938X_LDOH_MODE,
  810. 0x80, 0x00);
  811. break;
  812. };
  813. return ret;
  814. }
  815. static int wcd938x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  816. struct snd_kcontrol *kcontrol,
  817. int event)
  818. {
  819. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  820. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  821. int ret = 0;
  822. int hph_mode = wcd938x->hph_mode;
  823. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  824. w->name, event);
  825. switch (event) {
  826. case SND_SOC_DAPM_PRE_PMU:
  827. if (wcd938x->ldoh)
  828. snd_soc_component_update_bits(component,
  829. WCD938X_LDOH_MODE,
  830. 0x80, 0x80);
  831. if (wcd938x->update_wcd_event)
  832. wcd938x->update_wcd_event(wcd938x->handle,
  833. WCD_BOLERO_EVT_RX_MUTE,
  834. (WCD_RX1 << 0x10 | 0x01));
  835. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  836. wcd938x->rx_swr_dev->dev_num,
  837. true);
  838. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  839. WCD_CLSH_EVENT_PRE_DAC,
  840. WCD_CLSH_STATE_HPHL,
  841. hph_mode);
  842. wcd_clsh_set_hph_mode(component, CLS_H_HIFI);
  843. if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
  844. hph_mode == CLS_H_ULP) {
  845. snd_soc_component_update_bits(component,
  846. WCD938X_HPH_REFBUFF_LP_CTL, 0x01, 0x01);
  847. }
  848. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  849. 0x20, 0x20);
  850. wcd_clsh_set_hph_mode(component, hph_mode);
  851. /* 100 usec delay as per HW requirement */
  852. usleep_range(100, 110);
  853. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  854. snd_soc_component_update_bits(component,
  855. WCD938X_DIGITAL_PDM_WD_CTL0, 0x07, 0x03);
  856. break;
  857. case SND_SOC_DAPM_POST_PMU:
  858. /*
  859. * 7ms sleep is required if compander is enabled as per
  860. * HW requirement. If compander is disabled, then
  861. * 20ms delay is required.
  862. */
  863. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  864. if (!wcd938x->comp1_enable)
  865. usleep_range(20000, 20100);
  866. else
  867. usleep_range(7000, 7100);
  868. if (hph_mode == CLS_H_LP ||
  869. hph_mode == CLS_H_LOHIFI ||
  870. hph_mode == CLS_H_ULP)
  871. snd_soc_component_update_bits(component,
  872. WCD938X_HPH_REFBUFF_LP_CTL,
  873. 0x01, 0x00);
  874. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  875. }
  876. snd_soc_component_update_bits(component,
  877. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  878. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  879. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  880. snd_soc_component_update_bits(component,
  881. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  882. if (wcd938x->update_wcd_event)
  883. wcd938x->update_wcd_event(wcd938x->handle,
  884. WCD_BOLERO_EVT_RX_MUTE,
  885. (WCD_RX1 << 0x10));
  886. wcd_enable_irq(&wcd938x->irq_info,
  887. WCD938X_IRQ_HPHL_PDM_WD_INT);
  888. break;
  889. case SND_SOC_DAPM_PRE_PMD:
  890. if (wcd938x->update_wcd_event)
  891. wcd938x->update_wcd_event(wcd938x->handle,
  892. WCD_BOLERO_EVT_RX_MUTE,
  893. (WCD_RX1 << 0x10 | 0x1));
  894. wcd_disable_irq(&wcd938x->irq_info,
  895. WCD938X_IRQ_HPHL_PDM_WD_INT);
  896. if (wcd938x->update_wcd_event && wcd938x->comp1_enable)
  897. wcd938x->update_wcd_event(wcd938x->handle,
  898. WCD_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  899. (WCD_RX1 << 0x10));
  900. /*
  901. * 7ms sleep is required if compander is enabled as per
  902. * HW requirement. If compander is disabled, then
  903. * 20ms delay is required.
  904. */
  905. if (!wcd938x->comp1_enable)
  906. usleep_range(20000, 20100);
  907. else
  908. usleep_range(7000, 7100);
  909. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  910. 0x80, 0x00);
  911. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  912. WCD_EVENT_PRE_HPHL_PA_OFF,
  913. &wcd938x->mbhc->wcd_mbhc);
  914. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  915. break;
  916. case SND_SOC_DAPM_POST_PMD:
  917. /*
  918. * 7ms sleep is required if compander is enabled as per
  919. * HW requirement. If compander is disabled, then
  920. * 20ms delay is required.
  921. */
  922. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  923. if (!wcd938x->comp1_enable)
  924. usleep_range(21000, 21100);
  925. else
  926. usleep_range(7000, 7100);
  927. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  928. }
  929. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  930. WCD_EVENT_POST_HPHL_PA_OFF,
  931. &wcd938x->mbhc->wcd_mbhc);
  932. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  933. 0x20, 0x00);
  934. snd_soc_component_update_bits(component,
  935. WCD938X_DIGITAL_PDM_WD_CTL0, 0x07, 0x00);
  936. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  937. WCD_CLSH_EVENT_POST_PA,
  938. WCD_CLSH_STATE_HPHL,
  939. hph_mode);
  940. if (wcd938x->ldoh)
  941. snd_soc_component_update_bits(component,
  942. WCD938X_LDOH_MODE,
  943. 0x80, 0x00);
  944. break;
  945. };
  946. return ret;
  947. }
  948. static int wcd938x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  949. struct snd_kcontrol *kcontrol,
  950. int event)
  951. {
  952. struct snd_soc_component *component =
  953. snd_soc_dapm_to_component(w->dapm);
  954. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  955. int hph_mode = wcd938x->hph_mode;
  956. int ret = 0;
  957. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  958. w->name, event);
  959. switch (event) {
  960. case SND_SOC_DAPM_PRE_PMU:
  961. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  962. wcd938x->rx_swr_dev->dev_num,
  963. true);
  964. snd_soc_component_update_bits(component,
  965. WCD938X_DIGITAL_PDM_WD_CTL2, 0x01, 0x01);
  966. break;
  967. case SND_SOC_DAPM_POST_PMU:
  968. /* 1 msec delay as per HW requirement */
  969. usleep_range(1000, 1010);
  970. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  971. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  972. snd_soc_component_update_bits(component,
  973. WCD938X_ANA_RX_SUPPLIES,
  974. 0x02, 0x02);
  975. if (wcd938x->update_wcd_event)
  976. wcd938x->update_wcd_event(wcd938x->handle,
  977. WCD_BOLERO_EVT_RX_MUTE,
  978. (WCD_RX3 << 0x10));
  979. wcd_enable_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT);
  980. break;
  981. case SND_SOC_DAPM_PRE_PMD:
  982. wcd_disable_irq(&wcd938x->irq_info,
  983. WCD938X_IRQ_AUX_PDM_WD_INT);
  984. if (wcd938x->update_wcd_event)
  985. wcd938x->update_wcd_event(wcd938x->handle,
  986. WCD_BOLERO_EVT_RX_MUTE,
  987. (WCD_RX3 << 0x10 | 0x1));
  988. break;
  989. case SND_SOC_DAPM_POST_PMD:
  990. /* 1 msec delay as per HW requirement */
  991. usleep_range(1000, 1010);
  992. snd_soc_component_update_bits(component,
  993. WCD938X_DIGITAL_PDM_WD_CTL2, 0x01, 0x00);
  994. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  995. WCD_CLSH_EVENT_POST_PA,
  996. WCD_CLSH_STATE_AUX,
  997. hph_mode);
  998. wcd938x->flyback_cur_det_disable--;
  999. if (wcd938x->flyback_cur_det_disable == 0)
  1000. snd_soc_component_update_bits(component,
  1001. WCD938X_FLYBACK_EN,
  1002. 0x04, 0x04);
  1003. break;
  1004. };
  1005. return ret;
  1006. }
  1007. static int wcd938x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  1008. struct snd_kcontrol *kcontrol,
  1009. int event)
  1010. {
  1011. struct snd_soc_component *component =
  1012. snd_soc_dapm_to_component(w->dapm);
  1013. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1014. int hph_mode = wcd938x->hph_mode;
  1015. int ret = 0;
  1016. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1017. w->name, event);
  1018. switch (event) {
  1019. case SND_SOC_DAPM_PRE_PMU:
  1020. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  1021. wcd938x->rx_swr_dev->dev_num,
  1022. true);
  1023. /*
  1024. * Enable watchdog interrupt for HPHL or AUX
  1025. * depending on mux value
  1026. */
  1027. wcd938x->ear_rx_path =
  1028. snd_soc_component_read32(
  1029. component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
  1030. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  1031. snd_soc_component_update_bits(component,
  1032. WCD938X_DIGITAL_PDM_WD_CTL2,
  1033. 0x01, 0x01);
  1034. else
  1035. snd_soc_component_update_bits(component,
  1036. WCD938X_DIGITAL_PDM_WD_CTL0,
  1037. 0x07, 0x03);
  1038. if (!wcd938x->comp1_enable)
  1039. snd_soc_component_update_bits(component,
  1040. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  1041. break;
  1042. case SND_SOC_DAPM_POST_PMU:
  1043. /* 6 msec delay as per HW requirement */
  1044. usleep_range(6000, 6010);
  1045. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  1046. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  1047. snd_soc_component_update_bits(component,
  1048. WCD938X_ANA_RX_SUPPLIES,
  1049. 0x02, 0x02);
  1050. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  1051. if (wcd938x->update_wcd_event)
  1052. wcd938x->update_wcd_event(wcd938x->handle,
  1053. WCD_BOLERO_EVT_RX_MUTE,
  1054. (WCD_RX3 << 0x10));
  1055. wcd_enable_irq(&wcd938x->irq_info,
  1056. WCD938X_IRQ_AUX_PDM_WD_INT);
  1057. } else {
  1058. if (wcd938x->update_wcd_event)
  1059. wcd938x->update_wcd_event(wcd938x->handle,
  1060. WCD_BOLERO_EVT_RX_MUTE,
  1061. (WCD_RX1 << 0x10));
  1062. wcd_enable_irq(&wcd938x->irq_info,
  1063. WCD938X_IRQ_HPHL_PDM_WD_INT);
  1064. }
  1065. break;
  1066. case SND_SOC_DAPM_PRE_PMD:
  1067. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  1068. wcd_disable_irq(&wcd938x->irq_info,
  1069. WCD938X_IRQ_AUX_PDM_WD_INT);
  1070. if (wcd938x->update_wcd_event)
  1071. wcd938x->update_wcd_event(wcd938x->handle,
  1072. WCD_BOLERO_EVT_RX_MUTE,
  1073. (WCD_RX3 << 0x10 | 0x1));
  1074. } else {
  1075. wcd_disable_irq(&wcd938x->irq_info,
  1076. WCD938X_IRQ_HPHL_PDM_WD_INT);
  1077. if (wcd938x->update_wcd_event)
  1078. wcd938x->update_wcd_event(wcd938x->handle,
  1079. WCD_BOLERO_EVT_RX_MUTE,
  1080. (WCD_RX1 << 0x10 | 0x1));
  1081. }
  1082. break;
  1083. case SND_SOC_DAPM_POST_PMD:
  1084. if (!wcd938x->comp1_enable)
  1085. snd_soc_component_update_bits(component,
  1086. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  1087. /* 7 msec delay as per HW requirement */
  1088. usleep_range(7000, 7010);
  1089. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  1090. snd_soc_component_update_bits(component,
  1091. WCD938X_DIGITAL_PDM_WD_CTL2,
  1092. 0x01, 0x00);
  1093. else
  1094. snd_soc_component_update_bits(component,
  1095. WCD938X_DIGITAL_PDM_WD_CTL0,
  1096. 0x07, 0x00);
  1097. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  1098. WCD_CLSH_EVENT_POST_PA,
  1099. WCD_CLSH_STATE_EAR,
  1100. hph_mode);
  1101. wcd938x->flyback_cur_det_disable--;
  1102. if (wcd938x->flyback_cur_det_disable == 0)
  1103. snd_soc_component_update_bits(component,
  1104. WCD938X_FLYBACK_EN,
  1105. 0x04, 0x04);
  1106. break;
  1107. };
  1108. return ret;
  1109. }
  1110. static int wcd938x_enable_clsh(struct snd_soc_dapm_widget *w,
  1111. struct snd_kcontrol *kcontrol,
  1112. int event)
  1113. {
  1114. struct snd_soc_component *component =
  1115. snd_soc_dapm_to_component(w->dapm);
  1116. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1117. int mode = wcd938x->hph_mode;
  1118. int ret = 0;
  1119. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1120. w->name, event);
  1121. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  1122. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  1123. wcd938x_rx_connect_port(component, CLSH,
  1124. SND_SOC_DAPM_EVENT_ON(event));
  1125. }
  1126. if (SND_SOC_DAPM_EVENT_OFF(event))
  1127. ret = swr_slvdev_datapath_control(
  1128. wcd938x->rx_swr_dev,
  1129. wcd938x->rx_swr_dev->dev_num,
  1130. false);
  1131. return ret;
  1132. }
  1133. static int wcd938x_enable_rx1(struct snd_soc_dapm_widget *w,
  1134. struct snd_kcontrol *kcontrol,
  1135. int event)
  1136. {
  1137. struct snd_soc_component *component =
  1138. snd_soc_dapm_to_component(w->dapm);
  1139. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1140. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1141. w->name, event);
  1142. switch (event) {
  1143. case SND_SOC_DAPM_PRE_PMU:
  1144. wcd938x_rx_connect_port(component, HPH_L, true);
  1145. if (wcd938x->comp1_enable)
  1146. wcd938x_rx_connect_port(component, COMP_L, true);
  1147. break;
  1148. case SND_SOC_DAPM_POST_PMD:
  1149. wcd938x_rx_connect_port(component, HPH_L, false);
  1150. if (wcd938x->comp1_enable)
  1151. wcd938x_rx_connect_port(component, COMP_L, false);
  1152. wcd938x_rx_clk_disable(component);
  1153. snd_soc_component_update_bits(component,
  1154. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  1155. 0x01, 0x00);
  1156. break;
  1157. };
  1158. return 0;
  1159. }
  1160. static int wcd938x_enable_rx2(struct snd_soc_dapm_widget *w,
  1161. struct snd_kcontrol *kcontrol, int event)
  1162. {
  1163. struct snd_soc_component *component =
  1164. snd_soc_dapm_to_component(w->dapm);
  1165. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1166. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1167. w->name, event);
  1168. switch (event) {
  1169. case SND_SOC_DAPM_PRE_PMU:
  1170. wcd938x_rx_connect_port(component, HPH_R, true);
  1171. if (wcd938x->comp2_enable)
  1172. wcd938x_rx_connect_port(component, COMP_R, true);
  1173. break;
  1174. case SND_SOC_DAPM_POST_PMD:
  1175. wcd938x_rx_connect_port(component, HPH_R, false);
  1176. if (wcd938x->comp2_enable)
  1177. wcd938x_rx_connect_port(component, COMP_R, false);
  1178. wcd938x_rx_clk_disable(component);
  1179. snd_soc_component_update_bits(component,
  1180. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  1181. 0x02, 0x00);
  1182. break;
  1183. };
  1184. return 0;
  1185. }
  1186. static int wcd938x_enable_rx3(struct snd_soc_dapm_widget *w,
  1187. struct snd_kcontrol *kcontrol,
  1188. int event)
  1189. {
  1190. struct snd_soc_component *component =
  1191. snd_soc_dapm_to_component(w->dapm);
  1192. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1193. w->name, event);
  1194. switch (event) {
  1195. case SND_SOC_DAPM_PRE_PMU:
  1196. wcd938x_rx_connect_port(component, LO, true);
  1197. break;
  1198. case SND_SOC_DAPM_POST_PMD:
  1199. wcd938x_rx_connect_port(component, LO, false);
  1200. /* 6 msec delay as per HW requirement */
  1201. usleep_range(6000, 6010);
  1202. wcd938x_rx_clk_disable(component);
  1203. snd_soc_component_update_bits(component,
  1204. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  1205. break;
  1206. }
  1207. return 0;
  1208. }
  1209. static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  1210. struct snd_kcontrol *kcontrol,
  1211. int event)
  1212. {
  1213. struct snd_soc_component *component =
  1214. snd_soc_dapm_to_component(w->dapm);
  1215. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1216. u16 dmic_clk_reg, dmic_clk_en_reg;
  1217. s32 *dmic_clk_cnt;
  1218. u8 dmic_ctl_shift = 0;
  1219. u8 dmic_clk_shift = 0;
  1220. u8 dmic_clk_mask = 0;
  1221. u16 dmic2_left_en = 0;
  1222. int ret = 0;
  1223. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1224. w->name, event);
  1225. switch (w->shift) {
  1226. case 0:
  1227. case 1:
  1228. dmic_clk_cnt = &(wcd938x->dmic_0_1_clk_cnt);
  1229. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
  1230. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC1_CTL;
  1231. dmic_clk_mask = 0x0F;
  1232. dmic_clk_shift = 0x00;
  1233. dmic_ctl_shift = 0x00;
  1234. break;
  1235. case 2:
  1236. dmic2_left_en = WCD938X_DIGITAL_CDC_DMIC2_CTL;
  1237. case 3:
  1238. dmic_clk_cnt = &(wcd938x->dmic_2_3_clk_cnt);
  1239. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
  1240. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC2_CTL;
  1241. dmic_clk_mask = 0xF0;
  1242. dmic_clk_shift = 0x04;
  1243. dmic_ctl_shift = 0x01;
  1244. break;
  1245. case 4:
  1246. case 5:
  1247. dmic_clk_cnt = &(wcd938x->dmic_4_5_clk_cnt);
  1248. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
  1249. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC3_CTL;
  1250. dmic_clk_mask = 0x0F;
  1251. dmic_clk_shift = 0x00;
  1252. dmic_ctl_shift = 0x02;
  1253. break;
  1254. case 6:
  1255. case 7:
  1256. dmic_clk_cnt = &(wcd938x->dmic_6_7_clk_cnt);
  1257. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
  1258. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC4_CTL;
  1259. dmic_clk_mask = 0xF0;
  1260. dmic_clk_shift = 0x04;
  1261. dmic_ctl_shift = 0x03;
  1262. break;
  1263. default:
  1264. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  1265. __func__);
  1266. return -EINVAL;
  1267. };
  1268. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  1269. __func__, event, (w->shift +1), *dmic_clk_cnt);
  1270. switch (event) {
  1271. case SND_SOC_DAPM_PRE_PMU:
  1272. snd_soc_component_update_bits(component,
  1273. WCD938X_DIGITAL_CDC_AMIC_CTL,
  1274. (0x01 << dmic_ctl_shift), 0x00);
  1275. /* 250us sleep as per HW requirement */
  1276. usleep_range(250, 260);
  1277. if (dmic2_left_en)
  1278. snd_soc_component_update_bits(component,
  1279. dmic2_left_en, 0x80, 0x80);
  1280. /* Setting DMIC clock rate to 2.4MHz */
  1281. snd_soc_component_update_bits(component,
  1282. dmic_clk_reg, dmic_clk_mask,
  1283. (0x03 << dmic_clk_shift));
  1284. snd_soc_component_update_bits(component,
  1285. dmic_clk_en_reg, 0x08, 0x08);
  1286. /* enable clock scaling */
  1287. snd_soc_component_update_bits(component,
  1288. WCD938X_DIGITAL_CDC_DMIC_CTL, 0x06, 0x06);
  1289. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1290. wcd938x->tx_swr_dev->dev_num,
  1291. true);
  1292. break;
  1293. case SND_SOC_DAPM_POST_PMD:
  1294. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1295. wcd938x->tx_swr_dev->dev_num,
  1296. false);
  1297. snd_soc_component_update_bits(component,
  1298. WCD938X_DIGITAL_CDC_AMIC_CTL,
  1299. (0x01 << dmic_ctl_shift),
  1300. (0x01 << dmic_ctl_shift));
  1301. if (dmic2_left_en)
  1302. snd_soc_component_update_bits(component,
  1303. dmic2_left_en, 0x80, 0x00);
  1304. snd_soc_component_update_bits(component,
  1305. dmic_clk_en_reg, 0x08, 0x00);
  1306. break;
  1307. };
  1308. return ret;
  1309. }
  1310. /*
  1311. * wcd938x_get_micb_vout_ctl_val: converts micbias from volts to register value
  1312. * @micb_mv: micbias in mv
  1313. *
  1314. * return register value converted
  1315. */
  1316. int wcd938x_get_micb_vout_ctl_val(u32 micb_mv)
  1317. {
  1318. /* min micbias voltage is 1V and maximum is 2.85V */
  1319. if (micb_mv < 1000 || micb_mv > 2850) {
  1320. pr_err("%s: unsupported micbias voltage\n", __func__);
  1321. return -EINVAL;
  1322. }
  1323. return (micb_mv - 1000) / 50;
  1324. }
  1325. EXPORT_SYMBOL(wcd938x_get_micb_vout_ctl_val);
  1326. /*
  1327. * wcd938x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  1328. * @component: handle to snd_soc_component *
  1329. * @req_volt: micbias voltage to be set
  1330. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  1331. *
  1332. * return 0 if adjustment is success or error code in case of failure
  1333. */
  1334. int wcd938x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  1335. int req_volt, int micb_num)
  1336. {
  1337. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1338. int cur_vout_ctl, req_vout_ctl;
  1339. int micb_reg, micb_val, micb_en;
  1340. int ret = 0;
  1341. switch (micb_num) {
  1342. case MIC_BIAS_1:
  1343. micb_reg = WCD938X_ANA_MICB1;
  1344. break;
  1345. case MIC_BIAS_2:
  1346. micb_reg = WCD938X_ANA_MICB2;
  1347. break;
  1348. case MIC_BIAS_3:
  1349. micb_reg = WCD938X_ANA_MICB3;
  1350. break;
  1351. case MIC_BIAS_4:
  1352. micb_reg = WCD938X_ANA_MICB4;
  1353. break;
  1354. default:
  1355. return -EINVAL;
  1356. }
  1357. mutex_lock(&wcd938x->micb_lock);
  1358. /*
  1359. * If requested micbias voltage is same as current micbias
  1360. * voltage, then just return. Otherwise, adjust voltage as
  1361. * per requested value. If micbias is already enabled, then
  1362. * to avoid slow micbias ramp-up or down enable pull-up
  1363. * momentarily, change the micbias value and then re-enable
  1364. * micbias.
  1365. */
  1366. micb_val = snd_soc_component_read32(component, micb_reg);
  1367. micb_en = (micb_val & 0xC0) >> 6;
  1368. cur_vout_ctl = micb_val & 0x3F;
  1369. req_vout_ctl = wcd938x_get_micb_vout_ctl_val(req_volt);
  1370. if (req_vout_ctl < 0) {
  1371. ret = -EINVAL;
  1372. goto exit;
  1373. }
  1374. if (cur_vout_ctl == req_vout_ctl) {
  1375. ret = 0;
  1376. goto exit;
  1377. }
  1378. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  1379. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  1380. req_volt, micb_en);
  1381. if (micb_en == 0x1)
  1382. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  1383. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  1384. if (micb_en == 0x1) {
  1385. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  1386. /*
  1387. * Add 2ms delay as per HW requirement after enabling
  1388. * micbias
  1389. */
  1390. usleep_range(2000, 2100);
  1391. }
  1392. exit:
  1393. mutex_unlock(&wcd938x->micb_lock);
  1394. return ret;
  1395. }
  1396. EXPORT_SYMBOL(wcd938x_mbhc_micb_adjust_voltage);
  1397. static int wcd938x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1398. struct snd_kcontrol *kcontrol,
  1399. int event)
  1400. {
  1401. struct snd_soc_component *component =
  1402. snd_soc_dapm_to_component(w->dapm);
  1403. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1404. int ret = 0;
  1405. int bank = 0;
  1406. u8 mode = 0;
  1407. int i = 0;
  1408. int rate = 0;
  1409. bank = (wcd938x_swr_slv_get_current_bank(wcd938x->tx_swr_dev,
  1410. wcd938x->tx_swr_dev->dev_num) ? 0 : 1);
  1411. switch (event) {
  1412. case SND_SOC_DAPM_PRE_PMU:
  1413. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1414. if (test_bit(WCD_ADC1, &wcd938x->status_mask))
  1415. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC1]];
  1416. if (test_bit(WCD_ADC2, &wcd938x->status_mask))
  1417. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC2]];
  1418. if (test_bit(WCD_ADC3, &wcd938x->status_mask))
  1419. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC3]];
  1420. if (test_bit(WCD_ADC4, &wcd938x->status_mask))
  1421. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC4]];
  1422. if (mode != 0) {
  1423. for (i = 0; i < ADC_MODE_ULP2; i++) {
  1424. if (mode & (1 << i)) {
  1425. i++;
  1426. break;
  1427. }
  1428. }
  1429. }
  1430. rate = wcd938x_get_clk_rate(i);
  1431. wcd938x_set_swr_clk_rate(component, rate, bank);
  1432. }
  1433. if (w->shift == ADC2 && !(snd_soc_component_read32(component,
  1434. WCD938X_TX_NEW_AMIC_MUX_CFG) & 0x80)) {
  1435. if (!wcd938x->bcs_dis)
  1436. wcd938x_tx_connect_port(component, MBHC,
  1437. SWR_CLK_RATE_4P8MHZ, true);
  1438. set_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask);
  1439. }
  1440. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1441. wcd938x_tx_connect_port(component, w->shift, rate,
  1442. true);
  1443. /* Copy clk settings to active bank */
  1444. wcd938x_set_swr_clk_rate(component, rate, !bank);
  1445. } else {
  1446. wcd938x_tx_connect_port(component, w->shift,
  1447. SWR_CLK_RATE_2P4MHZ, true);
  1448. }
  1449. break;
  1450. case SND_SOC_DAPM_POST_PMD:
  1451. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1452. rate = wcd938x_get_clk_rate(ADC_MODE_INVALID);
  1453. wcd938x_set_swr_clk_rate(component, rate, !bank);
  1454. }
  1455. wcd938x_tx_connect_port(component, w->shift, 0, false);
  1456. if (w->shift == ADC2 &&
  1457. test_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask)) {
  1458. if (!wcd938x->bcs_dis)
  1459. wcd938x_tx_connect_port(component, MBHC, 0,
  1460. false);
  1461. clear_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask);
  1462. }
  1463. if (strnstr(w->name, "ADC", sizeof("ADC")))
  1464. wcd938x_set_swr_clk_rate(component, rate, bank);
  1465. break;
  1466. };
  1467. return ret;
  1468. }
  1469. static int wcd938x_get_adc_mode(int val)
  1470. {
  1471. int ret = 0;
  1472. switch (val) {
  1473. case ADC_MODE_INVALID:
  1474. ret = ADC_MODE_VAL_NORMAL;
  1475. break;
  1476. case ADC_MODE_HIFI:
  1477. ret = ADC_MODE_VAL_HIFI;
  1478. break;
  1479. case ADC_MODE_LO_HIF:
  1480. ret = ADC_MODE_VAL_LO_HIF;
  1481. break;
  1482. case ADC_MODE_NORMAL:
  1483. ret = ADC_MODE_VAL_NORMAL;
  1484. break;
  1485. case ADC_MODE_LP:
  1486. ret = ADC_MODE_VAL_LP;
  1487. break;
  1488. case ADC_MODE_ULP1:
  1489. ret = ADC_MODE_VAL_ULP1;
  1490. break;
  1491. case ADC_MODE_ULP2:
  1492. ret = ADC_MODE_VAL_ULP2;
  1493. break;
  1494. default:
  1495. ret = -EINVAL;
  1496. pr_err("%s: invalid ADC mode value %d\n", __func__, val);
  1497. break;
  1498. }
  1499. return ret;
  1500. }
  1501. static int wcd938x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  1502. struct snd_kcontrol *kcontrol,
  1503. int event){
  1504. struct snd_soc_component *component =
  1505. snd_soc_dapm_to_component(w->dapm);
  1506. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1507. int clk_rate = 0, ret = 0;
  1508. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1509. w->name, event);
  1510. switch (event) {
  1511. case SND_SOC_DAPM_PRE_PMU:
  1512. snd_soc_component_update_bits(component,
  1513. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x08);
  1514. snd_soc_component_update_bits(component,
  1515. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1516. set_bit(w->shift, &wcd938x->status_mask);
  1517. clk_rate = wcd938x_get_clk_rate(wcd938x->tx_mode[w->shift]);
  1518. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1519. wcd938x->tx_swr_dev->dev_num,
  1520. true);
  1521. break;
  1522. case SND_SOC_DAPM_POST_PMD:
  1523. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1524. wcd938x->tx_swr_dev->dev_num,
  1525. false);
  1526. snd_soc_component_update_bits(component,
  1527. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x00);
  1528. clear_bit(w->shift, &wcd938x->status_mask);
  1529. break;
  1530. };
  1531. return ret;
  1532. }
  1533. void wcd938x_disable_bcs_before_slow_insert(struct snd_soc_component *component,
  1534. bool bcs_disable)
  1535. {
  1536. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1537. if (wcd938x->update_wcd_event) {
  1538. if (bcs_disable)
  1539. wcd938x->update_wcd_event(wcd938x->handle,
  1540. WCD_BOLERO_EVT_BCS_CLK_OFF, 0);
  1541. else
  1542. wcd938x->update_wcd_event(wcd938x->handle,
  1543. WCD_BOLERO_EVT_BCS_CLK_OFF, 1);
  1544. }
  1545. }
  1546. int wcd938x_tx_channel_config(struct snd_soc_component *component,
  1547. int channel, int mode)
  1548. {
  1549. int reg = WCD938X_ANA_TX_CH2, mask = 0, val = 0;
  1550. int ret = 0;
  1551. switch (channel) {
  1552. case 0:
  1553. reg = WCD938X_ANA_TX_CH2;
  1554. mask = 0x40;
  1555. break;
  1556. case 1:
  1557. reg = WCD938X_ANA_TX_CH2;
  1558. mask = 0x20;
  1559. break;
  1560. case 2:
  1561. reg = WCD938X_ANA_TX_CH4;
  1562. mask = 0x40;
  1563. break;
  1564. case 3:
  1565. reg = WCD938X_ANA_TX_CH4;
  1566. mask = 0x20;
  1567. break;
  1568. default:
  1569. pr_err("%s: Invalid channel num %d\n", __func__, channel);
  1570. ret = -EINVAL;
  1571. break;
  1572. }
  1573. if (!mode)
  1574. val = 0x00;
  1575. else
  1576. val = mask;
  1577. if (!ret)
  1578. snd_soc_component_update_bits(component, reg, mask, val);
  1579. return ret;
  1580. }
  1581. static int wcd938x_enable_req(struct snd_soc_dapm_widget *w,
  1582. struct snd_kcontrol *kcontrol, int event)
  1583. {
  1584. struct snd_soc_component *component =
  1585. snd_soc_dapm_to_component(w->dapm);
  1586. int mode;
  1587. int ret = 0;
  1588. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1589. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1590. w->name, event);
  1591. switch (event) {
  1592. case SND_SOC_DAPM_PRE_PMU:
  1593. snd_soc_component_update_bits(component,
  1594. WCD938X_DIGITAL_CDC_REQ_CTL, 0x02, 0x02);
  1595. snd_soc_component_update_bits(component,
  1596. WCD938X_DIGITAL_CDC_REQ_CTL, 0x01, 0x00);
  1597. ret = wcd938x_tx_channel_config(component, w->shift, 1);
  1598. mode = wcd938x_get_adc_mode(wcd938x->tx_mode[w->shift]);
  1599. if (mode < 0) {
  1600. dev_info(component->dev,
  1601. "%s: invalid mode, setting to normal mode\n",
  1602. __func__);
  1603. mode = ADC_MODE_VAL_NORMAL;
  1604. }
  1605. switch (w->shift) {
  1606. case 0:
  1607. snd_soc_component_update_bits(component,
  1608. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x0F,
  1609. mode);
  1610. snd_soc_component_update_bits(component,
  1611. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x10);
  1612. break;
  1613. case 1:
  1614. snd_soc_component_update_bits(component,
  1615. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0xF0,
  1616. mode << 4);
  1617. snd_soc_component_update_bits(component,
  1618. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x20, 0x20);
  1619. break;
  1620. case 2:
  1621. snd_soc_component_update_bits(component,
  1622. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x0F,
  1623. mode);
  1624. snd_soc_component_update_bits(component,
  1625. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x40, 0x40);
  1626. break;
  1627. case 3:
  1628. snd_soc_component_update_bits(component,
  1629. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0xF0,
  1630. mode << 4);
  1631. snd_soc_component_update_bits(component,
  1632. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1633. break;
  1634. default:
  1635. break;
  1636. }
  1637. ret |= wcd938x_tx_channel_config(component, w->shift, 0);
  1638. break;
  1639. case SND_SOC_DAPM_POST_PMD:
  1640. switch (w->shift) {
  1641. case 0:
  1642. snd_soc_component_update_bits(component,
  1643. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x0F,
  1644. 0x00);
  1645. snd_soc_component_update_bits(component,
  1646. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x00);
  1647. break;
  1648. case 1:
  1649. snd_soc_component_update_bits(component,
  1650. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0xF0,
  1651. 0x00);
  1652. snd_soc_component_update_bits(component,
  1653. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x20, 0x00);
  1654. break;
  1655. case 2:
  1656. snd_soc_component_update_bits(component,
  1657. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x0F,
  1658. 0x00);
  1659. snd_soc_component_update_bits(component,
  1660. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x40, 0x00);
  1661. break;
  1662. case 3:
  1663. snd_soc_component_update_bits(component,
  1664. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0xF0,
  1665. 0x00);
  1666. snd_soc_component_update_bits(component,
  1667. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00);
  1668. break;
  1669. default:
  1670. break;
  1671. }
  1672. snd_soc_component_update_bits(component,
  1673. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
  1674. break;
  1675. };
  1676. return ret;
  1677. }
  1678. int wcd938x_micbias_control(struct snd_soc_component *component,
  1679. int micb_num, int req, bool is_dapm)
  1680. {
  1681. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1682. int micb_index = micb_num - 1;
  1683. u16 micb_reg;
  1684. int pre_off_event = 0, post_off_event = 0;
  1685. int post_on_event = 0, post_dapm_off = 0;
  1686. int post_dapm_on = 0;
  1687. int ret = 0;
  1688. if ((micb_index < 0) || (micb_index > WCD938X_MAX_MICBIAS - 1)) {
  1689. dev_err(component->dev,
  1690. "%s: Invalid micbias index, micb_ind:%d\n",
  1691. __func__, micb_index);
  1692. return -EINVAL;
  1693. }
  1694. if (NULL == wcd938x) {
  1695. dev_err(component->dev,
  1696. "%s: wcd938x private data is NULL\n", __func__);
  1697. return -EINVAL;
  1698. }
  1699. switch (micb_num) {
  1700. case MIC_BIAS_1:
  1701. micb_reg = WCD938X_ANA_MICB1;
  1702. break;
  1703. case MIC_BIAS_2:
  1704. micb_reg = WCD938X_ANA_MICB2;
  1705. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1706. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1707. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1708. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1709. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1710. break;
  1711. case MIC_BIAS_3:
  1712. micb_reg = WCD938X_ANA_MICB3;
  1713. break;
  1714. case MIC_BIAS_4:
  1715. micb_reg = WCD938X_ANA_MICB4;
  1716. break;
  1717. default:
  1718. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1719. __func__, micb_num);
  1720. return -EINVAL;
  1721. };
  1722. mutex_lock(&wcd938x->micb_lock);
  1723. switch (req) {
  1724. case MICB_PULLUP_ENABLE:
  1725. if (!wcd938x->dev_up) {
  1726. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1727. __func__, req);
  1728. ret = -ENODEV;
  1729. goto done;
  1730. }
  1731. wcd938x->pullup_ref[micb_index]++;
  1732. if ((wcd938x->pullup_ref[micb_index] == 1) &&
  1733. (wcd938x->micb_ref[micb_index] == 0))
  1734. snd_soc_component_update_bits(component, micb_reg,
  1735. 0xC0, 0x80);
  1736. break;
  1737. case MICB_PULLUP_DISABLE:
  1738. if (wcd938x->pullup_ref[micb_index] > 0)
  1739. wcd938x->pullup_ref[micb_index]--;
  1740. if (!wcd938x->dev_up) {
  1741. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1742. __func__, req);
  1743. ret = -ENODEV;
  1744. goto done;
  1745. }
  1746. if ((wcd938x->pullup_ref[micb_index] == 0) &&
  1747. (wcd938x->micb_ref[micb_index] == 0))
  1748. snd_soc_component_update_bits(component, micb_reg,
  1749. 0xC0, 0x00);
  1750. break;
  1751. case MICB_ENABLE:
  1752. if (!wcd938x->dev_up) {
  1753. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1754. __func__, req);
  1755. ret = -ENODEV;
  1756. goto done;
  1757. }
  1758. wcd938x->micb_ref[micb_index]++;
  1759. if (wcd938x->micb_ref[micb_index] == 1) {
  1760. snd_soc_component_update_bits(component,
  1761. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xF0, 0xF0);
  1762. snd_soc_component_update_bits(component,
  1763. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1764. snd_soc_component_update_bits(component,
  1765. WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x01, 0x01);
  1766. snd_soc_component_update_bits(component,
  1767. WCD938X_MICB1_TEST_CTL_2, 0x01, 0x01);
  1768. snd_soc_component_update_bits(component,
  1769. WCD938X_MICB2_TEST_CTL_2, 0x01, 0x01);
  1770. snd_soc_component_update_bits(component,
  1771. WCD938X_MICB3_TEST_CTL_2, 0x01, 0x01);
  1772. snd_soc_component_update_bits(component,
  1773. WCD938X_MICB4_TEST_CTL_2, 0x01, 0x01);
  1774. snd_soc_component_update_bits(component,
  1775. micb_reg, 0xC0, 0x40);
  1776. if (post_on_event)
  1777. blocking_notifier_call_chain(
  1778. &wcd938x->mbhc->notifier,
  1779. post_on_event,
  1780. &wcd938x->mbhc->wcd_mbhc);
  1781. }
  1782. if (is_dapm && post_dapm_on && wcd938x->mbhc)
  1783. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1784. post_dapm_on,
  1785. &wcd938x->mbhc->wcd_mbhc);
  1786. break;
  1787. case MICB_DISABLE:
  1788. if (wcd938x->micb_ref[micb_index] > 0)
  1789. wcd938x->micb_ref[micb_index]--;
  1790. if (!wcd938x->dev_up) {
  1791. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1792. __func__, req);
  1793. ret = -ENODEV;
  1794. goto done;
  1795. }
  1796. if ((wcd938x->micb_ref[micb_index] == 0) &&
  1797. (wcd938x->pullup_ref[micb_index] > 0))
  1798. snd_soc_component_update_bits(component, micb_reg,
  1799. 0xC0, 0x80);
  1800. else if ((wcd938x->micb_ref[micb_index] == 0) &&
  1801. (wcd938x->pullup_ref[micb_index] == 0)) {
  1802. if (pre_off_event && wcd938x->mbhc)
  1803. blocking_notifier_call_chain(
  1804. &wcd938x->mbhc->notifier,
  1805. pre_off_event,
  1806. &wcd938x->mbhc->wcd_mbhc);
  1807. snd_soc_component_update_bits(component, micb_reg,
  1808. 0xC0, 0x00);
  1809. if (post_off_event && wcd938x->mbhc)
  1810. blocking_notifier_call_chain(
  1811. &wcd938x->mbhc->notifier,
  1812. post_off_event,
  1813. &wcd938x->mbhc->wcd_mbhc);
  1814. }
  1815. if (is_dapm && post_dapm_off && wcd938x->mbhc)
  1816. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1817. post_dapm_off,
  1818. &wcd938x->mbhc->wcd_mbhc);
  1819. break;
  1820. };
  1821. dev_dbg(component->dev,
  1822. "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1823. __func__, micb_num, wcd938x->micb_ref[micb_index],
  1824. wcd938x->pullup_ref[micb_index]);
  1825. done:
  1826. mutex_unlock(&wcd938x->micb_lock);
  1827. return ret;
  1828. }
  1829. EXPORT_SYMBOL(wcd938x_micbias_control);
  1830. static int wcd938x_get_logical_addr(struct swr_device *swr_dev)
  1831. {
  1832. int ret = 0;
  1833. uint8_t devnum = 0;
  1834. int num_retry = NUM_ATTEMPTS;
  1835. do {
  1836. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1837. if (ret) {
  1838. dev_err(&swr_dev->dev,
  1839. "%s get devnum %d for dev addr %lx failed\n",
  1840. __func__, devnum, swr_dev->addr);
  1841. /* retry after 1ms */
  1842. usleep_range(1000, 1010);
  1843. }
  1844. } while (ret && --num_retry);
  1845. swr_dev->dev_num = devnum;
  1846. return 0;
  1847. }
  1848. static bool get_usbc_hs_status(struct snd_soc_component *component,
  1849. struct wcd_mbhc_config *mbhc_cfg)
  1850. {
  1851. if (mbhc_cfg->enable_usbc_analog) {
  1852. if (!(snd_soc_component_read32(component, WCD938X_ANA_MBHC_MECH)
  1853. & 0x20))
  1854. return true;
  1855. }
  1856. return false;
  1857. }
  1858. static int wcd938x_event_notify(struct notifier_block *block,
  1859. unsigned long val,
  1860. void *data)
  1861. {
  1862. u16 event = (val & 0xffff);
  1863. int ret = 0;
  1864. struct wcd938x_priv *wcd938x = dev_get_drvdata((struct device *)data);
  1865. struct snd_soc_component *component = wcd938x->component;
  1866. struct wcd_mbhc *mbhc;
  1867. switch (event) {
  1868. case BOLERO_WCD_EVT_TX_CH_HOLD_CLEAR:
  1869. if (test_bit(WCD_ADC1, &wcd938x->status_mask)) {
  1870. snd_soc_component_update_bits(component,
  1871. WCD938X_ANA_TX_CH2, 0x40, 0x00);
  1872. clear_bit(WCD_ADC1, &wcd938x->status_mask);
  1873. }
  1874. if (test_bit(WCD_ADC2, &wcd938x->status_mask)) {
  1875. snd_soc_component_update_bits(component,
  1876. WCD938X_ANA_TX_CH2, 0x20, 0x00);
  1877. clear_bit(WCD_ADC2, &wcd938x->status_mask);
  1878. }
  1879. if (test_bit(WCD_ADC3, &wcd938x->status_mask)) {
  1880. snd_soc_component_update_bits(component,
  1881. WCD938X_ANA_TX_CH4, 0x40, 0x00);
  1882. clear_bit(WCD_ADC3, &wcd938x->status_mask);
  1883. }
  1884. if (test_bit(WCD_ADC4, &wcd938x->status_mask)) {
  1885. snd_soc_component_update_bits(component,
  1886. WCD938X_ANA_TX_CH4, 0x20, 0x00);
  1887. clear_bit(WCD_ADC4, &wcd938x->status_mask);
  1888. }
  1889. break;
  1890. case BOLERO_WCD_EVT_PA_OFF_PRE_SSR:
  1891. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  1892. 0xC0, 0x00);
  1893. snd_soc_component_update_bits(component, WCD938X_ANA_EAR,
  1894. 0x80, 0x00);
  1895. snd_soc_component_update_bits(component, WCD938X_AUX_AUXPA,
  1896. 0x80, 0x00);
  1897. break;
  1898. case BOLERO_WCD_EVT_SSR_DOWN:
  1899. wcd938x->dev_up = false;
  1900. wcd938x->mbhc->wcd_mbhc.deinit_in_progress = true;
  1901. mbhc = &wcd938x->mbhc->wcd_mbhc;
  1902. wcd938x->usbc_hs_status = get_usbc_hs_status(component,
  1903. mbhc->mbhc_cfg);
  1904. wcd938x_mbhc_ssr_down(wcd938x->mbhc, component);
  1905. wcd938x_reset_low(wcd938x->dev);
  1906. break;
  1907. case BOLERO_WCD_EVT_SSR_UP:
  1908. wcd938x_reset(wcd938x->dev);
  1909. /* allow reset to take effect */
  1910. usleep_range(10000, 10010);
  1911. wcd938x_get_logical_addr(wcd938x->tx_swr_dev);
  1912. wcd938x_get_logical_addr(wcd938x->rx_swr_dev);
  1913. wcd938x_init_reg(component);
  1914. regcache_mark_dirty(wcd938x->regmap);
  1915. regcache_sync(wcd938x->regmap);
  1916. /* Initialize MBHC module */
  1917. mbhc = &wcd938x->mbhc->wcd_mbhc;
  1918. ret = wcd938x_mbhc_post_ssr_init(wcd938x->mbhc, component);
  1919. if (ret) {
  1920. dev_err(component->dev, "%s: mbhc initialization failed\n",
  1921. __func__);
  1922. } else {
  1923. wcd938x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  1924. if (wcd938x->usbc_hs_status)
  1925. mdelay(500);
  1926. }
  1927. wcd938x->mbhc->wcd_mbhc.deinit_in_progress = false;
  1928. wcd938x->dev_up = true;
  1929. break;
  1930. case BOLERO_WCD_EVT_CLK_NOTIFY:
  1931. snd_soc_component_update_bits(component,
  1932. WCD938X_DIGITAL_TOP_CLK_CFG, 0x06,
  1933. ((val >> 0x10) << 0x01));
  1934. break;
  1935. default:
  1936. dev_dbg(component->dev, "%s: invalid event %d\n", __func__, event);
  1937. break;
  1938. }
  1939. return 0;
  1940. }
  1941. static int __wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1942. int event)
  1943. {
  1944. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1945. int micb_num;
  1946. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1947. __func__, w->name, event);
  1948. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  1949. micb_num = MIC_BIAS_1;
  1950. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  1951. micb_num = MIC_BIAS_2;
  1952. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  1953. micb_num = MIC_BIAS_3;
  1954. else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4")))
  1955. micb_num = MIC_BIAS_4;
  1956. else
  1957. return -EINVAL;
  1958. switch (event) {
  1959. case SND_SOC_DAPM_PRE_PMU:
  1960. wcd938x_micbias_control(component, micb_num,
  1961. MICB_ENABLE, true);
  1962. break;
  1963. case SND_SOC_DAPM_POST_PMU:
  1964. /* 1 msec delay as per HW requirement */
  1965. usleep_range(1000, 1100);
  1966. break;
  1967. case SND_SOC_DAPM_POST_PMD:
  1968. wcd938x_micbias_control(component, micb_num,
  1969. MICB_DISABLE, true);
  1970. break;
  1971. };
  1972. return 0;
  1973. }
  1974. static int wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1975. struct snd_kcontrol *kcontrol,
  1976. int event)
  1977. {
  1978. return __wcd938x_codec_enable_micbias(w, event);
  1979. }
  1980. static int __wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1981. int event)
  1982. {
  1983. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1984. int micb_num;
  1985. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1986. __func__, w->name, event);
  1987. if (strnstr(w->name, "VA MIC BIAS1", sizeof("VA MIC BIAS1")))
  1988. micb_num = MIC_BIAS_1;
  1989. else if (strnstr(w->name, "VA MIC BIAS2", sizeof("VA MIC BIAS2")))
  1990. micb_num = MIC_BIAS_2;
  1991. else if (strnstr(w->name, "VA MIC BIAS3", sizeof("VA MIC BIAS3")))
  1992. micb_num = MIC_BIAS_3;
  1993. else if (strnstr(w->name, "VA MIC BIAS4", sizeof("VA MIC BIAS4")))
  1994. micb_num = MIC_BIAS_4;
  1995. else
  1996. return -EINVAL;
  1997. switch (event) {
  1998. case SND_SOC_DAPM_PRE_PMU:
  1999. wcd938x_micbias_control(component, micb_num,
  2000. MICB_PULLUP_ENABLE, true);
  2001. break;
  2002. case SND_SOC_DAPM_POST_PMU:
  2003. /* 1 msec delay as per HW requirement */
  2004. usleep_range(1000, 1100);
  2005. break;
  2006. case SND_SOC_DAPM_POST_PMD:
  2007. wcd938x_micbias_control(component, micb_num,
  2008. MICB_PULLUP_DISABLE, true);
  2009. break;
  2010. };
  2011. return 0;
  2012. }
  2013. static int wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  2014. struct snd_kcontrol *kcontrol,
  2015. int event)
  2016. {
  2017. return __wcd938x_codec_enable_micbias_pullup(w, event);
  2018. }
  2019. static int wcd938x_wakeup(void *handle, bool enable)
  2020. {
  2021. struct wcd938x_priv *priv;
  2022. int ret = 0;
  2023. if (!handle) {
  2024. pr_err("%s: NULL handle\n", __func__);
  2025. return -EINVAL;
  2026. }
  2027. priv = (struct wcd938x_priv *)handle;
  2028. if (!priv->tx_swr_dev) {
  2029. pr_err("%s: tx swr dev is NULL\n", __func__);
  2030. return -EINVAL;
  2031. }
  2032. mutex_lock(&priv->wakeup_lock);
  2033. if (enable)
  2034. ret = swr_device_wakeup_vote(priv->tx_swr_dev);
  2035. else
  2036. ret = swr_device_wakeup_unvote(priv->tx_swr_dev);
  2037. mutex_unlock(&priv->wakeup_lock);
  2038. return ret;
  2039. }
  2040. static int wcd938x_codec_force_enable_micbias(struct snd_soc_dapm_widget *w,
  2041. struct snd_kcontrol *kcontrol,
  2042. int event)
  2043. {
  2044. int ret = 0;
  2045. struct snd_soc_component *component =
  2046. snd_soc_dapm_to_component(w->dapm);
  2047. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2048. switch (event) {
  2049. case SND_SOC_DAPM_PRE_PMU:
  2050. wcd938x_wakeup(wcd938x, true);
  2051. ret = __wcd938x_codec_enable_micbias(w, SND_SOC_DAPM_PRE_PMU);
  2052. wcd938x_wakeup(wcd938x, false);
  2053. break;
  2054. case SND_SOC_DAPM_POST_PMD:
  2055. wcd938x_wakeup(wcd938x, true);
  2056. ret = __wcd938x_codec_enable_micbias(w, SND_SOC_DAPM_POST_PMD);
  2057. wcd938x_wakeup(wcd938x, false);
  2058. break;
  2059. }
  2060. return ret;
  2061. }
  2062. static int wcd938x_enable_micbias(struct wcd938x_priv *wcd938x,
  2063. int micb_num, int req)
  2064. {
  2065. int micb_index = micb_num - 1;
  2066. u16 micb_reg;
  2067. if (NULL == wcd938x) {
  2068. pr_err("%s: wcd938x private data is NULL\n", __func__);
  2069. return -EINVAL;
  2070. }
  2071. switch (micb_num) {
  2072. case MIC_BIAS_1:
  2073. micb_reg = WCD938X_ANA_MICB1;
  2074. break;
  2075. case MIC_BIAS_2:
  2076. micb_reg = WCD938X_ANA_MICB2;
  2077. break;
  2078. case MIC_BIAS_3:
  2079. micb_reg = WCD938X_ANA_MICB3;
  2080. break;
  2081. case MIC_BIAS_4:
  2082. micb_reg = WCD938X_ANA_MICB4;
  2083. break;
  2084. default:
  2085. pr_err("%s: Invalid micbias number: %d\n", __func__, micb_num);
  2086. return -EINVAL;
  2087. };
  2088. mutex_lock(&wcd938x->micb_lock);
  2089. switch (req) {
  2090. case MICB_ENABLE:
  2091. wcd938x->micb_ref[micb_index]++;
  2092. if (wcd938x->micb_ref[micb_index] == 1) {
  2093. regmap_update_bits(wcd938x->regmap,
  2094. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xE0, 0xE0);
  2095. regmap_update_bits(wcd938x->regmap,
  2096. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  2097. regmap_update_bits(wcd938x->regmap,
  2098. WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x01, 0x01);
  2099. regmap_update_bits(wcd938x->regmap,
  2100. WCD938X_MICB1_TEST_CTL_2, 0x01, 0x01);
  2101. regmap_update_bits(wcd938x->regmap,
  2102. WCD938X_MICB2_TEST_CTL_2, 0x01, 0x01);
  2103. regmap_update_bits(wcd938x->regmap,
  2104. WCD938X_MICB3_TEST_CTL_2, 0x01, 0x01);
  2105. regmap_update_bits(wcd938x->regmap,
  2106. WCD938X_MICB4_TEST_CTL_2, 0x01, 0x01);
  2107. regmap_update_bits(wcd938x->regmap,
  2108. micb_reg, 0xC0, 0x40);
  2109. regmap_update_bits(wcd938x->regmap, micb_reg, 0x3F, 0x10);
  2110. }
  2111. break;
  2112. case MICB_PULLUP_ENABLE:
  2113. wcd938x->pullup_ref[micb_index]++;
  2114. if ((wcd938x->pullup_ref[micb_index] == 1) &&
  2115. (wcd938x->micb_ref[micb_index] == 0))
  2116. regmap_update_bits(wcd938x->regmap, micb_reg,
  2117. 0xC0, 0x80);
  2118. break;
  2119. case MICB_PULLUP_DISABLE:
  2120. if (wcd938x->pullup_ref[micb_index] > 0)
  2121. wcd938x->pullup_ref[micb_index]--;
  2122. if ((wcd938x->pullup_ref[micb_index] == 0) &&
  2123. (wcd938x->micb_ref[micb_index] == 0))
  2124. regmap_update_bits(wcd938x->regmap, micb_reg,
  2125. 0xC0, 0x00);
  2126. break;
  2127. case MICB_DISABLE:
  2128. if (wcd938x->micb_ref[micb_index] > 0)
  2129. wcd938x->micb_ref[micb_index]--;
  2130. if ((wcd938x->micb_ref[micb_index] == 0) &&
  2131. (wcd938x->pullup_ref[micb_index] > 0))
  2132. regmap_update_bits(wcd938x->regmap, micb_reg,
  2133. 0xC0, 0x80);
  2134. else if ((wcd938x->micb_ref[micb_index] == 0) &&
  2135. (wcd938x->pullup_ref[micb_index] == 0))
  2136. regmap_update_bits(wcd938x->regmap, micb_reg,
  2137. 0xC0, 0x00);
  2138. break;
  2139. };
  2140. mutex_unlock(&wcd938x->micb_lock);
  2141. return 0;
  2142. }
  2143. int wcd938x_codec_force_enable_micbias_v2(struct snd_soc_component *component,
  2144. int event, int micb_num)
  2145. {
  2146. struct wcd938x_priv *wcd938x_priv = NULL;
  2147. if(NULL == component) {
  2148. pr_err("%s: wcd938x component is NULL\n", __func__);
  2149. return -EINVAL;
  2150. }
  2151. if(event != SND_SOC_DAPM_PRE_PMU && event != SND_SOC_DAPM_POST_PMD) {
  2152. pr_err("%s: invalid event: %d\n", __func__, event);
  2153. return -EINVAL;
  2154. }
  2155. if(micb_num < MIC_BIAS_1 || micb_num > MIC_BIAS_4) {
  2156. pr_err("%s: invalid mic bias num: %d\n", __func__, micb_num);
  2157. return -EINVAL;
  2158. }
  2159. wcd938x_priv = snd_soc_component_get_drvdata(component);
  2160. switch (event) {
  2161. case SND_SOC_DAPM_PRE_PMU:
  2162. wcd938x_wakeup(wcd938x_priv, true);
  2163. wcd938x_enable_micbias(wcd938x_priv, micb_num, MICB_PULLUP_ENABLE);
  2164. wcd938x_wakeup(wcd938x_priv, false);
  2165. break;
  2166. case SND_SOC_DAPM_POST_PMD:
  2167. wcd938x_wakeup(wcd938x_priv, true);
  2168. wcd938x_enable_micbias(wcd938x_priv, micb_num, MICB_PULLUP_DISABLE);
  2169. wcd938x_wakeup(wcd938x_priv, false);
  2170. break;
  2171. }
  2172. return 0;
  2173. }
  2174. EXPORT_SYMBOL(wcd938x_codec_force_enable_micbias_v2);
  2175. static inline int wcd938x_tx_path_get(const char *wname,
  2176. unsigned int *path_num)
  2177. {
  2178. int ret = 0;
  2179. char *widget_name = NULL;
  2180. char *w_name = NULL;
  2181. char *path_num_char = NULL;
  2182. char *path_name = NULL;
  2183. widget_name = kstrndup(wname, 9, GFP_KERNEL);
  2184. if (!widget_name)
  2185. return -EINVAL;
  2186. w_name = widget_name;
  2187. path_name = strsep(&widget_name, " ");
  2188. if (!path_name) {
  2189. pr_err("%s: Invalid widget name = %s\n",
  2190. __func__, widget_name);
  2191. ret = -EINVAL;
  2192. goto err;
  2193. }
  2194. path_num_char = strpbrk(path_name, "0123");
  2195. if (!path_num_char) {
  2196. pr_err("%s: tx path index not found\n",
  2197. __func__);
  2198. ret = -EINVAL;
  2199. goto err;
  2200. }
  2201. ret = kstrtouint(path_num_char, 10, path_num);
  2202. if (ret < 0)
  2203. pr_err("%s: Invalid tx path = %s\n",
  2204. __func__, w_name);
  2205. err:
  2206. kfree(w_name);
  2207. return ret;
  2208. }
  2209. static int wcd938x_tx_mode_get(struct snd_kcontrol *kcontrol,
  2210. struct snd_ctl_elem_value *ucontrol)
  2211. {
  2212. struct snd_soc_component *component =
  2213. snd_soc_kcontrol_component(kcontrol);
  2214. struct wcd938x_priv *wcd938x = NULL;
  2215. int ret = 0;
  2216. unsigned int path = 0;
  2217. if (!component)
  2218. return -EINVAL;
  2219. wcd938x = snd_soc_component_get_drvdata(component);
  2220. if (!wcd938x)
  2221. return -EINVAL;
  2222. ret = wcd938x_tx_path_get(kcontrol->id.name, &path);
  2223. if (ret < 0)
  2224. return ret;
  2225. ucontrol->value.integer.value[0] = wcd938x->tx_mode[path];
  2226. return 0;
  2227. }
  2228. static int wcd938x_tx_mode_put(struct snd_kcontrol *kcontrol,
  2229. struct snd_ctl_elem_value *ucontrol)
  2230. {
  2231. struct snd_soc_component *component =
  2232. snd_soc_kcontrol_component(kcontrol);
  2233. struct wcd938x_priv *wcd938x = NULL;
  2234. u32 mode_val;
  2235. unsigned int path = 0;
  2236. int ret = 0;
  2237. if (!component)
  2238. return -EINVAL;
  2239. wcd938x = snd_soc_component_get_drvdata(component);
  2240. if (!wcd938x)
  2241. return -EINVAL;
  2242. ret = wcd938x_tx_path_get(kcontrol->id.name, &path);
  2243. if (ret)
  2244. return ret;
  2245. mode_val = ucontrol->value.enumerated.item[0];
  2246. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  2247. wcd938x->tx_mode[path] = mode_val;
  2248. return 0;
  2249. }
  2250. static int wcd938x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  2251. struct snd_ctl_elem_value *ucontrol)
  2252. {
  2253. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2254. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2255. ucontrol->value.integer.value[0] = wcd938x->hph_mode;
  2256. return 0;
  2257. }
  2258. static int wcd938x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  2259. struct snd_ctl_elem_value *ucontrol)
  2260. {
  2261. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2262. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2263. u32 mode_val;
  2264. mode_val = ucontrol->value.enumerated.item[0];
  2265. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  2266. if (wcd938x->variant == WCD9380) {
  2267. if (mode_val == CLS_H_HIFI || mode_val == CLS_AB_HIFI) {
  2268. dev_info(component->dev,
  2269. "%s:Invalid HPH Mode, default to CLS_H_ULP\n",
  2270. __func__);
  2271. mode_val = CLS_H_ULP;
  2272. }
  2273. }
  2274. if (mode_val == CLS_H_NORMAL) {
  2275. dev_info(component->dev,
  2276. "%s:Invalid HPH Mode, default to class_AB\n",
  2277. __func__);
  2278. mode_val = CLS_H_ULP;
  2279. }
  2280. wcd938x->hph_mode = mode_val;
  2281. return 0;
  2282. }
  2283. static int wcd938x_ear_pa_gain_get(struct snd_kcontrol *kcontrol,
  2284. struct snd_ctl_elem_value *ucontrol)
  2285. {
  2286. u8 ear_pa_gain = 0;
  2287. struct snd_soc_component *component =
  2288. snd_soc_kcontrol_component(kcontrol);
  2289. ear_pa_gain = snd_soc_component_read32(component,
  2290. WCD938X_ANA_EAR_COMPANDER_CTL);
  2291. ear_pa_gain = (ear_pa_gain & 0x7C) >> 2;
  2292. ucontrol->value.integer.value[0] = ear_pa_gain;
  2293. dev_dbg(component->dev, "%s: ear_pa_gain = 0x%x\n", __func__,
  2294. ear_pa_gain);
  2295. return 0;
  2296. }
  2297. static int wcd938x_ear_pa_gain_put(struct snd_kcontrol *kcontrol,
  2298. struct snd_ctl_elem_value *ucontrol)
  2299. {
  2300. u8 ear_pa_gain = 0;
  2301. struct snd_soc_component *component =
  2302. snd_soc_kcontrol_component(kcontrol);
  2303. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2304. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  2305. __func__, ucontrol->value.integer.value[0]);
  2306. ear_pa_gain = ucontrol->value.integer.value[0] << 2;
  2307. if (!wcd938x->comp1_enable) {
  2308. snd_soc_component_update_bits(component,
  2309. WCD938X_ANA_EAR_COMPANDER_CTL,
  2310. 0x7C, ear_pa_gain);
  2311. }
  2312. return 0;
  2313. }
  2314. static int wcd938x_get_compander(struct snd_kcontrol *kcontrol,
  2315. struct snd_ctl_elem_value *ucontrol)
  2316. {
  2317. struct snd_soc_component *component =
  2318. snd_soc_kcontrol_component(kcontrol);
  2319. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2320. bool hphr;
  2321. struct soc_multi_mixer_control *mc;
  2322. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2323. hphr = mc->shift;
  2324. ucontrol->value.integer.value[0] = hphr ? wcd938x->comp2_enable :
  2325. wcd938x->comp1_enable;
  2326. return 0;
  2327. }
  2328. static int wcd938x_set_compander(struct snd_kcontrol *kcontrol,
  2329. struct snd_ctl_elem_value *ucontrol)
  2330. {
  2331. struct snd_soc_component *component =
  2332. snd_soc_kcontrol_component(kcontrol);
  2333. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2334. int value = ucontrol->value.integer.value[0];
  2335. bool hphr;
  2336. struct soc_multi_mixer_control *mc;
  2337. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2338. hphr = mc->shift;
  2339. if (hphr)
  2340. wcd938x->comp2_enable = value;
  2341. else
  2342. wcd938x->comp1_enable = value;
  2343. return 0;
  2344. }
  2345. static int wcd938x_codec_enable_vdd_buck(struct snd_soc_dapm_widget *w,
  2346. struct snd_kcontrol *kcontrol,
  2347. int event)
  2348. {
  2349. struct snd_soc_component *component =
  2350. snd_soc_dapm_to_component(w->dapm);
  2351. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2352. struct wcd938x_pdata *pdata = NULL;
  2353. int ret = 0;
  2354. pdata = dev_get_platdata(wcd938x->dev);
  2355. if (!pdata) {
  2356. dev_err(component->dev, "%s: pdata is NULL\n", __func__);
  2357. return -EINVAL;
  2358. }
  2359. if (!msm_cdc_is_ondemand_supply(wcd938x->dev,
  2360. wcd938x->supplies,
  2361. pdata->regulator,
  2362. pdata->num_supplies,
  2363. "cdc-vdd-buck"))
  2364. return 0;
  2365. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  2366. w->name, event);
  2367. switch (event) {
  2368. case SND_SOC_DAPM_PRE_PMU:
  2369. if (test_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask)) {
  2370. dev_dbg(component->dev,
  2371. "%s: buck already in enabled state\n",
  2372. __func__);
  2373. clear_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask);
  2374. return 0;
  2375. }
  2376. ret = msm_cdc_enable_ondemand_supply(wcd938x->dev,
  2377. wcd938x->supplies,
  2378. pdata->regulator,
  2379. pdata->num_supplies,
  2380. "cdc-vdd-buck");
  2381. if (ret == -EINVAL) {
  2382. dev_err(component->dev, "%s: vdd buck is not enabled\n",
  2383. __func__);
  2384. return ret;
  2385. }
  2386. clear_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask);
  2387. /*
  2388. * 200us sleep is required after LDO is enabled as per
  2389. * HW requirement
  2390. */
  2391. usleep_range(200, 250);
  2392. break;
  2393. case SND_SOC_DAPM_POST_PMD:
  2394. set_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask);
  2395. break;
  2396. }
  2397. return 0;
  2398. }
  2399. static int wcd938x_ldoh_get(struct snd_kcontrol *kcontrol,
  2400. struct snd_ctl_elem_value *ucontrol)
  2401. {
  2402. struct snd_soc_component *component =
  2403. snd_soc_kcontrol_component(kcontrol);
  2404. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2405. ucontrol->value.integer.value[0] = wcd938x->ldoh;
  2406. return 0;
  2407. }
  2408. static int wcd938x_ldoh_put(struct snd_kcontrol *kcontrol,
  2409. struct snd_ctl_elem_value *ucontrol)
  2410. {
  2411. struct snd_soc_component *component =
  2412. snd_soc_kcontrol_component(kcontrol);
  2413. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2414. wcd938x->ldoh = ucontrol->value.integer.value[0];
  2415. return 0;
  2416. }
  2417. const char * const tx_master_ch_text[] = {
  2418. "ZERO", "SWRM_TX1_CH1", "SWRM_TX1_CH2", "SWRM_TX1_CH3", "SWRM_TX1_CH4",
  2419. "SWRM_TX2_CH1", "SWRM_TX2_CH2", "SWRM_TX2_CH3", "SWRM_TX2_CH4",
  2420. "SWRM_TX3_CH1", "SWRM_TX3_CH2", "SWRM_TX3_CH3", "SWRM_TX3_CH4",
  2421. "SWRM_PCM_IN",
  2422. };
  2423. const struct soc_enum tx_master_ch_enum =
  2424. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_master_ch_text),
  2425. tx_master_ch_text);
  2426. static void wcd938x_tx_get_slave_ch_type_idx(const char *wname, int *ch_idx)
  2427. {
  2428. u8 ch_type = 0;
  2429. if (strnstr(wname, "ADC1", sizeof("ADC1")))
  2430. ch_type = ADC1;
  2431. else if (strnstr(wname, "ADC2", sizeof("ADC2")))
  2432. ch_type = ADC2;
  2433. else if (strnstr(wname, "ADC3", sizeof("ADC3")))
  2434. ch_type = ADC3;
  2435. else if (strnstr(wname, "ADC4", sizeof("ADC4")))
  2436. ch_type = ADC4;
  2437. else if (strnstr(wname, "DMIC0", sizeof("DMIC0")))
  2438. ch_type = DMIC0;
  2439. else if (strnstr(wname, "DMIC1", sizeof("DMIC1")))
  2440. ch_type = DMIC1;
  2441. else if (strnstr(wname, "MBHC", sizeof("MBHC")))
  2442. ch_type = MBHC;
  2443. else if (strnstr(wname, "DMIC2", sizeof("DMIC2")))
  2444. ch_type = DMIC2;
  2445. else if (strnstr(wname, "DMIC3", sizeof("DMIC3")))
  2446. ch_type = DMIC3;
  2447. else if (strnstr(wname, "DMIC4", sizeof("DMIC4")))
  2448. ch_type = DMIC4;
  2449. else if (strnstr(wname, "DMIC5", sizeof("DMIC5")))
  2450. ch_type = DMIC5;
  2451. else if (strnstr(wname, "DMIC6", sizeof("DMIC6")))
  2452. ch_type = DMIC6;
  2453. else if (strnstr(wname, "DMIC7", sizeof("DMIC7")))
  2454. ch_type = DMIC7;
  2455. else
  2456. pr_err("%s: port name: %s is not listed\n", __func__, wname);
  2457. if (ch_type)
  2458. *ch_idx = wcd938x_slave_get_slave_ch_val(ch_type);
  2459. else
  2460. *ch_idx = -EINVAL;
  2461. }
  2462. static int wcd938x_tx_master_ch_get(struct snd_kcontrol *kcontrol,
  2463. struct snd_ctl_elem_value *ucontrol)
  2464. {
  2465. struct snd_soc_component *component =
  2466. snd_soc_kcontrol_component(kcontrol);
  2467. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2468. int slave_ch_idx;
  2469. wcd938x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2470. if (slave_ch_idx != -EINVAL)
  2471. ucontrol->value.integer.value[0] =
  2472. wcd938x_slave_get_master_ch_val(
  2473. wcd938x->tx_master_ch_map[slave_ch_idx]);
  2474. return 0;
  2475. }
  2476. static int wcd938x_tx_master_ch_put(struct snd_kcontrol *kcontrol,
  2477. struct snd_ctl_elem_value *ucontrol)
  2478. {
  2479. struct snd_soc_component *component =
  2480. snd_soc_kcontrol_component(kcontrol);
  2481. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2482. int slave_ch_idx;
  2483. wcd938x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2484. dev_dbg(component->dev, "%s: slave_ch_idx: %d", __func__, slave_ch_idx);
  2485. dev_dbg(component->dev, "%s: ucontrol->value.enumerated.item[0] = %ld\n",
  2486. __func__, ucontrol->value.enumerated.item[0]);
  2487. if (slave_ch_idx != -EINVAL)
  2488. wcd938x->tx_master_ch_map[slave_ch_idx] =
  2489. wcd938x_slave_get_master_ch(
  2490. ucontrol->value.enumerated.item[0]);
  2491. return 0;
  2492. }
  2493. static int wcd938x_bcs_get(struct snd_kcontrol *kcontrol,
  2494. struct snd_ctl_elem_value *ucontrol)
  2495. {
  2496. struct snd_soc_component *component =
  2497. snd_soc_kcontrol_component(kcontrol);
  2498. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2499. ucontrol->value.integer.value[0] = wcd938x->bcs_dis;
  2500. return 0;
  2501. }
  2502. static int wcd938x_bcs_put(struct snd_kcontrol *kcontrol,
  2503. struct snd_ctl_elem_value *ucontrol)
  2504. {
  2505. struct snd_soc_component *component =
  2506. snd_soc_kcontrol_component(kcontrol);
  2507. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2508. wcd938x->bcs_dis = ucontrol->value.integer.value[0];
  2509. return 0;
  2510. }
  2511. static const char * const tx_mode_mux_text_wcd9380[] = {
  2512. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  2513. };
  2514. static const struct soc_enum tx_mode_mux_enum_wcd9380 =
  2515. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text_wcd9380),
  2516. tx_mode_mux_text_wcd9380);
  2517. static const char * const tx_mode_mux_text[] = {
  2518. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  2519. "ADC_ULP1", "ADC_ULP2",
  2520. };
  2521. static const struct soc_enum tx_mode_mux_enum =
  2522. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text),
  2523. tx_mode_mux_text);
  2524. static const char * const rx_hph_mode_mux_text_wcd9380[] = {
  2525. "CLS_H_INVALID", "CLS_H_INVALID_1", "CLS_H_LP", "CLS_AB",
  2526. "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_H_INVALID_2", "CLS_AB_LP",
  2527. "CLS_AB_LOHIFI",
  2528. };
  2529. static const char * const wcd938x_ear_pa_gain_text[] = {
  2530. "G_6_DB", "G_4P5_DB", "G_3_DB", "G_1P5_DB", "G_0_DB",
  2531. "G_M1P5_DB", "G_M3_DB", "G_M4P5_DB",
  2532. "G_M6_DB", "G_7P5_DB", "G_M9_DB",
  2533. "G_M10P5_DB", "G_M12_DB", "G_M13P5_DB",
  2534. "G_M15_DB", "G_M16P5_DB", "G_M18_DB",
  2535. };
  2536. static const struct soc_enum rx_hph_mode_mux_enum_wcd9380 =
  2537. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text_wcd9380),
  2538. rx_hph_mode_mux_text_wcd9380);
  2539. static SOC_ENUM_SINGLE_EXT_DECL(wcd938x_ear_pa_gain_enum,
  2540. wcd938x_ear_pa_gain_text);
  2541. static const char * const rx_hph_mode_mux_text[] = {
  2542. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  2543. "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI",
  2544. };
  2545. static const struct soc_enum rx_hph_mode_mux_enum =
  2546. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  2547. rx_hph_mode_mux_text);
  2548. static const struct snd_kcontrol_new wcd9380_snd_controls[] = {
  2549. SOC_ENUM_EXT("EAR PA GAIN", wcd938x_ear_pa_gain_enum,
  2550. wcd938x_ear_pa_gain_get, wcd938x_ear_pa_gain_put),
  2551. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum_wcd9380,
  2552. wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
  2553. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum_wcd9380,
  2554. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2555. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum_wcd9380,
  2556. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2557. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum_wcd9380,
  2558. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2559. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum_wcd9380,
  2560. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2561. };
  2562. static const struct snd_kcontrol_new wcd9385_snd_controls[] = {
  2563. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  2564. wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
  2565. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum,
  2566. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2567. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum,
  2568. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2569. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum,
  2570. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2571. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum,
  2572. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2573. };
  2574. static const struct snd_kcontrol_new wcd938x_snd_controls[] = {
  2575. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  2576. wcd938x_get_compander, wcd938x_set_compander),
  2577. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  2578. wcd938x_get_compander, wcd938x_set_compander),
  2579. SOC_SINGLE_EXT("LDOH Enable", SND_SOC_NOPM, 0, 1, 0,
  2580. wcd938x_ldoh_get, wcd938x_ldoh_put),
  2581. SOC_SINGLE_EXT("ADC2_BCS Disable", SND_SOC_NOPM, 0, 1, 0,
  2582. wcd938x_bcs_get, wcd938x_bcs_put),
  2583. SOC_SINGLE_TLV("HPHL Volume", WCD938X_HPH_L_EN, 0, 20, 1, line_gain),
  2584. SOC_SINGLE_TLV("HPHR Volume", WCD938X_HPH_R_EN, 0, 20, 1, line_gain),
  2585. SOC_SINGLE_TLV("ADC1 Volume", WCD938X_ANA_TX_CH1, 0, 20, 0,
  2586. analog_gain),
  2587. SOC_SINGLE_TLV("ADC2 Volume", WCD938X_ANA_TX_CH2, 0, 20, 0,
  2588. analog_gain),
  2589. SOC_SINGLE_TLV("ADC3 Volume", WCD938X_ANA_TX_CH3, 0, 20, 0,
  2590. analog_gain),
  2591. SOC_SINGLE_TLV("ADC4 Volume", WCD938X_ANA_TX_CH4, 0, 20, 0,
  2592. analog_gain),
  2593. SOC_ENUM_EXT("ADC1 ChMap", tx_master_ch_enum,
  2594. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2595. SOC_ENUM_EXT("ADC2 ChMap", tx_master_ch_enum,
  2596. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2597. SOC_ENUM_EXT("ADC3 ChMap", tx_master_ch_enum,
  2598. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2599. SOC_ENUM_EXT("ADC4 ChMap", tx_master_ch_enum,
  2600. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2601. SOC_ENUM_EXT("DMIC0 ChMap", tx_master_ch_enum,
  2602. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2603. SOC_ENUM_EXT("DMIC1 ChMap", tx_master_ch_enum,
  2604. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2605. SOC_ENUM_EXT("MBHC ChMap", tx_master_ch_enum,
  2606. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2607. SOC_ENUM_EXT("DMIC2 ChMap", tx_master_ch_enum,
  2608. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2609. SOC_ENUM_EXT("DMIC3 ChMap", tx_master_ch_enum,
  2610. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2611. SOC_ENUM_EXT("DMIC4 ChMap", tx_master_ch_enum,
  2612. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2613. SOC_ENUM_EXT("DMIC5 ChMap", tx_master_ch_enum,
  2614. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2615. SOC_ENUM_EXT("DMIC6 ChMap", tx_master_ch_enum,
  2616. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2617. SOC_ENUM_EXT("DMIC7 ChMap", tx_master_ch_enum,
  2618. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2619. };
  2620. static const struct snd_kcontrol_new adc1_switch[] = {
  2621. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2622. };
  2623. static const struct snd_kcontrol_new adc2_switch[] = {
  2624. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2625. };
  2626. static const struct snd_kcontrol_new adc3_switch[] = {
  2627. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2628. };
  2629. static const struct snd_kcontrol_new adc4_switch[] = {
  2630. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2631. };
  2632. static const struct snd_kcontrol_new dmic1_switch[] = {
  2633. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2634. };
  2635. static const struct snd_kcontrol_new dmic2_switch[] = {
  2636. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2637. };
  2638. static const struct snd_kcontrol_new dmic3_switch[] = {
  2639. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2640. };
  2641. static const struct snd_kcontrol_new dmic4_switch[] = {
  2642. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2643. };
  2644. static const struct snd_kcontrol_new dmic5_switch[] = {
  2645. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2646. };
  2647. static const struct snd_kcontrol_new dmic6_switch[] = {
  2648. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2649. };
  2650. static const struct snd_kcontrol_new dmic7_switch[] = {
  2651. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2652. };
  2653. static const struct snd_kcontrol_new dmic8_switch[] = {
  2654. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2655. };
  2656. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  2657. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2658. };
  2659. static const struct snd_kcontrol_new aux_rdac_switch[] = {
  2660. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2661. };
  2662. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  2663. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2664. };
  2665. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  2666. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2667. };
  2668. static const char * const adc2_mux_text[] = {
  2669. "INP2", "INP3"
  2670. };
  2671. static const struct soc_enum adc2_enum =
  2672. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 7,
  2673. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  2674. static const struct snd_kcontrol_new tx_adc2_mux =
  2675. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  2676. static const char * const adc3_mux_text[] = {
  2677. "INP4", "INP6"
  2678. };
  2679. static const struct soc_enum adc3_enum =
  2680. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 6,
  2681. ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
  2682. static const struct snd_kcontrol_new tx_adc3_mux =
  2683. SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
  2684. static const char * const adc4_mux_text[] = {
  2685. "INP5", "INP7"
  2686. };
  2687. static const struct soc_enum adc4_enum =
  2688. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 5,
  2689. ARRAY_SIZE(adc4_mux_text), adc4_mux_text);
  2690. static const struct snd_kcontrol_new tx_adc4_mux =
  2691. SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum);
  2692. static const char * const rdac3_mux_text[] = {
  2693. "RX1", "RX3"
  2694. };
  2695. static const char * const hdr12_mux_text[] = {
  2696. "NO_HDR12", "HDR12"
  2697. };
  2698. static const struct soc_enum hdr12_enum =
  2699. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 4,
  2700. ARRAY_SIZE(hdr12_mux_text), hdr12_mux_text);
  2701. static const struct snd_kcontrol_new tx_hdr12_mux =
  2702. SOC_DAPM_ENUM("HDR12 MUX Mux", hdr12_enum);
  2703. static const char * const hdr34_mux_text[] = {
  2704. "NO_HDR34", "HDR34"
  2705. };
  2706. static const struct soc_enum hdr34_enum =
  2707. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 3,
  2708. ARRAY_SIZE(hdr34_mux_text), hdr34_mux_text);
  2709. static const struct snd_kcontrol_new tx_hdr34_mux =
  2710. SOC_DAPM_ENUM("HDR34 MUX Mux", hdr34_enum);
  2711. static const struct soc_enum rdac3_enum =
  2712. SOC_ENUM_SINGLE(WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0,
  2713. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  2714. static const struct snd_kcontrol_new rx_rdac3_mux =
  2715. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  2716. static const struct snd_soc_dapm_widget wcd938x_dapm_widgets[] = {
  2717. /*input widgets*/
  2718. SND_SOC_DAPM_INPUT("AMIC1"),
  2719. SND_SOC_DAPM_INPUT("AMIC2"),
  2720. SND_SOC_DAPM_INPUT("AMIC3"),
  2721. SND_SOC_DAPM_INPUT("AMIC4"),
  2722. SND_SOC_DAPM_INPUT("AMIC5"),
  2723. SND_SOC_DAPM_INPUT("AMIC6"),
  2724. SND_SOC_DAPM_INPUT("AMIC7"),
  2725. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  2726. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  2727. SND_SOC_DAPM_INPUT("IN3_AUX"),
  2728. /*tx widgets*/
  2729. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  2730. wcd938x_codec_enable_adc,
  2731. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2732. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
  2733. wcd938x_codec_enable_adc,
  2734. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2735. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
  2736. wcd938x_codec_enable_adc,
  2737. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2738. SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0,
  2739. wcd938x_codec_enable_adc,
  2740. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2741. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  2742. wcd938x_codec_enable_dmic,
  2743. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2744. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  2745. wcd938x_codec_enable_dmic,
  2746. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2747. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  2748. wcd938x_codec_enable_dmic,
  2749. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2750. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  2751. wcd938x_codec_enable_dmic,
  2752. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2753. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  2754. wcd938x_codec_enable_dmic,
  2755. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2756. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  2757. wcd938x_codec_enable_dmic,
  2758. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2759. SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0,
  2760. wcd938x_codec_enable_dmic,
  2761. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2762. SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0,
  2763. wcd938x_codec_enable_dmic,
  2764. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2765. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  2766. NULL, 0, wcd938x_enable_req,
  2767. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2768. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0,
  2769. NULL, 0, wcd938x_enable_req,
  2770. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2771. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0,
  2772. NULL, 0, wcd938x_enable_req,
  2773. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2774. SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0,
  2775. NULL, 0, wcd938x_enable_req,
  2776. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2777. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  2778. &tx_adc2_mux),
  2779. SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0,
  2780. &tx_adc3_mux),
  2781. SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0,
  2782. &tx_adc4_mux),
  2783. SND_SOC_DAPM_MUX("HDR12 MUX", SND_SOC_NOPM, 0, 0,
  2784. &tx_hdr12_mux),
  2785. SND_SOC_DAPM_MUX("HDR34 MUX", SND_SOC_NOPM, 0, 0,
  2786. &tx_hdr34_mux),
  2787. /*tx mixers*/
  2788. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, ADC1, 0,
  2789. adc1_switch, ARRAY_SIZE(adc1_switch),
  2790. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2791. SND_SOC_DAPM_POST_PMD),
  2792. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, ADC2, 0,
  2793. adc2_switch, ARRAY_SIZE(adc2_switch),
  2794. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2795. SND_SOC_DAPM_POST_PMD),
  2796. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, ADC3, 0, adc3_switch,
  2797. ARRAY_SIZE(adc3_switch), wcd938x_tx_swr_ctrl,
  2798. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2799. SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, ADC4, 0, adc4_switch,
  2800. ARRAY_SIZE(adc4_switch), wcd938x_tx_swr_ctrl,
  2801. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2802. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, DMIC1,
  2803. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  2804. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2805. SND_SOC_DAPM_POST_PMD),
  2806. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, DMIC2,
  2807. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  2808. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2809. SND_SOC_DAPM_POST_PMD),
  2810. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, DMIC3,
  2811. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  2812. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2813. SND_SOC_DAPM_POST_PMD),
  2814. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, DMIC4,
  2815. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  2816. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2817. SND_SOC_DAPM_POST_PMD),
  2818. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, DMIC5,
  2819. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  2820. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2821. SND_SOC_DAPM_POST_PMD),
  2822. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, DMIC6,
  2823. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  2824. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2825. SND_SOC_DAPM_POST_PMD),
  2826. SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, DMIC7,
  2827. 0, dmic7_switch, ARRAY_SIZE(dmic7_switch),
  2828. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2829. SND_SOC_DAPM_POST_PMD),
  2830. SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, DMIC8,
  2831. 0, dmic8_switch, ARRAY_SIZE(dmic8_switch),
  2832. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2833. SND_SOC_DAPM_POST_PMD),
  2834. /* micbias widgets*/
  2835. SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2836. wcd938x_codec_enable_micbias,
  2837. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2838. SND_SOC_DAPM_POST_PMD),
  2839. SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2840. wcd938x_codec_enable_micbias,
  2841. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2842. SND_SOC_DAPM_POST_PMD),
  2843. SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2844. wcd938x_codec_enable_micbias,
  2845. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2846. SND_SOC_DAPM_POST_PMD),
  2847. SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, 0, 0,
  2848. wcd938x_codec_enable_micbias,
  2849. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2850. SND_SOC_DAPM_POST_PMD),
  2851. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS1_STANDALONE, SND_SOC_NOPM, 0, 0,
  2852. wcd938x_codec_force_enable_micbias,
  2853. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2854. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS2_STANDALONE, SND_SOC_NOPM, 0, 0,
  2855. wcd938x_codec_force_enable_micbias,
  2856. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2857. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS3_STANDALONE, SND_SOC_NOPM, 0, 0,
  2858. wcd938x_codec_force_enable_micbias,
  2859. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2860. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS4_STANDALONE, SND_SOC_NOPM, 0, 0,
  2861. wcd938x_codec_force_enable_micbias,
  2862. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2863. SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0,
  2864. wcd938x_codec_enable_vdd_buck,
  2865. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2866. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  2867. wcd938x_enable_clsh,
  2868. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2869. /*rx widgets*/
  2870. SND_SOC_DAPM_PGA_E("EAR PGA", WCD938X_ANA_EAR, 7, 0, NULL, 0,
  2871. wcd938x_codec_enable_ear_pa,
  2872. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2873. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2874. SND_SOC_DAPM_PGA_E("AUX PGA", WCD938X_AUX_AUXPA, 7, 0, NULL, 0,
  2875. wcd938x_codec_enable_aux_pa,
  2876. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2877. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2878. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD938X_ANA_HPH, 7, 0, NULL, 0,
  2879. wcd938x_codec_enable_hphl_pa,
  2880. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2881. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2882. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD938X_ANA_HPH, 6, 0, NULL, 0,
  2883. wcd938x_codec_enable_hphr_pa,
  2884. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2885. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2886. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  2887. wcd938x_codec_hphl_dac_event,
  2888. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2889. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2890. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  2891. wcd938x_codec_hphr_dac_event,
  2892. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2893. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2894. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  2895. wcd938x_codec_ear_dac_event,
  2896. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2897. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2898. SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
  2899. wcd938x_codec_aux_dac_event,
  2900. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2901. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2902. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  2903. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  2904. wcd938x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  2905. SND_SOC_DAPM_POST_PMD),
  2906. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  2907. wcd938x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  2908. SND_SOC_DAPM_POST_PMD),
  2909. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  2910. wcd938x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  2911. SND_SOC_DAPM_POST_PMD),
  2912. /* rx mixer widgets*/
  2913. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  2914. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  2915. SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
  2916. aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
  2917. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  2918. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  2919. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  2920. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  2921. /*output widgets tx*/
  2922. SND_SOC_DAPM_OUTPUT("WCD_TX_OUTPUT"),
  2923. /*output widgets rx*/
  2924. SND_SOC_DAPM_OUTPUT("EAR"),
  2925. SND_SOC_DAPM_OUTPUT("AUX"),
  2926. SND_SOC_DAPM_OUTPUT("HPHL"),
  2927. SND_SOC_DAPM_OUTPUT("HPHR"),
  2928. /* micbias pull up widgets*/
  2929. SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2930. wcd938x_codec_enable_micbias_pullup,
  2931. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2932. SND_SOC_DAPM_POST_PMD),
  2933. SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2934. wcd938x_codec_enable_micbias_pullup,
  2935. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2936. SND_SOC_DAPM_POST_PMD),
  2937. SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2938. wcd938x_codec_enable_micbias_pullup,
  2939. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2940. SND_SOC_DAPM_POST_PMD),
  2941. SND_SOC_DAPM_SUPPLY("VA MIC BIAS4", SND_SOC_NOPM, 0, 0,
  2942. wcd938x_codec_enable_micbias_pullup,
  2943. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2944. SND_SOC_DAPM_POST_PMD),
  2945. };
  2946. static const struct snd_soc_dapm_route wcd938x_audio_map[] = {
  2947. {"WCD_TX_OUTPUT", NULL, "ADC1_MIXER"},
  2948. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  2949. {"ADC1 REQ", NULL, "ADC1"},
  2950. {"ADC1", NULL, "AMIC1"},
  2951. {"WCD_TX_OUTPUT", NULL, "ADC2_MIXER"},
  2952. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  2953. {"ADC2 REQ", NULL, "ADC2"},
  2954. {"ADC2", NULL, "HDR12 MUX"},
  2955. {"HDR12 MUX", "NO_HDR12", "ADC2 MUX"},
  2956. {"HDR12 MUX", "HDR12", "AMIC1"},
  2957. {"ADC2 MUX", "INP3", "AMIC3"},
  2958. {"ADC2 MUX", "INP2", "AMIC2"},
  2959. {"WCD_TX_OUTPUT", NULL, "ADC3_MIXER"},
  2960. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  2961. {"ADC3 REQ", NULL, "ADC3"},
  2962. {"ADC3", NULL, "HDR34 MUX"},
  2963. {"HDR34 MUX", "NO_HDR34", "ADC3 MUX"},
  2964. {"HDR34 MUX", "HDR34", "AMIC5"},
  2965. {"ADC3 MUX", "INP4", "AMIC4"},
  2966. {"ADC3 MUX", "INP6", "AMIC6"},
  2967. {"WCD_TX_OUTPUT", NULL, "ADC4_MIXER"},
  2968. {"ADC4_MIXER", "Switch", "ADC4 REQ"},
  2969. {"ADC4 REQ", NULL, "ADC4"},
  2970. {"ADC4", NULL, "ADC4 MUX"},
  2971. {"ADC4 MUX", "INP5", "AMIC5"},
  2972. {"ADC4 MUX", "INP7", "AMIC7"},
  2973. {"WCD_TX_OUTPUT", NULL, "DMIC1_MIXER"},
  2974. {"DMIC1_MIXER", "Switch", "DMIC1"},
  2975. {"WCD_TX_OUTPUT", NULL, "DMIC2_MIXER"},
  2976. {"DMIC2_MIXER", "Switch", "DMIC2"},
  2977. {"WCD_TX_OUTPUT", NULL, "DMIC3_MIXER"},
  2978. {"DMIC3_MIXER", "Switch", "DMIC3"},
  2979. {"WCD_TX_OUTPUT", NULL, "DMIC4_MIXER"},
  2980. {"DMIC4_MIXER", "Switch", "DMIC4"},
  2981. {"WCD_TX_OUTPUT", NULL, "DMIC5_MIXER"},
  2982. {"DMIC5_MIXER", "Switch", "DMIC5"},
  2983. {"WCD_TX_OUTPUT", NULL, "DMIC6_MIXER"},
  2984. {"DMIC6_MIXER", "Switch", "DMIC6"},
  2985. {"WCD_TX_OUTPUT", NULL, "DMIC7_MIXER"},
  2986. {"DMIC7_MIXER", "Switch", "DMIC7"},
  2987. {"WCD_TX_OUTPUT", NULL, "DMIC8_MIXER"},
  2988. {"DMIC8_MIXER", "Switch", "DMIC8"},
  2989. {"IN1_HPHL", NULL, "VDD_BUCK"},
  2990. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  2991. {"RX1", NULL, "IN1_HPHL"},
  2992. {"RDAC1", NULL, "RX1"},
  2993. {"HPHL_RDAC", "Switch", "RDAC1"},
  2994. {"HPHL PGA", NULL, "HPHL_RDAC"},
  2995. {"HPHL", NULL, "HPHL PGA"},
  2996. {"IN2_HPHR", NULL, "VDD_BUCK"},
  2997. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  2998. {"RX2", NULL, "IN2_HPHR"},
  2999. {"RDAC2", NULL, "RX2"},
  3000. {"HPHR_RDAC", "Switch", "RDAC2"},
  3001. {"HPHR PGA", NULL, "HPHR_RDAC"},
  3002. {"HPHR", NULL, "HPHR PGA"},
  3003. {"IN3_AUX", NULL, "VDD_BUCK"},
  3004. {"IN3_AUX", NULL, "CLS_H_PORT"},
  3005. {"RX3", NULL, "IN3_AUX"},
  3006. {"RDAC4", NULL, "RX3"},
  3007. {"AUX_RDAC", "Switch", "RDAC4"},
  3008. {"AUX PGA", NULL, "AUX_RDAC"},
  3009. {"AUX", NULL, "AUX PGA"},
  3010. {"RDAC3_MUX", "RX3", "RX3"},
  3011. {"RDAC3_MUX", "RX1", "RX1"},
  3012. {"RDAC3", NULL, "RDAC3_MUX"},
  3013. {"EAR_RDAC", "Switch", "RDAC3"},
  3014. {"EAR PGA", NULL, "EAR_RDAC"},
  3015. {"EAR", NULL, "EAR PGA"},
  3016. };
  3017. static ssize_t wcd938x_version_read(struct snd_info_entry *entry,
  3018. void *file_private_data,
  3019. struct file *file,
  3020. char __user *buf, size_t count,
  3021. loff_t pos)
  3022. {
  3023. struct wcd938x_priv *priv;
  3024. char buffer[WCD938X_VERSION_ENTRY_SIZE];
  3025. int len = 0;
  3026. priv = (struct wcd938x_priv *) entry->private_data;
  3027. if (!priv) {
  3028. pr_err("%s: wcd938x priv is null\n", __func__);
  3029. return -EINVAL;
  3030. }
  3031. switch (priv->version) {
  3032. case WCD938X_VERSION_1_0:
  3033. len = snprintf(buffer, sizeof(buffer), "WCD938X_1_0\n");
  3034. break;
  3035. default:
  3036. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  3037. }
  3038. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  3039. }
  3040. static struct snd_info_entry_ops wcd938x_info_ops = {
  3041. .read = wcd938x_version_read,
  3042. };
  3043. static ssize_t wcd938x_variant_read(struct snd_info_entry *entry,
  3044. void *file_private_data,
  3045. struct file *file,
  3046. char __user *buf, size_t count,
  3047. loff_t pos)
  3048. {
  3049. struct wcd938x_priv *priv;
  3050. char buffer[WCD938X_VARIANT_ENTRY_SIZE];
  3051. int len = 0;
  3052. priv = (struct wcd938x_priv *) entry->private_data;
  3053. if (!priv) {
  3054. pr_err("%s: wcd938x priv is null\n", __func__);
  3055. return -EINVAL;
  3056. }
  3057. switch (priv->variant) {
  3058. case WCD9380:
  3059. len = snprintf(buffer, sizeof(buffer), "WCD9380\n");
  3060. break;
  3061. case WCD9385:
  3062. len = snprintf(buffer, sizeof(buffer), "WCD9385\n");
  3063. break;
  3064. default:
  3065. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  3066. }
  3067. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  3068. }
  3069. static struct snd_info_entry_ops wcd938x_variant_ops = {
  3070. .read = wcd938x_variant_read,
  3071. };
  3072. /*
  3073. * wcd938x_get_codec_variant
  3074. * @component: component instance
  3075. *
  3076. * Return: codec variant or -EINVAL in error.
  3077. */
  3078. int wcd938x_get_codec_variant(struct snd_soc_component *component)
  3079. {
  3080. struct wcd938x_priv *priv = NULL;
  3081. if (!component)
  3082. return -EINVAL;
  3083. priv = snd_soc_component_get_drvdata(component);
  3084. if (!priv) {
  3085. dev_err(component->dev,
  3086. "%s:wcd938x not probed\n", __func__);
  3087. return 0;
  3088. }
  3089. return priv->variant;
  3090. }
  3091. EXPORT_SYMBOL(wcd938x_get_codec_variant);
  3092. /*
  3093. * wcd938x_info_create_codec_entry - creates wcd938x module
  3094. * @codec_root: The parent directory
  3095. * @component: component instance
  3096. *
  3097. * Creates wcd938x module, variant and version entry under the given
  3098. * parent directory.
  3099. *
  3100. * Return: 0 on success or negative error code on failure.
  3101. */
  3102. int wcd938x_info_create_codec_entry(struct snd_info_entry *codec_root,
  3103. struct snd_soc_component *component)
  3104. {
  3105. struct snd_info_entry *version_entry;
  3106. struct snd_info_entry *variant_entry;
  3107. struct wcd938x_priv *priv;
  3108. struct snd_soc_card *card;
  3109. if (!codec_root || !component)
  3110. return -EINVAL;
  3111. priv = snd_soc_component_get_drvdata(component);
  3112. if (priv->entry) {
  3113. dev_dbg(priv->dev,
  3114. "%s:wcd938x module already created\n", __func__);
  3115. return 0;
  3116. }
  3117. card = component->card;
  3118. priv->entry = snd_info_create_module_entry(codec_root->module,
  3119. "wcd938x", codec_root);
  3120. if (!priv->entry) {
  3121. dev_dbg(component->dev, "%s: failed to create wcd938x entry\n",
  3122. __func__);
  3123. return -ENOMEM;
  3124. }
  3125. priv->entry->mode = S_IFDIR | 0555;
  3126. if (snd_info_register(priv->entry) < 0) {
  3127. snd_info_free_entry(priv->entry);
  3128. return -ENOMEM;
  3129. }
  3130. version_entry = snd_info_create_card_entry(card->snd_card,
  3131. "version",
  3132. priv->entry);
  3133. if (!version_entry) {
  3134. dev_dbg(component->dev, "%s: failed to create wcd938x version entry\n",
  3135. __func__);
  3136. snd_info_free_entry(priv->entry);
  3137. return -ENOMEM;
  3138. }
  3139. version_entry->private_data = priv;
  3140. version_entry->size = WCD938X_VERSION_ENTRY_SIZE;
  3141. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  3142. version_entry->c.ops = &wcd938x_info_ops;
  3143. if (snd_info_register(version_entry) < 0) {
  3144. snd_info_free_entry(version_entry);
  3145. snd_info_free_entry(priv->entry);
  3146. return -ENOMEM;
  3147. }
  3148. priv->version_entry = version_entry;
  3149. variant_entry = snd_info_create_card_entry(card->snd_card,
  3150. "variant",
  3151. priv->entry);
  3152. if (!variant_entry) {
  3153. dev_dbg(component->dev, "%s: failed to create wcd938x variant entry\n",
  3154. __func__);
  3155. snd_info_free_entry(version_entry);
  3156. snd_info_free_entry(priv->entry);
  3157. return -ENOMEM;
  3158. }
  3159. variant_entry->private_data = priv;
  3160. variant_entry->size = WCD938X_VARIANT_ENTRY_SIZE;
  3161. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  3162. variant_entry->c.ops = &wcd938x_variant_ops;
  3163. if (snd_info_register(variant_entry) < 0) {
  3164. snd_info_free_entry(variant_entry);
  3165. snd_info_free_entry(version_entry);
  3166. snd_info_free_entry(priv->entry);
  3167. return -ENOMEM;
  3168. }
  3169. priv->variant_entry = variant_entry;
  3170. return 0;
  3171. }
  3172. EXPORT_SYMBOL(wcd938x_info_create_codec_entry);
  3173. static int wcd938x_set_micbias_data(struct wcd938x_priv *wcd938x,
  3174. struct wcd938x_pdata *pdata)
  3175. {
  3176. int vout_ctl_1 = 0, vout_ctl_2 = 0, vout_ctl_3 = 0, vout_ctl_4 = 0;
  3177. int rc = 0;
  3178. if (!pdata) {
  3179. dev_err(wcd938x->dev, "%s: NULL pdata\n", __func__);
  3180. return -ENODEV;
  3181. }
  3182. /* set micbias voltage */
  3183. vout_ctl_1 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb1_mv);
  3184. vout_ctl_2 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb2_mv);
  3185. vout_ctl_3 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb3_mv);
  3186. vout_ctl_4 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb4_mv);
  3187. if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0 ||
  3188. vout_ctl_4 < 0) {
  3189. rc = -EINVAL;
  3190. goto done;
  3191. }
  3192. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB1, 0x3F,
  3193. vout_ctl_1);
  3194. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB2, 0x3F,
  3195. vout_ctl_2);
  3196. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB3, 0x3F,
  3197. vout_ctl_3);
  3198. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB4, 0x3F,
  3199. vout_ctl_4);
  3200. done:
  3201. return rc;
  3202. }
  3203. static int wcd938x_soc_codec_probe(struct snd_soc_component *component)
  3204. {
  3205. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  3206. struct snd_soc_dapm_context *dapm =
  3207. snd_soc_component_get_dapm(component);
  3208. int variant;
  3209. int ret = -EINVAL;
  3210. dev_info(component->dev, "%s()\n", __func__);
  3211. wcd938x = snd_soc_component_get_drvdata(component);
  3212. if (!wcd938x)
  3213. return -EINVAL;
  3214. wcd938x->component = component;
  3215. snd_soc_component_init_regmap(component, wcd938x->regmap);
  3216. variant = (snd_soc_component_read32(component,
  3217. WCD938X_DIGITAL_EFUSE_REG_0) & 0x1E) >> 1;
  3218. wcd938x->variant = variant;
  3219. wcd938x->fw_data = devm_kzalloc(component->dev,
  3220. sizeof(*(wcd938x->fw_data)),
  3221. GFP_KERNEL);
  3222. if (!wcd938x->fw_data) {
  3223. dev_err(component->dev, "Failed to allocate fw_data\n");
  3224. ret = -ENOMEM;
  3225. goto err;
  3226. }
  3227. set_bit(WCD9XXX_MBHC_CAL, wcd938x->fw_data->cal_bit);
  3228. ret = wcd_cal_create_hwdep(wcd938x->fw_data,
  3229. WCD9XXX_CODEC_HWDEP_NODE, component);
  3230. if (ret < 0) {
  3231. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  3232. goto err_hwdep;
  3233. }
  3234. ret = wcd938x_mbhc_init(&wcd938x->mbhc, component, wcd938x->fw_data);
  3235. if (ret) {
  3236. pr_err("%s: mbhc initialization failed\n", __func__);
  3237. goto err_hwdep;
  3238. }
  3239. snd_soc_dapm_ignore_suspend(dapm, "WCD938X_AIF Playback");
  3240. snd_soc_dapm_ignore_suspend(dapm, "WCD938X_AIF Capture");
  3241. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  3242. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  3243. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  3244. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  3245. snd_soc_dapm_ignore_suspend(dapm, "AMIC5");
  3246. snd_soc_dapm_ignore_suspend(dapm, "AMIC6");
  3247. snd_soc_dapm_ignore_suspend(dapm, "AMIC7");
  3248. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_OUTPUT");
  3249. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  3250. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  3251. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  3252. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  3253. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  3254. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  3255. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  3256. snd_soc_dapm_sync(dapm);
  3257. wcd_cls_h_init(&wcd938x->clsh_info);
  3258. wcd938x_init_reg(component);
  3259. if (wcd938x->variant == WCD9380) {
  3260. ret = snd_soc_add_component_controls(component, wcd9380_snd_controls,
  3261. ARRAY_SIZE(wcd9380_snd_controls));
  3262. if (ret < 0) {
  3263. dev_err(component->dev,
  3264. "%s: Failed to add snd ctrls for variant: %d\n",
  3265. __func__, wcd938x->variant);
  3266. goto err_hwdep;
  3267. }
  3268. }
  3269. if (wcd938x->variant == WCD9385) {
  3270. ret = snd_soc_add_component_controls(component, wcd9385_snd_controls,
  3271. ARRAY_SIZE(wcd9385_snd_controls));
  3272. if (ret < 0) {
  3273. dev_err(component->dev,
  3274. "%s: Failed to add snd ctrls for variant: %d\n",
  3275. __func__, wcd938x->variant);
  3276. goto err_hwdep;
  3277. }
  3278. }
  3279. wcd938x->version = WCD938X_VERSION_1_0;
  3280. /* Register event notifier */
  3281. wcd938x->nblock.notifier_call = wcd938x_event_notify;
  3282. if (wcd938x->register_notifier) {
  3283. ret = wcd938x->register_notifier(wcd938x->handle,
  3284. &wcd938x->nblock,
  3285. true);
  3286. if (ret) {
  3287. dev_err(component->dev,
  3288. "%s: Failed to register notifier %d\n",
  3289. __func__, ret);
  3290. return ret;
  3291. }
  3292. }
  3293. wcd938x->dev_up = true;
  3294. return ret;
  3295. err_hwdep:
  3296. wcd938x->fw_data = NULL;
  3297. err:
  3298. return ret;
  3299. }
  3300. static void wcd938x_soc_codec_remove(struct snd_soc_component *component)
  3301. {
  3302. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  3303. if (!wcd938x) {
  3304. dev_err(component->dev, "%s: wcd938x is already NULL\n",
  3305. __func__);
  3306. return;
  3307. }
  3308. if (wcd938x->register_notifier)
  3309. wcd938x->register_notifier(wcd938x->handle,
  3310. &wcd938x->nblock,
  3311. false);
  3312. }
  3313. static struct snd_soc_component_driver soc_codec_dev_wcd938x = {
  3314. .name = WCD938X_DRV_NAME,
  3315. .probe = wcd938x_soc_codec_probe,
  3316. .remove = wcd938x_soc_codec_remove,
  3317. .controls = wcd938x_snd_controls,
  3318. .num_controls = ARRAY_SIZE(wcd938x_snd_controls),
  3319. .dapm_widgets = wcd938x_dapm_widgets,
  3320. .num_dapm_widgets = ARRAY_SIZE(wcd938x_dapm_widgets),
  3321. .dapm_routes = wcd938x_audio_map,
  3322. .num_dapm_routes = ARRAY_SIZE(wcd938x_audio_map),
  3323. };
  3324. static int wcd938x_reset(struct device *dev)
  3325. {
  3326. struct wcd938x_priv *wcd938x = NULL;
  3327. int rc = 0;
  3328. int value = 0;
  3329. if (!dev)
  3330. return -ENODEV;
  3331. wcd938x = dev_get_drvdata(dev);
  3332. if (!wcd938x)
  3333. return -EINVAL;
  3334. if (!wcd938x->rst_np) {
  3335. dev_err(dev, "%s: reset gpio device node not specified\n",
  3336. __func__);
  3337. return -EINVAL;
  3338. }
  3339. value = msm_cdc_pinctrl_get_state(wcd938x->rst_np);
  3340. if (value > 0)
  3341. return 0;
  3342. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  3343. if (rc) {
  3344. dev_err(dev, "%s: wcd sleep state request fail!\n",
  3345. __func__);
  3346. return rc;
  3347. }
  3348. /* 20us sleep required after pulling the reset gpio to LOW */
  3349. usleep_range(20, 30);
  3350. rc = msm_cdc_pinctrl_select_active_state(wcd938x->rst_np);
  3351. if (rc) {
  3352. dev_err(dev, "%s: wcd active state request fail!\n",
  3353. __func__);
  3354. return rc;
  3355. }
  3356. /* 20us sleep required after pulling the reset gpio to HIGH */
  3357. usleep_range(20, 30);
  3358. return rc;
  3359. }
  3360. static int wcd938x_read_of_property_u32(struct device *dev, const char *name,
  3361. u32 *val)
  3362. {
  3363. int rc = 0;
  3364. rc = of_property_read_u32(dev->of_node, name, val);
  3365. if (rc)
  3366. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  3367. __func__, name, dev->of_node->full_name);
  3368. return rc;
  3369. }
  3370. static void wcd938x_dt_parse_micbias_info(struct device *dev,
  3371. struct wcd938x_micbias_setting *mb)
  3372. {
  3373. u32 prop_val = 0;
  3374. int rc = 0;
  3375. /* MB1 */
  3376. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  3377. NULL)) {
  3378. rc = wcd938x_read_of_property_u32(dev,
  3379. "qcom,cdc-micbias1-mv",
  3380. &prop_val);
  3381. if (!rc)
  3382. mb->micb1_mv = prop_val;
  3383. } else {
  3384. dev_info(dev, "%s: Micbias1 DT property not found\n",
  3385. __func__);
  3386. }
  3387. /* MB2 */
  3388. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  3389. NULL)) {
  3390. rc = wcd938x_read_of_property_u32(dev,
  3391. "qcom,cdc-micbias2-mv",
  3392. &prop_val);
  3393. if (!rc)
  3394. mb->micb2_mv = prop_val;
  3395. } else {
  3396. dev_info(dev, "%s: Micbias2 DT property not found\n",
  3397. __func__);
  3398. }
  3399. /* MB3 */
  3400. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  3401. NULL)) {
  3402. rc = wcd938x_read_of_property_u32(dev,
  3403. "qcom,cdc-micbias3-mv",
  3404. &prop_val);
  3405. if (!rc)
  3406. mb->micb3_mv = prop_val;
  3407. } else {
  3408. dev_info(dev, "%s: Micbias3 DT property not found\n",
  3409. __func__);
  3410. }
  3411. /* MB4 */
  3412. if (of_find_property(dev->of_node, "qcom,cdc-micbias4-mv",
  3413. NULL)) {
  3414. rc = wcd938x_read_of_property_u32(dev,
  3415. "qcom,cdc-micbias4-mv",
  3416. &prop_val);
  3417. if (!rc)
  3418. mb->micb4_mv = prop_val;
  3419. } else {
  3420. dev_info(dev, "%s: Micbias4 DT property not found\n",
  3421. __func__);
  3422. }
  3423. }
  3424. static int wcd938x_reset_low(struct device *dev)
  3425. {
  3426. struct wcd938x_priv *wcd938x = NULL;
  3427. int rc = 0;
  3428. if (!dev)
  3429. return -ENODEV;
  3430. wcd938x = dev_get_drvdata(dev);
  3431. if (!wcd938x)
  3432. return -EINVAL;
  3433. if (!wcd938x->rst_np) {
  3434. dev_err(dev, "%s: reset gpio device node not specified\n",
  3435. __func__);
  3436. return -EINVAL;
  3437. }
  3438. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  3439. if (rc) {
  3440. dev_err(dev, "%s: wcd sleep state request fail!\n",
  3441. __func__);
  3442. return rc;
  3443. }
  3444. /* 20us sleep required after pulling the reset gpio to LOW */
  3445. usleep_range(20, 30);
  3446. return rc;
  3447. }
  3448. struct wcd938x_pdata *wcd938x_populate_dt_data(struct device *dev)
  3449. {
  3450. struct wcd938x_pdata *pdata = NULL;
  3451. pdata = devm_kzalloc(dev, sizeof(struct wcd938x_pdata),
  3452. GFP_KERNEL);
  3453. if (!pdata)
  3454. return NULL;
  3455. pdata->rst_np = of_parse_phandle(dev->of_node,
  3456. "qcom,wcd-rst-gpio-node", 0);
  3457. if (!pdata->rst_np) {
  3458. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  3459. __func__, "qcom,wcd-rst-gpio-node",
  3460. dev->of_node->full_name);
  3461. return NULL;
  3462. }
  3463. /* Parse power supplies */
  3464. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  3465. &pdata->num_supplies);
  3466. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  3467. dev_err(dev, "%s: no power supplies defined for codec\n",
  3468. __func__);
  3469. return NULL;
  3470. }
  3471. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  3472. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  3473. wcd938x_dt_parse_micbias_info(dev, &pdata->micbias);
  3474. return pdata;
  3475. }
  3476. static irqreturn_t wcd938x_wd_handle_irq(int irq, void *data)
  3477. {
  3478. pr_err_ratelimited("%s: Watchdog interrupt for irq =%d triggered\n",
  3479. __func__, irq);
  3480. return IRQ_HANDLED;
  3481. }
  3482. static struct snd_soc_dai_driver wcd938x_dai[] = {
  3483. {
  3484. .name = "wcd938x_cdc",
  3485. .playback = {
  3486. .stream_name = "WCD938X_AIF Playback",
  3487. .rates = WCD938X_RATES | WCD938X_FRAC_RATES,
  3488. .formats = WCD938X_FORMATS,
  3489. .rate_max = 192000,
  3490. .rate_min = 8000,
  3491. .channels_min = 1,
  3492. .channels_max = 4,
  3493. },
  3494. .capture = {
  3495. .stream_name = "WCD938X_AIF Capture",
  3496. .rates = WCD938X_RATES | WCD938X_FRAC_RATES,
  3497. .formats = WCD938X_FORMATS,
  3498. .rate_max = 192000,
  3499. .rate_min = 8000,
  3500. .channels_min = 1,
  3501. .channels_max = 4,
  3502. },
  3503. },
  3504. };
  3505. static int wcd938x_bind(struct device *dev)
  3506. {
  3507. int ret = 0, i = 0;
  3508. struct wcd938x_pdata *pdata = dev_get_platdata(dev);
  3509. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  3510. /*
  3511. * Add 5msec delay to provide sufficient time for
  3512. * soundwire auto enumeration of slave devices as
  3513. * as per HW requirement.
  3514. */
  3515. usleep_range(5000, 5010);
  3516. ret = component_bind_all(dev, wcd938x);
  3517. if (ret) {
  3518. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  3519. __func__, ret);
  3520. return ret;
  3521. }
  3522. wcd938x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  3523. if (!wcd938x->rx_swr_dev) {
  3524. dev_err(dev, "%s: Could not find RX swr slave device\n",
  3525. __func__);
  3526. ret = -ENODEV;
  3527. goto err;
  3528. }
  3529. wcd938x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  3530. if (!wcd938x->tx_swr_dev) {
  3531. dev_err(dev, "%s: Could not find TX swr slave device\n",
  3532. __func__);
  3533. ret = -ENODEV;
  3534. goto err;
  3535. }
  3536. wcd938x->regmap = devm_regmap_init_swr(wcd938x->tx_swr_dev,
  3537. &wcd938x_regmap_config);
  3538. if (!wcd938x->regmap) {
  3539. dev_err(dev, "%s: Regmap init failed\n",
  3540. __func__);
  3541. goto err;
  3542. }
  3543. /* Set all interupts as edge triggered */
  3544. for (i = 0; i < wcd938x_regmap_irq_chip.num_regs; i++)
  3545. regmap_write(wcd938x->regmap,
  3546. (WCD938X_DIGITAL_INTR_LEVEL_0 + i), 0);
  3547. wcd938x_regmap_irq_chip.irq_drv_data = wcd938x;
  3548. wcd938x->irq_info.wcd_regmap_irq_chip = &wcd938x_regmap_irq_chip;
  3549. wcd938x->irq_info.codec_name = "WCD938X";
  3550. wcd938x->irq_info.regmap = wcd938x->regmap;
  3551. wcd938x->irq_info.dev = dev;
  3552. ret = wcd_irq_init(&wcd938x->irq_info, &wcd938x->virq);
  3553. if (ret) {
  3554. dev_err(wcd938x->dev, "%s: IRQ init failed: %d\n",
  3555. __func__, ret);
  3556. goto err;
  3557. }
  3558. wcd938x->tx_swr_dev->slave_irq = wcd938x->virq;
  3559. ret = wcd938x_set_micbias_data(wcd938x, pdata);
  3560. if (ret < 0) {
  3561. dev_err(dev, "%s: bad micbias pdata\n", __func__);
  3562. goto err_irq;
  3563. }
  3564. /* Request for watchdog interrupt */
  3565. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT,
  3566. "HPHR PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3567. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT,
  3568. "HPHL PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3569. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT,
  3570. "AUX PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3571. /* Disable watchdog interrupt for HPH and AUX */
  3572. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT);
  3573. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT);
  3574. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT);
  3575. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd938x,
  3576. wcd938x_dai, ARRAY_SIZE(wcd938x_dai));
  3577. if (ret) {
  3578. dev_err(dev, "%s: Codec registration failed\n",
  3579. __func__);
  3580. goto err_irq;
  3581. }
  3582. return ret;
  3583. err_irq:
  3584. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  3585. err:
  3586. component_unbind_all(dev, wcd938x);
  3587. return ret;
  3588. }
  3589. static void wcd938x_unbind(struct device *dev)
  3590. {
  3591. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  3592. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT, NULL);
  3593. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT, NULL);
  3594. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT, NULL);
  3595. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  3596. snd_soc_unregister_component(dev);
  3597. component_unbind_all(dev, wcd938x);
  3598. }
  3599. static const struct of_device_id wcd938x_dt_match[] = {
  3600. { .compatible = "qcom,wcd938x-codec", .data = "wcd938x"},
  3601. {}
  3602. };
  3603. static const struct component_master_ops wcd938x_comp_ops = {
  3604. .bind = wcd938x_bind,
  3605. .unbind = wcd938x_unbind,
  3606. };
  3607. static int wcd938x_compare_of(struct device *dev, void *data)
  3608. {
  3609. return dev->of_node == data;
  3610. }
  3611. static void wcd938x_release_of(struct device *dev, void *data)
  3612. {
  3613. of_node_put(data);
  3614. }
  3615. static int wcd938x_add_slave_components(struct device *dev,
  3616. struct component_match **matchptr)
  3617. {
  3618. struct device_node *np, *rx_node, *tx_node;
  3619. np = dev->of_node;
  3620. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  3621. if (!rx_node) {
  3622. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  3623. return -ENODEV;
  3624. }
  3625. of_node_get(rx_node);
  3626. component_match_add_release(dev, matchptr,
  3627. wcd938x_release_of,
  3628. wcd938x_compare_of,
  3629. rx_node);
  3630. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  3631. if (!tx_node) {
  3632. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  3633. return -ENODEV;
  3634. }
  3635. of_node_get(tx_node);
  3636. component_match_add_release(dev, matchptr,
  3637. wcd938x_release_of,
  3638. wcd938x_compare_of,
  3639. tx_node);
  3640. return 0;
  3641. }
  3642. static int wcd938x_probe(struct platform_device *pdev)
  3643. {
  3644. struct component_match *match = NULL;
  3645. struct wcd938x_priv *wcd938x = NULL;
  3646. struct wcd938x_pdata *pdata = NULL;
  3647. struct wcd_ctrl_platform_data *plat_data = NULL;
  3648. struct device *dev = &pdev->dev;
  3649. int ret;
  3650. wcd938x = devm_kzalloc(dev, sizeof(struct wcd938x_priv),
  3651. GFP_KERNEL);
  3652. if (!wcd938x)
  3653. return -ENOMEM;
  3654. dev_set_drvdata(dev, wcd938x);
  3655. wcd938x->dev = dev;
  3656. pdata = wcd938x_populate_dt_data(dev);
  3657. if (!pdata) {
  3658. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  3659. return -EINVAL;
  3660. }
  3661. dev->platform_data = pdata;
  3662. wcd938x->rst_np = pdata->rst_np;
  3663. ret = msm_cdc_init_supplies(dev, &wcd938x->supplies,
  3664. pdata->regulator, pdata->num_supplies);
  3665. if (!wcd938x->supplies) {
  3666. dev_err(dev, "%s: Cannot init wcd supplies\n",
  3667. __func__);
  3668. return ret;
  3669. }
  3670. plat_data = dev_get_platdata(dev->parent);
  3671. if (!plat_data) {
  3672. dev_err(dev, "%s: platform data from parent is NULL\n",
  3673. __func__);
  3674. return -EINVAL;
  3675. }
  3676. wcd938x->handle = (void *)plat_data->handle;
  3677. if (!wcd938x->handle) {
  3678. dev_err(dev, "%s: handle is NULL\n", __func__);
  3679. return -EINVAL;
  3680. }
  3681. wcd938x->update_wcd_event = plat_data->update_wcd_event;
  3682. if (!wcd938x->update_wcd_event) {
  3683. dev_err(dev, "%s: update_wcd_event api is null!\n",
  3684. __func__);
  3685. return -EINVAL;
  3686. }
  3687. wcd938x->register_notifier = plat_data->register_notifier;
  3688. if (!wcd938x->register_notifier) {
  3689. dev_err(dev, "%s: register_notifier api is null!\n",
  3690. __func__);
  3691. return -EINVAL;
  3692. }
  3693. ret = msm_cdc_enable_static_supplies(&pdev->dev, wcd938x->supplies,
  3694. pdata->regulator,
  3695. pdata->num_supplies);
  3696. if (ret) {
  3697. dev_err(dev, "%s: wcd static supply enable failed!\n",
  3698. __func__);
  3699. return ret;
  3700. }
  3701. ret = wcd938x_parse_port_mapping(dev, "qcom,rx_swr_ch_map",
  3702. CODEC_RX);
  3703. ret |= wcd938x_parse_port_mapping(dev, "qcom,tx_swr_ch_map",
  3704. CODEC_TX);
  3705. if (ret) {
  3706. dev_err(dev, "Failed to read port mapping\n");
  3707. goto err;
  3708. }
  3709. mutex_init(&wcd938x->wakeup_lock);
  3710. mutex_init(&wcd938x->micb_lock);
  3711. ret = wcd938x_add_slave_components(dev, &match);
  3712. if (ret)
  3713. goto err_lock_init;
  3714. wcd938x_reset(dev);
  3715. wcd938x->wakeup = wcd938x_wakeup;
  3716. return component_master_add_with_match(dev,
  3717. &wcd938x_comp_ops, match);
  3718. err_lock_init:
  3719. mutex_destroy(&wcd938x->micb_lock);
  3720. mutex_destroy(&wcd938x->wakeup_lock);
  3721. err:
  3722. return ret;
  3723. }
  3724. static int wcd938x_remove(struct platform_device *pdev)
  3725. {
  3726. struct wcd938x_priv *wcd938x = NULL;
  3727. wcd938x = platform_get_drvdata(pdev);
  3728. component_master_del(&pdev->dev, &wcd938x_comp_ops);
  3729. mutex_destroy(&wcd938x->micb_lock);
  3730. mutex_destroy(&wcd938x->wakeup_lock);
  3731. dev_set_drvdata(&pdev->dev, NULL);
  3732. return 0;
  3733. }
  3734. #ifdef CONFIG_PM_SLEEP
  3735. static int wcd938x_suspend(struct device *dev)
  3736. {
  3737. struct wcd938x_priv *wcd938x = NULL;
  3738. int ret = 0;
  3739. struct wcd938x_pdata *pdata = NULL;
  3740. if (!dev)
  3741. return -ENODEV;
  3742. wcd938x = dev_get_drvdata(dev);
  3743. if (!wcd938x)
  3744. return -EINVAL;
  3745. pdata = dev_get_platdata(wcd938x->dev);
  3746. if (!pdata) {
  3747. dev_err(dev, "%s: pdata is NULL\n", __func__);
  3748. return -EINVAL;
  3749. }
  3750. if (test_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask)) {
  3751. ret = msm_cdc_disable_ondemand_supply(wcd938x->dev,
  3752. wcd938x->supplies,
  3753. pdata->regulator,
  3754. pdata->num_supplies,
  3755. "cdc-vdd-buck");
  3756. if (ret == -EINVAL) {
  3757. dev_err(dev, "%s: vdd buck is not disabled\n",
  3758. __func__);
  3759. return 0;
  3760. }
  3761. clear_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask);
  3762. }
  3763. return 0;
  3764. }
  3765. static int wcd938x_resume(struct device *dev)
  3766. {
  3767. return 0;
  3768. }
  3769. static const struct dev_pm_ops wcd938x_dev_pm_ops = {
  3770. SET_SYSTEM_SLEEP_PM_OPS(
  3771. wcd938x_suspend,
  3772. wcd938x_resume
  3773. )
  3774. };
  3775. #endif
  3776. static struct platform_driver wcd938x_codec_driver = {
  3777. .probe = wcd938x_probe,
  3778. .remove = wcd938x_remove,
  3779. .driver = {
  3780. .name = "wcd938x_codec",
  3781. .owner = THIS_MODULE,
  3782. .of_match_table = of_match_ptr(wcd938x_dt_match),
  3783. #ifdef CONFIG_PM_SLEEP
  3784. .pm = &wcd938x_dev_pm_ops,
  3785. #endif
  3786. .suppress_bind_attrs = true,
  3787. },
  3788. };
  3789. module_platform_driver(wcd938x_codec_driver);
  3790. MODULE_DESCRIPTION("WCD938X Codec driver");
  3791. MODULE_LICENSE("GPL v2");