dp_rx_mon_status.c 48 KB

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  1. /*
  2. * Copyright (c) 2017-2019 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "hal_hw_headers.h"
  19. #include "dp_types.h"
  20. #include "dp_rx.h"
  21. #include "dp_peer.h"
  22. #include "hal_rx.h"
  23. #include "hal_api.h"
  24. #include "qdf_trace.h"
  25. #include "qdf_nbuf.h"
  26. #include "hal_api_mon.h"
  27. #include "dp_rx_mon.h"
  28. #include "dp_internal.h"
  29. #include "qdf_mem.h" /* qdf_mem_malloc,free */
  30. #include "htt.h"
  31. #ifdef FEATURE_PERPKT_INFO
  32. #include "dp_ratetable.h"
  33. #endif
  34. #ifdef WLAN_RX_PKT_CAPTURE_ENH
  35. #include "dp_rx_mon_feature.h"
  36. #else
  37. static QDF_STATUS
  38. dp_rx_handle_enh_capture(struct dp_soc *soc, struct dp_pdev *pdev,
  39. struct hal_rx_ppdu_info *ppdu_info)
  40. {
  41. return QDF_STATUS_SUCCESS;
  42. }
  43. static void
  44. dp_rx_mon_enh_capture_process(struct dp_pdev *pdev, uint32_t tlv_status,
  45. qdf_nbuf_t status_nbuf,
  46. struct hal_rx_ppdu_info *ppdu_info,
  47. bool *nbuf_used)
  48. {
  49. }
  50. #endif
  51. #ifdef WLAN_TX_PKT_CAPTURE_ENH
  52. #include "dp_rx_mon_feature.h"
  53. #else
  54. static QDF_STATUS
  55. dp_send_ack_frame_to_stack(struct dp_soc *soc,
  56. struct dp_pdev *pdev,
  57. struct hal_rx_ppdu_info *ppdu_info)
  58. {
  59. return QDF_STATUS_SUCCESS;
  60. }
  61. #endif
  62. #ifdef FEATURE_PERPKT_INFO
  63. static inline void
  64. dp_rx_populate_rx_rssi_chain(struct hal_rx_ppdu_info *ppdu_info,
  65. struct cdp_rx_indication_ppdu *cdp_rx_ppdu)
  66. {
  67. uint8_t chain, bw;
  68. int8_t rssi;
  69. for (chain = 0; chain < SS_COUNT; chain++) {
  70. for (bw = 0; bw < MAX_BW; bw++) {
  71. rssi = ppdu_info->rx_status.rssi_chain[chain][bw];
  72. if (rssi != DP_RSSI_INVAL)
  73. cdp_rx_ppdu->rssi_chain[chain][bw] = rssi;
  74. else
  75. cdp_rx_ppdu->rssi_chain[chain][bw] = 0;
  76. }
  77. }
  78. }
  79. /*
  80. * dp_rx_populate_su_evm_details() - Populate su evm info
  81. * @ppdu_info: ppdu info structure from ppdu ring
  82. * @cdp_rx_ppdu: rx ppdu indication structure
  83. */
  84. static inline void
  85. dp_rx_populate_su_evm_details(struct hal_rx_ppdu_info *ppdu_info,
  86. struct cdp_rx_indication_ppdu *cdp_rx_ppdu)
  87. {
  88. uint8_t pilot_evm;
  89. uint8_t nss_count;
  90. uint8_t pilot_count;
  91. nss_count = ppdu_info->evm_info.nss_count;
  92. pilot_count = ppdu_info->evm_info.pilot_count;
  93. if ((nss_count * pilot_count) > DP_RX_MAX_SU_EVM_COUNT) {
  94. qdf_err("pilot evm count is more than expected");
  95. return;
  96. }
  97. cdp_rx_ppdu->evm_info.pilot_count = pilot_count;
  98. cdp_rx_ppdu->evm_info.nss_count = nss_count;
  99. /* Populate evm for pilot_evm = nss_count*pilot_count */
  100. for (pilot_evm = 0; pilot_evm < nss_count * pilot_count; pilot_evm++) {
  101. cdp_rx_ppdu->evm_info.pilot_evm[pilot_evm] =
  102. ppdu_info->evm_info.pilot_evm[pilot_evm];
  103. }
  104. }
  105. /**
  106. * dp_rx_inc_rusize_cnt() - increment pdev stats based on RU size
  107. * @pdev: pdev ctx
  108. * @rx_user_status: mon rx user status
  109. *
  110. * Return: bool
  111. */
  112. static inline bool
  113. dp_rx_inc_rusize_cnt(struct dp_pdev *pdev,
  114. struct mon_rx_user_status *rx_user_status)
  115. {
  116. uint32_t ru_size;
  117. bool is_data;
  118. ru_size = rx_user_status->ofdma_ru_size;
  119. if (dp_is_subtype_data(rx_user_status->frame_control)) {
  120. DP_STATS_INC(pdev,
  121. ul_ofdma.data_rx_ru_size[ru_size], 1);
  122. is_data = true;
  123. } else {
  124. DP_STATS_INC(pdev,
  125. ul_ofdma.nondata_rx_ru_size[ru_size], 1);
  126. is_data = false;
  127. }
  128. return is_data;
  129. }
  130. /**
  131. * dp_rx_populate_cdp_indication_ppdu_user() - Populate per user cdp indication
  132. * @pdev: pdev ctx
  133. * @ppdu_info: ppdu info structure from ppdu ring
  134. * @ppdu_nbuf: qdf nbuf abstraction for linux skb
  135. *
  136. * Return: none
  137. */
  138. static inline void
  139. dp_rx_populate_cdp_indication_ppdu_user(struct dp_pdev *pdev,
  140. struct hal_rx_ppdu_info *ppdu_info,
  141. qdf_nbuf_t ppdu_nbuf)
  142. {
  143. struct dp_peer *peer;
  144. struct dp_soc *soc = pdev->soc;
  145. struct dp_ast_entry *ast_entry;
  146. struct cdp_rx_indication_ppdu *cdp_rx_ppdu;
  147. uint32_t ast_index;
  148. int i;
  149. struct mon_rx_user_status *rx_user_status;
  150. struct cdp_rx_stats_ppdu_user *rx_stats_peruser;
  151. int ru_size;
  152. bool is_data = false;
  153. uint32_t num_users;
  154. cdp_rx_ppdu = (struct cdp_rx_indication_ppdu *)ppdu_nbuf->data;
  155. num_users = ppdu_info->com_info.num_users;
  156. for (i = 0; i < num_users; i++) {
  157. if (i > OFDMA_NUM_USERS)
  158. return;
  159. rx_user_status = &ppdu_info->rx_user_status[i];
  160. rx_stats_peruser = &cdp_rx_ppdu->user[i];
  161. ast_index = rx_user_status->ast_index;
  162. if (ast_index >= wlan_cfg_get_max_ast_idx(soc->wlan_cfg_ctx)) {
  163. rx_stats_peruser->peer_id = HTT_INVALID_PEER;
  164. continue;
  165. }
  166. ast_entry = soc->ast_table[ast_index];
  167. if (!ast_entry) {
  168. rx_stats_peruser->peer_id = HTT_INVALID_PEER;
  169. continue;
  170. }
  171. peer = ast_entry->peer;
  172. if (!peer || peer->peer_ids[0] == HTT_INVALID_PEER) {
  173. rx_stats_peruser->peer_id = HTT_INVALID_PEER;
  174. continue;
  175. }
  176. rx_stats_peruser->first_data_seq_ctrl =
  177. rx_user_status->first_data_seq_ctrl;
  178. rx_stats_peruser->frame_control_info_valid =
  179. rx_user_status->frame_control_info_valid;
  180. rx_stats_peruser->frame_control =
  181. rx_user_status->frame_control;
  182. rx_stats_peruser->tcp_msdu_count =
  183. rx_user_status->tcp_msdu_count;
  184. rx_stats_peruser->udp_msdu_count =
  185. rx_user_status->udp_msdu_count;
  186. rx_stats_peruser->other_msdu_count =
  187. rx_user_status->other_msdu_count;
  188. rx_stats_peruser->num_msdu =
  189. rx_stats_peruser->tcp_msdu_count +
  190. rx_stats_peruser->udp_msdu_count +
  191. rx_stats_peruser->other_msdu_count;
  192. rx_stats_peruser->preamble_type =
  193. rx_user_status->preamble_type;
  194. rx_stats_peruser->mpdu_cnt_fcs_ok =
  195. rx_user_status->mpdu_cnt_fcs_ok;
  196. rx_stats_peruser->mpdu_cnt_fcs_err =
  197. rx_user_status->mpdu_cnt_fcs_err;
  198. qdf_mem_copy(&rx_stats_peruser->mpdu_fcs_ok_bitmap,
  199. &rx_user_status->mpdu_fcs_ok_bitmap,
  200. HAL_RX_NUM_WORDS_PER_PPDU_BITMAP *
  201. sizeof(rx_user_status->mpdu_fcs_ok_bitmap[0]));
  202. rx_stats_peruser->mpdu_ok_byte_count =
  203. rx_user_status->mpdu_ok_byte_count;
  204. rx_stats_peruser->mpdu_err_byte_count =
  205. rx_user_status->mpdu_err_byte_count;
  206. cdp_rx_ppdu->num_mpdu += rx_user_status->mpdu_cnt_fcs_ok;
  207. cdp_rx_ppdu->num_msdu += rx_stats_peruser->num_msdu;
  208. rx_stats_peruser->retries =
  209. CDP_FC_IS_RETRY_SET(rx_stats_peruser->frame_control) ?
  210. rx_stats_peruser->mpdu_cnt_fcs_ok : 0;
  211. if (rx_stats_peruser->mpdu_cnt_fcs_ok > 1)
  212. rx_stats_peruser->is_ampdu = 1;
  213. else
  214. rx_stats_peruser->is_ampdu = 0;
  215. rx_stats_peruser->tid = ppdu_info->rx_status.tid;
  216. qdf_mem_copy(rx_stats_peruser->mac_addr,
  217. peer->mac_addr.raw, QDF_MAC_ADDR_SIZE);
  218. rx_stats_peruser->peer_id = peer->peer_ids[0];
  219. cdp_rx_ppdu->vdev_id = peer->vdev->vdev_id;
  220. rx_stats_peruser->vdev_id = peer->vdev->vdev_id;
  221. rx_stats_peruser->mu_ul_info_valid = 0;
  222. if (cdp_rx_ppdu->u.ppdu_type == HAL_RX_TYPE_MU_OFDMA ||
  223. cdp_rx_ppdu->u.ppdu_type == HAL_RX_TYPE_MU_MIMO) {
  224. if (rx_user_status->mu_ul_info_valid) {
  225. rx_stats_peruser->nss = rx_user_status->nss;
  226. rx_stats_peruser->mcs = rx_user_status->mcs;
  227. rx_stats_peruser->mu_ul_info_valid =
  228. rx_user_status->mu_ul_info_valid;
  229. rx_stats_peruser->ofdma_ru_start_index =
  230. rx_user_status->ofdma_ru_start_index;
  231. rx_stats_peruser->ofdma_ru_width =
  232. rx_user_status->ofdma_ru_width;
  233. rx_stats_peruser->user_index = i;
  234. ru_size = rx_user_status->ofdma_ru_size;
  235. /*
  236. * max RU size will be equal to
  237. * HTT_UL_OFDMA_V0_RU_SIZE_RU_996x2
  238. */
  239. if (ru_size >= OFDMA_NUM_RU_SIZE) {
  240. dp_err("invalid ru_size %d\n",
  241. ru_size);
  242. return;
  243. }
  244. is_data = dp_rx_inc_rusize_cnt(pdev,
  245. rx_user_status);
  246. }
  247. if (is_data) {
  248. /* counter to get number of MU OFDMA */
  249. pdev->stats.ul_ofdma.data_rx_ppdu++;
  250. pdev->stats.ul_ofdma.data_users[num_users]++;
  251. }
  252. }
  253. }
  254. }
  255. /**
  256. * dp_rx_populate_cdp_indication_ppdu() - Populate cdp rx indication structure
  257. * @pdev: pdev ctx
  258. * @ppdu_info: ppdu info structure from ppdu ring
  259. * @ppdu_nbuf: qdf nbuf abstraction for linux skb
  260. *
  261. * Return: none
  262. */
  263. static inline void
  264. dp_rx_populate_cdp_indication_ppdu(struct dp_pdev *pdev,
  265. struct hal_rx_ppdu_info *ppdu_info,
  266. qdf_nbuf_t ppdu_nbuf)
  267. {
  268. struct dp_peer *peer;
  269. struct dp_soc *soc = pdev->soc;
  270. struct dp_ast_entry *ast_entry;
  271. struct cdp_rx_indication_ppdu *cdp_rx_ppdu;
  272. uint32_t ast_index;
  273. uint32_t i;
  274. cdp_rx_ppdu = (struct cdp_rx_indication_ppdu *)ppdu_nbuf->data;
  275. cdp_rx_ppdu->first_data_seq_ctrl =
  276. ppdu_info->rx_status.first_data_seq_ctrl;
  277. cdp_rx_ppdu->frame_ctrl =
  278. ppdu_info->rx_status.frame_control;
  279. cdp_rx_ppdu->tcp_msdu_count = ppdu_info->rx_status.tcp_msdu_count;
  280. cdp_rx_ppdu->udp_msdu_count = ppdu_info->rx_status.udp_msdu_count;
  281. cdp_rx_ppdu->other_msdu_count = ppdu_info->rx_status.other_msdu_count;
  282. cdp_rx_ppdu->u.preamble = ppdu_info->rx_status.preamble_type;
  283. /* num mpdu is consolidated and added together in num user loop */
  284. cdp_rx_ppdu->num_mpdu = ppdu_info->com_info.mpdu_cnt_fcs_ok;
  285. /* num msdu is consolidated and added together in num user loop */
  286. cdp_rx_ppdu->num_msdu = (cdp_rx_ppdu->tcp_msdu_count +
  287. cdp_rx_ppdu->udp_msdu_count +
  288. cdp_rx_ppdu->other_msdu_count);
  289. cdp_rx_ppdu->retries = CDP_FC_IS_RETRY_SET(cdp_rx_ppdu->frame_ctrl) ?
  290. ppdu_info->com_info.mpdu_cnt_fcs_ok : 0;
  291. if (ppdu_info->com_info.mpdu_cnt_fcs_ok > 1)
  292. cdp_rx_ppdu->is_ampdu = 1;
  293. else
  294. cdp_rx_ppdu->is_ampdu = 0;
  295. cdp_rx_ppdu->tid = ppdu_info->rx_status.tid;
  296. ast_index = ppdu_info->rx_status.ast_index;
  297. if (ast_index >= wlan_cfg_get_max_ast_idx(soc->wlan_cfg_ctx)) {
  298. cdp_rx_ppdu->peer_id = HTT_INVALID_PEER;
  299. return;
  300. }
  301. ast_entry = soc->ast_table[ast_index];
  302. if (!ast_entry) {
  303. cdp_rx_ppdu->peer_id = HTT_INVALID_PEER;
  304. return;
  305. }
  306. peer = ast_entry->peer;
  307. if (!peer || peer->peer_ids[0] == HTT_INVALID_PEER) {
  308. cdp_rx_ppdu->peer_id = HTT_INVALID_PEER;
  309. return;
  310. }
  311. qdf_mem_copy(cdp_rx_ppdu->mac_addr,
  312. peer->mac_addr.raw, QDF_MAC_ADDR_SIZE);
  313. cdp_rx_ppdu->peer_id = peer->peer_ids[0];
  314. cdp_rx_ppdu->vdev_id = peer->vdev->vdev_id;
  315. cdp_rx_ppdu->ppdu_id = ppdu_info->com_info.ppdu_id;
  316. cdp_rx_ppdu->length = ppdu_info->rx_status.ppdu_len;
  317. cdp_rx_ppdu->duration = ppdu_info->rx_status.duration;
  318. cdp_rx_ppdu->u.bw = ppdu_info->rx_status.bw;
  319. cdp_rx_ppdu->u.nss = ppdu_info->rx_status.nss;
  320. cdp_rx_ppdu->u.mcs = ppdu_info->rx_status.mcs;
  321. if ((ppdu_info->rx_status.sgi == VHT_SGI_NYSM) &&
  322. (ppdu_info->rx_status.preamble_type == HAL_RX_PKT_TYPE_11AC))
  323. cdp_rx_ppdu->u.gi = CDP_SGI_0_4_US;
  324. else
  325. cdp_rx_ppdu->u.gi = ppdu_info->rx_status.sgi;
  326. cdp_rx_ppdu->u.ldpc = ppdu_info->rx_status.ldpc;
  327. cdp_rx_ppdu->u.ppdu_type = ppdu_info->rx_status.reception_type;
  328. cdp_rx_ppdu->u.ltf_size = (ppdu_info->rx_status.he_data5 >>
  329. QDF_MON_STATUS_HE_LTF_SIZE_SHIFT) & 0x3;
  330. cdp_rx_ppdu->rssi = ppdu_info->rx_status.rssi_comb;
  331. cdp_rx_ppdu->timestamp = ppdu_info->rx_status.tsft;
  332. cdp_rx_ppdu->channel = ppdu_info->rx_status.chan_num;
  333. cdp_rx_ppdu->beamformed = ppdu_info->rx_status.beamformed;
  334. cdp_rx_ppdu->num_bytes = ppdu_info->rx_status.ppdu_len;
  335. cdp_rx_ppdu->lsig_a = ppdu_info->rx_status.rate;
  336. cdp_rx_ppdu->u.ltf_size = ppdu_info->rx_status.ltf_size;
  337. dp_rx_populate_rx_rssi_chain(ppdu_info, cdp_rx_ppdu);
  338. dp_rx_populate_su_evm_details(ppdu_info, cdp_rx_ppdu);
  339. cdp_rx_ppdu->rx_antenna = ppdu_info->rx_status.rx_antenna;
  340. cdp_rx_ppdu->nf = ppdu_info->rx_status.chan_noise_floor;
  341. for (i = 0; i < MAX_CHAIN; i++)
  342. cdp_rx_ppdu->per_chain_rssi[i] = ppdu_info->rx_status.rssi[i];
  343. cdp_rx_ppdu->is_mcast_bcast = ppdu_info->nac_info.mcast_bcast;
  344. cdp_rx_ppdu->num_users = ppdu_info->com_info.num_users;
  345. cdp_rx_ppdu->num_mpdu = 0;
  346. cdp_rx_ppdu->num_msdu = 0;
  347. dp_rx_populate_cdp_indication_ppdu_user(pdev, ppdu_info, ppdu_nbuf);
  348. }
  349. #else
  350. static inline void
  351. dp_rx_populate_cdp_indication_ppdu(struct dp_pdev *pdev,
  352. struct hal_rx_ppdu_info *ppdu_info,
  353. qdf_nbuf_t ppdu_nbuf)
  354. {
  355. }
  356. #endif
  357. /**
  358. * dp_rx_stats_update() - Update per-peer statistics
  359. * @soc: Datapath SOC handle
  360. * @peer: Datapath peer handle
  361. * @ppdu: PPDU Descriptor
  362. *
  363. * Return: None
  364. */
  365. #ifdef FEATURE_PERPKT_INFO
  366. static inline void dp_rx_rate_stats_update(struct dp_peer *peer,
  367. struct cdp_rx_indication_ppdu *ppdu,
  368. uint32_t user)
  369. {
  370. uint32_t ratekbps = 0;
  371. uint32_t ppdu_rx_rate = 0;
  372. uint32_t nss = 0;
  373. uint32_t rix;
  374. uint16_t ratecode;
  375. struct cdp_rx_stats_ppdu_user *ppdu_user;
  376. if (!peer || !ppdu)
  377. return;
  378. ppdu_user = &ppdu->user[user];
  379. if (ppdu_user->nss == 0)
  380. nss = 0;
  381. else
  382. nss = ppdu_user->nss - 1;
  383. ratekbps = dp_getrateindex(ppdu->u.gi,
  384. ppdu_user->mcs,
  385. nss,
  386. ppdu->u.preamble,
  387. ppdu->u.bw,
  388. &rix,
  389. &ratecode);
  390. if (!ratekbps)
  391. return;
  392. ppdu->rix = rix;
  393. DP_STATS_UPD(peer, rx.last_rx_rate, ratekbps);
  394. dp_ath_rate_lpf(peer->stats.rx.avg_rx_rate, ratekbps);
  395. ppdu_rx_rate = dp_ath_rate_out(peer->stats.rx.avg_rx_rate);
  396. DP_STATS_UPD(peer, rx.rnd_avg_rx_rate, ppdu_rx_rate);
  397. ppdu->rx_ratekbps = ratekbps;
  398. ppdu->rx_ratecode = ratecode;
  399. if (peer->vdev)
  400. peer->vdev->stats.rx.last_rx_rate = ratekbps;
  401. }
  402. static void dp_rx_stats_update(struct dp_pdev *pdev,
  403. struct cdp_rx_indication_ppdu *ppdu)
  404. {
  405. struct dp_soc *soc = NULL;
  406. uint8_t mcs, preamble, ac = 0, nss, ppdu_type;
  407. uint16_t num_msdu;
  408. uint8_t pkt_bw_offset;
  409. struct dp_peer *peer;
  410. struct cdp_rx_stats_ppdu_user *ppdu_user;
  411. uint32_t i;
  412. enum cdp_mu_packet_type mu_pkt_type;
  413. if (pdev)
  414. soc = pdev->soc;
  415. else
  416. return;
  417. if (!soc || soc->process_rx_status)
  418. return;
  419. preamble = ppdu->u.preamble;
  420. ppdu_type = ppdu->u.ppdu_type;
  421. for (i = 0; i < ppdu->num_users; i++) {
  422. ppdu_user = &ppdu->user[i];
  423. peer = dp_peer_find_by_id(soc, ppdu_user->peer_id);
  424. if (!peer)
  425. peer = pdev->invalid_peer;
  426. ppdu->cookie = (void *)peer->wlanstats_ctx;
  427. if (ppdu_type == HAL_RX_TYPE_SU) {
  428. mcs = ppdu->u.mcs;
  429. nss = ppdu->u.nss;
  430. } else {
  431. mcs = ppdu_user->mcs;
  432. nss = ppdu_user->nss;
  433. }
  434. num_msdu = ppdu_user->num_msdu;
  435. switch (ppdu->u.bw) {
  436. case CMN_BW_20MHZ:
  437. pkt_bw_offset = PKT_BW_GAIN_20MHZ;
  438. break;
  439. case CMN_BW_40MHZ:
  440. pkt_bw_offset = PKT_BW_GAIN_40MHZ;
  441. break;
  442. case CMN_BW_80MHZ:
  443. pkt_bw_offset = PKT_BW_GAIN_80MHZ;
  444. break;
  445. case CMN_BW_160MHZ:
  446. pkt_bw_offset = PKT_BW_GAIN_160MHZ;
  447. break;
  448. default:
  449. pkt_bw_offset = 0;
  450. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  451. "Invalid BW index = %d", ppdu->u.bw);
  452. }
  453. DP_STATS_UPD(peer, rx.rssi, (ppdu->rssi + pkt_bw_offset));
  454. if (peer->stats.rx.avg_rssi == INVALID_RSSI)
  455. peer->stats.rx.avg_rssi =
  456. CDP_RSSI_IN(peer->stats.rx.rssi);
  457. else
  458. CDP_RSSI_UPDATE_AVG(peer->stats.rx.avg_rssi,
  459. peer->stats.rx.rssi);
  460. if ((preamble == DOT11_A) || (preamble == DOT11_B))
  461. nss = 1;
  462. if (ppdu_type == HAL_RX_TYPE_SU) {
  463. if (nss) {
  464. DP_STATS_INC(peer, rx.nss[nss - 1], num_msdu);
  465. DP_STATS_INC(peer, rx.ppdu_nss[nss - 1], 1);
  466. }
  467. DP_STATS_INC(peer, rx.mpdu_cnt_fcs_ok,
  468. ppdu_user->mpdu_cnt_fcs_ok);
  469. DP_STATS_INC(peer, rx.mpdu_cnt_fcs_err,
  470. ppdu_user->mpdu_cnt_fcs_err);
  471. }
  472. if (ppdu_type >= HAL_RX_TYPE_MU_MIMO &&
  473. ppdu_type <= HAL_RX_TYPE_MU_OFDMA) {
  474. if (ppdu_type == HAL_RX_TYPE_MU_MIMO)
  475. mu_pkt_type = RX_TYPE_MU_MIMO;
  476. else
  477. mu_pkt_type = RX_TYPE_MU_OFDMA;
  478. if (nss) {
  479. DP_STATS_INC(peer, rx.nss[nss - 1], num_msdu);
  480. DP_STATS_INC(peer,
  481. rx.rx_mu[mu_pkt_type].ppdu_nss[nss - 1],
  482. 1);
  483. }
  484. DP_STATS_INC(peer,
  485. rx.rx_mu[mu_pkt_type].mpdu_cnt_fcs_ok,
  486. ppdu_user->mpdu_cnt_fcs_ok);
  487. DP_STATS_INC(peer,
  488. rx.rx_mu[mu_pkt_type].mpdu_cnt_fcs_err,
  489. ppdu_user->mpdu_cnt_fcs_err);
  490. }
  491. DP_STATS_INC(peer, rx.sgi_count[ppdu->u.gi], num_msdu);
  492. DP_STATS_INC(peer, rx.bw[ppdu->u.bw], num_msdu);
  493. DP_STATS_INC(peer, rx.reception_type[ppdu->u.ppdu_type],
  494. num_msdu);
  495. DP_STATS_INC(peer, rx.ppdu_cnt[ppdu->u.ppdu_type], 1);
  496. DP_STATS_INCC(peer, rx.ampdu_cnt, num_msdu,
  497. ppdu_user->is_ampdu);
  498. DP_STATS_INCC(peer, rx.non_ampdu_cnt, num_msdu,
  499. !(ppdu_user->is_ampdu));
  500. DP_STATS_UPD(peer, rx.rx_rate, mcs);
  501. DP_STATS_INCC(peer,
  502. rx.pkt_type[preamble].mcs_count[MAX_MCS - 1], num_msdu,
  503. ((mcs >= MAX_MCS_11A) && (preamble == DOT11_A)));
  504. DP_STATS_INCC(peer,
  505. rx.pkt_type[preamble].mcs_count[mcs], num_msdu,
  506. ((mcs < MAX_MCS_11A) && (preamble == DOT11_A)));
  507. DP_STATS_INCC(peer,
  508. rx.pkt_type[preamble].mcs_count[MAX_MCS - 1], num_msdu,
  509. ((mcs >= MAX_MCS_11B) && (preamble == DOT11_B)));
  510. DP_STATS_INCC(peer,
  511. rx.pkt_type[preamble].mcs_count[mcs], num_msdu,
  512. ((mcs < MAX_MCS_11B) && (preamble == DOT11_B)));
  513. DP_STATS_INCC(peer,
  514. rx.pkt_type[preamble].mcs_count[MAX_MCS - 1], num_msdu,
  515. ((mcs >= MAX_MCS_11A) && (preamble == DOT11_N)));
  516. DP_STATS_INCC(peer,
  517. rx.pkt_type[preamble].mcs_count[mcs], num_msdu,
  518. ((mcs < MAX_MCS_11A) && (preamble == DOT11_N)));
  519. DP_STATS_INCC(peer,
  520. rx.pkt_type[preamble].mcs_count[MAX_MCS - 1], num_msdu,
  521. ((mcs >= MAX_MCS_11AC) && (preamble == DOT11_AC)));
  522. DP_STATS_INCC(peer,
  523. rx.pkt_type[preamble].mcs_count[mcs], num_msdu,
  524. ((mcs < MAX_MCS_11AC) && (preamble == DOT11_AC)));
  525. DP_STATS_INCC(peer,
  526. rx.pkt_type[preamble].mcs_count[MAX_MCS - 1], num_msdu,
  527. ((mcs >= (MAX_MCS - 1)) && (preamble == DOT11_AX)));
  528. DP_STATS_INCC(peer,
  529. rx.pkt_type[preamble].mcs_count[mcs], num_msdu,
  530. ((mcs < (MAX_MCS - 1)) && (preamble == DOT11_AX)));
  531. DP_STATS_INCC(peer,
  532. rx.su_ax_ppdu_cnt.mcs_count[MAX_MCS - 1], 1,
  533. ((mcs >= (MAX_MCS - 1)) && (preamble == DOT11_AX) &&
  534. (ppdu_type == HAL_RX_TYPE_SU)));
  535. DP_STATS_INCC(peer,
  536. rx.su_ax_ppdu_cnt.mcs_count[mcs], 1,
  537. ((mcs < (MAX_MCS - 1)) && (preamble == DOT11_AX) &&
  538. (ppdu_type == HAL_RX_TYPE_SU)));
  539. DP_STATS_INCC(peer,
  540. rx.rx_mu[RX_TYPE_MU_OFDMA].ppdu.mcs_count[MAX_MCS - 1],
  541. 1, ((mcs >= (MAX_MCS - 1)) &&
  542. (preamble == DOT11_AX) &&
  543. (ppdu_type == HAL_RX_TYPE_MU_OFDMA)));
  544. DP_STATS_INCC(peer,
  545. rx.rx_mu[RX_TYPE_MU_OFDMA].ppdu.mcs_count[mcs],
  546. 1, ((mcs < (MAX_MCS - 1)) &&
  547. (preamble == DOT11_AX) &&
  548. (ppdu_type == HAL_RX_TYPE_MU_OFDMA)));
  549. DP_STATS_INCC(peer,
  550. rx.rx_mu[RX_TYPE_MU_MIMO].ppdu.mcs_count[MAX_MCS - 1],
  551. 1, ((mcs >= (MAX_MCS - 1)) &&
  552. (preamble == DOT11_AX) &&
  553. (ppdu_type == HAL_RX_TYPE_MU_MIMO)));
  554. DP_STATS_INCC(peer,
  555. rx.rx_mu[RX_TYPE_MU_MIMO].ppdu.mcs_count[mcs],
  556. 1, ((mcs < (MAX_MCS - 1)) &&
  557. (preamble == DOT11_AX) &&
  558. (ppdu_type == HAL_RX_TYPE_MU_MIMO)));
  559. /*
  560. * If invalid TID, it could be a non-qos frame, hence do not
  561. * update any AC counters
  562. */
  563. ac = TID_TO_WME_AC(ppdu_user->tid);
  564. if (ppdu->tid != HAL_TID_INVALID)
  565. DP_STATS_INC(peer, rx.wme_ac_type[ac], num_msdu);
  566. dp_peer_stats_notify(pdev, peer);
  567. DP_STATS_UPD(peer, rx.last_rssi, ppdu->rssi);
  568. if (peer == pdev->invalid_peer)
  569. continue;
  570. if (dp_is_subtype_data(ppdu->frame_ctrl))
  571. dp_rx_rate_stats_update(peer, ppdu, i);
  572. #if defined(FEATURE_PERPKT_INFO) && WDI_EVENT_ENABLE
  573. dp_wdi_event_handler(WDI_EVENT_UPDATE_DP_STATS, pdev->soc,
  574. &peer->stats, ppdu->peer_id,
  575. UPDATE_PEER_STATS, pdev->pdev_id);
  576. #endif
  577. dp_peer_unref_del_find_by_id(peer);
  578. }
  579. }
  580. #endif
  581. /*
  582. * dp_rx_get_fcs_ok_msdu() - get ppdu status buffer containing fcs_ok msdu
  583. * @pdev: pdev object
  584. * @ppdu_info: ppdu info object
  585. *
  586. * Return: nbuf
  587. */
  588. static inline qdf_nbuf_t
  589. dp_rx_get_fcs_ok_msdu(struct dp_pdev *pdev,
  590. struct hal_rx_ppdu_info *ppdu_info)
  591. {
  592. uint16_t mpdu_fcs_ok;
  593. qdf_nbuf_t status_nbuf = NULL;
  594. unsigned long *fcs_ok_bitmap;
  595. if (qdf_unlikely(qdf_nbuf_is_queue_empty(&pdev->rx_ppdu_buf_q)))
  596. return NULL;
  597. /* Obtain fcs_ok passed index from bitmap
  598. * this index is used to get fcs passed first msdu payload
  599. */
  600. fcs_ok_bitmap =
  601. (unsigned long *)&ppdu_info->com_info.mpdu_fcs_ok_bitmap[0];
  602. mpdu_fcs_ok = qdf_find_first_bit(fcs_ok_bitmap,
  603. HAL_RX_MAX_MPDU);
  604. if (qdf_unlikely(mpdu_fcs_ok >= HAL_RX_MAX_MPDU))
  605. goto end;
  606. if (qdf_unlikely(!ppdu_info->ppdu_msdu_info[mpdu_fcs_ok].nbuf))
  607. goto end;
  608. /* Get status buffer by indexing mpdu_fcs_ok index
  609. * containing first msdu payload with fcs passed
  610. * and clone the buffer
  611. */
  612. status_nbuf = ppdu_info->ppdu_msdu_info[mpdu_fcs_ok].nbuf;
  613. ppdu_info->ppdu_msdu_info[mpdu_fcs_ok].nbuf = NULL;
  614. /* Take ref of status nbuf as this nbuf is to be
  615. * freeed by upper layer.
  616. */
  617. qdf_nbuf_ref(status_nbuf);
  618. ppdu_info->fcs_ok_msdu_info.first_msdu_payload =
  619. ppdu_info->ppdu_msdu_info[mpdu_fcs_ok].first_msdu_payload;
  620. ppdu_info->fcs_ok_msdu_info.payload_len =
  621. ppdu_info->ppdu_msdu_info[mpdu_fcs_ok].payload_len;
  622. end:
  623. /* Free the ppdu status buffer queue */
  624. qdf_nbuf_queue_free(&pdev->rx_ppdu_buf_q);
  625. qdf_mem_zero(&ppdu_info->ppdu_msdu_info,
  626. (ppdu_info->com_info.mpdu_cnt_fcs_ok +
  627. ppdu_info->com_info.mpdu_cnt_fcs_err)
  628. * sizeof(struct hal_rx_msdu_payload_info));
  629. return status_nbuf;
  630. }
  631. static inline void
  632. dp_rx_handle_ppdu_status_buf(struct dp_pdev *pdev,
  633. struct hal_rx_ppdu_info *ppdu_info,
  634. qdf_nbuf_t status_nbuf)
  635. {
  636. qdf_nbuf_t dropnbuf;
  637. if (qdf_nbuf_queue_len(&pdev->rx_ppdu_buf_q) >
  638. HAL_RX_MAX_MPDU) {
  639. dropnbuf = qdf_nbuf_queue_remove(&pdev->rx_ppdu_buf_q);
  640. qdf_nbuf_free(dropnbuf);
  641. }
  642. qdf_nbuf_queue_add(&pdev->rx_ppdu_buf_q, status_nbuf);
  643. }
  644. /**
  645. * dp_rx_handle_mcopy_mode() - Allocate and deliver first MSDU payload
  646. * @soc: core txrx main context
  647. * @pdev: pdev strcuture
  648. * @ppdu_info: structure for rx ppdu ring
  649. *
  650. * Return: QDF_STATUS_SUCCESS - If nbuf to be freed by caller
  651. * QDF_STATUS_E_ALREADY - If nbuf not to be freed by caller
  652. */
  653. #ifdef FEATURE_PERPKT_INFO
  654. static inline QDF_STATUS
  655. dp_rx_handle_mcopy_mode(struct dp_soc *soc, struct dp_pdev *pdev,
  656. struct hal_rx_ppdu_info *ppdu_info, qdf_nbuf_t nbuf)
  657. {
  658. uint8_t size = 0;
  659. struct ieee80211_frame *wh;
  660. uint32_t *nbuf_data;
  661. if (!ppdu_info->fcs_ok_msdu_info.first_msdu_payload)
  662. return QDF_STATUS_SUCCESS;
  663. if (pdev->m_copy_id.rx_ppdu_id == ppdu_info->com_info.ppdu_id)
  664. return QDF_STATUS_SUCCESS;
  665. pdev->m_copy_id.rx_ppdu_id = ppdu_info->com_info.ppdu_id;
  666. wh = (struct ieee80211_frame *)
  667. (ppdu_info->fcs_ok_msdu_info.first_msdu_payload + 4);
  668. size = (ppdu_info->fcs_ok_msdu_info.first_msdu_payload -
  669. qdf_nbuf_data(nbuf));
  670. if (qdf_nbuf_pull_head(nbuf, size) == NULL)
  671. return QDF_STATUS_SUCCESS;
  672. if (((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) ==
  673. IEEE80211_FC0_TYPE_MGT) ||
  674. ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) ==
  675. IEEE80211_FC0_TYPE_CTL)) {
  676. return QDF_STATUS_SUCCESS;
  677. }
  678. ppdu_info->fcs_ok_msdu_info.first_msdu_payload = NULL;
  679. nbuf_data = (uint32_t *)qdf_nbuf_data(nbuf);
  680. *nbuf_data = pdev->ppdu_info.com_info.ppdu_id;
  681. /* only retain RX MSDU payload in the skb */
  682. qdf_nbuf_trim_tail(nbuf, qdf_nbuf_len(nbuf) -
  683. ppdu_info->fcs_ok_msdu_info.payload_len);
  684. dp_wdi_event_handler(WDI_EVENT_RX_DATA, soc,
  685. nbuf, HTT_INVALID_PEER, WDI_NO_VAL, pdev->pdev_id);
  686. return QDF_STATUS_E_ALREADY;
  687. }
  688. #else
  689. static inline QDF_STATUS
  690. dp_rx_handle_mcopy_mode(struct dp_soc *soc, struct dp_pdev *pdev,
  691. struct hal_rx_ppdu_info *ppdu_info, qdf_nbuf_t nbuf)
  692. {
  693. return QDF_STATUS_SUCCESS;
  694. }
  695. #endif
  696. #ifdef FEATURE_PERPKT_INFO
  697. static inline void
  698. dp_rx_process_mcopy_mode(struct dp_soc *soc, struct dp_pdev *pdev,
  699. struct hal_rx_ppdu_info *ppdu_info,
  700. uint32_t tlv_status,
  701. qdf_nbuf_t status_nbuf)
  702. {
  703. QDF_STATUS mcopy_status;
  704. if (qdf_unlikely(!ppdu_info->com_info.mpdu_cnt)) {
  705. qdf_nbuf_free(status_nbuf);
  706. return;
  707. }
  708. /* Add buffers to queue until we receive
  709. * HAL_TLV_STATUS_PPDU_DONE
  710. */
  711. dp_rx_handle_ppdu_status_buf(pdev, ppdu_info, status_nbuf);
  712. /* If tlv_status is PPDU_DONE, process rx_ppdu_buf_q
  713. * and devliver fcs_ok msdu buffer
  714. */
  715. if (tlv_status == HAL_TLV_STATUS_PPDU_DONE) {
  716. if (qdf_unlikely(ppdu_info->com_info.mpdu_cnt !=
  717. (ppdu_info->com_info.mpdu_cnt_fcs_ok +
  718. ppdu_info->com_info.mpdu_cnt_fcs_err))) {
  719. qdf_nbuf_queue_free(&pdev->rx_ppdu_buf_q);
  720. return;
  721. }
  722. /* Get rx ppdu status buffer having fcs ok msdu */
  723. status_nbuf = dp_rx_get_fcs_ok_msdu(pdev, ppdu_info);
  724. if (status_nbuf) {
  725. mcopy_status = dp_rx_handle_mcopy_mode(soc, pdev,
  726. ppdu_info,
  727. status_nbuf);
  728. if (mcopy_status == QDF_STATUS_SUCCESS)
  729. qdf_nbuf_free(status_nbuf);
  730. }
  731. }
  732. }
  733. #else
  734. static inline void
  735. dp_rx_process_mcopy_mode(struct dp_soc *soc, struct dp_pdev *pdev,
  736. struct hal_rx_ppdu_info *ppdu_info,
  737. uint32_t tlv_status,
  738. qdf_nbuf_t status_nbuf)
  739. {
  740. }
  741. #endif
  742. /**
  743. * dp_rx_handle_smart_mesh_mode() - Deliver header for smart mesh
  744. * @soc: Datapath SOC handle
  745. * @pdev: Datapath PDEV handle
  746. * @ppdu_info: Structure for rx ppdu info
  747. * @nbuf: Qdf nbuf abstraction for linux skb
  748. *
  749. * Return: 0 on success, 1 on failure
  750. */
  751. static inline int
  752. dp_rx_handle_smart_mesh_mode(struct dp_soc *soc, struct dp_pdev *pdev,
  753. struct hal_rx_ppdu_info *ppdu_info,
  754. qdf_nbuf_t nbuf)
  755. {
  756. uint8_t size = 0;
  757. if (!pdev->monitor_vdev) {
  758. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  759. "[%s]:[%d] Monitor vdev is NULL !!",
  760. __func__, __LINE__);
  761. return 1;
  762. }
  763. if (!ppdu_info->msdu_info.first_msdu_payload) {
  764. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  765. "[%s]:[%d] First msdu payload not present",
  766. __func__, __LINE__);
  767. return 1;
  768. }
  769. /* Adding 4 bytes to get to start of 802.11 frame after phy_ppdu_id */
  770. size = (ppdu_info->msdu_info.first_msdu_payload -
  771. qdf_nbuf_data(nbuf)) + 4;
  772. ppdu_info->msdu_info.first_msdu_payload = NULL;
  773. if (qdf_nbuf_pull_head(nbuf, size) == NULL) {
  774. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  775. "[%s]:[%d] No header present",
  776. __func__, __LINE__);
  777. return 1;
  778. }
  779. /* Only retain RX MSDU payload in the skb */
  780. qdf_nbuf_trim_tail(nbuf, qdf_nbuf_len(nbuf) -
  781. ppdu_info->msdu_info.payload_len);
  782. if (!qdf_nbuf_update_radiotap(&pdev->ppdu_info.rx_status, nbuf,
  783. qdf_nbuf_headroom(nbuf))) {
  784. DP_STATS_INC(pdev, dropped.mon_radiotap_update_err, 1);
  785. return 1;
  786. }
  787. pdev->monitor_vdev->osif_rx_mon(pdev->monitor_vdev->osif_vdev,
  788. nbuf, NULL);
  789. pdev->ppdu_info.rx_status.monitor_direct_used = 0;
  790. return 0;
  791. }
  792. /**
  793. * dp_rx_handle_ppdu_stats() - Allocate and deliver ppdu stats to cdp layer
  794. * @soc: core txrx main context
  795. * @pdev: pdev strcuture
  796. * @ppdu_info: structure for rx ppdu ring
  797. *
  798. * Return: none
  799. */
  800. #ifdef FEATURE_PERPKT_INFO
  801. static inline void
  802. dp_rx_handle_ppdu_stats(struct dp_soc *soc, struct dp_pdev *pdev,
  803. struct hal_rx_ppdu_info *ppdu_info)
  804. {
  805. qdf_nbuf_t ppdu_nbuf;
  806. struct cdp_rx_indication_ppdu *cdp_rx_ppdu;
  807. /*
  808. * Do not allocate if fcs error,
  809. * ast idx invalid / fctl invalid
  810. */
  811. if (ppdu_info->com_info.mpdu_cnt_fcs_ok == 0)
  812. return;
  813. if (ppdu_info->nac_info.fc_valid &&
  814. ppdu_info->nac_info.to_ds_flag &&
  815. ppdu_info->nac_info.mac_addr2_valid) {
  816. struct dp_neighbour_peer *peer = NULL;
  817. uint8_t rssi = ppdu_info->rx_status.rssi_comb;
  818. qdf_spin_lock_bh(&pdev->neighbour_peer_mutex);
  819. if (pdev->neighbour_peers_added) {
  820. TAILQ_FOREACH(peer, &pdev->neighbour_peers_list,
  821. neighbour_peer_list_elem) {
  822. if (!qdf_mem_cmp(&peer->neighbour_peers_macaddr,
  823. &ppdu_info->nac_info.mac_addr2,
  824. QDF_MAC_ADDR_SIZE)) {
  825. peer->rssi = rssi;
  826. break;
  827. }
  828. }
  829. }
  830. qdf_spin_unlock_bh(&pdev->neighbour_peer_mutex);
  831. }
  832. /* need not generate wdi event when mcopy and
  833. * enhanced stats are not enabled
  834. */
  835. if (!pdev->mcopy_mode && !pdev->enhanced_stats_en)
  836. return;
  837. if (!pdev->mcopy_mode) {
  838. if (!ppdu_info->rx_status.frame_control_info_valid)
  839. return;
  840. if (ppdu_info->rx_status.ast_index == HAL_AST_IDX_INVALID)
  841. return;
  842. }
  843. ppdu_nbuf = qdf_nbuf_alloc(soc->osdev,
  844. sizeof(struct cdp_rx_indication_ppdu), 0, 0, FALSE);
  845. if (ppdu_nbuf) {
  846. dp_rx_populate_cdp_indication_ppdu(pdev, ppdu_info, ppdu_nbuf);
  847. qdf_nbuf_put_tail(ppdu_nbuf,
  848. sizeof(struct cdp_rx_indication_ppdu));
  849. cdp_rx_ppdu = (struct cdp_rx_indication_ppdu *)ppdu_nbuf->data;
  850. dp_rx_stats_update(pdev, cdp_rx_ppdu);
  851. if (cdp_rx_ppdu->peer_id != HTT_INVALID_PEER) {
  852. dp_wdi_event_handler(WDI_EVENT_RX_PPDU_DESC,
  853. soc, ppdu_nbuf,
  854. cdp_rx_ppdu->peer_id,
  855. WDI_NO_VAL, pdev->pdev_id);
  856. } else if (pdev->mcopy_mode) {
  857. dp_wdi_event_handler(WDI_EVENT_RX_PPDU_DESC, soc,
  858. ppdu_nbuf, HTT_INVALID_PEER,
  859. WDI_NO_VAL, pdev->pdev_id);
  860. } else {
  861. qdf_nbuf_free(ppdu_nbuf);
  862. }
  863. }
  864. }
  865. #else
  866. static inline void
  867. dp_rx_handle_ppdu_stats(struct dp_soc *soc, struct dp_pdev *pdev,
  868. struct hal_rx_ppdu_info *ppdu_info)
  869. {
  870. }
  871. #endif
  872. /**
  873. * dp_rx_process_peer_based_pktlog() - Process Rx pktlog if peer based
  874. * filtering enabled
  875. * @soc: core txrx main context
  876. * @ppdu_info: Structure for rx ppdu info
  877. * @status_nbuf: Qdf nbuf abstraction for linux skb
  878. * @mac_id: mac_id/pdev_id correspondinggly for MCL and WIN
  879. *
  880. * Return: none
  881. */
  882. static inline void
  883. dp_rx_process_peer_based_pktlog(struct dp_soc *soc,
  884. struct hal_rx_ppdu_info *ppdu_info,
  885. qdf_nbuf_t status_nbuf, uint32_t mac_id)
  886. {
  887. struct dp_peer *peer;
  888. struct dp_ast_entry *ast_entry;
  889. uint32_t ast_index;
  890. ast_index = ppdu_info->rx_status.ast_index;
  891. if (ast_index < wlan_cfg_get_max_ast_idx(soc->wlan_cfg_ctx)) {
  892. ast_entry = soc->ast_table[ast_index];
  893. if (ast_entry) {
  894. peer = ast_entry->peer;
  895. if (peer && (peer->peer_ids[0] != HTT_INVALID_PEER)) {
  896. if (peer->peer_based_pktlog_filter) {
  897. dp_wdi_event_handler(
  898. WDI_EVENT_RX_DESC, soc,
  899. status_nbuf,
  900. peer->peer_ids[0],
  901. WDI_NO_VAL, mac_id);
  902. }
  903. }
  904. }
  905. }
  906. }
  907. #if defined(HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_M)
  908. static inline void
  909. dp_rx_ul_ofdma_ru_size_to_width(
  910. uint32_t ru_size,
  911. uint32_t *ru_width)
  912. {
  913. uint32_t width;
  914. width = 0;
  915. switch (ru_size) {
  916. case HTT_UL_OFDMA_V0_RU_SIZE_RU_26:
  917. width = 1;
  918. break;
  919. case HTT_UL_OFDMA_V0_RU_SIZE_RU_52:
  920. width = 2;
  921. break;
  922. case HTT_UL_OFDMA_V0_RU_SIZE_RU_106:
  923. width = 4;
  924. break;
  925. case HTT_UL_OFDMA_V0_RU_SIZE_RU_242:
  926. width = 9;
  927. break;
  928. case HTT_UL_OFDMA_V0_RU_SIZE_RU_484:
  929. width = 18;
  930. break;
  931. case HTT_UL_OFDMA_V0_RU_SIZE_RU_996:
  932. width = 37;
  933. break;
  934. case HTT_UL_OFDMA_V0_RU_SIZE_RU_996x2:
  935. width = 74;
  936. break;
  937. default:
  938. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  939. "RU size to width convert err");
  940. break;
  941. }
  942. *ru_width = width;
  943. }
  944. static inline void
  945. dp_rx_mon_handle_mu_ul_info(struct hal_rx_ppdu_info *ppdu_info)
  946. {
  947. struct mon_rx_user_status *mon_rx_user_status;
  948. uint32_t num_users;
  949. uint32_t i;
  950. uint32_t mu_ul_user_v0_word0;
  951. uint32_t mu_ul_user_v0_word1;
  952. uint32_t ru_width;
  953. uint32_t ru_size;
  954. if (!(ppdu_info->rx_status.reception_type == HAL_RX_TYPE_MU_OFDMA ||
  955. ppdu_info->rx_status.reception_type == HAL_RX_TYPE_MU_MIMO))
  956. return;
  957. num_users = ppdu_info->com_info.num_users;
  958. if (num_users > HAL_MAX_UL_MU_USERS)
  959. num_users = HAL_MAX_UL_MU_USERS;
  960. for (i = 0; i < num_users; i++) {
  961. mon_rx_user_status = &ppdu_info->rx_user_status[i];
  962. mu_ul_user_v0_word0 =
  963. mon_rx_user_status->mu_ul_user_v0_word0;
  964. mu_ul_user_v0_word1 =
  965. mon_rx_user_status->mu_ul_user_v0_word1;
  966. if (HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_GET(
  967. mu_ul_user_v0_word0) &&
  968. !HTT_UL_OFDMA_USER_INFO_V0_W0_VER_GET(
  969. mu_ul_user_v0_word0)) {
  970. mon_rx_user_status->mcs =
  971. HTT_UL_OFDMA_USER_INFO_V0_W1_MCS_GET(
  972. mu_ul_user_v0_word1);
  973. mon_rx_user_status->nss =
  974. HTT_UL_OFDMA_USER_INFO_V0_W1_NSS_GET(
  975. mu_ul_user_v0_word1) + 1;
  976. mon_rx_user_status->mu_ul_info_valid = 1;
  977. mon_rx_user_status->ofdma_ru_start_index =
  978. HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START_GET(
  979. mu_ul_user_v0_word1);
  980. ru_size =
  981. HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE_GET(
  982. mu_ul_user_v0_word1);
  983. dp_rx_ul_ofdma_ru_size_to_width(ru_size, &ru_width);
  984. mon_rx_user_status->ofdma_ru_width = ru_width;
  985. mon_rx_user_status->ofdma_ru_size = ru_size;
  986. }
  987. }
  988. }
  989. #else
  990. static inline void
  991. dp_rx_mon_handle_mu_ul_info(struct hal_rx_ppdu_info *ppdu_info)
  992. {
  993. }
  994. #endif
  995. /**
  996. * dp_rx_mon_status_process_tlv() - Process status TLV in status
  997. * buffer on Rx status Queue posted by status SRNG processing.
  998. * @soc: core txrx main context
  999. * @mac_id: mac_id which is one of 3 mac_ids _ring
  1000. *
  1001. * Return: none
  1002. */
  1003. static inline void
  1004. dp_rx_mon_status_process_tlv(struct dp_soc *soc, uint32_t mac_id,
  1005. uint32_t quota)
  1006. {
  1007. struct dp_pdev *pdev = dp_get_pdev_for_mac_id(soc, mac_id);
  1008. struct hal_rx_ppdu_info *ppdu_info;
  1009. qdf_nbuf_t status_nbuf;
  1010. uint8_t *rx_tlv;
  1011. uint8_t *rx_tlv_start;
  1012. uint32_t tlv_status = HAL_TLV_STATUS_BUF_DONE;
  1013. QDF_STATUS enh_log_status = QDF_STATUS_SUCCESS;
  1014. struct cdp_pdev_mon_stats *rx_mon_stats;
  1015. int smart_mesh_status;
  1016. enum WDI_EVENT pktlog_mode = WDI_NO_VAL;
  1017. bool nbuf_used;
  1018. uint32_t rx_enh_capture_mode;
  1019. ppdu_info = &pdev->ppdu_info;
  1020. rx_mon_stats = &pdev->rx_mon_stats;
  1021. if (pdev->mon_ppdu_status != DP_PPDU_STATUS_START)
  1022. return;
  1023. rx_enh_capture_mode = pdev->rx_enh_capture_mode;
  1024. while (!qdf_nbuf_is_queue_empty(&pdev->rx_status_q)) {
  1025. status_nbuf = qdf_nbuf_queue_remove(&pdev->rx_status_q);
  1026. rx_tlv = qdf_nbuf_data(status_nbuf);
  1027. rx_tlv_start = rx_tlv;
  1028. nbuf_used = false;
  1029. if ((pdev->monitor_vdev) || (pdev->enhanced_stats_en) ||
  1030. pdev->mcopy_mode ||
  1031. (rx_enh_capture_mode != CDP_RX_ENH_CAPTURE_DISABLED)) {
  1032. do {
  1033. tlv_status = hal_rx_status_get_tlv_info(rx_tlv,
  1034. ppdu_info, pdev->soc->hal_soc,
  1035. status_nbuf);
  1036. dp_rx_mon_update_dbg_ppdu_stats(ppdu_info,
  1037. rx_mon_stats);
  1038. dp_rx_mon_enh_capture_process(pdev, tlv_status,
  1039. status_nbuf, ppdu_info,
  1040. &nbuf_used);
  1041. rx_tlv = hal_rx_status_get_next_tlv(rx_tlv);
  1042. if ((rx_tlv - rx_tlv_start) >= RX_BUFFER_SIZE)
  1043. break;
  1044. } while ((tlv_status == HAL_TLV_STATUS_PPDU_NOT_DONE) ||
  1045. (tlv_status == HAL_TLV_STATUS_HEADER) ||
  1046. (tlv_status == HAL_TLV_STATUS_MPDU_END) ||
  1047. (tlv_status == HAL_TLV_STATUS_MSDU_END));
  1048. }
  1049. if (pdev->dp_peer_based_pktlog) {
  1050. dp_rx_process_peer_based_pktlog(soc, ppdu_info,
  1051. status_nbuf, mac_id);
  1052. } else {
  1053. if (pdev->rx_pktlog_mode == DP_RX_PKTLOG_FULL)
  1054. pktlog_mode = WDI_EVENT_RX_DESC;
  1055. else if (pdev->rx_pktlog_mode == DP_RX_PKTLOG_LITE)
  1056. pktlog_mode = WDI_EVENT_LITE_RX;
  1057. if (pktlog_mode != WDI_NO_VAL)
  1058. dp_wdi_event_handler(pktlog_mode, soc,
  1059. status_nbuf,
  1060. HTT_INVALID_PEER,
  1061. WDI_NO_VAL, mac_id);
  1062. }
  1063. /* smart monitor vap and m_copy cannot co-exist */
  1064. if (ppdu_info->rx_status.monitor_direct_used && pdev->neighbour_peers_added
  1065. && pdev->monitor_vdev) {
  1066. smart_mesh_status = dp_rx_handle_smart_mesh_mode(soc,
  1067. pdev, ppdu_info, status_nbuf);
  1068. if (smart_mesh_status)
  1069. qdf_nbuf_free(status_nbuf);
  1070. } else if (qdf_unlikely(pdev->mcopy_mode)) {
  1071. dp_rx_process_mcopy_mode(soc, pdev,
  1072. ppdu_info, tlv_status,
  1073. status_nbuf);
  1074. } else if (rx_enh_capture_mode != CDP_RX_ENH_CAPTURE_DISABLED) {
  1075. if (!nbuf_used)
  1076. qdf_nbuf_free(status_nbuf);
  1077. if (tlv_status == HAL_TLV_STATUS_PPDU_DONE)
  1078. enh_log_status =
  1079. dp_rx_handle_enh_capture(soc,
  1080. pdev, ppdu_info);
  1081. } else {
  1082. qdf_nbuf_free(status_nbuf);
  1083. }
  1084. if (tlv_status == HAL_TLV_STATUS_PPDU_NON_STD_DONE) {
  1085. dp_rx_mon_deliver_non_std(soc, mac_id);
  1086. } else if (tlv_status == HAL_TLV_STATUS_PPDU_DONE) {
  1087. rx_mon_stats->status_ppdu_done++;
  1088. dp_rx_mon_handle_mu_ul_info(ppdu_info);
  1089. if (pdev->tx_capture_enabled
  1090. != CDP_TX_ENH_CAPTURE_DISABLED)
  1091. dp_send_ack_frame_to_stack(soc, pdev,
  1092. ppdu_info);
  1093. if (pdev->enhanced_stats_en ||
  1094. pdev->mcopy_mode || pdev->neighbour_peers_added)
  1095. dp_rx_handle_ppdu_stats(soc, pdev, ppdu_info);
  1096. pdev->mon_ppdu_status = DP_PPDU_STATUS_DONE;
  1097. dp_rx_mon_dest_process(soc, mac_id, quota);
  1098. pdev->mon_ppdu_status = DP_PPDU_STATUS_START;
  1099. }
  1100. }
  1101. return;
  1102. }
  1103. /*
  1104. * dp_rx_mon_status_srng_process() - Process monitor status ring
  1105. * post the status ring buffer to Rx status Queue for later
  1106. * processing when status ring is filled with status TLV.
  1107. * Allocate a new buffer to status ring if the filled buffer
  1108. * is posted.
  1109. *
  1110. * @soc: core txrx main context
  1111. * @mac_id: mac_id which is one of 3 mac_ids
  1112. * @quota: No. of ring entry that can be serviced in one shot.
  1113. * Return: uint32_t: No. of ring entry that is processed.
  1114. */
  1115. static inline uint32_t
  1116. dp_rx_mon_status_srng_process(struct dp_soc *soc, uint32_t mac_id,
  1117. uint32_t quota)
  1118. {
  1119. struct dp_pdev *pdev = dp_get_pdev_for_mac_id(soc, mac_id);
  1120. hal_soc_handle_t hal_soc;
  1121. void *mon_status_srng;
  1122. void *rxdma_mon_status_ring_entry;
  1123. QDF_STATUS status;
  1124. uint32_t work_done = 0;
  1125. int mac_for_pdev = dp_get_mac_id_for_mac(soc, mac_id);
  1126. mon_status_srng = pdev->rxdma_mon_status_ring[mac_for_pdev].hal_srng;
  1127. qdf_assert(mon_status_srng);
  1128. if (!mon_status_srng || !hal_srng_initialized(mon_status_srng)) {
  1129. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1130. "%s %d : HAL Monitor Status Ring Init Failed -- %pK",
  1131. __func__, __LINE__, mon_status_srng);
  1132. return work_done;
  1133. }
  1134. hal_soc = soc->hal_soc;
  1135. qdf_assert(hal_soc);
  1136. if (qdf_unlikely(hal_srng_access_start(hal_soc, mon_status_srng)))
  1137. goto done;
  1138. /* mon_status_ring_desc => WBM_BUFFER_RING STRUCT =>
  1139. * BUFFER_ADDR_INFO STRUCT
  1140. */
  1141. while (qdf_likely((rxdma_mon_status_ring_entry =
  1142. hal_srng_src_peek(hal_soc, mon_status_srng))
  1143. && quota--)) {
  1144. uint32_t rx_buf_cookie;
  1145. qdf_nbuf_t status_nbuf;
  1146. struct dp_rx_desc *rx_desc;
  1147. uint8_t *status_buf;
  1148. qdf_dma_addr_t paddr;
  1149. uint64_t buf_addr;
  1150. buf_addr =
  1151. (HAL_RX_BUFFER_ADDR_31_0_GET(
  1152. rxdma_mon_status_ring_entry) |
  1153. ((uint64_t)(HAL_RX_BUFFER_ADDR_39_32_GET(
  1154. rxdma_mon_status_ring_entry)) << 32));
  1155. if (qdf_likely(buf_addr)) {
  1156. rx_buf_cookie =
  1157. HAL_RX_BUF_COOKIE_GET(
  1158. rxdma_mon_status_ring_entry);
  1159. rx_desc = dp_rx_cookie_2_va_mon_status(soc,
  1160. rx_buf_cookie);
  1161. qdf_assert(rx_desc);
  1162. status_nbuf = rx_desc->nbuf;
  1163. qdf_nbuf_sync_for_cpu(soc->osdev, status_nbuf,
  1164. QDF_DMA_FROM_DEVICE);
  1165. status_buf = qdf_nbuf_data(status_nbuf);
  1166. status = hal_get_rx_status_done(status_buf);
  1167. if (status != QDF_STATUS_SUCCESS) {
  1168. uint32_t hp, tp;
  1169. hal_get_sw_hptp(hal_soc, mon_status_srng,
  1170. &tp, &hp);
  1171. dp_info_rl("tlv tag status error hp:%u, tp:%u",
  1172. hp, tp);
  1173. pdev->rx_mon_stats.tlv_tag_status_err++;
  1174. /* WAR for missing status: Skip status entry */
  1175. hal_srng_src_get_next(hal_soc, mon_status_srng);
  1176. continue;
  1177. }
  1178. qdf_nbuf_set_pktlen(status_nbuf, RX_BUFFER_SIZE);
  1179. qdf_nbuf_unmap_single(soc->osdev, status_nbuf,
  1180. QDF_DMA_FROM_DEVICE);
  1181. /* Put the status_nbuf to queue */
  1182. qdf_nbuf_queue_add(&pdev->rx_status_q, status_nbuf);
  1183. } else {
  1184. union dp_rx_desc_list_elem_t *desc_list = NULL;
  1185. union dp_rx_desc_list_elem_t *tail = NULL;
  1186. struct rx_desc_pool *rx_desc_pool;
  1187. uint32_t num_alloc_desc;
  1188. rx_desc_pool = &soc->rx_desc_status[mac_id];
  1189. num_alloc_desc = dp_rx_get_free_desc_list(soc, mac_id,
  1190. rx_desc_pool,
  1191. 1,
  1192. &desc_list,
  1193. &tail);
  1194. /*
  1195. * No free descriptors available
  1196. */
  1197. if (qdf_unlikely(num_alloc_desc == 0)) {
  1198. work_done++;
  1199. break;
  1200. }
  1201. rx_desc = &desc_list->rx_desc;
  1202. }
  1203. status_nbuf = dp_rx_nbuf_prepare(soc, pdev);
  1204. /*
  1205. * qdf_nbuf alloc or map failed,
  1206. * free the dp rx desc to free list,
  1207. * fill in NULL dma address at current HP entry,
  1208. * keep HP in mon_status_ring unchanged,
  1209. * wait next time dp_rx_mon_status_srng_process
  1210. * to fill in buffer at current HP.
  1211. */
  1212. if (qdf_unlikely(!status_nbuf)) {
  1213. union dp_rx_desc_list_elem_t *desc_list = NULL;
  1214. union dp_rx_desc_list_elem_t *tail = NULL;
  1215. struct rx_desc_pool *rx_desc_pool;
  1216. rx_desc_pool = &soc->rx_desc_status[mac_id];
  1217. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1218. "%s: fail to allocate or map qdf_nbuf",
  1219. __func__);
  1220. dp_rx_add_to_free_desc_list(&desc_list,
  1221. &tail, rx_desc);
  1222. dp_rx_add_desc_list_to_free_list(soc, &desc_list,
  1223. &tail, mac_id, rx_desc_pool);
  1224. hal_rxdma_buff_addr_info_set(
  1225. rxdma_mon_status_ring_entry,
  1226. 0, 0, HAL_RX_BUF_RBM_SW3_BM);
  1227. work_done++;
  1228. break;
  1229. }
  1230. paddr = qdf_nbuf_get_frag_paddr(status_nbuf, 0);
  1231. rx_desc->nbuf = status_nbuf;
  1232. rx_desc->in_use = 1;
  1233. hal_rxdma_buff_addr_info_set(rxdma_mon_status_ring_entry,
  1234. paddr, rx_desc->cookie, HAL_RX_BUF_RBM_SW3_BM);
  1235. hal_srng_src_get_next(hal_soc, mon_status_srng);
  1236. work_done++;
  1237. }
  1238. done:
  1239. hal_srng_access_end(hal_soc, mon_status_srng);
  1240. return work_done;
  1241. }
  1242. /*
  1243. * dp_rx_mon_status_process() - Process monitor status ring and
  1244. * TLV in status ring.
  1245. *
  1246. * @soc: core txrx main context
  1247. * @mac_id: mac_id which is one of 3 mac_ids
  1248. * @quota: No. of ring entry that can be serviced in one shot.
  1249. * Return: uint32_t: No. of ring entry that is processed.
  1250. */
  1251. static inline uint32_t
  1252. dp_rx_mon_status_process(struct dp_soc *soc, uint32_t mac_id, uint32_t quota) {
  1253. uint32_t work_done;
  1254. work_done = dp_rx_mon_status_srng_process(soc, mac_id, quota);
  1255. quota -= work_done;
  1256. dp_rx_mon_status_process_tlv(soc, mac_id, quota);
  1257. return work_done;
  1258. }
  1259. /**
  1260. * dp_mon_process() - Main monitor mode processing roution.
  1261. * This call monitor status ring process then monitor
  1262. * destination ring process.
  1263. * Called from the bottom half (tasklet/NET_RX_SOFTIRQ)
  1264. * @soc: core txrx main context
  1265. * @mac_id: mac_id which is one of 3 mac_ids
  1266. * @quota: No. of status ring entry that can be serviced in one shot.
  1267. * Return: uint32_t: No. of ring entry that is processed.
  1268. */
  1269. uint32_t
  1270. dp_mon_process(struct dp_soc *soc, uint32_t mac_id, uint32_t quota) {
  1271. return dp_rx_mon_status_process(soc, mac_id, quota);
  1272. }
  1273. /**
  1274. * dp_rx_pdev_mon_status_detach() - detach dp rx for status ring
  1275. * @pdev: core txrx pdev context
  1276. * @mac_id: mac_id/pdev_id correspondinggly for MCL and WIN
  1277. *
  1278. * This function will detach DP RX status ring from
  1279. * main device context. will free DP Rx resources for
  1280. * status ring
  1281. *
  1282. * Return: QDF_STATUS_SUCCESS: success
  1283. * QDF_STATUS_E_RESOURCES: Error return
  1284. */
  1285. QDF_STATUS
  1286. dp_rx_pdev_mon_status_detach(struct dp_pdev *pdev, int mac_id)
  1287. {
  1288. struct dp_soc *soc = pdev->soc;
  1289. struct rx_desc_pool *rx_desc_pool;
  1290. rx_desc_pool = &soc->rx_desc_status[mac_id];
  1291. if (rx_desc_pool->pool_size != 0) {
  1292. if (!dp_is_soc_reinit(soc))
  1293. dp_rx_desc_nbuf_and_pool_free(soc, mac_id,
  1294. rx_desc_pool);
  1295. else
  1296. dp_rx_desc_nbuf_free(soc, rx_desc_pool);
  1297. }
  1298. return QDF_STATUS_SUCCESS;
  1299. }
  1300. /*
  1301. * dp_rx_buffers_replenish() - replenish monitor status ring with
  1302. * rx nbufs called during dp rx
  1303. * monitor status ring initialization
  1304. *
  1305. * @soc: core txrx main context
  1306. * @mac_id: mac_id which is one of 3 mac_ids
  1307. * @dp_rxdma_srng: dp monitor status circular ring
  1308. * @rx_desc_pool; Pointer to Rx descriptor pool
  1309. * @num_req_buffers: number of buffer to be replenished
  1310. * @desc_list: list of descs if called from dp rx monitor status
  1311. * process or NULL during dp rx initialization or
  1312. * out of buffer interrupt
  1313. * @tail: tail of descs list
  1314. * @owner: who owns the nbuf (host, NSS etc...)
  1315. * Return: return success or failure
  1316. */
  1317. static inline
  1318. QDF_STATUS dp_rx_mon_status_buffers_replenish(struct dp_soc *dp_soc,
  1319. uint32_t mac_id,
  1320. struct dp_srng *dp_rxdma_srng,
  1321. struct rx_desc_pool *rx_desc_pool,
  1322. uint32_t num_req_buffers,
  1323. union dp_rx_desc_list_elem_t **desc_list,
  1324. union dp_rx_desc_list_elem_t **tail,
  1325. uint8_t owner)
  1326. {
  1327. uint32_t num_alloc_desc;
  1328. uint16_t num_desc_to_free = 0;
  1329. uint32_t num_entries_avail;
  1330. uint32_t count = 0;
  1331. int sync_hw_ptr = 1;
  1332. qdf_dma_addr_t paddr;
  1333. qdf_nbuf_t rx_netbuf;
  1334. void *rxdma_ring_entry;
  1335. union dp_rx_desc_list_elem_t *next;
  1336. void *rxdma_srng;
  1337. struct dp_pdev *dp_pdev = dp_get_pdev_for_mac_id(dp_soc, mac_id);
  1338. rxdma_srng = dp_rxdma_srng->hal_srng;
  1339. qdf_assert(rxdma_srng);
  1340. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1341. "[%s][%d] requested %d buffers for replenish",
  1342. __func__, __LINE__, num_req_buffers);
  1343. /*
  1344. * if desc_list is NULL, allocate the descs from freelist
  1345. */
  1346. if (!(*desc_list)) {
  1347. num_alloc_desc = dp_rx_get_free_desc_list(dp_soc, mac_id,
  1348. rx_desc_pool,
  1349. num_req_buffers,
  1350. desc_list,
  1351. tail);
  1352. if (!num_alloc_desc) {
  1353. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1354. "[%s][%d] no free rx_descs in freelist",
  1355. __func__, __LINE__);
  1356. return QDF_STATUS_E_NOMEM;
  1357. }
  1358. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1359. "[%s][%d] %d rx desc allocated", __func__, __LINE__,
  1360. num_alloc_desc);
  1361. num_req_buffers = num_alloc_desc;
  1362. }
  1363. hal_srng_access_start(dp_soc->hal_soc, rxdma_srng);
  1364. num_entries_avail = hal_srng_src_num_avail(dp_soc->hal_soc,
  1365. rxdma_srng, sync_hw_ptr);
  1366. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1367. "[%s][%d] no of available entries in rxdma ring: %d",
  1368. __func__, __LINE__, num_entries_avail);
  1369. if (num_entries_avail < num_req_buffers) {
  1370. num_desc_to_free = num_req_buffers - num_entries_avail;
  1371. num_req_buffers = num_entries_avail;
  1372. }
  1373. while (count < num_req_buffers) {
  1374. rx_netbuf = dp_rx_nbuf_prepare(dp_soc, dp_pdev);
  1375. /*
  1376. * qdf_nbuf alloc or map failed,
  1377. * keep HP in mon_status_ring unchanged,
  1378. * wait dp_rx_mon_status_srng_process
  1379. * to fill in buffer at current HP.
  1380. */
  1381. if (qdf_unlikely(!rx_netbuf)) {
  1382. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1383. "%s: qdf_nbuf allocate or map fail, count %d",
  1384. __func__, count);
  1385. break;
  1386. }
  1387. paddr = qdf_nbuf_get_frag_paddr(rx_netbuf, 0);
  1388. next = (*desc_list)->next;
  1389. rxdma_ring_entry = hal_srng_src_get_next(dp_soc->hal_soc,
  1390. rxdma_srng);
  1391. if (qdf_unlikely(!rxdma_ring_entry)) {
  1392. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1393. "[%s][%d] rxdma_ring_entry is NULL, count - %d",
  1394. __func__, __LINE__, count);
  1395. qdf_nbuf_unmap_single(dp_soc->osdev, rx_netbuf,
  1396. QDF_DMA_FROM_DEVICE);
  1397. qdf_nbuf_free(rx_netbuf);
  1398. break;
  1399. }
  1400. (*desc_list)->rx_desc.nbuf = rx_netbuf;
  1401. (*desc_list)->rx_desc.in_use = 1;
  1402. count++;
  1403. hal_rxdma_buff_addr_info_set(rxdma_ring_entry, paddr,
  1404. (*desc_list)->rx_desc.cookie, owner);
  1405. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1406. "[%s][%d] rx_desc=%pK, cookie=%d, nbuf=%pK, \
  1407. paddr=%pK",
  1408. __func__, __LINE__, &(*desc_list)->rx_desc,
  1409. (*desc_list)->rx_desc.cookie, rx_netbuf,
  1410. (void *)paddr);
  1411. *desc_list = next;
  1412. }
  1413. hal_srng_access_end(dp_soc->hal_soc, rxdma_srng);
  1414. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1415. "successfully replenished %d buffers", num_req_buffers);
  1416. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1417. "%d rx desc added back to free list", num_desc_to_free);
  1418. /*
  1419. * add any available free desc back to the free list
  1420. */
  1421. if (*desc_list) {
  1422. dp_rx_add_desc_list_to_free_list(dp_soc, desc_list, tail,
  1423. mac_id, rx_desc_pool);
  1424. }
  1425. return QDF_STATUS_SUCCESS;
  1426. }
  1427. /**
  1428. * dp_rx_pdev_mon_status_attach() - attach DP RX monitor status ring
  1429. * @pdev: core txrx pdev context
  1430. * @ring_id: ring number
  1431. * This function will attach a DP RX monitor status ring into pDEV
  1432. * and replenish monitor status ring with buffer.
  1433. *
  1434. * Return: QDF_STATUS_SUCCESS: success
  1435. * QDF_STATUS_E_RESOURCES: Error return
  1436. */
  1437. QDF_STATUS
  1438. dp_rx_pdev_mon_status_attach(struct dp_pdev *pdev, int ring_id) {
  1439. struct dp_soc *soc = pdev->soc;
  1440. union dp_rx_desc_list_elem_t *desc_list = NULL;
  1441. union dp_rx_desc_list_elem_t *tail = NULL;
  1442. struct dp_srng *mon_status_ring;
  1443. uint32_t num_entries;
  1444. uint32_t i;
  1445. struct rx_desc_pool *rx_desc_pool;
  1446. QDF_STATUS status;
  1447. int mac_for_pdev = dp_get_mac_id_for_mac(soc, ring_id);
  1448. mon_status_ring = &pdev->rxdma_mon_status_ring[mac_for_pdev];
  1449. num_entries = mon_status_ring->num_entries;
  1450. rx_desc_pool = &soc->rx_desc_status[ring_id];
  1451. dp_info("Mon RX Status Pool[%d] entries=%d",
  1452. ring_id, num_entries);
  1453. status = dp_rx_desc_pool_alloc(soc, ring_id, num_entries + 1,
  1454. rx_desc_pool);
  1455. if (!QDF_IS_STATUS_SUCCESS(status))
  1456. return status;
  1457. dp_debug("Mon RX Status Buffers Replenish ring_id=%d", ring_id);
  1458. status = dp_rx_mon_status_buffers_replenish(soc, ring_id,
  1459. mon_status_ring,
  1460. rx_desc_pool,
  1461. num_entries,
  1462. &desc_list, &tail,
  1463. HAL_RX_BUF_RBM_SW3_BM);
  1464. if (!QDF_IS_STATUS_SUCCESS(status))
  1465. return status;
  1466. qdf_nbuf_queue_init(&pdev->rx_status_q);
  1467. qdf_nbuf_queue_init(&pdev->rx_ppdu_buf_q);
  1468. pdev->mon_ppdu_status = DP_PPDU_STATUS_START;
  1469. qdf_mem_zero(&(pdev->ppdu_info.rx_status),
  1470. sizeof(pdev->ppdu_info.rx_status));
  1471. qdf_mem_zero(&pdev->rx_mon_stats,
  1472. sizeof(pdev->rx_mon_stats));
  1473. dp_rx_mon_init_dbg_ppdu_stats(&pdev->ppdu_info,
  1474. &pdev->rx_mon_stats);
  1475. for (i = 0; i < MAX_MU_USERS; i++) {
  1476. qdf_nbuf_queue_init(&pdev->mpdu_q[i]);
  1477. pdev->is_mpdu_hdr[i] = true;
  1478. }
  1479. qdf_mem_zero(pdev->msdu_list, sizeof(pdev->msdu_list[MAX_MU_USERS]));
  1480. pdev->rx_enh_capture_mode = CDP_RX_ENH_CAPTURE_DISABLED;
  1481. return QDF_STATUS_SUCCESS;
  1482. }