sde_kms.c 113 KB

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  1. /*
  2. * Copyright (c) 2014-2020, The Linux Foundation. All rights reserved.
  3. * Copyright (C) 2013 Red Hat
  4. * Author: Rob Clark <[email protected]>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  19. #include <drm/drm_crtc.h>
  20. #include <drm/drm_fixed.h>
  21. #include <drm/drm_panel.h>
  22. #include <linux/debugfs.h>
  23. #include <linux/of_address.h>
  24. #include <linux/of_irq.h>
  25. #include <linux/dma-buf.h>
  26. #include <linux/memblock.h>
  27. #include <drm/drm_atomic_uapi.h>
  28. #include <drm/drm_probe_helper.h>
  29. #include "msm_drv.h"
  30. #include "msm_mmu.h"
  31. #include "msm_gem.h"
  32. #include "dsi_display.h"
  33. #include "dsi_drm.h"
  34. #include "sde_wb.h"
  35. #include "dp_display.h"
  36. #include "dp_drm.h"
  37. #include "dp_mst_drm.h"
  38. #include "sde_kms.h"
  39. #include "sde_core_irq.h"
  40. #include "sde_formats.h"
  41. #include "sde_hw_vbif.h"
  42. #include "sde_vbif.h"
  43. #include "sde_encoder.h"
  44. #include "sde_plane.h"
  45. #include "sde_crtc.h"
  46. #include "sde_color_processing.h"
  47. #include "sde_reg_dma.h"
  48. #include "sde_connector.h"
  49. #include "sde_vm.h"
  50. #include <linux/qcom_scm.h>
  51. #include "soc/qcom/secure_buffer.h"
  52. #include <linux/qtee_shmbridge.h>
  53. #include <linux/haven/hh_irq_lend.h>
  54. #define CREATE_TRACE_POINTS
  55. #include "sde_trace.h"
  56. /* defines for secure channel call */
  57. #define MEM_PROTECT_SD_CTRL_SWITCH 0x18
  58. #define MDP_DEVICE_ID 0x1A
  59. EXPORT_TRACEPOINT_SYMBOL(tracing_mark_write);
  60. static const char * const iommu_ports[] = {
  61. "mdp_0",
  62. };
  63. /**
  64. * Controls size of event log buffer. Specified as a power of 2.
  65. */
  66. #define SDE_EVTLOG_SIZE 1024
  67. /*
  68. * To enable overall DRM driver logging
  69. * # echo 0x2 > /sys/module/drm/parameters/debug
  70. *
  71. * To enable DRM driver h/w logging
  72. * # echo <mask> > /sys/kernel/debug/dri/0/debug/hw_log_mask
  73. *
  74. * See sde_hw_mdss.h for h/w logging mask definitions (search for SDE_DBG_MASK_)
  75. */
  76. #define SDE_DEBUGFS_DIR "msm_sde"
  77. #define SDE_DEBUGFS_HWMASKNAME "hw_log_mask"
  78. #define SDE_KMS_MODESET_LOCK_TIMEOUT_US 500
  79. #define SDE_KMS_MODESET_LOCK_MAX_TRIALS 20
  80. /**
  81. * sdecustom - enable certain driver customizations for sde clients
  82. * Enabling this modifies the standard DRM behavior slightly and assumes
  83. * that the clients have specific knowledge about the modifications that
  84. * are involved, so don't enable this unless you know what you're doing.
  85. *
  86. * Parts of the driver that are affected by this setting may be located by
  87. * searching for invocations of the 'sde_is_custom_client()' function.
  88. *
  89. * This is disabled by default.
  90. */
  91. static bool sdecustom = true;
  92. module_param(sdecustom, bool, 0400);
  93. MODULE_PARM_DESC(sdecustom, "Enable customizations for sde clients");
  94. static int sde_kms_hw_init(struct msm_kms *kms);
  95. static int _sde_kms_mmu_destroy(struct sde_kms *sde_kms);
  96. static int _sde_kms_mmu_init(struct sde_kms *sde_kms);
  97. static int _sde_kms_register_events(struct msm_kms *kms,
  98. struct drm_mode_object *obj, u32 event, bool en);
  99. bool sde_is_custom_client(void)
  100. {
  101. return sdecustom;
  102. }
  103. #ifdef CONFIG_DEBUG_FS
  104. void *sde_debugfs_get_root(struct sde_kms *sde_kms)
  105. {
  106. struct msm_drm_private *priv;
  107. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private)
  108. return NULL;
  109. priv = sde_kms->dev->dev_private;
  110. return priv->debug_root;
  111. }
  112. static int _sde_debugfs_init(struct sde_kms *sde_kms)
  113. {
  114. void *p;
  115. int rc;
  116. void *debugfs_root;
  117. p = sde_hw_util_get_log_mask_ptr();
  118. if (!sde_kms || !p)
  119. return -EINVAL;
  120. debugfs_root = sde_debugfs_get_root(sde_kms);
  121. if (!debugfs_root)
  122. return -EINVAL;
  123. /* allow debugfs_root to be NULL */
  124. debugfs_create_x32(SDE_DEBUGFS_HWMASKNAME, 0600, debugfs_root, p);
  125. (void) sde_debugfs_vbif_init(sde_kms, debugfs_root);
  126. (void) sde_debugfs_core_irq_init(sde_kms, debugfs_root);
  127. rc = sde_core_perf_debugfs_init(&sde_kms->perf, debugfs_root);
  128. if (rc) {
  129. SDE_ERROR("failed to init perf %d\n", rc);
  130. return rc;
  131. }
  132. if (sde_kms->catalog->qdss_count)
  133. debugfs_create_u32("qdss", 0600, debugfs_root,
  134. (u32 *)&sde_kms->qdss_enabled);
  135. debugfs_create_u32("pm_suspend_clk_dump", 0600, debugfs_root,
  136. (u32 *)&sde_kms->pm_suspend_clk_dump);
  137. return 0;
  138. }
  139. static void sde_kms_debugfs_destroy(struct msm_kms *kms)
  140. {
  141. struct sde_kms *sde_kms = to_sde_kms(kms);
  142. /* don't need to NULL check debugfs_root */
  143. if (sde_kms) {
  144. sde_debugfs_vbif_destroy(sde_kms);
  145. sde_debugfs_core_irq_destroy(sde_kms);
  146. }
  147. }
  148. static int _sde_kms_dump_clks_state(struct sde_kms *sde_kms)
  149. {
  150. int i;
  151. struct device *dev = sde_kms->dev->dev;
  152. SDE_INFO("runtime PM suspended:%d", pm_runtime_suspended(dev));
  153. for (i = 0; i < sde_kms->dsi_display_count; i++)
  154. dsi_display_dump_clks_state(sde_kms->dsi_displays[i]);
  155. return 0;
  156. }
  157. #else
  158. static int _sde_debugfs_init(struct sde_kms *sde_kms)
  159. {
  160. return 0;
  161. }
  162. static void sde_kms_debugfs_destroy(struct msm_kms *kms)
  163. {
  164. }
  165. static int _sde_kms_dump_clks_state(struct sde_kms *sde_kms)
  166. {
  167. return 0;
  168. }
  169. #endif
  170. static bool _sde_kms_skip_vblank_op(struct sde_kms *sde_kms)
  171. {
  172. struct sde_vm_ops *vm_ops = sde_vm_get_ops(sde_kms);
  173. if (vm_ops && vm_ops->vm_owns_hw
  174. && !vm_ops->vm_owns_hw(sde_kms))
  175. return true;
  176. return false;
  177. }
  178. static int sde_kms_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
  179. {
  180. int ret = 0;
  181. struct sde_kms *sde_kms;
  182. if (!kms)
  183. return -EINVAL;
  184. sde_kms = to_sde_kms(kms);
  185. sde_vm_lock(sde_kms);
  186. if (_sde_kms_skip_vblank_op(sde_kms)) {
  187. SDE_DEBUG("skipping vblank enable due to HW unavailablity\n");
  188. goto done;
  189. }
  190. SDE_ATRACE_BEGIN("sde_kms_enable_vblank");
  191. ret = sde_crtc_vblank(crtc, true);
  192. SDE_ATRACE_END("sde_kms_enable_vblank");
  193. done:
  194. sde_vm_unlock(sde_kms);
  195. return ret;
  196. }
  197. static void sde_kms_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
  198. {
  199. struct sde_kms *sde_kms;
  200. if (!kms)
  201. return;
  202. sde_kms = to_sde_kms(kms);
  203. sde_vm_lock(sde_kms);
  204. if (_sde_kms_skip_vblank_op(sde_kms)) {
  205. SDE_DEBUG("skipping vblank disable due to HW unavailablity\n");
  206. goto done;
  207. }
  208. SDE_ATRACE_BEGIN("sde_kms_disable_vblank");
  209. sde_crtc_vblank(crtc, false);
  210. SDE_ATRACE_END("sde_kms_disable_vblank");
  211. done:
  212. sde_vm_unlock(sde_kms);
  213. }
  214. static void sde_kms_wait_for_frame_transfer_complete(struct msm_kms *kms,
  215. struct drm_crtc *crtc)
  216. {
  217. struct drm_encoder *encoder;
  218. struct drm_device *dev;
  219. int ret;
  220. if (!kms || !crtc || !crtc->state || !crtc->dev) {
  221. SDE_ERROR("invalid params\n");
  222. return;
  223. }
  224. if (!crtc->state->enable) {
  225. SDE_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
  226. return;
  227. }
  228. if (!crtc->state->active) {
  229. SDE_DEBUG("[crtc:%d] not active\n", crtc->base.id);
  230. return;
  231. }
  232. dev = crtc->dev;
  233. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  234. if (encoder->crtc != crtc)
  235. continue;
  236. /*
  237. * Video Mode - Wait for VSYNC
  238. * Cmd Mode - Wait for PP_DONE. Will be no-op if transfer is
  239. * complete
  240. */
  241. SDE_EVT32_VERBOSE(DRMID(crtc));
  242. ret = sde_encoder_wait_for_event(encoder, MSM_ENC_TX_COMPLETE);
  243. if (ret && ret != -EWOULDBLOCK) {
  244. SDE_ERROR(
  245. "[crtc: %d][enc: %d] wait for commit done returned %d\n",
  246. crtc->base.id, encoder->base.id, ret);
  247. break;
  248. }
  249. }
  250. }
  251. static int _sde_kms_secure_ctrl_xin_clients(struct sde_kms *sde_kms,
  252. struct drm_crtc *crtc, bool enable)
  253. {
  254. struct drm_device *dev;
  255. struct msm_drm_private *priv;
  256. struct sde_mdss_cfg *sde_cfg;
  257. struct drm_plane *plane;
  258. int i, ret;
  259. dev = sde_kms->dev;
  260. priv = dev->dev_private;
  261. sde_cfg = sde_kms->catalog;
  262. ret = sde_vbif_halt_xin_mask(sde_kms,
  263. sde_cfg->sui_block_xin_mask, enable);
  264. if (ret) {
  265. SDE_ERROR("failed to halt some xin-clients, ret:%d\n", ret);
  266. return ret;
  267. }
  268. if (enable) {
  269. for (i = 0; i < priv->num_planes; i++) {
  270. plane = priv->planes[i];
  271. sde_plane_secure_ctrl_xin_client(plane, crtc);
  272. }
  273. }
  274. return 0;
  275. }
  276. /**
  277. * _sde_kms_scm_call - makes secure channel call to switch the VMIDs
  278. * @sde_kms: Pointer to sde_kms struct
  279. * @vimd: switch the stage 2 translation to this VMID
  280. */
  281. static int _sde_kms_scm_call(struct sde_kms *sde_kms, int vmid)
  282. {
  283. struct device dummy = {};
  284. dma_addr_t dma_handle;
  285. uint32_t num_sids;
  286. uint32_t *sec_sid;
  287. struct sde_mdss_cfg *sde_cfg = sde_kms->catalog;
  288. int ret = 0, i;
  289. struct qtee_shm shm;
  290. bool qtee_en = qtee_shmbridge_is_enabled();
  291. phys_addr_t mem_addr;
  292. u64 mem_size;
  293. num_sids = sde_cfg->sec_sid_mask_count;
  294. if (!num_sids) {
  295. SDE_ERROR("secure SID masks not configured, vmid 0x%x\n", vmid);
  296. return -EINVAL;
  297. }
  298. if (qtee_en) {
  299. ret = qtee_shmbridge_allocate_shm(num_sids * sizeof(uint32_t),
  300. &shm);
  301. if (ret)
  302. return -ENOMEM;
  303. sec_sid = (uint32_t *) shm.vaddr;
  304. mem_addr = shm.paddr;
  305. /**
  306. * SMMUSecureModeSwitch requires the size to be number of SID's
  307. * but shm allocates size in pages. Modify the args as per
  308. * client requirement.
  309. */
  310. mem_size = sizeof(uint32_t) * num_sids;
  311. } else {
  312. sec_sid = kcalloc(num_sids, sizeof(uint32_t), GFP_KERNEL);
  313. if (!sec_sid)
  314. return -ENOMEM;
  315. mem_addr = virt_to_phys(sec_sid);
  316. mem_size = sizeof(uint32_t) * num_sids;
  317. }
  318. for (i = 0; i < num_sids; i++) {
  319. sec_sid[i] = sde_cfg->sec_sid_mask[i];
  320. SDE_DEBUG("sid_mask[%d]: %d\n", i, sec_sid[i]);
  321. }
  322. ret = dma_coerce_mask_and_coherent(&dummy, DMA_BIT_MASK(64));
  323. if (ret) {
  324. SDE_ERROR("Failed to set dma mask for dummy dev %d\n", ret);
  325. goto map_error;
  326. }
  327. set_dma_ops(&dummy, NULL);
  328. dma_handle = dma_map_single(&dummy, sec_sid,
  329. num_sids * sizeof(uint32_t), DMA_TO_DEVICE);
  330. if (dma_mapping_error(&dummy, dma_handle)) {
  331. SDE_ERROR("dma_map_single for dummy dev failed vmid 0x%x\n",
  332. vmid);
  333. goto map_error;
  334. }
  335. SDE_DEBUG("calling scm_call for vmid 0x%x, num_sids %d, qtee_en %d",
  336. vmid, num_sids, qtee_en);
  337. ret = qcom_scm_mem_protect_sd_ctrl(MDP_DEVICE_ID, mem_addr,
  338. mem_size, vmid);
  339. if (ret)
  340. SDE_ERROR("Error:scm_call2, vmid %lld, ret%d\n",
  341. vmid, ret);
  342. SDE_EVT32(MEM_PROTECT_SD_CTRL_SWITCH, MDP_DEVICE_ID, mem_size,
  343. vmid, qtee_en, num_sids, ret);
  344. dma_unmap_single(&dummy, dma_handle,
  345. num_sids * sizeof(uint32_t), DMA_TO_DEVICE);
  346. map_error:
  347. if (qtee_en)
  348. qtee_shmbridge_free_shm(&shm);
  349. else
  350. kfree(sec_sid);
  351. return ret;
  352. }
  353. static int _sde_kms_detach_all_cb(struct sde_kms *sde_kms, u32 vmid)
  354. {
  355. u32 ret;
  356. if (atomic_inc_return(&sde_kms->detach_all_cb) > 1)
  357. return 0;
  358. /* detach_all_contexts */
  359. ret = sde_kms_mmu_detach(sde_kms, false);
  360. if (ret) {
  361. SDE_ERROR("failed to detach all cb ret:%d\n", ret);
  362. goto mmu_error;
  363. }
  364. ret = _sde_kms_scm_call(sde_kms, vmid);
  365. if (ret) {
  366. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  367. goto scm_error;
  368. }
  369. return 0;
  370. scm_error:
  371. sde_kms_mmu_attach(sde_kms, false);
  372. mmu_error:
  373. atomic_dec(&sde_kms->detach_all_cb);
  374. return ret;
  375. }
  376. static int _sde_kms_attach_all_cb(struct sde_kms *sde_kms, u32 vmid,
  377. u32 old_vmid)
  378. {
  379. u32 ret;
  380. if (atomic_dec_return(&sde_kms->detach_all_cb) != 0)
  381. return 0;
  382. ret = _sde_kms_scm_call(sde_kms, vmid);
  383. if (ret) {
  384. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  385. goto scm_error;
  386. }
  387. /* attach_all_contexts */
  388. ret = sde_kms_mmu_attach(sde_kms, false);
  389. if (ret) {
  390. SDE_ERROR("failed to attach all cb ret:%d\n", ret);
  391. goto mmu_error;
  392. }
  393. return 0;
  394. mmu_error:
  395. _sde_kms_scm_call(sde_kms, old_vmid);
  396. scm_error:
  397. atomic_inc(&sde_kms->detach_all_cb);
  398. return ret;
  399. }
  400. static int _sde_kms_detach_sec_cb(struct sde_kms *sde_kms, int vmid)
  401. {
  402. u32 ret;
  403. if (atomic_inc_return(&sde_kms->detach_sec_cb) > 1)
  404. return 0;
  405. /* detach secure_context */
  406. ret = sde_kms_mmu_detach(sde_kms, true);
  407. if (ret) {
  408. SDE_ERROR("failed to detach sec cb ret:%d\n", ret);
  409. goto mmu_error;
  410. }
  411. ret = _sde_kms_scm_call(sde_kms, vmid);
  412. if (ret) {
  413. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  414. goto scm_error;
  415. }
  416. return 0;
  417. scm_error:
  418. sde_kms_mmu_attach(sde_kms, true);
  419. mmu_error:
  420. atomic_dec(&sde_kms->detach_sec_cb);
  421. return ret;
  422. }
  423. static int _sde_kms_attach_sec_cb(struct sde_kms *sde_kms, u32 vmid,
  424. u32 old_vmid)
  425. {
  426. u32 ret;
  427. if (atomic_dec_return(&sde_kms->detach_sec_cb) != 0)
  428. return 0;
  429. ret = _sde_kms_scm_call(sde_kms, vmid);
  430. if (ret) {
  431. goto scm_error;
  432. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  433. }
  434. ret = sde_kms_mmu_attach(sde_kms, true);
  435. if (ret) {
  436. SDE_ERROR("failed to attach sec cb ret:%d\n", ret);
  437. goto mmu_error;
  438. }
  439. return 0;
  440. mmu_error:
  441. _sde_kms_scm_call(sde_kms, old_vmid);
  442. scm_error:
  443. atomic_inc(&sde_kms->detach_sec_cb);
  444. return ret;
  445. }
  446. static int _sde_kms_sui_misr_ctrl(struct sde_kms *sde_kms,
  447. struct drm_crtc *crtc, bool enable)
  448. {
  449. int ret;
  450. if (enable) {
  451. ret = pm_runtime_get_sync(sde_kms->dev->dev);
  452. if (ret < 0) {
  453. SDE_ERROR("failed to enable resource, ret:%d\n", ret);
  454. return ret;
  455. }
  456. sde_crtc_misr_setup(crtc, true, 1);
  457. ret = _sde_kms_secure_ctrl_xin_clients(sde_kms, crtc, true);
  458. if (ret) {
  459. sde_crtc_misr_setup(crtc, false, 0);
  460. pm_runtime_put_sync(sde_kms->dev->dev);
  461. return ret;
  462. }
  463. } else {
  464. _sde_kms_secure_ctrl_xin_clients(sde_kms, crtc, false);
  465. sde_crtc_misr_setup(crtc, false, 0);
  466. pm_runtime_put_sync(sde_kms->dev->dev);
  467. }
  468. return 0;
  469. }
  470. static int _sde_kms_secure_ctrl(struct sde_kms *sde_kms, struct drm_crtc *crtc,
  471. bool post_commit)
  472. {
  473. struct sde_kms_smmu_state_data *smmu_state = &sde_kms->smmu_state;
  474. int old_smmu_state = smmu_state->state;
  475. int ret = 0;
  476. u32 vmid;
  477. if (!sde_kms || !crtc) {
  478. SDE_ERROR("invalid argument(s)\n");
  479. return -EINVAL;
  480. }
  481. SDE_EVT32(DRMID(crtc), smmu_state->state, smmu_state->transition_type,
  482. post_commit, smmu_state->sui_misr_state,
  483. smmu_state->secure_level, SDE_EVTLOG_FUNC_ENTRY);
  484. if ((!smmu_state->transition_type) ||
  485. ((smmu_state->transition_type == POST_COMMIT) && !post_commit))
  486. /* Bail out */
  487. return 0;
  488. /* enable sui misr if requested, before the transition */
  489. if (smmu_state->sui_misr_state == SUI_MISR_ENABLE_REQ) {
  490. ret = _sde_kms_sui_misr_ctrl(sde_kms, crtc, true);
  491. if (ret) {
  492. smmu_state->sui_misr_state = NONE;
  493. goto end;
  494. }
  495. }
  496. mutex_lock(&sde_kms->secure_transition_lock);
  497. switch (smmu_state->state) {
  498. case DETACH_ALL_REQ:
  499. ret = _sde_kms_detach_all_cb(sde_kms, VMID_CP_SEC_DISPLAY);
  500. if (!ret)
  501. smmu_state->state = DETACHED;
  502. break;
  503. case ATTACH_ALL_REQ:
  504. ret = _sde_kms_attach_all_cb(sde_kms, VMID_CP_PIXEL,
  505. VMID_CP_SEC_DISPLAY);
  506. if (!ret) {
  507. smmu_state->state = ATTACHED;
  508. smmu_state->secure_level = SDE_DRM_SEC_NON_SEC;
  509. }
  510. break;
  511. case DETACH_SEC_REQ:
  512. vmid = (smmu_state->secure_level == SDE_DRM_SEC_ONLY) ?
  513. VMID_CP_SEC_DISPLAY : VMID_CP_CAMERA_PREVIEW;
  514. ret = _sde_kms_detach_sec_cb(sde_kms, vmid);
  515. if (!ret)
  516. smmu_state->state = DETACHED_SEC;
  517. break;
  518. case ATTACH_SEC_REQ:
  519. vmid = (smmu_state->secure_level == SDE_DRM_SEC_ONLY) ?
  520. VMID_CP_SEC_DISPLAY : VMID_CP_CAMERA_PREVIEW;
  521. ret = _sde_kms_attach_sec_cb(sde_kms, VMID_CP_PIXEL, vmid);
  522. if (!ret) {
  523. smmu_state->state = ATTACHED;
  524. smmu_state->secure_level = SDE_DRM_SEC_NON_SEC;
  525. }
  526. break;
  527. default:
  528. SDE_ERROR("crtc%d: invalid smmu state %d transition type %d\n",
  529. DRMID(crtc), smmu_state->state,
  530. smmu_state->transition_type);
  531. ret = -EINVAL;
  532. break;
  533. }
  534. mutex_unlock(&sde_kms->secure_transition_lock);
  535. /* disable sui misr if requested, after the transition */
  536. if (!ret && (smmu_state->sui_misr_state == SUI_MISR_DISABLE_REQ)) {
  537. ret = _sde_kms_sui_misr_ctrl(sde_kms, crtc, false);
  538. if (ret)
  539. goto end;
  540. }
  541. end:
  542. smmu_state->transition_error = false;
  543. if (ret) {
  544. smmu_state->transition_error = true;
  545. SDE_ERROR(
  546. "crtc%d: req_state %d, new_state %d, sec_lvl %d, ret %d\n",
  547. DRMID(crtc), old_smmu_state, smmu_state->state,
  548. smmu_state->secure_level, ret);
  549. smmu_state->state = smmu_state->prev_state;
  550. smmu_state->secure_level = smmu_state->prev_secure_level;
  551. if (smmu_state->sui_misr_state == SUI_MISR_ENABLE_REQ)
  552. _sde_kms_sui_misr_ctrl(sde_kms, crtc, false);
  553. }
  554. SDE_DEBUG("crtc %d: req_state %d, new_state %d, sec_lvl %d, ret %d\n",
  555. DRMID(crtc), old_smmu_state, smmu_state->state,
  556. smmu_state->secure_level, ret);
  557. SDE_EVT32(DRMID(crtc), smmu_state->state, smmu_state->prev_state,
  558. smmu_state->transition_type,
  559. smmu_state->transition_error,
  560. smmu_state->secure_level, smmu_state->prev_secure_level,
  561. smmu_state->sui_misr_state, ret, SDE_EVTLOG_FUNC_EXIT);
  562. smmu_state->sui_misr_state = NONE;
  563. smmu_state->transition_type = NONE;
  564. return ret;
  565. }
  566. static int sde_kms_prepare_secure_transition(struct msm_kms *kms,
  567. struct drm_atomic_state *state)
  568. {
  569. struct drm_crtc *crtc;
  570. struct drm_crtc_state *old_crtc_state;
  571. struct drm_plane_state *old_plane_state, *new_plane_state;
  572. struct drm_plane *plane;
  573. struct drm_plane_state *plane_state;
  574. struct sde_kms *sde_kms = to_sde_kms(kms);
  575. struct drm_device *dev = sde_kms->dev;
  576. int i, ops = 0, ret = 0;
  577. bool old_valid_fb = false;
  578. struct sde_kms_smmu_state_data *smmu_state = &sde_kms->smmu_state;
  579. for_each_old_crtc_in_state(state, crtc, old_crtc_state, i) {
  580. if (!crtc->state || !crtc->state->active)
  581. continue;
  582. /*
  583. * It is safe to assume only one active crtc,
  584. * and compatible translation modes on the
  585. * planes staged on this crtc.
  586. * otherwise validation would have failed.
  587. * For this CRTC,
  588. */
  589. /*
  590. * 1. Check if old state on the CRTC has planes
  591. * staged with valid fbs
  592. */
  593. for_each_old_plane_in_state(state, plane, plane_state, i) {
  594. if (!plane_state->crtc)
  595. continue;
  596. if (plane_state->fb) {
  597. old_valid_fb = true;
  598. break;
  599. }
  600. }
  601. /*
  602. * 2.Get the operations needed to be performed before
  603. * secure transition can be initiated.
  604. */
  605. ops = sde_crtc_get_secure_transition_ops(crtc,
  606. old_crtc_state, old_valid_fb);
  607. if (ops < 0) {
  608. SDE_ERROR("invalid secure operations %x\n", ops);
  609. return ops;
  610. }
  611. if (!ops) {
  612. smmu_state->transition_error = false;
  613. goto no_ops;
  614. }
  615. SDE_DEBUG("%d:secure operations(%x) started on state:%pK\n",
  616. crtc->base.id, ops, crtc->state);
  617. SDE_EVT32(DRMID(crtc), ops, crtc->state, old_valid_fb);
  618. /* 3. Perform operations needed for secure transition */
  619. if (ops & SDE_KMS_OPS_WAIT_FOR_TX_DONE) {
  620. SDE_DEBUG("wait_for_transfer_done\n");
  621. sde_kms_wait_for_frame_transfer_complete(kms, crtc);
  622. }
  623. if (ops & SDE_KMS_OPS_CLEANUP_PLANE_FB) {
  624. SDE_DEBUG("cleanup planes\n");
  625. drm_atomic_helper_cleanup_planes(dev, state);
  626. for_each_oldnew_plane_in_state(state, plane,
  627. old_plane_state, new_plane_state, i)
  628. sde_plane_destroy_fb(old_plane_state);
  629. }
  630. if (ops & SDE_KMS_OPS_SECURE_STATE_CHANGE) {
  631. SDE_DEBUG("secure ctrl\n");
  632. _sde_kms_secure_ctrl(sde_kms, crtc, false);
  633. }
  634. if (ops & SDE_KMS_OPS_PREPARE_PLANE_FB) {
  635. SDE_DEBUG("prepare planes %d",
  636. crtc->state->plane_mask);
  637. drm_atomic_crtc_for_each_plane(plane,
  638. crtc) {
  639. const struct drm_plane_helper_funcs *funcs;
  640. plane_state = plane->state;
  641. funcs = plane->helper_private;
  642. SDE_DEBUG("psde:%d FB[%u]\n",
  643. plane->base.id,
  644. plane->fb->base.id);
  645. if (!funcs)
  646. continue;
  647. if (funcs->prepare_fb(plane, plane_state)) {
  648. ret = funcs->prepare_fb(plane,
  649. plane_state);
  650. if (ret)
  651. return ret;
  652. }
  653. }
  654. }
  655. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_EXIT);
  656. SDE_DEBUG("secure operations completed\n");
  657. }
  658. no_ops:
  659. return 0;
  660. }
  661. static int _sde_kms_release_splash_buffer(unsigned int mem_addr,
  662. unsigned int splash_buffer_size,
  663. unsigned int ramdump_base,
  664. unsigned int ramdump_buffer_size)
  665. {
  666. unsigned long pfn_start, pfn_end, pfn_idx;
  667. int ret = 0;
  668. if (!mem_addr || !splash_buffer_size) {
  669. SDE_ERROR("invalid params\n");
  670. return -EINVAL;
  671. }
  672. /* leave ramdump memory only if base address matches */
  673. if (ramdump_base == mem_addr &&
  674. ramdump_buffer_size <= splash_buffer_size) {
  675. mem_addr += ramdump_buffer_size;
  676. splash_buffer_size -= ramdump_buffer_size;
  677. }
  678. pfn_start = mem_addr >> PAGE_SHIFT;
  679. pfn_end = (mem_addr + splash_buffer_size) >> PAGE_SHIFT;
  680. ret = memblock_free(mem_addr, splash_buffer_size);
  681. if (ret) {
  682. SDE_ERROR("continuous splash memory free failed:%d\n", ret);
  683. return ret;
  684. }
  685. for (pfn_idx = pfn_start; pfn_idx < pfn_end; pfn_idx++)
  686. free_reserved_page(pfn_to_page(pfn_idx));
  687. return ret;
  688. }
  689. static int _sde_kms_splash_mem_get(struct sde_kms *sde_kms,
  690. struct sde_splash_mem *splash)
  691. {
  692. struct msm_mmu *mmu = NULL;
  693. int ret = 0;
  694. if (!sde_kms->aspace[0]) {
  695. SDE_ERROR("aspace not found for sde kms node\n");
  696. return -EINVAL;
  697. }
  698. mmu = sde_kms->aspace[0]->mmu;
  699. if (!mmu) {
  700. SDE_ERROR("mmu not found for aspace\n");
  701. return -EINVAL;
  702. }
  703. if (!splash || !mmu->funcs || !mmu->funcs->one_to_one_map) {
  704. SDE_ERROR("invalid input params for map\n");
  705. return -EINVAL;
  706. }
  707. if (!splash->ref_cnt) {
  708. ret = mmu->funcs->one_to_one_map(mmu, splash->splash_buf_base,
  709. splash->splash_buf_base,
  710. splash->splash_buf_size,
  711. IOMMU_READ | IOMMU_NOEXEC);
  712. if (ret)
  713. SDE_ERROR("splash memory smmu map failed:%d\n", ret);
  714. }
  715. splash->ref_cnt++;
  716. SDE_DEBUG("one2one mapping done for base:%lx size:%x ref_cnt:%d\n",
  717. splash->splash_buf_base,
  718. splash->splash_buf_size,
  719. splash->ref_cnt);
  720. return ret;
  721. }
  722. static int _sde_kms_map_all_splash_regions(struct sde_kms *sde_kms)
  723. {
  724. int i = 0;
  725. int ret = 0;
  726. if (!sde_kms)
  727. return -EINVAL;
  728. for (i = 0; i < sde_kms->splash_data.num_splash_displays; i++) {
  729. ret = _sde_kms_splash_mem_get(sde_kms,
  730. sde_kms->splash_data.splash_display[i].splash);
  731. if (ret)
  732. return ret;
  733. }
  734. return ret;
  735. }
  736. static int _sde_kms_splash_mem_put(struct sde_kms *sde_kms,
  737. struct sde_splash_mem *splash)
  738. {
  739. struct msm_mmu *mmu = NULL;
  740. int rc = 0;
  741. if (!sde_kms || !sde_kms->aspace[0] || !sde_kms->aspace[0]->mmu) {
  742. SDE_ERROR("invalid params\n");
  743. return -EINVAL;
  744. }
  745. mmu = sde_kms->aspace[0]->mmu;
  746. if (!splash || !splash->ref_cnt ||
  747. !mmu || !mmu->funcs || !mmu->funcs->one_to_one_unmap)
  748. return -EINVAL;
  749. splash->ref_cnt--;
  750. SDE_DEBUG("splash base:%lx refcnt:%d\n",
  751. splash->splash_buf_base, splash->ref_cnt);
  752. if (!splash->ref_cnt) {
  753. mmu->funcs->one_to_one_unmap(mmu, splash->splash_buf_base,
  754. splash->splash_buf_size);
  755. rc = _sde_kms_release_splash_buffer(splash->splash_buf_base,
  756. splash->splash_buf_size, splash->ramdump_base,
  757. splash->ramdump_size);
  758. splash->splash_buf_base = 0;
  759. splash->splash_buf_size = 0;
  760. }
  761. return rc;
  762. }
  763. static int _sde_kms_unmap_all_splash_regions(struct sde_kms *sde_kms)
  764. {
  765. int i = 0;
  766. int ret = 0;
  767. if (!sde_kms || !sde_kms->splash_data.num_splash_regions)
  768. return -EINVAL;
  769. for (i = 0; i < sde_kms->splash_data.num_splash_displays; i++) {
  770. ret = _sde_kms_splash_mem_put(sde_kms,
  771. sde_kms->splash_data.splash_display[i].splash);
  772. if (ret)
  773. return ret;
  774. }
  775. return ret;
  776. }
  777. static int _sde_kms_get_blank(struct drm_crtc_state *crtc_state,
  778. struct drm_connector_state *conn_state)
  779. {
  780. int lp_mode, blank;
  781. if (crtc_state->active)
  782. lp_mode = sde_connector_get_property(conn_state,
  783. CONNECTOR_PROP_LP);
  784. else
  785. lp_mode = SDE_MODE_DPMS_OFF;
  786. switch (lp_mode) {
  787. case SDE_MODE_DPMS_ON:
  788. blank = DRM_PANEL_BLANK_UNBLANK;
  789. break;
  790. case SDE_MODE_DPMS_LP1:
  791. case SDE_MODE_DPMS_LP2:
  792. blank = DRM_PANEL_BLANK_LP;
  793. break;
  794. case SDE_MODE_DPMS_OFF:
  795. default:
  796. blank = DRM_PANEL_BLANK_POWERDOWN;
  797. break;
  798. }
  799. return blank;
  800. }
  801. static void _sde_kms_drm_check_dpms(struct drm_atomic_state *old_state,
  802. unsigned long event)
  803. {
  804. struct drm_connector *connector;
  805. struct drm_connector_state *old_conn_state;
  806. struct drm_crtc_state *old_crtc_state;
  807. struct drm_crtc *crtc;
  808. int i, old_mode, new_mode, old_fps, new_fps;
  809. for_each_old_connector_in_state(old_state, connector,
  810. old_conn_state, i) {
  811. crtc = connector->state->crtc ? connector->state->crtc :
  812. old_conn_state->crtc;
  813. if (!crtc)
  814. continue;
  815. new_fps = crtc->state->mode.vrefresh;
  816. new_mode = _sde_kms_get_blank(crtc->state, connector->state);
  817. if (old_conn_state->crtc) {
  818. old_crtc_state = drm_atomic_get_existing_crtc_state(
  819. old_state, old_conn_state->crtc);
  820. old_fps = old_crtc_state->mode.vrefresh;
  821. old_mode = _sde_kms_get_blank(old_crtc_state,
  822. old_conn_state);
  823. } else {
  824. old_fps = 0;
  825. old_mode = DRM_PANEL_BLANK_POWERDOWN;
  826. }
  827. if ((old_mode != new_mode) || (old_fps != new_fps)) {
  828. struct drm_panel_notifier notifier_data;
  829. SDE_EVT32(old_mode, new_mode, old_fps, new_fps,
  830. connector->panel, crtc->state->active,
  831. old_conn_state->crtc, event);
  832. pr_debug("change detected (power mode %d->%d, fps %d->%d)\n",
  833. old_mode, new_mode, old_fps, new_fps);
  834. /* If suspend resume and fps change are happening
  835. * at the same time, give preference to power mode
  836. * changes rather than fps change.
  837. */
  838. if ((old_mode == new_mode) && (old_fps != new_fps))
  839. new_mode = DRM_PANEL_BLANK_FPS_CHANGE;
  840. notifier_data.data = &new_mode;
  841. notifier_data.refresh_rate = new_fps;
  842. notifier_data.id = connector->base.id;
  843. if (connector->panel)
  844. drm_panel_notifier_call_chain(connector->panel,
  845. event, &notifier_data);
  846. }
  847. }
  848. }
  849. int sde_kms_vm_primary_prepare_commit(struct sde_kms *sde_kms,
  850. struct drm_atomic_state *state)
  851. {
  852. struct drm_device *ddev;
  853. struct drm_crtc *crtc;
  854. struct drm_encoder *encoder;
  855. struct drm_connector *connector;
  856. struct sde_vm_ops *vm_ops;
  857. struct sde_crtc_state *cstate;
  858. enum sde_crtc_vm_req vm_req;
  859. int rc = 0;
  860. ddev = sde_kms->dev;
  861. vm_ops = sde_vm_get_ops(sde_kms);
  862. if (!vm_ops)
  863. return -EINVAL;
  864. crtc = state->crtcs[0].ptr;
  865. cstate = to_sde_crtc_state(state->crtcs[0].new_state);
  866. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  867. if (vm_req != VM_REQ_ACQUIRE)
  868. return 0;
  869. /* enable MDSS irq line */
  870. sde_irq_update(&sde_kms->base, true);
  871. /* clear the stale IRQ status bits */
  872. if (sde_kms->hw_intr && sde_kms->hw_intr->ops.clear_all_irqs)
  873. sde_kms->hw_intr->ops.clear_all_irqs(sde_kms->hw_intr);
  874. /* enable the display path IRQ's */
  875. drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
  876. sde_encoder_irq_control(encoder, true);
  877. /* Schedule ESD work */
  878. list_for_each_entry(connector, &ddev->mode_config.connector_list, head)
  879. if (drm_connector_mask(connector) & crtc->state->connector_mask)
  880. sde_connector_schedule_status_work(connector, true);
  881. /* handle non-SDE pre_acquire */
  882. if (vm_ops->vm_client_post_acquire)
  883. rc = vm_ops->vm_client_post_acquire(sde_kms);
  884. return rc;
  885. }
  886. int sde_kms_vm_trusted_prepare_commit(struct sde_kms *sde_kms,
  887. struct drm_atomic_state *state)
  888. {
  889. struct drm_device *ddev;
  890. struct drm_plane *plane;
  891. struct sde_crtc_state *cstate;
  892. enum sde_crtc_vm_req vm_req;
  893. ddev = sde_kms->dev;
  894. cstate = to_sde_crtc_state(state->crtcs[0].new_state);
  895. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  896. if (vm_req != VM_REQ_ACQUIRE)
  897. return 0;
  898. /* Clear the stale IRQ status bits */
  899. if (sde_kms->hw_intr && sde_kms->hw_intr->ops.clear_all_irqs)
  900. sde_kms->hw_intr->ops.clear_all_irqs(sde_kms->hw_intr);
  901. /* Program the SID's for the trusted VM */
  902. list_for_each_entry(plane, &ddev->mode_config.plane_list, head)
  903. sde_plane_set_sid(plane, 1);
  904. sde_hw_set_lutdma_sid(sde_kms->hw_sid, 1);
  905. return 0;
  906. }
  907. static void sde_kms_prepare_commit(struct msm_kms *kms,
  908. struct drm_atomic_state *state)
  909. {
  910. struct sde_kms *sde_kms;
  911. struct msm_drm_private *priv;
  912. struct drm_device *dev;
  913. struct drm_encoder *encoder;
  914. struct drm_crtc *crtc;
  915. struct drm_crtc_state *crtc_state;
  916. struct sde_vm_ops *vm_ops;
  917. int i, rc;
  918. if (!kms)
  919. return;
  920. sde_kms = to_sde_kms(kms);
  921. dev = sde_kms->dev;
  922. if (!dev || !dev->dev_private)
  923. return;
  924. priv = dev->dev_private;
  925. SDE_ATRACE_BEGIN("prepare_commit");
  926. rc = pm_runtime_get_sync(sde_kms->dev->dev);
  927. if (rc < 0) {
  928. SDE_ERROR("failed to enable power resources %d\n", rc);
  929. SDE_EVT32(rc, SDE_EVTLOG_ERROR);
  930. goto end;
  931. }
  932. if (sde_kms->first_kickoff) {
  933. sde_power_scale_reg_bus(&priv->phandle, VOTE_INDEX_HIGH, false);
  934. sde_kms->first_kickoff = false;
  935. }
  936. for_each_old_crtc_in_state(state, crtc, crtc_state, i) {
  937. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  938. head) {
  939. if (encoder->crtc != crtc)
  940. continue;
  941. if (sde_encoder_prepare_commit(encoder) == -ETIMEDOUT) {
  942. SDE_ERROR("crtc:%d, initiating hw reset\n",
  943. DRMID(crtc));
  944. sde_encoder_needs_hw_reset(encoder);
  945. sde_crtc_set_needs_hw_reset(crtc);
  946. }
  947. }
  948. }
  949. /*
  950. * NOTE: for secure use cases we want to apply the new HW
  951. * configuration only after completing preparation for secure
  952. * transitions prepare below if any transtions is required.
  953. */
  954. sde_kms_prepare_secure_transition(kms, state);
  955. vm_ops = sde_vm_get_ops(sde_kms);
  956. if (!vm_ops)
  957. goto end_vm;
  958. if (vm_ops->vm_prepare_commit)
  959. vm_ops->vm_prepare_commit(sde_kms, state);
  960. end_vm:
  961. _sde_kms_drm_check_dpms(state, DRM_PANEL_EARLY_EVENT_BLANK);
  962. end:
  963. SDE_ATRACE_END("prepare_commit");
  964. }
  965. static void sde_kms_commit(struct msm_kms *kms,
  966. struct drm_atomic_state *old_state)
  967. {
  968. struct sde_kms *sde_kms;
  969. struct drm_crtc *crtc;
  970. struct drm_crtc_state *old_crtc_state;
  971. int i;
  972. if (!kms || !old_state)
  973. return;
  974. sde_kms = to_sde_kms(kms);
  975. if (!sde_kms_power_resource_is_enabled(sde_kms->dev)) {
  976. SDE_ERROR("power resource is not enabled\n");
  977. return;
  978. }
  979. SDE_ATRACE_BEGIN("sde_kms_commit");
  980. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  981. if (crtc->state->active) {
  982. SDE_EVT32(DRMID(crtc));
  983. sde_crtc_commit_kickoff(crtc, old_crtc_state);
  984. }
  985. }
  986. SDE_ATRACE_END("sde_kms_commit");
  987. }
  988. static void _sde_kms_free_splash_display_data(struct sde_kms *sde_kms,
  989. struct sde_splash_display *splash_display)
  990. {
  991. if (!sde_kms || !splash_display ||
  992. !sde_kms->splash_data.num_splash_displays)
  993. return;
  994. if (sde_kms->splash_data.num_splash_regions)
  995. _sde_kms_splash_mem_put(sde_kms, splash_display->splash);
  996. sde_kms->splash_data.num_splash_displays--;
  997. SDE_DEBUG("cont_splash handoff done, remaining:%d\n",
  998. sde_kms->splash_data.num_splash_displays);
  999. memset(splash_display, 0x0, sizeof(struct sde_splash_display));
  1000. }
  1001. static void _sde_kms_release_splash_resource(struct sde_kms *sde_kms,
  1002. struct drm_crtc *crtc)
  1003. {
  1004. struct msm_drm_private *priv;
  1005. struct sde_splash_display *splash_display;
  1006. int i;
  1007. if (!sde_kms || !crtc)
  1008. return;
  1009. priv = sde_kms->dev->dev_private;
  1010. if (!crtc->state->active || !sde_kms->splash_data.num_splash_displays)
  1011. return;
  1012. SDE_EVT32(DRMID(crtc), crtc->state->active,
  1013. sde_kms->splash_data.num_splash_displays);
  1014. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  1015. splash_display = &sde_kms->splash_data.splash_display[i];
  1016. if (splash_display->encoder &&
  1017. crtc == splash_display->encoder->crtc)
  1018. break;
  1019. }
  1020. if (i >= MAX_DSI_DISPLAYS)
  1021. return;
  1022. if (splash_display->cont_splash_enabled) {
  1023. sde_encoder_update_caps_for_cont_splash(splash_display->encoder,
  1024. splash_display, false);
  1025. _sde_kms_free_splash_display_data(sde_kms, splash_display);
  1026. }
  1027. /* remove the votes if all displays are done with splash */
  1028. if (!sde_kms->splash_data.num_splash_displays) {
  1029. for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++)
  1030. sde_power_data_bus_set_quota(&priv->phandle, i,
  1031. SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA,
  1032. SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA);
  1033. pm_runtime_put_sync(sde_kms->dev->dev);
  1034. }
  1035. }
  1036. void _sde_kms_program_mode_info(struct sde_kms *sde_kms)
  1037. {
  1038. struct drm_encoder *encoder;
  1039. struct drm_crtc *crtc;
  1040. struct drm_connector *connector;
  1041. struct drm_connector_list_iter conn_iter;
  1042. struct dsi_display *dsi_display;
  1043. struct drm_display_mode *drm_mode;
  1044. int i;
  1045. struct drm_device *dev;
  1046. u32 mode_index = 0;
  1047. if (!sde_kms->dev || !sde_kms->hw_mdp)
  1048. return;
  1049. dev = sde_kms->dev;
  1050. sde_kms->hw_mdp->ops.clear_mode_index(sde_kms->hw_mdp);
  1051. for (i = 0; i < sde_kms->dsi_display_count; i++) {
  1052. dsi_display = (struct dsi_display *)sde_kms->dsi_displays[i];
  1053. if (dsi_display->bridge->base.encoder) {
  1054. encoder = dsi_display->bridge->base.encoder;
  1055. crtc = encoder->crtc;
  1056. if (!crtc->state->active)
  1057. continue;
  1058. mutex_lock(&dev->mode_config.mutex);
  1059. drm_connector_list_iter_begin(dev, &conn_iter);
  1060. drm_for_each_connector_iter(connector, &conn_iter) {
  1061. if (connector->encoder_ids[0]
  1062. == encoder->base.id)
  1063. break;
  1064. }
  1065. drm_connector_list_iter_end(&conn_iter);
  1066. mutex_unlock(&dev->mode_config.mutex);
  1067. list_for_each_entry(drm_mode, &connector->modes, head) {
  1068. if (drm_mode_equal(
  1069. &crtc->state->mode, drm_mode))
  1070. break;
  1071. mode_index++;
  1072. }
  1073. sde_kms->hw_mdp->ops.set_mode_index(
  1074. sde_kms->hw_mdp, i, mode_index);
  1075. SDE_DEBUG("crtc:%d, display_idx:%d, mode_index:%d\n",
  1076. DRMID(crtc), i, mode_index);
  1077. }
  1078. }
  1079. }
  1080. int sde_kms_vm_trusted_post_commit(struct sde_kms *sde_kms,
  1081. struct drm_atomic_state *state)
  1082. {
  1083. struct sde_vm_ops *vm_ops;
  1084. struct drm_device *ddev;
  1085. struct drm_crtc *crtc;
  1086. struct drm_plane *plane;
  1087. struct drm_encoder *encoder;
  1088. struct sde_crtc_state *cstate;
  1089. struct drm_crtc_state *new_cstate;
  1090. enum sde_crtc_vm_req vm_req;
  1091. int rc = 0;
  1092. if (!sde_kms || !sde_vm_is_enabled(sde_kms))
  1093. return -EINVAL;
  1094. vm_ops = sde_vm_get_ops(sde_kms);
  1095. ddev = sde_kms->dev;
  1096. crtc = state->crtcs[0].ptr;
  1097. new_cstate = state->crtcs[0].new_state;
  1098. cstate = to_sde_crtc_state(new_cstate);
  1099. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  1100. if (vm_req != VM_REQ_RELEASE)
  1101. return rc;
  1102. if (!new_cstate->active && !new_cstate->active_changed)
  1103. return rc;
  1104. /* if vm_req is enabled, once CRTC on the commit is guaranteed */
  1105. sde_kms_wait_for_frame_transfer_complete(&sde_kms->base, crtc);
  1106. drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
  1107. sde_encoder_irq_control(encoder, false);
  1108. list_for_each_entry(plane, &ddev->mode_config.plane_list, head)
  1109. sde_plane_set_sid(plane, 0);
  1110. sde_hw_set_lutdma_sid(sde_kms->hw_sid, 0);
  1111. sde_kms_vm_trusted_resource_deinit(sde_kms);
  1112. if (vm_ops->vm_release)
  1113. rc = vm_ops->vm_release(sde_kms);
  1114. return rc;
  1115. }
  1116. int sde_kms_vm_pre_release(struct sde_kms *sde_kms,
  1117. struct drm_atomic_state *state)
  1118. {
  1119. struct drm_device *ddev;
  1120. struct drm_crtc *crtc;
  1121. struct drm_encoder *encoder;
  1122. struct drm_connector *connector;
  1123. int rc = 0;
  1124. ddev = sde_kms->dev;
  1125. crtc = state->crtcs[0].ptr;
  1126. /* if vm_req is enabled, once CRTC on the commit is guaranteed */
  1127. sde_kms_wait_for_frame_transfer_complete(&sde_kms->base, crtc);
  1128. /* disable ESD work */
  1129. list_for_each_entry(connector,
  1130. &ddev->mode_config.connector_list, head) {
  1131. if (drm_connector_mask(connector) & crtc->state->connector_mask)
  1132. sde_connector_schedule_status_work(connector, false);
  1133. }
  1134. /* disable SDE irq's */
  1135. drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
  1136. sde_encoder_irq_control(encoder, false);
  1137. /* disable IRQ line */
  1138. sde_irq_update(&sde_kms->base, false);
  1139. return rc;
  1140. }
  1141. int sde_kms_vm_primary_post_commit(struct sde_kms *sde_kms,
  1142. struct drm_atomic_state *state)
  1143. {
  1144. struct sde_vm_ops *vm_ops;
  1145. struct sde_crtc_state *cstate;
  1146. struct drm_crtc *crtc;
  1147. enum sde_crtc_vm_req vm_req;
  1148. int rc = 0;
  1149. if (!sde_kms || !sde_vm_is_enabled(sde_kms))
  1150. return -EINVAL;
  1151. vm_ops = sde_vm_get_ops(sde_kms);
  1152. crtc = state->crtcs[0].ptr;
  1153. cstate = to_sde_crtc_state(state->crtcs[0].new_state);
  1154. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  1155. if (vm_req != VM_REQ_RELEASE)
  1156. goto exit;
  1157. /* handle SDE pre-release */
  1158. sde_kms_vm_pre_release(sde_kms, state);
  1159. /* properly handoff color processing features */
  1160. sde_cp_crtc_vm_primary_handoff(crtc);
  1161. /* program the current drm mode info to scratch reg */
  1162. _sde_kms_program_mode_info(sde_kms);
  1163. /* handle non-SDE clients pre-release */
  1164. if (vm_ops->vm_client_pre_release) {
  1165. rc = vm_ops->vm_client_pre_release(sde_kms);
  1166. if (rc) {
  1167. SDE_ERROR("sde vm pre_release failed, rc=%d\n", rc);
  1168. goto exit;
  1169. }
  1170. }
  1171. /* release HW */
  1172. if (vm_ops->vm_release) {
  1173. rc = vm_ops->vm_release(sde_kms);
  1174. if (rc)
  1175. SDE_ERROR("sde vm assign failed, rc=%d\n", rc);
  1176. }
  1177. exit:
  1178. return rc;
  1179. }
  1180. static void sde_kms_complete_commit(struct msm_kms *kms,
  1181. struct drm_atomic_state *old_state)
  1182. {
  1183. struct sde_kms *sde_kms;
  1184. struct msm_drm_private *priv;
  1185. struct drm_crtc *crtc;
  1186. struct drm_crtc_state *old_crtc_state;
  1187. struct drm_connector *connector;
  1188. struct drm_connector_state *old_conn_state;
  1189. struct msm_display_conn_params params;
  1190. struct sde_vm_ops *vm_ops;
  1191. int i, rc = 0;
  1192. if (!kms || !old_state)
  1193. return;
  1194. sde_kms = to_sde_kms(kms);
  1195. if (!sde_kms->dev || !sde_kms->dev->dev_private)
  1196. return;
  1197. priv = sde_kms->dev->dev_private;
  1198. if (sde_kms_power_resource_is_enabled(sde_kms->dev) < 0) {
  1199. SDE_ERROR("power resource is not enabled\n");
  1200. return;
  1201. }
  1202. SDE_ATRACE_BEGIN("sde_kms_complete_commit");
  1203. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  1204. sde_crtc_complete_commit(crtc, old_crtc_state);
  1205. /* complete secure transitions if any */
  1206. if (sde_kms->smmu_state.transition_type == POST_COMMIT)
  1207. _sde_kms_secure_ctrl(sde_kms, crtc, true);
  1208. }
  1209. for_each_old_connector_in_state(old_state, connector,
  1210. old_conn_state, i) {
  1211. struct sde_connector *c_conn;
  1212. c_conn = to_sde_connector(connector);
  1213. if (!c_conn->ops.post_kickoff)
  1214. continue;
  1215. memset(&params, 0, sizeof(params));
  1216. sde_connector_complete_qsync_commit(connector, &params);
  1217. rc = c_conn->ops.post_kickoff(connector, &params);
  1218. if (rc) {
  1219. pr_err("Connector Post kickoff failed rc=%d\n",
  1220. rc);
  1221. }
  1222. }
  1223. vm_ops = sde_vm_get_ops(sde_kms);
  1224. if (vm_ops && vm_ops->vm_post_commit) {
  1225. rc = vm_ops->vm_post_commit(sde_kms, old_state);
  1226. if (rc)
  1227. SDE_ERROR("vm post commit failed, rc = %d\n",
  1228. rc);
  1229. }
  1230. _sde_kms_drm_check_dpms(old_state, DRM_PANEL_EVENT_BLANK);
  1231. pm_runtime_put_sync(sde_kms->dev->dev);
  1232. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i)
  1233. _sde_kms_release_splash_resource(sde_kms, crtc);
  1234. SDE_EVT32_VERBOSE(SDE_EVTLOG_FUNC_EXIT);
  1235. SDE_ATRACE_END("sde_kms_complete_commit");
  1236. }
  1237. static void sde_kms_wait_for_commit_done(struct msm_kms *kms,
  1238. struct drm_crtc *crtc)
  1239. {
  1240. struct drm_encoder *encoder;
  1241. struct drm_device *dev;
  1242. int ret;
  1243. if (!kms || !crtc || !crtc->state) {
  1244. SDE_ERROR("invalid params\n");
  1245. return;
  1246. }
  1247. dev = crtc->dev;
  1248. if (!crtc->state->enable) {
  1249. SDE_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
  1250. return;
  1251. }
  1252. if (!crtc->state->active) {
  1253. SDE_DEBUG("[crtc:%d] not active\n", crtc->base.id);
  1254. return;
  1255. }
  1256. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  1257. SDE_ERROR("power resource is not enabled\n");
  1258. return;
  1259. }
  1260. SDE_ATRACE_BEGIN("sde_kms_wait_for_commit_done");
  1261. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  1262. if (encoder->crtc != crtc)
  1263. continue;
  1264. /*
  1265. * Wait for post-flush if necessary to delay before
  1266. * plane_cleanup. For example, wait for vsync in case of video
  1267. * mode panels. This may be a no-op for command mode panels.
  1268. */
  1269. SDE_EVT32_VERBOSE(DRMID(crtc));
  1270. ret = sde_encoder_wait_for_event(encoder, MSM_ENC_COMMIT_DONE);
  1271. if (ret && ret != -EWOULDBLOCK) {
  1272. SDE_ERROR("wait for commit done returned %d\n", ret);
  1273. sde_crtc_request_frame_reset(crtc);
  1274. break;
  1275. }
  1276. sde_crtc_complete_flip(crtc, NULL);
  1277. }
  1278. sde_crtc_static_cache_read_kickoff(crtc);
  1279. SDE_ATRACE_END("sde_ksm_wait_for_commit_done");
  1280. }
  1281. static void sde_kms_prepare_fence(struct msm_kms *kms,
  1282. struct drm_atomic_state *old_state)
  1283. {
  1284. struct drm_crtc *crtc;
  1285. struct drm_crtc_state *old_crtc_state;
  1286. int i, rc;
  1287. if (!kms || !old_state || !old_state->dev || !old_state->acquire_ctx) {
  1288. SDE_ERROR("invalid argument(s)\n");
  1289. return;
  1290. }
  1291. SDE_ATRACE_BEGIN("sde_kms_prepare_fence");
  1292. retry:
  1293. /* attempt to acquire ww mutex for connection */
  1294. rc = drm_modeset_lock(&old_state->dev->mode_config.connection_mutex,
  1295. old_state->acquire_ctx);
  1296. if (rc == -EDEADLK) {
  1297. drm_modeset_backoff(old_state->acquire_ctx);
  1298. goto retry;
  1299. }
  1300. /* old_state actually contains updated crtc pointers */
  1301. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  1302. if (crtc->state->active || crtc->state->active_changed)
  1303. sde_crtc_prepare_commit(crtc, old_crtc_state);
  1304. }
  1305. SDE_ATRACE_END("sde_kms_prepare_fence");
  1306. }
  1307. /**
  1308. * _sde_kms_get_displays - query for underlying display handles and cache them
  1309. * @sde_kms: Pointer to sde kms structure
  1310. * Returns: Zero on success
  1311. */
  1312. static int _sde_kms_get_displays(struct sde_kms *sde_kms)
  1313. {
  1314. int rc = -ENOMEM;
  1315. if (!sde_kms) {
  1316. SDE_ERROR("invalid sde kms\n");
  1317. return -EINVAL;
  1318. }
  1319. /* dsi */
  1320. sde_kms->dsi_displays = NULL;
  1321. sde_kms->dsi_display_count = dsi_display_get_num_of_displays();
  1322. if (sde_kms->dsi_display_count) {
  1323. sde_kms->dsi_displays = kcalloc(sde_kms->dsi_display_count,
  1324. sizeof(void *),
  1325. GFP_KERNEL);
  1326. if (!sde_kms->dsi_displays) {
  1327. SDE_ERROR("failed to allocate dsi displays\n");
  1328. goto exit_deinit_dsi;
  1329. }
  1330. sde_kms->dsi_display_count =
  1331. dsi_display_get_active_displays(sde_kms->dsi_displays,
  1332. sde_kms->dsi_display_count);
  1333. }
  1334. /* wb */
  1335. sde_kms->wb_displays = NULL;
  1336. sde_kms->wb_display_count = sde_wb_get_num_of_displays();
  1337. if (sde_kms->wb_display_count) {
  1338. sde_kms->wb_displays = kcalloc(sde_kms->wb_display_count,
  1339. sizeof(void *),
  1340. GFP_KERNEL);
  1341. if (!sde_kms->wb_displays) {
  1342. SDE_ERROR("failed to allocate wb displays\n");
  1343. goto exit_deinit_wb;
  1344. }
  1345. sde_kms->wb_display_count =
  1346. wb_display_get_displays(sde_kms->wb_displays,
  1347. sde_kms->wb_display_count);
  1348. }
  1349. /* dp */
  1350. sde_kms->dp_displays = NULL;
  1351. sde_kms->dp_display_count = dp_display_get_num_of_displays();
  1352. if (sde_kms->dp_display_count) {
  1353. sde_kms->dp_displays = kcalloc(sde_kms->dp_display_count,
  1354. sizeof(void *), GFP_KERNEL);
  1355. if (!sde_kms->dp_displays) {
  1356. SDE_ERROR("failed to allocate dp displays\n");
  1357. goto exit_deinit_dp;
  1358. }
  1359. sde_kms->dp_display_count =
  1360. dp_display_get_displays(sde_kms->dp_displays,
  1361. sde_kms->dp_display_count);
  1362. sde_kms->dp_stream_count = dp_display_get_num_of_streams();
  1363. }
  1364. return 0;
  1365. exit_deinit_dp:
  1366. kfree(sde_kms->dp_displays);
  1367. sde_kms->dp_stream_count = 0;
  1368. sde_kms->dp_display_count = 0;
  1369. sde_kms->dp_displays = NULL;
  1370. exit_deinit_wb:
  1371. kfree(sde_kms->wb_displays);
  1372. sde_kms->wb_display_count = 0;
  1373. sde_kms->wb_displays = NULL;
  1374. exit_deinit_dsi:
  1375. kfree(sde_kms->dsi_displays);
  1376. sde_kms->dsi_display_count = 0;
  1377. sde_kms->dsi_displays = NULL;
  1378. return rc;
  1379. }
  1380. /**
  1381. * _sde_kms_release_displays - release cache of underlying display handles
  1382. * @sde_kms: Pointer to sde kms structure
  1383. */
  1384. static void _sde_kms_release_displays(struct sde_kms *sde_kms)
  1385. {
  1386. if (!sde_kms) {
  1387. SDE_ERROR("invalid sde kms\n");
  1388. return;
  1389. }
  1390. kfree(sde_kms->wb_displays);
  1391. sde_kms->wb_displays = NULL;
  1392. sde_kms->wb_display_count = 0;
  1393. kfree(sde_kms->dsi_displays);
  1394. sde_kms->dsi_displays = NULL;
  1395. sde_kms->dsi_display_count = 0;
  1396. }
  1397. /**
  1398. * _sde_kms_setup_displays - create encoders, bridges and connectors
  1399. * for underlying displays
  1400. * @dev: Pointer to drm device structure
  1401. * @priv: Pointer to private drm device data
  1402. * @sde_kms: Pointer to sde kms structure
  1403. * Returns: Zero on success
  1404. */
  1405. static int _sde_kms_setup_displays(struct drm_device *dev,
  1406. struct msm_drm_private *priv,
  1407. struct sde_kms *sde_kms)
  1408. {
  1409. static const struct sde_connector_ops dsi_ops = {
  1410. .set_info_blob = dsi_conn_set_info_blob,
  1411. .detect = dsi_conn_detect,
  1412. .get_modes = dsi_connector_get_modes,
  1413. .pre_destroy = dsi_connector_put_modes,
  1414. .mode_valid = dsi_conn_mode_valid,
  1415. .get_info = dsi_display_get_info,
  1416. .set_backlight = dsi_display_set_backlight,
  1417. .soft_reset = dsi_display_soft_reset,
  1418. .pre_kickoff = dsi_conn_pre_kickoff,
  1419. .clk_ctrl = dsi_display_clk_ctrl,
  1420. .set_power = dsi_display_set_power,
  1421. .get_mode_info = dsi_conn_get_mode_info,
  1422. .get_dst_format = dsi_display_get_dst_format,
  1423. .post_kickoff = dsi_conn_post_kickoff,
  1424. .check_status = dsi_display_check_status,
  1425. .enable_event = dsi_conn_enable_event,
  1426. .cmd_transfer = dsi_display_cmd_transfer,
  1427. .cont_splash_config = dsi_display_cont_splash_config,
  1428. .cont_splash_res_disable = dsi_display_cont_splash_res_disable,
  1429. .get_panel_vfp = dsi_display_get_panel_vfp,
  1430. .get_default_lms = dsi_display_get_default_lms,
  1431. .cmd_receive = dsi_display_cmd_receive,
  1432. .install_properties = NULL,
  1433. .set_allowed_mode_switch = dsi_conn_set_allowed_mode_switch,
  1434. };
  1435. static const struct sde_connector_ops wb_ops = {
  1436. .post_init = sde_wb_connector_post_init,
  1437. .set_info_blob = sde_wb_connector_set_info_blob,
  1438. .detect = sde_wb_connector_detect,
  1439. .get_modes = sde_wb_connector_get_modes,
  1440. .set_property = sde_wb_connector_set_property,
  1441. .get_info = sde_wb_get_info,
  1442. .soft_reset = NULL,
  1443. .get_mode_info = sde_wb_get_mode_info,
  1444. .get_dst_format = NULL,
  1445. .check_status = NULL,
  1446. .cmd_transfer = NULL,
  1447. .cont_splash_config = NULL,
  1448. .cont_splash_res_disable = NULL,
  1449. .get_panel_vfp = NULL,
  1450. .cmd_receive = NULL,
  1451. .install_properties = NULL,
  1452. .set_allowed_mode_switch = NULL,
  1453. };
  1454. static const struct sde_connector_ops dp_ops = {
  1455. .post_init = dp_connector_post_init,
  1456. .detect = dp_connector_detect,
  1457. .get_modes = dp_connector_get_modes,
  1458. .atomic_check = dp_connector_atomic_check,
  1459. .mode_valid = dp_connector_mode_valid,
  1460. .get_info = dp_connector_get_info,
  1461. .get_mode_info = dp_connector_get_mode_info,
  1462. .post_open = dp_connector_post_open,
  1463. .check_status = NULL,
  1464. .set_colorspace = dp_connector_set_colorspace,
  1465. .config_hdr = dp_connector_config_hdr,
  1466. .cmd_transfer = NULL,
  1467. .cont_splash_config = NULL,
  1468. .cont_splash_res_disable = NULL,
  1469. .get_panel_vfp = NULL,
  1470. .update_pps = dp_connector_update_pps,
  1471. .cmd_receive = NULL,
  1472. .install_properties = dp_connector_install_properties,
  1473. .set_allowed_mode_switch = NULL,
  1474. };
  1475. struct msm_display_info info;
  1476. struct drm_encoder *encoder;
  1477. void *display, *connector;
  1478. int i, max_encoders;
  1479. int rc = 0;
  1480. u32 dsc_count = 0, mixer_count = 0;
  1481. u32 max_dp_dsc_count, max_dp_mixer_count;
  1482. if (!dev || !priv || !sde_kms) {
  1483. SDE_ERROR("invalid argument(s)\n");
  1484. return -EINVAL;
  1485. }
  1486. max_encoders = sde_kms->dsi_display_count + sde_kms->wb_display_count +
  1487. sde_kms->dp_display_count +
  1488. sde_kms->dp_stream_count;
  1489. if (max_encoders > ARRAY_SIZE(priv->encoders)) {
  1490. max_encoders = ARRAY_SIZE(priv->encoders);
  1491. SDE_ERROR("capping number of displays to %d", max_encoders);
  1492. }
  1493. /* wb */
  1494. for (i = 0; i < sde_kms->wb_display_count &&
  1495. priv->num_encoders < max_encoders; ++i) {
  1496. display = sde_kms->wb_displays[i];
  1497. encoder = NULL;
  1498. memset(&info, 0x0, sizeof(info));
  1499. rc = sde_wb_get_info(NULL, &info, display);
  1500. if (rc) {
  1501. SDE_ERROR("wb get_info %d failed\n", i);
  1502. continue;
  1503. }
  1504. encoder = sde_encoder_init(dev, &info);
  1505. if (IS_ERR_OR_NULL(encoder)) {
  1506. SDE_ERROR("encoder init failed for wb %d\n", i);
  1507. continue;
  1508. }
  1509. rc = sde_wb_drm_init(display, encoder);
  1510. if (rc) {
  1511. SDE_ERROR("wb bridge %d init failed, %d\n", i, rc);
  1512. sde_encoder_destroy(encoder);
  1513. continue;
  1514. }
  1515. connector = sde_connector_init(dev,
  1516. encoder,
  1517. 0,
  1518. display,
  1519. &wb_ops,
  1520. DRM_CONNECTOR_POLL_HPD,
  1521. DRM_MODE_CONNECTOR_VIRTUAL);
  1522. if (connector) {
  1523. priv->encoders[priv->num_encoders++] = encoder;
  1524. priv->connectors[priv->num_connectors++] = connector;
  1525. } else {
  1526. SDE_ERROR("wb %d connector init failed\n", i);
  1527. sde_wb_drm_deinit(display);
  1528. sde_encoder_destroy(encoder);
  1529. }
  1530. }
  1531. /* dsi */
  1532. for (i = 0; i < sde_kms->dsi_display_count &&
  1533. priv->num_encoders < max_encoders; ++i) {
  1534. display = sde_kms->dsi_displays[i];
  1535. encoder = NULL;
  1536. memset(&info, 0x0, sizeof(info));
  1537. rc = dsi_display_get_info(NULL, &info, display);
  1538. if (rc) {
  1539. SDE_ERROR("dsi get_info %d failed\n", i);
  1540. continue;
  1541. }
  1542. encoder = sde_encoder_init(dev, &info);
  1543. if (IS_ERR_OR_NULL(encoder)) {
  1544. SDE_ERROR("encoder init failed for dsi %d\n", i);
  1545. continue;
  1546. }
  1547. rc = dsi_display_drm_bridge_init(display, encoder);
  1548. if (rc) {
  1549. SDE_ERROR("dsi bridge %d init failed, %d\n", i, rc);
  1550. sde_encoder_destroy(encoder);
  1551. continue;
  1552. }
  1553. connector = sde_connector_init(dev,
  1554. encoder,
  1555. dsi_display_get_drm_panel(display),
  1556. display,
  1557. &dsi_ops,
  1558. DRM_CONNECTOR_POLL_HPD,
  1559. DRM_MODE_CONNECTOR_DSI);
  1560. if (connector) {
  1561. priv->encoders[priv->num_encoders++] = encoder;
  1562. priv->connectors[priv->num_connectors++] = connector;
  1563. } else {
  1564. SDE_ERROR("dsi %d connector init failed\n", i);
  1565. dsi_display_drm_bridge_deinit(display);
  1566. sde_encoder_destroy(encoder);
  1567. continue;
  1568. }
  1569. rc = dsi_display_drm_ext_bridge_init(display,
  1570. encoder, connector);
  1571. if (rc) {
  1572. SDE_ERROR("dsi %d ext bridge init failed\n", rc);
  1573. dsi_display_drm_bridge_deinit(display);
  1574. sde_connector_destroy(connector);
  1575. sde_encoder_destroy(encoder);
  1576. }
  1577. dsc_count += info.dsc_count;
  1578. mixer_count += info.lm_count;
  1579. }
  1580. max_dp_mixer_count = sde_kms->catalog->mixer_count > mixer_count ?
  1581. sde_kms->catalog->mixer_count - mixer_count : 0;
  1582. max_dp_dsc_count = sde_kms->catalog->dsc_count > dsc_count ?
  1583. sde_kms->catalog->dsc_count - dsc_count : 0;
  1584. /* dp */
  1585. for (i = 0; i < sde_kms->dp_display_count &&
  1586. priv->num_encoders < max_encoders; ++i) {
  1587. int idx;
  1588. display = sde_kms->dp_displays[i];
  1589. encoder = NULL;
  1590. memset(&info, 0x0, sizeof(info));
  1591. rc = dp_connector_get_info(NULL, &info, display);
  1592. if (rc) {
  1593. SDE_ERROR("dp get_info %d failed\n", i);
  1594. continue;
  1595. }
  1596. encoder = sde_encoder_init(dev, &info);
  1597. if (IS_ERR_OR_NULL(encoder)) {
  1598. SDE_ERROR("dp encoder init failed %d\n", i);
  1599. continue;
  1600. }
  1601. rc = dp_drm_bridge_init(display, encoder,
  1602. max_dp_mixer_count, max_dp_dsc_count);
  1603. if (rc) {
  1604. SDE_ERROR("dp bridge %d init failed, %d\n", i, rc);
  1605. sde_encoder_destroy(encoder);
  1606. continue;
  1607. }
  1608. connector = sde_connector_init(dev,
  1609. encoder,
  1610. NULL,
  1611. display,
  1612. &dp_ops,
  1613. DRM_CONNECTOR_POLL_HPD,
  1614. DRM_MODE_CONNECTOR_DisplayPort);
  1615. if (connector) {
  1616. priv->encoders[priv->num_encoders++] = encoder;
  1617. priv->connectors[priv->num_connectors++] = connector;
  1618. } else {
  1619. SDE_ERROR("dp %d connector init failed\n", i);
  1620. dp_drm_bridge_deinit(display);
  1621. sde_encoder_destroy(encoder);
  1622. }
  1623. /* update display cap to MST_MODE for DP MST encoders */
  1624. info.capabilities |= MSM_DISPLAY_CAP_MST_MODE;
  1625. for (idx = 0; idx < sde_kms->dp_stream_count &&
  1626. priv->num_encoders < max_encoders; idx++) {
  1627. info.h_tile_instance[0] = idx;
  1628. encoder = sde_encoder_init(dev, &info);
  1629. if (IS_ERR_OR_NULL(encoder)) {
  1630. SDE_ERROR("dp mst encoder init failed %d\n", i);
  1631. continue;
  1632. }
  1633. rc = dp_mst_drm_bridge_init(display, encoder);
  1634. if (rc) {
  1635. SDE_ERROR("dp mst bridge %d init failed, %d\n",
  1636. i, rc);
  1637. sde_encoder_destroy(encoder);
  1638. continue;
  1639. }
  1640. priv->encoders[priv->num_encoders++] = encoder;
  1641. }
  1642. }
  1643. return 0;
  1644. }
  1645. static void _sde_kms_drm_obj_destroy(struct sde_kms *sde_kms)
  1646. {
  1647. struct msm_drm_private *priv;
  1648. int i;
  1649. if (!sde_kms) {
  1650. SDE_ERROR("invalid sde_kms\n");
  1651. return;
  1652. } else if (!sde_kms->dev) {
  1653. SDE_ERROR("invalid dev\n");
  1654. return;
  1655. } else if (!sde_kms->dev->dev_private) {
  1656. SDE_ERROR("invalid dev_private\n");
  1657. return;
  1658. }
  1659. priv = sde_kms->dev->dev_private;
  1660. for (i = 0; i < priv->num_crtcs; i++)
  1661. priv->crtcs[i]->funcs->destroy(priv->crtcs[i]);
  1662. priv->num_crtcs = 0;
  1663. for (i = 0; i < priv->num_planes; i++)
  1664. priv->planes[i]->funcs->destroy(priv->planes[i]);
  1665. priv->num_planes = 0;
  1666. for (i = 0; i < priv->num_connectors; i++)
  1667. priv->connectors[i]->funcs->destroy(priv->connectors[i]);
  1668. priv->num_connectors = 0;
  1669. for (i = 0; i < priv->num_encoders; i++)
  1670. priv->encoders[i]->funcs->destroy(priv->encoders[i]);
  1671. priv->num_encoders = 0;
  1672. _sde_kms_release_displays(sde_kms);
  1673. }
  1674. static int _sde_kms_drm_obj_init(struct sde_kms *sde_kms)
  1675. {
  1676. struct drm_device *dev;
  1677. struct drm_plane *primary_planes[MAX_PLANES], *plane;
  1678. struct drm_crtc *crtc;
  1679. struct msm_drm_private *priv;
  1680. struct sde_mdss_cfg *catalog;
  1681. int primary_planes_idx = 0, i, ret;
  1682. int max_crtc_count;
  1683. u32 sspp_id[MAX_PLANES];
  1684. u32 master_plane_id[MAX_PLANES];
  1685. u32 num_virt_planes = 0;
  1686. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  1687. SDE_ERROR("invalid sde_kms\n");
  1688. return -EINVAL;
  1689. }
  1690. dev = sde_kms->dev;
  1691. priv = dev->dev_private;
  1692. catalog = sde_kms->catalog;
  1693. ret = sde_core_irq_domain_add(sde_kms);
  1694. if (ret)
  1695. goto fail_irq;
  1696. /*
  1697. * Query for underlying display drivers, and create connectors,
  1698. * bridges and encoders for them.
  1699. */
  1700. if (!_sde_kms_get_displays(sde_kms))
  1701. (void)_sde_kms_setup_displays(dev, priv, sde_kms);
  1702. max_crtc_count = min(catalog->mixer_count, priv->num_encoders);
  1703. /* Create the planes */
  1704. for (i = 0; i < catalog->sspp_count; i++) {
  1705. bool primary = true;
  1706. if (catalog->sspp[i].features & BIT(SDE_SSPP_CURSOR)
  1707. || primary_planes_idx >= max_crtc_count)
  1708. primary = false;
  1709. plane = sde_plane_init(dev, catalog->sspp[i].id, primary,
  1710. (1UL << max_crtc_count) - 1, 0);
  1711. if (IS_ERR(plane)) {
  1712. SDE_ERROR("sde_plane_init failed\n");
  1713. ret = PTR_ERR(plane);
  1714. goto fail;
  1715. }
  1716. priv->planes[priv->num_planes++] = plane;
  1717. if (primary)
  1718. primary_planes[primary_planes_idx++] = plane;
  1719. if (sde_hw_sspp_multirect_enabled(&catalog->sspp[i]) &&
  1720. sde_is_custom_client()) {
  1721. int priority =
  1722. catalog->sspp[i].sblk->smart_dma_priority;
  1723. sspp_id[priority - 1] = catalog->sspp[i].id;
  1724. master_plane_id[priority - 1] = plane->base.id;
  1725. num_virt_planes++;
  1726. }
  1727. }
  1728. /* Initialize smart DMA virtual planes */
  1729. for (i = 0; i < num_virt_planes; i++) {
  1730. plane = sde_plane_init(dev, sspp_id[i], false,
  1731. (1UL << max_crtc_count) - 1, master_plane_id[i]);
  1732. if (IS_ERR(plane)) {
  1733. SDE_ERROR("sde_plane for virtual SSPP init failed\n");
  1734. ret = PTR_ERR(plane);
  1735. goto fail;
  1736. }
  1737. priv->planes[priv->num_planes++] = plane;
  1738. }
  1739. max_crtc_count = min(max_crtc_count, primary_planes_idx);
  1740. /* Create one CRTC per encoder */
  1741. for (i = 0; i < max_crtc_count; i++) {
  1742. crtc = sde_crtc_init(dev, primary_planes[i]);
  1743. if (IS_ERR(crtc)) {
  1744. ret = PTR_ERR(crtc);
  1745. goto fail;
  1746. }
  1747. priv->crtcs[priv->num_crtcs++] = crtc;
  1748. }
  1749. if (sde_is_custom_client()) {
  1750. /* All CRTCs are compatible with all planes */
  1751. for (i = 0; i < priv->num_planes; i++)
  1752. priv->planes[i]->possible_crtcs =
  1753. (1 << priv->num_crtcs) - 1;
  1754. }
  1755. /* All CRTCs are compatible with all encoders */
  1756. for (i = 0; i < priv->num_encoders; i++)
  1757. priv->encoders[i]->possible_crtcs = (1 << priv->num_crtcs) - 1;
  1758. return 0;
  1759. fail:
  1760. _sde_kms_drm_obj_destroy(sde_kms);
  1761. fail_irq:
  1762. sde_core_irq_domain_fini(sde_kms);
  1763. return ret;
  1764. }
  1765. /**
  1766. * sde_kms_timeline_status - provides current timeline status
  1767. * This API should be called without mode config lock.
  1768. * @dev: Pointer to drm device
  1769. */
  1770. void sde_kms_timeline_status(struct drm_device *dev)
  1771. {
  1772. struct drm_crtc *crtc;
  1773. struct drm_connector *conn;
  1774. struct drm_connector_list_iter conn_iter;
  1775. if (!dev) {
  1776. SDE_ERROR("invalid drm device node\n");
  1777. return;
  1778. }
  1779. drm_for_each_crtc(crtc, dev)
  1780. sde_crtc_timeline_status(crtc);
  1781. if (mutex_is_locked(&dev->mode_config.mutex)) {
  1782. /*
  1783. *Probably locked from last close dumping status anyway
  1784. */
  1785. SDE_ERROR("dumping conn_timeline without mode_config lock\n");
  1786. drm_connector_list_iter_begin(dev, &conn_iter);
  1787. drm_for_each_connector_iter(conn, &conn_iter)
  1788. sde_conn_timeline_status(conn);
  1789. drm_connector_list_iter_end(&conn_iter);
  1790. return;
  1791. }
  1792. mutex_lock(&dev->mode_config.mutex);
  1793. drm_connector_list_iter_begin(dev, &conn_iter);
  1794. drm_for_each_connector_iter(conn, &conn_iter)
  1795. sde_conn_timeline_status(conn);
  1796. drm_connector_list_iter_end(&conn_iter);
  1797. mutex_unlock(&dev->mode_config.mutex);
  1798. }
  1799. static int sde_kms_postinit(struct msm_kms *kms)
  1800. {
  1801. struct sde_kms *sde_kms = to_sde_kms(kms);
  1802. struct drm_device *dev;
  1803. struct drm_crtc *crtc;
  1804. int rc;
  1805. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  1806. SDE_ERROR("invalid sde_kms\n");
  1807. return -EINVAL;
  1808. }
  1809. dev = sde_kms->dev;
  1810. rc = _sde_debugfs_init(sde_kms);
  1811. if (rc)
  1812. SDE_ERROR("sde_debugfs init failed: %d\n", rc);
  1813. drm_for_each_crtc(crtc, dev)
  1814. sde_crtc_post_init(dev, crtc);
  1815. return rc;
  1816. }
  1817. static long sde_kms_round_pixclk(struct msm_kms *kms, unsigned long rate,
  1818. struct drm_encoder *encoder)
  1819. {
  1820. return rate;
  1821. }
  1822. static void _sde_kms_hw_destroy(struct sde_kms *sde_kms,
  1823. struct platform_device *pdev)
  1824. {
  1825. struct drm_device *dev;
  1826. struct msm_drm_private *priv;
  1827. struct sde_vm_ops *vm_ops;
  1828. int i;
  1829. if (!sde_kms || !pdev)
  1830. return;
  1831. dev = sde_kms->dev;
  1832. if (!dev)
  1833. return;
  1834. priv = dev->dev_private;
  1835. if (!priv)
  1836. return;
  1837. if (sde_kms->genpd_init) {
  1838. sde_kms->genpd_init = false;
  1839. pm_genpd_remove(&sde_kms->genpd);
  1840. of_genpd_del_provider(pdev->dev.of_node);
  1841. }
  1842. vm_ops = sde_vm_get_ops(sde_kms);
  1843. if (vm_ops && vm_ops->vm_deinit)
  1844. vm_ops->vm_deinit(sde_kms, vm_ops);
  1845. if (sde_kms->hw_intr)
  1846. sde_hw_intr_destroy(sde_kms->hw_intr);
  1847. sde_kms->hw_intr = NULL;
  1848. if (sde_kms->power_event)
  1849. sde_power_handle_unregister_event(
  1850. &priv->phandle, sde_kms->power_event);
  1851. _sde_kms_release_displays(sde_kms);
  1852. _sde_kms_unmap_all_splash_regions(sde_kms);
  1853. if (sde_kms->catalog) {
  1854. for (i = 0; i < sde_kms->catalog->vbif_count; i++) {
  1855. u32 vbif_idx = sde_kms->catalog->vbif[i].id;
  1856. if ((vbif_idx < VBIF_MAX) && sde_kms->hw_vbif[vbif_idx])
  1857. sde_hw_vbif_destroy(sde_kms->hw_vbif[vbif_idx]);
  1858. }
  1859. }
  1860. if (sde_kms->rm_init)
  1861. sde_rm_destroy(&sde_kms->rm);
  1862. sde_kms->rm_init = false;
  1863. if (sde_kms->catalog)
  1864. sde_hw_catalog_deinit(sde_kms->catalog);
  1865. sde_kms->catalog = NULL;
  1866. if (sde_kms->sid)
  1867. msm_iounmap(pdev, sde_kms->sid);
  1868. sde_kms->sid = NULL;
  1869. if (sde_kms->reg_dma)
  1870. msm_iounmap(pdev, sde_kms->reg_dma);
  1871. sde_kms->reg_dma = NULL;
  1872. if (sde_kms->vbif[VBIF_NRT])
  1873. msm_iounmap(pdev, sde_kms->vbif[VBIF_NRT]);
  1874. sde_kms->vbif[VBIF_NRT] = NULL;
  1875. if (sde_kms->vbif[VBIF_RT])
  1876. msm_iounmap(pdev, sde_kms->vbif[VBIF_RT]);
  1877. sde_kms->vbif[VBIF_RT] = NULL;
  1878. if (sde_kms->mmio)
  1879. msm_iounmap(pdev, sde_kms->mmio);
  1880. sde_kms->mmio = NULL;
  1881. sde_reg_dma_deinit();
  1882. _sde_kms_mmu_destroy(sde_kms);
  1883. }
  1884. int sde_kms_mmu_detach(struct sde_kms *sde_kms, bool secure_only)
  1885. {
  1886. int i;
  1887. if (!sde_kms)
  1888. return -EINVAL;
  1889. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  1890. struct msm_mmu *mmu;
  1891. struct msm_gem_address_space *aspace = sde_kms->aspace[i];
  1892. if (!aspace)
  1893. continue;
  1894. mmu = sde_kms->aspace[i]->mmu;
  1895. if (secure_only &&
  1896. !aspace->mmu->funcs->is_domain_secure(mmu))
  1897. continue;
  1898. /* cleanup aspace before detaching */
  1899. msm_gem_aspace_domain_attach_detach_update(aspace, true);
  1900. SDE_DEBUG("Detaching domain:%d\n", i);
  1901. aspace->mmu->funcs->detach(mmu, (const char **)iommu_ports,
  1902. ARRAY_SIZE(iommu_ports));
  1903. aspace->domain_attached = false;
  1904. }
  1905. return 0;
  1906. }
  1907. int sde_kms_mmu_attach(struct sde_kms *sde_kms, bool secure_only)
  1908. {
  1909. int i;
  1910. if (!sde_kms)
  1911. return -EINVAL;
  1912. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  1913. struct msm_mmu *mmu;
  1914. struct msm_gem_address_space *aspace = sde_kms->aspace[i];
  1915. if (!aspace)
  1916. continue;
  1917. mmu = sde_kms->aspace[i]->mmu;
  1918. if (secure_only &&
  1919. !aspace->mmu->funcs->is_domain_secure(mmu))
  1920. continue;
  1921. SDE_DEBUG("Attaching domain:%d\n", i);
  1922. aspace->mmu->funcs->attach(mmu, (const char **)iommu_ports,
  1923. ARRAY_SIZE(iommu_ports));
  1924. aspace->domain_attached = true;
  1925. msm_gem_aspace_domain_attach_detach_update(aspace, false);
  1926. }
  1927. return 0;
  1928. }
  1929. static void sde_kms_destroy(struct msm_kms *kms)
  1930. {
  1931. struct sde_kms *sde_kms;
  1932. struct drm_device *dev;
  1933. if (!kms) {
  1934. SDE_ERROR("invalid kms\n");
  1935. return;
  1936. }
  1937. sde_kms = to_sde_kms(kms);
  1938. dev = sde_kms->dev;
  1939. if (!dev || !dev->dev) {
  1940. SDE_ERROR("invalid device\n");
  1941. return;
  1942. }
  1943. _sde_kms_hw_destroy(sde_kms, to_platform_device(dev->dev));
  1944. kfree(sde_kms);
  1945. }
  1946. static int _sde_kms_helper_reset_custom_properties(struct sde_kms *sde_kms,
  1947. struct drm_atomic_state *state)
  1948. {
  1949. struct drm_device *dev = sde_kms->dev;
  1950. struct drm_plane *plane;
  1951. struct drm_plane_state *plane_state;
  1952. struct drm_crtc *crtc;
  1953. struct drm_crtc_state *crtc_state;
  1954. struct drm_connector *conn;
  1955. struct drm_connector_state *conn_state;
  1956. struct drm_connector_list_iter conn_iter;
  1957. int ret = 0;
  1958. drm_for_each_plane(plane, dev) {
  1959. plane_state = drm_atomic_get_plane_state(state, plane);
  1960. if (IS_ERR(plane_state)) {
  1961. ret = PTR_ERR(plane_state);
  1962. SDE_ERROR("error %d getting plane %d state\n",
  1963. ret, DRMID(plane));
  1964. return ret;
  1965. }
  1966. ret = sde_plane_helper_reset_custom_properties(plane,
  1967. plane_state);
  1968. if (ret) {
  1969. SDE_ERROR("error %d resetting plane props %d\n",
  1970. ret, DRMID(plane));
  1971. return ret;
  1972. }
  1973. }
  1974. drm_for_each_crtc(crtc, dev) {
  1975. crtc_state = drm_atomic_get_crtc_state(state, crtc);
  1976. if (IS_ERR(crtc_state)) {
  1977. ret = PTR_ERR(crtc_state);
  1978. SDE_ERROR("error %d getting crtc %d state\n",
  1979. ret, DRMID(crtc));
  1980. return ret;
  1981. }
  1982. ret = sde_crtc_helper_reset_custom_properties(crtc, crtc_state);
  1983. if (ret) {
  1984. SDE_ERROR("error %d resetting crtc props %d\n",
  1985. ret, DRMID(crtc));
  1986. return ret;
  1987. }
  1988. }
  1989. drm_connector_list_iter_begin(dev, &conn_iter);
  1990. drm_for_each_connector_iter(conn, &conn_iter) {
  1991. conn_state = drm_atomic_get_connector_state(state, conn);
  1992. if (IS_ERR(conn_state)) {
  1993. ret = PTR_ERR(conn_state);
  1994. SDE_ERROR("error %d getting connector %d state\n",
  1995. ret, DRMID(conn));
  1996. return ret;
  1997. }
  1998. ret = sde_connector_helper_reset_custom_properties(conn,
  1999. conn_state);
  2000. if (ret) {
  2001. SDE_ERROR("error %d resetting connector props %d\n",
  2002. ret, DRMID(conn));
  2003. return ret;
  2004. }
  2005. }
  2006. drm_connector_list_iter_end(&conn_iter);
  2007. return ret;
  2008. }
  2009. static void sde_kms_lastclose(struct msm_kms *kms)
  2010. {
  2011. struct sde_kms *sde_kms;
  2012. struct drm_device *dev;
  2013. struct drm_atomic_state *state;
  2014. struct drm_modeset_acquire_ctx ctx;
  2015. int ret;
  2016. if (!kms) {
  2017. SDE_ERROR("invalid argument\n");
  2018. return;
  2019. }
  2020. sde_kms = to_sde_kms(kms);
  2021. dev = sde_kms->dev;
  2022. drm_modeset_acquire_init(&ctx, 0);
  2023. state = drm_atomic_state_alloc(dev);
  2024. if (!state) {
  2025. ret = -ENOMEM;
  2026. goto out_ctx;
  2027. }
  2028. state->acquire_ctx = &ctx;
  2029. retry:
  2030. ret = drm_modeset_lock_all_ctx(dev, &ctx);
  2031. if (ret)
  2032. goto out_state;
  2033. ret = _sde_kms_helper_reset_custom_properties(sde_kms, state);
  2034. if (ret)
  2035. goto out_state;
  2036. ret = drm_atomic_commit(state);
  2037. out_state:
  2038. if (ret == -EDEADLK)
  2039. goto backoff;
  2040. drm_atomic_state_put(state);
  2041. out_ctx:
  2042. drm_modeset_drop_locks(&ctx);
  2043. drm_modeset_acquire_fini(&ctx);
  2044. if (ret)
  2045. SDE_ERROR("kms lastclose failed: %d\n", ret);
  2046. return;
  2047. backoff:
  2048. drm_atomic_state_clear(state);
  2049. drm_modeset_backoff(&ctx);
  2050. goto retry;
  2051. }
  2052. static int sde_kms_check_vm_request(struct msm_kms *kms,
  2053. struct drm_atomic_state *state)
  2054. {
  2055. struct sde_kms *sde_kms;
  2056. struct drm_device *dev;
  2057. struct drm_crtc *crtc;
  2058. struct drm_crtc_state *new_cstate, *old_cstate;
  2059. uint32_t i, commit_crtc_cnt = 0, global_crtc_cnt = 0;
  2060. struct drm_crtc *active_crtc = NULL, *global_active_crtc = NULL;
  2061. enum sde_crtc_vm_req old_vm_req = VM_REQ_NONE, new_vm_req = VM_REQ_NONE;
  2062. struct sde_vm_ops *vm_ops;
  2063. bool vm_req_active = false;
  2064. enum sde_crtc_idle_pc_state idle_pc_state;
  2065. int rc = 0;
  2066. if (!kms || !state)
  2067. return -EINVAL;
  2068. sde_kms = to_sde_kms(kms);
  2069. dev = sde_kms->dev;
  2070. vm_ops = sde_vm_get_ops(sde_kms);
  2071. if (!vm_ops)
  2072. return 0;
  2073. for_each_oldnew_crtc_in_state(state, crtc, old_cstate, new_cstate, i) {
  2074. struct sde_crtc_state *old_state = NULL, *new_state = NULL;
  2075. new_state = to_sde_crtc_state(new_cstate);
  2076. if (!new_cstate->active && !new_cstate->active_changed)
  2077. continue;
  2078. new_vm_req = sde_crtc_get_property(new_state,
  2079. CRTC_PROP_VM_REQ_STATE);
  2080. commit_crtc_cnt++;
  2081. if (old_cstate) {
  2082. old_state = to_sde_crtc_state(old_cstate);
  2083. old_vm_req = sde_crtc_get_property(old_state,
  2084. CRTC_PROP_VM_REQ_STATE);
  2085. }
  2086. /**
  2087. * No active request if the transition is from
  2088. * VM_REQ_NONE to VM_REQ_NONE
  2089. */
  2090. if (new_vm_req || (old_state && old_vm_req))
  2091. vm_req_active = true;
  2092. idle_pc_state = sde_crtc_get_property(new_state,
  2093. CRTC_PROP_IDLE_PC_STATE);
  2094. active_crtc = crtc;
  2095. }
  2096. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  2097. if (!crtc->state->active)
  2098. continue;
  2099. global_crtc_cnt++;
  2100. global_active_crtc = crtc;
  2101. }
  2102. /* Check for single crtc commits only on valid VM requests */
  2103. if (vm_req_active && active_crtc && global_active_crtc &&
  2104. (commit_crtc_cnt > sde_kms->catalog->max_trusted_vm_displays ||
  2105. global_crtc_cnt > sde_kms->catalog->max_trusted_vm_displays ||
  2106. active_crtc != global_active_crtc)) {
  2107. SDE_ERROR(
  2108. "failed to switch VM due to CRTC concurrencies: MAX_CNT: %d active_cnt: %d global_cnt: %d active_crtc: %d global_crtc: %d\n",
  2109. sde_kms->catalog->max_trusted_vm_displays,
  2110. commit_crtc_cnt, global_crtc_cnt, active_crtc,
  2111. global_active_crtc);
  2112. return -E2BIG;
  2113. }
  2114. if (!vm_req_active)
  2115. return 0;
  2116. /* disable idle-pc before releasing the HW */
  2117. if ((new_vm_req == VM_REQ_RELEASE) &&
  2118. (idle_pc_state == IDLE_PC_ENABLE)) {
  2119. SDE_ERROR("failed to switch VM since idle-pc is enabled\n");
  2120. return -EINVAL;
  2121. }
  2122. sde_vm_lock(sde_kms);
  2123. if (vm_ops->vm_request_valid)
  2124. rc = vm_ops->vm_request_valid(sde_kms, old_vm_req, new_vm_req);
  2125. if (rc)
  2126. SDE_ERROR(
  2127. "failed to complete vm transition request. old_state = %d, new_state = %d, hw_ownership: %d\n",
  2128. old_vm_req, new_vm_req, vm_ops->vm_owns_hw(sde_kms));
  2129. sde_vm_unlock(sde_kms);
  2130. return rc;
  2131. }
  2132. static int sde_kms_check_secure_transition(struct msm_kms *kms,
  2133. struct drm_atomic_state *state)
  2134. {
  2135. struct sde_kms *sde_kms;
  2136. struct drm_device *dev;
  2137. struct drm_crtc *crtc;
  2138. struct drm_crtc *cur_crtc = NULL, *global_crtc = NULL;
  2139. struct drm_crtc_state *crtc_state;
  2140. int active_crtc_cnt = 0, global_active_crtc_cnt = 0;
  2141. bool sec_session = false, global_sec_session = false;
  2142. uint32_t fb_ns = 0, fb_sec = 0, fb_sec_dir = 0;
  2143. int i;
  2144. if (!kms || !state) {
  2145. return -EINVAL;
  2146. SDE_ERROR("invalid arguments\n");
  2147. }
  2148. sde_kms = to_sde_kms(kms);
  2149. dev = sde_kms->dev;
  2150. /* iterate state object for active secure/non-secure crtc */
  2151. for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
  2152. if (!crtc_state->active)
  2153. continue;
  2154. active_crtc_cnt++;
  2155. sde_crtc_state_find_plane_fb_modes(crtc_state, &fb_ns,
  2156. &fb_sec, &fb_sec_dir);
  2157. if (fb_sec_dir)
  2158. sec_session = true;
  2159. cur_crtc = crtc;
  2160. }
  2161. /* iterate global list for active and secure/non-secure crtc */
  2162. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  2163. if (!crtc->state->active)
  2164. continue;
  2165. global_active_crtc_cnt++;
  2166. /* update only when crtc is not the same as current crtc */
  2167. if (crtc != cur_crtc) {
  2168. fb_ns = fb_sec = fb_sec_dir = 0;
  2169. sde_crtc_find_plane_fb_modes(crtc, &fb_ns,
  2170. &fb_sec, &fb_sec_dir);
  2171. if (fb_sec_dir)
  2172. global_sec_session = true;
  2173. global_crtc = crtc;
  2174. }
  2175. }
  2176. if (!global_sec_session && !sec_session)
  2177. return 0;
  2178. /*
  2179. * - fail crtc commit, if secure-camera/secure-ui session is
  2180. * in-progress in any other display
  2181. * - fail secure-camera/secure-ui crtc commit, if any other display
  2182. * session is in-progress
  2183. */
  2184. if ((global_active_crtc_cnt > MAX_ALLOWED_CRTC_CNT_DURING_SECURE) ||
  2185. (active_crtc_cnt > MAX_ALLOWED_CRTC_CNT_DURING_SECURE)) {
  2186. SDE_ERROR(
  2187. "crtc%d secure check failed global_active:%d active:%d\n",
  2188. cur_crtc ? cur_crtc->base.id : -1,
  2189. global_active_crtc_cnt, active_crtc_cnt);
  2190. return -EPERM;
  2191. /*
  2192. * As only one crtc is allowed during secure session, the crtc
  2193. * in this commit should match with the global crtc
  2194. */
  2195. } else if (global_crtc && cur_crtc && (global_crtc != cur_crtc)) {
  2196. SDE_ERROR("crtc%d-sec%d not allowed during crtc%d-sec%d\n",
  2197. cur_crtc->base.id, sec_session,
  2198. global_crtc->base.id, global_sec_session);
  2199. return -EPERM;
  2200. }
  2201. return 0;
  2202. }
  2203. static int sde_kms_atomic_check(struct msm_kms *kms,
  2204. struct drm_atomic_state *state)
  2205. {
  2206. struct sde_kms *sde_kms;
  2207. struct drm_device *dev;
  2208. int ret;
  2209. if (!kms || !state)
  2210. return -EINVAL;
  2211. sde_kms = to_sde_kms(kms);
  2212. dev = sde_kms->dev;
  2213. SDE_ATRACE_BEGIN("atomic_check");
  2214. if (sde_kms_is_suspend_blocked(dev)) {
  2215. SDE_DEBUG("suspended, skip atomic_check\n");
  2216. ret = -EBUSY;
  2217. goto end;
  2218. }
  2219. ret = drm_atomic_helper_check(dev, state);
  2220. if (ret)
  2221. goto end;
  2222. /*
  2223. * Check if any secure transition(moving CRTC between secure and
  2224. * non-secure state and vice-versa) is allowed or not. when moving
  2225. * to secure state, planes with fb_mode set to dir_translated only can
  2226. * be staged on the CRTC, and only one CRTC can be active during
  2227. * Secure state
  2228. */
  2229. ret = sde_kms_check_secure_transition(kms, state);
  2230. if (ret)
  2231. goto end;
  2232. ret = sde_kms_check_vm_request(kms, state);
  2233. if (ret)
  2234. SDE_ERROR("vm switch request checks failed\n");
  2235. end:
  2236. SDE_ATRACE_END("atomic_check");
  2237. return ret;
  2238. }
  2239. static struct msm_gem_address_space*
  2240. _sde_kms_get_address_space(struct msm_kms *kms,
  2241. unsigned int domain)
  2242. {
  2243. struct sde_kms *sde_kms;
  2244. if (!kms) {
  2245. SDE_ERROR("invalid kms\n");
  2246. return NULL;
  2247. }
  2248. sde_kms = to_sde_kms(kms);
  2249. if (!sde_kms) {
  2250. SDE_ERROR("invalid sde_kms\n");
  2251. return NULL;
  2252. }
  2253. if (domain >= MSM_SMMU_DOMAIN_MAX)
  2254. return NULL;
  2255. return (sde_kms->aspace[domain] &&
  2256. sde_kms->aspace[domain]->domain_attached) ?
  2257. sde_kms->aspace[domain] : NULL;
  2258. }
  2259. static struct device *_sde_kms_get_address_space_device(struct msm_kms *kms,
  2260. unsigned int domain)
  2261. {
  2262. struct sde_kms *sde_kms;
  2263. struct msm_gem_address_space *aspace;
  2264. if (!kms) {
  2265. SDE_ERROR("invalid kms\n");
  2266. return NULL;
  2267. }
  2268. sde_kms = to_sde_kms(kms);
  2269. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  2270. SDE_ERROR("invalid params\n");
  2271. return NULL;
  2272. }
  2273. aspace = _sde_kms_get_address_space(kms, domain);
  2274. return (aspace && aspace->domain_attached) ?
  2275. msm_gem_get_aspace_device(aspace) : NULL;
  2276. }
  2277. static void _sde_kms_post_open(struct msm_kms *kms, struct drm_file *file)
  2278. {
  2279. struct drm_device *dev = NULL;
  2280. struct sde_kms *sde_kms = NULL;
  2281. struct drm_connector *connector = NULL;
  2282. struct drm_connector_list_iter conn_iter;
  2283. struct sde_connector *sde_conn = NULL;
  2284. if (!kms) {
  2285. SDE_ERROR("invalid kms\n");
  2286. return;
  2287. }
  2288. sde_kms = to_sde_kms(kms);
  2289. dev = sde_kms->dev;
  2290. if (!dev) {
  2291. SDE_ERROR("invalid device\n");
  2292. return;
  2293. }
  2294. if (!dev->mode_config.poll_enabled)
  2295. return;
  2296. mutex_lock(&dev->mode_config.mutex);
  2297. drm_connector_list_iter_begin(dev, &conn_iter);
  2298. drm_for_each_connector_iter(connector, &conn_iter) {
  2299. /* Only handle HPD capable connectors. */
  2300. if (!(connector->polled & DRM_CONNECTOR_POLL_HPD))
  2301. continue;
  2302. sde_conn = to_sde_connector(connector);
  2303. if (sde_conn->ops.post_open)
  2304. sde_conn->ops.post_open(&sde_conn->base,
  2305. sde_conn->display);
  2306. }
  2307. drm_connector_list_iter_end(&conn_iter);
  2308. mutex_unlock(&dev->mode_config.mutex);
  2309. }
  2310. static int _sde_kms_update_planes_for_cont_splash(struct sde_kms *sde_kms,
  2311. struct sde_splash_display *splash_display,
  2312. struct drm_crtc *crtc)
  2313. {
  2314. struct msm_drm_private *priv;
  2315. struct drm_plane *plane;
  2316. struct sde_splash_mem *splash;
  2317. enum sde_sspp plane_id;
  2318. bool is_virtual;
  2319. int i, j;
  2320. if (!sde_kms || !splash_display || !crtc) {
  2321. SDE_ERROR("invalid input args\n");
  2322. return -EINVAL;
  2323. }
  2324. priv = sde_kms->dev->dev_private;
  2325. for (i = 0; i < priv->num_planes; i++) {
  2326. plane = priv->planes[i];
  2327. plane_id = sde_plane_pipe(plane);
  2328. is_virtual = is_sde_plane_virtual(plane);
  2329. splash = splash_display->splash;
  2330. for (j = 0; j < splash_display->pipe_cnt; j++) {
  2331. if ((plane_id != splash_display->pipes[j].sspp) ||
  2332. (splash_display->pipes[j].is_virtual
  2333. != is_virtual))
  2334. continue;
  2335. if (splash && sde_plane_validate_src_addr(plane,
  2336. splash->splash_buf_base,
  2337. splash->splash_buf_size)) {
  2338. SDE_ERROR("invalid adr on pipe:%d crtc:%d\n",
  2339. plane_id, crtc->base.id);
  2340. }
  2341. SDE_DEBUG("set crtc:%d for plane:%d rect:%d\n",
  2342. crtc->base.id, plane_id, is_virtual);
  2343. }
  2344. }
  2345. return 0;
  2346. }
  2347. static struct drm_display_mode *_sde_kms_get_splash_mode(
  2348. struct sde_kms *sde_kms, struct drm_connector *connector,
  2349. u32 display_idx)
  2350. {
  2351. struct drm_display_mode *drm_mode = NULL, *curr_mode = NULL;
  2352. u32 i = 0, mode_index;
  2353. if (sde_kms->splash_data.type == SDE_SPLASH_HANDOFF) {
  2354. /* currently consider modes[0] as the preferred mode */
  2355. curr_mode = list_first_entry(&connector->modes,
  2356. struct drm_display_mode, head);
  2357. } else if (sde_kms->hw_mdp && sde_kms->hw_mdp->ops.get_mode_index) {
  2358. mode_index = sde_kms->hw_mdp->ops.get_mode_index(
  2359. sde_kms->hw_mdp, display_idx);
  2360. list_for_each_entry(drm_mode, &connector->modes, head) {
  2361. if (mode_index == i) {
  2362. curr_mode = drm_mode;
  2363. break;
  2364. }
  2365. i++;
  2366. }
  2367. }
  2368. return curr_mode;
  2369. }
  2370. static int sde_kms_inform_cont_splash_res_disable(struct msm_kms *kms,
  2371. struct dsi_display *dsi_display)
  2372. {
  2373. void *display;
  2374. struct drm_encoder *encoder = NULL;
  2375. struct msm_display_info info;
  2376. struct drm_device *dev;
  2377. struct sde_kms *sde_kms;
  2378. struct drm_connector_list_iter conn_iter;
  2379. struct drm_connector *connector = NULL;
  2380. struct sde_connector *sde_conn = NULL;
  2381. int rc = 0;
  2382. sde_kms = to_sde_kms(kms);
  2383. dev = sde_kms->dev;
  2384. display = dsi_display;
  2385. if (dsi_display) {
  2386. if (dsi_display->bridge->base.encoder) {
  2387. encoder = dsi_display->bridge->base.encoder;
  2388. SDE_DEBUG("encoder name = %s\n", encoder->name);
  2389. }
  2390. memset(&info, 0x0, sizeof(info));
  2391. rc = dsi_display_get_info(NULL, &info, display);
  2392. if (rc) {
  2393. SDE_ERROR("%s: dsi get_info failed: %d\n",
  2394. rc, __func__);
  2395. encoder = NULL;
  2396. }
  2397. }
  2398. drm_connector_list_iter_begin(dev, &conn_iter);
  2399. drm_for_each_connector_iter(connector, &conn_iter) {
  2400. /**
  2401. * Inform cont_splash is disabled to each interface/connector.
  2402. * This is currently supported for DSI interface.
  2403. */
  2404. sde_conn = to_sde_connector(connector);
  2405. if (sde_conn && sde_conn->ops.cont_splash_res_disable) {
  2406. if (!dsi_display || !encoder) {
  2407. sde_conn->ops.cont_splash_res_disable
  2408. (sde_conn->display);
  2409. } else if (connector->encoder_ids[0]
  2410. == encoder->base.id) {
  2411. /**
  2412. * This handles dual DSI
  2413. * configuration where one DSI
  2414. * interface has cont_splash
  2415. * enabled and the other doesn't.
  2416. */
  2417. sde_conn->ops.cont_splash_res_disable
  2418. (sde_conn->display);
  2419. break;
  2420. }
  2421. }
  2422. }
  2423. drm_connector_list_iter_end(&conn_iter);
  2424. return 0;
  2425. }
  2426. static int sde_kms_cont_splash_config(struct msm_kms *kms)
  2427. {
  2428. void *display;
  2429. struct dsi_display *dsi_display;
  2430. struct msm_display_info info;
  2431. struct drm_encoder *encoder = NULL;
  2432. struct drm_crtc *crtc = NULL;
  2433. int i, rc = 0;
  2434. struct drm_display_mode *drm_mode = NULL;
  2435. struct drm_device *dev;
  2436. struct msm_drm_private *priv;
  2437. struct sde_kms *sde_kms;
  2438. struct drm_connector_list_iter conn_iter;
  2439. struct drm_connector *connector = NULL;
  2440. struct sde_connector *sde_conn = NULL;
  2441. struct sde_splash_display *splash_display;
  2442. if (!kms) {
  2443. SDE_ERROR("invalid kms\n");
  2444. return -EINVAL;
  2445. }
  2446. sde_kms = to_sde_kms(kms);
  2447. dev = sde_kms->dev;
  2448. if (!dev) {
  2449. SDE_ERROR("invalid device\n");
  2450. return -EINVAL;
  2451. }
  2452. if (((sde_kms->splash_data.type == SDE_SPLASH_HANDOFF)
  2453. && (!sde_kms->splash_data.num_splash_regions)) ||
  2454. !sde_kms->splash_data.num_splash_displays) {
  2455. DRM_INFO("cont_splash feature not enabled\n");
  2456. sde_kms_inform_cont_splash_res_disable(kms, NULL);
  2457. return rc;
  2458. }
  2459. DRM_INFO("cont_splash enabled in %d of %d display(s)\n",
  2460. sde_kms->splash_data.num_splash_displays,
  2461. sde_kms->dsi_display_count);
  2462. /* dsi */
  2463. for (i = 0; i < sde_kms->dsi_display_count; ++i) {
  2464. display = sde_kms->dsi_displays[i];
  2465. dsi_display = (struct dsi_display *)display;
  2466. splash_display = &sde_kms->splash_data.splash_display[i];
  2467. if (!splash_display->cont_splash_enabled) {
  2468. SDE_DEBUG("display->name = %s splash not enabled\n",
  2469. dsi_display->name);
  2470. sde_kms_inform_cont_splash_res_disable(kms,
  2471. dsi_display);
  2472. continue;
  2473. }
  2474. SDE_DEBUG("display->name = %s\n", dsi_display->name);
  2475. if (dsi_display->bridge->base.encoder) {
  2476. encoder = dsi_display->bridge->base.encoder;
  2477. SDE_DEBUG("encoder name = %s\n", encoder->name);
  2478. }
  2479. memset(&info, 0x0, sizeof(info));
  2480. rc = dsi_display_get_info(NULL, &info, display);
  2481. if (rc) {
  2482. SDE_ERROR("dsi get_info %d failed\n", i);
  2483. encoder = NULL;
  2484. continue;
  2485. }
  2486. SDE_DEBUG("info.is_connected = %s, info.display_type = %d\n",
  2487. ((info.is_connected) ? "true" : "false"),
  2488. info.display_type);
  2489. if (!encoder) {
  2490. SDE_ERROR("encoder not initialized\n");
  2491. return -EINVAL;
  2492. }
  2493. priv = sde_kms->dev->dev_private;
  2494. encoder->crtc = priv->crtcs[i];
  2495. crtc = encoder->crtc;
  2496. splash_display->encoder = encoder;
  2497. SDE_DEBUG("for dsi-display:%d crtc id = %d enc id =%d\n",
  2498. i, crtc->base.id, encoder->base.id);
  2499. mutex_lock(&dev->mode_config.mutex);
  2500. drm_connector_list_iter_begin(dev, &conn_iter);
  2501. drm_for_each_connector_iter(connector, &conn_iter) {
  2502. /**
  2503. * SDE_KMS doesn't attach more than one encoder to
  2504. * a DSI connector. So it is safe to check only with
  2505. * the first encoder entry. Revisit this logic if we
  2506. * ever have to support continuous splash for
  2507. * external displays in MST configuration.
  2508. */
  2509. if (connector->encoder_ids[0] == encoder->base.id)
  2510. break;
  2511. }
  2512. drm_connector_list_iter_end(&conn_iter);
  2513. if (!connector) {
  2514. SDE_ERROR("connector not initialized\n");
  2515. mutex_unlock(&dev->mode_config.mutex);
  2516. return -EINVAL;
  2517. }
  2518. if (connector->funcs->fill_modes) {
  2519. connector->funcs->fill_modes(connector,
  2520. dev->mode_config.max_width,
  2521. dev->mode_config.max_height);
  2522. } else {
  2523. SDE_ERROR("fill_modes api not defined\n");
  2524. mutex_unlock(&dev->mode_config.mutex);
  2525. return -EINVAL;
  2526. }
  2527. mutex_unlock(&dev->mode_config.mutex);
  2528. crtc->state->encoder_mask = (1 << drm_encoder_index(encoder));
  2529. drm_mode = _sde_kms_get_splash_mode(sde_kms, connector, i);
  2530. if (!drm_mode) {
  2531. SDE_ERROR("invalid drm-mode type:%d, index:%d\n",
  2532. sde_kms->splash_data.type, i);
  2533. return -EINVAL;
  2534. }
  2535. SDE_DEBUG("drm_mode->name = %s, type=0x%x, flags=0x%x\n",
  2536. drm_mode->name, drm_mode->type,
  2537. drm_mode->flags);
  2538. /* Update CRTC drm structure */
  2539. crtc->state->active = true;
  2540. rc = drm_atomic_set_mode_for_crtc(crtc->state, drm_mode);
  2541. if (rc) {
  2542. SDE_ERROR("Failed: set mode for crtc. rc = %d\n", rc);
  2543. return rc;
  2544. }
  2545. drm_mode_copy(&crtc->state->adjusted_mode, drm_mode);
  2546. drm_mode_copy(&crtc->mode, drm_mode);
  2547. /* Update encoder structure */
  2548. sde_encoder_update_caps_for_cont_splash(encoder,
  2549. splash_display, true);
  2550. sde_crtc_update_cont_splash_settings(crtc);
  2551. sde_conn = to_sde_connector(connector);
  2552. if (sde_conn && sde_conn->ops.cont_splash_config)
  2553. sde_conn->ops.cont_splash_config(sde_conn->display);
  2554. rc = _sde_kms_update_planes_for_cont_splash(sde_kms,
  2555. splash_display, crtc);
  2556. if (rc) {
  2557. SDE_ERROR("Failed: updating plane status rc=%d\n", rc);
  2558. return rc;
  2559. }
  2560. }
  2561. return rc;
  2562. }
  2563. static bool sde_kms_check_for_splash(struct msm_kms *kms)
  2564. {
  2565. struct sde_kms *sde_kms;
  2566. if (!kms) {
  2567. SDE_ERROR("invalid kms\n");
  2568. return false;
  2569. }
  2570. sde_kms = to_sde_kms(kms);
  2571. return sde_kms->splash_data.num_splash_displays;
  2572. }
  2573. static int sde_kms_get_mixer_count(const struct msm_kms *kms,
  2574. const struct drm_display_mode *mode,
  2575. const struct msm_resource_caps_info *res, u32 *num_lm)
  2576. {
  2577. struct sde_kms *sde_kms;
  2578. s64 mode_clock_hz = 0;
  2579. s64 max_mdp_clock_hz = 0;
  2580. s64 max_lm_width = 0;
  2581. s64 hdisplay_fp = 0;
  2582. s64 htotal_fp = 0;
  2583. s64 vtotal_fp = 0;
  2584. s64 vrefresh_fp = 0;
  2585. s64 mdp_fudge_factor = 0;
  2586. s64 num_lm_fp = 0;
  2587. s64 lm_clk_fp = 0;
  2588. s64 lm_width_fp = 0;
  2589. int rc = 0;
  2590. if (!num_lm) {
  2591. SDE_ERROR("invalid num_lm pointer\n");
  2592. return -EINVAL;
  2593. }
  2594. /* default to 1 layer mixer */
  2595. *num_lm = 1;
  2596. if (!kms || !mode || !res) {
  2597. SDE_ERROR("invalid input args\n");
  2598. return -EINVAL;
  2599. }
  2600. sde_kms = to_sde_kms(kms);
  2601. max_mdp_clock_hz = drm_int2fixp(sde_kms->perf.max_core_clk_rate);
  2602. max_lm_width = drm_int2fixp(res->max_mixer_width);
  2603. hdisplay_fp = drm_int2fixp(mode->hdisplay);
  2604. htotal_fp = drm_int2fixp(mode->htotal);
  2605. vtotal_fp = drm_int2fixp(mode->vtotal);
  2606. vrefresh_fp = drm_int2fixp(mode->vrefresh);
  2607. mdp_fudge_factor = drm_fixp_from_fraction(105, 100);
  2608. /* mode clock = [(h * v * fps * 1.05) / (num_lm)] */
  2609. mode_clock_hz = drm_fixp_mul(htotal_fp, vtotal_fp);
  2610. mode_clock_hz = drm_fixp_mul(mode_clock_hz, vrefresh_fp);
  2611. mode_clock_hz = drm_fixp_mul(mode_clock_hz, mdp_fudge_factor);
  2612. if (mode_clock_hz > max_mdp_clock_hz ||
  2613. hdisplay_fp > max_lm_width) {
  2614. *num_lm = 0;
  2615. do {
  2616. *num_lm += 2;
  2617. num_lm_fp = drm_int2fixp(*num_lm);
  2618. lm_clk_fp = drm_fixp_div(mode_clock_hz, num_lm_fp);
  2619. lm_width_fp = drm_fixp_div(hdisplay_fp, num_lm_fp);
  2620. if (*num_lm > 4) {
  2621. rc = -EINVAL;
  2622. goto error;
  2623. }
  2624. } while (lm_clk_fp > max_mdp_clock_hz ||
  2625. lm_width_fp > max_lm_width);
  2626. mode_clock_hz = lm_clk_fp;
  2627. }
  2628. SDE_DEBUG("[%s] h=%d v=%d fps=%d lm=%d mode_clk=%llu max_clk=%llu\n",
  2629. mode->name, mode->htotal, mode->vtotal, mode->vrefresh,
  2630. *num_lm, drm_fixp2int(mode_clock_hz),
  2631. sde_kms->perf.max_core_clk_rate);
  2632. return 0;
  2633. error:
  2634. SDE_ERROR("required mode clk exceeds max mdp clk\n");
  2635. SDE_ERROR("[%s] h=%d v=%d fps=%d lm=%d mode_clk=%llu max_clk=%llu\n",
  2636. mode->name, mode->htotal, mode->vtotal, mode->vrefresh,
  2637. *num_lm, drm_fixp2int(mode_clock_hz),
  2638. sde_kms->perf.max_core_clk_rate);
  2639. return rc;
  2640. }
  2641. static int sde_kms_get_dsc_count(const struct msm_kms *kms,
  2642. u32 hdisplay, u32 *num_dsc)
  2643. {
  2644. struct sde_kms *sde_kms;
  2645. uint32_t max_dsc_width;
  2646. if (!num_dsc) {
  2647. SDE_ERROR("invalid num_dsc pointer\n");
  2648. return -EINVAL;
  2649. }
  2650. *num_dsc = 0;
  2651. if (!kms || !hdisplay) {
  2652. SDE_ERROR("invalid input args\n");
  2653. return -EINVAL;
  2654. }
  2655. sde_kms = to_sde_kms(kms);
  2656. max_dsc_width = sde_kms->catalog->max_dsc_width;
  2657. *num_dsc = DIV_ROUND_UP(hdisplay, max_dsc_width);
  2658. SDE_DEBUG("h=%d, max_dsc_width=%d, num_dsc=%d\n",
  2659. hdisplay, max_dsc_width,
  2660. *num_dsc);
  2661. return 0;
  2662. }
  2663. static void _sde_kms_null_commit(struct drm_device *dev,
  2664. struct drm_encoder *enc)
  2665. {
  2666. struct drm_modeset_acquire_ctx ctx;
  2667. struct drm_connector *conn = NULL;
  2668. struct drm_connector *tmp_conn = NULL;
  2669. struct drm_connector_list_iter conn_iter;
  2670. struct drm_atomic_state *state = NULL;
  2671. struct drm_crtc_state *crtc_state = NULL;
  2672. struct drm_connector_state *conn_state = NULL;
  2673. int retry_cnt = 0;
  2674. int ret = 0;
  2675. drm_modeset_acquire_init(&ctx, 0);
  2676. retry:
  2677. ret = drm_modeset_lock_all_ctx(dev, &ctx);
  2678. if (ret == -EDEADLK && retry_cnt < SDE_KMS_MODESET_LOCK_MAX_TRIALS) {
  2679. drm_modeset_backoff(&ctx);
  2680. retry_cnt++;
  2681. udelay(SDE_KMS_MODESET_LOCK_TIMEOUT_US);
  2682. goto retry;
  2683. } else if (WARN_ON(ret)) {
  2684. goto end;
  2685. }
  2686. state = drm_atomic_state_alloc(dev);
  2687. if (!state) {
  2688. DRM_ERROR("failed to allocate atomic state, %d\n", ret);
  2689. goto end;
  2690. }
  2691. state->acquire_ctx = &ctx;
  2692. drm_connector_list_iter_begin(dev, &conn_iter);
  2693. drm_for_each_connector_iter(tmp_conn, &conn_iter) {
  2694. if (enc == tmp_conn->state->best_encoder) {
  2695. conn = tmp_conn;
  2696. break;
  2697. }
  2698. }
  2699. drm_connector_list_iter_end(&conn_iter);
  2700. if (!conn) {
  2701. SDE_ERROR("error in finding conn for enc:%d\n", DRMID(enc));
  2702. goto end;
  2703. }
  2704. crtc_state = drm_atomic_get_crtc_state(state, enc->crtc);
  2705. conn_state = drm_atomic_get_connector_state(state, conn);
  2706. if (IS_ERR(conn_state)) {
  2707. SDE_ERROR("error %d getting connector %d state\n",
  2708. ret, DRMID(conn));
  2709. goto end;
  2710. }
  2711. crtc_state->active = true;
  2712. ret = drm_atomic_set_crtc_for_connector(conn_state, enc->crtc);
  2713. if (ret)
  2714. SDE_ERROR("error %d setting the crtc\n", ret);
  2715. ret = drm_atomic_commit(state);
  2716. if (ret)
  2717. SDE_ERROR("Error %d doing the atomic commit\n", ret);
  2718. end:
  2719. if (state)
  2720. drm_atomic_state_put(state);
  2721. drm_modeset_drop_locks(&ctx);
  2722. drm_modeset_acquire_fini(&ctx);
  2723. }
  2724. void sde_kms_display_early_wakeup(struct drm_device *dev,
  2725. const int32_t connector_id)
  2726. {
  2727. struct drm_connector_list_iter conn_iter;
  2728. struct drm_connector *conn;
  2729. struct drm_encoder *drm_enc;
  2730. drm_connector_list_iter_begin(dev, &conn_iter);
  2731. drm_for_each_connector_iter(conn, &conn_iter) {
  2732. if (connector_id != DRM_MSM_WAKE_UP_ALL_DISPLAYS &&
  2733. connector_id != conn->base.id)
  2734. continue;
  2735. if (conn->state && conn->state->best_encoder)
  2736. drm_enc = conn->state->best_encoder;
  2737. else
  2738. drm_enc = conn->encoder;
  2739. if (drm_enc)
  2740. sde_encoder_early_wakeup(drm_enc);
  2741. }
  2742. drm_connector_list_iter_end(&conn_iter);
  2743. }
  2744. static void _sde_kms_pm_suspend_idle_helper(struct sde_kms *sde_kms,
  2745. struct device *dev)
  2746. {
  2747. int i, ret, crtc_id = 0;
  2748. struct drm_device *ddev = dev_get_drvdata(dev);
  2749. struct drm_connector *conn;
  2750. struct drm_connector_list_iter conn_iter;
  2751. struct msm_drm_private *priv = sde_kms->dev->dev_private;
  2752. drm_connector_list_iter_begin(ddev, &conn_iter);
  2753. drm_for_each_connector_iter(conn, &conn_iter) {
  2754. uint64_t lp;
  2755. lp = sde_connector_get_lp(conn);
  2756. if (lp != SDE_MODE_DPMS_LP2)
  2757. continue;
  2758. if (sde_encoder_in_clone_mode(conn->encoder))
  2759. continue;
  2760. ret = sde_encoder_wait_for_event(conn->encoder,
  2761. MSM_ENC_TX_COMPLETE);
  2762. if (ret && ret != -EWOULDBLOCK) {
  2763. SDE_ERROR(
  2764. "[conn: %d] wait for commit done returned %d\n",
  2765. conn->base.id, ret);
  2766. } else if (!ret) {
  2767. crtc_id = drm_crtc_index(conn->state->crtc);
  2768. if (priv->event_thread[crtc_id].thread)
  2769. kthread_flush_worker(
  2770. &priv->event_thread[crtc_id].worker);
  2771. sde_encoder_idle_request(conn->encoder);
  2772. }
  2773. }
  2774. drm_connector_list_iter_end(&conn_iter);
  2775. for (i = 0; i < priv->num_crtcs; i++) {
  2776. if (priv->disp_thread[i].thread)
  2777. kthread_flush_worker(
  2778. &priv->disp_thread[i].worker);
  2779. if (priv->event_thread[i].thread)
  2780. kthread_flush_worker(
  2781. &priv->event_thread[i].worker);
  2782. }
  2783. kthread_flush_worker(&priv->pp_event_worker);
  2784. }
  2785. static int sde_kms_pm_suspend(struct device *dev)
  2786. {
  2787. struct drm_device *ddev;
  2788. struct drm_modeset_acquire_ctx ctx;
  2789. struct drm_connector *conn;
  2790. struct drm_encoder *enc;
  2791. struct drm_connector_list_iter conn_iter;
  2792. struct drm_atomic_state *state = NULL;
  2793. struct sde_kms *sde_kms;
  2794. int ret = 0, num_crtcs = 0;
  2795. if (!dev)
  2796. return -EINVAL;
  2797. ddev = dev_get_drvdata(dev);
  2798. if (!ddev || !ddev_to_msm_kms(ddev))
  2799. return -EINVAL;
  2800. sde_kms = to_sde_kms(ddev_to_msm_kms(ddev));
  2801. SDE_EVT32(0);
  2802. /* disable hot-plug polling */
  2803. drm_kms_helper_poll_disable(ddev);
  2804. /* if a display stuck in CS trigger a null commit to complete handoff */
  2805. drm_for_each_encoder(enc, ddev) {
  2806. if (sde_encoder_in_cont_splash(enc) && enc->crtc)
  2807. _sde_kms_null_commit(ddev, enc);
  2808. }
  2809. /* acquire modeset lock(s) */
  2810. drm_modeset_acquire_init(&ctx, 0);
  2811. retry:
  2812. ret = drm_modeset_lock_all_ctx(ddev, &ctx);
  2813. if (ret)
  2814. goto unlock;
  2815. /* save current state for resume */
  2816. if (sde_kms->suspend_state)
  2817. drm_atomic_state_put(sde_kms->suspend_state);
  2818. sde_kms->suspend_state = drm_atomic_helper_duplicate_state(ddev, &ctx);
  2819. if (IS_ERR_OR_NULL(sde_kms->suspend_state)) {
  2820. ret = PTR_ERR(sde_kms->suspend_state);
  2821. DRM_ERROR("failed to back up suspend state, %d\n", ret);
  2822. sde_kms->suspend_state = NULL;
  2823. goto unlock;
  2824. }
  2825. /* create atomic state to disable all CRTCs */
  2826. state = drm_atomic_state_alloc(ddev);
  2827. if (!state) {
  2828. ret = -ENOMEM;
  2829. DRM_ERROR("failed to allocate crtc disable state, %d\n", ret);
  2830. goto unlock;
  2831. }
  2832. state->acquire_ctx = &ctx;
  2833. drm_connector_list_iter_begin(ddev, &conn_iter);
  2834. drm_for_each_connector_iter(conn, &conn_iter) {
  2835. struct drm_crtc_state *crtc_state;
  2836. uint64_t lp;
  2837. if (!conn->state || !conn->state->crtc ||
  2838. conn->dpms != DRM_MODE_DPMS_ON ||
  2839. sde_encoder_in_clone_mode(conn->encoder))
  2840. continue;
  2841. lp = sde_connector_get_lp(conn);
  2842. if (lp == SDE_MODE_DPMS_LP1) {
  2843. /* transition LP1->LP2 on pm suspend */
  2844. ret = sde_connector_set_property_for_commit(conn, state,
  2845. CONNECTOR_PROP_LP, SDE_MODE_DPMS_LP2);
  2846. if (ret) {
  2847. DRM_ERROR("failed to set lp2 for conn %d\n",
  2848. conn->base.id);
  2849. drm_connector_list_iter_end(&conn_iter);
  2850. goto unlock;
  2851. }
  2852. }
  2853. if (lp != SDE_MODE_DPMS_LP2) {
  2854. /* force CRTC to be inactive */
  2855. crtc_state = drm_atomic_get_crtc_state(state,
  2856. conn->state->crtc);
  2857. if (IS_ERR_OR_NULL(crtc_state)) {
  2858. DRM_ERROR("failed to get crtc %d state\n",
  2859. conn->state->crtc->base.id);
  2860. drm_connector_list_iter_end(&conn_iter);
  2861. goto unlock;
  2862. }
  2863. if (lp != SDE_MODE_DPMS_LP1)
  2864. crtc_state->active = false;
  2865. ++num_crtcs;
  2866. }
  2867. }
  2868. drm_connector_list_iter_end(&conn_iter);
  2869. /* check for nothing to do */
  2870. if (num_crtcs == 0) {
  2871. DRM_DEBUG("all crtcs are already in the off state\n");
  2872. sde_kms->suspend_block = true;
  2873. _sde_kms_pm_suspend_idle_helper(sde_kms, dev);
  2874. goto unlock;
  2875. }
  2876. /* commit the "disable all" state */
  2877. ret = drm_atomic_commit(state);
  2878. if (ret < 0) {
  2879. DRM_ERROR("failed to disable crtcs, %d\n", ret);
  2880. goto unlock;
  2881. }
  2882. sde_kms->suspend_block = true;
  2883. _sde_kms_pm_suspend_idle_helper(sde_kms, dev);
  2884. unlock:
  2885. if (state) {
  2886. drm_atomic_state_put(state);
  2887. state = NULL;
  2888. }
  2889. if (ret == -EDEADLK) {
  2890. drm_modeset_backoff(&ctx);
  2891. goto retry;
  2892. }
  2893. drm_modeset_drop_locks(&ctx);
  2894. drm_modeset_acquire_fini(&ctx);
  2895. /*
  2896. * pm runtime driver avoids multiple runtime_suspend API call by
  2897. * checking runtime_status. However, this call helps when there is a
  2898. * race condition between pm_suspend call and doze_suspend/power_off
  2899. * commit. It removes the extra vote from suspend and adds it back
  2900. * later to allow power collapse during pm_suspend call
  2901. */
  2902. pm_runtime_put_sync(dev);
  2903. pm_runtime_get_noresume(dev);
  2904. /* dump clock state before entering suspend */
  2905. if (sde_kms->pm_suspend_clk_dump)
  2906. _sde_kms_dump_clks_state(sde_kms);
  2907. return ret;
  2908. }
  2909. static int sde_kms_pm_resume(struct device *dev)
  2910. {
  2911. struct drm_device *ddev;
  2912. struct sde_kms *sde_kms;
  2913. struct drm_modeset_acquire_ctx ctx;
  2914. int ret, i;
  2915. if (!dev)
  2916. return -EINVAL;
  2917. ddev = dev_get_drvdata(dev);
  2918. if (!ddev || !ddev_to_msm_kms(ddev))
  2919. return -EINVAL;
  2920. sde_kms = to_sde_kms(ddev_to_msm_kms(ddev));
  2921. SDE_EVT32(sde_kms->suspend_state != NULL);
  2922. drm_mode_config_reset(ddev);
  2923. drm_modeset_acquire_init(&ctx, 0);
  2924. retry:
  2925. ret = drm_modeset_lock_all_ctx(ddev, &ctx);
  2926. if (ret == -EDEADLK) {
  2927. drm_modeset_backoff(&ctx);
  2928. goto retry;
  2929. } else if (WARN_ON(ret)) {
  2930. goto end;
  2931. }
  2932. sde_kms->suspend_block = false;
  2933. if (sde_kms->suspend_state) {
  2934. sde_kms->suspend_state->acquire_ctx = &ctx;
  2935. for (i = 0; i < TEARDOWN_DEADLOCK_RETRY_MAX; i++) {
  2936. ret = drm_atomic_helper_commit_duplicated_state(
  2937. sde_kms->suspend_state, &ctx);
  2938. if (ret != -EDEADLK)
  2939. break;
  2940. drm_modeset_backoff(&ctx);
  2941. }
  2942. if (ret < 0)
  2943. DRM_ERROR("failed to restore state, %d\n", ret);
  2944. drm_atomic_state_put(sde_kms->suspend_state);
  2945. sde_kms->suspend_state = NULL;
  2946. }
  2947. end:
  2948. drm_modeset_drop_locks(&ctx);
  2949. drm_modeset_acquire_fini(&ctx);
  2950. /* enable hot-plug polling */
  2951. drm_kms_helper_poll_enable(ddev);
  2952. return 0;
  2953. }
  2954. static const struct msm_kms_funcs kms_funcs = {
  2955. .hw_init = sde_kms_hw_init,
  2956. .postinit = sde_kms_postinit,
  2957. .irq_preinstall = sde_irq_preinstall,
  2958. .irq_postinstall = sde_irq_postinstall,
  2959. .irq_uninstall = sde_irq_uninstall,
  2960. .irq = sde_irq,
  2961. .lastclose = sde_kms_lastclose,
  2962. .prepare_fence = sde_kms_prepare_fence,
  2963. .prepare_commit = sde_kms_prepare_commit,
  2964. .commit = sde_kms_commit,
  2965. .complete_commit = sde_kms_complete_commit,
  2966. .wait_for_crtc_commit_done = sde_kms_wait_for_commit_done,
  2967. .wait_for_tx_complete = sde_kms_wait_for_frame_transfer_complete,
  2968. .enable_vblank = sde_kms_enable_vblank,
  2969. .disable_vblank = sde_kms_disable_vblank,
  2970. .check_modified_format = sde_format_check_modified_format,
  2971. .atomic_check = sde_kms_atomic_check,
  2972. .get_format = sde_get_msm_format,
  2973. .round_pixclk = sde_kms_round_pixclk,
  2974. .display_early_wakeup = sde_kms_display_early_wakeup,
  2975. .pm_suspend = sde_kms_pm_suspend,
  2976. .pm_resume = sde_kms_pm_resume,
  2977. .destroy = sde_kms_destroy,
  2978. .debugfs_destroy = sde_kms_debugfs_destroy,
  2979. .cont_splash_config = sde_kms_cont_splash_config,
  2980. .register_events = _sde_kms_register_events,
  2981. .get_address_space = _sde_kms_get_address_space,
  2982. .get_address_space_device = _sde_kms_get_address_space_device,
  2983. .postopen = _sde_kms_post_open,
  2984. .check_for_splash = sde_kms_check_for_splash,
  2985. .get_mixer_count = sde_kms_get_mixer_count,
  2986. .get_dsc_count = sde_kms_get_dsc_count,
  2987. };
  2988. static int _sde_kms_mmu_destroy(struct sde_kms *sde_kms)
  2989. {
  2990. int i;
  2991. for (i = ARRAY_SIZE(sde_kms->aspace) - 1; i >= 0; i--) {
  2992. if (!sde_kms->aspace[i])
  2993. continue;
  2994. msm_gem_address_space_put(sde_kms->aspace[i]);
  2995. sde_kms->aspace[i] = NULL;
  2996. }
  2997. return 0;
  2998. }
  2999. static int _sde_kms_mmu_init(struct sde_kms *sde_kms)
  3000. {
  3001. struct msm_mmu *mmu;
  3002. int i, ret;
  3003. int early_map = 0;
  3004. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev)
  3005. return -EINVAL;
  3006. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  3007. struct msm_gem_address_space *aspace;
  3008. mmu = msm_smmu_new(sde_kms->dev->dev, i);
  3009. if (IS_ERR(mmu)) {
  3010. ret = PTR_ERR(mmu);
  3011. SDE_DEBUG("failed to init iommu id %d: rc:%d\n",
  3012. i, ret);
  3013. continue;
  3014. }
  3015. aspace = msm_gem_smmu_address_space_create(sde_kms->dev,
  3016. mmu, "sde");
  3017. if (IS_ERR(aspace)) {
  3018. ret = PTR_ERR(aspace);
  3019. mmu->funcs->destroy(mmu);
  3020. goto fail;
  3021. }
  3022. sde_kms->aspace[i] = aspace;
  3023. aspace->domain_attached = true;
  3024. /* Mapping splash memory block */
  3025. if ((i == MSM_SMMU_DOMAIN_UNSECURE) &&
  3026. sde_kms->splash_data.num_splash_regions) {
  3027. ret = _sde_kms_map_all_splash_regions(sde_kms);
  3028. if (ret) {
  3029. SDE_ERROR("failed to map ret:%d\n", ret);
  3030. goto fail;
  3031. }
  3032. }
  3033. /*
  3034. * disable early-map which would have been enabled during
  3035. * bootup by smmu through the device-tree hint for cont-spash
  3036. */
  3037. ret = mmu->funcs->set_attribute(mmu, DOMAIN_ATTR_EARLY_MAP,
  3038. &early_map);
  3039. if (ret) {
  3040. SDE_ERROR("failed to set_att ret:%d, early_map:%d\n",
  3041. ret, early_map);
  3042. goto early_map_fail;
  3043. }
  3044. }
  3045. sde_kms->base.aspace = sde_kms->aspace[0];
  3046. return 0;
  3047. early_map_fail:
  3048. _sde_kms_unmap_all_splash_regions(sde_kms);
  3049. fail:
  3050. _sde_kms_mmu_destroy(sde_kms);
  3051. return ret;
  3052. }
  3053. static void sde_kms_init_rot_sid_hw(struct sde_kms *sde_kms)
  3054. {
  3055. if (!sde_kms || !sde_kms->hw_sid || sde_in_trusted_vm(sde_kms))
  3056. return;
  3057. sde_hw_set_rotator_sid(sde_kms->hw_sid);
  3058. }
  3059. static void sde_kms_init_shared_hw(struct sde_kms *sde_kms)
  3060. {
  3061. if (!sde_kms || !sde_kms->hw_mdp || !sde_kms->catalog)
  3062. return;
  3063. if (sde_kms->hw_mdp->ops.reset_ubwc)
  3064. sde_kms->hw_mdp->ops.reset_ubwc(sde_kms->hw_mdp,
  3065. sde_kms->catalog);
  3066. }
  3067. static void _sde_kms_set_lutdma_vbif_remap(struct sde_kms *sde_kms)
  3068. {
  3069. struct sde_vbif_set_qos_params qos_params;
  3070. struct sde_mdss_cfg *catalog;
  3071. if (!sde_kms->catalog)
  3072. return;
  3073. catalog = sde_kms->catalog;
  3074. memset(&qos_params, 0, sizeof(qos_params));
  3075. qos_params.vbif_idx = catalog->dma_cfg.vbif_idx;
  3076. qos_params.xin_id = catalog->dma_cfg.xin_id;
  3077. qos_params.clk_ctrl = catalog->dma_cfg.clk_ctrl;
  3078. qos_params.client_type = VBIF_LUTDMA_CLIENT;
  3079. sde_vbif_set_qos_remap(sde_kms, &qos_params);
  3080. }
  3081. static int _sde_kms_active_override(struct sde_kms *sde_kms, bool enable)
  3082. {
  3083. struct sde_hw_uidle *uidle;
  3084. if (!sde_kms) {
  3085. SDE_ERROR("invalid kms\n");
  3086. return -EINVAL;
  3087. }
  3088. uidle = sde_kms->hw_uidle;
  3089. if (uidle && uidle->ops.active_override_enable)
  3090. uidle->ops.active_override_enable(uidle, enable);
  3091. return 0;
  3092. }
  3093. static void _sde_kms_update_pm_qos_irq_request(struct sde_kms *sde_kms)
  3094. {
  3095. struct device *cpu_dev;
  3096. int cpu = 0;
  3097. u32 cpu_irq_latency = sde_kms->catalog->perf.cpu_irq_latency;
  3098. if (cpumask_empty(&sde_kms->irq_cpu_mask)) {
  3099. SDE_DEBUG("%s: irq_cpu_mask is empty\n", __func__);
  3100. return;
  3101. }
  3102. for_each_cpu(cpu, &sde_kms->irq_cpu_mask) {
  3103. cpu_dev = get_cpu_device(cpu);
  3104. if (!cpu_dev) {
  3105. SDE_DEBUG("%s: failed to get cpu%d device\n", __func__,
  3106. cpu);
  3107. continue;
  3108. }
  3109. if (dev_pm_qos_request_active(&sde_kms->pm_qos_irq_req[cpu]))
  3110. dev_pm_qos_update_request(&sde_kms->pm_qos_irq_req[cpu],
  3111. cpu_irq_latency);
  3112. else
  3113. dev_pm_qos_add_request(cpu_dev,
  3114. &sde_kms->pm_qos_irq_req[cpu],
  3115. DEV_PM_QOS_RESUME_LATENCY,
  3116. cpu_irq_latency);
  3117. }
  3118. }
  3119. static void _sde_kms_remove_pm_qos_irq_request(struct sde_kms *sde_kms)
  3120. {
  3121. struct device *cpu_dev;
  3122. int cpu = 0;
  3123. if (cpumask_empty(&sde_kms->irq_cpu_mask)) {
  3124. SDE_DEBUG("%s: irq_cpu_mask is empty\n", __func__);
  3125. return;
  3126. }
  3127. for_each_cpu(cpu, &sde_kms->irq_cpu_mask) {
  3128. cpu_dev = get_cpu_device(cpu);
  3129. if (!cpu_dev) {
  3130. SDE_DEBUG("%s: failed to get cpu%d device\n", __func__,
  3131. cpu);
  3132. continue;
  3133. }
  3134. if (dev_pm_qos_request_active(&sde_kms->pm_qos_irq_req[cpu]))
  3135. dev_pm_qos_remove_request(
  3136. &sde_kms->pm_qos_irq_req[cpu]);
  3137. }
  3138. }
  3139. void sde_kms_cpu_vote_for_irq(struct sde_kms *sde_kms, bool enable)
  3140. {
  3141. struct msm_drm_private *priv = sde_kms->dev->dev_private;
  3142. mutex_lock(&priv->phandle.phandle_lock);
  3143. if (enable && atomic_inc_return(&sde_kms->irq_vote_count) == 1)
  3144. _sde_kms_update_pm_qos_irq_request(sde_kms);
  3145. else if (!enable && atomic_dec_return(&sde_kms->irq_vote_count) == 0)
  3146. _sde_kms_remove_pm_qos_irq_request(sde_kms);
  3147. mutex_unlock(&priv->phandle.phandle_lock);
  3148. }
  3149. static void sde_kms_irq_affinity_notify(
  3150. struct irq_affinity_notify *affinity_notify,
  3151. const cpumask_t *mask)
  3152. {
  3153. struct msm_drm_private *priv;
  3154. struct sde_kms *sde_kms = container_of(affinity_notify,
  3155. struct sde_kms, affinity_notify);
  3156. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private)
  3157. return;
  3158. priv = sde_kms->dev->dev_private;
  3159. mutex_lock(&priv->phandle.phandle_lock);
  3160. // save irq cpu mask
  3161. sde_kms->irq_cpu_mask = *mask;
  3162. // request vote with updated irq cpu mask
  3163. if (atomic_read(&sde_kms->irq_vote_count))
  3164. _sde_kms_update_pm_qos_irq_request(sde_kms);
  3165. mutex_unlock(&priv->phandle.phandle_lock);
  3166. }
  3167. static void sde_kms_irq_affinity_release(struct kref *ref) {}
  3168. static void sde_kms_handle_power_event(u32 event_type, void *usr)
  3169. {
  3170. struct sde_kms *sde_kms = usr;
  3171. struct msm_kms *msm_kms;
  3172. msm_kms = &sde_kms->base;
  3173. if (!sde_kms)
  3174. return;
  3175. SDE_DEBUG("event_type:%d\n", event_type);
  3176. SDE_EVT32_VERBOSE(event_type);
  3177. if (event_type == SDE_POWER_EVENT_POST_ENABLE) {
  3178. sde_irq_update(msm_kms, true);
  3179. sde_kms->first_kickoff = true;
  3180. /**
  3181. * Rotator sid needs to be programmed since uefi doesn't
  3182. * configure it during continuous splash
  3183. */
  3184. sde_kms_init_rot_sid_hw(sde_kms);
  3185. if (sde_kms->splash_data.num_splash_displays ||
  3186. sde_in_trusted_vm(sde_kms))
  3187. return;
  3188. sde_vbif_init_memtypes(sde_kms);
  3189. sde_kms_init_shared_hw(sde_kms);
  3190. _sde_kms_set_lutdma_vbif_remap(sde_kms);
  3191. } else if (event_type == SDE_POWER_EVENT_PRE_DISABLE) {
  3192. sde_irq_update(msm_kms, false);
  3193. sde_kms->first_kickoff = false;
  3194. if (sde_in_trusted_vm(sde_kms))
  3195. return;
  3196. _sde_kms_active_override(sde_kms, true);
  3197. if (!is_sde_rsc_available(SDE_RSC_INDEX))
  3198. sde_vbif_axi_halt_request(sde_kms);
  3199. }
  3200. }
  3201. #define genpd_to_sde_kms(domain) container_of(domain, struct sde_kms, genpd)
  3202. static int sde_kms_pd_enable(struct generic_pm_domain *genpd)
  3203. {
  3204. struct sde_kms *sde_kms = genpd_to_sde_kms(genpd);
  3205. int rc = -EINVAL;
  3206. SDE_DEBUG("\n");
  3207. rc = pm_runtime_get_sync(sde_kms->dev->dev);
  3208. if (rc > 0)
  3209. rc = 0;
  3210. SDE_EVT32(rc, genpd->device_count);
  3211. return rc;
  3212. }
  3213. static int sde_kms_pd_disable(struct generic_pm_domain *genpd)
  3214. {
  3215. struct sde_kms *sde_kms = genpd_to_sde_kms(genpd);
  3216. SDE_DEBUG("\n");
  3217. pm_runtime_put_sync(sde_kms->dev->dev);
  3218. SDE_EVT32(genpd->device_count);
  3219. return 0;
  3220. }
  3221. static int _sde_kms_get_splash_data(struct sde_kms *sde_kms,
  3222. struct sde_splash_data *data)
  3223. {
  3224. int i = 0;
  3225. int ret = 0;
  3226. struct device_node *parent, *node, *node1;
  3227. struct resource r, r1;
  3228. const char *node_name = "splash_region";
  3229. struct sde_splash_mem *mem;
  3230. bool share_splash_mem = false;
  3231. int num_displays, num_regions;
  3232. struct sde_splash_display *splash_display;
  3233. if (!data)
  3234. return -EINVAL;
  3235. memset(data, 0, sizeof(*data));
  3236. parent = of_find_node_by_path("/reserved-memory");
  3237. if (!parent) {
  3238. SDE_ERROR("failed to find reserved-memory node\n");
  3239. return -EINVAL;
  3240. }
  3241. node = of_find_node_by_name(parent, node_name);
  3242. if (!node) {
  3243. SDE_DEBUG("failed to find node %s\n", node_name);
  3244. return -EINVAL;
  3245. }
  3246. node1 = of_find_node_by_name(NULL, "disp_rdump_region");
  3247. if (!node1)
  3248. SDE_DEBUG("failed to find disp ramdump memory reservation\n");
  3249. /**
  3250. * Support sharing a single splash memory for all the built in displays
  3251. * and also independent splash region per displays. Incase of
  3252. * independent splash region for each connected display, dtsi node of
  3253. * cont_splash_region should be collection of all memory regions
  3254. * Ex: <r1.start r1.end r2.start r2.end ... rn.start, rn.end>
  3255. */
  3256. num_displays = dsi_display_get_num_of_displays();
  3257. num_regions = of_property_count_u64_elems(node, "reg") / 2;
  3258. data->num_splash_displays = num_displays;
  3259. SDE_DEBUG("splash mem num_regions:%d\n", num_regions);
  3260. if (num_displays > num_regions) {
  3261. share_splash_mem = true;
  3262. pr_info(":%d displays share same splash buf\n", num_displays);
  3263. }
  3264. for (i = 0; i < num_displays; i++) {
  3265. splash_display = &data->splash_display[i];
  3266. if (!i || !share_splash_mem) {
  3267. if (of_address_to_resource(node, i, &r)) {
  3268. SDE_ERROR("invalid data for:%s\n", node_name);
  3269. return -EINVAL;
  3270. }
  3271. mem = &data->splash_mem[i];
  3272. if (!node1 || of_address_to_resource(node1, i, &r1)) {
  3273. SDE_DEBUG("failed to find ramdump memory\n");
  3274. mem->ramdump_base = 0;
  3275. mem->ramdump_size = 0;
  3276. } else {
  3277. mem->ramdump_base = (unsigned long)r1.start;
  3278. mem->ramdump_size = (r1.end - r1.start) + 1;
  3279. }
  3280. mem->splash_buf_base = (unsigned long)r.start;
  3281. mem->splash_buf_size = (r.end - r.start) + 1;
  3282. mem->ref_cnt = 0;
  3283. splash_display->splash = mem;
  3284. data->num_splash_regions++;
  3285. } else {
  3286. data->splash_display[i].splash = &data->splash_mem[0];
  3287. }
  3288. SDE_DEBUG("splash mem for disp:%d add:%lx size:%x\n", (i + 1),
  3289. splash_display->splash->splash_buf_base,
  3290. splash_display->splash->splash_buf_size);
  3291. }
  3292. sde_kms->splash_data.type = SDE_SPLASH_HANDOFF;
  3293. return ret;
  3294. }
  3295. static int _sde_kms_hw_init_ioremap(struct sde_kms *sde_kms,
  3296. struct platform_device *platformdev)
  3297. {
  3298. int rc = -EINVAL;
  3299. sde_kms->mmio = msm_ioremap(platformdev, "mdp_phys", "mdp_phys");
  3300. if (IS_ERR(sde_kms->mmio)) {
  3301. rc = PTR_ERR(sde_kms->mmio);
  3302. SDE_ERROR("mdp register memory map failed: %d\n", rc);
  3303. sde_kms->mmio = NULL;
  3304. goto error;
  3305. }
  3306. DRM_INFO("mapped mdp address space @%pK\n", sde_kms->mmio);
  3307. sde_kms->mmio_len = msm_iomap_size(platformdev, "mdp_phys");
  3308. rc = sde_dbg_reg_register_base(SDE_DBG_NAME, sde_kms->mmio,
  3309. sde_kms->mmio_len);
  3310. if (rc)
  3311. SDE_ERROR("dbg base register kms failed: %d\n", rc);
  3312. sde_kms->vbif[VBIF_RT] = msm_ioremap(platformdev, "vbif_phys",
  3313. "vbif_phys");
  3314. if (IS_ERR(sde_kms->vbif[VBIF_RT])) {
  3315. rc = PTR_ERR(sde_kms->vbif[VBIF_RT]);
  3316. SDE_ERROR("vbif register memory map failed: %d\n", rc);
  3317. sde_kms->vbif[VBIF_RT] = NULL;
  3318. goto error;
  3319. }
  3320. sde_kms->vbif_len[VBIF_RT] = msm_iomap_size(platformdev,
  3321. "vbif_phys");
  3322. rc = sde_dbg_reg_register_base("vbif_rt", sde_kms->vbif[VBIF_RT],
  3323. sde_kms->vbif_len[VBIF_RT]);
  3324. if (rc)
  3325. SDE_ERROR("dbg base register vbif_rt failed: %d\n", rc);
  3326. sde_kms->vbif[VBIF_NRT] = msm_ioremap(platformdev, "vbif_nrt_phys",
  3327. "vbif_nrt_phys");
  3328. if (IS_ERR(sde_kms->vbif[VBIF_NRT])) {
  3329. sde_kms->vbif[VBIF_NRT] = NULL;
  3330. SDE_DEBUG("VBIF NRT is not defined");
  3331. } else {
  3332. sde_kms->vbif_len[VBIF_NRT] = msm_iomap_size(platformdev,
  3333. "vbif_nrt_phys");
  3334. rc = sde_dbg_reg_register_base("vbif_nrt",
  3335. sde_kms->vbif[VBIF_NRT],
  3336. sde_kms->vbif_len[VBIF_NRT]);
  3337. if (rc)
  3338. SDE_ERROR("dbg base register vbif_nrt failed: %d\n",
  3339. rc);
  3340. }
  3341. sde_kms->reg_dma = msm_ioremap(platformdev, "regdma_phys",
  3342. "regdma_phys");
  3343. if (IS_ERR(sde_kms->reg_dma)) {
  3344. sde_kms->reg_dma = NULL;
  3345. SDE_DEBUG("REG_DMA is not defined");
  3346. } else {
  3347. sde_kms->reg_dma_len = msm_iomap_size(platformdev,
  3348. "regdma_phys");
  3349. rc = sde_dbg_reg_register_base("reg_dma",
  3350. sde_kms->reg_dma,
  3351. sde_kms->reg_dma_len);
  3352. if (rc)
  3353. SDE_ERROR("dbg base register reg_dma failed: %d\n",
  3354. rc);
  3355. }
  3356. sde_kms->sid = msm_ioremap(platformdev, "sid_phys",
  3357. "sid_phys");
  3358. if (IS_ERR(sde_kms->sid)) {
  3359. SDE_DEBUG("sid register is not defined: %d\n", rc);
  3360. sde_kms->sid = NULL;
  3361. } else {
  3362. sde_kms->sid_len = msm_iomap_size(platformdev, "sid_phys");
  3363. rc = sde_dbg_reg_register_base("sid", sde_kms->sid,
  3364. sde_kms->sid_len);
  3365. if (rc)
  3366. SDE_ERROR("dbg base register sid failed: %d\n", rc);
  3367. }
  3368. error:
  3369. return rc;
  3370. }
  3371. static int _sde_kms_hw_init_power_helper(struct drm_device *dev,
  3372. struct sde_kms *sde_kms)
  3373. {
  3374. int rc = 0;
  3375. if (of_find_property(dev->dev->of_node, "#power-domain-cells", NULL)) {
  3376. sde_kms->genpd.name = dev->unique;
  3377. sde_kms->genpd.power_off = sde_kms_pd_disable;
  3378. sde_kms->genpd.power_on = sde_kms_pd_enable;
  3379. rc = pm_genpd_init(&sde_kms->genpd, NULL, true);
  3380. if (rc < 0) {
  3381. SDE_ERROR("failed to init genpd provider %s: %d\n",
  3382. sde_kms->genpd.name, rc);
  3383. return rc;
  3384. }
  3385. rc = of_genpd_add_provider_simple(dev->dev->of_node,
  3386. &sde_kms->genpd);
  3387. if (rc < 0) {
  3388. SDE_ERROR("failed to add genpd provider %s: %d\n",
  3389. sde_kms->genpd.name, rc);
  3390. pm_genpd_remove(&sde_kms->genpd);
  3391. return rc;
  3392. }
  3393. sde_kms->genpd_init = true;
  3394. SDE_DEBUG("added genpd provider %s\n", sde_kms->genpd.name);
  3395. }
  3396. return rc;
  3397. }
  3398. static int _sde_kms_hw_init_blocks(struct sde_kms *sde_kms,
  3399. struct drm_device *dev,
  3400. struct msm_drm_private *priv)
  3401. {
  3402. struct sde_rm *rm = NULL;
  3403. int i, rc = -EINVAL;
  3404. sde_kms->catalog = sde_hw_catalog_init(dev);
  3405. if (IS_ERR_OR_NULL(sde_kms->catalog)) {
  3406. rc = PTR_ERR(sde_kms->catalog);
  3407. if (!sde_kms->catalog)
  3408. rc = -EINVAL;
  3409. SDE_ERROR("catalog init failed: %d\n", rc);
  3410. sde_kms->catalog = NULL;
  3411. goto power_error;
  3412. }
  3413. sde_kms->core_rev = sde_kms->catalog->hwversion;
  3414. pr_info("sde hardware revision:0x%x\n", sde_kms->core_rev);
  3415. /* initialize power domain if defined */
  3416. rc = _sde_kms_hw_init_power_helper(dev, sde_kms);
  3417. if (rc) {
  3418. SDE_ERROR("_sde_kms_hw_init_power_helper failed: %d\n", rc);
  3419. goto genpd_err;
  3420. }
  3421. rc = _sde_kms_mmu_init(sde_kms);
  3422. if (rc) {
  3423. SDE_ERROR("sde_kms_mmu_init failed: %d\n", rc);
  3424. goto power_error;
  3425. }
  3426. /* Initialize reg dma block which is a singleton */
  3427. rc = sde_reg_dma_init(sde_kms->reg_dma, sde_kms->catalog,
  3428. sde_kms->dev);
  3429. if (rc) {
  3430. SDE_ERROR("failed: reg dma init failed\n");
  3431. goto power_error;
  3432. }
  3433. sde_dbg_init_dbg_buses(sde_kms->core_rev);
  3434. rm = &sde_kms->rm;
  3435. rc = sde_rm_init(rm, sde_kms->catalog, sde_kms->mmio,
  3436. sde_kms->dev);
  3437. if (rc) {
  3438. SDE_ERROR("rm init failed: %d\n", rc);
  3439. goto power_error;
  3440. }
  3441. sde_kms->rm_init = true;
  3442. sde_kms->hw_intr = sde_hw_intr_init(sde_kms->mmio, sde_kms->catalog);
  3443. if (IS_ERR_OR_NULL(sde_kms->hw_intr)) {
  3444. rc = PTR_ERR(sde_kms->hw_intr);
  3445. SDE_ERROR("hw_intr init failed: %d\n", rc);
  3446. sde_kms->hw_intr = NULL;
  3447. goto hw_intr_init_err;
  3448. }
  3449. /*
  3450. * Attempt continuous splash handoff only if reserved
  3451. * splash memory is found & release resources on any error
  3452. * in finding display hw config in splash
  3453. */
  3454. if (sde_kms->splash_data.num_splash_regions) {
  3455. struct sde_splash_display *display;
  3456. int ret, display_count =
  3457. sde_kms->splash_data.num_splash_displays;
  3458. ret = sde_rm_cont_splash_res_init(priv, &sde_kms->rm,
  3459. &sde_kms->splash_data, sde_kms->catalog);
  3460. for (i = 0; i < display_count; i++) {
  3461. display = &sde_kms->splash_data.splash_display[i];
  3462. /*
  3463. * free splash region on resource init failure and
  3464. * cont-splash disabled case
  3465. */
  3466. if (!display->cont_splash_enabled || ret)
  3467. _sde_kms_free_splash_display_data(
  3468. sde_kms, display);
  3469. }
  3470. }
  3471. sde_kms->hw_mdp = sde_rm_get_mdp(&sde_kms->rm);
  3472. if (IS_ERR_OR_NULL(sde_kms->hw_mdp)) {
  3473. rc = PTR_ERR(sde_kms->hw_mdp);
  3474. if (!sde_kms->hw_mdp)
  3475. rc = -EINVAL;
  3476. SDE_ERROR("failed to get hw_mdp: %d\n", rc);
  3477. sde_kms->hw_mdp = NULL;
  3478. goto power_error;
  3479. }
  3480. for (i = 0; i < sde_kms->catalog->vbif_count; i++) {
  3481. u32 vbif_idx = sde_kms->catalog->vbif[i].id;
  3482. sde_kms->hw_vbif[i] = sde_hw_vbif_init(vbif_idx,
  3483. sde_kms->vbif[vbif_idx], sde_kms->catalog);
  3484. if (IS_ERR_OR_NULL(sde_kms->hw_vbif[vbif_idx])) {
  3485. rc = PTR_ERR(sde_kms->hw_vbif[vbif_idx]);
  3486. if (!sde_kms->hw_vbif[vbif_idx])
  3487. rc = -EINVAL;
  3488. SDE_ERROR("failed to init vbif %d: %d\n", vbif_idx, rc);
  3489. sde_kms->hw_vbif[vbif_idx] = NULL;
  3490. goto power_error;
  3491. }
  3492. }
  3493. if (sde_kms->catalog->uidle_cfg.uidle_rev) {
  3494. sde_kms->hw_uidle = sde_hw_uidle_init(UIDLE, sde_kms->mmio,
  3495. sde_kms->mmio_len, sde_kms->catalog);
  3496. if (IS_ERR_OR_NULL(sde_kms->hw_uidle)) {
  3497. rc = PTR_ERR(sde_kms->hw_uidle);
  3498. if (!sde_kms->hw_uidle)
  3499. rc = -EINVAL;
  3500. /* uidle is optional, so do not make it a fatal error */
  3501. SDE_ERROR("failed to init uidle rc:%d\n", rc);
  3502. sde_kms->hw_uidle = NULL;
  3503. rc = 0;
  3504. }
  3505. } else {
  3506. sde_kms->hw_uidle = NULL;
  3507. }
  3508. if (sde_kms->sid) {
  3509. sde_kms->hw_sid = sde_hw_sid_init(sde_kms->sid,
  3510. sde_kms->sid_len, sde_kms->catalog);
  3511. if (IS_ERR_OR_NULL(sde_kms->hw_sid)) {
  3512. rc = PTR_ERR(sde_kms->hw_sid);
  3513. SDE_ERROR("failed to init sid %ld\n", rc);
  3514. sde_kms->hw_sid = NULL;
  3515. goto power_error;
  3516. }
  3517. }
  3518. rc = sde_core_perf_init(&sde_kms->perf, dev, sde_kms->catalog,
  3519. &priv->phandle, "core_clk");
  3520. if (rc) {
  3521. SDE_ERROR("failed to init perf %d\n", rc);
  3522. goto perf_err;
  3523. }
  3524. /*
  3525. * _sde_kms_drm_obj_init should create the DRM related objects
  3526. * i.e. CRTCs, planes, encoders, connectors and so forth
  3527. */
  3528. rc = _sde_kms_drm_obj_init(sde_kms);
  3529. if (rc) {
  3530. SDE_ERROR("modeset init failed: %d\n", rc);
  3531. goto drm_obj_init_err;
  3532. }
  3533. return 0;
  3534. genpd_err:
  3535. drm_obj_init_err:
  3536. sde_core_perf_destroy(&sde_kms->perf);
  3537. hw_intr_init_err:
  3538. perf_err:
  3539. power_error:
  3540. return rc;
  3541. }
  3542. int sde_kms_get_io_resources(struct sde_kms *sde_kms, struct msm_io_res *io_res)
  3543. {
  3544. struct platform_device *pdev = to_platform_device(sde_kms->dev->dev);
  3545. int rc = 0;
  3546. rc = msm_dss_get_io_mem(pdev, &io_res->mem);
  3547. if (rc) {
  3548. SDE_ERROR("failed to get io mem for KMS, rc = %d\n", rc);
  3549. return rc;
  3550. }
  3551. rc = msm_dss_get_pmic_io_mem(pdev, &io_res->mem);
  3552. if (rc) {
  3553. SDE_ERROR("failed to get io mem for pmic, rc:%d\n", rc);
  3554. return rc;
  3555. }
  3556. rc = msm_dss_get_io_irq(pdev, &io_res->irq, HH_IRQ_LABEL_SDE);
  3557. if (rc) {
  3558. SDE_ERROR("failed to get io irq for KMS");
  3559. return rc;
  3560. }
  3561. return rc;
  3562. }
  3563. static int sde_kms_hw_init(struct msm_kms *kms)
  3564. {
  3565. struct sde_kms *sde_kms;
  3566. struct drm_device *dev;
  3567. struct msm_drm_private *priv;
  3568. struct platform_device *platformdev;
  3569. int i, irq_num, rc = -EINVAL;
  3570. if (!kms) {
  3571. SDE_ERROR("invalid kms\n");
  3572. goto end;
  3573. }
  3574. sde_kms = to_sde_kms(kms);
  3575. dev = sde_kms->dev;
  3576. if (!dev || !dev->dev) {
  3577. SDE_ERROR("invalid device\n");
  3578. goto end;
  3579. }
  3580. platformdev = to_platform_device(dev->dev);
  3581. priv = dev->dev_private;
  3582. if (!priv) {
  3583. SDE_ERROR("invalid private data\n");
  3584. goto end;
  3585. }
  3586. rc = _sde_kms_hw_init_ioremap(sde_kms, platformdev);
  3587. if (rc)
  3588. goto error;
  3589. rc = _sde_kms_get_splash_data(sde_kms, &sde_kms->splash_data);
  3590. if (rc)
  3591. SDE_DEBUG("sde splash data fetch failed: %d\n", rc);
  3592. rc = _sde_kms_hw_init_blocks(sde_kms, dev, priv);
  3593. if (rc)
  3594. goto error;
  3595. dev->mode_config.min_width = sde_kms->catalog->min_display_width;
  3596. dev->mode_config.min_height = sde_kms->catalog->min_display_height;
  3597. dev->mode_config.max_width = sde_kms->catalog->max_display_width;
  3598. dev->mode_config.max_height = sde_kms->catalog->max_display_height;
  3599. mutex_init(&sde_kms->secure_transition_lock);
  3600. atomic_set(&sde_kms->detach_sec_cb, 0);
  3601. atomic_set(&sde_kms->detach_all_cb, 0);
  3602. atomic_set(&sde_kms->irq_vote_count, 0);
  3603. /*
  3604. * Support format modifiers for compression etc.
  3605. */
  3606. dev->mode_config.allow_fb_modifiers = true;
  3607. /*
  3608. * Handle (re)initializations during power enable
  3609. */
  3610. sde_kms_handle_power_event(SDE_POWER_EVENT_POST_ENABLE, sde_kms);
  3611. sde_kms->power_event = sde_power_handle_register_event(&priv->phandle,
  3612. SDE_POWER_EVENT_POST_ENABLE |
  3613. SDE_POWER_EVENT_PRE_DISABLE,
  3614. sde_kms_handle_power_event, sde_kms, "kms");
  3615. if (sde_kms->splash_data.num_splash_displays) {
  3616. SDE_DEBUG("Skipping MDP Resources disable\n");
  3617. } else {
  3618. for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++)
  3619. sde_power_data_bus_set_quota(&priv->phandle, i,
  3620. SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA,
  3621. SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA);
  3622. pm_runtime_put_sync(sde_kms->dev->dev);
  3623. }
  3624. sde_kms->affinity_notify.notify = sde_kms_irq_affinity_notify;
  3625. sde_kms->affinity_notify.release = sde_kms_irq_affinity_release;
  3626. irq_num = platform_get_irq(to_platform_device(sde_kms->dev->dev), 0);
  3627. SDE_DEBUG("Registering for notification of irq_num: %d\n", irq_num);
  3628. irq_set_affinity_notifier(irq_num, &sde_kms->affinity_notify);
  3629. if (sde_in_trusted_vm(sde_kms))
  3630. rc = sde_vm_trusted_init(sde_kms);
  3631. else
  3632. rc = sde_vm_primary_init(sde_kms);
  3633. if (rc) {
  3634. SDE_ERROR("failed to initialize VM ops, rc: %d\n", rc);
  3635. goto error;
  3636. }
  3637. return 0;
  3638. error:
  3639. _sde_kms_hw_destroy(sde_kms, platformdev);
  3640. end:
  3641. return rc;
  3642. }
  3643. struct msm_kms *sde_kms_init(struct drm_device *dev)
  3644. {
  3645. struct msm_drm_private *priv;
  3646. struct sde_kms *sde_kms;
  3647. if (!dev || !dev->dev_private) {
  3648. SDE_ERROR("drm device node invalid\n");
  3649. return ERR_PTR(-EINVAL);
  3650. }
  3651. priv = dev->dev_private;
  3652. sde_kms = kzalloc(sizeof(*sde_kms), GFP_KERNEL);
  3653. if (!sde_kms) {
  3654. SDE_ERROR("failed to allocate sde kms\n");
  3655. return ERR_PTR(-ENOMEM);
  3656. }
  3657. msm_kms_init(&sde_kms->base, &kms_funcs);
  3658. sde_kms->dev = dev;
  3659. return &sde_kms->base;
  3660. }
  3661. void sde_kms_vm_trusted_resource_deinit(struct sde_kms *sde_kms)
  3662. {
  3663. struct dsi_display *display;
  3664. struct sde_splash_display *handoff_display;
  3665. int i;
  3666. for (i = 0; i < sde_kms->dsi_display_count; i++) {
  3667. handoff_display = &sde_kms->splash_data.splash_display[i];
  3668. display = (struct dsi_display *)sde_kms->dsi_displays[i];
  3669. if (handoff_display->cont_splash_enabled)
  3670. _sde_kms_free_splash_display_data(sde_kms,
  3671. handoff_display);
  3672. dsi_display_set_active_state(display, false);
  3673. }
  3674. memset(&sde_kms->splash_data, 0, sizeof(struct sde_splash_data));
  3675. }
  3676. int sde_kms_vm_trusted_resource_init(struct sde_kms *sde_kms)
  3677. {
  3678. struct drm_device *dev;
  3679. struct msm_drm_private *priv;
  3680. struct sde_splash_display *handoff_display;
  3681. struct dsi_display *display;
  3682. struct sde_vm_ops *vm_ops;
  3683. int ret, i;
  3684. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private) {
  3685. SDE_ERROR("invalid params\n");
  3686. return -EINVAL;
  3687. }
  3688. vm_ops = sde_vm_get_ops(sde_kms);
  3689. if (vm_ops && !vm_ops->vm_owns_hw(sde_kms)) {
  3690. SDE_DEBUG(
  3691. "skipping sde res init as device assign is not completed\n");
  3692. return 0;
  3693. }
  3694. if (sde_kms->dsi_display_count != 1) {
  3695. SDE_ERROR("no. of displays not supported:%d\n",
  3696. sde_kms->dsi_display_count);
  3697. return -EINVAL;
  3698. }
  3699. dev = sde_kms->dev;
  3700. priv = dev->dev_private;
  3701. sde_kms->splash_data.type = SDE_VM_HANDOFF;
  3702. sde_kms->splash_data.num_splash_displays = sde_kms->dsi_display_count;
  3703. ret = sde_rm_cont_splash_res_init(priv, &sde_kms->rm,
  3704. &sde_kms->splash_data, sde_kms->catalog);
  3705. for (i = 0; i < sde_kms->dsi_display_count; i++) {
  3706. handoff_display = &sde_kms->splash_data.splash_display[i];
  3707. display = (struct dsi_display *)sde_kms->dsi_displays[i];
  3708. if (!handoff_display->cont_splash_enabled || ret)
  3709. _sde_kms_free_splash_display_data(sde_kms,
  3710. handoff_display);
  3711. else
  3712. dsi_display_set_active_state(display, true);
  3713. }
  3714. ret = sde_kms_cont_splash_config(&sde_kms->base);
  3715. if (ret) {
  3716. SDE_ERROR("error in setting handoff configs\n");
  3717. goto error;
  3718. }
  3719. /**
  3720. * fill-in vote for the continuous splash hanodff path, which will be
  3721. * removed on the successful first commit.
  3722. */
  3723. pm_runtime_get_sync(sde_kms->dev->dev);
  3724. return 0;
  3725. error:
  3726. sde_kms_vm_trusted_resource_deinit(sde_kms);
  3727. return ret;
  3728. }
  3729. static int _sde_kms_register_events(struct msm_kms *kms,
  3730. struct drm_mode_object *obj, u32 event, bool en)
  3731. {
  3732. int ret = 0;
  3733. struct drm_crtc *crtc = NULL;
  3734. struct drm_connector *conn = NULL;
  3735. struct sde_kms *sde_kms = NULL;
  3736. if (!kms || !obj) {
  3737. SDE_ERROR("invalid argument kms %pK obj %pK\n", kms, obj);
  3738. return -EINVAL;
  3739. }
  3740. sde_kms = to_sde_kms(kms);
  3741. switch (obj->type) {
  3742. case DRM_MODE_OBJECT_CRTC:
  3743. crtc = obj_to_crtc(obj);
  3744. ret = sde_crtc_register_custom_event(sde_kms, crtc, event, en);
  3745. break;
  3746. case DRM_MODE_OBJECT_CONNECTOR:
  3747. conn = obj_to_connector(obj);
  3748. ret = sde_connector_register_custom_event(sde_kms, conn, event,
  3749. en);
  3750. break;
  3751. }
  3752. return ret;
  3753. }
  3754. int sde_kms_handle_recovery(struct drm_encoder *encoder)
  3755. {
  3756. SDE_EVT32(DRMID(encoder), MSM_ENC_ACTIVE_REGION);
  3757. return sde_encoder_wait_for_event(encoder, MSM_ENC_ACTIVE_REGION);
  3758. }