dp_tx.c 178 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "htt.h"
  20. #include "dp_htt.h"
  21. #include "hal_hw_headers.h"
  22. #include "dp_tx.h"
  23. #include "dp_tx_desc.h"
  24. #include "dp_peer.h"
  25. #include "dp_types.h"
  26. #include "hal_tx.h"
  27. #include "qdf_mem.h"
  28. #include "qdf_nbuf.h"
  29. #include "qdf_net_types.h"
  30. #include "qdf_module.h"
  31. #include <wlan_cfg.h>
  32. #include "dp_ipa.h"
  33. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  34. #include "if_meta_hdr.h"
  35. #endif
  36. #include "enet.h"
  37. #include "dp_internal.h"
  38. #ifdef ATH_SUPPORT_IQUE
  39. #include "dp_txrx_me.h"
  40. #endif
  41. #include "dp_hist.h"
  42. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  43. #include <wlan_dp_swlm.h>
  44. #endif
  45. #ifdef WIFI_MONITOR_SUPPORT
  46. #include <dp_mon.h>
  47. #endif
  48. #ifdef FEATURE_WDS
  49. #include "dp_txrx_wds.h"
  50. #endif
  51. #include "cdp_txrx_cmn_reg.h"
  52. #ifdef CONFIG_SAWF
  53. #include <dp_sawf.h>
  54. #endif
  55. /* Flag to skip CCE classify when mesh or tid override enabled */
  56. #define DP_TX_SKIP_CCE_CLASSIFY \
  57. (DP_TXRX_HLOS_TID_OVERRIDE_ENABLED | DP_TX_MESH_ENABLED)
  58. /* TODO Add support in TSO */
  59. #define DP_DESC_NUM_FRAG(x) 0
  60. /* disable TQM_BYPASS */
  61. #define TQM_BYPASS_WAR 0
  62. /* invalid peer id for reinject*/
  63. #define DP_INVALID_PEER 0XFFFE
  64. #define DP_RETRY_COUNT 7
  65. #ifdef WLAN_PEER_JITTER
  66. #define DP_AVG_JITTER_WEIGHT_DENOM 4
  67. #define DP_AVG_DELAY_WEIGHT_DENOM 3
  68. #endif
  69. #ifdef QCA_DP_TX_FW_METADATA_V2
  70. #define DP_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)\
  71. HTT_TX_TCL_METADATA_V2_PDEV_ID_SET(_var, _val)
  72. #define DP_TX_TCL_METADATA_VALID_HTT_SET(_var, _val) \
  73. HTT_TX_TCL_METADATA_V2_VALID_HTT_SET(_var, _val)
  74. #define DP_TX_TCL_METADATA_TYPE_SET(_var, _val) \
  75. HTT_TX_TCL_METADATA_TYPE_V2_SET(_var, _val)
  76. #define DP_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val) \
  77. HTT_TX_TCL_METADATA_V2_HOST_INSPECTED_SET(_var, _val)
  78. #define DP_TX_TCL_METADATA_PEER_ID_SET(_var, _val) \
  79. HTT_TX_TCL_METADATA_V2_PEER_ID_SET(_var, _val)
  80. #define DP_TX_TCL_METADATA_VDEV_ID_SET(_var, _val) \
  81. HTT_TX_TCL_METADATA_V2_VDEV_ID_SET(_var, _val)
  82. #define DP_TCL_METADATA_TYPE_PEER_BASED \
  83. HTT_TCL_METADATA_V2_TYPE_PEER_BASED
  84. #define DP_TCL_METADATA_TYPE_VDEV_BASED \
  85. HTT_TCL_METADATA_V2_TYPE_VDEV_BASED
  86. #else
  87. #define DP_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)\
  88. HTT_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)
  89. #define DP_TX_TCL_METADATA_VALID_HTT_SET(_var, _val) \
  90. HTT_TX_TCL_METADATA_VALID_HTT_SET(_var, _val)
  91. #define DP_TX_TCL_METADATA_TYPE_SET(_var, _val) \
  92. HTT_TX_TCL_METADATA_TYPE_SET(_var, _val)
  93. #define DP_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val) \
  94. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val)
  95. #define DP_TX_TCL_METADATA_PEER_ID_SET(_var, _val) \
  96. HTT_TX_TCL_METADATA_PEER_ID_SET(_var, _val)
  97. #define DP_TX_TCL_METADATA_VDEV_ID_SET(_var, _val) \
  98. HTT_TX_TCL_METADATA_VDEV_ID_SET(_var, _val)
  99. #define DP_TCL_METADATA_TYPE_PEER_BASED \
  100. HTT_TCL_METADATA_TYPE_PEER_BASED
  101. #define DP_TCL_METADATA_TYPE_VDEV_BASED \
  102. HTT_TCL_METADATA_TYPE_VDEV_BASED
  103. #endif
  104. /*mapping between hal encrypt type and cdp_sec_type*/
  105. uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  106. HAL_TX_ENCRYPT_TYPE_WEP_128,
  107. HAL_TX_ENCRYPT_TYPE_WEP_104,
  108. HAL_TX_ENCRYPT_TYPE_WEP_40,
  109. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  110. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  111. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  112. HAL_TX_ENCRYPT_TYPE_WAPI,
  113. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  114. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  115. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  116. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  117. qdf_export_symbol(sec_type_map);
  118. #ifdef WLAN_FEATURE_DP_TX_DESC_HISTORY
  119. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  120. {
  121. enum dp_tx_event_type type;
  122. if (flags & DP_TX_DESC_FLAG_FLUSH)
  123. type = DP_TX_DESC_FLUSH;
  124. else if (flags & DP_TX_DESC_FLAG_TX_COMP_ERR)
  125. type = DP_TX_COMP_UNMAP_ERR;
  126. else if (flags & DP_TX_DESC_FLAG_COMPLETED_TX)
  127. type = DP_TX_COMP_UNMAP;
  128. else
  129. type = DP_TX_DESC_UNMAP;
  130. return type;
  131. }
  132. static inline void
  133. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  134. qdf_nbuf_t skb, uint32_t sw_cookie,
  135. enum dp_tx_event_type type)
  136. {
  137. struct dp_tx_tcl_history *tx_tcl_history = &soc->tx_tcl_history;
  138. struct dp_tx_comp_history *tx_comp_history = &soc->tx_comp_history;
  139. struct dp_tx_desc_event *entry;
  140. uint32_t idx;
  141. uint16_t slot;
  142. switch (type) {
  143. case DP_TX_COMP_UNMAP:
  144. case DP_TX_COMP_UNMAP_ERR:
  145. case DP_TX_COMP_MSDU_EXT:
  146. if (qdf_unlikely(!tx_comp_history->allocated))
  147. return;
  148. dp_get_frag_hist_next_atomic_idx(&tx_comp_history->index, &idx,
  149. &slot,
  150. DP_TX_COMP_HIST_SLOT_SHIFT,
  151. DP_TX_COMP_HIST_PER_SLOT_MAX,
  152. DP_TX_COMP_HISTORY_SIZE);
  153. entry = &tx_comp_history->entry[slot][idx];
  154. break;
  155. case DP_TX_DESC_MAP:
  156. case DP_TX_DESC_UNMAP:
  157. case DP_TX_DESC_COOKIE:
  158. case DP_TX_DESC_FLUSH:
  159. if (qdf_unlikely(!tx_tcl_history->allocated))
  160. return;
  161. dp_get_frag_hist_next_atomic_idx(&tx_tcl_history->index, &idx,
  162. &slot,
  163. DP_TX_TCL_HIST_SLOT_SHIFT,
  164. DP_TX_TCL_HIST_PER_SLOT_MAX,
  165. DP_TX_TCL_HISTORY_SIZE);
  166. entry = &tx_tcl_history->entry[slot][idx];
  167. break;
  168. default:
  169. dp_info_rl("Invalid dp_tx_event_type: %d", type);
  170. return;
  171. }
  172. entry->skb = skb;
  173. entry->paddr = paddr;
  174. entry->sw_cookie = sw_cookie;
  175. entry->type = type;
  176. entry->ts = qdf_get_log_timestamp();
  177. }
  178. static inline void
  179. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  180. struct qdf_tso_seg_elem_t *tso_seg,
  181. qdf_nbuf_t skb, uint32_t sw_cookie,
  182. enum dp_tx_event_type type)
  183. {
  184. int i;
  185. for (i = 1; i < tso_seg->seg.num_frags; i++) {
  186. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[i].paddr,
  187. skb, sw_cookie, type);
  188. }
  189. if (!tso_seg->next)
  190. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[0].paddr,
  191. skb, 0xFFFFFFFF, type);
  192. }
  193. static inline void
  194. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  195. qdf_nbuf_t skb, uint32_t sw_cookie,
  196. enum dp_tx_event_type type)
  197. {
  198. struct qdf_tso_seg_elem_t *curr_seg = tso_info.tso_seg_list;
  199. uint32_t num_segs = tso_info.num_segs;
  200. while (num_segs) {
  201. dp_tx_tso_seg_history_add(soc, curr_seg, skb, sw_cookie, type);
  202. curr_seg = curr_seg->next;
  203. num_segs--;
  204. }
  205. }
  206. #else
  207. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  208. {
  209. return DP_TX_DESC_INVAL_EVT;
  210. }
  211. static inline void
  212. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  213. qdf_nbuf_t skb, uint32_t sw_cookie,
  214. enum dp_tx_event_type type)
  215. {
  216. }
  217. static inline void
  218. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  219. struct qdf_tso_seg_elem_t *tso_seg,
  220. qdf_nbuf_t skb, uint32_t sw_cookie,
  221. enum dp_tx_event_type type)
  222. {
  223. }
  224. static inline void
  225. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  226. qdf_nbuf_t skb, uint32_t sw_cookie,
  227. enum dp_tx_event_type type)
  228. {
  229. }
  230. #endif /* WLAN_FEATURE_DP_TX_DESC_HISTORY */
  231. static int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc);
  232. /**
  233. * dp_is_tput_high() - Check if throughput is high
  234. *
  235. * @soc - core txrx main context
  236. *
  237. * The current function is based of the RTPM tput policy variable where RTPM is
  238. * avoided based on throughput.
  239. */
  240. static inline int dp_is_tput_high(struct dp_soc *soc)
  241. {
  242. return dp_get_rtpm_tput_policy_requirement(soc);
  243. }
  244. #if defined(FEATURE_TSO)
  245. /**
  246. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  247. *
  248. * @soc - core txrx main context
  249. * @seg_desc - tso segment descriptor
  250. * @num_seg_desc - tso number segment descriptor
  251. */
  252. static void dp_tx_tso_unmap_segment(
  253. struct dp_soc *soc,
  254. struct qdf_tso_seg_elem_t *seg_desc,
  255. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  256. {
  257. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  258. if (qdf_unlikely(!seg_desc)) {
  259. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  260. __func__, __LINE__);
  261. qdf_assert(0);
  262. } else if (qdf_unlikely(!num_seg_desc)) {
  263. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  264. __func__, __LINE__);
  265. qdf_assert(0);
  266. } else {
  267. bool is_last_seg;
  268. /* no tso segment left to do dma unmap */
  269. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  270. return;
  271. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  272. true : false;
  273. qdf_nbuf_unmap_tso_segment(soc->osdev,
  274. seg_desc, is_last_seg);
  275. num_seg_desc->num_seg.tso_cmn_num_seg--;
  276. }
  277. }
  278. /**
  279. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  280. * back to the freelist
  281. *
  282. * @soc - soc device handle
  283. * @tx_desc - Tx software descriptor
  284. */
  285. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  286. struct dp_tx_desc_s *tx_desc)
  287. {
  288. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  289. if (qdf_unlikely(!tx_desc->msdu_ext_desc->tso_desc)) {
  290. dp_tx_err("SO desc is NULL!");
  291. qdf_assert(0);
  292. } else if (qdf_unlikely(!tx_desc->msdu_ext_desc->tso_num_desc)) {
  293. dp_tx_err("TSO num desc is NULL!");
  294. qdf_assert(0);
  295. } else {
  296. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  297. (struct qdf_tso_num_seg_elem_t *)tx_desc->
  298. msdu_ext_desc->tso_num_desc;
  299. /* Add the tso num segment into the free list */
  300. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  301. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  302. tx_desc->msdu_ext_desc->
  303. tso_num_desc);
  304. tx_desc->msdu_ext_desc->tso_num_desc = NULL;
  305. DP_STATS_INC(tx_desc->pdev, tso_stats.tso_comp, 1);
  306. }
  307. /* Add the tso segment into the free list*/
  308. dp_tx_tso_desc_free(soc,
  309. tx_desc->pool_id, tx_desc->msdu_ext_desc->
  310. tso_desc);
  311. tx_desc->msdu_ext_desc->tso_desc = NULL;
  312. }
  313. }
  314. #else
  315. static void dp_tx_tso_unmap_segment(
  316. struct dp_soc *soc,
  317. struct qdf_tso_seg_elem_t *seg_desc,
  318. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  319. {
  320. }
  321. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  322. struct dp_tx_desc_s *tx_desc)
  323. {
  324. }
  325. #endif
  326. /**
  327. * dp_tx_desc_release() - Release Tx Descriptor
  328. * @tx_desc : Tx Descriptor
  329. * @desc_pool_id: Descriptor Pool ID
  330. *
  331. * Deallocate all resources attached to Tx descriptor and free the Tx
  332. * descriptor.
  333. *
  334. * Return:
  335. */
  336. void
  337. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  338. {
  339. struct dp_pdev *pdev = tx_desc->pdev;
  340. struct dp_soc *soc;
  341. uint8_t comp_status = 0;
  342. qdf_assert(pdev);
  343. soc = pdev->soc;
  344. dp_tx_outstanding_dec(pdev);
  345. if (tx_desc->msdu_ext_desc) {
  346. if (tx_desc->frm_type == dp_tx_frm_tso)
  347. dp_tx_tso_desc_release(soc, tx_desc);
  348. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  349. dp_tx_me_free_buf(tx_desc->pdev,
  350. tx_desc->msdu_ext_desc->me_buffer);
  351. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  352. }
  353. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  354. qdf_atomic_dec(&soc->num_tx_exception);
  355. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  356. tx_desc->buffer_src)
  357. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  358. soc->hal_soc);
  359. else
  360. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  361. dp_tx_debug("Tx Completion Release desc %d status %d outstanding %d",
  362. tx_desc->id, comp_status,
  363. qdf_atomic_read(&pdev->num_tx_outstanding));
  364. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  365. return;
  366. }
  367. /**
  368. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  369. * @vdev: DP vdev Handle
  370. * @nbuf: skb
  371. * @msdu_info: msdu_info required to create HTT metadata
  372. *
  373. * Prepares and fills HTT metadata in the frame pre-header for special frames
  374. * that should be transmitted using varying transmit parameters.
  375. * There are 2 VDEV modes that currently needs this special metadata -
  376. * 1) Mesh Mode
  377. * 2) DSRC Mode
  378. *
  379. * Return: HTT metadata size
  380. *
  381. */
  382. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  383. struct dp_tx_msdu_info_s *msdu_info)
  384. {
  385. uint32_t *meta_data = msdu_info->meta_data;
  386. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  387. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  388. uint8_t htt_desc_size;
  389. /* Size rounded of multiple of 8 bytes */
  390. uint8_t htt_desc_size_aligned;
  391. uint8_t *hdr = NULL;
  392. /*
  393. * Metadata - HTT MSDU Extension header
  394. */
  395. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  396. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  397. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  398. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  399. meta_data[0]) ||
  400. msdu_info->exception_fw) {
  401. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  402. htt_desc_size_aligned)) {
  403. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  404. htt_desc_size_aligned);
  405. if (!nbuf) {
  406. /*
  407. * qdf_nbuf_realloc_headroom won't do skb_clone
  408. * as skb_realloc_headroom does. so, no free is
  409. * needed here.
  410. */
  411. DP_STATS_INC(vdev,
  412. tx_i.dropped.headroom_insufficient,
  413. 1);
  414. qdf_print(" %s[%d] skb_realloc_headroom failed",
  415. __func__, __LINE__);
  416. return 0;
  417. }
  418. }
  419. /* Fill and add HTT metaheader */
  420. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  421. if (!hdr) {
  422. dp_tx_err("Error in filling HTT metadata");
  423. return 0;
  424. }
  425. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  426. } else if (vdev->opmode == wlan_op_mode_ocb) {
  427. /* Todo - Add support for DSRC */
  428. }
  429. return htt_desc_size_aligned;
  430. }
  431. /**
  432. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  433. * @tso_seg: TSO segment to process
  434. * @ext_desc: Pointer to MSDU extension descriptor
  435. *
  436. * Return: void
  437. */
  438. #if defined(FEATURE_TSO)
  439. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  440. void *ext_desc)
  441. {
  442. uint8_t num_frag;
  443. uint32_t tso_flags;
  444. /*
  445. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  446. * tcp_flag_mask
  447. *
  448. * Checksum enable flags are set in TCL descriptor and not in Extension
  449. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  450. */
  451. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  452. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  453. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  454. tso_seg->tso_flags.ip_len);
  455. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  456. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  457. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  458. uint32_t lo = 0;
  459. uint32_t hi = 0;
  460. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  461. (tso_seg->tso_frags[num_frag].length));
  462. qdf_dmaaddr_to_32s(
  463. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  464. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  465. tso_seg->tso_frags[num_frag].length);
  466. }
  467. return;
  468. }
  469. #else
  470. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  471. void *ext_desc)
  472. {
  473. return;
  474. }
  475. #endif
  476. #if defined(FEATURE_TSO)
  477. /**
  478. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  479. * allocated and free them
  480. *
  481. * @soc: soc handle
  482. * @free_seg: list of tso segments
  483. * @msdu_info: msdu descriptor
  484. *
  485. * Return - void
  486. */
  487. static void dp_tx_free_tso_seg_list(
  488. struct dp_soc *soc,
  489. struct qdf_tso_seg_elem_t *free_seg,
  490. struct dp_tx_msdu_info_s *msdu_info)
  491. {
  492. struct qdf_tso_seg_elem_t *next_seg;
  493. while (free_seg) {
  494. next_seg = free_seg->next;
  495. dp_tx_tso_desc_free(soc,
  496. msdu_info->tx_queue.desc_pool_id,
  497. free_seg);
  498. free_seg = next_seg;
  499. }
  500. }
  501. /**
  502. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  503. * allocated and free them
  504. *
  505. * @soc: soc handle
  506. * @free_num_seg: list of tso number segments
  507. * @msdu_info: msdu descriptor
  508. * Return - void
  509. */
  510. static void dp_tx_free_tso_num_seg_list(
  511. struct dp_soc *soc,
  512. struct qdf_tso_num_seg_elem_t *free_num_seg,
  513. struct dp_tx_msdu_info_s *msdu_info)
  514. {
  515. struct qdf_tso_num_seg_elem_t *next_num_seg;
  516. while (free_num_seg) {
  517. next_num_seg = free_num_seg->next;
  518. dp_tso_num_seg_free(soc,
  519. msdu_info->tx_queue.desc_pool_id,
  520. free_num_seg);
  521. free_num_seg = next_num_seg;
  522. }
  523. }
  524. /**
  525. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  526. * do dma unmap for each segment
  527. *
  528. * @soc: soc handle
  529. * @free_seg: list of tso segments
  530. * @num_seg_desc: tso number segment descriptor
  531. *
  532. * Return - void
  533. */
  534. static void dp_tx_unmap_tso_seg_list(
  535. struct dp_soc *soc,
  536. struct qdf_tso_seg_elem_t *free_seg,
  537. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  538. {
  539. struct qdf_tso_seg_elem_t *next_seg;
  540. if (qdf_unlikely(!num_seg_desc)) {
  541. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  542. return;
  543. }
  544. while (free_seg) {
  545. next_seg = free_seg->next;
  546. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  547. free_seg = next_seg;
  548. }
  549. }
  550. #ifdef FEATURE_TSO_STATS
  551. /**
  552. * dp_tso_get_stats_idx: Retrieve the tso packet id
  553. * @pdev - pdev handle
  554. *
  555. * Return: id
  556. */
  557. static uint32_t dp_tso_get_stats_idx(struct dp_pdev *pdev)
  558. {
  559. uint32_t stats_idx;
  560. stats_idx = (((uint32_t)qdf_atomic_inc_return(&pdev->tso_idx))
  561. % CDP_MAX_TSO_PACKETS);
  562. return stats_idx;
  563. }
  564. #else
  565. static int dp_tso_get_stats_idx(struct dp_pdev *pdev)
  566. {
  567. return 0;
  568. }
  569. #endif /* FEATURE_TSO_STATS */
  570. /**
  571. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  572. * free the tso segments descriptor and
  573. * tso num segments descriptor
  574. *
  575. * @soc: soc handle
  576. * @msdu_info: msdu descriptor
  577. * @tso_seg_unmap: flag to show if dma unmap is necessary
  578. *
  579. * Return - void
  580. */
  581. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  582. struct dp_tx_msdu_info_s *msdu_info,
  583. bool tso_seg_unmap)
  584. {
  585. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  586. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  587. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  588. tso_info->tso_num_seg_list;
  589. /* do dma unmap for each segment */
  590. if (tso_seg_unmap)
  591. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  592. /* free all tso number segment descriptor though looks only have 1 */
  593. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  594. /* free all tso segment descriptor */
  595. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  596. }
  597. /**
  598. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  599. * @vdev: virtual device handle
  600. * @msdu: network buffer
  601. * @msdu_info: meta data associated with the msdu
  602. *
  603. * Return: QDF_STATUS_SUCCESS success
  604. */
  605. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  606. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  607. {
  608. struct qdf_tso_seg_elem_t *tso_seg;
  609. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  610. struct dp_soc *soc = vdev->pdev->soc;
  611. struct dp_pdev *pdev = vdev->pdev;
  612. struct qdf_tso_info_t *tso_info;
  613. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  614. tso_info = &msdu_info->u.tso_info;
  615. tso_info->curr_seg = NULL;
  616. tso_info->tso_seg_list = NULL;
  617. tso_info->num_segs = num_seg;
  618. msdu_info->frm_type = dp_tx_frm_tso;
  619. tso_info->tso_num_seg_list = NULL;
  620. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  621. while (num_seg) {
  622. tso_seg = dp_tx_tso_desc_alloc(
  623. soc, msdu_info->tx_queue.desc_pool_id);
  624. if (tso_seg) {
  625. tso_seg->next = tso_info->tso_seg_list;
  626. tso_info->tso_seg_list = tso_seg;
  627. num_seg--;
  628. } else {
  629. dp_err_rl("Failed to alloc tso seg desc");
  630. DP_STATS_INC_PKT(vdev->pdev,
  631. tso_stats.tso_no_mem_dropped, 1,
  632. qdf_nbuf_len(msdu));
  633. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  634. return QDF_STATUS_E_NOMEM;
  635. }
  636. }
  637. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  638. tso_num_seg = dp_tso_num_seg_alloc(soc,
  639. msdu_info->tx_queue.desc_pool_id);
  640. if (tso_num_seg) {
  641. tso_num_seg->next = tso_info->tso_num_seg_list;
  642. tso_info->tso_num_seg_list = tso_num_seg;
  643. } else {
  644. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  645. __func__);
  646. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  647. return QDF_STATUS_E_NOMEM;
  648. }
  649. msdu_info->num_seg =
  650. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  651. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  652. msdu_info->num_seg);
  653. if (!(msdu_info->num_seg)) {
  654. /*
  655. * Free allocated TSO seg desc and number seg desc,
  656. * do unmap for segments if dma map has done.
  657. */
  658. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  659. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  660. return QDF_STATUS_E_INVAL;
  661. }
  662. dp_tx_tso_history_add(soc, msdu_info->u.tso_info,
  663. msdu, 0, DP_TX_DESC_MAP);
  664. tso_info->curr_seg = tso_info->tso_seg_list;
  665. tso_info->msdu_stats_idx = dp_tso_get_stats_idx(pdev);
  666. dp_tso_packet_update(pdev, tso_info->msdu_stats_idx,
  667. msdu, msdu_info->num_seg);
  668. dp_tso_segment_stats_update(pdev, tso_info->tso_seg_list,
  669. tso_info->msdu_stats_idx);
  670. dp_stats_tso_segment_histogram_update(pdev, msdu_info->num_seg);
  671. return QDF_STATUS_SUCCESS;
  672. }
  673. #else
  674. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  675. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  676. {
  677. return QDF_STATUS_E_NOMEM;
  678. }
  679. #endif
  680. QDF_COMPILE_TIME_ASSERT(dp_tx_htt_metadata_len_check,
  681. (DP_TX_MSDU_INFO_META_DATA_DWORDS * 4 >=
  682. sizeof(struct htt_tx_msdu_desc_ext2_t)));
  683. /**
  684. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  685. * @vdev: DP Vdev handle
  686. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  687. * @desc_pool_id: Descriptor Pool ID
  688. *
  689. * Return:
  690. */
  691. static
  692. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  693. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  694. {
  695. uint8_t i;
  696. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  697. struct dp_tx_seg_info_s *seg_info;
  698. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  699. struct dp_soc *soc = vdev->pdev->soc;
  700. /* Allocate an extension descriptor */
  701. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  702. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  703. if (!msdu_ext_desc) {
  704. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  705. return NULL;
  706. }
  707. if (msdu_info->exception_fw &&
  708. qdf_unlikely(vdev->mesh_vdev)) {
  709. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  710. &msdu_info->meta_data[0],
  711. sizeof(struct htt_tx_msdu_desc_ext2_t));
  712. qdf_atomic_inc(&soc->num_tx_exception);
  713. msdu_ext_desc->flags |= DP_TX_EXT_DESC_FLAG_METADATA_VALID;
  714. }
  715. switch (msdu_info->frm_type) {
  716. case dp_tx_frm_sg:
  717. case dp_tx_frm_me:
  718. case dp_tx_frm_raw:
  719. seg_info = msdu_info->u.sg_info.curr_seg;
  720. /* Update the buffer pointers in MSDU Extension Descriptor */
  721. for (i = 0; i < seg_info->frag_cnt; i++) {
  722. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  723. seg_info->frags[i].paddr_lo,
  724. seg_info->frags[i].paddr_hi,
  725. seg_info->frags[i].len);
  726. }
  727. break;
  728. case dp_tx_frm_tso:
  729. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  730. &cached_ext_desc[0]);
  731. break;
  732. default:
  733. break;
  734. }
  735. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  736. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  737. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  738. msdu_ext_desc->vaddr);
  739. return msdu_ext_desc;
  740. }
  741. /**
  742. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  743. *
  744. * @skb: skb to be traced
  745. * @msdu_id: msdu_id of the packet
  746. * @vdev_id: vdev_id of the packet
  747. *
  748. * Return: None
  749. */
  750. #ifdef DP_DISABLE_TX_PKT_TRACE
  751. static void dp_tx_trace_pkt(struct dp_soc *soc,
  752. qdf_nbuf_t skb, uint16_t msdu_id,
  753. uint8_t vdev_id)
  754. {
  755. }
  756. #else
  757. static void dp_tx_trace_pkt(struct dp_soc *soc,
  758. qdf_nbuf_t skb, uint16_t msdu_id,
  759. uint8_t vdev_id)
  760. {
  761. if (dp_is_tput_high(soc))
  762. return;
  763. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  764. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  765. DPTRACE(qdf_dp_trace_ptr(skb,
  766. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  767. QDF_TRACE_DEFAULT_PDEV_ID,
  768. qdf_nbuf_data_addr(skb),
  769. sizeof(qdf_nbuf_data(skb)),
  770. msdu_id, vdev_id, 0));
  771. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  772. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  773. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  774. msdu_id, QDF_TX));
  775. }
  776. #endif
  777. #ifdef WLAN_DP_FEATURE_MARK_ICMP_REQ_TO_FW
  778. /**
  779. * dp_tx_is_nbuf_marked_exception() - Check if the packet has been marked as
  780. * exception by the upper layer (OS_IF)
  781. * @soc: DP soc handle
  782. * @nbuf: packet to be transmitted
  783. *
  784. * Returns: 1 if the packet is marked as exception,
  785. * 0, if the packet is not marked as exception.
  786. */
  787. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  788. qdf_nbuf_t nbuf)
  789. {
  790. return QDF_NBUF_CB_TX_PACKET_TO_FW(nbuf);
  791. }
  792. #else
  793. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  794. qdf_nbuf_t nbuf)
  795. {
  796. return 0;
  797. }
  798. #endif
  799. #ifdef DP_TRAFFIC_END_INDICATION
  800. /**
  801. * dp_tx_get_traffic_end_indication_pkt() - Allocate and prepare packet to send
  802. * as indication to fw to inform that
  803. * data stream has ended
  804. * @vdev: DP vdev handle
  805. * @nbuf: original buffer from network stack
  806. *
  807. * Return: NULL on failure,
  808. * nbuf on success
  809. */
  810. static inline qdf_nbuf_t
  811. dp_tx_get_traffic_end_indication_pkt(struct dp_vdev *vdev,
  812. qdf_nbuf_t nbuf)
  813. {
  814. /* Packet length should be enough to copy upto L3 header */
  815. uint8_t end_nbuf_len = 64;
  816. uint8_t htt_desc_size_aligned;
  817. uint8_t htt_desc_size;
  818. qdf_nbuf_t end_nbuf;
  819. if (qdf_unlikely(QDF_NBUF_CB_GET_PACKET_TYPE(nbuf) ==
  820. QDF_NBUF_CB_PACKET_TYPE_END_INDICATION)) {
  821. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  822. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  823. end_nbuf = qdf_nbuf_queue_remove(&vdev->end_ind_pkt_q);
  824. if (!end_nbuf) {
  825. end_nbuf = qdf_nbuf_alloc(NULL,
  826. (htt_desc_size_aligned +
  827. end_nbuf_len),
  828. htt_desc_size_aligned,
  829. 8, false);
  830. if (!end_nbuf) {
  831. dp_err("Packet allocation failed");
  832. goto out;
  833. }
  834. } else {
  835. qdf_nbuf_reset(end_nbuf, htt_desc_size_aligned, 8);
  836. }
  837. qdf_mem_copy(qdf_nbuf_data(end_nbuf), qdf_nbuf_data(nbuf),
  838. end_nbuf_len);
  839. qdf_nbuf_set_pktlen(end_nbuf, end_nbuf_len);
  840. return end_nbuf;
  841. }
  842. out:
  843. return NULL;
  844. }
  845. /**
  846. * dp_tx_send_traffic_end_indication_pkt() - Send indication packet to FW
  847. * via exception path.
  848. * @vdev: DP vdev handle
  849. * @end_nbuf: skb to send as indication
  850. * @msdu_info: msdu_info of original nbuf
  851. * @peer_id: peer id
  852. *
  853. * Return: None
  854. */
  855. static inline void
  856. dp_tx_send_traffic_end_indication_pkt(struct dp_vdev *vdev,
  857. qdf_nbuf_t end_nbuf,
  858. struct dp_tx_msdu_info_s *msdu_info,
  859. uint16_t peer_id)
  860. {
  861. struct dp_tx_msdu_info_s e_msdu_info = {0};
  862. qdf_nbuf_t nbuf;
  863. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  864. (struct htt_tx_msdu_desc_ext2_t *)(e_msdu_info.meta_data);
  865. e_msdu_info.tx_queue = msdu_info->tx_queue;
  866. e_msdu_info.tid = msdu_info->tid;
  867. e_msdu_info.exception_fw = 1;
  868. desc_ext->host_tx_desc_pool = 1;
  869. desc_ext->traffic_end_indication = 1;
  870. nbuf = dp_tx_send_msdu_single(vdev, end_nbuf, &e_msdu_info,
  871. peer_id, NULL);
  872. if (nbuf) {
  873. dp_err("Traffic end indication packet tx failed");
  874. qdf_nbuf_free(nbuf);
  875. }
  876. }
  877. /**
  878. * dp_tx_traffic_end_indication_set_desc_flag() - Set tx descriptor flag to
  879. * mark it traffic end indication
  880. * packet.
  881. * @tx_desc: Tx descriptor pointer
  882. * @msdu_info: msdu_info structure pointer
  883. *
  884. * Return: None
  885. */
  886. static inline void
  887. dp_tx_traffic_end_indication_set_desc_flag(struct dp_tx_desc_s *tx_desc,
  888. struct dp_tx_msdu_info_s *msdu_info)
  889. {
  890. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  891. (struct htt_tx_msdu_desc_ext2_t *)(msdu_info->meta_data);
  892. if (qdf_unlikely(desc_ext->traffic_end_indication))
  893. tx_desc->flags |= DP_TX_DESC_FLAG_TRAFFIC_END_IND;
  894. }
  895. /**
  896. * dp_tx_traffic_end_indication_enq_ind_pkt() - Enqueue the packet instead of
  897. * freeing which are associated
  898. * with traffic end indication
  899. * flagged descriptor.
  900. * @soc: dp soc handle
  901. * @desc: Tx descriptor pointer
  902. * @nbuf: buffer pointer
  903. *
  904. * Return: True if packet gets enqueued else false
  905. */
  906. static bool
  907. dp_tx_traffic_end_indication_enq_ind_pkt(struct dp_soc *soc,
  908. struct dp_tx_desc_s *desc,
  909. qdf_nbuf_t nbuf)
  910. {
  911. struct dp_vdev *vdev = NULL;
  912. if (qdf_unlikely((desc->flags &
  913. DP_TX_DESC_FLAG_TRAFFIC_END_IND) != 0)) {
  914. vdev = dp_vdev_get_ref_by_id(soc, desc->vdev_id,
  915. DP_MOD_ID_TX_COMP);
  916. if (vdev) {
  917. qdf_nbuf_queue_add(&vdev->end_ind_pkt_q, nbuf);
  918. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_COMP);
  919. return true;
  920. }
  921. }
  922. return false;
  923. }
  924. /**
  925. * dp_tx_traffic_end_indication_is_enabled() - get the feature
  926. * enable/disable status
  927. * @vdev: dp vdev handle
  928. *
  929. * Return: True if feature is enable else false
  930. */
  931. static inline bool
  932. dp_tx_traffic_end_indication_is_enabled(struct dp_vdev *vdev)
  933. {
  934. return qdf_unlikely(vdev->traffic_end_ind_en);
  935. }
  936. static inline qdf_nbuf_t
  937. dp_tx_send_msdu_single_wrapper(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  938. struct dp_tx_msdu_info_s *msdu_info,
  939. uint16_t peer_id, qdf_nbuf_t end_nbuf)
  940. {
  941. if (dp_tx_traffic_end_indication_is_enabled(vdev))
  942. end_nbuf = dp_tx_get_traffic_end_indication_pkt(vdev, nbuf);
  943. nbuf = dp_tx_send_msdu_single(vdev, nbuf, msdu_info, peer_id, NULL);
  944. if (qdf_unlikely(end_nbuf))
  945. dp_tx_send_traffic_end_indication_pkt(vdev, end_nbuf,
  946. msdu_info, peer_id);
  947. return nbuf;
  948. }
  949. #else
  950. static inline qdf_nbuf_t
  951. dp_tx_get_traffic_end_indication_pkt(struct dp_vdev *vdev,
  952. qdf_nbuf_t nbuf)
  953. {
  954. return NULL;
  955. }
  956. static inline void
  957. dp_tx_send_traffic_end_indication_pkt(struct dp_vdev *vdev,
  958. qdf_nbuf_t end_nbuf,
  959. struct dp_tx_msdu_info_s *msdu_info,
  960. uint16_t peer_id)
  961. {}
  962. static inline void
  963. dp_tx_traffic_end_indication_set_desc_flag(struct dp_tx_desc_s *tx_desc,
  964. struct dp_tx_msdu_info_s *msdu_info)
  965. {}
  966. static inline bool
  967. dp_tx_traffic_end_indication_enq_ind_pkt(struct dp_soc *soc,
  968. struct dp_tx_desc_s *desc,
  969. qdf_nbuf_t nbuf)
  970. {
  971. return false;
  972. }
  973. static inline bool
  974. dp_tx_traffic_end_indication_is_enabled(struct dp_vdev *vdev)
  975. {
  976. return false;
  977. }
  978. static inline qdf_nbuf_t
  979. dp_tx_send_msdu_single_wrapper(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  980. struct dp_tx_msdu_info_s *msdu_info,
  981. uint16_t peer_id, qdf_nbuf_t end_nbuf)
  982. {
  983. return dp_tx_send_msdu_single(vdev, nbuf, msdu_info, peer_id, NULL);
  984. }
  985. #endif
  986. #if defined(QCA_SUPPORT_WDS_EXTENDED)
  987. static bool
  988. dp_tx_is_wds_ast_override_en(struct dp_soc *soc,
  989. struct cdp_tx_exception_metadata *tx_exc_metadata)
  990. {
  991. if (soc->features.wds_ext_ast_override_enable &&
  992. tx_exc_metadata && tx_exc_metadata->is_wds_extended)
  993. return true;
  994. return false;
  995. }
  996. #else
  997. static bool
  998. dp_tx_is_wds_ast_override_en(struct dp_soc *soc,
  999. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1000. {
  1001. return false;
  1002. }
  1003. #endif
  1004. /**
  1005. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  1006. * @vdev: DP vdev handle
  1007. * @nbuf: skb
  1008. * @desc_pool_id: Descriptor pool ID
  1009. * @meta_data: Metadata to the fw
  1010. * @tx_exc_metadata: Handle that holds exception path metadata
  1011. * Allocate and prepare Tx descriptor with msdu information.
  1012. *
  1013. * Return: Pointer to Tx Descriptor on success,
  1014. * NULL on failure
  1015. */
  1016. static
  1017. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  1018. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  1019. struct dp_tx_msdu_info_s *msdu_info,
  1020. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1021. {
  1022. uint8_t align_pad;
  1023. uint8_t is_exception = 0;
  1024. uint8_t htt_hdr_size;
  1025. struct dp_tx_desc_s *tx_desc;
  1026. struct dp_pdev *pdev = vdev->pdev;
  1027. struct dp_soc *soc = pdev->soc;
  1028. if (dp_tx_limit_check(vdev, nbuf))
  1029. return NULL;
  1030. /* Allocate software Tx descriptor */
  1031. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  1032. if (qdf_unlikely(!tx_desc)) {
  1033. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  1034. DP_STATS_INC(vdev, tx_i.dropped.desc_na_exc_alloc_fail.num, 1);
  1035. return NULL;
  1036. }
  1037. dp_tx_outstanding_inc(pdev);
  1038. /* Initialize the SW tx descriptor */
  1039. tx_desc->nbuf = nbuf;
  1040. tx_desc->frm_type = dp_tx_frm_std;
  1041. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  1042. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  1043. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  1044. tx_desc->vdev_id = vdev->vdev_id;
  1045. tx_desc->pdev = pdev;
  1046. tx_desc->msdu_ext_desc = NULL;
  1047. tx_desc->pkt_offset = 0;
  1048. tx_desc->length = qdf_nbuf_headlen(nbuf);
  1049. tx_desc->shinfo_addr = skb_end_pointer(nbuf);
  1050. dp_tx_trace_pkt(soc, nbuf, tx_desc->id, vdev->vdev_id);
  1051. if (qdf_unlikely(vdev->multipass_en)) {
  1052. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  1053. goto failure;
  1054. }
  1055. /* Packets marked by upper layer (OS-IF) to be sent to FW */
  1056. if (dp_tx_is_nbuf_marked_exception(soc, nbuf))
  1057. is_exception = 1;
  1058. /* for BE chipsets if wds extension was enbled will not mark FW
  1059. * in desc will mark ast index based search for ast index.
  1060. */
  1061. if (dp_tx_is_wds_ast_override_en(soc, tx_exc_metadata))
  1062. return tx_desc;
  1063. /*
  1064. * For special modes (vdev_type == ocb or mesh), data frames should be
  1065. * transmitted using varying transmit parameters (tx spec) which include
  1066. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  1067. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  1068. * These frames are sent as exception packets to firmware.
  1069. *
  1070. * HW requirement is that metadata should always point to a
  1071. * 8-byte aligned address. So we add alignment pad to start of buffer.
  1072. * HTT Metadata should be ensured to be multiple of 8-bytes,
  1073. * to get 8-byte aligned start address along with align_pad added
  1074. *
  1075. * |-----------------------------|
  1076. * | |
  1077. * |-----------------------------| <-----Buffer Pointer Address given
  1078. * | | ^ in HW descriptor (aligned)
  1079. * | HTT Metadata | |
  1080. * | | |
  1081. * | | | Packet Offset given in descriptor
  1082. * | | |
  1083. * |-----------------------------| |
  1084. * | Alignment Pad | v
  1085. * |-----------------------------| <----- Actual buffer start address
  1086. * | SKB Data | (Unaligned)
  1087. * | |
  1088. * | |
  1089. * | |
  1090. * | |
  1091. * | |
  1092. * |-----------------------------|
  1093. */
  1094. if (qdf_unlikely((msdu_info->exception_fw)) ||
  1095. (vdev->opmode == wlan_op_mode_ocb) ||
  1096. (tx_exc_metadata &&
  1097. tx_exc_metadata->is_tx_sniffer)) {
  1098. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  1099. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  1100. DP_STATS_INC(vdev,
  1101. tx_i.dropped.headroom_insufficient, 1);
  1102. goto failure;
  1103. }
  1104. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  1105. dp_tx_err("qdf_nbuf_push_head failed");
  1106. goto failure;
  1107. }
  1108. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  1109. msdu_info);
  1110. if (htt_hdr_size == 0)
  1111. goto failure;
  1112. tx_desc->length = qdf_nbuf_headlen(nbuf);
  1113. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  1114. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1115. dp_tx_traffic_end_indication_set_desc_flag(tx_desc,
  1116. msdu_info);
  1117. is_exception = 1;
  1118. tx_desc->length -= tx_desc->pkt_offset;
  1119. }
  1120. #if !TQM_BYPASS_WAR
  1121. if (is_exception || tx_exc_metadata)
  1122. #endif
  1123. {
  1124. /* Temporary WAR due to TQM VP issues */
  1125. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1126. qdf_atomic_inc(&soc->num_tx_exception);
  1127. }
  1128. return tx_desc;
  1129. failure:
  1130. dp_tx_desc_release(tx_desc, desc_pool_id);
  1131. return NULL;
  1132. }
  1133. /**
  1134. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  1135. * @vdev: DP vdev handle
  1136. * @nbuf: skb
  1137. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  1138. * @desc_pool_id : Descriptor Pool ID
  1139. *
  1140. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  1141. * information. For frames with fragments, allocate and prepare
  1142. * an MSDU extension descriptor
  1143. *
  1144. * Return: Pointer to Tx Descriptor on success,
  1145. * NULL on failure
  1146. */
  1147. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  1148. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  1149. uint8_t desc_pool_id)
  1150. {
  1151. struct dp_tx_desc_s *tx_desc;
  1152. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  1153. struct dp_pdev *pdev = vdev->pdev;
  1154. struct dp_soc *soc = pdev->soc;
  1155. if (dp_tx_limit_check(vdev, nbuf))
  1156. return NULL;
  1157. /* Allocate software Tx descriptor */
  1158. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  1159. if (!tx_desc) {
  1160. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  1161. return NULL;
  1162. }
  1163. dp_tx_tso_seg_history_add(soc, msdu_info->u.tso_info.curr_seg,
  1164. nbuf, tx_desc->id, DP_TX_DESC_COOKIE);
  1165. dp_tx_outstanding_inc(pdev);
  1166. /* Initialize the SW tx descriptor */
  1167. tx_desc->nbuf = nbuf;
  1168. tx_desc->frm_type = msdu_info->frm_type;
  1169. tx_desc->tx_encap_type = vdev->tx_encap_type;
  1170. tx_desc->vdev_id = vdev->vdev_id;
  1171. tx_desc->pdev = pdev;
  1172. tx_desc->pkt_offset = 0;
  1173. dp_tx_trace_pkt(soc, nbuf, tx_desc->id, vdev->vdev_id);
  1174. /* Handle scattered frames - TSO/SG/ME */
  1175. /* Allocate and prepare an extension descriptor for scattered frames */
  1176. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  1177. if (!msdu_ext_desc) {
  1178. dp_tx_info("Tx Extension Descriptor Alloc Fail");
  1179. goto failure;
  1180. }
  1181. #if TQM_BYPASS_WAR
  1182. /* Temporary WAR due to TQM VP issues */
  1183. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1184. qdf_atomic_inc(&soc->num_tx_exception);
  1185. #endif
  1186. if (qdf_unlikely(msdu_info->exception_fw))
  1187. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1188. tx_desc->msdu_ext_desc = msdu_ext_desc;
  1189. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  1190. msdu_ext_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  1191. msdu_ext_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  1192. tx_desc->dma_addr = msdu_ext_desc->paddr;
  1193. if (msdu_ext_desc->flags & DP_TX_EXT_DESC_FLAG_METADATA_VALID)
  1194. tx_desc->length = HAL_TX_EXT_DESC_WITH_META_DATA;
  1195. else
  1196. tx_desc->length = HAL_TX_EXTENSION_DESC_LEN_BYTES;
  1197. return tx_desc;
  1198. failure:
  1199. dp_tx_desc_release(tx_desc, desc_pool_id);
  1200. return NULL;
  1201. }
  1202. /**
  1203. * dp_tx_prepare_raw() - Prepare RAW packet TX
  1204. * @vdev: DP vdev handle
  1205. * @nbuf: buffer pointer
  1206. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1207. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  1208. * descriptor
  1209. *
  1210. * Return:
  1211. */
  1212. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1213. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1214. {
  1215. qdf_nbuf_t curr_nbuf = NULL;
  1216. uint16_t total_len = 0;
  1217. qdf_dma_addr_t paddr;
  1218. int32_t i;
  1219. int32_t mapped_buf_num = 0;
  1220. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  1221. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1222. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  1223. /* Continue only if frames are of DATA type */
  1224. if (!DP_FRAME_IS_DATA(qos_wh)) {
  1225. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  1226. dp_tx_debug("Pkt. recd is of not data type");
  1227. goto error;
  1228. }
  1229. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  1230. if (vdev->raw_mode_war &&
  1231. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  1232. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  1233. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  1234. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  1235. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  1236. /*
  1237. * Number of nbuf's must not exceed the size of the frags
  1238. * array in seg_info.
  1239. */
  1240. if (i >= DP_TX_MAX_NUM_FRAGS) {
  1241. dp_err_rl("nbuf cnt exceeds the max number of segs");
  1242. DP_STATS_INC(vdev, tx_i.raw.num_frags_overflow_err, 1);
  1243. goto error;
  1244. }
  1245. if (QDF_STATUS_SUCCESS !=
  1246. qdf_nbuf_map_nbytes_single(vdev->osdev,
  1247. curr_nbuf,
  1248. QDF_DMA_TO_DEVICE,
  1249. curr_nbuf->len)) {
  1250. dp_tx_err("%s dma map error ", __func__);
  1251. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  1252. goto error;
  1253. }
  1254. /* Update the count of mapped nbuf's */
  1255. mapped_buf_num++;
  1256. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  1257. seg_info->frags[i].paddr_lo = paddr;
  1258. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  1259. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  1260. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  1261. total_len += qdf_nbuf_len(curr_nbuf);
  1262. }
  1263. seg_info->frag_cnt = i;
  1264. seg_info->total_len = total_len;
  1265. seg_info->next = NULL;
  1266. sg_info->curr_seg = seg_info;
  1267. msdu_info->frm_type = dp_tx_frm_raw;
  1268. msdu_info->num_seg = 1;
  1269. return nbuf;
  1270. error:
  1271. i = 0;
  1272. while (nbuf) {
  1273. curr_nbuf = nbuf;
  1274. if (i < mapped_buf_num) {
  1275. qdf_nbuf_unmap_nbytes_single(vdev->osdev, curr_nbuf,
  1276. QDF_DMA_TO_DEVICE,
  1277. curr_nbuf->len);
  1278. i++;
  1279. }
  1280. nbuf = qdf_nbuf_next(nbuf);
  1281. qdf_nbuf_free(curr_nbuf);
  1282. }
  1283. return NULL;
  1284. }
  1285. /**
  1286. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  1287. * @soc: DP soc handle
  1288. * @nbuf: Buffer pointer
  1289. *
  1290. * unmap the chain of nbufs that belong to this RAW frame.
  1291. *
  1292. * Return: None
  1293. */
  1294. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  1295. qdf_nbuf_t nbuf)
  1296. {
  1297. qdf_nbuf_t cur_nbuf = nbuf;
  1298. do {
  1299. qdf_nbuf_unmap_nbytes_single(soc->osdev, cur_nbuf,
  1300. QDF_DMA_TO_DEVICE,
  1301. cur_nbuf->len);
  1302. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  1303. } while (cur_nbuf);
  1304. }
  1305. #ifdef VDEV_PEER_PROTOCOL_COUNT
  1306. void dp_vdev_peer_stats_update_protocol_cnt_tx(struct dp_vdev *vdev_hdl,
  1307. qdf_nbuf_t nbuf)
  1308. {
  1309. qdf_nbuf_t nbuf_local;
  1310. struct dp_vdev *vdev_local = vdev_hdl;
  1311. do {
  1312. if (qdf_likely(!((vdev_local)->peer_protocol_count_track)))
  1313. break;
  1314. nbuf_local = nbuf;
  1315. if (qdf_unlikely(((vdev_local)->tx_encap_type) ==
  1316. htt_cmn_pkt_type_raw))
  1317. break;
  1318. else if (qdf_unlikely(qdf_nbuf_is_nonlinear((nbuf_local))))
  1319. break;
  1320. else if (qdf_nbuf_is_tso((nbuf_local)))
  1321. break;
  1322. dp_vdev_peer_stats_update_protocol_cnt((vdev_local),
  1323. (nbuf_local),
  1324. NULL, 1, 0);
  1325. } while (0);
  1326. }
  1327. #endif
  1328. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  1329. /**
  1330. * dp_tx_update_stats() - Update soc level tx stats
  1331. * @soc: DP soc handle
  1332. * @tx_desc: TX descriptor reference
  1333. * @ring_id: TCL ring id
  1334. *
  1335. * Returns: none
  1336. */
  1337. void dp_tx_update_stats(struct dp_soc *soc,
  1338. struct dp_tx_desc_s *tx_desc,
  1339. uint8_t ring_id)
  1340. {
  1341. uint32_t stats_len = dp_tx_get_pkt_len(tx_desc);
  1342. DP_STATS_INC_PKT(soc, tx.egress[ring_id], 1, stats_len);
  1343. }
  1344. int
  1345. dp_tx_attempt_coalescing(struct dp_soc *soc, struct dp_vdev *vdev,
  1346. struct dp_tx_desc_s *tx_desc,
  1347. uint8_t tid,
  1348. struct dp_tx_msdu_info_s *msdu_info,
  1349. uint8_t ring_id)
  1350. {
  1351. struct dp_swlm *swlm = &soc->swlm;
  1352. union swlm_data swlm_query_data;
  1353. struct dp_swlm_tcl_data tcl_data;
  1354. QDF_STATUS status;
  1355. int ret;
  1356. if (!swlm->is_enabled)
  1357. return msdu_info->skip_hp_update;
  1358. tcl_data.nbuf = tx_desc->nbuf;
  1359. tcl_data.tid = tid;
  1360. tcl_data.ring_id = ring_id;
  1361. tcl_data.pkt_len = dp_tx_get_pkt_len(tx_desc);
  1362. tcl_data.num_ll_connections = vdev->num_latency_critical_conn;
  1363. swlm_query_data.tcl_data = &tcl_data;
  1364. status = dp_swlm_tcl_pre_check(soc, &tcl_data);
  1365. if (QDF_IS_STATUS_ERROR(status)) {
  1366. dp_swlm_tcl_reset_session_data(soc, ring_id);
  1367. DP_STATS_INC(swlm, tcl[ring_id].coalesce_fail, 1);
  1368. return 0;
  1369. }
  1370. ret = dp_swlm_query_policy(soc, TCL_DATA, swlm_query_data);
  1371. if (ret) {
  1372. DP_STATS_INC(swlm, tcl[ring_id].coalesce_success, 1);
  1373. } else {
  1374. DP_STATS_INC(swlm, tcl[ring_id].coalesce_fail, 1);
  1375. }
  1376. return ret;
  1377. }
  1378. void
  1379. dp_tx_ring_access_end(struct dp_soc *soc, hal_ring_handle_t hal_ring_hdl,
  1380. int coalesce)
  1381. {
  1382. if (coalesce)
  1383. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1384. else
  1385. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1386. }
  1387. static inline void
  1388. dp_tx_is_hp_update_required(uint32_t i, struct dp_tx_msdu_info_s *msdu_info)
  1389. {
  1390. if (((i + 1) < msdu_info->num_seg))
  1391. msdu_info->skip_hp_update = 1;
  1392. else
  1393. msdu_info->skip_hp_update = 0;
  1394. }
  1395. static inline void
  1396. dp_flush_tcp_hp(struct dp_soc *soc, uint8_t ring_id)
  1397. {
  1398. hal_ring_handle_t hal_ring_hdl =
  1399. dp_tx_get_hal_ring_hdl(soc, ring_id);
  1400. if (dp_tx_hal_ring_access_start(soc, hal_ring_hdl)) {
  1401. dp_err("Fillmore: SRNG access start failed");
  1402. return;
  1403. }
  1404. dp_tx_ring_access_end_wrapper(soc, hal_ring_hdl, 0);
  1405. }
  1406. static inline void
  1407. dp_tx_check_and_flush_hp(struct dp_soc *soc,
  1408. QDF_STATUS status,
  1409. struct dp_tx_msdu_info_s *msdu_info)
  1410. {
  1411. if (QDF_IS_STATUS_ERROR(status) && !msdu_info->skip_hp_update) {
  1412. dp_flush_tcp_hp(soc,
  1413. (msdu_info->tx_queue.ring_id & DP_TX_QUEUE_MASK));
  1414. }
  1415. }
  1416. #else
  1417. static inline void
  1418. dp_tx_is_hp_update_required(uint32_t i, struct dp_tx_msdu_info_s *msdu_info)
  1419. {
  1420. }
  1421. static inline void
  1422. dp_tx_check_and_flush_hp(struct dp_soc *soc,
  1423. QDF_STATUS status,
  1424. struct dp_tx_msdu_info_s *msdu_info)
  1425. {
  1426. }
  1427. #endif
  1428. #ifdef FEATURE_RUNTIME_PM
  1429. static inline int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc)
  1430. {
  1431. int ret;
  1432. ret = qdf_atomic_read(&soc->rtpm_high_tput_flag) &&
  1433. (hif_rtpm_get_state() <= HIF_RTPM_STATE_ON);
  1434. return ret;
  1435. }
  1436. /**
  1437. * dp_tx_ring_access_end_wrapper() - Wrapper for ring access end
  1438. * @soc: Datapath soc handle
  1439. * @hal_ring_hdl: HAL ring handle
  1440. * @coalesce: Coalesce the current write or not
  1441. *
  1442. * Wrapper for HAL ring access end for data transmission for
  1443. * FEATURE_RUNTIME_PM
  1444. *
  1445. * Returns: none
  1446. */
  1447. void
  1448. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1449. hal_ring_handle_t hal_ring_hdl,
  1450. int coalesce)
  1451. {
  1452. int ret;
  1453. /*
  1454. * Avoid runtime get and put APIs under high throughput scenarios.
  1455. */
  1456. if (dp_get_rtpm_tput_policy_requirement(soc)) {
  1457. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1458. return;
  1459. }
  1460. ret = hif_rtpm_get(HIF_RTPM_GET_ASYNC, HIF_RTPM_ID_DP);
  1461. if (QDF_IS_STATUS_SUCCESS(ret)) {
  1462. if (hif_system_pm_state_check(soc->hif_handle)) {
  1463. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1464. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1465. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1466. } else {
  1467. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1468. }
  1469. hif_rtpm_put(HIF_RTPM_PUT_ASYNC, HIF_RTPM_ID_DP);
  1470. } else {
  1471. dp_runtime_get(soc);
  1472. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1473. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1474. qdf_atomic_inc(&soc->tx_pending_rtpm);
  1475. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1476. dp_runtime_put(soc);
  1477. }
  1478. }
  1479. #else
  1480. #ifdef DP_POWER_SAVE
  1481. void
  1482. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1483. hal_ring_handle_t hal_ring_hdl,
  1484. int coalesce)
  1485. {
  1486. if (hif_system_pm_state_check(soc->hif_handle)) {
  1487. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1488. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1489. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1490. } else {
  1491. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1492. }
  1493. }
  1494. #endif
  1495. static inline int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc)
  1496. {
  1497. return 0;
  1498. }
  1499. #endif
  1500. /**
  1501. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1502. * @vdev: DP vdev handle
  1503. * @nbuf: skb
  1504. *
  1505. * Extract the DSCP or PCP information from frame and map into TID value.
  1506. *
  1507. * Return: void
  1508. */
  1509. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1510. struct dp_tx_msdu_info_s *msdu_info)
  1511. {
  1512. uint8_t tos = 0, dscp_tid_override = 0;
  1513. uint8_t *hdr_ptr, *L3datap;
  1514. uint8_t is_mcast = 0;
  1515. qdf_ether_header_t *eh = NULL;
  1516. qdf_ethervlan_header_t *evh = NULL;
  1517. uint16_t ether_type;
  1518. qdf_llc_t *llcHdr;
  1519. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1520. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1521. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1522. eh = (qdf_ether_header_t *)nbuf->data;
  1523. hdr_ptr = (uint8_t *)(eh->ether_dhost);
  1524. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1525. } else {
  1526. qdf_dot3_qosframe_t *qos_wh =
  1527. (qdf_dot3_qosframe_t *) nbuf->data;
  1528. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1529. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1530. return;
  1531. }
  1532. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1533. ether_type = eh->ether_type;
  1534. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1535. /*
  1536. * Check if packet is dot3 or eth2 type.
  1537. */
  1538. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1539. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1540. sizeof(*llcHdr));
  1541. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1542. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1543. sizeof(*llcHdr);
  1544. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1545. + sizeof(*llcHdr) +
  1546. sizeof(qdf_net_vlanhdr_t));
  1547. } else {
  1548. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1549. sizeof(*llcHdr);
  1550. }
  1551. } else {
  1552. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1553. evh = (qdf_ethervlan_header_t *) eh;
  1554. ether_type = evh->ether_type;
  1555. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1556. }
  1557. }
  1558. /*
  1559. * Find priority from IP TOS DSCP field
  1560. */
  1561. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1562. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1563. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1564. /* Only for unicast frames */
  1565. if (!is_mcast) {
  1566. /* send it on VO queue */
  1567. msdu_info->tid = DP_VO_TID;
  1568. }
  1569. } else {
  1570. /*
  1571. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1572. * from TOS byte.
  1573. */
  1574. tos = ip->ip_tos;
  1575. dscp_tid_override = 1;
  1576. }
  1577. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1578. /* TODO
  1579. * use flowlabel
  1580. *igmpmld cases to be handled in phase 2
  1581. */
  1582. unsigned long ver_pri_flowlabel;
  1583. unsigned long pri;
  1584. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1585. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1586. DP_IPV6_PRIORITY_SHIFT;
  1587. tos = pri;
  1588. dscp_tid_override = 1;
  1589. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1590. msdu_info->tid = DP_VO_TID;
  1591. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1592. /* Only for unicast frames */
  1593. if (!is_mcast) {
  1594. /* send ucast arp on VO queue */
  1595. msdu_info->tid = DP_VO_TID;
  1596. }
  1597. }
  1598. /*
  1599. * Assign all MCAST packets to BE
  1600. */
  1601. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1602. if (is_mcast) {
  1603. tos = 0;
  1604. dscp_tid_override = 1;
  1605. }
  1606. }
  1607. if (dscp_tid_override == 1) {
  1608. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1609. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1610. }
  1611. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1612. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1613. return;
  1614. }
  1615. /**
  1616. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1617. * @vdev: DP vdev handle
  1618. * @nbuf: skb
  1619. *
  1620. * Software based TID classification is required when more than 2 DSCP-TID
  1621. * mapping tables are needed.
  1622. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1623. *
  1624. * Return: void
  1625. */
  1626. static inline void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1627. struct dp_tx_msdu_info_s *msdu_info)
  1628. {
  1629. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1630. /*
  1631. * skip_sw_tid_classification flag will set in below cases-
  1632. * 1. vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map
  1633. * 2. hlos_tid_override enabled for vdev
  1634. * 3. mesh mode enabled for vdev
  1635. */
  1636. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1637. /* Update tid in msdu_info from skb priority */
  1638. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1639. & DP_TXRX_HLOS_TID_OVERRIDE_ENABLED)) {
  1640. uint32_t tid = qdf_nbuf_get_priority(nbuf);
  1641. if (tid == DP_TX_INVALID_QOS_TAG)
  1642. return;
  1643. msdu_info->tid = tid;
  1644. return;
  1645. }
  1646. return;
  1647. }
  1648. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1649. }
  1650. #ifdef FEATURE_WLAN_TDLS
  1651. /**
  1652. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1653. * @soc: datapath SOC
  1654. * @vdev: datapath vdev
  1655. * @tx_desc: TX descriptor
  1656. *
  1657. * Return: None
  1658. */
  1659. static void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1660. struct dp_vdev *vdev,
  1661. struct dp_tx_desc_s *tx_desc)
  1662. {
  1663. if (vdev) {
  1664. if (vdev->is_tdls_frame) {
  1665. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1666. vdev->is_tdls_frame = false;
  1667. }
  1668. }
  1669. }
  1670. static uint8_t dp_htt_tx_comp_get_status(struct dp_soc *soc, char *htt_desc)
  1671. {
  1672. uint8_t tx_status = HTT_TX_FW2WBM_TX_STATUS_MAX;
  1673. switch (soc->arch_id) {
  1674. case CDP_ARCH_TYPE_LI:
  1675. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  1676. break;
  1677. case CDP_ARCH_TYPE_BE:
  1678. tx_status = HTT_TX_WBM_COMPLETION_V3_TX_STATUS_GET(htt_desc[0]);
  1679. break;
  1680. default:
  1681. dp_err("Incorrect CDP_ARCH %d", soc->arch_id);
  1682. QDF_BUG(0);
  1683. }
  1684. return tx_status;
  1685. }
  1686. /**
  1687. * dp_non_std_htt_tx_comp_free_buff() - Free the non std tx packet buffer
  1688. * @soc: dp_soc handle
  1689. * @tx_desc: TX descriptor
  1690. * @vdev: datapath vdev handle
  1691. *
  1692. * Return: None
  1693. */
  1694. static void dp_non_std_htt_tx_comp_free_buff(struct dp_soc *soc,
  1695. struct dp_tx_desc_s *tx_desc)
  1696. {
  1697. uint8_t tx_status = 0;
  1698. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  1699. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1700. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1701. DP_MOD_ID_TDLS);
  1702. if (qdf_unlikely(!vdev)) {
  1703. dp_err_rl("vdev is null!");
  1704. goto error;
  1705. }
  1706. hal_tx_comp_get_htt_desc(&tx_desc->comp, htt_tx_status);
  1707. tx_status = dp_htt_tx_comp_get_status(soc, htt_tx_status);
  1708. dp_debug("vdev_id: %d tx_status: %d", tx_desc->vdev_id, tx_status);
  1709. if (vdev->tx_non_std_data_callback.func) {
  1710. qdf_nbuf_set_next(nbuf, NULL);
  1711. vdev->tx_non_std_data_callback.func(
  1712. vdev->tx_non_std_data_callback.ctxt,
  1713. nbuf, tx_status);
  1714. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1715. return;
  1716. } else {
  1717. dp_err_rl("callback func is null");
  1718. }
  1719. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1720. error:
  1721. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1722. qdf_nbuf_free(nbuf);
  1723. }
  1724. /**
  1725. * dp_tx_msdu_single_map() - do nbuf map
  1726. * @vdev: DP vdev handle
  1727. * @tx_desc: DP TX descriptor pointer
  1728. * @nbuf: skb pointer
  1729. *
  1730. * For TDLS frame, use qdf_nbuf_map_single() to align with the unmap
  1731. * operation done in other component.
  1732. *
  1733. * Return: QDF_STATUS
  1734. */
  1735. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1736. struct dp_tx_desc_s *tx_desc,
  1737. qdf_nbuf_t nbuf)
  1738. {
  1739. if (qdf_likely(!(tx_desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)))
  1740. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1741. nbuf,
  1742. QDF_DMA_TO_DEVICE,
  1743. nbuf->len);
  1744. else
  1745. return qdf_nbuf_map_single(vdev->osdev, nbuf,
  1746. QDF_DMA_TO_DEVICE);
  1747. }
  1748. #else
  1749. static inline void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1750. struct dp_vdev *vdev,
  1751. struct dp_tx_desc_s *tx_desc)
  1752. {
  1753. }
  1754. static inline void dp_non_std_htt_tx_comp_free_buff(struct dp_soc *soc,
  1755. struct dp_tx_desc_s *tx_desc)
  1756. {
  1757. }
  1758. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1759. struct dp_tx_desc_s *tx_desc,
  1760. qdf_nbuf_t nbuf)
  1761. {
  1762. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1763. nbuf,
  1764. QDF_DMA_TO_DEVICE,
  1765. nbuf->len);
  1766. }
  1767. #endif
  1768. static inline
  1769. qdf_dma_addr_t dp_tx_nbuf_map_regular(struct dp_vdev *vdev,
  1770. struct dp_tx_desc_s *tx_desc,
  1771. qdf_nbuf_t nbuf)
  1772. {
  1773. QDF_STATUS ret = QDF_STATUS_E_FAILURE;
  1774. ret = dp_tx_msdu_single_map(vdev, tx_desc, nbuf);
  1775. if (qdf_unlikely(QDF_IS_STATUS_ERROR(ret)))
  1776. return 0;
  1777. return qdf_nbuf_mapped_paddr_get(nbuf);
  1778. }
  1779. static inline
  1780. void dp_tx_nbuf_unmap_regular(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1781. {
  1782. qdf_nbuf_unmap_nbytes_single_paddr(soc->osdev,
  1783. desc->nbuf,
  1784. desc->dma_addr,
  1785. QDF_DMA_TO_DEVICE,
  1786. desc->length);
  1787. }
  1788. #ifdef QCA_DP_TX_RMNET_OPTIMIZATION
  1789. static inline bool
  1790. is_nbuf_frm_rmnet(qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info)
  1791. {
  1792. struct net_device *ingress_dev;
  1793. skb_frag_t *frag;
  1794. uint16_t buf_len = 0;
  1795. uint16_t linear_data_len = 0;
  1796. uint8_t *payload_addr = NULL;
  1797. ingress_dev = dev_get_by_index(dev_net(nbuf->dev), nbuf->skb_iif);
  1798. if ((ingress_dev->priv_flags & IFF_PHONY_HEADROOM)) {
  1799. dev_put(ingress_dev);
  1800. frag = &(skb_shinfo(nbuf)->frags[0]);
  1801. buf_len = skb_frag_size(frag);
  1802. payload_addr = (uint8_t *)skb_frag_address(frag);
  1803. linear_data_len = skb_headlen(nbuf);
  1804. buf_len += linear_data_len;
  1805. payload_addr = payload_addr - linear_data_len;
  1806. memcpy(payload_addr, nbuf->data, linear_data_len);
  1807. msdu_info->frm_type = dp_tx_frm_rmnet;
  1808. msdu_info->buf_len = buf_len;
  1809. msdu_info->payload_addr = payload_addr;
  1810. return true;
  1811. }
  1812. dev_put(ingress_dev);
  1813. return false;
  1814. }
  1815. static inline
  1816. qdf_dma_addr_t dp_tx_rmnet_nbuf_map(struct dp_tx_msdu_info_s *msdu_info,
  1817. struct dp_tx_desc_s *tx_desc)
  1818. {
  1819. qdf_dma_addr_t paddr;
  1820. paddr = (qdf_dma_addr_t)qdf_mem_virt_to_phys(msdu_info->payload_addr);
  1821. tx_desc->length = msdu_info->buf_len;
  1822. qdf_nbuf_dma_clean_range((void *)msdu_info->payload_addr,
  1823. (void *)(msdu_info->payload_addr +
  1824. msdu_info->buf_len));
  1825. tx_desc->flags |= DP_TX_DESC_FLAG_RMNET;
  1826. return paddr;
  1827. }
  1828. #else
  1829. static inline bool
  1830. is_nbuf_frm_rmnet(qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info)
  1831. {
  1832. return false;
  1833. }
  1834. static inline
  1835. qdf_dma_addr_t dp_tx_rmnet_nbuf_map(struct dp_tx_msdu_info_s *msdu_info,
  1836. struct dp_tx_desc_s *tx_desc)
  1837. {
  1838. return 0;
  1839. }
  1840. #endif
  1841. #if defined(QCA_DP_TX_NBUF_NO_MAP_UNMAP) && !defined(BUILD_X86)
  1842. static inline
  1843. qdf_dma_addr_t dp_tx_nbuf_map(struct dp_vdev *vdev,
  1844. struct dp_tx_desc_s *tx_desc,
  1845. qdf_nbuf_t nbuf)
  1846. {
  1847. if (qdf_likely(tx_desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  1848. qdf_nbuf_dma_clean_range((void *)nbuf->data,
  1849. (void *)(nbuf->data + nbuf->len));
  1850. return (qdf_dma_addr_t)qdf_mem_virt_to_phys(nbuf->data);
  1851. } else {
  1852. return dp_tx_nbuf_map_regular(vdev, tx_desc, nbuf);
  1853. }
  1854. }
  1855. static inline
  1856. void dp_tx_nbuf_unmap(struct dp_soc *soc,
  1857. struct dp_tx_desc_s *desc)
  1858. {
  1859. if (qdf_unlikely(!(desc->flags &
  1860. (DP_TX_DESC_FLAG_SIMPLE | DP_TX_DESC_FLAG_RMNET))))
  1861. return dp_tx_nbuf_unmap_regular(soc, desc);
  1862. }
  1863. #else
  1864. static inline
  1865. qdf_dma_addr_t dp_tx_nbuf_map(struct dp_vdev *vdev,
  1866. struct dp_tx_desc_s *tx_desc,
  1867. qdf_nbuf_t nbuf)
  1868. {
  1869. return dp_tx_nbuf_map_regular(vdev, tx_desc, nbuf);
  1870. }
  1871. static inline
  1872. void dp_tx_nbuf_unmap(struct dp_soc *soc,
  1873. struct dp_tx_desc_s *desc)
  1874. {
  1875. return dp_tx_nbuf_unmap_regular(soc, desc);
  1876. }
  1877. #endif
  1878. #if defined(WLAN_TX_PKT_CAPTURE_ENH) || defined(FEATURE_PERPKT_INFO)
  1879. static inline
  1880. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1881. {
  1882. dp_tx_nbuf_unmap(soc, desc);
  1883. desc->flags |= DP_TX_DESC_FLAG_UNMAP_DONE;
  1884. }
  1885. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1886. {
  1887. if (qdf_likely(!(desc->flags & DP_TX_DESC_FLAG_UNMAP_DONE)))
  1888. dp_tx_nbuf_unmap(soc, desc);
  1889. }
  1890. #else
  1891. static inline
  1892. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1893. {
  1894. }
  1895. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1896. {
  1897. dp_tx_nbuf_unmap(soc, desc);
  1898. }
  1899. #endif
  1900. #ifdef MESH_MODE_SUPPORT
  1901. /**
  1902. * dp_tx_update_mesh_flags() - Update descriptor flags for mesh VAP
  1903. * @soc: datapath SOC
  1904. * @vdev: datapath vdev
  1905. * @tx_desc: TX descriptor
  1906. *
  1907. * Return: None
  1908. */
  1909. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1910. struct dp_vdev *vdev,
  1911. struct dp_tx_desc_s *tx_desc)
  1912. {
  1913. if (qdf_unlikely(vdev->mesh_vdev))
  1914. tx_desc->flags |= DP_TX_DESC_FLAG_MESH_MODE;
  1915. }
  1916. /**
  1917. * dp_mesh_tx_comp_free_buff() - Free the mesh tx packet buffer
  1918. * @soc: dp_soc handle
  1919. * @tx_desc: TX descriptor
  1920. * @delayed_free: delay the nbuf free
  1921. *
  1922. * Return: nbuf to be freed late
  1923. */
  1924. static inline qdf_nbuf_t dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1925. struct dp_tx_desc_s *tx_desc,
  1926. bool delayed_free)
  1927. {
  1928. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1929. struct dp_vdev *vdev = NULL;
  1930. vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id, DP_MOD_ID_MESH);
  1931. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  1932. if (vdev)
  1933. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  1934. if (delayed_free)
  1935. return nbuf;
  1936. qdf_nbuf_free(nbuf);
  1937. } else {
  1938. if (vdev && vdev->osif_tx_free_ext) {
  1939. vdev->osif_tx_free_ext((nbuf));
  1940. } else {
  1941. if (delayed_free)
  1942. return nbuf;
  1943. qdf_nbuf_free(nbuf);
  1944. }
  1945. }
  1946. if (vdev)
  1947. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  1948. return NULL;
  1949. }
  1950. #else
  1951. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1952. struct dp_vdev *vdev,
  1953. struct dp_tx_desc_s *tx_desc)
  1954. {
  1955. }
  1956. static inline qdf_nbuf_t dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1957. struct dp_tx_desc_s *tx_desc,
  1958. bool delayed_free)
  1959. {
  1960. return NULL;
  1961. }
  1962. #endif
  1963. /**
  1964. * dp_tx_frame_is_drop() - checks if the packet is loopback
  1965. * @vdev: DP vdev handle
  1966. * @nbuf: skb
  1967. *
  1968. * Return: 1 if frame needs to be dropped else 0
  1969. */
  1970. int dp_tx_frame_is_drop(struct dp_vdev *vdev, uint8_t *srcmac, uint8_t *dstmac)
  1971. {
  1972. struct dp_pdev *pdev = NULL;
  1973. struct dp_ast_entry *src_ast_entry = NULL;
  1974. struct dp_ast_entry *dst_ast_entry = NULL;
  1975. struct dp_soc *soc = NULL;
  1976. qdf_assert(vdev);
  1977. pdev = vdev->pdev;
  1978. qdf_assert(pdev);
  1979. soc = pdev->soc;
  1980. dst_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1981. (soc, dstmac, vdev->pdev->pdev_id);
  1982. src_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1983. (soc, srcmac, vdev->pdev->pdev_id);
  1984. if (dst_ast_entry && src_ast_entry) {
  1985. if (dst_ast_entry->peer_id ==
  1986. src_ast_entry->peer_id)
  1987. return 1;
  1988. }
  1989. return 0;
  1990. }
  1991. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  1992. defined(WLAN_MCAST_MLO)
  1993. /* MLO peer id for reinject*/
  1994. #define DP_MLO_MCAST_REINJECT_PEER_ID 0XFFFD
  1995. /* MLO vdev id inc offset */
  1996. #define DP_MLO_VDEV_ID_OFFSET 0x80
  1997. static inline void
  1998. dp_tx_bypass_reinjection(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  1999. {
  2000. if (!(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)) {
  2001. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  2002. qdf_atomic_inc(&soc->num_tx_exception);
  2003. }
  2004. }
  2005. static inline void
  2006. dp_tx_update_mcast_param(uint16_t peer_id,
  2007. uint16_t *htt_tcl_metadata,
  2008. struct dp_vdev *vdev,
  2009. struct dp_tx_msdu_info_s *msdu_info)
  2010. {
  2011. if (peer_id == DP_MLO_MCAST_REINJECT_PEER_ID) {
  2012. *htt_tcl_metadata = 0;
  2013. DP_TX_TCL_METADATA_TYPE_SET(
  2014. *htt_tcl_metadata,
  2015. HTT_TCL_METADATA_V2_TYPE_GLOBAL_SEQ_BASED);
  2016. HTT_TX_TCL_METADATA_GLBL_SEQ_NO_SET(*htt_tcl_metadata,
  2017. msdu_info->gsn);
  2018. msdu_info->vdev_id = vdev->vdev_id + DP_MLO_VDEV_ID_OFFSET;
  2019. if (qdf_unlikely(vdev->nawds_enabled))
  2020. HTT_TX_TCL_METADATA_GLBL_SEQ_HOST_INSPECTED_SET(
  2021. *htt_tcl_metadata, 1);
  2022. } else {
  2023. msdu_info->vdev_id = vdev->vdev_id;
  2024. }
  2025. }
  2026. #else
  2027. static inline void
  2028. dp_tx_bypass_reinjection(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2029. {
  2030. }
  2031. static inline void
  2032. dp_tx_update_mcast_param(uint16_t peer_id,
  2033. uint16_t *htt_tcl_metadata,
  2034. struct dp_vdev *vdev,
  2035. struct dp_tx_msdu_info_s *msdu_info)
  2036. {
  2037. }
  2038. #endif
  2039. #ifdef DP_TX_SW_DROP_STATS_INC
  2040. static void tx_sw_drop_stats_inc(struct dp_pdev *pdev,
  2041. qdf_nbuf_t nbuf,
  2042. enum cdp_tx_sw_drop drop_code)
  2043. {
  2044. /* EAPOL Drop stats */
  2045. if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf)) {
  2046. switch (drop_code) {
  2047. case TX_DESC_ERR:
  2048. DP_STATS_INC(pdev, eap_drop_stats.tx_desc_err, 1);
  2049. break;
  2050. case TX_HAL_RING_ACCESS_ERR:
  2051. DP_STATS_INC(pdev,
  2052. eap_drop_stats.tx_hal_ring_access_err, 1);
  2053. break;
  2054. case TX_DMA_MAP_ERR:
  2055. DP_STATS_INC(pdev, eap_drop_stats.tx_dma_map_err, 1);
  2056. break;
  2057. case TX_HW_ENQUEUE:
  2058. DP_STATS_INC(pdev, eap_drop_stats.tx_hw_enqueue, 1);
  2059. break;
  2060. case TX_SW_ENQUEUE:
  2061. DP_STATS_INC(pdev, eap_drop_stats.tx_sw_enqueue, 1);
  2062. break;
  2063. default:
  2064. dp_info_rl("Invalid eapol_drop code: %d", drop_code);
  2065. break;
  2066. }
  2067. }
  2068. }
  2069. #else
  2070. static void tx_sw_drop_stats_inc(struct dp_pdev *pdev,
  2071. qdf_nbuf_t nbuf,
  2072. enum cdp_tx_sw_drop drop_code)
  2073. {
  2074. }
  2075. #endif
  2076. /**
  2077. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  2078. * @vdev: DP vdev handle
  2079. * @nbuf: skb
  2080. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  2081. * @meta_data: Metadata to the fw
  2082. * @tx_q: Tx queue to be used for this Tx frame
  2083. * @peer_id: peer_id of the peer in case of NAWDS frames
  2084. * @tx_exc_metadata: Handle that holds exception path metadata
  2085. *
  2086. * Return: NULL on success,
  2087. * nbuf when it fails to send
  2088. */
  2089. qdf_nbuf_t
  2090. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2091. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  2092. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2093. {
  2094. struct dp_pdev *pdev = vdev->pdev;
  2095. struct dp_soc *soc = pdev->soc;
  2096. struct dp_tx_desc_s *tx_desc;
  2097. QDF_STATUS status;
  2098. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  2099. uint16_t htt_tcl_metadata = 0;
  2100. enum cdp_tx_sw_drop drop_code = TX_MAX_DROP;
  2101. uint8_t tid = msdu_info->tid;
  2102. struct cdp_tid_tx_stats *tid_stats = NULL;
  2103. qdf_dma_addr_t paddr;
  2104. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  2105. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  2106. msdu_info, tx_exc_metadata);
  2107. if (!tx_desc) {
  2108. dp_err_rl("Tx_desc prepare Fail vdev_id %d vdev %pK queue %d",
  2109. vdev->vdev_id, vdev, tx_q->desc_pool_id);
  2110. drop_code = TX_DESC_ERR;
  2111. goto fail_return;
  2112. }
  2113. dp_tx_update_tdls_flags(soc, vdev, tx_desc);
  2114. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  2115. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2116. DP_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  2117. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  2118. DP_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  2119. DP_TCL_METADATA_TYPE_PEER_BASED);
  2120. DP_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  2121. peer_id);
  2122. dp_tx_bypass_reinjection(soc, tx_desc);
  2123. } else
  2124. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2125. if (msdu_info->exception_fw)
  2126. DP_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  2127. dp_tx_desc_update_fast_comp_flag(soc, tx_desc,
  2128. !pdev->enhanced_stats_en);
  2129. dp_tx_update_mesh_flags(soc, vdev, tx_desc);
  2130. if (qdf_unlikely(msdu_info->frm_type == dp_tx_frm_rmnet))
  2131. paddr = dp_tx_rmnet_nbuf_map(msdu_info, tx_desc);
  2132. else
  2133. paddr = dp_tx_nbuf_map(vdev, tx_desc, nbuf);
  2134. if (!paddr) {
  2135. /* Handle failure */
  2136. dp_err("qdf_nbuf_map failed");
  2137. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  2138. drop_code = TX_DMA_MAP_ERR;
  2139. goto release_desc;
  2140. }
  2141. tx_desc->dma_addr = paddr;
  2142. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  2143. tx_desc->id, DP_TX_DESC_MAP);
  2144. dp_tx_update_mcast_param(peer_id, &htt_tcl_metadata, vdev, msdu_info);
  2145. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  2146. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  2147. htt_tcl_metadata,
  2148. tx_exc_metadata, msdu_info);
  2149. if (status != QDF_STATUS_SUCCESS) {
  2150. dp_tx_err_rl("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  2151. tx_desc, tx_q->ring_id);
  2152. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  2153. tx_desc->id, DP_TX_DESC_UNMAP);
  2154. dp_tx_nbuf_unmap(soc, tx_desc);
  2155. drop_code = TX_HW_ENQUEUE;
  2156. goto release_desc;
  2157. }
  2158. tx_sw_drop_stats_inc(pdev, nbuf, drop_code);
  2159. return NULL;
  2160. release_desc:
  2161. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2162. fail_return:
  2163. dp_tx_get_tid(vdev, nbuf, msdu_info);
  2164. tx_sw_drop_stats_inc(pdev, nbuf, drop_code);
  2165. tid_stats = &pdev->stats.tid_stats.
  2166. tid_tx_stats[tx_q->ring_id][tid];
  2167. tid_stats->swdrop_cnt[drop_code]++;
  2168. return nbuf;
  2169. }
  2170. /**
  2171. * dp_tdls_tx_comp_free_buff() - Free non std buffer when TDLS flag is set
  2172. * @soc: Soc handle
  2173. * @desc: software Tx descriptor to be processed
  2174. *
  2175. * Return: 0 if Success
  2176. */
  2177. #ifdef FEATURE_WLAN_TDLS
  2178. static inline int
  2179. dp_tdls_tx_comp_free_buff(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  2180. {
  2181. /* If it is TDLS mgmt, don't unmap or free the frame */
  2182. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME) {
  2183. dp_non_std_htt_tx_comp_free_buff(soc, desc);
  2184. return 0;
  2185. }
  2186. return 1;
  2187. }
  2188. #else
  2189. static inline int
  2190. dp_tdls_tx_comp_free_buff(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  2191. {
  2192. return 1;
  2193. }
  2194. #endif
  2195. /**
  2196. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2197. * @soc: Soc handle
  2198. * @desc: software Tx descriptor to be processed
  2199. * @delayed_free: defer freeing of nbuf
  2200. *
  2201. * Return: nbuf to be freed later
  2202. */
  2203. qdf_nbuf_t dp_tx_comp_free_buf(struct dp_soc *soc, struct dp_tx_desc_s *desc,
  2204. bool delayed_free)
  2205. {
  2206. qdf_nbuf_t nbuf = desc->nbuf;
  2207. enum dp_tx_event_type type = dp_tx_get_event_type(desc->flags);
  2208. /* nbuf already freed in vdev detach path */
  2209. if (!nbuf)
  2210. return NULL;
  2211. if (!dp_tdls_tx_comp_free_buff(soc, desc))
  2212. return NULL;
  2213. /* 0 : MSDU buffer, 1 : MLE */
  2214. if (desc->msdu_ext_desc) {
  2215. /* TSO free */
  2216. if (hal_tx_ext_desc_get_tso_enable(
  2217. desc->msdu_ext_desc->vaddr)) {
  2218. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  2219. desc->id, DP_TX_COMP_MSDU_EXT);
  2220. dp_tx_tso_seg_history_add(soc,
  2221. desc->msdu_ext_desc->tso_desc,
  2222. desc->nbuf, desc->id, type);
  2223. /* unmap eash TSO seg before free the nbuf */
  2224. dp_tx_tso_unmap_segment(soc,
  2225. desc->msdu_ext_desc->tso_desc,
  2226. desc->msdu_ext_desc->
  2227. tso_num_desc);
  2228. goto nbuf_free;
  2229. }
  2230. if (qdf_unlikely(desc->frm_type == dp_tx_frm_sg)) {
  2231. void *msdu_ext_desc = desc->msdu_ext_desc->vaddr;
  2232. qdf_dma_addr_t iova;
  2233. uint32_t frag_len;
  2234. uint32_t i;
  2235. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf,
  2236. QDF_DMA_TO_DEVICE,
  2237. qdf_nbuf_headlen(nbuf));
  2238. for (i = 1; i < DP_TX_MAX_NUM_FRAGS; i++) {
  2239. hal_tx_ext_desc_get_frag_info(msdu_ext_desc, i,
  2240. &iova,
  2241. &frag_len);
  2242. if (!iova || !frag_len)
  2243. break;
  2244. qdf_mem_unmap_page(soc->osdev, iova, frag_len,
  2245. QDF_DMA_TO_DEVICE);
  2246. }
  2247. goto nbuf_free;
  2248. }
  2249. }
  2250. /* If it's ME frame, dont unmap the cloned nbuf's */
  2251. if ((desc->flags & DP_TX_DESC_FLAG_ME) && qdf_nbuf_is_cloned(nbuf))
  2252. goto nbuf_free;
  2253. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf, desc->id, type);
  2254. dp_tx_unmap(soc, desc);
  2255. if (desc->flags & DP_TX_DESC_FLAG_MESH_MODE)
  2256. return dp_mesh_tx_comp_free_buff(soc, desc, delayed_free);
  2257. if (dp_tx_traffic_end_indication_enq_ind_pkt(soc, desc, nbuf))
  2258. return NULL;
  2259. nbuf_free:
  2260. if (delayed_free)
  2261. return nbuf;
  2262. qdf_nbuf_free(nbuf);
  2263. return NULL;
  2264. }
  2265. /**
  2266. * dp_tx_sg_unmap_buf() - Unmap scatter gather fragments
  2267. * @soc: DP soc handle
  2268. * @nbuf: skb
  2269. * @msdu_info: MSDU info
  2270. *
  2271. * Return: None
  2272. */
  2273. static inline void
  2274. dp_tx_sg_unmap_buf(struct dp_soc *soc, qdf_nbuf_t nbuf,
  2275. struct dp_tx_msdu_info_s *msdu_info)
  2276. {
  2277. uint32_t cur_idx;
  2278. struct dp_tx_seg_info_s *seg = msdu_info->u.sg_info.curr_seg;
  2279. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE,
  2280. qdf_nbuf_headlen(nbuf));
  2281. for (cur_idx = 1; cur_idx < seg->frag_cnt; cur_idx++)
  2282. qdf_mem_unmap_page(soc->osdev, (qdf_dma_addr_t)
  2283. (seg->frags[cur_idx].paddr_lo | ((uint64_t)
  2284. seg->frags[cur_idx].paddr_hi) << 32),
  2285. seg->frags[cur_idx].len,
  2286. QDF_DMA_TO_DEVICE);
  2287. }
  2288. /**
  2289. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  2290. * @vdev: DP vdev handle
  2291. * @nbuf: skb
  2292. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  2293. *
  2294. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  2295. *
  2296. * Return: NULL on success,
  2297. * nbuf when it fails to send
  2298. */
  2299. #if QDF_LOCK_STATS
  2300. noinline
  2301. #else
  2302. #endif
  2303. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2304. struct dp_tx_msdu_info_s *msdu_info)
  2305. {
  2306. uint32_t i;
  2307. struct dp_pdev *pdev = vdev->pdev;
  2308. struct dp_soc *soc = pdev->soc;
  2309. struct dp_tx_desc_s *tx_desc;
  2310. bool is_cce_classified = false;
  2311. QDF_STATUS status;
  2312. uint16_t htt_tcl_metadata = 0;
  2313. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  2314. struct cdp_tid_tx_stats *tid_stats = NULL;
  2315. uint8_t prep_desc_fail = 0, hw_enq_fail = 0;
  2316. if (msdu_info->frm_type == dp_tx_frm_me)
  2317. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2318. i = 0;
  2319. /* Print statement to track i and num_seg */
  2320. /*
  2321. * For each segment (maps to 1 MSDU) , prepare software and hardware
  2322. * descriptors using information in msdu_info
  2323. */
  2324. while (i < msdu_info->num_seg) {
  2325. /*
  2326. * Setup Tx descriptor for an MSDU, and MSDU extension
  2327. * descriptor
  2328. */
  2329. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  2330. tx_q->desc_pool_id);
  2331. if (!tx_desc) {
  2332. if (msdu_info->frm_type == dp_tx_frm_me) {
  2333. prep_desc_fail++;
  2334. dp_tx_me_free_buf(pdev,
  2335. (void *)(msdu_info->u.sg_info
  2336. .curr_seg->frags[0].vaddr));
  2337. if (prep_desc_fail == msdu_info->num_seg) {
  2338. /*
  2339. * Unmap is needed only if descriptor
  2340. * preparation failed for all segments.
  2341. */
  2342. qdf_nbuf_unmap(soc->osdev,
  2343. msdu_info->u.sg_info.
  2344. curr_seg->nbuf,
  2345. QDF_DMA_TO_DEVICE);
  2346. }
  2347. /*
  2348. * Free the nbuf for the current segment
  2349. * and make it point to the next in the list.
  2350. * For me, there are as many segments as there
  2351. * are no of clients.
  2352. */
  2353. qdf_nbuf_free(msdu_info->u.sg_info
  2354. .curr_seg->nbuf);
  2355. if (msdu_info->u.sg_info.curr_seg->next) {
  2356. msdu_info->u.sg_info.curr_seg =
  2357. msdu_info->u.sg_info
  2358. .curr_seg->next;
  2359. nbuf = msdu_info->u.sg_info
  2360. .curr_seg->nbuf;
  2361. }
  2362. i++;
  2363. continue;
  2364. }
  2365. if (msdu_info->frm_type == dp_tx_frm_tso) {
  2366. dp_tx_tso_seg_history_add(
  2367. soc,
  2368. msdu_info->u.tso_info.curr_seg,
  2369. nbuf, 0, DP_TX_DESC_UNMAP);
  2370. dp_tx_tso_unmap_segment(soc,
  2371. msdu_info->u.tso_info.
  2372. curr_seg,
  2373. msdu_info->u.tso_info.
  2374. tso_num_seg_list);
  2375. if (msdu_info->u.tso_info.curr_seg->next) {
  2376. msdu_info->u.tso_info.curr_seg =
  2377. msdu_info->u.tso_info.curr_seg->next;
  2378. i++;
  2379. continue;
  2380. }
  2381. }
  2382. if (msdu_info->frm_type == dp_tx_frm_sg)
  2383. dp_tx_sg_unmap_buf(soc, nbuf, msdu_info);
  2384. goto done;
  2385. }
  2386. if (msdu_info->frm_type == dp_tx_frm_me) {
  2387. tx_desc->msdu_ext_desc->me_buffer =
  2388. (struct dp_tx_me_buf_t *)msdu_info->
  2389. u.sg_info.curr_seg->frags[0].vaddr;
  2390. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  2391. }
  2392. if (is_cce_classified)
  2393. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  2394. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2395. if (msdu_info->exception_fw) {
  2396. DP_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  2397. }
  2398. dp_tx_is_hp_update_required(i, msdu_info);
  2399. /*
  2400. * For frames with multiple segments (TSO, ME), jump to next
  2401. * segment.
  2402. */
  2403. if (msdu_info->frm_type == dp_tx_frm_tso) {
  2404. if (msdu_info->u.tso_info.curr_seg->next) {
  2405. msdu_info->u.tso_info.curr_seg =
  2406. msdu_info->u.tso_info.curr_seg->next;
  2407. /*
  2408. * If this is a jumbo nbuf, then increment the
  2409. * number of nbuf users for each additional
  2410. * segment of the msdu. This will ensure that
  2411. * the skb is freed only after receiving tx
  2412. * completion for all segments of an nbuf
  2413. */
  2414. qdf_nbuf_inc_users(nbuf);
  2415. /* Check with MCL if this is needed */
  2416. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf;
  2417. */
  2418. }
  2419. }
  2420. dp_tx_update_mcast_param(DP_INVALID_PEER,
  2421. &htt_tcl_metadata,
  2422. vdev,
  2423. msdu_info);
  2424. /*
  2425. * Enqueue the Tx MSDU descriptor to HW for transmit
  2426. */
  2427. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  2428. htt_tcl_metadata,
  2429. NULL, msdu_info);
  2430. dp_tx_check_and_flush_hp(soc, status, msdu_info);
  2431. if (status != QDF_STATUS_SUCCESS) {
  2432. dp_info_rl("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  2433. tx_desc, tx_q->ring_id);
  2434. dp_tx_get_tid(vdev, nbuf, msdu_info);
  2435. tid_stats = &pdev->stats.tid_stats.
  2436. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  2437. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  2438. if (msdu_info->frm_type == dp_tx_frm_me) {
  2439. hw_enq_fail++;
  2440. if (hw_enq_fail == msdu_info->num_seg) {
  2441. /*
  2442. * Unmap is needed only if enqueue
  2443. * failed for all segments.
  2444. */
  2445. qdf_nbuf_unmap(soc->osdev,
  2446. msdu_info->u.sg_info.
  2447. curr_seg->nbuf,
  2448. QDF_DMA_TO_DEVICE);
  2449. }
  2450. /*
  2451. * Free the nbuf for the current segment
  2452. * and make it point to the next in the list.
  2453. * For me, there are as many segments as there
  2454. * are no of clients.
  2455. */
  2456. qdf_nbuf_free(msdu_info->u.sg_info
  2457. .curr_seg->nbuf);
  2458. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2459. if (msdu_info->u.sg_info.curr_seg->next) {
  2460. msdu_info->u.sg_info.curr_seg =
  2461. msdu_info->u.sg_info
  2462. .curr_seg->next;
  2463. nbuf = msdu_info->u.sg_info
  2464. .curr_seg->nbuf;
  2465. } else
  2466. break;
  2467. i++;
  2468. continue;
  2469. }
  2470. /*
  2471. * For TSO frames, the nbuf users increment done for
  2472. * the current segment has to be reverted, since the
  2473. * hw enqueue for this segment failed
  2474. */
  2475. if (msdu_info->frm_type == dp_tx_frm_tso &&
  2476. msdu_info->u.tso_info.curr_seg) {
  2477. /*
  2478. * unmap and free current,
  2479. * retransmit remaining segments
  2480. */
  2481. dp_tx_comp_free_buf(soc, tx_desc, false);
  2482. i++;
  2483. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2484. continue;
  2485. }
  2486. if (msdu_info->frm_type == dp_tx_frm_sg)
  2487. dp_tx_sg_unmap_buf(soc, nbuf, msdu_info);
  2488. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2489. goto done;
  2490. }
  2491. /*
  2492. * TODO
  2493. * if tso_info structure can be modified to have curr_seg
  2494. * as first element, following 2 blocks of code (for TSO and SG)
  2495. * can be combined into 1
  2496. */
  2497. /*
  2498. * For Multicast-Unicast converted packets,
  2499. * each converted frame (for a client) is represented as
  2500. * 1 segment
  2501. */
  2502. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  2503. (msdu_info->frm_type == dp_tx_frm_me)) {
  2504. if (msdu_info->u.sg_info.curr_seg->next) {
  2505. msdu_info->u.sg_info.curr_seg =
  2506. msdu_info->u.sg_info.curr_seg->next;
  2507. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2508. } else
  2509. break;
  2510. }
  2511. i++;
  2512. }
  2513. nbuf = NULL;
  2514. done:
  2515. return nbuf;
  2516. }
  2517. /**
  2518. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  2519. * for SG frames
  2520. * @vdev: DP vdev handle
  2521. * @nbuf: skb
  2522. * @seg_info: Pointer to Segment info Descriptor to be prepared
  2523. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2524. *
  2525. * Return: NULL on success,
  2526. * nbuf when it fails to send
  2527. */
  2528. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2529. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  2530. {
  2531. uint32_t cur_frag, nr_frags, i;
  2532. qdf_dma_addr_t paddr;
  2533. struct dp_tx_sg_info_s *sg_info;
  2534. sg_info = &msdu_info->u.sg_info;
  2535. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  2536. if (QDF_STATUS_SUCCESS !=
  2537. qdf_nbuf_map_nbytes_single(vdev->osdev, nbuf,
  2538. QDF_DMA_TO_DEVICE,
  2539. qdf_nbuf_headlen(nbuf))) {
  2540. dp_tx_err("dma map error");
  2541. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2542. qdf_nbuf_free(nbuf);
  2543. return NULL;
  2544. }
  2545. paddr = qdf_nbuf_mapped_paddr_get(nbuf);
  2546. seg_info->frags[0].paddr_lo = paddr;
  2547. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  2548. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  2549. seg_info->frags[0].vaddr = (void *) nbuf;
  2550. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  2551. if (QDF_STATUS_SUCCESS != qdf_nbuf_frag_map(vdev->osdev,
  2552. nbuf, 0,
  2553. QDF_DMA_TO_DEVICE,
  2554. cur_frag)) {
  2555. dp_tx_err("frag dma map error");
  2556. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2557. goto map_err;
  2558. }
  2559. paddr = qdf_nbuf_get_tx_frag_paddr(nbuf);
  2560. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  2561. seg_info->frags[cur_frag + 1].paddr_hi =
  2562. ((uint64_t) paddr) >> 32;
  2563. seg_info->frags[cur_frag + 1].len =
  2564. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  2565. }
  2566. seg_info->frag_cnt = (cur_frag + 1);
  2567. seg_info->total_len = qdf_nbuf_len(nbuf);
  2568. seg_info->next = NULL;
  2569. sg_info->curr_seg = seg_info;
  2570. msdu_info->frm_type = dp_tx_frm_sg;
  2571. msdu_info->num_seg = 1;
  2572. return nbuf;
  2573. map_err:
  2574. /* restore paddr into nbuf before calling unmap */
  2575. qdf_nbuf_mapped_paddr_set(nbuf,
  2576. (qdf_dma_addr_t)(seg_info->frags[0].paddr_lo |
  2577. ((uint64_t)
  2578. seg_info->frags[0].paddr_hi) << 32));
  2579. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  2580. QDF_DMA_TO_DEVICE,
  2581. seg_info->frags[0].len);
  2582. for (i = 1; i <= cur_frag; i++) {
  2583. qdf_mem_unmap_page(vdev->osdev, (qdf_dma_addr_t)
  2584. (seg_info->frags[i].paddr_lo | ((uint64_t)
  2585. seg_info->frags[i].paddr_hi) << 32),
  2586. seg_info->frags[i].len,
  2587. QDF_DMA_TO_DEVICE);
  2588. }
  2589. qdf_nbuf_free(nbuf);
  2590. return NULL;
  2591. }
  2592. /**
  2593. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  2594. * @vdev: DP vdev handle
  2595. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2596. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  2597. *
  2598. * Return: NULL on failure,
  2599. * nbuf when extracted successfully
  2600. */
  2601. static
  2602. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  2603. struct dp_tx_msdu_info_s *msdu_info,
  2604. uint16_t ppdu_cookie)
  2605. {
  2606. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2607. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2608. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2609. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  2610. (msdu_info->meta_data[5], 1);
  2611. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  2612. (msdu_info->meta_data[5], 1);
  2613. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  2614. (msdu_info->meta_data[6], ppdu_cookie);
  2615. msdu_info->exception_fw = 1;
  2616. msdu_info->is_tx_sniffer = 1;
  2617. }
  2618. #ifdef MESH_MODE_SUPPORT
  2619. /**
  2620. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  2621. and prepare msdu_info for mesh frames.
  2622. * @vdev: DP vdev handle
  2623. * @nbuf: skb
  2624. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2625. *
  2626. * Return: NULL on failure,
  2627. * nbuf when extracted successfully
  2628. */
  2629. static
  2630. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2631. struct dp_tx_msdu_info_s *msdu_info)
  2632. {
  2633. struct meta_hdr_s *mhdr;
  2634. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2635. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2636. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2637. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  2638. msdu_info->exception_fw = 0;
  2639. goto remove_meta_hdr;
  2640. }
  2641. msdu_info->exception_fw = 1;
  2642. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2643. meta_data->host_tx_desc_pool = 1;
  2644. meta_data->update_peer_cache = 1;
  2645. meta_data->learning_frame = 1;
  2646. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  2647. meta_data->power = mhdr->power;
  2648. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  2649. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  2650. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  2651. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  2652. meta_data->dyn_bw = 1;
  2653. meta_data->valid_pwr = 1;
  2654. meta_data->valid_mcs_mask = 1;
  2655. meta_data->valid_nss_mask = 1;
  2656. meta_data->valid_preamble_type = 1;
  2657. meta_data->valid_retries = 1;
  2658. meta_data->valid_bw_info = 1;
  2659. }
  2660. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  2661. meta_data->encrypt_type = 0;
  2662. meta_data->valid_encrypt_type = 1;
  2663. meta_data->learning_frame = 0;
  2664. }
  2665. meta_data->valid_key_flags = 1;
  2666. meta_data->key_flags = (mhdr->keyix & 0x3);
  2667. remove_meta_hdr:
  2668. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2669. dp_tx_err("qdf_nbuf_pull_head failed");
  2670. qdf_nbuf_free(nbuf);
  2671. return NULL;
  2672. }
  2673. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  2674. dp_tx_info("Meta hdr %0x %0x %0x %0x %0x %0x"
  2675. " tid %d to_fw %d",
  2676. msdu_info->meta_data[0],
  2677. msdu_info->meta_data[1],
  2678. msdu_info->meta_data[2],
  2679. msdu_info->meta_data[3],
  2680. msdu_info->meta_data[4],
  2681. msdu_info->meta_data[5],
  2682. msdu_info->tid, msdu_info->exception_fw);
  2683. return nbuf;
  2684. }
  2685. #else
  2686. static
  2687. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2688. struct dp_tx_msdu_info_s *msdu_info)
  2689. {
  2690. return nbuf;
  2691. }
  2692. #endif
  2693. /**
  2694. * dp_check_exc_metadata() - Checks if parameters are valid
  2695. * @tx_exc - holds all exception path parameters
  2696. *
  2697. * Returns true when all the parameters are valid else false
  2698. *
  2699. */
  2700. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  2701. {
  2702. bool invalid_tid = (tx_exc->tid >= DP_MAX_TIDS && tx_exc->tid !=
  2703. HTT_INVALID_TID);
  2704. bool invalid_encap_type =
  2705. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  2706. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  2707. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  2708. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  2709. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  2710. tx_exc->ppdu_cookie == 0);
  2711. if (tx_exc->is_intrabss_fwd)
  2712. return true;
  2713. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  2714. invalid_cookie) {
  2715. return false;
  2716. }
  2717. return true;
  2718. }
  2719. #ifdef ATH_SUPPORT_IQUE
  2720. /**
  2721. * dp_tx_mcast_enhance() - Multicast enhancement on TX
  2722. * @vdev: vdev handle
  2723. * @nbuf: skb
  2724. *
  2725. * Return: true on success,
  2726. * false on failure
  2727. */
  2728. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2729. {
  2730. qdf_ether_header_t *eh;
  2731. /* Mcast to Ucast Conversion*/
  2732. if (qdf_likely(!vdev->mcast_enhancement_en))
  2733. return true;
  2734. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2735. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2736. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2737. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  2738. qdf_nbuf_set_next(nbuf, NULL);
  2739. DP_STATS_INC_PKT(vdev, tx_i.mcast_en.mcast_pkt, 1,
  2740. qdf_nbuf_len(nbuf));
  2741. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  2742. QDF_STATUS_SUCCESS) {
  2743. return false;
  2744. }
  2745. if (qdf_unlikely(vdev->igmp_mcast_enhanc_en > 0)) {
  2746. if (dp_tx_prepare_send_igmp_me(vdev, nbuf) ==
  2747. QDF_STATUS_SUCCESS) {
  2748. return false;
  2749. }
  2750. }
  2751. }
  2752. return true;
  2753. }
  2754. #else
  2755. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2756. {
  2757. return true;
  2758. }
  2759. #endif
  2760. #ifdef QCA_SUPPORT_WDS_EXTENDED
  2761. /**
  2762. * dp_tx_mcast_drop() - Drop mcast frame if drop_tx_mcast is set in WDS_EXT
  2763. * @vdev: vdev handle
  2764. * @nbuf: skb
  2765. *
  2766. * Return: true if frame is dropped, false otherwise
  2767. */
  2768. static inline bool dp_tx_mcast_drop(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2769. {
  2770. /* Drop tx mcast and WDS Extended feature check */
  2771. if (qdf_unlikely((vdev->drop_tx_mcast) && (vdev->wds_ext_enabled))) {
  2772. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  2773. qdf_nbuf_data(nbuf);
  2774. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  2775. DP_STATS_INC(vdev, tx_i.dropped.tx_mcast_drop, 1);
  2776. return true;
  2777. }
  2778. }
  2779. return false;
  2780. }
  2781. #else
  2782. static inline bool dp_tx_mcast_drop(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2783. {
  2784. return false;
  2785. }
  2786. #endif
  2787. /**
  2788. * dp_tx_per_pkt_vdev_id_check() - vdev id check for frame
  2789. * @nbuf: qdf_nbuf_t
  2790. * @vdev: struct dp_vdev *
  2791. *
  2792. * Allow packet for processing only if it is for peer client which is
  2793. * connected with same vap. Drop packet if client is connected to
  2794. * different vap.
  2795. *
  2796. * Return: QDF_STATUS
  2797. */
  2798. static inline QDF_STATUS
  2799. dp_tx_per_pkt_vdev_id_check(qdf_nbuf_t nbuf, struct dp_vdev *vdev)
  2800. {
  2801. struct dp_ast_entry *dst_ast_entry = NULL;
  2802. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2803. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) ||
  2804. DP_FRAME_IS_BROADCAST((eh)->ether_dhost))
  2805. return QDF_STATUS_SUCCESS;
  2806. qdf_spin_lock_bh(&vdev->pdev->soc->ast_lock);
  2807. dst_ast_entry = dp_peer_ast_hash_find_by_vdevid(vdev->pdev->soc,
  2808. eh->ether_dhost,
  2809. vdev->vdev_id);
  2810. /* If there is no ast entry, return failure */
  2811. if (qdf_unlikely(!dst_ast_entry)) {
  2812. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2813. return QDF_STATUS_E_FAILURE;
  2814. }
  2815. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2816. return QDF_STATUS_SUCCESS;
  2817. }
  2818. /**
  2819. * dp_tx_nawds_handler() - NAWDS handler
  2820. *
  2821. * @soc: DP soc handle
  2822. * @vdev_id: id of DP vdev handle
  2823. * @msdu_info: msdu_info required to create HTT metadata
  2824. * @nbuf: skb
  2825. *
  2826. * This API transfers the multicast frames with the peer id
  2827. * on NAWDS enabled peer.
  2828. * Return: none
  2829. */
  2830. static inline
  2831. void dp_tx_nawds_handler(struct dp_soc *soc, struct dp_vdev *vdev,
  2832. struct dp_tx_msdu_info_s *msdu_info,
  2833. qdf_nbuf_t nbuf, uint16_t sa_peer_id)
  2834. {
  2835. struct dp_peer *peer = NULL;
  2836. qdf_nbuf_t nbuf_clone = NULL;
  2837. uint16_t peer_id = DP_INVALID_PEER;
  2838. struct dp_txrx_peer *txrx_peer;
  2839. /* This check avoids pkt forwarding which is entered
  2840. * in the ast table but still doesn't have valid peerid.
  2841. */
  2842. if (sa_peer_id == HTT_INVALID_PEER)
  2843. return;
  2844. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2845. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2846. txrx_peer = dp_get_txrx_peer(peer);
  2847. if (!txrx_peer)
  2848. continue;
  2849. if (!txrx_peer->bss_peer && txrx_peer->nawds_enabled) {
  2850. peer_id = peer->peer_id;
  2851. if (!dp_peer_is_primary_link_peer(peer))
  2852. continue;
  2853. /* Multicast packets needs to be
  2854. * dropped in case of intra bss forwarding
  2855. */
  2856. if (sa_peer_id == txrx_peer->peer_id) {
  2857. dp_tx_debug("multicast packet");
  2858. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  2859. tx.nawds_mcast_drop,
  2860. 1);
  2861. continue;
  2862. }
  2863. nbuf_clone = qdf_nbuf_clone(nbuf);
  2864. if (!nbuf_clone) {
  2865. QDF_TRACE(QDF_MODULE_ID_DP,
  2866. QDF_TRACE_LEVEL_ERROR,
  2867. FL("nbuf clone failed"));
  2868. break;
  2869. }
  2870. nbuf_clone = dp_tx_send_msdu_single(vdev, nbuf_clone,
  2871. msdu_info, peer_id,
  2872. NULL);
  2873. if (nbuf_clone) {
  2874. dp_tx_debug("pkt send failed");
  2875. qdf_nbuf_free(nbuf_clone);
  2876. } else {
  2877. if (peer_id != DP_INVALID_PEER)
  2878. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  2879. tx.nawds_mcast,
  2880. 1, qdf_nbuf_len(nbuf));
  2881. }
  2882. }
  2883. }
  2884. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2885. }
  2886. /**
  2887. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  2888. * @soc: DP soc handle
  2889. * @vdev_id: id of DP vdev handle
  2890. * @nbuf: skb
  2891. * @tx_exc_metadata: Handle that holds exception path meta data
  2892. *
  2893. * Entry point for Core Tx layer (DP_TX) invoked from
  2894. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2895. *
  2896. * Return: NULL on success,
  2897. * nbuf when it fails to send
  2898. */
  2899. qdf_nbuf_t
  2900. dp_tx_send_exception(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2901. qdf_nbuf_t nbuf,
  2902. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2903. {
  2904. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2905. struct dp_tx_msdu_info_s msdu_info;
  2906. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2907. DP_MOD_ID_TX_EXCEPTION);
  2908. if (qdf_unlikely(!vdev))
  2909. goto fail;
  2910. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2911. if (!tx_exc_metadata)
  2912. goto fail;
  2913. msdu_info.tid = tx_exc_metadata->tid;
  2914. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2915. QDF_MAC_ADDR_REF(nbuf->data));
  2916. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2917. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  2918. dp_tx_err("Invalid parameters in exception path");
  2919. goto fail;
  2920. }
  2921. /* for peer based metadata check if peer is valid */
  2922. if (tx_exc_metadata->peer_id != CDP_INVALID_PEER) {
  2923. struct dp_peer *peer = NULL;
  2924. peer = dp_peer_get_ref_by_id(vdev->pdev->soc,
  2925. tx_exc_metadata->peer_id,
  2926. DP_MOD_ID_TX_EXCEPTION);
  2927. if (qdf_unlikely(!peer)) {
  2928. DP_STATS_INC(vdev,
  2929. tx_i.dropped.invalid_peer_id_in_exc_path,
  2930. 1);
  2931. goto fail;
  2932. }
  2933. dp_peer_unref_delete(peer, DP_MOD_ID_TX_EXCEPTION);
  2934. }
  2935. /* Basic sanity checks for unsupported packets */
  2936. /* MESH mode */
  2937. if (qdf_unlikely(vdev->mesh_vdev)) {
  2938. dp_tx_err("Mesh mode is not supported in exception path");
  2939. goto fail;
  2940. }
  2941. /*
  2942. * Classify the frame and call corresponding
  2943. * "prepare" function which extracts the segment (TSO)
  2944. * and fragmentation information (for TSO , SG, ME, or Raw)
  2945. * into MSDU_INFO structure which is later used to fill
  2946. * SW and HW descriptors.
  2947. */
  2948. if (qdf_nbuf_is_tso(nbuf)) {
  2949. dp_verbose_debug("TSO frame %pK", vdev);
  2950. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2951. qdf_nbuf_len(nbuf));
  2952. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2953. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2954. qdf_nbuf_len(nbuf));
  2955. goto fail;
  2956. }
  2957. DP_STATS_INC(vdev, tx_i.rcvd.num, msdu_info.num_seg - 1);
  2958. goto send_multiple;
  2959. }
  2960. /* SG */
  2961. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2962. struct dp_tx_seg_info_s seg_info = {0};
  2963. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2964. if (!nbuf)
  2965. goto fail;
  2966. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2967. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2968. qdf_nbuf_len(nbuf));
  2969. goto send_multiple;
  2970. }
  2971. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  2972. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  2973. qdf_nbuf_len(nbuf));
  2974. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  2975. tx_exc_metadata->ppdu_cookie);
  2976. }
  2977. /*
  2978. * Get HW Queue to use for this frame.
  2979. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2980. * dedicated for data and 1 for command.
  2981. * "queue_id" maps to one hardware ring.
  2982. * With each ring, we also associate a unique Tx descriptor pool
  2983. * to minimize lock contention for these resources.
  2984. */
  2985. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2986. if (qdf_likely(tx_exc_metadata->is_intrabss_fwd)) {
  2987. if (qdf_unlikely(vdev->nawds_enabled)) {
  2988. /*
  2989. * This is a multicast packet
  2990. */
  2991. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf,
  2992. tx_exc_metadata->peer_id);
  2993. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2994. 1, qdf_nbuf_len(nbuf));
  2995. }
  2996. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2997. DP_INVALID_PEER, NULL);
  2998. } else {
  2999. /*
  3000. * Check exception descriptors
  3001. */
  3002. if (dp_tx_exception_limit_check(vdev))
  3003. goto fail;
  3004. /* Single linear frame */
  3005. /*
  3006. * If nbuf is a simple linear frame, use send_single function to
  3007. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  3008. * SRNG. There is no need to setup a MSDU extension descriptor.
  3009. */
  3010. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  3011. tx_exc_metadata->peer_id,
  3012. tx_exc_metadata);
  3013. }
  3014. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  3015. return nbuf;
  3016. send_multiple:
  3017. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  3018. fail:
  3019. if (vdev)
  3020. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  3021. dp_verbose_debug("pkt send failed");
  3022. return nbuf;
  3023. }
  3024. /**
  3025. * dp_tx_send_exception_vdev_id_check() - Transmit a frame on a given VAP
  3026. * in exception path in special case to avoid regular exception path chk.
  3027. * @soc: DP soc handle
  3028. * @vdev_id: id of DP vdev handle
  3029. * @nbuf: skb
  3030. * @tx_exc_metadata: Handle that holds exception path meta data
  3031. *
  3032. * Entry point for Core Tx layer (DP_TX) invoked from
  3033. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  3034. *
  3035. * Return: NULL on success,
  3036. * nbuf when it fails to send
  3037. */
  3038. qdf_nbuf_t
  3039. dp_tx_send_exception_vdev_id_check(struct cdp_soc_t *soc_hdl,
  3040. uint8_t vdev_id, qdf_nbuf_t nbuf,
  3041. struct cdp_tx_exception_metadata *tx_exc_metadata)
  3042. {
  3043. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3044. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3045. DP_MOD_ID_TX_EXCEPTION);
  3046. if (qdf_unlikely(!vdev))
  3047. goto fail;
  3048. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  3049. == QDF_STATUS_E_FAILURE)) {
  3050. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  3051. goto fail;
  3052. }
  3053. /* Unref count as it will again be taken inside dp_tx_exception */
  3054. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  3055. return dp_tx_send_exception(soc_hdl, vdev_id, nbuf, tx_exc_metadata);
  3056. fail:
  3057. if (vdev)
  3058. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  3059. dp_verbose_debug("pkt send failed");
  3060. return nbuf;
  3061. }
  3062. /**
  3063. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  3064. * @soc: DP soc handle
  3065. * @vdev_id: DP vdev handle
  3066. * @nbuf: skb
  3067. *
  3068. * Entry point for Core Tx layer (DP_TX) invoked from
  3069. * hard_start_xmit in OSIF/HDD
  3070. *
  3071. * Return: NULL on success,
  3072. * nbuf when it fails to send
  3073. */
  3074. #ifdef MESH_MODE_SUPPORT
  3075. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3076. qdf_nbuf_t nbuf)
  3077. {
  3078. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3079. struct meta_hdr_s *mhdr;
  3080. qdf_nbuf_t nbuf_mesh = NULL;
  3081. qdf_nbuf_t nbuf_clone = NULL;
  3082. struct dp_vdev *vdev;
  3083. uint8_t no_enc_frame = 0;
  3084. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  3085. if (!nbuf_mesh) {
  3086. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3087. "qdf_nbuf_unshare failed");
  3088. return nbuf;
  3089. }
  3090. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_MESH);
  3091. if (!vdev) {
  3092. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3093. "vdev is NULL for vdev_id %d", vdev_id);
  3094. return nbuf;
  3095. }
  3096. nbuf = nbuf_mesh;
  3097. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  3098. if ((vdev->sec_type != cdp_sec_type_none) &&
  3099. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  3100. no_enc_frame = 1;
  3101. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  3102. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  3103. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  3104. !no_enc_frame) {
  3105. nbuf_clone = qdf_nbuf_clone(nbuf);
  3106. if (!nbuf_clone) {
  3107. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3108. "qdf_nbuf_clone failed");
  3109. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  3110. return nbuf;
  3111. }
  3112. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  3113. }
  3114. if (nbuf_clone) {
  3115. if (!dp_tx_send(soc_hdl, vdev_id, nbuf_clone)) {
  3116. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  3117. } else {
  3118. qdf_nbuf_free(nbuf_clone);
  3119. }
  3120. }
  3121. if (no_enc_frame)
  3122. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  3123. else
  3124. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  3125. nbuf = dp_tx_send(soc_hdl, vdev_id, nbuf);
  3126. if ((!nbuf) && no_enc_frame) {
  3127. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  3128. }
  3129. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  3130. return nbuf;
  3131. }
  3132. #else
  3133. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc, uint8_t vdev_id,
  3134. qdf_nbuf_t nbuf)
  3135. {
  3136. return dp_tx_send(soc, vdev_id, nbuf);
  3137. }
  3138. #endif
  3139. #ifdef QCA_DP_TX_NBUF_AND_NBUF_DATA_PREFETCH
  3140. static inline
  3141. void dp_tx_prefetch_nbuf_data(qdf_nbuf_t nbuf)
  3142. {
  3143. if (nbuf) {
  3144. qdf_prefetch(&nbuf->len);
  3145. qdf_prefetch(&nbuf->data);
  3146. }
  3147. }
  3148. #else
  3149. static inline
  3150. void dp_tx_prefetch_nbuf_data(qdf_nbuf_t nbuf)
  3151. {
  3152. }
  3153. #endif
  3154. #ifdef DP_UMAC_HW_RESET_SUPPORT
  3155. /*
  3156. * dp_tx_drop() - Drop the frame on a given VAP
  3157. * @soc: DP soc handle
  3158. * @vdev_id: id of DP vdev handle
  3159. * @nbuf: skb
  3160. *
  3161. * Drop all the incoming packets
  3162. *
  3163. * Return: nbuf
  3164. *
  3165. */
  3166. qdf_nbuf_t dp_tx_drop(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3167. qdf_nbuf_t nbuf)
  3168. {
  3169. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3170. struct dp_vdev *vdev = NULL;
  3171. vdev = soc->vdev_id_map[vdev_id];
  3172. if (qdf_unlikely(!vdev))
  3173. return nbuf;
  3174. DP_STATS_INC(vdev, tx_i.dropped.drop_ingress, 1);
  3175. return nbuf;
  3176. }
  3177. /*
  3178. * dp_tx_exc_drop() - Drop the frame on a given VAP
  3179. * @soc: DP soc handle
  3180. * @vdev_id: id of DP vdev handle
  3181. * @nbuf: skb
  3182. * @tx_exc_metadata: Handle that holds exception path meta data
  3183. *
  3184. * Drop all the incoming packets
  3185. *
  3186. * Return: nbuf
  3187. *
  3188. */
  3189. qdf_nbuf_t dp_tx_exc_drop(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3190. qdf_nbuf_t nbuf,
  3191. struct cdp_tx_exception_metadata *tx_exc_metadata)
  3192. {
  3193. return dp_tx_drop(soc_hdl, vdev_id, nbuf);
  3194. }
  3195. #endif
  3196. #ifdef FEATURE_DIRECT_LINK
  3197. /*
  3198. * dp_vdev_tx_mark_to_fw() - Mark to_fw bit for the tx packet
  3199. * @nbuf: skb
  3200. * @vdev: DP vdev handle
  3201. *
  3202. * Return: None
  3203. */
  3204. static inline void dp_vdev_tx_mark_to_fw(qdf_nbuf_t nbuf, struct dp_vdev *vdev)
  3205. {
  3206. if (qdf_unlikely(vdev->to_fw))
  3207. QDF_NBUF_CB_TX_PACKET_TO_FW(nbuf) = 1;
  3208. }
  3209. #else
  3210. static inline void dp_vdev_tx_mark_to_fw(qdf_nbuf_t nbuf, struct dp_vdev *vdev)
  3211. {
  3212. }
  3213. #endif
  3214. /*
  3215. * dp_tx_send() - Transmit a frame on a given VAP
  3216. * @soc: DP soc handle
  3217. * @vdev_id: id of DP vdev handle
  3218. * @nbuf: skb
  3219. *
  3220. * Entry point for Core Tx layer (DP_TX) invoked from
  3221. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  3222. * cases
  3223. *
  3224. * Return: NULL on success,
  3225. * nbuf when it fails to send
  3226. */
  3227. qdf_nbuf_t dp_tx_send(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3228. qdf_nbuf_t nbuf)
  3229. {
  3230. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3231. uint16_t peer_id = HTT_INVALID_PEER;
  3232. /*
  3233. * doing a memzero is causing additional function call overhead
  3234. * so doing static stack clearing
  3235. */
  3236. struct dp_tx_msdu_info_s msdu_info = {0};
  3237. struct dp_vdev *vdev = NULL;
  3238. qdf_nbuf_t end_nbuf = NULL;
  3239. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  3240. return nbuf;
  3241. /*
  3242. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  3243. * this in per packet path.
  3244. *
  3245. * As in this path vdev memory is already protected with netdev
  3246. * tx lock
  3247. */
  3248. vdev = soc->vdev_id_map[vdev_id];
  3249. if (qdf_unlikely(!vdev))
  3250. return nbuf;
  3251. dp_vdev_tx_mark_to_fw(nbuf, vdev);
  3252. /*
  3253. * Set Default Host TID value to invalid TID
  3254. * (TID override disabled)
  3255. */
  3256. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  3257. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  3258. if (qdf_unlikely(vdev->mesh_vdev)) {
  3259. qdf_nbuf_t nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  3260. &msdu_info);
  3261. if (!nbuf_mesh) {
  3262. dp_verbose_debug("Extracting mesh metadata failed");
  3263. return nbuf;
  3264. }
  3265. nbuf = nbuf_mesh;
  3266. }
  3267. /*
  3268. * Get HW Queue to use for this frame.
  3269. * TCL supports upto 4 DMA rings, out of which 3 rings are
  3270. * dedicated for data and 1 for command.
  3271. * "queue_id" maps to one hardware ring.
  3272. * With each ring, we also associate a unique Tx descriptor pool
  3273. * to minimize lock contention for these resources.
  3274. */
  3275. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  3276. DP_STATS_INC(vdev, tx_i.rcvd_per_core[msdu_info.tx_queue.desc_pool_id],
  3277. 1);
  3278. /*
  3279. * TCL H/W supports 2 DSCP-TID mapping tables.
  3280. * Table 1 - Default DSCP-TID mapping table
  3281. * Table 2 - 1 DSCP-TID override table
  3282. *
  3283. * If we need a different DSCP-TID mapping for this vap,
  3284. * call tid_classify to extract DSCP/ToS from frame and
  3285. * map to a TID and store in msdu_info. This is later used
  3286. * to fill in TCL Input descriptor (per-packet TID override).
  3287. */
  3288. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  3289. /*
  3290. * Classify the frame and call corresponding
  3291. * "prepare" function which extracts the segment (TSO)
  3292. * and fragmentation information (for TSO , SG, ME, or Raw)
  3293. * into MSDU_INFO structure which is later used to fill
  3294. * SW and HW descriptors.
  3295. */
  3296. if (qdf_nbuf_is_tso(nbuf)) {
  3297. dp_verbose_debug("TSO frame %pK", vdev);
  3298. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  3299. qdf_nbuf_len(nbuf));
  3300. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  3301. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  3302. qdf_nbuf_len(nbuf));
  3303. return nbuf;
  3304. }
  3305. DP_STATS_INC(vdev, tx_i.rcvd.num, msdu_info.num_seg - 1);
  3306. goto send_multiple;
  3307. }
  3308. /* SG */
  3309. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  3310. if (qdf_nbuf_get_nr_frags(nbuf) > DP_TX_MAX_NUM_FRAGS - 1) {
  3311. if (qdf_unlikely(qdf_nbuf_linearize(nbuf)))
  3312. return nbuf;
  3313. } else {
  3314. struct dp_tx_seg_info_s seg_info = {0};
  3315. if (qdf_unlikely(is_nbuf_frm_rmnet(nbuf, &msdu_info)))
  3316. goto send_single;
  3317. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info,
  3318. &msdu_info);
  3319. if (!nbuf)
  3320. return NULL;
  3321. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  3322. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  3323. qdf_nbuf_len(nbuf));
  3324. goto send_multiple;
  3325. }
  3326. }
  3327. if (qdf_unlikely(!dp_tx_mcast_enhance(vdev, nbuf)))
  3328. return NULL;
  3329. if (qdf_unlikely(dp_tx_mcast_drop(vdev, nbuf)))
  3330. return nbuf;
  3331. /* RAW */
  3332. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  3333. struct dp_tx_seg_info_s seg_info = {0};
  3334. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  3335. if (!nbuf)
  3336. return NULL;
  3337. dp_verbose_debug("Raw frame %pK", vdev);
  3338. goto send_multiple;
  3339. }
  3340. if (qdf_unlikely(vdev->nawds_enabled)) {
  3341. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  3342. qdf_nbuf_data(nbuf);
  3343. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  3344. uint16_t sa_peer_id = DP_INVALID_PEER;
  3345. if (!soc->ast_offload_support) {
  3346. struct dp_ast_entry *ast_entry = NULL;
  3347. qdf_spin_lock_bh(&soc->ast_lock);
  3348. ast_entry = dp_peer_ast_hash_find_by_pdevid
  3349. (soc,
  3350. (uint8_t *)(eh->ether_shost),
  3351. vdev->pdev->pdev_id);
  3352. if (ast_entry)
  3353. sa_peer_id = ast_entry->peer_id;
  3354. qdf_spin_unlock_bh(&soc->ast_lock);
  3355. }
  3356. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf,
  3357. sa_peer_id);
  3358. }
  3359. peer_id = DP_INVALID_PEER;
  3360. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  3361. 1, qdf_nbuf_len(nbuf));
  3362. }
  3363. send_single:
  3364. /* Single linear frame */
  3365. /*
  3366. * If nbuf is a simple linear frame, use send_single function to
  3367. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  3368. * SRNG. There is no need to setup a MSDU extension descriptor.
  3369. */
  3370. dp_tx_prefetch_nbuf_data(nbuf);
  3371. nbuf = dp_tx_send_msdu_single_wrapper(vdev, nbuf, &msdu_info,
  3372. peer_id, end_nbuf);
  3373. return nbuf;
  3374. send_multiple:
  3375. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  3376. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  3377. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  3378. return nbuf;
  3379. }
  3380. /**
  3381. * dp_tx_send_vdev_id_check() - Transmit a frame on a given VAP in special
  3382. * case to vaoid check in perpkt path.
  3383. * @soc: DP soc handle
  3384. * @vdev_id: id of DP vdev handle
  3385. * @nbuf: skb
  3386. *
  3387. * Entry point for Core Tx layer (DP_TX) invoked from
  3388. * hard_start_xmit in OSIF/HDD to transmit packet through dp_tx_send
  3389. * with special condition to avoid per pkt check in dp_tx_send
  3390. *
  3391. * Return: NULL on success,
  3392. * nbuf when it fails to send
  3393. */
  3394. qdf_nbuf_t dp_tx_send_vdev_id_check(struct cdp_soc_t *soc_hdl,
  3395. uint8_t vdev_id, qdf_nbuf_t nbuf)
  3396. {
  3397. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3398. struct dp_vdev *vdev = NULL;
  3399. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  3400. return nbuf;
  3401. /*
  3402. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  3403. * this in per packet path.
  3404. *
  3405. * As in this path vdev memory is already protected with netdev
  3406. * tx lock
  3407. */
  3408. vdev = soc->vdev_id_map[vdev_id];
  3409. if (qdf_unlikely(!vdev))
  3410. return nbuf;
  3411. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  3412. == QDF_STATUS_E_FAILURE)) {
  3413. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  3414. return nbuf;
  3415. }
  3416. return dp_tx_send(soc_hdl, vdev_id, nbuf);
  3417. }
  3418. #ifdef UMAC_SUPPORT_PROXY_ARP
  3419. /**
  3420. * dp_tx_proxy_arp() - Tx proxy arp handler
  3421. * @vdev: datapath vdev handle
  3422. * @buf: sk buffer
  3423. *
  3424. * Return: status
  3425. */
  3426. static inline
  3427. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  3428. {
  3429. if (vdev->osif_proxy_arp)
  3430. return vdev->osif_proxy_arp(vdev->osif_vdev, nbuf);
  3431. /*
  3432. * when UMAC_SUPPORT_PROXY_ARP is defined, we expect
  3433. * osif_proxy_arp has a valid function pointer assigned
  3434. * to it
  3435. */
  3436. dp_tx_err("valid function pointer for osif_proxy_arp is expected!!\n");
  3437. return QDF_STATUS_NOT_INITIALIZED;
  3438. }
  3439. #else
  3440. /**
  3441. * dp_tx_proxy_arp() - Tx proxy arp handler
  3442. * @vdev: datapath vdev handle
  3443. * @buf: sk buffer
  3444. *
  3445. * This function always return 0 when UMAC_SUPPORT_PROXY_ARP
  3446. * is not defined.
  3447. *
  3448. * Return: status
  3449. */
  3450. static inline
  3451. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  3452. {
  3453. return QDF_STATUS_SUCCESS;
  3454. }
  3455. #endif
  3456. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP)
  3457. #ifdef WLAN_MCAST_MLO
  3458. static bool
  3459. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3460. struct dp_tx_desc_s *tx_desc,
  3461. qdf_nbuf_t nbuf,
  3462. uint8_t reinject_reason)
  3463. {
  3464. if (reinject_reason == HTT_TX_FW2WBM_REINJECT_REASON_MLO_MCAST) {
  3465. if (soc->arch_ops.dp_tx_mcast_handler)
  3466. soc->arch_ops.dp_tx_mcast_handler(soc, vdev, nbuf);
  3467. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3468. return true;
  3469. }
  3470. return false;
  3471. }
  3472. #else /* WLAN_MCAST_MLO */
  3473. static inline bool
  3474. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3475. struct dp_tx_desc_s *tx_desc,
  3476. qdf_nbuf_t nbuf,
  3477. uint8_t reinject_reason)
  3478. {
  3479. return false;
  3480. }
  3481. #endif /* WLAN_MCAST_MLO */
  3482. #else
  3483. static inline bool
  3484. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3485. struct dp_tx_desc_s *tx_desc,
  3486. qdf_nbuf_t nbuf,
  3487. uint8_t reinject_reason)
  3488. {
  3489. return false;
  3490. }
  3491. #endif
  3492. /**
  3493. * dp_tx_reinject_handler() - Tx Reinject Handler
  3494. * @soc: datapath soc handle
  3495. * @vdev: datapath vdev handle
  3496. * @tx_desc: software descriptor head pointer
  3497. * @status : Tx completion status from HTT descriptor
  3498. * @reinject_reason : reinject reason from HTT descriptor
  3499. *
  3500. * This function reinjects frames back to Target.
  3501. * Todo - Host queue needs to be added
  3502. *
  3503. * Return: none
  3504. */
  3505. void dp_tx_reinject_handler(struct dp_soc *soc,
  3506. struct dp_vdev *vdev,
  3507. struct dp_tx_desc_s *tx_desc,
  3508. uint8_t *status,
  3509. uint8_t reinject_reason)
  3510. {
  3511. struct dp_peer *peer = NULL;
  3512. uint32_t peer_id = HTT_INVALID_PEER;
  3513. qdf_nbuf_t nbuf = tx_desc->nbuf;
  3514. qdf_nbuf_t nbuf_copy = NULL;
  3515. struct dp_tx_msdu_info_s msdu_info;
  3516. #ifdef WDS_VENDOR_EXTENSION
  3517. int is_mcast = 0, is_ucast = 0;
  3518. int num_peers_3addr = 0;
  3519. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  3520. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  3521. #endif
  3522. struct dp_txrx_peer *txrx_peer;
  3523. qdf_assert(vdev);
  3524. dp_tx_debug("Tx reinject path");
  3525. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  3526. qdf_nbuf_len(tx_desc->nbuf));
  3527. if (dp_tx_reinject_mlo_hdl(soc, vdev, tx_desc, nbuf, reinject_reason))
  3528. return;
  3529. #ifdef WDS_VENDOR_EXTENSION
  3530. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  3531. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  3532. } else {
  3533. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  3534. }
  3535. is_ucast = !is_mcast;
  3536. qdf_spin_lock_bh(&vdev->peer_list_lock);
  3537. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3538. txrx_peer = dp_get_txrx_peer(peer);
  3539. if (!txrx_peer || txrx_peer->bss_peer)
  3540. continue;
  3541. /* Detect wds peers that use 3-addr framing for mcast.
  3542. * if there are any, the bss_peer is used to send the
  3543. * the mcast frame using 3-addr format. all wds enabled
  3544. * peers that use 4-addr framing for mcast frames will
  3545. * be duplicated and sent as 4-addr frames below.
  3546. */
  3547. if (!txrx_peer->wds_enabled ||
  3548. !txrx_peer->wds_ecm.wds_tx_mcast_4addr) {
  3549. num_peers_3addr = 1;
  3550. break;
  3551. }
  3552. }
  3553. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  3554. #endif
  3555. if (qdf_unlikely(vdev->mesh_vdev)) {
  3556. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  3557. } else {
  3558. qdf_spin_lock_bh(&vdev->peer_list_lock);
  3559. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3560. txrx_peer = dp_get_txrx_peer(peer);
  3561. if (!txrx_peer)
  3562. continue;
  3563. if ((txrx_peer->peer_id != HTT_INVALID_PEER) &&
  3564. #ifdef WDS_VENDOR_EXTENSION
  3565. /*
  3566. * . if 3-addr STA, then send on BSS Peer
  3567. * . if Peer WDS enabled and accept 4-addr mcast,
  3568. * send mcast on that peer only
  3569. * . if Peer WDS enabled and accept 4-addr ucast,
  3570. * send ucast on that peer only
  3571. */
  3572. ((txrx_peer->bss_peer && num_peers_3addr && is_mcast) ||
  3573. (txrx_peer->wds_enabled &&
  3574. ((is_mcast && txrx_peer->wds_ecm.wds_tx_mcast_4addr) ||
  3575. (is_ucast &&
  3576. txrx_peer->wds_ecm.wds_tx_ucast_4addr))))) {
  3577. #else
  3578. (txrx_peer->bss_peer &&
  3579. (dp_tx_proxy_arp(vdev, nbuf) == QDF_STATUS_SUCCESS))) {
  3580. #endif
  3581. peer_id = DP_INVALID_PEER;
  3582. nbuf_copy = qdf_nbuf_copy(nbuf);
  3583. if (!nbuf_copy) {
  3584. dp_tx_debug("nbuf copy failed");
  3585. break;
  3586. }
  3587. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  3588. dp_tx_get_queue(vdev, nbuf,
  3589. &msdu_info.tx_queue);
  3590. nbuf_copy = dp_tx_send_msdu_single(vdev,
  3591. nbuf_copy,
  3592. &msdu_info,
  3593. peer_id,
  3594. NULL);
  3595. if (nbuf_copy) {
  3596. dp_tx_debug("pkt send failed");
  3597. qdf_nbuf_free(nbuf_copy);
  3598. }
  3599. }
  3600. }
  3601. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  3602. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  3603. QDF_DMA_TO_DEVICE, nbuf->len);
  3604. qdf_nbuf_free(nbuf);
  3605. }
  3606. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3607. }
  3608. /**
  3609. * dp_tx_inspect_handler() - Tx Inspect Handler
  3610. * @soc: datapath soc handle
  3611. * @vdev: datapath vdev handle
  3612. * @tx_desc: software descriptor head pointer
  3613. * @status : Tx completion status from HTT descriptor
  3614. *
  3615. * Handles Tx frames sent back to Host for inspection
  3616. * (ProxyARP)
  3617. *
  3618. * Return: none
  3619. */
  3620. void dp_tx_inspect_handler(struct dp_soc *soc,
  3621. struct dp_vdev *vdev,
  3622. struct dp_tx_desc_s *tx_desc,
  3623. uint8_t *status)
  3624. {
  3625. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3626. "%s Tx inspect path",
  3627. __func__);
  3628. DP_STATS_INC_PKT(vdev, tx_i.inspect_pkts, 1,
  3629. qdf_nbuf_len(tx_desc->nbuf));
  3630. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  3631. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3632. }
  3633. #ifdef MESH_MODE_SUPPORT
  3634. /**
  3635. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  3636. * in mesh meta header
  3637. * @tx_desc: software descriptor head pointer
  3638. * @ts: pointer to tx completion stats
  3639. * Return: none
  3640. */
  3641. static
  3642. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3643. struct hal_tx_completion_status *ts)
  3644. {
  3645. qdf_nbuf_t netbuf = tx_desc->nbuf;
  3646. if (!tx_desc->msdu_ext_desc) {
  3647. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  3648. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3649. "netbuf %pK offset %d",
  3650. netbuf, tx_desc->pkt_offset);
  3651. return;
  3652. }
  3653. }
  3654. }
  3655. #else
  3656. static
  3657. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3658. struct hal_tx_completion_status *ts)
  3659. {
  3660. }
  3661. #endif
  3662. #ifdef CONFIG_SAWF
  3663. static void dp_tx_update_peer_sawf_stats(struct dp_soc *soc,
  3664. struct dp_vdev *vdev,
  3665. struct dp_txrx_peer *txrx_peer,
  3666. struct dp_tx_desc_s *tx_desc,
  3667. struct hal_tx_completion_status *ts,
  3668. uint8_t tid)
  3669. {
  3670. dp_sawf_tx_compl_update_peer_stats(soc, vdev, txrx_peer, tx_desc,
  3671. ts, tid);
  3672. }
  3673. static void dp_tx_compute_delay_avg(struct cdp_delay_tx_stats *tx_delay,
  3674. uint32_t nw_delay,
  3675. uint32_t sw_delay,
  3676. uint32_t hw_delay)
  3677. {
  3678. dp_peer_tid_delay_avg(tx_delay,
  3679. nw_delay,
  3680. sw_delay,
  3681. hw_delay);
  3682. }
  3683. #else
  3684. static void dp_tx_update_peer_sawf_stats(struct dp_soc *soc,
  3685. struct dp_vdev *vdev,
  3686. struct dp_txrx_peer *txrx_peer,
  3687. struct dp_tx_desc_s *tx_desc,
  3688. struct hal_tx_completion_status *ts,
  3689. uint8_t tid)
  3690. {
  3691. }
  3692. static inline void
  3693. dp_tx_compute_delay_avg(struct cdp_delay_tx_stats *tx_delay,
  3694. uint32_t nw_delay, uint32_t sw_delay,
  3695. uint32_t hw_delay)
  3696. {
  3697. }
  3698. #endif
  3699. #ifdef QCA_PEER_EXT_STATS
  3700. #ifdef WLAN_CONFIG_TX_DELAY
  3701. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  3702. struct dp_tx_desc_s *tx_desc,
  3703. struct hal_tx_completion_status *ts,
  3704. struct dp_vdev *vdev)
  3705. {
  3706. struct dp_soc *soc = vdev->pdev->soc;
  3707. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  3708. int64_t timestamp_ingress, timestamp_hw_enqueue;
  3709. uint32_t sw_enqueue_delay, fwhw_transmit_delay = 0;
  3710. if (!ts->valid)
  3711. return;
  3712. timestamp_ingress = qdf_nbuf_get_timestamp_us(tx_desc->nbuf);
  3713. timestamp_hw_enqueue = qdf_ktime_to_us(tx_desc->timestamp);
  3714. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3715. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  3716. if (soc->arch_ops.dp_tx_compute_hw_delay)
  3717. if (!soc->arch_ops.dp_tx_compute_hw_delay(soc, vdev, ts,
  3718. &fwhw_transmit_delay))
  3719. dp_hist_update_stats(&tx_delay->hwtx_delay,
  3720. fwhw_transmit_delay);
  3721. dp_tx_compute_delay_avg(tx_delay, 0, sw_enqueue_delay,
  3722. fwhw_transmit_delay);
  3723. }
  3724. #else
  3725. /*
  3726. * dp_tx_compute_tid_delay() - Compute per TID delay
  3727. * @stats: Per TID delay stats
  3728. * @tx_desc: Software Tx descriptor
  3729. * @ts: Tx completion status
  3730. * @vdev: vdev
  3731. *
  3732. * Compute the software enqueue and hw enqueue delays and
  3733. * update the respective histograms
  3734. *
  3735. * Return: void
  3736. */
  3737. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  3738. struct dp_tx_desc_s *tx_desc,
  3739. struct hal_tx_completion_status *ts,
  3740. struct dp_vdev *vdev)
  3741. {
  3742. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  3743. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3744. uint32_t sw_enqueue_delay, fwhw_transmit_delay;
  3745. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3746. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3747. timestamp_hw_enqueue = qdf_ktime_to_ms(tx_desc->timestamp);
  3748. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3749. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3750. timestamp_hw_enqueue);
  3751. /*
  3752. * Update the Tx software enqueue delay and HW enque-Completion delay.
  3753. */
  3754. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  3755. dp_hist_update_stats(&tx_delay->hwtx_delay, fwhw_transmit_delay);
  3756. }
  3757. #endif
  3758. /*
  3759. * dp_tx_update_peer_delay_stats() - Update the peer delay stats
  3760. * @txrx_peer: DP peer context
  3761. * @tx_desc: Tx software descriptor
  3762. * @tid: Transmission ID
  3763. * @ring_id: Rx CPU context ID/CPU_ID
  3764. *
  3765. * Update the peer extended stats. These are enhanced other
  3766. * delay stats per msdu level.
  3767. *
  3768. * Return: void
  3769. */
  3770. static void dp_tx_update_peer_delay_stats(struct dp_txrx_peer *txrx_peer,
  3771. struct dp_tx_desc_s *tx_desc,
  3772. struct hal_tx_completion_status *ts,
  3773. uint8_t ring_id)
  3774. {
  3775. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  3776. struct dp_soc *soc = NULL;
  3777. struct dp_peer_delay_stats *delay_stats = NULL;
  3778. uint8_t tid;
  3779. soc = pdev->soc;
  3780. if (qdf_likely(!wlan_cfg_is_peer_ext_stats_enabled(soc->wlan_cfg_ctx)))
  3781. return;
  3782. if (!txrx_peer->delay_stats)
  3783. return;
  3784. tid = ts->tid;
  3785. delay_stats = txrx_peer->delay_stats;
  3786. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  3787. /*
  3788. * For non-TID packets use the TID 9
  3789. */
  3790. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3791. tid = CDP_MAX_DATA_TIDS - 1;
  3792. dp_tx_compute_tid_delay(&delay_stats->delay_tid_stats[tid][ring_id],
  3793. tx_desc, ts, txrx_peer->vdev);
  3794. }
  3795. #else
  3796. static inline
  3797. void dp_tx_update_peer_delay_stats(struct dp_txrx_peer *txrx_peer,
  3798. struct dp_tx_desc_s *tx_desc,
  3799. struct hal_tx_completion_status *ts,
  3800. uint8_t ring_id)
  3801. {
  3802. }
  3803. #endif
  3804. #ifdef WLAN_PEER_JITTER
  3805. /*
  3806. * dp_tx_jitter_get_avg_jitter() - compute the average jitter
  3807. * @curr_delay: Current delay
  3808. * @prev_Delay: Previous delay
  3809. * @avg_jitter: Average Jitter
  3810. * Return: Newly Computed Average Jitter
  3811. */
  3812. static uint32_t dp_tx_jitter_get_avg_jitter(uint32_t curr_delay,
  3813. uint32_t prev_delay,
  3814. uint32_t avg_jitter)
  3815. {
  3816. uint32_t curr_jitter;
  3817. int32_t jitter_diff;
  3818. curr_jitter = qdf_abs(curr_delay - prev_delay);
  3819. if (!avg_jitter)
  3820. return curr_jitter;
  3821. jitter_diff = curr_jitter - avg_jitter;
  3822. if (jitter_diff < 0)
  3823. avg_jitter = avg_jitter -
  3824. (qdf_abs(jitter_diff) >> DP_AVG_JITTER_WEIGHT_DENOM);
  3825. else
  3826. avg_jitter = avg_jitter +
  3827. (qdf_abs(jitter_diff) >> DP_AVG_JITTER_WEIGHT_DENOM);
  3828. return avg_jitter;
  3829. }
  3830. /*
  3831. * dp_tx_jitter_get_avg_delay() - compute the average delay
  3832. * @curr_delay: Current delay
  3833. * @avg_Delay: Average delay
  3834. * Return: Newly Computed Average Delay
  3835. */
  3836. static uint32_t dp_tx_jitter_get_avg_delay(uint32_t curr_delay,
  3837. uint32_t avg_delay)
  3838. {
  3839. int32_t delay_diff;
  3840. if (!avg_delay)
  3841. return curr_delay;
  3842. delay_diff = curr_delay - avg_delay;
  3843. if (delay_diff < 0)
  3844. avg_delay = avg_delay - (qdf_abs(delay_diff) >>
  3845. DP_AVG_DELAY_WEIGHT_DENOM);
  3846. else
  3847. avg_delay = avg_delay + (qdf_abs(delay_diff) >>
  3848. DP_AVG_DELAY_WEIGHT_DENOM);
  3849. return avg_delay;
  3850. }
  3851. #ifdef WLAN_CONFIG_TX_DELAY
  3852. /*
  3853. * dp_tx_compute_cur_delay() - get the current delay
  3854. * @soc: soc handle
  3855. * @vdev: vdev structure for data path state
  3856. * @ts: Tx completion status
  3857. * @curr_delay: current delay
  3858. * @tx_desc: tx descriptor
  3859. * Return: void
  3860. */
  3861. static
  3862. QDF_STATUS dp_tx_compute_cur_delay(struct dp_soc *soc,
  3863. struct dp_vdev *vdev,
  3864. struct hal_tx_completion_status *ts,
  3865. uint32_t *curr_delay,
  3866. struct dp_tx_desc_s *tx_desc)
  3867. {
  3868. QDF_STATUS status = QDF_STATUS_E_FAILURE;
  3869. if (soc->arch_ops.dp_tx_compute_hw_delay)
  3870. status = soc->arch_ops.dp_tx_compute_hw_delay(soc, vdev, ts,
  3871. curr_delay);
  3872. return status;
  3873. }
  3874. #else
  3875. static
  3876. QDF_STATUS dp_tx_compute_cur_delay(struct dp_soc *soc,
  3877. struct dp_vdev *vdev,
  3878. struct hal_tx_completion_status *ts,
  3879. uint32_t *curr_delay,
  3880. struct dp_tx_desc_s *tx_desc)
  3881. {
  3882. int64_t current_timestamp, timestamp_hw_enqueue;
  3883. current_timestamp = qdf_ktime_to_us(qdf_ktime_real_get());
  3884. timestamp_hw_enqueue = qdf_ktime_to_us(tx_desc->timestamp);
  3885. *curr_delay = (uint32_t)(current_timestamp - timestamp_hw_enqueue);
  3886. return QDF_STATUS_SUCCESS;
  3887. }
  3888. #endif
  3889. /* dp_tx_compute_tid_jitter() - compute per tid per ring jitter
  3890. * @jiiter - per tid per ring jitter stats
  3891. * @ts: Tx completion status
  3892. * @vdev - vdev structure for data path state
  3893. * @tx_desc - tx descriptor
  3894. * Return: void
  3895. */
  3896. static void dp_tx_compute_tid_jitter(struct cdp_peer_tid_stats *jitter,
  3897. struct hal_tx_completion_status *ts,
  3898. struct dp_vdev *vdev,
  3899. struct dp_tx_desc_s *tx_desc)
  3900. {
  3901. uint32_t curr_delay, avg_delay, avg_jitter, prev_delay;
  3902. struct dp_soc *soc = vdev->pdev->soc;
  3903. QDF_STATUS status = QDF_STATUS_E_FAILURE;
  3904. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  3905. jitter->tx_drop += 1;
  3906. return;
  3907. }
  3908. status = dp_tx_compute_cur_delay(soc, vdev, ts, &curr_delay,
  3909. tx_desc);
  3910. if (QDF_IS_STATUS_SUCCESS(status)) {
  3911. avg_delay = jitter->tx_avg_delay;
  3912. avg_jitter = jitter->tx_avg_jitter;
  3913. prev_delay = jitter->tx_prev_delay;
  3914. avg_jitter = dp_tx_jitter_get_avg_jitter(curr_delay,
  3915. prev_delay,
  3916. avg_jitter);
  3917. avg_delay = dp_tx_jitter_get_avg_delay(curr_delay, avg_delay);
  3918. jitter->tx_avg_delay = avg_delay;
  3919. jitter->tx_avg_jitter = avg_jitter;
  3920. jitter->tx_prev_delay = curr_delay;
  3921. jitter->tx_total_success += 1;
  3922. } else if (status == QDF_STATUS_E_FAILURE) {
  3923. jitter->tx_avg_err += 1;
  3924. }
  3925. }
  3926. /* dp_tx_update_peer_jitter_stats() - Update the peer jitter stats
  3927. * @txrx_peer: DP peer context
  3928. * @tx_desc: Tx software descriptor
  3929. * @ts: Tx completion status
  3930. * @ring_id: Rx CPU context ID/CPU_ID
  3931. * Return: void
  3932. */
  3933. static void dp_tx_update_peer_jitter_stats(struct dp_txrx_peer *txrx_peer,
  3934. struct dp_tx_desc_s *tx_desc,
  3935. struct hal_tx_completion_status *ts,
  3936. uint8_t ring_id)
  3937. {
  3938. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  3939. struct dp_soc *soc = pdev->soc;
  3940. struct cdp_peer_tid_stats *jitter_stats = NULL;
  3941. uint8_t tid;
  3942. struct cdp_peer_tid_stats *rx_tid = NULL;
  3943. if (qdf_likely(!wlan_cfg_is_peer_jitter_stats_enabled(soc->wlan_cfg_ctx)))
  3944. return;
  3945. tid = ts->tid;
  3946. jitter_stats = txrx_peer->jitter_stats;
  3947. qdf_assert_always(jitter_stats);
  3948. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  3949. /*
  3950. * For non-TID packets use the TID 9
  3951. */
  3952. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3953. tid = CDP_MAX_DATA_TIDS - 1;
  3954. rx_tid = &jitter_stats[tid * CDP_MAX_TXRX_CTX + ring_id];
  3955. dp_tx_compute_tid_jitter(rx_tid,
  3956. ts, txrx_peer->vdev, tx_desc);
  3957. }
  3958. #else
  3959. static void dp_tx_update_peer_jitter_stats(struct dp_txrx_peer *txrx_peer,
  3960. struct dp_tx_desc_s *tx_desc,
  3961. struct hal_tx_completion_status *ts,
  3962. uint8_t ring_id)
  3963. {
  3964. }
  3965. #endif
  3966. #ifdef HW_TX_DELAY_STATS_ENABLE
  3967. /**
  3968. * dp_update_tx_delay_stats() - update the delay stats
  3969. * @vdev: vdev handle
  3970. * @delay: delay in ms or us based on the flag delay_in_us
  3971. * @tid: tid value
  3972. * @mode: type of tx delay mode
  3973. * @ring id: ring number
  3974. * @delay_in_us: flag to indicate whether the delay is in ms or us
  3975. *
  3976. * Return: none
  3977. */
  3978. static inline
  3979. void dp_update_tx_delay_stats(struct dp_vdev *vdev, uint32_t delay, uint8_t tid,
  3980. uint8_t mode, uint8_t ring_id, bool delay_in_us)
  3981. {
  3982. struct cdp_tid_tx_stats *tstats =
  3983. &vdev->stats.tid_tx_stats[ring_id][tid];
  3984. dp_update_delay_stats(tstats, NULL, delay, tid, mode, ring_id,
  3985. delay_in_us);
  3986. }
  3987. #else
  3988. static inline
  3989. void dp_update_tx_delay_stats(struct dp_vdev *vdev, uint32_t delay, uint8_t tid,
  3990. uint8_t mode, uint8_t ring_id, bool delay_in_us)
  3991. {
  3992. struct cdp_tid_tx_stats *tstats =
  3993. &vdev->pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3994. dp_update_delay_stats(tstats, NULL, delay, tid, mode, ring_id,
  3995. delay_in_us);
  3996. }
  3997. #endif
  3998. /**
  3999. * dp_tx_compute_delay() - Compute and fill in all timestamps
  4000. * to pass in correct fields
  4001. *
  4002. * @vdev: pdev handle
  4003. * @tx_desc: tx descriptor
  4004. * @tid: tid value
  4005. * @ring_id: TCL or WBM ring number for transmit path
  4006. * Return: none
  4007. */
  4008. void dp_tx_compute_delay(struct dp_vdev *vdev, struct dp_tx_desc_s *tx_desc,
  4009. uint8_t tid, uint8_t ring_id)
  4010. {
  4011. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  4012. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  4013. uint32_t fwhw_transmit_delay_us;
  4014. if (qdf_likely(!vdev->pdev->delay_stats_flag) &&
  4015. qdf_likely(!dp_is_vdev_tx_delay_stats_enabled(vdev)))
  4016. return;
  4017. if (dp_is_vdev_tx_delay_stats_enabled(vdev)) {
  4018. fwhw_transmit_delay_us =
  4019. qdf_ktime_to_us(qdf_ktime_real_get()) -
  4020. qdf_ktime_to_us(tx_desc->timestamp);
  4021. /*
  4022. * Delay between packet enqueued to HW and Tx completion in us
  4023. */
  4024. dp_update_tx_delay_stats(vdev, fwhw_transmit_delay_us, tid,
  4025. CDP_DELAY_STATS_FW_HW_TRANSMIT,
  4026. ring_id, true);
  4027. /*
  4028. * For MCL, only enqueue to completion delay is required
  4029. * so return if the vdev flag is enabled.
  4030. */
  4031. return;
  4032. }
  4033. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  4034. timestamp_hw_enqueue = qdf_ktime_to_ms(tx_desc->timestamp);
  4035. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  4036. timestamp_hw_enqueue);
  4037. if (!timestamp_hw_enqueue)
  4038. return;
  4039. /*
  4040. * Delay between packet enqueued to HW and Tx completion in ms
  4041. */
  4042. dp_update_tx_delay_stats(vdev, fwhw_transmit_delay, tid,
  4043. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id,
  4044. false);
  4045. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  4046. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  4047. interframe_delay = (uint32_t)(timestamp_ingress -
  4048. vdev->prev_tx_enq_tstamp);
  4049. /*
  4050. * Delay in software enqueue
  4051. */
  4052. dp_update_tx_delay_stats(vdev, sw_enqueue_delay, tid,
  4053. CDP_DELAY_STATS_SW_ENQ, ring_id,
  4054. false);
  4055. /*
  4056. * Update interframe delay stats calculated at hardstart receive point.
  4057. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  4058. * interframe delay will not be calculate correctly for 1st frame.
  4059. * On the other side, this will help in avoiding extra per packet check
  4060. * of !vdev->prev_tx_enq_tstamp.
  4061. */
  4062. dp_update_tx_delay_stats(vdev, interframe_delay, tid,
  4063. CDP_DELAY_STATS_TX_INTERFRAME, ring_id,
  4064. false);
  4065. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  4066. }
  4067. #ifdef DISABLE_DP_STATS
  4068. static
  4069. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf,
  4070. struct dp_txrx_peer *txrx_peer)
  4071. {
  4072. }
  4073. #else
  4074. static inline void
  4075. dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_txrx_peer *txrx_peer)
  4076. {
  4077. enum qdf_proto_subtype subtype = QDF_PROTO_INVALID;
  4078. DPTRACE(qdf_dp_track_noack_check(nbuf, &subtype));
  4079. if (subtype != QDF_PROTO_INVALID)
  4080. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.no_ack_count[subtype],
  4081. 1);
  4082. }
  4083. #endif
  4084. #ifndef QCA_ENHANCED_STATS_SUPPORT
  4085. #ifdef DP_PEER_EXTENDED_API
  4086. static inline uint8_t
  4087. dp_tx_get_mpdu_retry_threshold(struct dp_txrx_peer *txrx_peer)
  4088. {
  4089. return txrx_peer->mpdu_retry_threshold;
  4090. }
  4091. #else
  4092. static inline uint8_t
  4093. dp_tx_get_mpdu_retry_threshold(struct dp_txrx_peer *txrx_peer)
  4094. {
  4095. return 0;
  4096. }
  4097. #endif
  4098. /**
  4099. * dp_tx_update_peer_extd_stats()- Update Tx extended path stats for peer
  4100. *
  4101. * @ts: Tx compltion status
  4102. * @txrx_peer: datapath txrx_peer handle
  4103. *
  4104. * Return: void
  4105. */
  4106. static inline void
  4107. dp_tx_update_peer_extd_stats(struct hal_tx_completion_status *ts,
  4108. struct dp_txrx_peer *txrx_peer)
  4109. {
  4110. uint8_t mcs, pkt_type, dst_mcs_idx;
  4111. uint8_t retry_threshold = dp_tx_get_mpdu_retry_threshold(txrx_peer);
  4112. mcs = ts->mcs;
  4113. pkt_type = ts->pkt_type;
  4114. /* do HW to SW pkt type conversion */
  4115. pkt_type = (pkt_type >= HAL_DOT11_MAX ? DOT11_MAX :
  4116. hal_2_dp_pkt_type_map[pkt_type]);
  4117. dst_mcs_idx = dp_get_mcs_array_index_by_pkt_type_mcs(pkt_type, mcs);
  4118. if (MCS_INVALID_ARRAY_INDEX != dst_mcs_idx)
  4119. DP_PEER_EXTD_STATS_INC(txrx_peer,
  4120. tx.pkt_type[pkt_type].mcs_count[dst_mcs_idx],
  4121. 1);
  4122. DP_PEER_EXTD_STATS_INC(txrx_peer, tx.sgi_count[ts->sgi], 1);
  4123. DP_PEER_EXTD_STATS_INC(txrx_peer, tx.bw[ts->bw], 1);
  4124. DP_PEER_EXTD_STATS_UPD(txrx_peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  4125. DP_PEER_EXTD_STATS_INC(txrx_peer,
  4126. tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  4127. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.stbc, 1, ts->stbc);
  4128. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.ldpc, 1, ts->ldpc);
  4129. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.retries, 1, ts->transmit_cnt > 1);
  4130. if (ts->first_msdu) {
  4131. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.retries_mpdu, 1,
  4132. ts->transmit_cnt > 1);
  4133. if (!retry_threshold)
  4134. return;
  4135. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.mpdu_success_with_retries,
  4136. qdf_do_div(ts->transmit_cnt,
  4137. retry_threshold),
  4138. ts->transmit_cnt > retry_threshold);
  4139. }
  4140. }
  4141. #else
  4142. static inline void
  4143. dp_tx_update_peer_extd_stats(struct hal_tx_completion_status *ts,
  4144. struct dp_txrx_peer *txrx_peer)
  4145. {
  4146. }
  4147. #endif
  4148. /**
  4149. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  4150. * per wbm ring
  4151. *
  4152. * @tx_desc: software descriptor head pointer
  4153. * @ts: Tx completion status
  4154. * @peer: peer handle
  4155. * @ring_id: ring number
  4156. *
  4157. * Return: None
  4158. */
  4159. static inline void
  4160. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  4161. struct hal_tx_completion_status *ts,
  4162. struct dp_txrx_peer *txrx_peer, uint8_t ring_id)
  4163. {
  4164. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  4165. uint8_t tid = ts->tid;
  4166. uint32_t length;
  4167. struct cdp_tid_tx_stats *tid_stats;
  4168. if (!pdev)
  4169. return;
  4170. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  4171. tid = CDP_MAX_DATA_TIDS - 1;
  4172. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  4173. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  4174. dp_err_rl("Release source:%d is not from TQM", ts->release_src);
  4175. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.release_src_not_tqm, 1);
  4176. return;
  4177. }
  4178. length = qdf_nbuf_len(tx_desc->nbuf);
  4179. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4180. if (qdf_unlikely(pdev->delay_stats_flag) ||
  4181. qdf_unlikely(dp_is_vdev_tx_delay_stats_enabled(txrx_peer->vdev)))
  4182. dp_tx_compute_delay(txrx_peer->vdev, tx_desc, tid, ring_id);
  4183. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  4184. tid_stats->tqm_status_cnt[ts->status]++;
  4185. }
  4186. if (qdf_likely(ts->status == HAL_TX_TQM_RR_FRAME_ACKED)) {
  4187. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.retry_count, 1,
  4188. ts->transmit_cnt > 1);
  4189. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.multiple_retry_count,
  4190. 1, ts->transmit_cnt > 2);
  4191. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.ofdma, 1, ts->ofdma);
  4192. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.amsdu_cnt, 1,
  4193. ts->msdu_part_of_amsdu);
  4194. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.non_amsdu_cnt, 1,
  4195. !ts->msdu_part_of_amsdu);
  4196. txrx_peer->stats.per_pkt_stats.tx.last_tx_ts =
  4197. qdf_system_ticks();
  4198. dp_tx_update_peer_extd_stats(ts, txrx_peer);
  4199. return;
  4200. }
  4201. /*
  4202. * tx_failed is ideally supposed to be updated from HTT ppdu
  4203. * completion stats. But in IPQ807X/IPQ6018 chipsets owing to
  4204. * hw limitation there are no completions for failed cases.
  4205. * Hence updating tx_failed from data path. Please note that
  4206. * if tx_failed is fixed to be from ppdu, then this has to be
  4207. * removed
  4208. */
  4209. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4210. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.failed_retry_count, 1,
  4211. ts->transmit_cnt > DP_RETRY_COUNT);
  4212. dp_update_no_ack_stats(tx_desc->nbuf, txrx_peer);
  4213. if (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED) {
  4214. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.age_out, 1);
  4215. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_REM) {
  4216. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.dropped.fw_rem, 1,
  4217. length);
  4218. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX) {
  4219. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_rem_notx, 1);
  4220. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_TX) {
  4221. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_rem_tx, 1);
  4222. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON1) {
  4223. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason1, 1);
  4224. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON2) {
  4225. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason2, 1);
  4226. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON3) {
  4227. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason3, 1);
  4228. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_DISABLE_QUEUE) {
  4229. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4230. tx.dropped.fw_rem_queue_disable, 1);
  4231. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_TILL_NONMATCHING) {
  4232. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4233. tx.dropped.fw_rem_no_match, 1);
  4234. } else if (ts->status == HAL_TX_TQM_RR_DROP_THRESHOLD) {
  4235. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4236. tx.dropped.drop_threshold, 1);
  4237. } else if (ts->status == HAL_TX_TQM_RR_LINK_DESC_UNAVAILABLE) {
  4238. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4239. tx.dropped.drop_link_desc_na, 1);
  4240. } else if (ts->status == HAL_TX_TQM_RR_DROP_OR_INVALID_MSDU) {
  4241. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4242. tx.dropped.invalid_drop, 1);
  4243. } else if (ts->status == HAL_TX_TQM_RR_MULTICAST_DROP) {
  4244. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4245. tx.dropped.mcast_vdev_drop, 1);
  4246. } else {
  4247. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.invalid_rr, 1);
  4248. }
  4249. }
  4250. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4251. /**
  4252. * dp_tx_flow_pool_lock() - take flow pool lock
  4253. * @soc: core txrx main context
  4254. * @tx_desc: tx desc
  4255. *
  4256. * Return: None
  4257. */
  4258. static inline
  4259. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  4260. struct dp_tx_desc_s *tx_desc)
  4261. {
  4262. struct dp_tx_desc_pool_s *pool;
  4263. uint8_t desc_pool_id;
  4264. desc_pool_id = tx_desc->pool_id;
  4265. pool = &soc->tx_desc[desc_pool_id];
  4266. qdf_spin_lock_bh(&pool->flow_pool_lock);
  4267. }
  4268. /**
  4269. * dp_tx_flow_pool_unlock() - release flow pool lock
  4270. * @soc: core txrx main context
  4271. * @tx_desc: tx desc
  4272. *
  4273. * Return: None
  4274. */
  4275. static inline
  4276. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  4277. struct dp_tx_desc_s *tx_desc)
  4278. {
  4279. struct dp_tx_desc_pool_s *pool;
  4280. uint8_t desc_pool_id;
  4281. desc_pool_id = tx_desc->pool_id;
  4282. pool = &soc->tx_desc[desc_pool_id];
  4283. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  4284. }
  4285. #else
  4286. static inline
  4287. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  4288. {
  4289. }
  4290. static inline
  4291. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  4292. {
  4293. }
  4294. #endif
  4295. /**
  4296. * dp_tx_notify_completion() - Notify tx completion for this desc
  4297. * @soc: core txrx main context
  4298. * @vdev: datapath vdev handle
  4299. * @tx_desc: tx desc
  4300. * @netbuf: buffer
  4301. * @status: tx status
  4302. *
  4303. * Return: none
  4304. */
  4305. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  4306. struct dp_vdev *vdev,
  4307. struct dp_tx_desc_s *tx_desc,
  4308. qdf_nbuf_t netbuf,
  4309. uint8_t status)
  4310. {
  4311. void *osif_dev;
  4312. ol_txrx_completion_fp tx_compl_cbk = NULL;
  4313. uint16_t flag = BIT(QDF_TX_RX_STATUS_DOWNLOAD_SUCC);
  4314. qdf_assert(tx_desc);
  4315. if (!vdev ||
  4316. !vdev->osif_vdev) {
  4317. return;
  4318. }
  4319. osif_dev = vdev->osif_vdev;
  4320. tx_compl_cbk = vdev->tx_comp;
  4321. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  4322. flag |= BIT(QDF_TX_RX_STATUS_OK);
  4323. if (tx_compl_cbk)
  4324. tx_compl_cbk(netbuf, osif_dev, flag);
  4325. }
  4326. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  4327. * @pdev: pdev handle
  4328. * @tid: tid value
  4329. * @txdesc_ts: timestamp from txdesc
  4330. * @ppdu_id: ppdu id
  4331. *
  4332. * Return: none
  4333. */
  4334. #ifdef FEATURE_PERPKT_INFO
  4335. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  4336. struct dp_txrx_peer *txrx_peer,
  4337. uint8_t tid,
  4338. uint64_t txdesc_ts,
  4339. uint32_t ppdu_id)
  4340. {
  4341. uint64_t delta_ms;
  4342. struct cdp_tx_sojourn_stats *sojourn_stats;
  4343. struct dp_peer *primary_link_peer = NULL;
  4344. struct dp_soc *link_peer_soc = NULL;
  4345. if (qdf_unlikely(!pdev->enhanced_stats_en))
  4346. return;
  4347. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  4348. tid >= CDP_DATA_TID_MAX))
  4349. return;
  4350. if (qdf_unlikely(!pdev->sojourn_buf))
  4351. return;
  4352. primary_link_peer = dp_get_primary_link_peer_by_id(pdev->soc,
  4353. txrx_peer->peer_id,
  4354. DP_MOD_ID_TX_COMP);
  4355. if (qdf_unlikely(!primary_link_peer))
  4356. return;
  4357. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  4358. qdf_nbuf_data(pdev->sojourn_buf);
  4359. link_peer_soc = primary_link_peer->vdev->pdev->soc;
  4360. sojourn_stats->cookie = (void *)
  4361. dp_monitor_peer_get_peerstats_ctx(link_peer_soc,
  4362. primary_link_peer);
  4363. delta_ms = qdf_ktime_to_ms(qdf_ktime_real_get()) -
  4364. txdesc_ts;
  4365. qdf_ewma_tx_lag_add(&txrx_peer->stats.per_pkt_stats.tx.avg_sojourn_msdu[tid],
  4366. delta_ms);
  4367. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  4368. sojourn_stats->num_msdus[tid] = 1;
  4369. sojourn_stats->avg_sojourn_msdu[tid].internal =
  4370. txrx_peer->stats.per_pkt_stats.tx.avg_sojourn_msdu[tid].internal;
  4371. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  4372. pdev->sojourn_buf, HTT_INVALID_PEER,
  4373. WDI_NO_VAL, pdev->pdev_id);
  4374. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  4375. sojourn_stats->num_msdus[tid] = 0;
  4376. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  4377. dp_peer_unref_delete(primary_link_peer, DP_MOD_ID_TX_COMP);
  4378. }
  4379. #else
  4380. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  4381. struct dp_txrx_peer *txrx_peer,
  4382. uint8_t tid,
  4383. uint64_t txdesc_ts,
  4384. uint32_t ppdu_id)
  4385. {
  4386. }
  4387. #endif
  4388. #ifdef WLAN_FEATURE_PKT_CAPTURE_V2
  4389. /**
  4390. * dp_send_completion_to_pkt_capture() - send tx completion to packet capture
  4391. * @soc: dp_soc handle
  4392. * @desc: Tx Descriptor
  4393. * @ts: HAL Tx completion descriptor contents
  4394. *
  4395. * This function is used to send tx completion to packet capture
  4396. */
  4397. void dp_send_completion_to_pkt_capture(struct dp_soc *soc,
  4398. struct dp_tx_desc_s *desc,
  4399. struct hal_tx_completion_status *ts)
  4400. {
  4401. dp_wdi_event_handler(WDI_EVENT_PKT_CAPTURE_TX_DATA, soc,
  4402. desc, ts->peer_id,
  4403. WDI_NO_VAL, desc->pdev->pdev_id);
  4404. }
  4405. #endif
  4406. /**
  4407. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  4408. * @soc: DP Soc handle
  4409. * @tx_desc: software Tx descriptor
  4410. * @ts : Tx completion status from HAL/HTT descriptor
  4411. *
  4412. * Return: none
  4413. */
  4414. void
  4415. dp_tx_comp_process_desc(struct dp_soc *soc,
  4416. struct dp_tx_desc_s *desc,
  4417. struct hal_tx_completion_status *ts,
  4418. struct dp_txrx_peer *txrx_peer)
  4419. {
  4420. uint64_t time_latency = 0;
  4421. uint16_t peer_id = DP_INVALID_PEER_ID;
  4422. /*
  4423. * m_copy/tx_capture modes are not supported for
  4424. * scatter gather packets
  4425. */
  4426. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  4427. time_latency = (qdf_ktime_to_ms(qdf_ktime_real_get()) -
  4428. qdf_ktime_to_ms(desc->timestamp));
  4429. }
  4430. dp_send_completion_to_pkt_capture(soc, desc, ts);
  4431. if (dp_tx_pkt_tracepoints_enabled())
  4432. qdf_trace_dp_packet(desc->nbuf, QDF_TX,
  4433. desc->msdu_ext_desc ?
  4434. desc->msdu_ext_desc->tso_desc : NULL,
  4435. qdf_ktime_to_ms(desc->timestamp));
  4436. if (!(desc->msdu_ext_desc)) {
  4437. dp_tx_enh_unmap(soc, desc);
  4438. if (txrx_peer)
  4439. peer_id = txrx_peer->peer_id;
  4440. if (QDF_STATUS_SUCCESS ==
  4441. dp_monitor_tx_add_to_comp_queue(soc, desc, ts, peer_id)) {
  4442. return;
  4443. }
  4444. if (QDF_STATUS_SUCCESS ==
  4445. dp_get_completion_indication_for_stack(soc,
  4446. desc->pdev,
  4447. txrx_peer, ts,
  4448. desc->nbuf,
  4449. time_latency)) {
  4450. dp_send_completion_to_stack(soc,
  4451. desc->pdev,
  4452. ts->peer_id,
  4453. ts->ppdu_id,
  4454. desc->nbuf);
  4455. return;
  4456. }
  4457. }
  4458. desc->flags |= DP_TX_DESC_FLAG_COMPLETED_TX;
  4459. dp_tx_comp_free_buf(soc, desc, false);
  4460. }
  4461. #ifdef DISABLE_DP_STATS
  4462. /**
  4463. * dp_tx_update_connectivity_stats() - update tx connectivity stats
  4464. * @soc: core txrx main context
  4465. * @tx_desc: tx desc
  4466. * @status: tx status
  4467. *
  4468. * Return: none
  4469. */
  4470. static inline
  4471. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  4472. struct dp_vdev *vdev,
  4473. struct dp_tx_desc_s *tx_desc,
  4474. uint8_t status)
  4475. {
  4476. }
  4477. #else
  4478. static inline
  4479. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  4480. struct dp_vdev *vdev,
  4481. struct dp_tx_desc_s *tx_desc,
  4482. uint8_t status)
  4483. {
  4484. void *osif_dev;
  4485. ol_txrx_stats_rx_fp stats_cbk;
  4486. uint8_t pkt_type;
  4487. qdf_assert(tx_desc);
  4488. if (!vdev ||
  4489. !vdev->osif_vdev ||
  4490. !vdev->stats_cb)
  4491. return;
  4492. osif_dev = vdev->osif_vdev;
  4493. stats_cbk = vdev->stats_cb;
  4494. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_HOST_FW_SENT, &pkt_type);
  4495. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  4496. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_ACK_CNT,
  4497. &pkt_type);
  4498. }
  4499. #endif
  4500. #if defined(WLAN_FEATURE_TSF_UPLINK_DELAY) || defined(WLAN_CONFIG_TX_DELAY)
  4501. /* Mask for bit29 ~ bit31 */
  4502. #define DP_TX_TS_BIT29_31_MASK 0xE0000000
  4503. /* Timestamp value (unit us) if bit29 is set */
  4504. #define DP_TX_TS_BIT29_SET_VALUE BIT(29)
  4505. /**
  4506. * dp_tx_adjust_enqueue_buffer_ts() - adjust the enqueue buffer_timestamp
  4507. * @ack_ts: OTA ack timestamp, unit us.
  4508. * @enqueue_ts: TCL enqueue TX data to TQM timestamp, unit us.
  4509. * @base_delta_ts: base timestamp delta for ack_ts and enqueue_ts
  4510. *
  4511. * this function will restore the bit29 ~ bit31 3 bits value for
  4512. * buffer_timestamp in wbm2sw ring entry, currently buffer_timestamp only
  4513. * can support 0x7FFF * 1024 us (29 bits), but if the timestamp is >
  4514. * 0x7FFF * 1024 us, bit29~ bit31 will be lost.
  4515. *
  4516. * Return: the adjusted buffer_timestamp value
  4517. */
  4518. static inline
  4519. uint32_t dp_tx_adjust_enqueue_buffer_ts(uint32_t ack_ts,
  4520. uint32_t enqueue_ts,
  4521. uint32_t base_delta_ts)
  4522. {
  4523. uint32_t ack_buffer_ts;
  4524. uint32_t ack_buffer_ts_bit29_31;
  4525. uint32_t adjusted_enqueue_ts;
  4526. /* corresponding buffer_timestamp value when receive OTA Ack */
  4527. ack_buffer_ts = ack_ts - base_delta_ts;
  4528. ack_buffer_ts_bit29_31 = ack_buffer_ts & DP_TX_TS_BIT29_31_MASK;
  4529. /* restore the bit29 ~ bit31 value */
  4530. adjusted_enqueue_ts = ack_buffer_ts_bit29_31 | enqueue_ts;
  4531. /*
  4532. * if actual enqueue_ts value occupied 29 bits only, this enqueue_ts
  4533. * value + real UL delay overflow 29 bits, then 30th bit (bit-29)
  4534. * should not be marked, otherwise extra 0x20000000 us is added to
  4535. * enqueue_ts.
  4536. */
  4537. if (qdf_unlikely(adjusted_enqueue_ts > ack_buffer_ts))
  4538. adjusted_enqueue_ts -= DP_TX_TS_BIT29_SET_VALUE;
  4539. return adjusted_enqueue_ts;
  4540. }
  4541. QDF_STATUS
  4542. dp_tx_compute_hw_delay_us(struct hal_tx_completion_status *ts,
  4543. uint32_t delta_tsf,
  4544. uint32_t *delay_us)
  4545. {
  4546. uint32_t buffer_ts;
  4547. uint32_t delay;
  4548. if (!delay_us)
  4549. return QDF_STATUS_E_INVAL;
  4550. /* Tx_rate_stats_info_valid is 0 and tsf is invalid then */
  4551. if (!ts->valid)
  4552. return QDF_STATUS_E_INVAL;
  4553. /* buffer_timestamp is in units of 1024 us and is [31:13] of
  4554. * WBM_RELEASE_RING_4. After left shift 10 bits, it's
  4555. * valid up to 29 bits.
  4556. */
  4557. buffer_ts = ts->buffer_timestamp << 10;
  4558. buffer_ts = dp_tx_adjust_enqueue_buffer_ts(ts->tsf,
  4559. buffer_ts, delta_tsf);
  4560. delay = ts->tsf - buffer_ts - delta_tsf;
  4561. if (qdf_unlikely(delay & 0x80000000)) {
  4562. dp_err_rl("delay = 0x%x (-ve)\n"
  4563. "release_src = %d\n"
  4564. "ppdu_id = 0x%x\n"
  4565. "peer_id = 0x%x\n"
  4566. "tid = 0x%x\n"
  4567. "release_reason = %d\n"
  4568. "tsf = %u (0x%x)\n"
  4569. "buffer_timestamp = %u (0x%x)\n"
  4570. "delta_tsf = %u (0x%x)\n",
  4571. delay, ts->release_src, ts->ppdu_id, ts->peer_id,
  4572. ts->tid, ts->status, ts->tsf, ts->tsf,
  4573. ts->buffer_timestamp, ts->buffer_timestamp,
  4574. delta_tsf, delta_tsf);
  4575. delay = 0;
  4576. goto end;
  4577. }
  4578. delay &= 0x1FFFFFFF; /* mask 29 BITS */
  4579. if (delay > 0x1000000) {
  4580. dp_info_rl("----------------------\n"
  4581. "Tx completion status:\n"
  4582. "----------------------\n"
  4583. "release_src = %d\n"
  4584. "ppdu_id = 0x%x\n"
  4585. "release_reason = %d\n"
  4586. "tsf = %u (0x%x)\n"
  4587. "buffer_timestamp = %u (0x%x)\n"
  4588. "delta_tsf = %u (0x%x)\n",
  4589. ts->release_src, ts->ppdu_id, ts->status,
  4590. ts->tsf, ts->tsf, ts->buffer_timestamp,
  4591. ts->buffer_timestamp, delta_tsf, delta_tsf);
  4592. return QDF_STATUS_E_FAILURE;
  4593. }
  4594. end:
  4595. *delay_us = delay;
  4596. return QDF_STATUS_SUCCESS;
  4597. }
  4598. void dp_set_delta_tsf(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4599. uint32_t delta_tsf)
  4600. {
  4601. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4602. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4603. DP_MOD_ID_CDP);
  4604. if (!vdev) {
  4605. dp_err_rl("vdev %d does not exist", vdev_id);
  4606. return;
  4607. }
  4608. vdev->delta_tsf = delta_tsf;
  4609. dp_debug("vdev id %u delta_tsf %u", vdev_id, delta_tsf);
  4610. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4611. }
  4612. #endif
  4613. #ifdef WLAN_FEATURE_TSF_UPLINK_DELAY
  4614. QDF_STATUS dp_set_tsf_ul_delay_report(struct cdp_soc_t *soc_hdl,
  4615. uint8_t vdev_id, bool enable)
  4616. {
  4617. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4618. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4619. DP_MOD_ID_CDP);
  4620. if (!vdev) {
  4621. dp_err_rl("vdev %d does not exist", vdev_id);
  4622. return QDF_STATUS_E_FAILURE;
  4623. }
  4624. qdf_atomic_set(&vdev->ul_delay_report, enable);
  4625. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4626. return QDF_STATUS_SUCCESS;
  4627. }
  4628. QDF_STATUS dp_get_uplink_delay(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4629. uint32_t *val)
  4630. {
  4631. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4632. struct dp_vdev *vdev;
  4633. uint32_t delay_accum;
  4634. uint32_t pkts_accum;
  4635. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_CDP);
  4636. if (!vdev) {
  4637. dp_err_rl("vdev %d does not exist", vdev_id);
  4638. return QDF_STATUS_E_FAILURE;
  4639. }
  4640. if (!qdf_atomic_read(&vdev->ul_delay_report)) {
  4641. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4642. return QDF_STATUS_E_FAILURE;
  4643. }
  4644. /* Average uplink delay based on current accumulated values */
  4645. delay_accum = qdf_atomic_read(&vdev->ul_delay_accum);
  4646. pkts_accum = qdf_atomic_read(&vdev->ul_pkts_accum);
  4647. *val = delay_accum / pkts_accum;
  4648. dp_debug("uplink_delay %u delay_accum %u pkts_accum %u", *val,
  4649. delay_accum, pkts_accum);
  4650. /* Reset accumulated values to 0 */
  4651. qdf_atomic_set(&vdev->ul_delay_accum, 0);
  4652. qdf_atomic_set(&vdev->ul_pkts_accum, 0);
  4653. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4654. return QDF_STATUS_SUCCESS;
  4655. }
  4656. static void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  4657. struct hal_tx_completion_status *ts)
  4658. {
  4659. uint32_t ul_delay;
  4660. if (qdf_unlikely(!vdev)) {
  4661. dp_info_rl("vdev is null or delete in progress");
  4662. return;
  4663. }
  4664. if (!qdf_atomic_read(&vdev->ul_delay_report))
  4665. return;
  4666. if (QDF_IS_STATUS_ERROR(dp_tx_compute_hw_delay_us(ts,
  4667. vdev->delta_tsf,
  4668. &ul_delay)))
  4669. return;
  4670. ul_delay /= 1000; /* in unit of ms */
  4671. qdf_atomic_add(ul_delay, &vdev->ul_delay_accum);
  4672. qdf_atomic_inc(&vdev->ul_pkts_accum);
  4673. }
  4674. #else /* !WLAN_FEATURE_TSF_UPLINK_DELAY */
  4675. static inline
  4676. void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  4677. struct hal_tx_completion_status *ts)
  4678. {
  4679. }
  4680. #endif /* WLAN_FEATURE_TSF_UPLINK_DELAY */
  4681. /**
  4682. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  4683. * @soc: DP soc handle
  4684. * @tx_desc: software descriptor head pointer
  4685. * @ts: Tx completion status
  4686. * @txrx_peer: txrx peer handle
  4687. * @ring_id: ring number
  4688. *
  4689. * Return: none
  4690. */
  4691. void dp_tx_comp_process_tx_status(struct dp_soc *soc,
  4692. struct dp_tx_desc_s *tx_desc,
  4693. struct hal_tx_completion_status *ts,
  4694. struct dp_txrx_peer *txrx_peer,
  4695. uint8_t ring_id)
  4696. {
  4697. uint32_t length;
  4698. qdf_ether_header_t *eh;
  4699. struct dp_vdev *vdev = NULL;
  4700. qdf_nbuf_t nbuf = tx_desc->nbuf;
  4701. enum qdf_dp_tx_rx_status dp_status;
  4702. if (!nbuf) {
  4703. dp_info_rl("invalid tx descriptor. nbuf NULL");
  4704. goto out;
  4705. }
  4706. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  4707. length = dp_tx_get_pkt_len(tx_desc);
  4708. dp_status = dp_tx_hw_to_qdf(ts->status);
  4709. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  4710. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  4711. QDF_TRACE_DEFAULT_PDEV_ID,
  4712. qdf_nbuf_data_addr(nbuf),
  4713. sizeof(qdf_nbuf_data(nbuf)),
  4714. tx_desc->id, ts->status, dp_status));
  4715. dp_tx_comp_debug("-------------------- \n"
  4716. "Tx Completion Stats: \n"
  4717. "-------------------- \n"
  4718. "ack_frame_rssi = %d \n"
  4719. "first_msdu = %d \n"
  4720. "last_msdu = %d \n"
  4721. "msdu_part_of_amsdu = %d \n"
  4722. "rate_stats valid = %d \n"
  4723. "bw = %d \n"
  4724. "pkt_type = %d \n"
  4725. "stbc = %d \n"
  4726. "ldpc = %d \n"
  4727. "sgi = %d \n"
  4728. "mcs = %d \n"
  4729. "ofdma = %d \n"
  4730. "tones_in_ru = %d \n"
  4731. "tsf = %d \n"
  4732. "ppdu_id = %d \n"
  4733. "transmit_cnt = %d \n"
  4734. "tid = %d \n"
  4735. "peer_id = %d\n"
  4736. "tx_status = %d\n",
  4737. ts->ack_frame_rssi, ts->first_msdu,
  4738. ts->last_msdu, ts->msdu_part_of_amsdu,
  4739. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  4740. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  4741. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  4742. ts->transmit_cnt, ts->tid, ts->peer_id,
  4743. ts->status);
  4744. /* Update SoC level stats */
  4745. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  4746. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  4747. if (!txrx_peer) {
  4748. dp_info_rl("peer is null or deletion in progress");
  4749. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  4750. goto out;
  4751. }
  4752. vdev = txrx_peer->vdev;
  4753. dp_tx_update_connectivity_stats(soc, vdev, tx_desc, ts->status);
  4754. dp_tx_update_uplink_delay(soc, vdev, ts);
  4755. /* check tx complete notification */
  4756. if (qdf_nbuf_tx_notify_comp_get(nbuf))
  4757. dp_tx_notify_completion(soc, vdev, tx_desc,
  4758. nbuf, ts->status);
  4759. /* Update per-packet stats for mesh mode */
  4760. if (qdf_unlikely(vdev->mesh_vdev) &&
  4761. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  4762. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  4763. /* Update peer level stats */
  4764. if (qdf_unlikely(txrx_peer->bss_peer &&
  4765. vdev->opmode == wlan_op_mode_ap)) {
  4766. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  4767. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.mcast, 1,
  4768. length);
  4769. if (txrx_peer->vdev->tx_encap_type ==
  4770. htt_cmn_pkt_type_ethernet &&
  4771. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  4772. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  4773. tx.bcast, 1,
  4774. length);
  4775. }
  4776. }
  4777. } else {
  4778. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.ucast, 1, length);
  4779. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED) {
  4780. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.tx_success,
  4781. 1, length);
  4782. if (qdf_unlikely(txrx_peer->in_twt)) {
  4783. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  4784. tx.tx_success_twt,
  4785. 1, length);
  4786. }
  4787. }
  4788. }
  4789. dp_tx_update_peer_stats(tx_desc, ts, txrx_peer, ring_id);
  4790. dp_tx_update_peer_delay_stats(txrx_peer, tx_desc, ts, ring_id);
  4791. dp_tx_update_peer_jitter_stats(txrx_peer, tx_desc, ts, ring_id);
  4792. dp_tx_update_peer_sawf_stats(soc, vdev, txrx_peer, tx_desc,
  4793. ts, ts->tid);
  4794. dp_tx_send_pktlog(soc, vdev->pdev, tx_desc, nbuf, dp_status);
  4795. #ifdef QCA_SUPPORT_RDK_STATS
  4796. if (soc->peerstats_enabled)
  4797. dp_tx_sojourn_stats_process(vdev->pdev, txrx_peer, ts->tid,
  4798. qdf_ktime_to_ms(tx_desc->timestamp),
  4799. ts->ppdu_id);
  4800. #endif
  4801. out:
  4802. return;
  4803. }
  4804. #if defined(QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT) && \
  4805. defined(QCA_ENHANCED_STATS_SUPPORT)
  4806. /*
  4807. * dp_tx_update_peer_basic_stats(): Update peer basic stats
  4808. * @txrx_peer: Datapath txrx_peer handle
  4809. * @length: Length of the packet
  4810. * @tx_status: Tx status from TQM/FW
  4811. * @update: enhanced flag value present in dp_pdev
  4812. *
  4813. * Return: none
  4814. */
  4815. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4816. uint32_t length, uint8_t tx_status,
  4817. bool update)
  4818. {
  4819. if (update || (!txrx_peer->hw_txrx_stats_en)) {
  4820. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4821. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4822. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4823. }
  4824. }
  4825. #elif defined(QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT)
  4826. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4827. uint32_t length, uint8_t tx_status,
  4828. bool update)
  4829. {
  4830. if (!txrx_peer->hw_txrx_stats_en) {
  4831. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4832. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4833. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4834. }
  4835. }
  4836. #else
  4837. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4838. uint32_t length, uint8_t tx_status,
  4839. bool update)
  4840. {
  4841. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4842. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4843. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4844. }
  4845. #endif
  4846. /*
  4847. * dp_tx_prefetch_next_nbuf_data(): Prefetch nbuf and nbuf data
  4848. * @nbuf: skb buffer
  4849. *
  4850. * Return: none
  4851. */
  4852. #ifdef QCA_DP_RX_NBUF_AND_NBUF_DATA_PREFETCH
  4853. static inline
  4854. void dp_tx_prefetch_next_nbuf_data(struct dp_tx_desc_s *next)
  4855. {
  4856. qdf_nbuf_t nbuf = NULL;
  4857. if (next)
  4858. nbuf = next->nbuf;
  4859. if (nbuf)
  4860. qdf_prefetch(nbuf);
  4861. }
  4862. #else
  4863. static inline
  4864. void dp_tx_prefetch_next_nbuf_data(struct dp_tx_desc_s *next)
  4865. {
  4866. }
  4867. #endif
  4868. /**
  4869. * dp_tx_mcast_reinject_handler() - Tx reinjected multicast packets handler
  4870. * @soc: core txrx main context
  4871. * @desc: software descriptor
  4872. *
  4873. * Return: true when packet is reinjected
  4874. */
  4875. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  4876. defined(WLAN_MCAST_MLO)
  4877. static inline bool
  4878. dp_tx_mcast_reinject_handler(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  4879. {
  4880. struct dp_vdev *vdev = NULL;
  4881. if (desc->tx_status == HAL_TX_TQM_RR_MULTICAST_DROP) {
  4882. if (!soc->arch_ops.dp_tx_mcast_handler ||
  4883. !soc->arch_ops.dp_tx_is_mcast_primary)
  4884. return false;
  4885. vdev = dp_vdev_get_ref_by_id(soc, desc->vdev_id,
  4886. DP_MOD_ID_REINJECT);
  4887. if (qdf_unlikely(!vdev)) {
  4888. dp_tx_comp_info_rl("Unable to get vdev ref %d",
  4889. desc->id);
  4890. return false;
  4891. }
  4892. if (!(soc->arch_ops.dp_tx_is_mcast_primary(soc, vdev))) {
  4893. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_REINJECT);
  4894. return false;
  4895. }
  4896. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  4897. qdf_nbuf_len(desc->nbuf));
  4898. soc->arch_ops.dp_tx_mcast_handler(soc, vdev, desc->nbuf);
  4899. dp_tx_desc_release(desc, desc->pool_id);
  4900. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_REINJECT);
  4901. return true;
  4902. }
  4903. return false;
  4904. }
  4905. #else
  4906. static inline bool
  4907. dp_tx_mcast_reinject_handler(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  4908. {
  4909. return false;
  4910. }
  4911. #endif
  4912. #ifdef QCA_DP_TX_NBUF_LIST_FREE
  4913. static inline void
  4914. dp_tx_nbuf_queue_head_init(qdf_nbuf_queue_head_t *nbuf_queue_head)
  4915. {
  4916. qdf_nbuf_queue_head_init(nbuf_queue_head);
  4917. }
  4918. static inline void
  4919. dp_tx_nbuf_dev_queue_free(qdf_nbuf_queue_head_t *nbuf_queue_head,
  4920. struct dp_tx_desc_s *desc)
  4921. {
  4922. qdf_nbuf_t nbuf = NULL;
  4923. nbuf = desc->nbuf;
  4924. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_FAST))
  4925. qdf_nbuf_dev_queue_head(nbuf_queue_head, nbuf);
  4926. else
  4927. qdf_nbuf_free(nbuf);
  4928. }
  4929. static inline void
  4930. dp_tx_nbuf_dev_kfree_list(qdf_nbuf_queue_head_t *nbuf_queue_head)
  4931. {
  4932. qdf_nbuf_dev_kfree_list(nbuf_queue_head);
  4933. }
  4934. #else
  4935. static inline void
  4936. dp_tx_nbuf_queue_head_init(qdf_nbuf_queue_head_t *nbuf_queue_head)
  4937. {
  4938. }
  4939. static inline void
  4940. dp_tx_nbuf_dev_queue_free(qdf_nbuf_queue_head_t *nbuf_queue_head,
  4941. struct dp_tx_desc_s *desc)
  4942. {
  4943. qdf_nbuf_free(desc->nbuf);
  4944. }
  4945. static inline void
  4946. dp_tx_nbuf_dev_kfree_list(qdf_nbuf_queue_head_t *nbuf_queue_head)
  4947. {
  4948. }
  4949. #endif
  4950. /**
  4951. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  4952. * @soc: core txrx main context
  4953. * @comp_head: software descriptor head pointer
  4954. * @ring_id: ring number
  4955. *
  4956. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  4957. * and release the software descriptors after processing is complete
  4958. *
  4959. * Return: none
  4960. */
  4961. void
  4962. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  4963. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  4964. {
  4965. struct dp_tx_desc_s *desc;
  4966. struct dp_tx_desc_s *next;
  4967. struct hal_tx_completion_status ts;
  4968. struct dp_txrx_peer *txrx_peer = NULL;
  4969. uint16_t peer_id = DP_INVALID_PEER;
  4970. dp_txrx_ref_handle txrx_ref_handle = NULL;
  4971. qdf_nbuf_queue_head_t h;
  4972. desc = comp_head;
  4973. dp_tx_nbuf_queue_head_init(&h);
  4974. while (desc) {
  4975. next = desc->next;
  4976. dp_tx_prefetch_next_nbuf_data(next);
  4977. if (peer_id != desc->peer_id) {
  4978. if (txrx_peer)
  4979. dp_txrx_peer_unref_delete(txrx_ref_handle,
  4980. DP_MOD_ID_TX_COMP);
  4981. peer_id = desc->peer_id;
  4982. txrx_peer =
  4983. dp_txrx_peer_get_ref_by_id(soc, peer_id,
  4984. &txrx_ref_handle,
  4985. DP_MOD_ID_TX_COMP);
  4986. }
  4987. if (dp_tx_mcast_reinject_handler(soc, desc)) {
  4988. desc = next;
  4989. continue;
  4990. }
  4991. if (desc->flags & DP_TX_DESC_FLAG_PPEDS) {
  4992. if (qdf_likely(txrx_peer))
  4993. dp_tx_update_peer_basic_stats(txrx_peer,
  4994. desc->length,
  4995. desc->tx_status,
  4996. false);
  4997. dp_tx_nbuf_dev_queue_free(&h, desc);
  4998. dp_ppeds_tx_desc_free(soc, desc);
  4999. desc = next;
  5000. continue;
  5001. }
  5002. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  5003. struct dp_pdev *pdev = desc->pdev;
  5004. if (qdf_likely(txrx_peer))
  5005. dp_tx_update_peer_basic_stats(txrx_peer,
  5006. desc->length,
  5007. desc->tx_status,
  5008. false);
  5009. qdf_assert(pdev);
  5010. dp_tx_outstanding_dec(pdev);
  5011. /*
  5012. * Calling a QDF WRAPPER here is creating significant
  5013. * performance impact so avoided the wrapper call here
  5014. */
  5015. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  5016. desc->id, DP_TX_COMP_UNMAP);
  5017. dp_tx_nbuf_unmap(soc, desc);
  5018. dp_tx_nbuf_dev_queue_free(&h, desc);
  5019. dp_tx_desc_free(soc, desc, desc->pool_id);
  5020. desc = next;
  5021. continue;
  5022. }
  5023. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  5024. dp_tx_comp_process_tx_status(soc, desc, &ts, txrx_peer,
  5025. ring_id);
  5026. dp_tx_comp_process_desc(soc, desc, &ts, txrx_peer);
  5027. dp_tx_desc_release(desc, desc->pool_id);
  5028. desc = next;
  5029. }
  5030. dp_tx_nbuf_dev_kfree_list(&h);
  5031. if (txrx_peer)
  5032. dp_txrx_peer_unref_delete(txrx_ref_handle, DP_MOD_ID_TX_COMP);
  5033. }
  5034. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  5035. static inline
  5036. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  5037. int max_reap_limit)
  5038. {
  5039. bool limit_hit = false;
  5040. limit_hit =
  5041. (num_reaped >= max_reap_limit) ? true : false;
  5042. if (limit_hit)
  5043. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  5044. return limit_hit;
  5045. }
  5046. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  5047. {
  5048. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  5049. }
  5050. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  5051. {
  5052. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  5053. return cfg->tx_comp_loop_pkt_limit;
  5054. }
  5055. #else
  5056. static inline
  5057. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  5058. int max_reap_limit)
  5059. {
  5060. return false;
  5061. }
  5062. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  5063. {
  5064. return false;
  5065. }
  5066. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  5067. {
  5068. return 0;
  5069. }
  5070. #endif
  5071. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  5072. static inline int
  5073. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  5074. int *max_reap_limit)
  5075. {
  5076. return soc->arch_ops.dp_srng_test_and_update_nf_params(soc, dp_srng,
  5077. max_reap_limit);
  5078. }
  5079. #else
  5080. static inline int
  5081. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  5082. int *max_reap_limit)
  5083. {
  5084. return 0;
  5085. }
  5086. #endif
  5087. #ifdef DP_TX_TRACKING
  5088. void dp_tx_desc_check_corruption(struct dp_tx_desc_s *tx_desc)
  5089. {
  5090. if ((tx_desc->magic != DP_TX_MAGIC_PATTERN_INUSE) &&
  5091. (tx_desc->magic != DP_TX_MAGIC_PATTERN_FREE)) {
  5092. dp_err_rl("tx_desc %u is corrupted", tx_desc->id);
  5093. qdf_trigger_self_recovery(NULL, QDF_TX_DESC_LEAK);
  5094. }
  5095. }
  5096. #endif
  5097. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  5098. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  5099. uint32_t quota)
  5100. {
  5101. void *tx_comp_hal_desc;
  5102. void *last_prefetched_hw_desc = NULL;
  5103. struct dp_tx_desc_s *last_prefetched_sw_desc = NULL;
  5104. hal_soc_handle_t hal_soc;
  5105. uint8_t buffer_src;
  5106. struct dp_tx_desc_s *tx_desc = NULL;
  5107. struct dp_tx_desc_s *head_desc = NULL;
  5108. struct dp_tx_desc_s *tail_desc = NULL;
  5109. uint32_t num_processed = 0;
  5110. uint32_t count;
  5111. uint32_t num_avail_for_reap = 0;
  5112. bool force_break = false;
  5113. struct dp_srng *tx_comp_ring = &soc->tx_comp_ring[ring_id];
  5114. int max_reap_limit, ring_near_full;
  5115. uint32_t num_entries;
  5116. DP_HIST_INIT();
  5117. num_entries = hal_srng_get_num_entries(soc->hal_soc, hal_ring_hdl);
  5118. more_data:
  5119. hal_soc = soc->hal_soc;
  5120. /* Re-initialize local variables to be re-used */
  5121. head_desc = NULL;
  5122. tail_desc = NULL;
  5123. count = 0;
  5124. max_reap_limit = dp_tx_comp_get_loop_pkt_limit(soc);
  5125. ring_near_full = dp_srng_test_and_update_nf_params(soc, tx_comp_ring,
  5126. &max_reap_limit);
  5127. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  5128. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  5129. return 0;
  5130. }
  5131. if (!num_avail_for_reap)
  5132. num_avail_for_reap = hal_srng_dst_num_valid(hal_soc,
  5133. hal_ring_hdl, 0);
  5134. if (num_avail_for_reap >= quota)
  5135. num_avail_for_reap = quota;
  5136. dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap);
  5137. last_prefetched_hw_desc = dp_srng_dst_prefetch_32_byte_desc(hal_soc,
  5138. hal_ring_hdl,
  5139. num_avail_for_reap);
  5140. /* Find head descriptor from completion ring */
  5141. while (qdf_likely(num_avail_for_reap--)) {
  5142. tx_comp_hal_desc = dp_srng_dst_get_next(soc, hal_ring_hdl);
  5143. if (qdf_unlikely(!tx_comp_hal_desc))
  5144. break;
  5145. buffer_src = hal_tx_comp_get_buffer_source(hal_soc,
  5146. tx_comp_hal_desc);
  5147. /* If this buffer was not released by TQM or FW, then it is not
  5148. * Tx completion indication, assert */
  5149. if (qdf_unlikely(buffer_src !=
  5150. HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  5151. (qdf_unlikely(buffer_src !=
  5152. HAL_TX_COMP_RELEASE_SOURCE_FW))) {
  5153. uint8_t wbm_internal_error;
  5154. dp_err_rl(
  5155. "Tx comp release_src != TQM | FW but from %d",
  5156. buffer_src);
  5157. hal_dump_comp_desc(tx_comp_hal_desc);
  5158. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  5159. /* When WBM sees NULL buffer_addr_info in any of
  5160. * ingress rings it sends an error indication,
  5161. * with wbm_internal_error=1, to a specific ring.
  5162. * The WBM2SW ring used to indicate these errors is
  5163. * fixed in HW, and that ring is being used as Tx
  5164. * completion ring. These errors are not related to
  5165. * Tx completions, and should just be ignored
  5166. */
  5167. wbm_internal_error = hal_get_wbm_internal_error(
  5168. hal_soc,
  5169. tx_comp_hal_desc);
  5170. if (wbm_internal_error) {
  5171. dp_err_rl("Tx comp wbm_internal_error!!");
  5172. DP_STATS_INC(soc, tx.wbm_internal_error[WBM_INT_ERROR_ALL], 1);
  5173. if (HAL_TX_COMP_RELEASE_SOURCE_REO ==
  5174. buffer_src)
  5175. dp_handle_wbm_internal_error(
  5176. soc,
  5177. tx_comp_hal_desc,
  5178. hal_tx_comp_get_buffer_type(
  5179. tx_comp_hal_desc));
  5180. } else {
  5181. dp_err_rl("Tx comp wbm_internal_error false");
  5182. DP_STATS_INC(soc, tx.non_wbm_internal_err, 1);
  5183. }
  5184. continue;
  5185. }
  5186. soc->arch_ops.tx_comp_get_params_from_hal_desc(soc,
  5187. tx_comp_hal_desc,
  5188. &tx_desc);
  5189. if (qdf_unlikely(!tx_desc)) {
  5190. dp_err("unable to retrieve tx_desc!");
  5191. hal_dump_comp_desc(tx_comp_hal_desc);
  5192. DP_STATS_INC(soc, tx.invalid_tx_comp_desc, 1);
  5193. QDF_BUG(0);
  5194. continue;
  5195. }
  5196. tx_desc->buffer_src = buffer_src;
  5197. if (tx_desc->flags & DP_TX_DESC_FLAG_PPEDS)
  5198. goto add_to_pool2;
  5199. /*
  5200. * If the release source is FW, process the HTT status
  5201. */
  5202. if (qdf_unlikely(buffer_src ==
  5203. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  5204. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  5205. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  5206. htt_tx_status);
  5207. /* Collect hw completion contents */
  5208. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  5209. &tx_desc->comp, 1);
  5210. soc->arch_ops.dp_tx_process_htt_completion(
  5211. soc,
  5212. tx_desc,
  5213. htt_tx_status,
  5214. ring_id);
  5215. } else {
  5216. tx_desc->tx_status =
  5217. hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  5218. tx_desc->buffer_src = buffer_src;
  5219. /*
  5220. * If the fast completion mode is enabled extended
  5221. * metadata from descriptor is not copied
  5222. */
  5223. if (qdf_likely(tx_desc->flags &
  5224. DP_TX_DESC_FLAG_SIMPLE))
  5225. goto add_to_pool;
  5226. /*
  5227. * If the descriptor is already freed in vdev_detach,
  5228. * continue to next descriptor
  5229. */
  5230. if (qdf_unlikely
  5231. ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) &&
  5232. !tx_desc->flags)) {
  5233. dp_tx_comp_info_rl("Descriptor freed in vdev_detach %d",
  5234. tx_desc->id);
  5235. DP_STATS_INC(soc, tx.tx_comp_exception, 1);
  5236. dp_tx_desc_check_corruption(tx_desc);
  5237. continue;
  5238. }
  5239. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  5240. dp_tx_comp_info_rl("pdev in down state %d",
  5241. tx_desc->id);
  5242. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  5243. dp_tx_comp_free_buf(soc, tx_desc, false);
  5244. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  5245. goto next_desc;
  5246. }
  5247. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  5248. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  5249. dp_tx_comp_alert("Txdesc invalid, flgs = %x,id = %d",
  5250. tx_desc->flags, tx_desc->id);
  5251. qdf_assert_always(0);
  5252. }
  5253. /* Collect hw completion contents */
  5254. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  5255. &tx_desc->comp, 1);
  5256. add_to_pool:
  5257. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  5258. add_to_pool2:
  5259. /* First ring descriptor on the cycle */
  5260. if (!head_desc) {
  5261. head_desc = tx_desc;
  5262. tail_desc = tx_desc;
  5263. }
  5264. tail_desc->next = tx_desc;
  5265. tx_desc->next = NULL;
  5266. tail_desc = tx_desc;
  5267. }
  5268. next_desc:
  5269. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  5270. /*
  5271. * Processed packet count is more than given quota
  5272. * stop to processing
  5273. */
  5274. count++;
  5275. dp_tx_prefetch_hw_sw_nbuf_desc(soc, hal_soc,
  5276. num_avail_for_reap,
  5277. hal_ring_hdl,
  5278. &last_prefetched_hw_desc,
  5279. &last_prefetched_sw_desc);
  5280. if (dp_tx_comp_loop_pkt_limit_hit(soc, count, max_reap_limit))
  5281. break;
  5282. }
  5283. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  5284. /* Process the reaped descriptors */
  5285. if (head_desc)
  5286. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  5287. DP_STATS_INC(soc, tx.tx_comp[ring_id], count);
  5288. /*
  5289. * If we are processing in near-full condition, there are 3 scenario
  5290. * 1) Ring entries has reached critical state
  5291. * 2) Ring entries are still near high threshold
  5292. * 3) Ring entries are below the safe level
  5293. *
  5294. * One more loop will move the state to normal processing and yield
  5295. */
  5296. if (ring_near_full)
  5297. goto more_data;
  5298. if (dp_tx_comp_enable_eol_data_check(soc)) {
  5299. if (num_processed >= quota)
  5300. force_break = true;
  5301. if (!force_break &&
  5302. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  5303. hal_ring_hdl)) {
  5304. DP_STATS_INC(soc, tx.hp_oos2, 1);
  5305. if (!hif_exec_should_yield(soc->hif_handle,
  5306. int_ctx->dp_intr_id))
  5307. goto more_data;
  5308. num_avail_for_reap =
  5309. hal_srng_dst_num_valid_locked(soc->hal_soc,
  5310. hal_ring_hdl,
  5311. true);
  5312. if (qdf_unlikely(num_entries &&
  5313. (num_avail_for_reap >=
  5314. num_entries >> 1))) {
  5315. DP_STATS_INC(soc, tx.near_full, 1);
  5316. goto more_data;
  5317. }
  5318. }
  5319. }
  5320. DP_TX_HIST_STATS_PER_PDEV();
  5321. return num_processed;
  5322. }
  5323. #ifdef FEATURE_WLAN_TDLS
  5324. qdf_nbuf_t dp_tx_non_std(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  5325. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  5326. {
  5327. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  5328. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  5329. DP_MOD_ID_TDLS);
  5330. if (!vdev) {
  5331. dp_err("vdev handle for id %d is NULL", vdev_id);
  5332. return NULL;
  5333. }
  5334. if (tx_spec & OL_TX_SPEC_NO_FREE)
  5335. vdev->is_tdls_frame = true;
  5336. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  5337. return dp_tx_send(soc_hdl, vdev_id, msdu_list);
  5338. }
  5339. #endif
  5340. /**
  5341. * dp_tx_vdev_attach() - attach vdev to dp tx
  5342. * @vdev: virtual device instance
  5343. *
  5344. * Return: QDF_STATUS_SUCCESS: success
  5345. * QDF_STATUS_E_RESOURCES: Error return
  5346. */
  5347. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  5348. {
  5349. int pdev_id;
  5350. /*
  5351. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  5352. */
  5353. DP_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  5354. DP_TCL_METADATA_TYPE_VDEV_BASED);
  5355. DP_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  5356. vdev->vdev_id);
  5357. pdev_id =
  5358. dp_get_target_pdev_id_for_host_pdev_id(vdev->pdev->soc,
  5359. vdev->pdev->pdev_id);
  5360. DP_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata, pdev_id);
  5361. /*
  5362. * Set HTT Extension Valid bit to 0 by default
  5363. */
  5364. DP_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  5365. dp_tx_vdev_update_search_flags(vdev);
  5366. return QDF_STATUS_SUCCESS;
  5367. }
  5368. #ifndef FEATURE_WDS
  5369. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  5370. {
  5371. return false;
  5372. }
  5373. #endif
  5374. /**
  5375. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  5376. * @vdev: virtual device instance
  5377. *
  5378. * Return: void
  5379. *
  5380. */
  5381. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  5382. {
  5383. struct dp_soc *soc = vdev->pdev->soc;
  5384. /*
  5385. * Enable both AddrY (SA based search) and AddrX (Da based search)
  5386. * for TDLS link
  5387. *
  5388. * Enable AddrY (SA based search) only for non-WDS STA and
  5389. * ProxySTA VAP (in HKv1) modes.
  5390. *
  5391. * In all other VAP modes, only DA based search should be
  5392. * enabled
  5393. */
  5394. if (vdev->opmode == wlan_op_mode_sta &&
  5395. vdev->tdls_link_connected)
  5396. vdev->hal_desc_addr_search_flags =
  5397. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  5398. else if ((vdev->opmode == wlan_op_mode_sta) &&
  5399. !dp_tx_da_search_override(vdev))
  5400. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  5401. else
  5402. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  5403. if (vdev->opmode == wlan_op_mode_sta && !vdev->tdls_link_connected)
  5404. vdev->search_type = soc->sta_mode_search_policy;
  5405. else
  5406. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  5407. }
  5408. static inline bool
  5409. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  5410. struct dp_vdev *vdev,
  5411. struct dp_tx_desc_s *tx_desc)
  5412. {
  5413. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  5414. return false;
  5415. /*
  5416. * if vdev is given, then only check whether desc
  5417. * vdev match. if vdev is NULL, then check whether
  5418. * desc pdev match.
  5419. */
  5420. return vdev ? (tx_desc->vdev_id == vdev->vdev_id) :
  5421. (tx_desc->pdev == pdev);
  5422. }
  5423. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  5424. /**
  5425. * dp_tx_desc_flush() - release resources associated
  5426. * to TX Desc
  5427. *
  5428. * @dp_pdev: Handle to DP pdev structure
  5429. * @vdev: virtual device instance
  5430. * NULL: no specific Vdev is required and check all allcated TX desc
  5431. * on this pdev.
  5432. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  5433. *
  5434. * @force_free:
  5435. * true: flush the TX desc.
  5436. * false: only reset the Vdev in each allocated TX desc
  5437. * that associated to current Vdev.
  5438. *
  5439. * This function will go through the TX desc pool to flush
  5440. * the outstanding TX data or reset Vdev to NULL in associated TX
  5441. * Desc.
  5442. */
  5443. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  5444. bool force_free)
  5445. {
  5446. uint8_t i;
  5447. uint32_t j;
  5448. uint32_t num_desc, page_id, offset;
  5449. uint16_t num_desc_per_page;
  5450. struct dp_soc *soc = pdev->soc;
  5451. struct dp_tx_desc_s *tx_desc = NULL;
  5452. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  5453. if (!vdev && !force_free) {
  5454. dp_err("Reset TX desc vdev, Vdev param is required!");
  5455. return;
  5456. }
  5457. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  5458. tx_desc_pool = &soc->tx_desc[i];
  5459. if (!(tx_desc_pool->pool_size) ||
  5460. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  5461. !(tx_desc_pool->desc_pages.cacheable_pages))
  5462. continue;
  5463. /*
  5464. * Add flow pool lock protection in case pool is freed
  5465. * due to all tx_desc is recycled when handle TX completion.
  5466. * this is not necessary when do force flush as:
  5467. * a. double lock will happen if dp_tx_desc_release is
  5468. * also trying to acquire it.
  5469. * b. dp interrupt has been disabled before do force TX desc
  5470. * flush in dp_pdev_deinit().
  5471. */
  5472. if (!force_free)
  5473. qdf_spin_lock_bh(&tx_desc_pool->flow_pool_lock);
  5474. num_desc = tx_desc_pool->pool_size;
  5475. num_desc_per_page =
  5476. tx_desc_pool->desc_pages.num_element_per_page;
  5477. for (j = 0; j < num_desc; j++) {
  5478. page_id = j / num_desc_per_page;
  5479. offset = j % num_desc_per_page;
  5480. if (qdf_unlikely(!(tx_desc_pool->
  5481. desc_pages.cacheable_pages)))
  5482. break;
  5483. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  5484. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  5485. /*
  5486. * Free TX desc if force free is
  5487. * required, otherwise only reset vdev
  5488. * in this TX desc.
  5489. */
  5490. if (force_free) {
  5491. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  5492. dp_tx_comp_free_buf(soc, tx_desc,
  5493. false);
  5494. dp_tx_desc_release(tx_desc, i);
  5495. } else {
  5496. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  5497. }
  5498. }
  5499. }
  5500. if (!force_free)
  5501. qdf_spin_unlock_bh(&tx_desc_pool->flow_pool_lock);
  5502. }
  5503. }
  5504. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  5505. /**
  5506. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  5507. *
  5508. * @soc: Handle to DP soc structure
  5509. * @tx_desc: pointer of one TX desc
  5510. * @desc_pool_id: TX Desc pool id
  5511. */
  5512. static inline void
  5513. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  5514. uint8_t desc_pool_id)
  5515. {
  5516. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  5517. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  5518. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  5519. }
  5520. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  5521. bool force_free)
  5522. {
  5523. uint8_t i, num_pool;
  5524. uint32_t j;
  5525. uint32_t num_desc, page_id, offset;
  5526. uint16_t num_desc_per_page;
  5527. struct dp_soc *soc = pdev->soc;
  5528. struct dp_tx_desc_s *tx_desc = NULL;
  5529. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  5530. if (!vdev && !force_free) {
  5531. dp_err("Reset TX desc vdev, Vdev param is required!");
  5532. return;
  5533. }
  5534. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5535. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5536. for (i = 0; i < num_pool; i++) {
  5537. tx_desc_pool = &soc->tx_desc[i];
  5538. if (!tx_desc_pool->desc_pages.cacheable_pages)
  5539. continue;
  5540. num_desc_per_page =
  5541. tx_desc_pool->desc_pages.num_element_per_page;
  5542. for (j = 0; j < num_desc; j++) {
  5543. page_id = j / num_desc_per_page;
  5544. offset = j % num_desc_per_page;
  5545. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  5546. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  5547. if (force_free) {
  5548. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  5549. dp_tx_comp_free_buf(soc, tx_desc,
  5550. false);
  5551. dp_tx_desc_release(tx_desc, i);
  5552. } else {
  5553. dp_tx_desc_reset_vdev(soc, tx_desc,
  5554. i);
  5555. }
  5556. }
  5557. }
  5558. }
  5559. }
  5560. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  5561. /**
  5562. * dp_tx_vdev_detach() - detach vdev from dp tx
  5563. * @vdev: virtual device instance
  5564. *
  5565. * Return: QDF_STATUS_SUCCESS: success
  5566. * QDF_STATUS_E_RESOURCES: Error return
  5567. */
  5568. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  5569. {
  5570. struct dp_pdev *pdev = vdev->pdev;
  5571. /* Reset TX desc associated to this Vdev as NULL */
  5572. dp_tx_desc_flush(pdev, vdev, false);
  5573. return QDF_STATUS_SUCCESS;
  5574. }
  5575. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  5576. /* Pools will be allocated dynamically */
  5577. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  5578. int num_desc)
  5579. {
  5580. uint8_t i;
  5581. for (i = 0; i < num_pool; i++) {
  5582. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  5583. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  5584. }
  5585. return QDF_STATUS_SUCCESS;
  5586. }
  5587. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  5588. uint32_t num_desc)
  5589. {
  5590. return QDF_STATUS_SUCCESS;
  5591. }
  5592. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  5593. {
  5594. }
  5595. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  5596. {
  5597. uint8_t i;
  5598. for (i = 0; i < num_pool; i++)
  5599. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  5600. }
  5601. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  5602. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  5603. uint32_t num_desc)
  5604. {
  5605. uint8_t i, count;
  5606. /* Allocate software Tx descriptor pools */
  5607. for (i = 0; i < num_pool; i++) {
  5608. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  5609. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  5610. FL("Tx Desc Pool alloc %d failed %pK"),
  5611. i, soc);
  5612. goto fail;
  5613. }
  5614. }
  5615. return QDF_STATUS_SUCCESS;
  5616. fail:
  5617. for (count = 0; count < i; count++)
  5618. dp_tx_desc_pool_free(soc, count);
  5619. return QDF_STATUS_E_NOMEM;
  5620. }
  5621. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  5622. uint32_t num_desc)
  5623. {
  5624. uint8_t i;
  5625. for (i = 0; i < num_pool; i++) {
  5626. if (dp_tx_desc_pool_init(soc, i, num_desc)) {
  5627. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  5628. FL("Tx Desc Pool init %d failed %pK"),
  5629. i, soc);
  5630. return QDF_STATUS_E_NOMEM;
  5631. }
  5632. }
  5633. return QDF_STATUS_SUCCESS;
  5634. }
  5635. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  5636. {
  5637. uint8_t i;
  5638. for (i = 0; i < num_pool; i++)
  5639. dp_tx_desc_pool_deinit(soc, i);
  5640. }
  5641. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  5642. {
  5643. uint8_t i;
  5644. for (i = 0; i < num_pool; i++)
  5645. dp_tx_desc_pool_free(soc, i);
  5646. }
  5647. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  5648. /**
  5649. * dp_tx_tso_cmn_desc_pool_deinit() - de-initialize TSO descriptors
  5650. * @soc: core txrx main context
  5651. * @num_pool: number of pools
  5652. *
  5653. */
  5654. static void dp_tx_tso_cmn_desc_pool_deinit(struct dp_soc *soc, uint8_t num_pool)
  5655. {
  5656. dp_tx_tso_desc_pool_deinit(soc, num_pool);
  5657. dp_tx_tso_num_seg_pool_deinit(soc, num_pool);
  5658. }
  5659. /**
  5660. * dp_tx_tso_cmn_desc_pool_free() - free TSO descriptors
  5661. * @soc: core txrx main context
  5662. * @num_pool: number of pools
  5663. *
  5664. */
  5665. static void dp_tx_tso_cmn_desc_pool_free(struct dp_soc *soc, uint8_t num_pool)
  5666. {
  5667. dp_tx_tso_desc_pool_free(soc, num_pool);
  5668. dp_tx_tso_num_seg_pool_free(soc, num_pool);
  5669. }
  5670. /**
  5671. * dp_soc_tx_desc_sw_pools_free() - free all TX descriptors
  5672. * @soc: core txrx main context
  5673. *
  5674. * This function frees all tx related descriptors as below
  5675. * 1. Regular TX descriptors (static pools)
  5676. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  5677. * 3. TSO descriptors
  5678. *
  5679. */
  5680. void dp_soc_tx_desc_sw_pools_free(struct dp_soc *soc)
  5681. {
  5682. uint8_t num_pool;
  5683. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5684. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  5685. dp_tx_ext_desc_pool_free(soc, num_pool);
  5686. dp_tx_delete_static_pools(soc, num_pool);
  5687. }
  5688. /**
  5689. * dp_soc_tx_desc_sw_pools_deinit() - de-initialize all TX descriptors
  5690. * @soc: core txrx main context
  5691. *
  5692. * This function de-initializes all tx related descriptors as below
  5693. * 1. Regular TX descriptors (static pools)
  5694. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  5695. * 3. TSO descriptors
  5696. *
  5697. */
  5698. void dp_soc_tx_desc_sw_pools_deinit(struct dp_soc *soc)
  5699. {
  5700. uint8_t num_pool;
  5701. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5702. dp_tx_flow_control_deinit(soc);
  5703. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  5704. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  5705. dp_tx_deinit_static_pools(soc, num_pool);
  5706. }
  5707. /**
  5708. * dp_tx_tso_cmn_desc_pool_alloc() - TSO cmn desc pool allocator
  5709. * @soc: DP soc handle
  5710. * @num_pool: Number of pools
  5711. * @num_desc: Number of descriptors
  5712. *
  5713. * Reserve TSO descriptor buffers
  5714. *
  5715. * Return: QDF_STATUS_E_FAILURE on failure or
  5716. * QDF_STATUS_SUCCESS on success
  5717. */
  5718. static QDF_STATUS dp_tx_tso_cmn_desc_pool_alloc(struct dp_soc *soc,
  5719. uint8_t num_pool,
  5720. uint32_t num_desc)
  5721. {
  5722. if (dp_tx_tso_desc_pool_alloc(soc, num_pool, num_desc)) {
  5723. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  5724. return QDF_STATUS_E_FAILURE;
  5725. }
  5726. if (dp_tx_tso_num_seg_pool_alloc(soc, num_pool, num_desc)) {
  5727. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  5728. num_pool, soc);
  5729. return QDF_STATUS_E_FAILURE;
  5730. }
  5731. return QDF_STATUS_SUCCESS;
  5732. }
  5733. /**
  5734. * dp_tx_tso_cmn_desc_pool_init() - TSO cmn desc pool init
  5735. * @soc: DP soc handle
  5736. * @num_pool: Number of pools
  5737. * @num_desc: Number of descriptors
  5738. *
  5739. * Initialize TSO descriptor pools
  5740. *
  5741. * Return: QDF_STATUS_E_FAILURE on failure or
  5742. * QDF_STATUS_SUCCESS on success
  5743. */
  5744. static QDF_STATUS dp_tx_tso_cmn_desc_pool_init(struct dp_soc *soc,
  5745. uint8_t num_pool,
  5746. uint32_t num_desc)
  5747. {
  5748. if (dp_tx_tso_desc_pool_init(soc, num_pool, num_desc)) {
  5749. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  5750. return QDF_STATUS_E_FAILURE;
  5751. }
  5752. if (dp_tx_tso_num_seg_pool_init(soc, num_pool, num_desc)) {
  5753. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  5754. num_pool, soc);
  5755. return QDF_STATUS_E_FAILURE;
  5756. }
  5757. return QDF_STATUS_SUCCESS;
  5758. }
  5759. /**
  5760. * dp_soc_tx_desc_sw_pools_alloc() - Allocate tx descriptor pool memory
  5761. * @soc: core txrx main context
  5762. *
  5763. * This function allocates memory for following descriptor pools
  5764. * 1. regular sw tx descriptor pools (static pools)
  5765. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  5766. * 3. TSO descriptor pools
  5767. *
  5768. * Return: QDF_STATUS_SUCCESS: success
  5769. * QDF_STATUS_E_RESOURCES: Error return
  5770. */
  5771. QDF_STATUS dp_soc_tx_desc_sw_pools_alloc(struct dp_soc *soc)
  5772. {
  5773. uint8_t num_pool;
  5774. uint32_t num_desc;
  5775. uint32_t num_ext_desc;
  5776. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5777. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5778. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5779. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  5780. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  5781. __func__, num_pool, num_desc);
  5782. if ((num_pool > MAX_TXDESC_POOLS) ||
  5783. (num_desc > WLAN_CFG_NUM_TX_DESC_MAX))
  5784. goto fail1;
  5785. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  5786. goto fail1;
  5787. if (dp_tx_ext_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5788. goto fail2;
  5789. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  5790. return QDF_STATUS_SUCCESS;
  5791. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5792. goto fail3;
  5793. return QDF_STATUS_SUCCESS;
  5794. fail3:
  5795. dp_tx_ext_desc_pool_free(soc, num_pool);
  5796. fail2:
  5797. dp_tx_delete_static_pools(soc, num_pool);
  5798. fail1:
  5799. return QDF_STATUS_E_RESOURCES;
  5800. }
  5801. /**
  5802. * dp_soc_tx_desc_sw_pools_init() - Initialise TX descriptor pools
  5803. * @soc: core txrx main context
  5804. *
  5805. * This function initializes the following TX descriptor pools
  5806. * 1. regular sw tx descriptor pools (static pools)
  5807. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  5808. * 3. TSO descriptor pools
  5809. *
  5810. * Return: QDF_STATUS_SUCCESS: success
  5811. * QDF_STATUS_E_RESOURCES: Error return
  5812. */
  5813. QDF_STATUS dp_soc_tx_desc_sw_pools_init(struct dp_soc *soc)
  5814. {
  5815. uint8_t num_pool;
  5816. uint32_t num_desc;
  5817. uint32_t num_ext_desc;
  5818. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5819. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5820. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5821. if (dp_tx_init_static_pools(soc, num_pool, num_desc))
  5822. goto fail1;
  5823. if (dp_tx_ext_desc_pool_init(soc, num_pool, num_ext_desc))
  5824. goto fail2;
  5825. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  5826. return QDF_STATUS_SUCCESS;
  5827. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  5828. goto fail3;
  5829. dp_tx_flow_control_init(soc);
  5830. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  5831. return QDF_STATUS_SUCCESS;
  5832. fail3:
  5833. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  5834. fail2:
  5835. dp_tx_deinit_static_pools(soc, num_pool);
  5836. fail1:
  5837. return QDF_STATUS_E_RESOURCES;
  5838. }
  5839. /**
  5840. * dp_tso_soc_attach() - Allocate and initialize TSO descriptors
  5841. * @txrx_soc: dp soc handle
  5842. *
  5843. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  5844. * QDF_STATUS_E_FAILURE
  5845. */
  5846. QDF_STATUS dp_tso_soc_attach(struct cdp_soc_t *txrx_soc)
  5847. {
  5848. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  5849. uint8_t num_pool;
  5850. uint32_t num_ext_desc;
  5851. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5852. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5853. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5854. return QDF_STATUS_E_FAILURE;
  5855. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  5856. return QDF_STATUS_E_FAILURE;
  5857. return QDF_STATUS_SUCCESS;
  5858. }
  5859. /**
  5860. * dp_tso_soc_detach() - de-initialize and free the TSO descriptors
  5861. * @txrx_soc: dp soc handle
  5862. *
  5863. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  5864. */
  5865. QDF_STATUS dp_tso_soc_detach(struct cdp_soc_t *txrx_soc)
  5866. {
  5867. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  5868. uint8_t num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5869. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  5870. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  5871. return QDF_STATUS_SUCCESS;
  5872. }
  5873. #ifdef CONFIG_DP_PKT_ADD_TIMESTAMP
  5874. void dp_pkt_add_timestamp(struct dp_vdev *vdev,
  5875. enum qdf_pkt_timestamp_index index, uint64_t time,
  5876. qdf_nbuf_t nbuf)
  5877. {
  5878. if (qdf_unlikely(qdf_is_dp_pkt_timestamp_enabled())) {
  5879. uint64_t tsf_time;
  5880. if (vdev->get_tsf_time) {
  5881. vdev->get_tsf_time(vdev->osif_vdev, time, &tsf_time);
  5882. qdf_add_dp_pkt_timestamp(nbuf, index, tsf_time);
  5883. }
  5884. }
  5885. }
  5886. void dp_pkt_get_timestamp(uint64_t *time)
  5887. {
  5888. if (qdf_unlikely(qdf_is_dp_pkt_timestamp_enabled()))
  5889. *time = qdf_get_log_timestamp();
  5890. }
  5891. #endif