dp_be.c 69 KB

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  1. /*
  2. * Copyright (c) 2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include <wlan_utility.h>
  20. #include <dp_internal.h>
  21. #include <dp_htt.h>
  22. #include "dp_be.h"
  23. #include "dp_be_tx.h"
  24. #include "dp_be_rx.h"
  25. #ifdef WIFI_MONITOR_SUPPORT
  26. #if !defined(DISABLE_MON_CONFIG) && defined(QCA_MONITOR_2_0_SUPPORT)
  27. #include "dp_mon_2.0.h"
  28. #endif
  29. #include "dp_mon.h"
  30. #endif
  31. #include <hal_be_api.h>
  32. #ifdef WLAN_SUPPORT_PPEDS
  33. #include "be/dp_ppeds.h"
  34. #include <ppe_vp_public.h>
  35. #include <ppe_drv_sc.h>
  36. #endif
  37. /* Generic AST entry aging timer value */
  38. #define DP_AST_AGING_TIMER_DEFAULT_MS 5000
  39. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  40. #define DP_TX_VDEV_ID_CHECK_ENABLE 0
  41. static struct wlan_cfg_tcl_wbm_ring_num_map g_tcl_wbm_map_array[MAX_TCL_DATA_RINGS] = {
  42. {.tcl_ring_num = 0, .wbm_ring_num = 0, .wbm_rbm_id = HAL_BE_WBM_SW0_BM_ID, .for_ipa = 0},
  43. {1, 4, HAL_BE_WBM_SW4_BM_ID, 0},
  44. {2, 2, HAL_BE_WBM_SW2_BM_ID, 0},
  45. #ifdef QCA_WIFI_KIWI_V2
  46. {3, 5, HAL_BE_WBM_SW5_BM_ID, 0},
  47. {4, 6, HAL_BE_WBM_SW6_BM_ID, 0}
  48. #else
  49. {3, 6, HAL_BE_WBM_SW5_BM_ID, 0},
  50. {4, 7, HAL_BE_WBM_SW6_BM_ID, 0}
  51. #endif
  52. };
  53. #else
  54. #define DP_TX_VDEV_ID_CHECK_ENABLE 1
  55. static struct wlan_cfg_tcl_wbm_ring_num_map g_tcl_wbm_map_array[MAX_TCL_DATA_RINGS] = {
  56. {.tcl_ring_num = 0, .wbm_ring_num = 0, .wbm_rbm_id = HAL_BE_WBM_SW0_BM_ID, .for_ipa = 0},
  57. {1, 1, HAL_BE_WBM_SW1_BM_ID, 0},
  58. {2, 2, HAL_BE_WBM_SW2_BM_ID, 0},
  59. {3, 3, HAL_BE_WBM_SW3_BM_ID, 0},
  60. {4, 4, HAL_BE_WBM_SW4_BM_ID, 0}
  61. };
  62. #endif
  63. #ifdef WLAN_SUPPORT_PPEDS
  64. static struct cdp_ppeds_txrx_ops dp_ops_ppeds_be = {
  65. .ppeds_entry_attach = dp_ppeds_attach_vdev_be,
  66. .ppeds_entry_detach = dp_ppeds_detach_vdev_be,
  67. .ppeds_set_int_pri2tid = dp_ppeds_set_int_pri2tid_be,
  68. .ppeds_update_int_pri2tid = dp_ppeds_update_int_pri2tid_be,
  69. .ppeds_entry_dump = dp_ppeds_dump_ppe_vp_tbl_be,
  70. .ppeds_enable_pri2tid = dp_ppeds_vdev_enable_pri2tid_be,
  71. };
  72. static void dp_ppeds_rings_status(struct dp_soc *soc)
  73. {
  74. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  75. dp_print_ring_stat_from_hal(soc, &be_soc->reo2ppe_ring, REO2PPE);
  76. dp_print_ring_stat_from_hal(soc, &be_soc->ppe2tcl_ring, PPE2TCL);
  77. dp_print_ring_stat_from_hal(soc, &be_soc->ppeds_wbm_release_ring,
  78. WBM2SW_RELEASE);
  79. }
  80. static void dp_ppeds_inuse_desc(struct dp_soc *soc)
  81. {
  82. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  83. DP_PRINT_STATS("PPE-DS Tx Descriptors in Use = %u num_free %u",
  84. be_soc->ppeds_tx_desc.num_allocated,
  85. be_soc->ppeds_tx_desc.num_free);
  86. }
  87. #endif
  88. static void dp_soc_cfg_attach_be(struct dp_soc *soc)
  89. {
  90. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx = soc->wlan_cfg_ctx;
  91. wlan_cfg_set_rx_rel_ring_id(soc_cfg_ctx, WBM2SW_REL_ERR_RING_NUM);
  92. soc->wlan_cfg_ctx->tcl_wbm_map_array = g_tcl_wbm_map_array;
  93. /* this is used only when dmac mode is enabled */
  94. soc->num_rx_refill_buf_rings = 1;
  95. soc->wlan_cfg_ctx->notify_frame_support =
  96. DP_MARK_NOTIFY_FRAME_SUPPORT;
  97. }
  98. qdf_size_t dp_get_context_size_be(enum dp_context_type context_type)
  99. {
  100. switch (context_type) {
  101. case DP_CONTEXT_TYPE_SOC:
  102. return sizeof(struct dp_soc_be);
  103. case DP_CONTEXT_TYPE_PDEV:
  104. return sizeof(struct dp_pdev_be);
  105. case DP_CONTEXT_TYPE_VDEV:
  106. return sizeof(struct dp_vdev_be);
  107. case DP_CONTEXT_TYPE_PEER:
  108. return sizeof(struct dp_peer_be);
  109. default:
  110. return 0;
  111. }
  112. }
  113. #ifdef DP_FEATURE_HW_COOKIE_CONVERSION
  114. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  115. /**
  116. * dp_cc_wbm_sw_en_cfg() - configure HW cookie conversion enablement
  117. * per wbm2sw ring
  118. *
  119. * @cc_cfg: HAL HW cookie conversion configuration structure pointer
  120. *
  121. * Return: None
  122. */
  123. static inline
  124. void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg)
  125. {
  126. cc_cfg->wbm2sw6_cc_en = 1;
  127. cc_cfg->wbm2sw5_cc_en = 1;
  128. cc_cfg->wbm2sw4_cc_en = 1;
  129. cc_cfg->wbm2sw3_cc_en = 1;
  130. cc_cfg->wbm2sw2_cc_en = 1;
  131. /* disable wbm2sw1 hw cc as it's for FW */
  132. cc_cfg->wbm2sw1_cc_en = 0;
  133. cc_cfg->wbm2sw0_cc_en = 1;
  134. cc_cfg->wbm2fw_cc_en = 0;
  135. }
  136. #else
  137. static inline
  138. void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg)
  139. {
  140. cc_cfg->wbm2sw6_cc_en = 1;
  141. cc_cfg->wbm2sw5_cc_en = 1;
  142. cc_cfg->wbm2sw4_cc_en = 1;
  143. cc_cfg->wbm2sw3_cc_en = 1;
  144. cc_cfg->wbm2sw2_cc_en = 1;
  145. cc_cfg->wbm2sw1_cc_en = 1;
  146. cc_cfg->wbm2sw0_cc_en = 1;
  147. cc_cfg->wbm2fw_cc_en = 0;
  148. }
  149. #endif
  150. #if defined(WLAN_SUPPORT_RX_FISA)
  151. static QDF_STATUS dp_fisa_fst_cmem_addr_init(struct dp_soc *soc)
  152. {
  153. dp_info("cmem base 0x%llx, total size 0x%llx avail_size 0x%llx",
  154. soc->cmem_base, soc->cmem_total_size, soc->cmem_avail_size);
  155. /* get CMEM for cookie conversion */
  156. if (soc->cmem_avail_size < DP_CMEM_FST_SIZE) {
  157. dp_err("cmem_size 0x%llx bytes < 16K", soc->cmem_avail_size);
  158. return QDF_STATUS_E_NOMEM;
  159. }
  160. soc->fst_cmem_size = DP_CMEM_FST_SIZE;
  161. soc->fst_cmem_base = soc->cmem_base +
  162. (soc->cmem_total_size - soc->cmem_avail_size);
  163. soc->cmem_avail_size -= soc->fst_cmem_size;
  164. dp_info("fst_cmem_base 0x%llx, fst_cmem_size 0x%llx",
  165. soc->fst_cmem_base, soc->fst_cmem_size);
  166. return QDF_STATUS_SUCCESS;
  167. }
  168. #else /* !WLAN_SUPPORT_RX_FISA */
  169. static QDF_STATUS dp_fisa_fst_cmem_addr_init(struct dp_soc *soc)
  170. {
  171. return QDF_STATUS_SUCCESS;
  172. }
  173. #endif
  174. /**
  175. * dp_cc_reg_cfg_init() - initialize and configure HW cookie
  176. * conversion register
  177. *
  178. * @soc: SOC handle
  179. * @is_4k_align: page address 4k aligned
  180. *
  181. * Return: None
  182. */
  183. static void dp_cc_reg_cfg_init(struct dp_soc *soc,
  184. bool is_4k_align)
  185. {
  186. struct hal_hw_cc_config cc_cfg = { 0 };
  187. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  188. if (soc->cdp_soc.ol_ops->get_con_mode &&
  189. soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_FTM_MODE)
  190. return;
  191. if (!soc->wlan_cfg_ctx->hw_cc_enabled) {
  192. dp_info("INI skip HW CC register setting");
  193. return;
  194. }
  195. cc_cfg.lut_base_addr_31_0 = be_soc->cc_cmem_base;
  196. cc_cfg.cc_global_en = true;
  197. cc_cfg.page_4k_align = is_4k_align;
  198. cc_cfg.cookie_offset_msb = DP_CC_DESC_ID_SPT_VA_OS_MSB;
  199. cc_cfg.cookie_page_msb = DP_CC_DESC_ID_PPT_PAGE_OS_MSB;
  200. /* 36th bit should be 1 then HW know this is CMEM address */
  201. cc_cfg.lut_base_addr_39_32 = 0x10;
  202. cc_cfg.error_path_cookie_conv_en = true;
  203. cc_cfg.release_path_cookie_conv_en = true;
  204. dp_cc_wbm_sw_en_cfg(&cc_cfg);
  205. hal_cookie_conversion_reg_cfg_be(soc->hal_soc, &cc_cfg);
  206. }
  207. /**
  208. * dp_hw_cc_cmem_write() - DP wrapper function for CMEM buffer writing
  209. * @hal_soc_hdl: HAL SOC handle
  210. * @offset: CMEM address
  211. * @value: value to write
  212. *
  213. * Return: None.
  214. */
  215. static inline void dp_hw_cc_cmem_write(hal_soc_handle_t hal_soc_hdl,
  216. uint32_t offset,
  217. uint32_t value)
  218. {
  219. hal_cmem_write(hal_soc_hdl, offset, value);
  220. }
  221. /**
  222. * dp_hw_cc_cmem_addr_init() - Check and initialize CMEM base address for
  223. * HW cookie conversion
  224. *
  225. * @soc: SOC handle
  226. *
  227. * Return: 0 in case of success, else error value
  228. */
  229. static inline QDF_STATUS dp_hw_cc_cmem_addr_init(struct dp_soc *soc)
  230. {
  231. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  232. dp_info("cmem base 0x%llx, total size 0x%llx avail_size 0x%llx",
  233. soc->cmem_base, soc->cmem_total_size, soc->cmem_avail_size);
  234. /* get CMEM for cookie conversion */
  235. if (soc->cmem_avail_size < DP_CC_PPT_MEM_SIZE) {
  236. dp_err("cmem_size 0x%llx bytes < 4K", soc->cmem_avail_size);
  237. return QDF_STATUS_E_RESOURCES;
  238. }
  239. be_soc->cc_cmem_base = (uint32_t)(soc->cmem_base +
  240. DP_CC_MEM_OFFSET_IN_CMEM);
  241. soc->cmem_avail_size -= DP_CC_PPT_MEM_SIZE;
  242. dp_info("cc_cmem_base 0x%x, cmem_avail_size 0x%llx",
  243. be_soc->cc_cmem_base, soc->cmem_avail_size);
  244. return QDF_STATUS_SUCCESS;
  245. }
  246. static QDF_STATUS dp_get_cmem_allocation(struct dp_soc *soc,
  247. uint8_t for_feature)
  248. {
  249. QDF_STATUS status = QDF_STATUS_E_NOMEM;
  250. switch (for_feature) {
  251. case COOKIE_CONVERSION:
  252. status = dp_hw_cc_cmem_addr_init(soc);
  253. break;
  254. case FISA_FST:
  255. status = dp_fisa_fst_cmem_addr_init(soc);
  256. break;
  257. default:
  258. dp_err("Invalid CMEM request");
  259. }
  260. return status;
  261. }
  262. #else
  263. static inline void dp_cc_reg_cfg_init(struct dp_soc *soc,
  264. bool is_4k_align) {}
  265. static inline void dp_hw_cc_cmem_write(hal_soc_handle_t hal_soc_hdl,
  266. uint32_t offset,
  267. uint32_t value)
  268. { }
  269. static inline QDF_STATUS dp_hw_cc_cmem_addr_init(struct dp_soc *soc)
  270. {
  271. return QDF_STATUS_SUCCESS;
  272. }
  273. static QDF_STATUS dp_get_cmem_allocation(struct dp_soc *soc,
  274. uint8_t for_feature)
  275. {
  276. return QDF_STATUS_SUCCESS;
  277. }
  278. #endif
  279. QDF_STATUS
  280. dp_hw_cookie_conversion_attach(struct dp_soc_be *be_soc,
  281. struct dp_hw_cookie_conversion_t *cc_ctx,
  282. uint32_t num_descs,
  283. enum dp_desc_type desc_type,
  284. uint8_t desc_pool_id)
  285. {
  286. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  287. uint32_t num_spt_pages, i = 0;
  288. struct dp_spt_page_desc *spt_desc;
  289. struct qdf_mem_dma_page_t *dma_page;
  290. uint8_t chip_id;
  291. /* estimate how many SPT DDR pages needed */
  292. num_spt_pages = num_descs / DP_CC_SPT_PAGE_MAX_ENTRIES;
  293. num_spt_pages = num_spt_pages <= DP_CC_PPT_MAX_ENTRIES ?
  294. num_spt_pages : DP_CC_PPT_MAX_ENTRIES;
  295. dp_info("num_spt_pages needed %d", num_spt_pages);
  296. dp_desc_multi_pages_mem_alloc(soc, DP_HW_CC_SPT_PAGE_TYPE,
  297. &cc_ctx->page_pool, qdf_page_size,
  298. num_spt_pages, 0, false);
  299. if (!cc_ctx->page_pool.dma_pages) {
  300. dp_err("spt ddr pages allocation failed");
  301. return QDF_STATUS_E_RESOURCES;
  302. }
  303. cc_ctx->page_desc_base = qdf_mem_malloc(
  304. num_spt_pages * sizeof(struct dp_spt_page_desc));
  305. if (!cc_ctx->page_desc_base) {
  306. dp_err("spt page descs allocation failed");
  307. goto fail_0;
  308. }
  309. chip_id = dp_mlo_get_chip_id(soc);
  310. cc_ctx->cmem_offset = dp_desc_pool_get_cmem_base(chip_id, desc_pool_id,
  311. desc_type);
  312. /* initial page desc */
  313. spt_desc = cc_ctx->page_desc_base;
  314. dma_page = cc_ctx->page_pool.dma_pages;
  315. while (i < num_spt_pages) {
  316. /* check if page address 4K aligned */
  317. if (qdf_unlikely(dma_page[i].page_p_addr & 0xFFF)) {
  318. dp_err("non-4k aligned pages addr %pK",
  319. (void *)dma_page[i].page_p_addr);
  320. goto fail_1;
  321. }
  322. spt_desc[i].page_v_addr =
  323. dma_page[i].page_v_addr_start;
  324. spt_desc[i].page_p_addr =
  325. dma_page[i].page_p_addr;
  326. i++;
  327. }
  328. cc_ctx->total_page_num = num_spt_pages;
  329. qdf_spinlock_create(&cc_ctx->cc_lock);
  330. return QDF_STATUS_SUCCESS;
  331. fail_1:
  332. qdf_mem_free(cc_ctx->page_desc_base);
  333. fail_0:
  334. dp_desc_multi_pages_mem_free(soc, DP_HW_CC_SPT_PAGE_TYPE,
  335. &cc_ctx->page_pool, 0, false);
  336. return QDF_STATUS_E_FAILURE;
  337. }
  338. QDF_STATUS
  339. dp_hw_cookie_conversion_detach(struct dp_soc_be *be_soc,
  340. struct dp_hw_cookie_conversion_t *cc_ctx)
  341. {
  342. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  343. qdf_mem_free(cc_ctx->page_desc_base);
  344. dp_desc_multi_pages_mem_free(soc, DP_HW_CC_SPT_PAGE_TYPE,
  345. &cc_ctx->page_pool, 0, false);
  346. qdf_spinlock_destroy(&cc_ctx->cc_lock);
  347. return QDF_STATUS_SUCCESS;
  348. }
  349. QDF_STATUS
  350. dp_hw_cookie_conversion_init(struct dp_soc_be *be_soc,
  351. struct dp_hw_cookie_conversion_t *cc_ctx)
  352. {
  353. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  354. uint32_t i = 0;
  355. struct dp_spt_page_desc *spt_desc;
  356. uint32_t ppt_index;
  357. uint32_t ppt_id_start;
  358. if (!cc_ctx->total_page_num) {
  359. dp_err("total page num is 0");
  360. return QDF_STATUS_E_INVAL;
  361. }
  362. ppt_id_start = DP_CMEM_OFFSET_TO_PPT_ID(cc_ctx->cmem_offset);
  363. spt_desc = cc_ctx->page_desc_base;
  364. while (i < cc_ctx->total_page_num) {
  365. /* write page PA to CMEM */
  366. dp_hw_cc_cmem_write(soc->hal_soc,
  367. (cc_ctx->cmem_offset + be_soc->cc_cmem_base
  368. + (i * DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)),
  369. (spt_desc[i].page_p_addr >>
  370. DP_CC_PPT_ENTRY_HW_APEND_BITS_4K_ALIGNED));
  371. ppt_index = ppt_id_start + i;
  372. if (ppt_index >= DP_CC_PPT_MAX_ENTRIES)
  373. qdf_assert_always(0);
  374. spt_desc[i].ppt_index = ppt_index;
  375. be_soc->page_desc_base[ppt_index].page_v_addr =
  376. spt_desc[i].page_v_addr;
  377. i++;
  378. }
  379. return QDF_STATUS_SUCCESS;
  380. }
  381. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  382. QDF_STATUS
  383. dp_hw_cookie_conversion_deinit(struct dp_soc_be *be_soc,
  384. struct dp_hw_cookie_conversion_t *cc_ctx)
  385. {
  386. uint32_t ppt_index;
  387. struct dp_spt_page_desc *spt_desc;
  388. int i = 0;
  389. spt_desc = cc_ctx->page_desc_base;
  390. while (i < cc_ctx->total_page_num) {
  391. ppt_index = spt_desc[i].ppt_index;
  392. be_soc->page_desc_base[ppt_index].page_v_addr = NULL;
  393. i++;
  394. }
  395. return QDF_STATUS_SUCCESS;
  396. }
  397. #else
  398. QDF_STATUS
  399. dp_hw_cookie_conversion_deinit(struct dp_soc_be *be_soc,
  400. struct dp_hw_cookie_conversion_t *cc_ctx)
  401. {
  402. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  403. uint32_t ppt_index;
  404. struct dp_spt_page_desc *spt_desc;
  405. int i = 0;
  406. spt_desc = cc_ctx->page_desc_base;
  407. while (i < cc_ctx->total_page_num) {
  408. /* reset PA in CMEM to NULL */
  409. dp_hw_cc_cmem_write(soc->hal_soc,
  410. (cc_ctx->cmem_offset + be_soc->cc_cmem_base
  411. + (i * DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)),
  412. 0);
  413. ppt_index = spt_desc[i].ppt_index;
  414. be_soc->page_desc_base[ppt_index].page_v_addr = NULL;
  415. i++;
  416. }
  417. return QDF_STATUS_SUCCESS;
  418. }
  419. #endif
  420. #ifdef WLAN_SUPPORT_PPEDS
  421. static QDF_STATUS dp_soc_ppeds_attach_be(struct dp_soc *soc)
  422. {
  423. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  424. struct cdp_ops *cdp_ops = soc->cdp_soc.ops;
  425. /*
  426. * Check if PPE DS is enabled.
  427. */
  428. if (!wlan_cfg_get_dp_soc_is_ppeds_enabled(soc->wlan_cfg_ctx))
  429. return QDF_STATUS_SUCCESS;
  430. if (dp_ppeds_attach_soc_be(be_soc) != QDF_STATUS_SUCCESS)
  431. return QDF_STATUS_SUCCESS;
  432. cdp_ops->ppeds_ops = &dp_ops_ppeds_be;
  433. return QDF_STATUS_SUCCESS;
  434. }
  435. static QDF_STATUS dp_soc_ppeds_detach_be(struct dp_soc *soc)
  436. {
  437. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  438. struct cdp_ops *cdp_ops = soc->cdp_soc.ops;
  439. if (!wlan_cfg_get_dp_soc_is_ppeds_enabled(soc->wlan_cfg_ctx))
  440. return QDF_STATUS_E_FAILURE;
  441. dp_ppeds_detach_soc_be(be_soc);
  442. cdp_ops->ppeds_ops = NULL;
  443. return QDF_STATUS_SUCCESS;
  444. }
  445. static QDF_STATUS dp_peer_ppeds_default_route_be(struct dp_soc *soc,
  446. struct dp_peer_be *be_peer,
  447. uint8_t vdev_id,
  448. uint16_t src_info)
  449. {
  450. uint16_t service_code;
  451. uint8_t priority_valid;
  452. uint8_t use_ppe_ds = PEER_ROUTING_USE_PPE;
  453. uint8_t peer_routing_enabled = PEER_ROUTING_ENABLED;
  454. QDF_STATUS status = QDF_STATUS_SUCCESS;
  455. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  456. struct dp_vdev_be *be_vdev;
  457. be_vdev = dp_get_be_vdev_from_dp_vdev(be_peer->peer.vdev);
  458. /*
  459. * Program service code bypass to avoid L2 new mac address
  460. * learning exception when fdb learning is disabled.
  461. */
  462. service_code = PPE_DRV_SC_SPF_BYPASS;
  463. priority_valid = be_peer->priority_valid;
  464. /*
  465. * if FST is enabled then let flow rule take the decision of
  466. * routing the pkt to DS or host
  467. */
  468. if (wlan_cfg_is_rx_flow_tag_enabled(cfg))
  469. use_ppe_ds = 0;
  470. if (soc->cdp_soc.ol_ops->peer_set_ppeds_default_routing) {
  471. status =
  472. soc->cdp_soc.ol_ops->peer_set_ppeds_default_routing
  473. (soc->ctrl_psoc,
  474. be_peer->peer.mac_addr.raw,
  475. service_code, priority_valid,
  476. src_info, vdev_id, use_ppe_ds,
  477. peer_routing_enabled);
  478. if (status != QDF_STATUS_SUCCESS) {
  479. dp_err("vdev_id: %d, PPE peer routing mac:"
  480. QDF_MAC_ADDR_FMT, vdev_id,
  481. QDF_MAC_ADDR_REF(be_peer->peer.mac_addr.raw));
  482. return QDF_STATUS_E_FAILURE;
  483. }
  484. }
  485. return QDF_STATUS_SUCCESS;
  486. }
  487. #ifdef WLAN_FEATURE_11BE_MLO
  488. static QDF_STATUS dp_peer_setup_ppeds_be(struct dp_soc *soc,
  489. struct dp_peer *peer,
  490. struct dp_vdev_be *be_vdev)
  491. {
  492. struct dp_ppe_vp_profile *ppe_vp_profile = &be_vdev->ppe_vp_profile;
  493. uint16_t src_info = ppe_vp_profile->vp_num;
  494. uint8_t vdev_id = be_vdev->vdev.vdev_id;
  495. struct dp_peer_be *be_peer = dp_get_be_peer_from_dp_peer(peer);
  496. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  497. if (!be_peer) {
  498. dp_err("BE peer is null");
  499. return QDF_STATUS_E_NULL_VALUE;
  500. }
  501. if (IS_DP_LEGACY_PEER(peer)) {
  502. qdf_status = dp_peer_ppeds_default_route_be(soc, be_peer,
  503. vdev_id, src_info);
  504. } else if (IS_MLO_DP_MLD_PEER(peer)) {
  505. int i;
  506. struct dp_peer *link_peer = NULL;
  507. struct dp_mld_link_peers link_peers_info;
  508. /* get link peers with reference */
  509. dp_get_link_peers_ref_from_mld_peer(soc, peer, &link_peers_info,
  510. DP_MOD_ID_DS);
  511. for (i = 0; i < link_peers_info.num_links; i++) {
  512. link_peer = link_peers_info.link_peers[i];
  513. be_peer = dp_get_be_peer_from_dp_peer(link_peer);
  514. if (!be_peer) {
  515. dp_err("BE peer is null");
  516. continue;
  517. }
  518. be_vdev = dp_get_be_vdev_from_dp_vdev(link_peer->vdev);
  519. if (!be_vdev) {
  520. dp_err("BE vap is null for peer id %d ",
  521. link_peer->peer_id);
  522. continue;
  523. }
  524. vdev_id = be_vdev->vdev.vdev_id;
  525. qdf_status = dp_peer_ppeds_default_route_be(soc,
  526. be_peer,
  527. vdev_id,
  528. src_info);
  529. }
  530. dp_release_link_peers_ref(&link_peers_info, DP_MOD_ID_DS);
  531. } else {
  532. struct dp_peer *mld_peer = DP_GET_MLD_PEER_FROM_PEER(peer);
  533. if (!mld_peer)
  534. return qdf_status;
  535. be_vdev = dp_get_be_vdev_from_dp_vdev(mld_peer->vdev);
  536. if (!be_vdev) {
  537. dp_err("BE vap is null");
  538. return QDF_STATUS_E_NULL_VALUE;
  539. }
  540. ppe_vp_profile = &be_vdev->ppe_vp_profile;
  541. src_info = ppe_vp_profile->vp_num;
  542. qdf_status = dp_peer_ppeds_default_route_be(soc, be_peer,
  543. vdev_id, src_info);
  544. }
  545. return qdf_status;
  546. }
  547. #else
  548. static QDF_STATUS dp_peer_setup_ppeds_be(struct dp_soc *soc,
  549. struct dp_peer *peer,
  550. struct dp_vdev_be *be_vdev)
  551. {
  552. struct dp_ppe_vp_profile *ppe_vp_profile = &be_vdev->ppe_vp_profile;
  553. struct dp_peer_be *be_peer = dp_get_be_peer_from_dp_peer(peer);
  554. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  555. if (!be_peer) {
  556. dp_err("BE peer is null");
  557. return QDF_STATUS_E_NULL_VALUE;
  558. }
  559. qdf_status = dp_peer_ppeds_default_route_be(soc, be_peer,
  560. be_vdev->vdev.vdev_id,
  561. ppe_vp_profile->vp_num);
  562. return qdf_status;
  563. }
  564. #endif
  565. #else
  566. static QDF_STATUS dp_ppeds_init_soc_be(struct dp_soc *soc)
  567. {
  568. return QDF_STATUS_SUCCESS;
  569. }
  570. static QDF_STATUS dp_ppeds_deinit_soc_be(struct dp_soc *soc)
  571. {
  572. return QDF_STATUS_SUCCESS;
  573. }
  574. static inline QDF_STATUS dp_soc_ppeds_attach_be(struct dp_soc *soc)
  575. {
  576. return QDF_STATUS_SUCCESS;
  577. }
  578. static inline QDF_STATUS dp_soc_ppeds_detach_be(struct dp_soc *soc)
  579. {
  580. return QDF_STATUS_SUCCESS;
  581. }
  582. static inline
  583. QDF_STATUS dp_peer_setup_ppeds_be(struct dp_soc *soc, struct dp_peer *peer,
  584. struct dp_vdev_be *be_vdev)
  585. {
  586. return QDF_STATUS_SUCCESS;
  587. }
  588. #endif /* WLAN_SUPPORT_PPEDS */
  589. static QDF_STATUS dp_soc_detach_be(struct dp_soc *soc)
  590. {
  591. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  592. int i = 0;
  593. dp_soc_ppeds_detach_be(soc);
  594. for (i = 0; i < MAX_TXDESC_POOLS; i++)
  595. dp_hw_cookie_conversion_detach(be_soc,
  596. &be_soc->tx_cc_ctx[i]);
  597. for (i = 0; i < MAX_RXDESC_POOLS; i++)
  598. dp_hw_cookie_conversion_detach(be_soc,
  599. &be_soc->rx_cc_ctx[i]);
  600. qdf_mem_free(be_soc->page_desc_base);
  601. be_soc->page_desc_base = NULL;
  602. return QDF_STATUS_SUCCESS;
  603. }
  604. #ifdef WLAN_MLO_MULTI_CHIP
  605. #ifdef WLAN_MCAST_MLO
  606. static inline void
  607. dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev)
  608. {
  609. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  610. be_vdev->mcast_primary = false;
  611. be_vdev->seq_num = 0;
  612. hal_tx_mcast_mlo_reinject_routing_set(
  613. soc->hal_soc,
  614. HAL_TX_MCAST_MLO_REINJECT_TQM_NOTIFY);
  615. if (vdev->opmode == wlan_op_mode_ap) {
  616. hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc,
  617. vdev->vdev_id,
  618. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  619. }
  620. }
  621. static inline void
  622. dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev)
  623. {
  624. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  625. be_vdev->seq_num = 0;
  626. be_vdev->mcast_primary = false;
  627. vdev->mlo_vdev = false;
  628. }
  629. static void dp_set_rx_fst_be(struct dp_soc *soc, struct dp_rx_fst *fst)
  630. {
  631. dp_mlo_set_rx_fst(soc, fst);
  632. }
  633. static struct dp_rx_fst *dp_get_rx_fst_be(struct dp_soc *soc)
  634. {
  635. return dp_mlo_get_rx_fst(soc);
  636. }
  637. static uint8_t dp_rx_fst_deref_be(struct dp_soc *soc)
  638. {
  639. return dp_mlo_rx_fst_deref(soc);
  640. }
  641. static void dp_rx_fst_ref_be(struct dp_soc *soc)
  642. {
  643. dp_mlo_rx_fst_ref(soc);
  644. }
  645. #else
  646. static inline void
  647. dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev)
  648. {
  649. }
  650. static inline void
  651. dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev)
  652. {
  653. }
  654. static void dp_set_rx_fst_be(struct dp_soc *soc, struct dp_rx_fst *fst)
  655. {
  656. }
  657. static struct dp_rx_fst *dp_get_rx_fst_be(struct dp_soc *soc)
  658. {
  659. return NULL;
  660. }
  661. static uint8_t dp_rx_fst_deref_be(struct dp_soc *soc)
  662. {
  663. return 1;
  664. }
  665. static void dp_rx_fst_ref_be(struct dp_soc *soc)
  666. {
  667. }
  668. #endif
  669. static void dp_mlo_init_ptnr_list(struct dp_vdev *vdev)
  670. {
  671. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  672. qdf_mem_set(be_vdev->partner_vdev_list,
  673. WLAN_MAX_MLO_CHIPS * WLAN_MAX_MLO_LINKS_PER_SOC,
  674. CDP_INVALID_VDEV_ID);
  675. }
  676. static void dp_get_rx_hash_key_be(struct dp_soc *soc,
  677. struct cdp_lro_hash_config *lro_hash)
  678. {
  679. dp_mlo_get_rx_hash_key(soc, lro_hash);
  680. }
  681. #else
  682. static inline void
  683. dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev)
  684. {
  685. }
  686. static inline void
  687. dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev)
  688. {
  689. }
  690. static void dp_mlo_init_ptnr_list(struct dp_vdev *vdev)
  691. {
  692. }
  693. static void dp_get_rx_hash_key_be(struct dp_soc *soc,
  694. struct cdp_lro_hash_config *lro_hash)
  695. {
  696. dp_get_rx_hash_key_bytes(lro_hash);
  697. }
  698. static void dp_set_rx_fst_be(struct dp_soc *soc, struct dp_rx_fst *fst)
  699. {
  700. }
  701. static struct dp_rx_fst *dp_get_rx_fst_be(struct dp_soc *soc)
  702. {
  703. return NULL;
  704. }
  705. static uint8_t dp_rx_fst_deref_be(struct dp_soc *soc)
  706. {
  707. return 1;
  708. }
  709. static void dp_rx_fst_ref_be(struct dp_soc *soc)
  710. {
  711. }
  712. #endif
  713. static QDF_STATUS dp_soc_attach_be(struct dp_soc *soc,
  714. struct cdp_soc_attach_params *params)
  715. {
  716. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  717. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  718. uint32_t max_tx_rx_desc_num, num_spt_pages;
  719. uint32_t num_entries;
  720. int i = 0;
  721. max_tx_rx_desc_num = WLAN_CFG_NUM_TX_DESC_MAX * MAX_TXDESC_POOLS +
  722. WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX * MAX_RXDESC_POOLS +
  723. WLAN_CFG_NUM_PPEDS_TX_DESC_MAX * MAX_PPE_TXDESC_POOLS;
  724. /* estimate how many SPT DDR pages needed */
  725. num_spt_pages = max_tx_rx_desc_num / DP_CC_SPT_PAGE_MAX_ENTRIES;
  726. num_spt_pages = num_spt_pages <= DP_CC_PPT_MAX_ENTRIES ?
  727. num_spt_pages : DP_CC_PPT_MAX_ENTRIES;
  728. be_soc->page_desc_base = qdf_mem_malloc(
  729. DP_CC_PPT_MAX_ENTRIES * sizeof(struct dp_spt_page_desc));
  730. if (!be_soc->page_desc_base) {
  731. dp_err("spt page descs allocation failed");
  732. return QDF_STATUS_E_NOMEM;
  733. }
  734. soc->wbm_sw0_bm_id = hal_tx_get_wbm_sw0_bm_id();
  735. qdf_status = dp_get_cmem_allocation(soc, COOKIE_CONVERSION);
  736. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  737. goto fail;
  738. dp_soc_mlo_fill_params(soc, params);
  739. qdf_status = dp_soc_ppeds_attach_be(soc);
  740. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  741. goto fail;
  742. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  743. num_entries = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  744. qdf_status =
  745. dp_hw_cookie_conversion_attach(be_soc,
  746. &be_soc->tx_cc_ctx[i],
  747. num_entries,
  748. DP_TX_DESC_TYPE, i);
  749. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  750. goto fail;
  751. }
  752. qdf_status = dp_get_cmem_allocation(soc, FISA_FST);
  753. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  754. goto fail;
  755. for (i = 0; i < MAX_RXDESC_POOLS; i++) {
  756. num_entries =
  757. wlan_cfg_get_dp_soc_rx_sw_desc_num(soc->wlan_cfg_ctx);
  758. qdf_status =
  759. dp_hw_cookie_conversion_attach(be_soc,
  760. &be_soc->rx_cc_ctx[i],
  761. num_entries,
  762. DP_RX_DESC_BUF_TYPE, i);
  763. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  764. goto fail;
  765. }
  766. return qdf_status;
  767. fail:
  768. dp_soc_detach_be(soc);
  769. return qdf_status;
  770. }
  771. static QDF_STATUS dp_soc_deinit_be(struct dp_soc *soc)
  772. {
  773. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  774. int i = 0;
  775. dp_tx_deinit_bank_profiles(be_soc);
  776. for (i = 0; i < MAX_TXDESC_POOLS; i++)
  777. dp_hw_cookie_conversion_deinit(be_soc,
  778. &be_soc->tx_cc_ctx[i]);
  779. for (i = 0; i < MAX_RXDESC_POOLS; i++)
  780. dp_hw_cookie_conversion_deinit(be_soc,
  781. &be_soc->rx_cc_ctx[i]);
  782. dp_ppeds_deinit_soc_be(soc);
  783. return QDF_STATUS_SUCCESS;
  784. }
  785. static QDF_STATUS dp_soc_init_be(struct dp_soc *soc)
  786. {
  787. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  788. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  789. int i = 0;
  790. dp_ppeds_init_soc_be(soc);
  791. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  792. qdf_status =
  793. dp_hw_cookie_conversion_init(be_soc,
  794. &be_soc->tx_cc_ctx[i]);
  795. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  796. goto fail;
  797. }
  798. for (i = 0; i < MAX_RXDESC_POOLS; i++) {
  799. qdf_status =
  800. dp_hw_cookie_conversion_init(be_soc,
  801. &be_soc->rx_cc_ctx[i]);
  802. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  803. goto fail;
  804. }
  805. /* route vdev_id mismatch notification via FW completion */
  806. hal_tx_vdev_mismatch_routing_set(soc->hal_soc,
  807. HAL_TX_VDEV_MISMATCH_FW_NOTIFY);
  808. qdf_status = dp_tx_init_bank_profiles(be_soc);
  809. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  810. goto fail;
  811. /* write WBM/REO cookie conversion CFG register */
  812. dp_cc_reg_cfg_init(soc, true);
  813. return qdf_status;
  814. fail:
  815. dp_soc_deinit_be(soc);
  816. return qdf_status;
  817. }
  818. static QDF_STATUS dp_pdev_attach_be(struct dp_pdev *pdev,
  819. struct cdp_pdev_attach_params *params)
  820. {
  821. dp_pdev_mlo_fill_params(pdev, params);
  822. return QDF_STATUS_SUCCESS;
  823. }
  824. static QDF_STATUS dp_pdev_detach_be(struct dp_pdev *pdev)
  825. {
  826. dp_mlo_update_link_to_pdev_unmap(pdev->soc, pdev);
  827. return QDF_STATUS_SUCCESS;
  828. }
  829. #ifdef INTRA_BSS_FWD_OFFLOAD
  830. static
  831. void dp_vdev_set_intra_bss(struct dp_soc *soc, uint16_t vdev_id, bool enable)
  832. {
  833. soc->cdp_soc.ol_ops->vdev_set_intra_bss(soc->ctrl_psoc, vdev_id,
  834. enable);
  835. }
  836. #else
  837. static
  838. void dp_vdev_set_intra_bss(struct dp_soc *soc, uint16_t vdev_id, bool enable)
  839. {
  840. }
  841. #endif
  842. static QDF_STATUS dp_vdev_attach_be(struct dp_soc *soc, struct dp_vdev *vdev)
  843. {
  844. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  845. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  846. struct dp_pdev *pdev = vdev->pdev;
  847. if (vdev->opmode == wlan_op_mode_monitor)
  848. return QDF_STATUS_SUCCESS;
  849. be_vdev->vdev_id_check_en = DP_TX_VDEV_ID_CHECK_ENABLE;
  850. be_vdev->bank_id = dp_tx_get_bank_profile(be_soc, be_vdev);
  851. vdev->bank_id = be_vdev->bank_id;
  852. if (be_vdev->bank_id == DP_BE_INVALID_BANK_ID) {
  853. QDF_BUG(0);
  854. return QDF_STATUS_E_FAULT;
  855. }
  856. if (vdev->opmode == wlan_op_mode_sta) {
  857. if (soc->cdp_soc.ol_ops->set_mec_timer)
  858. soc->cdp_soc.ol_ops->set_mec_timer(
  859. soc->ctrl_psoc,
  860. vdev->vdev_id,
  861. DP_AST_AGING_TIMER_DEFAULT_MS);
  862. if (pdev->isolation)
  863. hal_tx_vdev_mcast_ctrl_set(soc->hal_soc, vdev->vdev_id,
  864. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  865. else
  866. hal_tx_vdev_mcast_ctrl_set(soc->hal_soc, vdev->vdev_id,
  867. HAL_TX_MCAST_CTRL_MEC_NOTIFY);
  868. } else if (vdev->ap_bridge_enabled) {
  869. dp_vdev_set_intra_bss(soc, vdev->vdev_id, true);
  870. }
  871. dp_mlo_mcast_init(soc, vdev);
  872. dp_mlo_init_ptnr_list(vdev);
  873. return QDF_STATUS_SUCCESS;
  874. }
  875. static QDF_STATUS dp_vdev_detach_be(struct dp_soc *soc, struct dp_vdev *vdev)
  876. {
  877. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  878. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  879. if (vdev->opmode == wlan_op_mode_monitor)
  880. return QDF_STATUS_SUCCESS;
  881. if (vdev->opmode == wlan_op_mode_ap)
  882. dp_mlo_mcast_deinit(soc, vdev);
  883. dp_tx_put_bank_profile(be_soc, be_vdev);
  884. dp_clr_mlo_ptnr_list(soc, vdev);
  885. return QDF_STATUS_SUCCESS;
  886. }
  887. #ifdef WLAN_SUPPORT_PPEDS
  888. static QDF_STATUS dp_peer_setup_be(struct dp_soc *soc, struct dp_peer *peer)
  889. {
  890. struct dp_vdev_be *be_vdev;
  891. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  892. be_vdev = dp_get_be_vdev_from_dp_vdev(peer->vdev);
  893. if (!be_vdev) {
  894. qdf_err("BE vap is null");
  895. return QDF_STATUS_E_NULL_VALUE;
  896. }
  897. /*
  898. * Check if PPE DS routing is enabled on the associated vap.
  899. */
  900. if (be_vdev->ppe_vp_enabled == PPE_VP_USER_TYPE_DS)
  901. qdf_status = dp_peer_setup_ppeds_be(soc, peer, be_vdev);
  902. return qdf_status;
  903. }
  904. #else
  905. static QDF_STATUS dp_peer_setup_be(struct dp_soc *soc, struct dp_peer *peer)
  906. {
  907. return QDF_STATUS_SUCCESS;
  908. }
  909. #endif
  910. qdf_size_t dp_get_soc_context_size_be(void)
  911. {
  912. return sizeof(struct dp_soc_be);
  913. }
  914. #ifdef CONFIG_WORD_BASED_TLV
  915. /**
  916. * dp_rxdma_ring_wmask_cfg_be() - Setup RXDMA ring word mask config
  917. * @soc: Common DP soc handle
  918. * @htt_tlv_filter: Rx SRNG TLV and filter setting
  919. *
  920. * Return: none
  921. */
  922. static inline void
  923. dp_rxdma_ring_wmask_cfg_be(struct dp_soc *soc,
  924. struct htt_rx_ring_tlv_filter *htt_tlv_filter)
  925. {
  926. htt_tlv_filter->rx_msdu_end_wmask =
  927. hal_rx_msdu_end_wmask_get(soc->hal_soc);
  928. htt_tlv_filter->rx_mpdu_start_wmask =
  929. hal_rx_mpdu_start_wmask_get(soc->hal_soc);
  930. }
  931. #else
  932. static inline void
  933. dp_rxdma_ring_wmask_cfg_be(struct dp_soc *soc,
  934. struct htt_rx_ring_tlv_filter *htt_tlv_filter)
  935. {
  936. }
  937. #endif
  938. #ifdef WLAN_SUPPORT_PPEDS
  939. static
  940. void dp_free_ppeds_interrupts(struct dp_soc *soc, struct dp_srng *srng,
  941. int ring_type, int ring_num)
  942. {
  943. if (srng->irq >= 0) {
  944. if (ring_type == WBM2SW_RELEASE &&
  945. ring_num == WBM2_SW_PPE_REL_RING_ID)
  946. pld_pfrm_free_irq(soc->osdev->dev, srng->irq, soc);
  947. else if (ring_type == REO2PPE || ring_type == PPE2TCL)
  948. pld_pfrm_free_irq(soc->osdev->dev, srng->irq,
  949. dp_get_ppe_ds_ctxt(soc));
  950. }
  951. }
  952. static
  953. int dp_register_ppeds_interrupts(struct dp_soc *soc, struct dp_srng *srng,
  954. int vector, int ring_type, int ring_num)
  955. {
  956. int irq = -1, ret = 0;
  957. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  958. int pci_slot = pld_get_pci_slot(soc->osdev->dev);
  959. srng->irq = -1;
  960. irq = pld_get_msi_irq(soc->osdev->dev, vector);
  961. if (ring_type == WBM2SW_RELEASE &&
  962. ring_num == WBM2_SW_PPE_REL_RING_ID) {
  963. snprintf(be_soc->irq_name[2], DP_PPE_INTR_STRNG_LEN,
  964. "pci%d_ppe_wbm_rel", pci_slot);
  965. ret = pld_pfrm_request_irq(soc->osdev->dev, irq,
  966. dp_ppeds_handle_tx_comp,
  967. IRQF_SHARED | IRQF_NO_SUSPEND,
  968. be_soc->irq_name[2], (void *)soc);
  969. if (ret)
  970. goto fail;
  971. } else if (ring_type == REO2PPE && be_soc->ppeds_int_mode_enabled) {
  972. snprintf(be_soc->irq_name[0], DP_PPE_INTR_STRNG_LEN,
  973. "pci%d_reo2ppe", pci_slot);
  974. ret = pld_pfrm_request_irq(soc->osdev->dev, irq,
  975. dp_ppe_ds_reo2ppe_irq_handler,
  976. IRQF_SHARED | IRQF_NO_SUSPEND,
  977. be_soc->irq_name[0],
  978. dp_get_ppe_ds_ctxt(soc));
  979. if (ret)
  980. goto fail;
  981. } else if (ring_type == PPE2TCL && be_soc->ppeds_int_mode_enabled) {
  982. snprintf(be_soc->irq_name[1], DP_PPE_INTR_STRNG_LEN,
  983. "pci%d_ppe2tcl", pci_slot);
  984. ret = pld_pfrm_request_irq(soc->osdev->dev, irq,
  985. dp_ppe_ds_ppe2tcl_irq_handler,
  986. IRQF_SHARED | IRQF_NO_SUSPEND,
  987. be_soc->irq_name[1],
  988. dp_get_ppe_ds_ctxt(soc));
  989. if (ret)
  990. goto fail;
  991. pld_pfrm_disable_irq_nosync(soc->osdev->dev, irq);
  992. } else {
  993. return 0;
  994. }
  995. srng->irq = irq;
  996. dp_info("Registered irq %d for soc %pK ring type %d",
  997. irq, soc, ring_type);
  998. return 0;
  999. fail:
  1000. dp_err("Unable to config irq : ring type %d irq %d vector %d",
  1001. ring_type, irq, vector);
  1002. return ret;
  1003. }
  1004. void dp_ppeds_disable_irq(struct dp_soc *soc, struct dp_srng *srng)
  1005. {
  1006. if (srng->irq >= 0)
  1007. pld_pfrm_disable_irq_nosync(soc->osdev->dev, srng->irq);
  1008. }
  1009. void dp_ppeds_enable_irq(struct dp_soc *soc, struct dp_srng *srng)
  1010. {
  1011. if (srng->irq >= 0)
  1012. pld_pfrm_enable_irq(soc->osdev->dev, srng->irq);
  1013. }
  1014. #endif
  1015. #ifdef NO_RX_PKT_HDR_TLV
  1016. /**
  1017. * dp_rxdma_ring_sel_cfg_be() - Setup RXDMA ring config
  1018. * @soc: Common DP soc handle
  1019. *
  1020. * Return: QDF_STATUS
  1021. */
  1022. static QDF_STATUS
  1023. dp_rxdma_ring_sel_cfg_be(struct dp_soc *soc)
  1024. {
  1025. int i;
  1026. int mac_id;
  1027. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  1028. struct dp_srng *rx_mac_srng;
  1029. QDF_STATUS status = QDF_STATUS_SUCCESS;
  1030. /*
  1031. * In Beryllium chipset msdu_start, mpdu_end
  1032. * and rx_attn are part of msdu_end/mpdu_start
  1033. */
  1034. htt_tlv_filter.msdu_start = 0;
  1035. htt_tlv_filter.mpdu_end = 0;
  1036. htt_tlv_filter.attention = 0;
  1037. htt_tlv_filter.mpdu_start = 1;
  1038. htt_tlv_filter.msdu_end = 1;
  1039. htt_tlv_filter.packet = 1;
  1040. htt_tlv_filter.packet_header = 0;
  1041. htt_tlv_filter.ppdu_start = 0;
  1042. htt_tlv_filter.ppdu_end = 0;
  1043. htt_tlv_filter.ppdu_end_user_stats = 0;
  1044. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  1045. htt_tlv_filter.ppdu_end_status_done = 0;
  1046. htt_tlv_filter.enable_fp = 1;
  1047. htt_tlv_filter.enable_md = 0;
  1048. htt_tlv_filter.enable_md = 0;
  1049. htt_tlv_filter.enable_mo = 0;
  1050. htt_tlv_filter.fp_mgmt_filter = 0;
  1051. htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_BA_REQ;
  1052. htt_tlv_filter.fp_data_filter = (FILTER_DATA_UCAST |
  1053. FILTER_DATA_MCAST |
  1054. FILTER_DATA_DATA);
  1055. htt_tlv_filter.mo_mgmt_filter = 0;
  1056. htt_tlv_filter.mo_ctrl_filter = 0;
  1057. htt_tlv_filter.mo_data_filter = 0;
  1058. htt_tlv_filter.md_data_filter = 0;
  1059. htt_tlv_filter.offset_valid = true;
  1060. /* Not subscribing to mpdu_end, msdu_start and rx_attn */
  1061. htt_tlv_filter.rx_mpdu_end_offset = 0;
  1062. htt_tlv_filter.rx_msdu_start_offset = 0;
  1063. htt_tlv_filter.rx_attn_offset = 0;
  1064. /*
  1065. * For monitor mode, the packet hdr tlv is enabled later during
  1066. * filter update
  1067. */
  1068. if (soc->cdp_soc.ol_ops->get_con_mode &&
  1069. soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_MONITOR_MODE)
  1070. htt_tlv_filter.rx_packet_offset = soc->rx_mon_pkt_tlv_size;
  1071. else
  1072. htt_tlv_filter.rx_packet_offset = soc->rx_pkt_tlv_size;
  1073. /*Not subscribing rx_pkt_header*/
  1074. htt_tlv_filter.rx_header_offset = 0;
  1075. htt_tlv_filter.rx_mpdu_start_offset =
  1076. hal_rx_mpdu_start_offset_get(soc->hal_soc);
  1077. htt_tlv_filter.rx_msdu_end_offset =
  1078. hal_rx_msdu_end_offset_get(soc->hal_soc);
  1079. dp_rxdma_ring_wmask_cfg_be(soc, &htt_tlv_filter);
  1080. for (i = 0; i < MAX_PDEV_CNT; i++) {
  1081. struct dp_pdev *pdev = soc->pdev_list[i];
  1082. if (!pdev)
  1083. continue;
  1084. for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
  1085. int mac_for_pdev =
  1086. dp_get_mac_id_for_pdev(mac_id, pdev->pdev_id);
  1087. /*
  1088. * Obtain lmac id from pdev to access the LMAC ring
  1089. * in soc context
  1090. */
  1091. int lmac_id =
  1092. dp_get_lmac_id_for_pdev_id(soc, mac_id,
  1093. pdev->pdev_id);
  1094. rx_mac_srng = dp_get_rxdma_ring(pdev, lmac_id);
  1095. if (!rx_mac_srng->hal_srng)
  1096. continue;
  1097. htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev,
  1098. rx_mac_srng->hal_srng,
  1099. RXDMA_BUF, RX_DATA_BUFFER_SIZE,
  1100. &htt_tlv_filter);
  1101. }
  1102. }
  1103. return status;
  1104. }
  1105. #else
  1106. /**
  1107. * dp_rxdma_ring_sel_cfg_be() - Setup RXDMA ring config
  1108. * @soc: Common DP soc handle
  1109. *
  1110. * Return: QDF_STATUS
  1111. */
  1112. static QDF_STATUS
  1113. dp_rxdma_ring_sel_cfg_be(struct dp_soc *soc)
  1114. {
  1115. int i;
  1116. int mac_id;
  1117. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  1118. struct dp_srng *rx_mac_srng;
  1119. QDF_STATUS status = QDF_STATUS_SUCCESS;
  1120. /*
  1121. * In Beryllium chipset msdu_start, mpdu_end
  1122. * and rx_attn are part of msdu_end/mpdu_start
  1123. */
  1124. htt_tlv_filter.msdu_start = 0;
  1125. htt_tlv_filter.mpdu_end = 0;
  1126. htt_tlv_filter.attention = 0;
  1127. htt_tlv_filter.mpdu_start = 1;
  1128. htt_tlv_filter.msdu_end = 1;
  1129. htt_tlv_filter.packet = 1;
  1130. htt_tlv_filter.packet_header = 1;
  1131. htt_tlv_filter.ppdu_start = 0;
  1132. htt_tlv_filter.ppdu_end = 0;
  1133. htt_tlv_filter.ppdu_end_user_stats = 0;
  1134. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  1135. htt_tlv_filter.ppdu_end_status_done = 0;
  1136. htt_tlv_filter.enable_fp = 1;
  1137. htt_tlv_filter.enable_md = 0;
  1138. htt_tlv_filter.enable_md = 0;
  1139. htt_tlv_filter.enable_mo = 0;
  1140. htt_tlv_filter.fp_mgmt_filter = 0;
  1141. htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_BA_REQ;
  1142. htt_tlv_filter.fp_data_filter = (FILTER_DATA_UCAST |
  1143. FILTER_DATA_MCAST |
  1144. FILTER_DATA_DATA);
  1145. htt_tlv_filter.mo_mgmt_filter = 0;
  1146. htt_tlv_filter.mo_ctrl_filter = 0;
  1147. htt_tlv_filter.mo_data_filter = 0;
  1148. htt_tlv_filter.md_data_filter = 0;
  1149. htt_tlv_filter.offset_valid = true;
  1150. /* Not subscribing to mpdu_end, msdu_start and rx_attn */
  1151. htt_tlv_filter.rx_mpdu_end_offset = 0;
  1152. htt_tlv_filter.rx_msdu_start_offset = 0;
  1153. htt_tlv_filter.rx_attn_offset = 0;
  1154. /*
  1155. * For monitor mode, the packet hdr tlv is enabled later during
  1156. * filter update
  1157. */
  1158. if (soc->cdp_soc.ol_ops->get_con_mode &&
  1159. soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_MONITOR_MODE)
  1160. htt_tlv_filter.rx_packet_offset = soc->rx_mon_pkt_tlv_size;
  1161. else
  1162. htt_tlv_filter.rx_packet_offset = soc->rx_pkt_tlv_size;
  1163. htt_tlv_filter.rx_header_offset =
  1164. hal_rx_pkt_tlv_offset_get(soc->hal_soc);
  1165. htt_tlv_filter.rx_mpdu_start_offset =
  1166. hal_rx_mpdu_start_offset_get(soc->hal_soc);
  1167. htt_tlv_filter.rx_msdu_end_offset =
  1168. hal_rx_msdu_end_offset_get(soc->hal_soc);
  1169. dp_info("TLV subscription\n"
  1170. "msdu_start %d, mpdu_end %d, attention %d"
  1171. "mpdu_start %d, msdu_end %d, pkt_hdr %d, pkt %d\n"
  1172. "TLV offsets\n"
  1173. "msdu_start %d, mpdu_end %d, attention %d"
  1174. "mpdu_start %d, msdu_end %d, pkt_hdr %d, pkt %d\n",
  1175. htt_tlv_filter.msdu_start,
  1176. htt_tlv_filter.mpdu_end,
  1177. htt_tlv_filter.attention,
  1178. htt_tlv_filter.mpdu_start,
  1179. htt_tlv_filter.msdu_end,
  1180. htt_tlv_filter.packet_header,
  1181. htt_tlv_filter.packet,
  1182. htt_tlv_filter.rx_msdu_start_offset,
  1183. htt_tlv_filter.rx_mpdu_end_offset,
  1184. htt_tlv_filter.rx_attn_offset,
  1185. htt_tlv_filter.rx_mpdu_start_offset,
  1186. htt_tlv_filter.rx_msdu_end_offset,
  1187. htt_tlv_filter.rx_header_offset,
  1188. htt_tlv_filter.rx_packet_offset);
  1189. for (i = 0; i < MAX_PDEV_CNT; i++) {
  1190. struct dp_pdev *pdev = soc->pdev_list[i];
  1191. if (!pdev)
  1192. continue;
  1193. for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
  1194. int mac_for_pdev =
  1195. dp_get_mac_id_for_pdev(mac_id, pdev->pdev_id);
  1196. /*
  1197. * Obtain lmac id from pdev to access the LMAC ring
  1198. * in soc context
  1199. */
  1200. int lmac_id =
  1201. dp_get_lmac_id_for_pdev_id(soc, mac_id,
  1202. pdev->pdev_id);
  1203. rx_mac_srng = dp_get_rxdma_ring(pdev, lmac_id);
  1204. if (!rx_mac_srng->hal_srng)
  1205. continue;
  1206. htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev,
  1207. rx_mac_srng->hal_srng,
  1208. RXDMA_BUF, RX_DATA_BUFFER_SIZE,
  1209. &htt_tlv_filter);
  1210. }
  1211. }
  1212. return status;
  1213. }
  1214. #endif
  1215. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  1216. /**
  1217. * dp_service_near_full_srngs_be() - Main bottom half callback for the
  1218. * near-full IRQs.
  1219. * @soc: Datapath SoC handle
  1220. * @int_ctx: Interrupt context
  1221. * @dp_budget: Budget of the work that can be done in the bottom half
  1222. *
  1223. * Return: work done in the handler
  1224. */
  1225. static uint32_t
  1226. dp_service_near_full_srngs_be(struct dp_soc *soc, struct dp_intr *int_ctx,
  1227. uint32_t dp_budget)
  1228. {
  1229. int ring = 0;
  1230. int budget = dp_budget;
  1231. uint32_t work_done = 0;
  1232. uint32_t remaining_quota = dp_budget;
  1233. struct dp_intr_stats *intr_stats = &int_ctx->intr_stats;
  1234. int tx_ring_near_full_mask = int_ctx->tx_ring_near_full_mask;
  1235. int rx_near_full_grp_1_mask = int_ctx->rx_near_full_grp_1_mask;
  1236. int rx_near_full_grp_2_mask = int_ctx->rx_near_full_grp_2_mask;
  1237. int rx_near_full_mask = rx_near_full_grp_1_mask |
  1238. rx_near_full_grp_2_mask;
  1239. dp_verbose_debug("rx_ring_near_full 0x%x tx_ring_near_full 0x%x",
  1240. rx_near_full_mask,
  1241. tx_ring_near_full_mask);
  1242. if (rx_near_full_mask) {
  1243. for (ring = 0; ring < soc->num_reo_dest_rings; ring++) {
  1244. if (!(rx_near_full_mask & (1 << ring)))
  1245. continue;
  1246. work_done = dp_rx_nf_process(int_ctx,
  1247. soc->reo_dest_ring[ring].hal_srng,
  1248. ring, remaining_quota);
  1249. if (work_done) {
  1250. intr_stats->num_rx_ring_near_full_masks[ring]++;
  1251. dp_verbose_debug("rx NF mask 0x%x ring %d, work_done %d budget %d",
  1252. rx_near_full_mask, ring,
  1253. work_done,
  1254. budget);
  1255. budget -= work_done;
  1256. if (budget <= 0)
  1257. goto budget_done;
  1258. remaining_quota = budget;
  1259. }
  1260. }
  1261. }
  1262. if (tx_ring_near_full_mask) {
  1263. for (ring = 0; ring < soc->num_tcl_data_rings; ring++) {
  1264. if (!(tx_ring_near_full_mask & (1 << ring)))
  1265. continue;
  1266. work_done = dp_tx_comp_nf_handler(int_ctx, soc,
  1267. soc->tx_comp_ring[ring].hal_srng,
  1268. ring, remaining_quota);
  1269. if (work_done) {
  1270. intr_stats->num_tx_comp_ring_near_full_masks[ring]++;
  1271. dp_verbose_debug("tx NF mask 0x%x ring %d, work_done %d budget %d",
  1272. tx_ring_near_full_mask, ring,
  1273. work_done, budget);
  1274. budget -= work_done;
  1275. if (budget <= 0)
  1276. break;
  1277. remaining_quota = budget;
  1278. }
  1279. }
  1280. }
  1281. intr_stats->num_near_full_masks++;
  1282. budget_done:
  1283. return dp_budget - budget;
  1284. }
  1285. /**
  1286. * dp_srng_test_and_update_nf_params_be() - Check if the srng is in near full
  1287. * state and set the reap_limit appropriately
  1288. * as per the near full state
  1289. * @soc: Datapath soc handle
  1290. * @dp_srng: Datapath handle for SRNG
  1291. * @max_reap_limit: [Output Buffer] Buffer to set the max reap limit as per
  1292. * the srng near-full state
  1293. *
  1294. * Return: 1, if the srng is in near-full state
  1295. * 0, if the srng is not in near-full state
  1296. */
  1297. static int
  1298. dp_srng_test_and_update_nf_params_be(struct dp_soc *soc,
  1299. struct dp_srng *dp_srng,
  1300. int *max_reap_limit)
  1301. {
  1302. return _dp_srng_test_and_update_nf_params(soc, dp_srng, max_reap_limit);
  1303. }
  1304. /**
  1305. * dp_init_near_full_arch_ops_be() - Initialize the arch ops handler for the
  1306. * near full IRQ handling operations.
  1307. * @arch_ops: arch ops handle
  1308. *
  1309. * Return: none
  1310. */
  1311. static inline void
  1312. dp_init_near_full_arch_ops_be(struct dp_arch_ops *arch_ops)
  1313. {
  1314. arch_ops->dp_service_near_full_srngs = dp_service_near_full_srngs_be;
  1315. arch_ops->dp_srng_test_and_update_nf_params =
  1316. dp_srng_test_and_update_nf_params_be;
  1317. }
  1318. #else
  1319. static inline void
  1320. dp_init_near_full_arch_ops_be(struct dp_arch_ops *arch_ops)
  1321. {
  1322. }
  1323. #endif
  1324. #ifdef WLAN_SUPPORT_PPEDS
  1325. static void dp_soc_ppeds_srng_deinit(struct dp_soc *soc)
  1326. {
  1327. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1328. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  1329. soc_cfg_ctx = soc->wlan_cfg_ctx;
  1330. if (!wlan_cfg_get_dp_soc_is_ppeds_enabled(soc_cfg_ctx))
  1331. return;
  1332. dp_srng_deinit(soc, &be_soc->ppe2tcl_ring, PPE2TCL, 0);
  1333. wlan_minidump_remove(be_soc->ppe2tcl_ring.base_vaddr_unaligned,
  1334. be_soc->ppe2tcl_ring.alloc_size,
  1335. soc->ctrl_psoc,
  1336. WLAN_MD_DP_SRNG_PPE2TCL,
  1337. "ppe2tcl_ring");
  1338. dp_srng_deinit(soc, &be_soc->reo2ppe_ring, REO2PPE, 0);
  1339. wlan_minidump_remove(be_soc->reo2ppe_ring.base_vaddr_unaligned,
  1340. be_soc->reo2ppe_ring.alloc_size,
  1341. soc->ctrl_psoc,
  1342. WLAN_MD_DP_SRNG_REO2PPE,
  1343. "reo2ppe_ring");
  1344. dp_srng_deinit(soc, &be_soc->ppeds_wbm_release_ring, WBM2SW_RELEASE,
  1345. WBM2_SW_PPE_REL_RING_ID);
  1346. wlan_minidump_remove(be_soc->ppeds_wbm_release_ring.base_vaddr_unaligned,
  1347. be_soc->ppeds_wbm_release_ring.alloc_size,
  1348. soc->ctrl_psoc,
  1349. WLAN_MD_DP_SRNG_PPE_WBM2SW_RELEASE,
  1350. "ppeds_wbm_release_ring");
  1351. }
  1352. static void dp_soc_ppeds_srng_free(struct dp_soc *soc)
  1353. {
  1354. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1355. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  1356. soc_cfg_ctx = soc->wlan_cfg_ctx;
  1357. if (!wlan_cfg_get_dp_soc_is_ppeds_enabled(soc_cfg_ctx))
  1358. return;
  1359. dp_srng_free(soc, &be_soc->ppeds_wbm_release_ring);
  1360. dp_srng_free(soc, &be_soc->ppe2tcl_ring);
  1361. dp_srng_free(soc, &be_soc->reo2ppe_ring);
  1362. }
  1363. static QDF_STATUS dp_soc_ppeds_srng_alloc(struct dp_soc *soc)
  1364. {
  1365. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1366. uint32_t entries;
  1367. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  1368. soc_cfg_ctx = soc->wlan_cfg_ctx;
  1369. if (!wlan_cfg_get_dp_soc_is_ppeds_enabled(soc_cfg_ctx))
  1370. return QDF_STATUS_SUCCESS;
  1371. entries = wlan_cfg_get_dp_soc_reo2ppe_ring_size(soc_cfg_ctx);
  1372. if (dp_srng_alloc(soc, &be_soc->reo2ppe_ring, REO2PPE,
  1373. entries, 0)) {
  1374. dp_err("%pK: dp_srng_alloc failed for reo2ppe", soc);
  1375. goto fail;
  1376. }
  1377. entries = wlan_cfg_get_dp_soc_ppe2tcl_ring_size(soc_cfg_ctx);
  1378. if (dp_srng_alloc(soc, &be_soc->ppe2tcl_ring, PPE2TCL,
  1379. entries, 0)) {
  1380. dp_err("%pK: dp_srng_alloc failed for ppe2tcl_ring", soc);
  1381. goto fail;
  1382. }
  1383. entries = wlan_cfg_tx_comp_ring_size(soc_cfg_ctx);
  1384. if (dp_srng_alloc(soc, &be_soc->ppeds_wbm_release_ring, WBM2SW_RELEASE,
  1385. entries, 1)) {
  1386. dp_err("%pK: dp_srng_alloc failed for ppeds_wbm_release_ring",
  1387. soc);
  1388. goto fail;
  1389. }
  1390. return QDF_STATUS_SUCCESS;
  1391. fail:
  1392. dp_soc_ppeds_srng_free(soc);
  1393. return QDF_STATUS_E_NOMEM;
  1394. }
  1395. static QDF_STATUS dp_soc_ppeds_srng_init(struct dp_soc *soc)
  1396. {
  1397. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1398. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  1399. hal_soc_handle_t hal_soc = soc->hal_soc;
  1400. struct dp_ppe_ds_idxs idx = {0};
  1401. soc_cfg_ctx = soc->wlan_cfg_ctx;
  1402. if (!wlan_cfg_get_dp_soc_is_ppeds_enabled(soc_cfg_ctx))
  1403. return QDF_STATUS_SUCCESS;
  1404. if (dp_ppeds_register_soc_be(be_soc, &idx)) {
  1405. dp_err("%pK: ppeds registration failed", soc);
  1406. goto fail;
  1407. }
  1408. if (dp_srng_init_idx(soc, &be_soc->reo2ppe_ring, REO2PPE, 0, 0,
  1409. idx.reo2ppe_start_idx)) {
  1410. dp_err("%pK: dp_srng_init failed for reo2ppe", soc);
  1411. goto fail;
  1412. }
  1413. wlan_minidump_log(be_soc->reo2ppe_ring.base_vaddr_unaligned,
  1414. be_soc->reo2ppe_ring.alloc_size,
  1415. soc->ctrl_psoc,
  1416. WLAN_MD_DP_SRNG_REO2PPE,
  1417. "reo2ppe_ring");
  1418. hal_reo_config_reo2ppe_dest_info(hal_soc);
  1419. if (dp_srng_init_idx(soc, &be_soc->ppe2tcl_ring, PPE2TCL, 0, 0,
  1420. idx.ppe2tcl_start_idx)) {
  1421. dp_err("%pK: dp_srng_init failed for ppe2tcl_ring", soc);
  1422. goto fail;
  1423. }
  1424. wlan_minidump_log(be_soc->ppe2tcl_ring.base_vaddr_unaligned,
  1425. be_soc->ppe2tcl_ring.alloc_size,
  1426. soc->ctrl_psoc,
  1427. WLAN_MD_DP_SRNG_PPE2TCL,
  1428. "ppe2tcl_ring");
  1429. hal_tx_config_rbm_mapping_be(soc->hal_soc,
  1430. be_soc->ppe2tcl_ring.hal_srng,
  1431. WBM2_SW_PPE_REL_MAP_ID);
  1432. if (dp_srng_init(soc, &be_soc->ppeds_wbm_release_ring, WBM2SW_RELEASE,
  1433. WBM2_SW_PPE_REL_RING_ID, 0)) {
  1434. dp_err("%pK: dp_srng_init failed for ppeds_wbm_release_ring",
  1435. soc);
  1436. goto fail;
  1437. }
  1438. wlan_minidump_remove(be_soc->ppeds_wbm_release_ring.base_vaddr_unaligned,
  1439. be_soc->ppeds_wbm_release_ring.alloc_size,
  1440. soc->ctrl_psoc,
  1441. WLAN_MD_DP_SRNG_PPE_WBM2SW_RELEASE,
  1442. "ppeds_wbm_release_ring");
  1443. return QDF_STATUS_SUCCESS;
  1444. fail:
  1445. dp_soc_ppeds_srng_deinit(soc);
  1446. return QDF_STATUS_E_NOMEM;
  1447. }
  1448. #else
  1449. static void dp_soc_ppeds_srng_deinit(struct dp_soc *soc)
  1450. {
  1451. }
  1452. static void dp_soc_ppeds_srng_free(struct dp_soc *soc)
  1453. {
  1454. }
  1455. static QDF_STATUS dp_soc_ppeds_srng_alloc(struct dp_soc *soc)
  1456. {
  1457. return QDF_STATUS_SUCCESS;
  1458. }
  1459. static QDF_STATUS dp_soc_ppeds_srng_init(struct dp_soc *soc)
  1460. {
  1461. return QDF_STATUS_SUCCESS;
  1462. }
  1463. #endif
  1464. static void dp_soc_srng_deinit_be(struct dp_soc *soc)
  1465. {
  1466. uint32_t i;
  1467. dp_soc_ppeds_srng_deinit(soc);
  1468. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1469. for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
  1470. dp_srng_deinit(soc, &soc->rx_refill_buf_ring[i],
  1471. RXDMA_BUF, 0);
  1472. }
  1473. }
  1474. }
  1475. static void dp_soc_srng_free_be(struct dp_soc *soc)
  1476. {
  1477. uint32_t i;
  1478. dp_soc_ppeds_srng_free(soc);
  1479. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1480. for (i = 0; i < soc->num_rx_refill_buf_rings; i++)
  1481. dp_srng_free(soc, &soc->rx_refill_buf_ring[i]);
  1482. }
  1483. }
  1484. static QDF_STATUS dp_soc_srng_alloc_be(struct dp_soc *soc)
  1485. {
  1486. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  1487. uint32_t ring_size;
  1488. uint32_t i;
  1489. soc_cfg_ctx = soc->wlan_cfg_ctx;
  1490. ring_size = wlan_cfg_get_dp_soc_rxdma_refill_ring_size(soc_cfg_ctx);
  1491. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1492. for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
  1493. if (dp_srng_alloc(soc, &soc->rx_refill_buf_ring[i],
  1494. RXDMA_BUF, ring_size, 0)) {
  1495. dp_err("%pK: dp_srng_alloc failed refill ring",
  1496. soc);
  1497. goto fail;
  1498. }
  1499. }
  1500. }
  1501. if (dp_soc_ppeds_srng_alloc(soc)) {
  1502. dp_err("%pK: ppe rings alloc failed",
  1503. soc);
  1504. goto fail;
  1505. }
  1506. return QDF_STATUS_SUCCESS;
  1507. fail:
  1508. dp_soc_srng_free_be(soc);
  1509. return QDF_STATUS_E_NOMEM;
  1510. }
  1511. static QDF_STATUS dp_soc_srng_init_be(struct dp_soc *soc)
  1512. {
  1513. int i = 0;
  1514. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1515. for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
  1516. if (dp_srng_init(soc, &soc->rx_refill_buf_ring[i],
  1517. RXDMA_BUF, 0, 0)) {
  1518. dp_err("%pK: dp_srng_init failed refill ring",
  1519. soc);
  1520. goto fail;
  1521. }
  1522. }
  1523. }
  1524. if (dp_soc_ppeds_srng_init(soc)) {
  1525. dp_err("%pK: ppe ds rings init failed",
  1526. soc);
  1527. goto fail;
  1528. }
  1529. return QDF_STATUS_SUCCESS;
  1530. fail:
  1531. dp_soc_srng_deinit_be(soc);
  1532. return QDF_STATUS_E_NOMEM;
  1533. }
  1534. #ifdef WLAN_FEATURE_11BE_MLO
  1535. static inline unsigned
  1536. dp_mlo_peer_find_hash_index(dp_mld_peer_hash_obj_t mld_hash_obj,
  1537. union dp_align_mac_addr *mac_addr)
  1538. {
  1539. uint32_t index;
  1540. index =
  1541. mac_addr->align2.bytes_ab ^
  1542. mac_addr->align2.bytes_cd ^
  1543. mac_addr->align2.bytes_ef;
  1544. index ^= index >> mld_hash_obj->mld_peer_hash.idx_bits;
  1545. index &= mld_hash_obj->mld_peer_hash.mask;
  1546. return index;
  1547. }
  1548. QDF_STATUS
  1549. dp_mlo_peer_find_hash_attach_be(dp_mld_peer_hash_obj_t mld_hash_obj,
  1550. int hash_elems)
  1551. {
  1552. int i, log2;
  1553. if (!mld_hash_obj)
  1554. return QDF_STATUS_E_FAILURE;
  1555. hash_elems *= DP_PEER_HASH_LOAD_MULT;
  1556. hash_elems >>= DP_PEER_HASH_LOAD_SHIFT;
  1557. log2 = dp_log2_ceil(hash_elems);
  1558. hash_elems = 1 << log2;
  1559. mld_hash_obj->mld_peer_hash.mask = hash_elems - 1;
  1560. mld_hash_obj->mld_peer_hash.idx_bits = log2;
  1561. /* allocate an array of TAILQ peer object lists */
  1562. mld_hash_obj->mld_peer_hash.bins = qdf_mem_malloc(
  1563. hash_elems * sizeof(TAILQ_HEAD(anonymous_tail_q, dp_peer)));
  1564. if (!mld_hash_obj->mld_peer_hash.bins)
  1565. return QDF_STATUS_E_NOMEM;
  1566. for (i = 0; i < hash_elems; i++)
  1567. TAILQ_INIT(&mld_hash_obj->mld_peer_hash.bins[i]);
  1568. qdf_spinlock_create(&mld_hash_obj->mld_peer_hash_lock);
  1569. return QDF_STATUS_SUCCESS;
  1570. }
  1571. void
  1572. dp_mlo_peer_find_hash_detach_be(dp_mld_peer_hash_obj_t mld_hash_obj)
  1573. {
  1574. if (!mld_hash_obj)
  1575. return;
  1576. if (mld_hash_obj->mld_peer_hash.bins) {
  1577. qdf_mem_free(mld_hash_obj->mld_peer_hash.bins);
  1578. mld_hash_obj->mld_peer_hash.bins = NULL;
  1579. qdf_spinlock_destroy(&mld_hash_obj->mld_peer_hash_lock);
  1580. }
  1581. }
  1582. #ifdef WLAN_MLO_MULTI_CHIP
  1583. static QDF_STATUS dp_mlo_peer_find_hash_attach_wrapper(struct dp_soc *soc)
  1584. {
  1585. /* In case of MULTI chip MLO peer hash table when MLO global object
  1586. * is created, avoid from SOC attach path
  1587. */
  1588. return QDF_STATUS_SUCCESS;
  1589. }
  1590. static void dp_mlo_peer_find_hash_detach_wrapper(struct dp_soc *soc)
  1591. {
  1592. }
  1593. #else
  1594. static QDF_STATUS dp_mlo_peer_find_hash_attach_wrapper(struct dp_soc *soc)
  1595. {
  1596. dp_mld_peer_hash_obj_t mld_hash_obj;
  1597. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1598. if (!mld_hash_obj)
  1599. return QDF_STATUS_E_FAILURE;
  1600. return dp_mlo_peer_find_hash_attach_be(mld_hash_obj, soc->max_peers);
  1601. }
  1602. static void dp_mlo_peer_find_hash_detach_wrapper(struct dp_soc *soc)
  1603. {
  1604. dp_mld_peer_hash_obj_t mld_hash_obj;
  1605. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1606. if (!mld_hash_obj)
  1607. return;
  1608. return dp_mlo_peer_find_hash_detach_be(mld_hash_obj);
  1609. }
  1610. #endif
  1611. static struct dp_peer *
  1612. dp_mlo_peer_find_hash_find_be(struct dp_soc *soc,
  1613. uint8_t *peer_mac_addr,
  1614. int mac_addr_is_aligned,
  1615. enum dp_mod_id mod_id,
  1616. uint8_t vdev_id)
  1617. {
  1618. union dp_align_mac_addr local_mac_addr_aligned, *mac_addr;
  1619. uint32_t index;
  1620. struct dp_peer *peer;
  1621. struct dp_vdev *vdev;
  1622. dp_mld_peer_hash_obj_t mld_hash_obj;
  1623. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1624. if (!mld_hash_obj)
  1625. return NULL;
  1626. if (!mld_hash_obj->mld_peer_hash.bins)
  1627. return NULL;
  1628. if (mac_addr_is_aligned) {
  1629. mac_addr = (union dp_align_mac_addr *)peer_mac_addr;
  1630. } else {
  1631. qdf_mem_copy(
  1632. &local_mac_addr_aligned.raw[0],
  1633. peer_mac_addr, QDF_MAC_ADDR_SIZE);
  1634. mac_addr = &local_mac_addr_aligned;
  1635. }
  1636. if (vdev_id != DP_VDEV_ALL) {
  1637. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, mod_id);
  1638. if (!vdev) {
  1639. dp_err("vdev is null\n");
  1640. return NULL;
  1641. }
  1642. } else {
  1643. vdev = NULL;
  1644. }
  1645. /* search mld peer table if no link peer for given mac address */
  1646. index = dp_mlo_peer_find_hash_index(mld_hash_obj, mac_addr);
  1647. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1648. TAILQ_FOREACH(peer, &mld_hash_obj->mld_peer_hash.bins[index],
  1649. hash_list_elem) {
  1650. if (dp_peer_find_mac_addr_cmp(mac_addr, &peer->mac_addr) == 0) {
  1651. if ((vdev_id == DP_VDEV_ALL) || (
  1652. dp_peer_find_mac_addr_cmp(
  1653. &peer->vdev->mld_mac_addr,
  1654. &vdev->mld_mac_addr) == 0)) {
  1655. /* take peer reference before returning */
  1656. if (dp_peer_get_ref(NULL, peer, mod_id) !=
  1657. QDF_STATUS_SUCCESS)
  1658. peer = NULL;
  1659. if (vdev)
  1660. dp_vdev_unref_delete(soc, vdev, mod_id);
  1661. qdf_spin_unlock_bh(
  1662. &mld_hash_obj->mld_peer_hash_lock);
  1663. return peer;
  1664. }
  1665. }
  1666. }
  1667. if (vdev)
  1668. dp_vdev_unref_delete(soc, vdev, mod_id);
  1669. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1670. return NULL; /* failure */
  1671. }
  1672. static void
  1673. dp_mlo_peer_find_hash_remove_be(struct dp_soc *soc, struct dp_peer *peer)
  1674. {
  1675. uint32_t index;
  1676. struct dp_peer *tmppeer = NULL;
  1677. int found = 0;
  1678. dp_mld_peer_hash_obj_t mld_hash_obj;
  1679. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1680. if (!mld_hash_obj)
  1681. return;
  1682. index = dp_mlo_peer_find_hash_index(mld_hash_obj, &peer->mac_addr);
  1683. QDF_ASSERT(!TAILQ_EMPTY(&mld_hash_obj->mld_peer_hash.bins[index]));
  1684. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1685. TAILQ_FOREACH(tmppeer, &mld_hash_obj->mld_peer_hash.bins[index],
  1686. hash_list_elem) {
  1687. if (tmppeer == peer) {
  1688. found = 1;
  1689. break;
  1690. }
  1691. }
  1692. QDF_ASSERT(found);
  1693. TAILQ_REMOVE(&mld_hash_obj->mld_peer_hash.bins[index], peer,
  1694. hash_list_elem);
  1695. dp_info("Peer %pK (" QDF_MAC_ADDR_FMT ") removed. (found %u)",
  1696. peer, QDF_MAC_ADDR_REF(peer->mac_addr.raw), found);
  1697. dp_peer_unref_delete(peer, DP_MOD_ID_CONFIG);
  1698. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1699. }
  1700. static void
  1701. dp_mlo_peer_find_hash_add_be(struct dp_soc *soc, struct dp_peer *peer)
  1702. {
  1703. uint32_t index;
  1704. dp_mld_peer_hash_obj_t mld_hash_obj;
  1705. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1706. if (!mld_hash_obj)
  1707. return;
  1708. index = dp_mlo_peer_find_hash_index(mld_hash_obj, &peer->mac_addr);
  1709. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1710. if (QDF_IS_STATUS_ERROR(dp_peer_get_ref(NULL, peer,
  1711. DP_MOD_ID_CONFIG))) {
  1712. dp_err("fail to get peer ref:" QDF_MAC_ADDR_FMT,
  1713. QDF_MAC_ADDR_REF(peer->mac_addr.raw));
  1714. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1715. return;
  1716. }
  1717. TAILQ_INSERT_TAIL(&mld_hash_obj->mld_peer_hash.bins[index], peer,
  1718. hash_list_elem);
  1719. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1720. dp_info("Peer %pK (" QDF_MAC_ADDR_FMT ") added",
  1721. peer, QDF_MAC_ADDR_REF(peer->mac_addr.raw));
  1722. }
  1723. void dp_print_mlo_ast_stats_be(struct dp_soc *soc)
  1724. {
  1725. uint32_t index;
  1726. struct dp_peer *peer;
  1727. dp_mld_peer_hash_obj_t mld_hash_obj;
  1728. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1729. if (!mld_hash_obj)
  1730. return;
  1731. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1732. for (index = 0; index < mld_hash_obj->mld_peer_hash.mask; index++) {
  1733. TAILQ_FOREACH(peer, &mld_hash_obj->mld_peer_hash.bins[index],
  1734. hash_list_elem) {
  1735. dp_print_peer_ast_entries(soc, peer, NULL);
  1736. }
  1737. }
  1738. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1739. }
  1740. #endif
  1741. #if defined(DP_UMAC_HW_HARD_RESET) && defined(DP_UMAC_HW_RESET_SUPPORT)
  1742. static void dp_reconfig_tx_vdev_mcast_ctrl_be(struct dp_soc *soc,
  1743. struct dp_vdev *vdev)
  1744. {
  1745. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1746. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1747. hal_soc_handle_t hal_soc = soc->hal_soc;
  1748. uint8_t vdev_id = vdev->vdev_id;
  1749. if (vdev->opmode == wlan_op_mode_sta) {
  1750. if (vdev->pdev->isolation)
  1751. hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id,
  1752. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  1753. else
  1754. hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id,
  1755. HAL_TX_MCAST_CTRL_MEC_NOTIFY);
  1756. } else if (vdev->opmode == wlan_op_mode_ap) {
  1757. hal_tx_mcast_mlo_reinject_routing_set(
  1758. hal_soc,
  1759. HAL_TX_MCAST_MLO_REINJECT_TQM_NOTIFY);
  1760. if (vdev->mlo_vdev) {
  1761. hal_tx_vdev_mcast_ctrl_set(
  1762. hal_soc,
  1763. vdev_id,
  1764. HAL_TX_MCAST_CTRL_NO_SPECIAL);
  1765. } else {
  1766. hal_tx_vdev_mcast_ctrl_set(hal_soc,
  1767. vdev_id,
  1768. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  1769. }
  1770. }
  1771. }
  1772. static void dp_bank_reconfig_be(struct dp_soc *soc, struct dp_vdev *vdev)
  1773. {
  1774. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1775. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1776. union hal_tx_bank_config *bank_config;
  1777. if (!be_vdev || be_vdev->bank_id == DP_BE_INVALID_BANK_ID)
  1778. return;
  1779. bank_config = &be_soc->bank_profiles[be_vdev->bank_id].bank_config;
  1780. hal_tx_populate_bank_register(be_soc->soc.hal_soc, bank_config,
  1781. be_vdev->bank_id);
  1782. }
  1783. #endif
  1784. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  1785. defined(WLAN_MCAST_MLO)
  1786. static void dp_mlo_mcast_reset_pri_mcast(struct dp_vdev_be *be_vdev,
  1787. struct dp_vdev *ptnr_vdev,
  1788. void *arg)
  1789. {
  1790. struct dp_vdev_be *be_ptnr_vdev =
  1791. dp_get_be_vdev_from_dp_vdev(ptnr_vdev);
  1792. be_ptnr_vdev->mcast_primary = false;
  1793. }
  1794. static void dp_txrx_set_mlo_mcast_primary_vdev_param_be(
  1795. struct dp_vdev *vdev,
  1796. cdp_config_param_type val)
  1797. {
  1798. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1799. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(
  1800. be_vdev->vdev.pdev->soc);
  1801. be_vdev->mcast_primary = val.cdp_vdev_param_mcast_vdev;
  1802. vdev->mlo_vdev = true;
  1803. hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc,
  1804. vdev->vdev_id,
  1805. HAL_TX_MCAST_CTRL_NO_SPECIAL);
  1806. if (be_vdev->mcast_primary) {
  1807. dp_mcast_mlo_iter_ptnr_vdev(be_soc, be_vdev,
  1808. dp_mlo_mcast_reset_pri_mcast,
  1809. (void *)&be_vdev->mcast_primary,
  1810. DP_MOD_ID_TX_MCAST);
  1811. }
  1812. }
  1813. static void dp_txrx_reset_mlo_mcast_primary_vdev_param_be(
  1814. struct dp_vdev *vdev,
  1815. cdp_config_param_type val)
  1816. {
  1817. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1818. be_vdev->mcast_primary = false;
  1819. vdev->mlo_vdev = false;
  1820. hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc,
  1821. vdev->vdev_id,
  1822. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  1823. }
  1824. /**
  1825. * dp_txrx_get_vdev_mcast_param_be() - Target specific ops for getting vdev
  1826. * params related to multicast
  1827. * @soc: DP soc handle
  1828. * @vdev: pointer to vdev structure
  1829. * @val: buffer address
  1830. *
  1831. * Return: QDF_STATUS
  1832. */
  1833. static
  1834. QDF_STATUS dp_txrx_get_vdev_mcast_param_be(struct dp_soc *soc,
  1835. struct dp_vdev *vdev,
  1836. cdp_config_param_type *val)
  1837. {
  1838. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1839. if (be_vdev->mcast_primary)
  1840. val->cdp_vdev_param_mcast_vdev = true;
  1841. else
  1842. val->cdp_vdev_param_mcast_vdev = false;
  1843. return QDF_STATUS_SUCCESS;
  1844. }
  1845. #else
  1846. static void dp_txrx_set_mlo_mcast_primary_vdev_param_be(
  1847. struct dp_vdev *vdev,
  1848. cdp_config_param_type val)
  1849. {
  1850. }
  1851. static void dp_txrx_reset_mlo_mcast_primary_vdev_param_be(
  1852. struct dp_vdev *vdev,
  1853. cdp_config_param_type val)
  1854. {
  1855. }
  1856. static
  1857. QDF_STATUS dp_txrx_get_vdev_mcast_param_be(struct dp_soc *soc,
  1858. struct dp_vdev *vdev,
  1859. cdp_config_param_type *val)
  1860. {
  1861. return QDF_STATUS_SUCCESS;
  1862. }
  1863. #endif
  1864. #ifdef DP_TX_IMPLICIT_RBM_MAPPING
  1865. static void dp_tx_implicit_rbm_set_be(struct dp_soc *soc,
  1866. uint8_t tx_ring_id,
  1867. uint8_t bm_id)
  1868. {
  1869. hal_tx_config_rbm_mapping_be(soc->hal_soc,
  1870. soc->tcl_data_ring[tx_ring_id].hal_srng,
  1871. bm_id);
  1872. }
  1873. #else
  1874. static void dp_tx_implicit_rbm_set_be(struct dp_soc *soc,
  1875. uint8_t tx_ring_id,
  1876. uint8_t bm_id)
  1877. {
  1878. }
  1879. #endif
  1880. /**
  1881. * dp_txrx_set_vdev_param_be() - Target specific ops while setting vdev params
  1882. * @soc: DP soc handle
  1883. * @vdev: pointer to vdev structure
  1884. * @param: parameter type to get value
  1885. * @val: value
  1886. *
  1887. * Return: QDF_STATUS
  1888. */
  1889. static
  1890. QDF_STATUS dp_txrx_set_vdev_param_be(struct dp_soc *soc,
  1891. struct dp_vdev *vdev,
  1892. enum cdp_vdev_param_type param,
  1893. cdp_config_param_type val)
  1894. {
  1895. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1896. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1897. switch (param) {
  1898. case CDP_TX_ENCAP_TYPE:
  1899. case CDP_UPDATE_DSCP_TO_TID_MAP:
  1900. case CDP_UPDATE_TDLS_FLAGS:
  1901. dp_tx_update_bank_profile(be_soc, be_vdev);
  1902. break;
  1903. case CDP_ENABLE_CIPHER:
  1904. if (vdev->tx_encap_type == htt_cmn_pkt_type_raw)
  1905. dp_tx_update_bank_profile(be_soc, be_vdev);
  1906. break;
  1907. case CDP_SET_MCAST_VDEV:
  1908. dp_txrx_set_mlo_mcast_primary_vdev_param_be(vdev, val);
  1909. break;
  1910. case CDP_RESET_MLO_MCAST_VDEV:
  1911. dp_txrx_reset_mlo_mcast_primary_vdev_param_be(vdev, val);
  1912. break;
  1913. default:
  1914. dp_warn("invalid param %d", param);
  1915. break;
  1916. }
  1917. return QDF_STATUS_SUCCESS;
  1918. }
  1919. #ifdef WLAN_FEATURE_11BE_MLO
  1920. #ifdef DP_USE_REDUCED_PEER_ID_FIELD_WIDTH
  1921. static inline void
  1922. dp_soc_max_peer_id_set(struct dp_soc *soc)
  1923. {
  1924. soc->peer_id_shift = dp_log2_ceil(soc->max_peers);
  1925. soc->peer_id_mask = (1 << soc->peer_id_shift) - 1;
  1926. /*
  1927. * Double the peers since we use ML indication bit
  1928. * alongwith peer_id to find peers.
  1929. */
  1930. soc->max_peer_id = 1 << (soc->peer_id_shift + 1);
  1931. }
  1932. #else
  1933. static inline void
  1934. dp_soc_max_peer_id_set(struct dp_soc *soc)
  1935. {
  1936. soc->max_peer_id =
  1937. (1 << (HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID_S + 1)) - 1;
  1938. }
  1939. #endif /* DP_USE_REDUCED_PEER_ID_FIELD_WIDTH */
  1940. #else
  1941. static inline void
  1942. dp_soc_max_peer_id_set(struct dp_soc *soc)
  1943. {
  1944. soc->max_peer_id = soc->max_peers;
  1945. }
  1946. #endif /* WLAN_FEATURE_11BE_MLO */
  1947. static void dp_peer_map_detach_be(struct dp_soc *soc)
  1948. {
  1949. if (soc->host_ast_db_enable)
  1950. dp_peer_ast_hash_detach(soc);
  1951. }
  1952. static QDF_STATUS dp_peer_map_attach_be(struct dp_soc *soc)
  1953. {
  1954. QDF_STATUS status;
  1955. if (soc->host_ast_db_enable) {
  1956. status = dp_peer_ast_hash_attach(soc);
  1957. if (QDF_IS_STATUS_ERROR(status))
  1958. return status;
  1959. }
  1960. dp_soc_max_peer_id_set(soc);
  1961. return QDF_STATUS_SUCCESS;
  1962. }
  1963. static struct dp_peer *dp_find_peer_by_destmac_be(struct dp_soc *soc,
  1964. uint8_t *dest_mac,
  1965. uint8_t vdev_id)
  1966. {
  1967. struct dp_peer *peer = NULL;
  1968. struct dp_peer *tgt_peer = NULL;
  1969. struct dp_ast_entry *ast_entry = NULL;
  1970. uint16_t peer_id;
  1971. qdf_spin_lock_bh(&soc->ast_lock);
  1972. ast_entry = dp_peer_ast_hash_find_soc(soc, dest_mac);
  1973. if (!ast_entry) {
  1974. qdf_spin_unlock_bh(&soc->ast_lock);
  1975. dp_err("NULL ast entry");
  1976. return NULL;
  1977. }
  1978. peer_id = ast_entry->peer_id;
  1979. qdf_spin_unlock_bh(&soc->ast_lock);
  1980. if (peer_id == HTT_INVALID_PEER)
  1981. return NULL;
  1982. peer = dp_peer_get_ref_by_id(soc, peer_id, DP_MOD_ID_SAWF);
  1983. if (!peer) {
  1984. dp_err("NULL peer for peer_id:%d", peer_id);
  1985. return NULL;
  1986. }
  1987. tgt_peer = dp_get_tgt_peer_from_peer(peer);
  1988. /*
  1989. * Once tgt_peer is obtained,
  1990. * release the ref taken for original peer.
  1991. */
  1992. dp_peer_get_ref(NULL, tgt_peer, DP_MOD_ID_SAWF);
  1993. dp_peer_unref_delete(peer, DP_MOD_ID_SAWF);
  1994. return tgt_peer;
  1995. }
  1996. #ifdef WLAN_FEATURE_11BE_MLO
  1997. #ifdef WLAN_MCAST_MLO
  1998. static inline void
  1999. dp_initialize_arch_ops_be_mcast_mlo(struct dp_arch_ops *arch_ops)
  2000. {
  2001. arch_ops->dp_tx_mcast_handler = dp_tx_mlo_mcast_handler_be;
  2002. arch_ops->dp_rx_mcast_handler = dp_rx_mlo_igmp_handler;
  2003. arch_ops->dp_tx_is_mcast_primary = dp_tx_mlo_is_mcast_primary_be;
  2004. }
  2005. #else /* WLAN_MCAST_MLO */
  2006. static inline void
  2007. dp_initialize_arch_ops_be_mcast_mlo(struct dp_arch_ops *arch_ops)
  2008. {
  2009. }
  2010. #endif /* WLAN_MCAST_MLO */
  2011. #ifdef WLAN_MLO_MULTI_CHIP
  2012. static inline void
  2013. dp_initialize_arch_ops_be_mlo_multi_chip(struct dp_arch_ops *arch_ops)
  2014. {
  2015. arch_ops->dp_partner_chips_map = dp_mlo_partner_chips_map;
  2016. arch_ops->dp_partner_chips_unmap = dp_mlo_partner_chips_unmap;
  2017. arch_ops->dp_soc_get_by_idle_bm_id = dp_soc_get_by_idle_bm_id;
  2018. }
  2019. #else
  2020. static inline void
  2021. dp_initialize_arch_ops_be_mlo_multi_chip(struct dp_arch_ops *arch_ops)
  2022. {
  2023. }
  2024. #endif
  2025. static inline void
  2026. dp_initialize_arch_ops_be_mlo(struct dp_arch_ops *arch_ops)
  2027. {
  2028. dp_initialize_arch_ops_be_mcast_mlo(arch_ops);
  2029. dp_initialize_arch_ops_be_mlo_multi_chip(arch_ops);
  2030. arch_ops->mlo_peer_find_hash_detach =
  2031. dp_mlo_peer_find_hash_detach_wrapper;
  2032. arch_ops->mlo_peer_find_hash_attach =
  2033. dp_mlo_peer_find_hash_attach_wrapper;
  2034. arch_ops->mlo_peer_find_hash_add = dp_mlo_peer_find_hash_add_be;
  2035. arch_ops->mlo_peer_find_hash_remove = dp_mlo_peer_find_hash_remove_be;
  2036. arch_ops->mlo_peer_find_hash_find = dp_mlo_peer_find_hash_find_be;
  2037. }
  2038. #else /* WLAN_FEATURE_11BE_MLO */
  2039. static inline void
  2040. dp_initialize_arch_ops_be_mlo(struct dp_arch_ops *arch_ops)
  2041. {
  2042. }
  2043. #endif /* WLAN_FEATURE_11BE_MLO */
  2044. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP)
  2045. #define DP_LMAC_PEER_ID_MSB_LEGACY 2
  2046. #define DP_LMAC_PEER_ID_MSB_MLO 3
  2047. static void dp_peer_get_reo_hash_be(struct dp_vdev *vdev,
  2048. struct cdp_peer_setup_info *setup_info,
  2049. enum cdp_host_reo_dest_ring *reo_dest,
  2050. bool *hash_based,
  2051. uint8_t *lmac_peer_id_msb)
  2052. {
  2053. struct dp_soc *soc = vdev->pdev->soc;
  2054. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  2055. if (!be_soc->mlo_enabled)
  2056. return dp_vdev_get_default_reo_hash(vdev, reo_dest,
  2057. hash_based);
  2058. *hash_based = wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx);
  2059. *reo_dest = vdev->pdev->reo_dest;
  2060. /* Not a ML link peer use non-mlo */
  2061. if (!setup_info) {
  2062. *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_LEGACY;
  2063. return;
  2064. }
  2065. /* For STA ML VAP we do not have num links info at this point
  2066. * use MLO case always
  2067. */
  2068. if (vdev->opmode == wlan_op_mode_sta) {
  2069. *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_MLO;
  2070. return;
  2071. }
  2072. /* For AP ML VAP consider the peer as ML only it associates with
  2073. * multiple links
  2074. */
  2075. if (setup_info->num_links == 1) {
  2076. *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_LEGACY;
  2077. return;
  2078. }
  2079. *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_MLO;
  2080. }
  2081. static bool dp_reo_remap_config_be(struct dp_soc *soc,
  2082. uint32_t *remap0,
  2083. uint32_t *remap1,
  2084. uint32_t *remap2)
  2085. {
  2086. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  2087. uint32_t reo_config = wlan_cfg_get_reo_rings_mapping(soc->wlan_cfg_ctx);
  2088. uint32_t reo_mlo_config =
  2089. wlan_cfg_mlo_rx_ring_map_get(soc->wlan_cfg_ctx);
  2090. if (!be_soc->mlo_enabled)
  2091. return dp_reo_remap_config(soc, remap0, remap1, remap2);
  2092. *remap0 = hal_reo_ix_remap_value_get_be(soc->hal_soc, reo_mlo_config);
  2093. *remap1 = hal_reo_ix_remap_value_get_be(soc->hal_soc, reo_config);
  2094. *remap2 = hal_reo_ix_remap_value_get_be(soc->hal_soc, reo_mlo_config);
  2095. return true;
  2096. }
  2097. #else
  2098. static void dp_peer_get_reo_hash_be(struct dp_vdev *vdev,
  2099. struct cdp_peer_setup_info *setup_info,
  2100. enum cdp_host_reo_dest_ring *reo_dest,
  2101. bool *hash_based,
  2102. uint8_t *lmac_peer_id_msb)
  2103. {
  2104. dp_vdev_get_default_reo_hash(vdev, reo_dest, hash_based);
  2105. }
  2106. static bool dp_reo_remap_config_be(struct dp_soc *soc,
  2107. uint32_t *remap0,
  2108. uint32_t *remap1,
  2109. uint32_t *remap2)
  2110. {
  2111. return dp_reo_remap_config(soc, remap0, remap1, remap2);
  2112. }
  2113. #endif
  2114. #ifdef IPA_OFFLOAD
  2115. static int8_t dp_ipa_get_bank_id_be(struct dp_soc *soc)
  2116. {
  2117. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  2118. return be_soc->ipa_bank_id;
  2119. }
  2120. static inline void dp_initialize_arch_ops_be_ipa(struct dp_arch_ops *arch_ops)
  2121. {
  2122. arch_ops->ipa_get_bank_id = dp_ipa_get_bank_id_be;
  2123. }
  2124. #else /* !IPA_OFFLOAD */
  2125. static inline void dp_initialize_arch_ops_be_ipa(struct dp_arch_ops *arch_ops)
  2126. {
  2127. }
  2128. #endif /* IPA_OFFLOAD */
  2129. void dp_initialize_arch_ops_be(struct dp_arch_ops *arch_ops)
  2130. {
  2131. #ifndef QCA_HOST_MODE_WIFI_DISABLED
  2132. arch_ops->tx_hw_enqueue = dp_tx_hw_enqueue_be;
  2133. arch_ops->dp_rx_process = dp_rx_process_be;
  2134. arch_ops->dp_tx_send_fast = dp_tx_fast_send_be;
  2135. arch_ops->tx_comp_get_params_from_hal_desc =
  2136. dp_tx_comp_get_params_from_hal_desc_be;
  2137. arch_ops->dp_tx_process_htt_completion =
  2138. dp_tx_process_htt_completion_be;
  2139. arch_ops->dp_tx_desc_pool_init = dp_tx_desc_pool_init_be;
  2140. arch_ops->dp_tx_desc_pool_deinit = dp_tx_desc_pool_deinit_be;
  2141. arch_ops->dp_rx_desc_pool_init = dp_rx_desc_pool_init_be;
  2142. arch_ops->dp_rx_desc_pool_deinit = dp_rx_desc_pool_deinit_be;
  2143. arch_ops->dp_wbm_get_rx_desc_from_hal_desc =
  2144. dp_wbm_get_rx_desc_from_hal_desc_be;
  2145. arch_ops->dp_tx_compute_hw_delay = dp_tx_compute_tx_delay_be;
  2146. arch_ops->dp_rx_chain_msdus = dp_rx_chain_msdus_be;
  2147. #endif
  2148. arch_ops->txrx_get_context_size = dp_get_context_size_be;
  2149. #ifdef WIFI_MONITOR_SUPPORT
  2150. arch_ops->txrx_get_mon_context_size = dp_mon_get_context_size_be;
  2151. #endif
  2152. arch_ops->dp_rx_desc_cookie_2_va =
  2153. dp_rx_desc_cookie_2_va_be;
  2154. arch_ops->dp_rx_intrabss_mcast_handler =
  2155. dp_rx_intrabss_mcast_handler_be;
  2156. arch_ops->dp_rx_word_mask_subscribe = dp_rx_word_mask_subscribe_be;
  2157. arch_ops->txrx_soc_attach = dp_soc_attach_be;
  2158. arch_ops->txrx_soc_detach = dp_soc_detach_be;
  2159. arch_ops->txrx_soc_init = dp_soc_init_be;
  2160. arch_ops->txrx_soc_deinit = dp_soc_deinit_be;
  2161. arch_ops->txrx_soc_srng_alloc = dp_soc_srng_alloc_be;
  2162. arch_ops->txrx_soc_srng_init = dp_soc_srng_init_be;
  2163. arch_ops->txrx_soc_srng_deinit = dp_soc_srng_deinit_be;
  2164. arch_ops->txrx_soc_srng_free = dp_soc_srng_free_be;
  2165. arch_ops->txrx_pdev_attach = dp_pdev_attach_be;
  2166. arch_ops->txrx_pdev_detach = dp_pdev_detach_be;
  2167. arch_ops->txrx_vdev_attach = dp_vdev_attach_be;
  2168. arch_ops->txrx_vdev_detach = dp_vdev_detach_be;
  2169. arch_ops->txrx_peer_setup = dp_peer_setup_be;
  2170. arch_ops->txrx_peer_map_attach = dp_peer_map_attach_be;
  2171. arch_ops->txrx_peer_map_detach = dp_peer_map_detach_be;
  2172. arch_ops->dp_rxdma_ring_sel_cfg = dp_rxdma_ring_sel_cfg_be;
  2173. arch_ops->dp_rx_peer_metadata_peer_id_get =
  2174. dp_rx_peer_metadata_peer_id_get_be;
  2175. arch_ops->soc_cfg_attach = dp_soc_cfg_attach_be;
  2176. arch_ops->tx_implicit_rbm_set = dp_tx_implicit_rbm_set_be;
  2177. arch_ops->txrx_set_vdev_param = dp_txrx_set_vdev_param_be;
  2178. dp_initialize_arch_ops_be_mlo(arch_ops);
  2179. arch_ops->dp_rx_replenish_soc_get = dp_rx_replensih_soc_get;
  2180. arch_ops->dp_soc_get_num_soc = dp_soc_get_num_soc_be;
  2181. arch_ops->dp_peer_rx_reorder_queue_setup =
  2182. dp_peer_rx_reorder_queue_setup_be;
  2183. arch_ops->txrx_print_peer_stats = dp_print_peer_txrx_stats_be;
  2184. arch_ops->dp_find_peer_by_destmac = dp_find_peer_by_destmac_be;
  2185. #if defined(DP_UMAC_HW_HARD_RESET) && defined(DP_UMAC_HW_RESET_SUPPORT)
  2186. arch_ops->dp_bank_reconfig = dp_bank_reconfig_be;
  2187. arch_ops->dp_reconfig_tx_vdev_mcast_ctrl =
  2188. dp_reconfig_tx_vdev_mcast_ctrl_be;
  2189. arch_ops->dp_cc_reg_cfg_init = dp_cc_reg_cfg_init;
  2190. #endif
  2191. #ifdef WLAN_SUPPORT_PPEDS
  2192. arch_ops->dp_txrx_ppeds_rings_status = dp_ppeds_rings_status;
  2193. arch_ops->txrx_soc_ppeds_start = dp_ppeds_start_soc_be;
  2194. arch_ops->txrx_soc_ppeds_stop = dp_ppeds_stop_soc_be;
  2195. arch_ops->dp_register_ppeds_interrupts = dp_register_ppeds_interrupts;
  2196. arch_ops->dp_free_ppeds_interrupts = dp_free_ppeds_interrupts;
  2197. arch_ops->dp_tx_ppeds_inuse_desc = dp_ppeds_inuse_desc;
  2198. arch_ops->dp_tx_ppeds_cfg_astidx_cache_mapping =
  2199. dp_tx_ppeds_cfg_astidx_cache_mapping;
  2200. #endif
  2201. dp_init_near_full_arch_ops_be(arch_ops);
  2202. arch_ops->get_reo_qdesc_addr = dp_rx_get_reo_qdesc_addr_be;
  2203. arch_ops->get_rx_hash_key = dp_get_rx_hash_key_be;
  2204. arch_ops->dp_set_rx_fst = dp_set_rx_fst_be;
  2205. arch_ops->dp_get_rx_fst = dp_get_rx_fst_be;
  2206. arch_ops->dp_rx_fst_deref = dp_rx_fst_deref_be;
  2207. arch_ops->dp_rx_fst_ref = dp_rx_fst_ref_be;
  2208. arch_ops->print_mlo_ast_stats = dp_print_mlo_ast_stats_be;
  2209. arch_ops->peer_get_reo_hash = dp_peer_get_reo_hash_be;
  2210. arch_ops->reo_remap_config = dp_reo_remap_config_be;
  2211. arch_ops->txrx_get_vdev_mcast_param = dp_txrx_get_vdev_mcast_param_be;
  2212. dp_initialize_arch_ops_be_ipa(arch_ops);
  2213. }