bus.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include "bus.h"
  7. #include "debug.h"
  8. #include "pci.h"
  9. enum cnss_dev_bus_type cnss_get_dev_bus_type(struct device *dev)
  10. {
  11. if (!dev)
  12. return CNSS_BUS_NONE;
  13. if (!dev->bus)
  14. return CNSS_BUS_NONE;
  15. if (memcmp(dev->bus->name, "pci", 3) == 0)
  16. return CNSS_BUS_PCI;
  17. else
  18. return CNSS_BUS_NONE;
  19. }
  20. enum cnss_dev_bus_type cnss_get_bus_type(struct cnss_plat_data *plat_priv)
  21. {
  22. int ret;
  23. struct device *dev;
  24. u32 bus_type_dt = CNSS_BUS_NONE;
  25. if (plat_priv->dt_type == CNSS_DTT_MULTIEXCHG) {
  26. dev = &plat_priv->plat_dev->dev;
  27. ret = of_property_read_u32(dev->of_node, "qcom,bus-type",
  28. &bus_type_dt);
  29. if (!ret)
  30. if (bus_type_dt < CNSS_BUS_MAX)
  31. cnss_pr_dbg("Got bus type[%u] from dt\n",
  32. bus_type_dt);
  33. else
  34. bus_type_dt = CNSS_BUS_NONE;
  35. else
  36. cnss_pr_err("No bus type for multi-exchg dt\n");
  37. return bus_type_dt;
  38. }
  39. switch (plat_priv->device_id) {
  40. case QCA6174_DEVICE_ID:
  41. case QCA6290_DEVICE_ID:
  42. case QCA6390_DEVICE_ID:
  43. case QCN7605_DEVICE_ID:
  44. case QCA6490_DEVICE_ID:
  45. case KIWI_DEVICE_ID:
  46. case MANGO_DEVICE_ID:
  47. case PEACH_DEVICE_ID:
  48. return CNSS_BUS_PCI;
  49. default:
  50. cnss_pr_err("Unknown device_id: 0x%lx\n", plat_priv->device_id);
  51. return CNSS_BUS_NONE;
  52. }
  53. }
  54. void *cnss_bus_dev_to_bus_priv(struct device *dev)
  55. {
  56. if (!dev)
  57. return NULL;
  58. switch (cnss_get_dev_bus_type(dev)) {
  59. case CNSS_BUS_PCI:
  60. return cnss_get_pci_priv(to_pci_dev(dev));
  61. default:
  62. return NULL;
  63. }
  64. }
  65. struct cnss_plat_data *cnss_bus_dev_to_plat_priv(struct device *dev)
  66. {
  67. void *bus_priv;
  68. if (!dev)
  69. return cnss_get_plat_priv(NULL);
  70. bus_priv = cnss_bus_dev_to_bus_priv(dev);
  71. if (!bus_priv)
  72. return NULL;
  73. switch (cnss_get_dev_bus_type(dev)) {
  74. case CNSS_BUS_PCI:
  75. return cnss_pci_priv_to_plat_priv(bus_priv);
  76. default:
  77. return NULL;
  78. }
  79. }
  80. int cnss_bus_init(struct cnss_plat_data *plat_priv)
  81. {
  82. if (!plat_priv)
  83. return -ENODEV;
  84. switch (plat_priv->bus_type) {
  85. case CNSS_BUS_PCI:
  86. return cnss_pci_init(plat_priv);
  87. default:
  88. cnss_pr_err("Unsupported bus type: %d\n",
  89. plat_priv->bus_type);
  90. return -EINVAL;
  91. }
  92. }
  93. void cnss_bus_deinit(struct cnss_plat_data *plat_priv)
  94. {
  95. if (!plat_priv)
  96. return;
  97. switch (plat_priv->bus_type) {
  98. case CNSS_BUS_PCI:
  99. return cnss_pci_deinit(plat_priv);
  100. default:
  101. cnss_pr_err("Unsupported bus type: %d\n",
  102. plat_priv->bus_type);
  103. return;
  104. }
  105. }
  106. void cnss_bus_add_fw_prefix_name(struct cnss_plat_data *plat_priv,
  107. char *prefix_name, char *name)
  108. {
  109. if (!plat_priv)
  110. return;
  111. switch (plat_priv->bus_type) {
  112. case CNSS_BUS_PCI:
  113. return cnss_pci_add_fw_prefix_name(plat_priv->bus_priv,
  114. prefix_name, name);
  115. default:
  116. cnss_pr_err("Unsupported bus type: %d\n",
  117. plat_priv->bus_type);
  118. return;
  119. }
  120. }
  121. int cnss_bus_load_m3(struct cnss_plat_data *plat_priv)
  122. {
  123. if (!plat_priv)
  124. return -ENODEV;
  125. switch (plat_priv->bus_type) {
  126. case CNSS_BUS_PCI:
  127. return cnss_pci_load_m3(plat_priv->bus_priv);
  128. default:
  129. cnss_pr_err("Unsupported bus type: %d\n",
  130. plat_priv->bus_type);
  131. return -EINVAL;
  132. }
  133. }
  134. int cnss_bus_load_aux(struct cnss_plat_data *plat_priv)
  135. {
  136. if (!plat_priv)
  137. return -ENODEV;
  138. switch (plat_priv->bus_type) {
  139. case CNSS_BUS_PCI:
  140. return cnss_pci_load_aux(plat_priv->bus_priv);
  141. default:
  142. cnss_pr_err("Unsupported bus type: %d\n",
  143. plat_priv->bus_type);
  144. return -EINVAL;
  145. }
  146. }
  147. int cnss_bus_handle_dev_sol_irq(struct cnss_plat_data *plat_priv)
  148. {
  149. if (!plat_priv)
  150. return -ENODEV;
  151. switch (plat_priv->bus_type) {
  152. case CNSS_BUS_PCI:
  153. return cnss_pci_handle_dev_sol_irq(plat_priv->bus_priv);
  154. default:
  155. cnss_pr_err("Unsupported bus type: %d\n",
  156. plat_priv->bus_type);
  157. return -EINVAL;
  158. }
  159. }
  160. int cnss_bus_alloc_fw_mem(struct cnss_plat_data *plat_priv)
  161. {
  162. if (!plat_priv)
  163. return -ENODEV;
  164. switch (plat_priv->bus_type) {
  165. case CNSS_BUS_PCI:
  166. return cnss_pci_alloc_fw_mem(plat_priv->bus_priv);
  167. default:
  168. cnss_pr_err("Unsupported bus type: %d\n",
  169. plat_priv->bus_type);
  170. return -EINVAL;
  171. }
  172. }
  173. int cnss_bus_alloc_qdss_mem(struct cnss_plat_data *plat_priv)
  174. {
  175. if (!plat_priv)
  176. return -ENODEV;
  177. switch (plat_priv->bus_type) {
  178. case CNSS_BUS_PCI:
  179. return cnss_pci_alloc_qdss_mem(plat_priv->bus_priv);
  180. default:
  181. cnss_pr_err("Unsupported bus type: %d\n",
  182. plat_priv->bus_type);
  183. return -EINVAL;
  184. }
  185. }
  186. void cnss_bus_free_qdss_mem(struct cnss_plat_data *plat_priv)
  187. {
  188. if (!plat_priv)
  189. return;
  190. switch (plat_priv->bus_type) {
  191. case CNSS_BUS_PCI:
  192. cnss_pci_free_qdss_mem(plat_priv->bus_priv);
  193. return;
  194. default:
  195. cnss_pr_err("Unsupported bus type: %d\n",
  196. plat_priv->bus_type);
  197. return;
  198. }
  199. }
  200. u32 cnss_bus_get_wake_irq(struct cnss_plat_data *plat_priv)
  201. {
  202. if (!plat_priv)
  203. return -ENODEV;
  204. switch (plat_priv->bus_type) {
  205. case CNSS_BUS_PCI:
  206. return cnss_pci_get_wake_msi(plat_priv->bus_priv);
  207. default:
  208. cnss_pr_err("Unsupported bus type: %d\n",
  209. plat_priv->bus_type);
  210. return -EINVAL;
  211. }
  212. }
  213. int cnss_bus_force_fw_assert_hdlr(struct cnss_plat_data *plat_priv)
  214. {
  215. if (!plat_priv)
  216. return -ENODEV;
  217. switch (plat_priv->bus_type) {
  218. case CNSS_BUS_PCI:
  219. return cnss_pci_force_fw_assert_hdlr(plat_priv->bus_priv);
  220. default:
  221. cnss_pr_err("Unsupported bus type: %d\n",
  222. plat_priv->bus_type);
  223. return -EINVAL;
  224. }
  225. }
  226. int cnss_bus_qmi_send_get(struct cnss_plat_data *plat_priv)
  227. {
  228. if (!plat_priv)
  229. return -ENODEV;
  230. switch (plat_priv->bus_type) {
  231. case CNSS_BUS_PCI:
  232. return cnss_pci_qmi_send_get(plat_priv->bus_priv);
  233. default:
  234. cnss_pr_err("Unsupported bus type: %d\n",
  235. plat_priv->bus_type);
  236. return -EINVAL;
  237. }
  238. }
  239. int cnss_bus_qmi_send_put(struct cnss_plat_data *plat_priv)
  240. {
  241. if (!plat_priv)
  242. return -ENODEV;
  243. switch (plat_priv->bus_type) {
  244. case CNSS_BUS_PCI:
  245. return cnss_pci_qmi_send_put(plat_priv->bus_priv);
  246. default:
  247. cnss_pr_err("Unsupported bus type: %d\n",
  248. plat_priv->bus_type);
  249. return -EINVAL;
  250. }
  251. }
  252. void cnss_bus_fw_boot_timeout_hdlr(struct timer_list *t)
  253. {
  254. struct cnss_plat_data *plat_priv =
  255. from_timer(plat_priv, t, fw_boot_timer);
  256. if (!plat_priv)
  257. return;
  258. switch (plat_priv->bus_type) {
  259. case CNSS_BUS_PCI:
  260. return cnss_pci_fw_boot_timeout_hdlr(plat_priv->bus_priv);
  261. default:
  262. cnss_pr_err("Unsupported bus type: %d\n",
  263. plat_priv->bus_type);
  264. return;
  265. }
  266. }
  267. void cnss_bus_collect_dump_info(struct cnss_plat_data *plat_priv, bool in_panic)
  268. {
  269. if (!plat_priv)
  270. return;
  271. switch (plat_priv->bus_type) {
  272. case CNSS_BUS_PCI:
  273. return cnss_pci_collect_dump_info(plat_priv->bus_priv,
  274. in_panic);
  275. default:
  276. cnss_pr_err("Unsupported bus type: %d\n",
  277. plat_priv->bus_type);
  278. return;
  279. }
  280. }
  281. void cnss_bus_device_crashed(struct cnss_plat_data *plat_priv)
  282. {
  283. if (!plat_priv)
  284. return;
  285. switch (plat_priv->bus_type) {
  286. case CNSS_BUS_PCI:
  287. return cnss_pci_device_crashed(plat_priv->bus_priv);
  288. default:
  289. cnss_pr_err("Unsupported bus type: %d\n",
  290. plat_priv->bus_type);
  291. return;
  292. }
  293. }
  294. int cnss_bus_call_driver_probe(struct cnss_plat_data *plat_priv)
  295. {
  296. if (!plat_priv)
  297. return -ENODEV;
  298. switch (plat_priv->bus_type) {
  299. case CNSS_BUS_PCI:
  300. return cnss_pci_call_driver_probe(plat_priv->bus_priv);
  301. default:
  302. cnss_pr_err("Unsupported bus type: %d\n",
  303. plat_priv->bus_type);
  304. return -EINVAL;
  305. }
  306. }
  307. int cnss_bus_call_driver_remove(struct cnss_plat_data *plat_priv)
  308. {
  309. if (!plat_priv)
  310. return -ENODEV;
  311. switch (plat_priv->bus_type) {
  312. case CNSS_BUS_PCI:
  313. return cnss_pci_call_driver_remove(plat_priv->bus_priv);
  314. default:
  315. cnss_pr_err("Unsupported bus type: %d\n",
  316. plat_priv->bus_type);
  317. return -EINVAL;
  318. }
  319. }
  320. int cnss_bus_dev_powerup(struct cnss_plat_data *plat_priv)
  321. {
  322. if (!plat_priv)
  323. return -ENODEV;
  324. switch (plat_priv->bus_type) {
  325. case CNSS_BUS_PCI:
  326. return cnss_pci_dev_powerup(plat_priv->bus_priv);
  327. default:
  328. cnss_pr_err("Unsupported bus type: %d\n",
  329. plat_priv->bus_type);
  330. return -EINVAL;
  331. }
  332. }
  333. int cnss_bus_dev_shutdown(struct cnss_plat_data *plat_priv)
  334. {
  335. if (!plat_priv)
  336. return -ENODEV;
  337. switch (plat_priv->bus_type) {
  338. case CNSS_BUS_PCI:
  339. return cnss_pci_dev_shutdown(plat_priv->bus_priv);
  340. default:
  341. cnss_pr_err("Unsupported bus type: %d\n",
  342. plat_priv->bus_type);
  343. return -EINVAL;
  344. }
  345. }
  346. int cnss_bus_dev_crash_shutdown(struct cnss_plat_data *plat_priv)
  347. {
  348. if (!plat_priv)
  349. return -ENODEV;
  350. switch (plat_priv->bus_type) {
  351. case CNSS_BUS_PCI:
  352. return cnss_pci_dev_crash_shutdown(plat_priv->bus_priv);
  353. default:
  354. cnss_pr_err("Unsupported bus type: %d\n",
  355. plat_priv->bus_type);
  356. return -EINVAL;
  357. }
  358. }
  359. int cnss_bus_dev_ramdump(struct cnss_plat_data *plat_priv)
  360. {
  361. if (!plat_priv)
  362. return -ENODEV;
  363. switch (plat_priv->bus_type) {
  364. case CNSS_BUS_PCI:
  365. return cnss_pci_dev_ramdump(plat_priv->bus_priv);
  366. default:
  367. cnss_pr_err("Unsupported bus type: %d\n",
  368. plat_priv->bus_type);
  369. return -EINVAL;
  370. }
  371. }
  372. int cnss_bus_register_driver_hdlr(struct cnss_plat_data *plat_priv, void *data)
  373. {
  374. if (!plat_priv)
  375. return -ENODEV;
  376. switch (plat_priv->bus_type) {
  377. case CNSS_BUS_PCI:
  378. return cnss_pci_register_driver_hdlr(plat_priv->bus_priv, data);
  379. default:
  380. cnss_pr_err("Unsupported bus type: %d\n",
  381. plat_priv->bus_type);
  382. return -EINVAL;
  383. }
  384. }
  385. int cnss_bus_unregister_driver_hdlr(struct cnss_plat_data *plat_priv)
  386. {
  387. if (!plat_priv)
  388. return -ENODEV;
  389. switch (plat_priv->bus_type) {
  390. case CNSS_BUS_PCI:
  391. return cnss_pci_unregister_driver_hdlr(plat_priv->bus_priv);
  392. default:
  393. cnss_pr_err("Unsupported bus type: %d\n",
  394. plat_priv->bus_type);
  395. return -EINVAL;
  396. }
  397. }
  398. int cnss_bus_call_driver_modem_status(struct cnss_plat_data *plat_priv,
  399. int modem_current_status)
  400. {
  401. if (!plat_priv)
  402. return -ENODEV;
  403. switch (plat_priv->bus_type) {
  404. case CNSS_BUS_PCI:
  405. return cnss_pci_call_driver_modem_status(plat_priv->bus_priv,
  406. modem_current_status);
  407. default:
  408. cnss_pr_err("Unsupported bus type: %d\n",
  409. plat_priv->bus_type);
  410. return -EINVAL;
  411. }
  412. }
  413. int cnss_bus_update_status(struct cnss_plat_data *plat_priv,
  414. enum cnss_driver_status status)
  415. {
  416. if (!plat_priv)
  417. return -ENODEV;
  418. switch (plat_priv->bus_type) {
  419. case CNSS_BUS_PCI:
  420. return cnss_pci_update_status(plat_priv->bus_priv, status);
  421. default:
  422. cnss_pr_err("Unsupported bus type: %d\n",
  423. plat_priv->bus_type);
  424. return -EINVAL;
  425. }
  426. }
  427. int cnss_bus_update_uevent(struct cnss_plat_data *plat_priv,
  428. enum cnss_driver_status status, void *data)
  429. {
  430. if (!plat_priv)
  431. return -ENODEV;
  432. switch (plat_priv->bus_type) {
  433. case CNSS_BUS_PCI:
  434. return cnss_pci_call_driver_uevent(plat_priv->bus_priv,
  435. status, data);
  436. default:
  437. cnss_pr_err("Unsupported bus type: %d\n",
  438. plat_priv->bus_type);
  439. return -EINVAL;
  440. }
  441. }
  442. int cnss_bus_is_device_down(struct cnss_plat_data *plat_priv)
  443. {
  444. if (!plat_priv)
  445. return -ENODEV;
  446. switch (plat_priv->bus_type) {
  447. case CNSS_BUS_PCI:
  448. return cnss_pcie_is_device_down(plat_priv->bus_priv);
  449. default:
  450. cnss_pr_dbg("Unsupported bus type: %d\n",
  451. plat_priv->bus_type);
  452. return 0;
  453. }
  454. }
  455. int cnss_bus_check_link_status(struct cnss_plat_data *plat_priv)
  456. {
  457. if (!plat_priv)
  458. return -ENODEV;
  459. switch (plat_priv->bus_type) {
  460. case CNSS_BUS_PCI:
  461. return cnss_pci_check_link_status(plat_priv->bus_priv);
  462. default:
  463. cnss_pr_dbg("Unsupported bus type: %d\n",
  464. plat_priv->bus_type);
  465. return 0;
  466. }
  467. }
  468. int cnss_bus_recover_link_down(struct cnss_plat_data *plat_priv)
  469. {
  470. if (!plat_priv)
  471. return -ENODEV;
  472. switch (plat_priv->bus_type) {
  473. case CNSS_BUS_PCI:
  474. return cnss_pci_recover_link_down(plat_priv->bus_priv);
  475. default:
  476. cnss_pr_dbg("Unsupported bus type: %d\n",
  477. plat_priv->bus_type);
  478. return -EINVAL;
  479. }
  480. }
  481. int cnss_bus_debug_reg_read(struct cnss_plat_data *plat_priv, u32 offset,
  482. u32 *val, bool raw_access)
  483. {
  484. if (!plat_priv)
  485. return -ENODEV;
  486. switch (plat_priv->bus_type) {
  487. case CNSS_BUS_PCI:
  488. return cnss_pci_debug_reg_read(plat_priv->bus_priv, offset,
  489. val, raw_access);
  490. default:
  491. cnss_pr_dbg("Unsupported bus type: %d\n",
  492. plat_priv->bus_type);
  493. return 0;
  494. }
  495. }
  496. int cnss_bus_debug_reg_write(struct cnss_plat_data *plat_priv, u32 offset,
  497. u32 val, bool raw_access)
  498. {
  499. if (!plat_priv)
  500. return -ENODEV;
  501. switch (plat_priv->bus_type) {
  502. case CNSS_BUS_PCI:
  503. return cnss_pci_debug_reg_write(plat_priv->bus_priv, offset,
  504. val, raw_access);
  505. default:
  506. cnss_pr_dbg("Unsupported bus type: %d\n",
  507. plat_priv->bus_type);
  508. return 0;
  509. }
  510. }
  511. int cnss_bus_get_iova(struct cnss_plat_data *plat_priv, u64 *addr, u64 *size)
  512. {
  513. if (!plat_priv)
  514. return -ENODEV;
  515. switch (plat_priv->bus_type) {
  516. case CNSS_BUS_PCI:
  517. return cnss_pci_get_iova(plat_priv->bus_priv, addr, size);
  518. default:
  519. cnss_pr_err("Unsupported bus type: %d\n",
  520. plat_priv->bus_type);
  521. return -EINVAL;
  522. }
  523. }
  524. int cnss_bus_get_iova_ipa(struct cnss_plat_data *plat_priv, u64 *addr,
  525. u64 *size)
  526. {
  527. if (!plat_priv)
  528. return -ENODEV;
  529. switch (plat_priv->bus_type) {
  530. case CNSS_BUS_PCI:
  531. return cnss_pci_get_iova_ipa(plat_priv->bus_priv, addr, size);
  532. default:
  533. cnss_pr_err("Unsupported bus type: %d\n",
  534. plat_priv->bus_type);
  535. return -EINVAL;
  536. }
  537. }
  538. bool cnss_bus_is_smmu_s1_enabled(struct cnss_plat_data *plat_priv)
  539. {
  540. if (!plat_priv)
  541. return false;
  542. switch (plat_priv->bus_type) {
  543. case CNSS_BUS_PCI:
  544. return cnss_pci_is_smmu_s1_enabled(plat_priv->bus_priv);
  545. default:
  546. cnss_pr_err("Unsupported bus type: %d\n",
  547. plat_priv->bus_type);
  548. return false;
  549. }
  550. }
  551. int cnss_bus_update_time_sync_period(struct cnss_plat_data *plat_priv,
  552. unsigned int time_sync_period)
  553. {
  554. if (!plat_priv)
  555. return -ENODEV;
  556. switch (plat_priv->bus_type) {
  557. case CNSS_BUS_PCI:
  558. return cnss_pci_update_time_sync_period(plat_priv->bus_priv,
  559. time_sync_period);
  560. default:
  561. cnss_pr_err("Unsupported bus type: %d\n",
  562. plat_priv->bus_type);
  563. return -EINVAL;
  564. }
  565. }
  566. int cnss_bus_set_therm_cdev_state(struct cnss_plat_data *plat_priv,
  567. unsigned long thermal_state,
  568. int tcdev_id)
  569. {
  570. if (!plat_priv)
  571. return -ENODEV;
  572. switch (plat_priv->bus_type) {
  573. case CNSS_BUS_PCI:
  574. return cnss_pci_set_therm_cdev_state(plat_priv->bus_priv,
  575. thermal_state,
  576. tcdev_id);
  577. default:
  578. cnss_pr_err("Unsupported bus type: %d\n", plat_priv->bus_type);
  579. return -EINVAL;
  580. }
  581. }
  582. int cnss_bus_get_msi_assignment(struct cnss_plat_data *plat_priv,
  583. char *msi_name,
  584. int *num_vectors,
  585. u32 *user_base_data,
  586. u32 *base_vector)
  587. {
  588. if (!plat_priv)
  589. return -ENODEV;
  590. switch (plat_priv->bus_type) {
  591. case CNSS_BUS_PCI:
  592. return cnss_pci_get_user_msi_assignment(plat_priv->bus_priv,
  593. msi_name,
  594. num_vectors,
  595. user_base_data,
  596. base_vector);
  597. default:
  598. cnss_pr_err("Unsupported bus type: %d\n", plat_priv->bus_type);
  599. return -EINVAL;
  600. }
  601. }
  602. #if IS_ENABLED(CONFIG_MHI_BUS_MISC)
  603. void cnss_bus_disable_mhi_satellite_cfg(struct cnss_plat_data *plat_priv)
  604. {
  605. struct cnss_pci_data *pci_priv;
  606. pci_priv = plat_priv->bus_priv;
  607. if (!pci_priv) {
  608. cnss_pr_err("mhi satellite could not be disabled since pci_priv is NULL\n");
  609. return;
  610. }
  611. switch (plat_priv->bus_type) {
  612. case CNSS_BUS_PCI:
  613. /* MHI satellite configuration is only for KIWI V2 and
  614. * that too only in DRV mode.
  615. */
  616. if (plat_priv->device_id == KIWI_DEVICE_ID &&
  617. plat_priv->device_version.major_version == FW_V2_NUMBER) {
  618. cnss_pr_dbg("Remove MHI satellite configuration\n");
  619. return cnss_mhi_controller_set_base(pci_priv, 0);
  620. }
  621. break;
  622. default:
  623. cnss_pr_dbg("Unsupported bus type: %d, ignore disable mhi satellite cfg\n",
  624. plat_priv->bus_type);
  625. return;
  626. }
  627. return;
  628. }
  629. #else
  630. void cnss_bus_disable_mhi_satellite_cfg(struct cnss_plat_data *pci_priv)
  631. {
  632. }
  633. #endif