sde_kms.c 87 KB

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  1. /*
  2. * Copyright (c) 2014-2019, The Linux Foundation. All rights reserved.
  3. * Copyright (C) 2013 Red Hat
  4. * Author: Rob Clark <[email protected]>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  19. #include <drm/drm_crtc.h>
  20. #include <drm/drm_fixed.h>
  21. #include <linux/debugfs.h>
  22. #include <linux/of_address.h>
  23. #include <linux/of_irq.h>
  24. #include <linux/dma-buf.h>
  25. #include <linux/memblock.h>
  26. #include <linux/bootmem.h>
  27. #include "msm_drv.h"
  28. #include "msm_mmu.h"
  29. #include "msm_gem.h"
  30. #include "dsi_display.h"
  31. #include "dsi_drm.h"
  32. #include "sde_wb.h"
  33. #include "dp_display.h"
  34. #include "dp_drm.h"
  35. #include "sde_kms.h"
  36. #include "sde_core_irq.h"
  37. #include "sde_formats.h"
  38. #include "sde_hw_vbif.h"
  39. #include "sde_vbif.h"
  40. #include "sde_encoder.h"
  41. #include "sde_plane.h"
  42. #include "sde_crtc.h"
  43. #include "sde_reg_dma.h"
  44. #include <soc/qcom/scm.h>
  45. #include "soc/qcom/secure_buffer.h"
  46. #include "soc/qcom/qtee_shmbridge.h"
  47. #define CREATE_TRACE_POINTS
  48. #include "sde_trace.h"
  49. /* defines for secure channel call */
  50. #define MEM_PROTECT_SD_CTRL_SWITCH 0x18
  51. #define MDP_DEVICE_ID 0x1A
  52. static const char * const iommu_ports[] = {
  53. "mdp_0",
  54. };
  55. /**
  56. * Controls size of event log buffer. Specified as a power of 2.
  57. */
  58. #define SDE_EVTLOG_SIZE 1024
  59. /*
  60. * To enable overall DRM driver logging
  61. * # echo 0x2 > /sys/module/drm/parameters/debug
  62. *
  63. * To enable DRM driver h/w logging
  64. * # echo <mask> > /sys/kernel/debug/dri/0/debug/hw_log_mask
  65. *
  66. * See sde_hw_mdss.h for h/w logging mask definitions (search for SDE_DBG_MASK_)
  67. */
  68. #define SDE_DEBUGFS_DIR "msm_sde"
  69. #define SDE_DEBUGFS_HWMASKNAME "hw_log_mask"
  70. #define SDE_KMS_MODESET_LOCK_TIMEOUT_US 500
  71. #define SDE_KMS_MODESET_LOCK_MAX_TRIALS 20
  72. /**
  73. * sdecustom - enable certain driver customizations for sde clients
  74. * Enabling this modifies the standard DRM behavior slightly and assumes
  75. * that the clients have specific knowledge about the modifications that
  76. * are involved, so don't enable this unless you know what you're doing.
  77. *
  78. * Parts of the driver that are affected by this setting may be located by
  79. * searching for invocations of the 'sde_is_custom_client()' function.
  80. *
  81. * This is disabled by default.
  82. */
  83. static bool sdecustom = true;
  84. module_param(sdecustom, bool, 0400);
  85. MODULE_PARM_DESC(sdecustom, "Enable customizations for sde clients");
  86. static int sde_kms_hw_init(struct msm_kms *kms);
  87. static int _sde_kms_mmu_destroy(struct sde_kms *sde_kms);
  88. static int _sde_kms_mmu_init(struct sde_kms *sde_kms);
  89. static int _sde_kms_register_events(struct msm_kms *kms,
  90. struct drm_mode_object *obj, u32 event, bool en);
  91. bool sde_is_custom_client(void)
  92. {
  93. return sdecustom;
  94. }
  95. #ifdef CONFIG_DEBUG_FS
  96. void *sde_debugfs_get_root(struct sde_kms *sde_kms)
  97. {
  98. struct msm_drm_private *priv;
  99. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private)
  100. return NULL;
  101. priv = sde_kms->dev->dev_private;
  102. return priv->debug_root;
  103. }
  104. static int _sde_debugfs_init(struct sde_kms *sde_kms)
  105. {
  106. void *p;
  107. int rc;
  108. void *debugfs_root;
  109. p = sde_hw_util_get_log_mask_ptr();
  110. if (!sde_kms || !p)
  111. return -EINVAL;
  112. debugfs_root = sde_debugfs_get_root(sde_kms);
  113. if (!debugfs_root)
  114. return -EINVAL;
  115. /* allow debugfs_root to be NULL */
  116. debugfs_create_x32(SDE_DEBUGFS_HWMASKNAME, 0600, debugfs_root, p);
  117. (void) sde_debugfs_vbif_init(sde_kms, debugfs_root);
  118. (void) sde_debugfs_core_irq_init(sde_kms, debugfs_root);
  119. rc = sde_core_perf_debugfs_init(&sde_kms->perf, debugfs_root);
  120. if (rc) {
  121. SDE_ERROR("failed to init perf %d\n", rc);
  122. return rc;
  123. }
  124. if (sde_kms->catalog->qdss_count)
  125. debugfs_create_u32("qdss", 0600, debugfs_root,
  126. (u32 *)&sde_kms->qdss_enabled);
  127. return 0;
  128. }
  129. static void _sde_debugfs_destroy(struct sde_kms *sde_kms)
  130. {
  131. /* don't need to NULL check debugfs_root */
  132. if (sde_kms) {
  133. sde_debugfs_vbif_destroy(sde_kms);
  134. sde_debugfs_core_irq_destroy(sde_kms);
  135. }
  136. }
  137. #else
  138. static int _sde_debugfs_init(struct sde_kms *sde_kms)
  139. {
  140. return 0;
  141. }
  142. static void _sde_debugfs_destroy(struct sde_kms *sde_kms)
  143. {
  144. }
  145. #endif
  146. static int sde_kms_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
  147. {
  148. int ret = 0;
  149. SDE_ATRACE_BEGIN("sde_kms_enable_vblank");
  150. ret = sde_crtc_vblank(crtc, true);
  151. SDE_ATRACE_END("sde_kms_enable_vblank");
  152. return ret;
  153. }
  154. static void sde_kms_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
  155. {
  156. SDE_ATRACE_BEGIN("sde_kms_disable_vblank");
  157. sde_crtc_vblank(crtc, false);
  158. SDE_ATRACE_END("sde_kms_disable_vblank");
  159. }
  160. static void sde_kms_wait_for_frame_transfer_complete(struct msm_kms *kms,
  161. struct drm_crtc *crtc)
  162. {
  163. struct drm_encoder *encoder;
  164. struct drm_device *dev;
  165. int ret;
  166. if (!kms || !crtc || !crtc->state || !crtc->dev) {
  167. SDE_ERROR("invalid params\n");
  168. return;
  169. }
  170. if (!crtc->state->enable) {
  171. SDE_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
  172. return;
  173. }
  174. if (!crtc->state->active) {
  175. SDE_DEBUG("[crtc:%d] not active\n", crtc->base.id);
  176. return;
  177. }
  178. dev = crtc->dev;
  179. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  180. if (encoder->crtc != crtc)
  181. continue;
  182. /*
  183. * Video Mode - Wait for VSYNC
  184. * Cmd Mode - Wait for PP_DONE. Will be no-op if transfer is
  185. * complete
  186. */
  187. SDE_EVT32_VERBOSE(DRMID(crtc));
  188. ret = sde_encoder_wait_for_event(encoder, MSM_ENC_TX_COMPLETE);
  189. if (ret && ret != -EWOULDBLOCK) {
  190. SDE_ERROR(
  191. "[crtc: %d][enc: %d] wait for commit done returned %d\n",
  192. crtc->base.id, encoder->base.id, ret);
  193. break;
  194. }
  195. }
  196. }
  197. static int _sde_kms_secure_ctrl_xin_clients(struct sde_kms *sde_kms,
  198. struct drm_crtc *crtc, bool enable)
  199. {
  200. struct drm_device *dev;
  201. struct msm_drm_private *priv;
  202. struct sde_mdss_cfg *sde_cfg;
  203. struct drm_plane *plane;
  204. int i, ret;
  205. dev = sde_kms->dev;
  206. priv = dev->dev_private;
  207. sde_cfg = sde_kms->catalog;
  208. ret = sde_vbif_halt_xin_mask(sde_kms,
  209. sde_cfg->sui_block_xin_mask, enable);
  210. if (ret) {
  211. SDE_ERROR("failed to halt some xin-clients, ret:%d\n", ret);
  212. return ret;
  213. }
  214. if (enable) {
  215. for (i = 0; i < priv->num_planes; i++) {
  216. plane = priv->planes[i];
  217. sde_plane_secure_ctrl_xin_client(plane, crtc);
  218. }
  219. }
  220. return 0;
  221. }
  222. /**
  223. * _sde_kms_scm_call - makes secure channel call to switch the VMIDs
  224. * @sde_kms: Pointer to sde_kms struct
  225. * @vimd: switch the stage 2 translation to this VMID
  226. */
  227. static int _sde_kms_scm_call(struct sde_kms *sde_kms, int vmid)
  228. {
  229. struct scm_desc desc = {0};
  230. uint32_t num_sids;
  231. uint32_t *sec_sid;
  232. uint32_t mem_protect_sd_ctrl_id = MEM_PROTECT_SD_CTRL_SWITCH;
  233. struct sde_mdss_cfg *sde_cfg = sde_kms->catalog;
  234. int ret = 0, i;
  235. struct qtee_shm shm;
  236. bool qtee_en = qtee_shmbridge_is_enabled();
  237. num_sids = sde_cfg->sec_sid_mask_count;
  238. if (!num_sids) {
  239. SDE_ERROR("secure SID masks not configured, vmid 0x%x\n", vmid);
  240. return -EINVAL;
  241. }
  242. if (qtee_en) {
  243. ret = qtee_shmbridge_allocate_shm(num_sids * sizeof(uint32_t),
  244. &shm);
  245. if (ret)
  246. return -ENOMEM;
  247. sec_sid = (uint32_t *) shm.vaddr;
  248. desc.args[1] = shm.paddr;
  249. desc.args[2] = shm.size;
  250. } else {
  251. sec_sid = kcalloc(num_sids, sizeof(uint32_t), GFP_KERNEL);
  252. if (!sec_sid)
  253. return -ENOMEM;
  254. desc.args[1] = SCM_BUFFER_PHYS(sec_sid);
  255. desc.args[2] = sizeof(uint32_t) * num_sids;
  256. }
  257. desc.arginfo = SCM_ARGS(4, SCM_VAL, SCM_RW, SCM_VAL, SCM_VAL);
  258. desc.args[0] = MDP_DEVICE_ID;
  259. desc.args[3] = vmid;
  260. for (i = 0; i < num_sids; i++) {
  261. sec_sid[i] = sde_cfg->sec_sid_mask[i];
  262. SDE_DEBUG("sid_mask[%d]: %d\n", i, sec_sid[i]);
  263. }
  264. dmac_flush_range(sec_sid, sec_sid + num_sids);
  265. SDE_DEBUG("calling scm_call for vmid 0x%x, num_sids %d, qtee_en %d",
  266. vmid, num_sids, qtee_en);
  267. ret = scm_call2(SCM_SIP_FNID(SCM_SVC_MP,
  268. mem_protect_sd_ctrl_id), &desc);
  269. if (ret)
  270. SDE_ERROR("Error:scm_call2, vmid %lld, ret%d\n",
  271. desc.args[3], ret);
  272. SDE_EVT32(mem_protect_sd_ctrl_id, desc.args[0], desc.args[2],
  273. desc.args[3], qtee_en, num_sids, ret);
  274. if (qtee_en)
  275. qtee_shmbridge_free_shm(&shm);
  276. else
  277. kfree(sec_sid);
  278. return ret;
  279. }
  280. static int _sde_kms_detach_all_cb(struct sde_kms *sde_kms, u32 vmid)
  281. {
  282. u32 ret = 0;
  283. if (atomic_inc_return(&sde_kms->detach_all_cb) > 1)
  284. goto end;
  285. /* detach_all_contexts */
  286. ret = sde_kms_mmu_detach(sde_kms, false);
  287. if (ret) {
  288. SDE_ERROR("failed to detach all cb ret:%d\n", ret);
  289. goto end;
  290. }
  291. ret = _sde_kms_scm_call(sde_kms, vmid);
  292. if (ret)
  293. goto end;
  294. end:
  295. return ret;
  296. }
  297. static int _sde_kms_attach_all_cb(struct sde_kms *sde_kms, int vmid)
  298. {
  299. u32 ret = 0;
  300. if (atomic_dec_return(&sde_kms->detach_all_cb) != 0)
  301. goto end;
  302. ret = _sde_kms_scm_call(sde_kms, vmid);
  303. if (ret)
  304. goto end;
  305. /* attach_all_contexts */
  306. ret = sde_kms_mmu_attach(sde_kms, false);
  307. if (ret) {
  308. SDE_ERROR("failed to attach all cb ret:%d\n", ret);
  309. goto end;
  310. }
  311. end:
  312. return ret;
  313. }
  314. static int _sde_kms_detach_sec_cb(struct sde_kms *sde_kms, int vmid)
  315. {
  316. u32 ret = 0;
  317. if (atomic_inc_return(&sde_kms->detach_sec_cb) > 1)
  318. goto end;
  319. /* detach secure_context */
  320. ret = sde_kms_mmu_detach(sde_kms, true);
  321. if (ret) {
  322. SDE_ERROR("failed to detach sec cb ret:%d\n", ret);
  323. goto end;
  324. }
  325. ret = _sde_kms_scm_call(sde_kms, vmid);
  326. if (ret)
  327. goto end;
  328. end:
  329. return ret;
  330. }
  331. static int _sde_kms_attach_sec_cb(struct sde_kms *sde_kms, int vmid)
  332. {
  333. u32 ret = 0;
  334. if (atomic_dec_return(&sde_kms->detach_sec_cb) != 0)
  335. goto end;
  336. ret = _sde_kms_scm_call(sde_kms, vmid);
  337. if (ret)
  338. goto end;
  339. ret = sde_kms_mmu_attach(sde_kms, true);
  340. if (ret) {
  341. SDE_ERROR("failed to attach sec cb ret:%d\n", ret);
  342. goto end;
  343. }
  344. end:
  345. return ret;
  346. }
  347. static int _sde_kms_sui_misr_ctrl(struct sde_kms *sde_kms,
  348. struct drm_crtc *crtc, bool enable)
  349. {
  350. int ret;
  351. if (enable) {
  352. ret = pm_runtime_get_sync(sde_kms->dev->dev);
  353. if (ret < 0) {
  354. SDE_ERROR("failed to enable resource, ret:%d\n", ret);
  355. return ret;
  356. }
  357. sde_crtc_misr_setup(crtc, true, 1);
  358. ret = _sde_kms_secure_ctrl_xin_clients(sde_kms, crtc, true);
  359. if (ret) {
  360. pm_runtime_put_sync(sde_kms->dev->dev);
  361. return ret;
  362. }
  363. } else {
  364. _sde_kms_secure_ctrl_xin_clients(sde_kms, crtc, false);
  365. sde_crtc_misr_setup(crtc, false, 0);
  366. pm_runtime_put_sync(sde_kms->dev->dev);
  367. }
  368. return 0;
  369. }
  370. static int _sde_kms_secure_ctrl(struct sde_kms *sde_kms, struct drm_crtc *crtc,
  371. bool post_commit)
  372. {
  373. struct sde_kms_smmu_state_data *smmu_state = &sde_kms->smmu_state;
  374. int old_smmu_state = smmu_state->state;
  375. int ret = 0;
  376. u32 vmid;
  377. if (!sde_kms || !crtc) {
  378. SDE_ERROR("invalid argument(s)\n");
  379. return -EINVAL;
  380. }
  381. SDE_EVT32(DRMID(crtc), smmu_state->state, smmu_state->transition_type,
  382. post_commit, smmu_state->sui_misr_state,
  383. smmu_state->secure_level, SDE_EVTLOG_FUNC_ENTRY);
  384. if ((!smmu_state->transition_type) ||
  385. ((smmu_state->transition_type == POST_COMMIT) && !post_commit))
  386. /* Bail out */
  387. return 0;
  388. /* enable sui misr if requested, before the transition */
  389. if (smmu_state->sui_misr_state == SUI_MISR_ENABLE_REQ) {
  390. ret = _sde_kms_sui_misr_ctrl(sde_kms, crtc, true);
  391. if (ret)
  392. goto end;
  393. }
  394. mutex_lock(&sde_kms->secure_transition_lock);
  395. switch (smmu_state->state) {
  396. case DETACH_ALL_REQ:
  397. ret = _sde_kms_detach_all_cb(sde_kms, VMID_CP_SEC_DISPLAY);
  398. if (!ret)
  399. smmu_state->state = DETACHED;
  400. break;
  401. case ATTACH_ALL_REQ:
  402. ret = _sde_kms_attach_all_cb(sde_kms, VMID_CP_PIXEL);
  403. if (!ret) {
  404. smmu_state->state = ATTACHED;
  405. smmu_state->secure_level = SDE_DRM_SEC_NON_SEC;
  406. }
  407. break;
  408. case DETACH_SEC_REQ:
  409. vmid = (smmu_state->secure_level == SDE_DRM_SEC_ONLY) ?
  410. VMID_CP_SEC_DISPLAY : VMID_CP_CAMERA_PREVIEW;
  411. ret = _sde_kms_detach_sec_cb(sde_kms, vmid);
  412. if (!ret)
  413. smmu_state->state = DETACHED_SEC;
  414. break;
  415. case ATTACH_SEC_REQ:
  416. ret = _sde_kms_attach_sec_cb(sde_kms, VMID_CP_PIXEL);
  417. if (!ret) {
  418. smmu_state->state = ATTACHED;
  419. smmu_state->secure_level = SDE_DRM_SEC_NON_SEC;
  420. }
  421. break;
  422. default:
  423. SDE_ERROR("crtc%d: invalid smmu state %d transition type %d\n",
  424. DRMID(crtc), smmu_state->state,
  425. smmu_state->transition_type);
  426. ret = -EINVAL;
  427. break;
  428. }
  429. mutex_unlock(&sde_kms->secure_transition_lock);
  430. /* disable sui misr if requested, after the transition */
  431. if (!ret && (smmu_state->sui_misr_state == SUI_MISR_DISABLE_REQ)) {
  432. ret = _sde_kms_sui_misr_ctrl(sde_kms, crtc, false);
  433. if (ret)
  434. goto end;
  435. }
  436. end:
  437. smmu_state->sui_misr_state = NONE;
  438. smmu_state->transition_type = NONE;
  439. smmu_state->transition_error = false;
  440. /*
  441. * If switch failed, toggling secure_level is enough since
  442. * there are only two secure levels - secure/non-secure
  443. */
  444. if (ret) {
  445. smmu_state->transition_error = true;
  446. smmu_state->state = smmu_state->prev_state;
  447. smmu_state->secure_level = !smmu_state->secure_level;
  448. }
  449. SDE_DEBUG(
  450. "crtc %d: old_state %d, req_state %d, new_state %d, sec_lvl %d, ret %d\n",
  451. DRMID(crtc), smmu_state->prev_state, old_smmu_state,
  452. smmu_state->state, smmu_state->secure_level, ret);
  453. SDE_EVT32(DRMID(crtc), smmu_state->prev_state,
  454. smmu_state->state, smmu_state->transition_type,
  455. smmu_state->transition_error, smmu_state->secure_level,
  456. smmu_state->sui_misr_state, ret, SDE_EVTLOG_FUNC_EXIT);
  457. return ret;
  458. }
  459. static int sde_kms_prepare_secure_transition(struct msm_kms *kms,
  460. struct drm_atomic_state *state)
  461. {
  462. struct drm_crtc *crtc;
  463. struct drm_crtc_state *old_crtc_state;
  464. struct drm_plane *plane;
  465. struct drm_plane_state *plane_state;
  466. struct sde_kms *sde_kms = to_sde_kms(kms);
  467. struct drm_device *dev = sde_kms->dev;
  468. int i, ops = 0, ret = 0;
  469. bool old_valid_fb = false;
  470. for_each_old_crtc_in_state(state, crtc, old_crtc_state, i) {
  471. if (!crtc->state || !crtc->state->active)
  472. continue;
  473. /*
  474. * It is safe to assume only one active crtc,
  475. * and compatible translation modes on the
  476. * planes staged on this crtc.
  477. * otherwise validation would have failed.
  478. * For this CRTC,
  479. */
  480. /*
  481. * 1. Check if old state on the CRTC has planes
  482. * staged with valid fbs
  483. */
  484. for_each_old_plane_in_state(state, plane, plane_state, i) {
  485. if (!plane_state->crtc)
  486. continue;
  487. if (plane_state->fb) {
  488. old_valid_fb = true;
  489. break;
  490. }
  491. }
  492. /*
  493. * 2.Get the operations needed to be performed before
  494. * secure transition can be initiated.
  495. */
  496. ops = sde_crtc_get_secure_transition_ops(crtc,
  497. old_crtc_state, old_valid_fb);
  498. if (ops < 0) {
  499. SDE_ERROR("invalid secure operations %x\n", ops);
  500. return ops;
  501. }
  502. if (!ops)
  503. goto no_ops;
  504. SDE_DEBUG("%d:secure operations(%x) started on state:%pK\n",
  505. crtc->base.id, ops, crtc->state);
  506. SDE_EVT32(DRMID(crtc), ops, crtc->state, old_valid_fb);
  507. /* 3. Perform operations needed for secure transition */
  508. if (ops & SDE_KMS_OPS_WAIT_FOR_TX_DONE) {
  509. SDE_DEBUG("wait_for_transfer_done\n");
  510. sde_kms_wait_for_frame_transfer_complete(kms, crtc);
  511. }
  512. if (ops & SDE_KMS_OPS_CLEANUP_PLANE_FB) {
  513. SDE_DEBUG("cleanup planes\n");
  514. drm_atomic_helper_cleanup_planes(dev, state);
  515. }
  516. if (ops & SDE_KMS_OPS_SECURE_STATE_CHANGE) {
  517. SDE_DEBUG("secure ctrl\n");
  518. _sde_kms_secure_ctrl(sde_kms, crtc, false);
  519. }
  520. if (ops & SDE_KMS_OPS_PREPARE_PLANE_FB) {
  521. SDE_DEBUG("prepare planes %d",
  522. crtc->state->plane_mask);
  523. drm_atomic_crtc_for_each_plane(plane,
  524. crtc) {
  525. const struct drm_plane_helper_funcs *funcs;
  526. plane_state = plane->state;
  527. funcs = plane->helper_private;
  528. SDE_DEBUG("psde:%d FB[%u]\n",
  529. plane->base.id,
  530. plane->fb->base.id);
  531. if (!funcs)
  532. continue;
  533. if (funcs->prepare_fb(plane, plane_state)) {
  534. ret = funcs->prepare_fb(plane,
  535. plane_state);
  536. if (ret)
  537. return ret;
  538. }
  539. }
  540. }
  541. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_EXIT);
  542. SDE_DEBUG("secure operations completed\n");
  543. }
  544. no_ops:
  545. return 0;
  546. }
  547. static int _sde_kms_release_splash_buffer(unsigned int mem_addr,
  548. unsigned int splash_buffer_size,
  549. unsigned int ramdump_base,
  550. unsigned int ramdump_buffer_size)
  551. {
  552. unsigned long pfn_start, pfn_end, pfn_idx;
  553. int ret = 0;
  554. if (!mem_addr || !splash_buffer_size) {
  555. SDE_ERROR("invalid params\n");
  556. return -EINVAL;
  557. }
  558. /* leave ramdump memory only if base address matches */
  559. if (ramdump_base == mem_addr &&
  560. ramdump_buffer_size <= splash_buffer_size) {
  561. mem_addr += ramdump_buffer_size;
  562. splash_buffer_size -= ramdump_buffer_size;
  563. }
  564. pfn_start = mem_addr >> PAGE_SHIFT;
  565. pfn_end = (mem_addr + splash_buffer_size) >> PAGE_SHIFT;
  566. ret = memblock_free(mem_addr, splash_buffer_size);
  567. if (ret) {
  568. SDE_ERROR("continuous splash memory free failed:%d\n", ret);
  569. return ret;
  570. }
  571. for (pfn_idx = pfn_start; pfn_idx < pfn_end; pfn_idx++)
  572. free_reserved_page(pfn_to_page(pfn_idx));
  573. return ret;
  574. }
  575. static int _sde_kms_splash_mem_get(struct sde_kms *sde_kms,
  576. struct sde_splash_mem *splash)
  577. {
  578. struct msm_mmu *mmu = NULL;
  579. int ret = 0;
  580. if (!sde_kms->aspace[0]) {
  581. SDE_ERROR("aspace not found for sde kms node\n");
  582. return -EINVAL;
  583. }
  584. mmu = sde_kms->aspace[0]->mmu;
  585. if (!mmu) {
  586. SDE_ERROR("mmu not found for aspace\n");
  587. return -EINVAL;
  588. }
  589. if (!splash || !mmu->funcs || !mmu->funcs->one_to_one_map) {
  590. SDE_ERROR("invalid input params for map\n");
  591. return -EINVAL;
  592. }
  593. if (!splash->ref_cnt) {
  594. ret = mmu->funcs->one_to_one_map(mmu, splash->splash_buf_base,
  595. splash->splash_buf_base,
  596. splash->splash_buf_size,
  597. IOMMU_READ | IOMMU_NOEXEC);
  598. if (ret)
  599. SDE_ERROR("splash memory smmu map failed:%d\n", ret);
  600. }
  601. splash->ref_cnt++;
  602. SDE_DEBUG("one2one mapping done for base:%lx size:%x ref_cnt:%d\n",
  603. splash->splash_buf_base,
  604. splash->splash_buf_size,
  605. splash->ref_cnt);
  606. return ret;
  607. }
  608. static int _sde_kms_map_all_splash_regions(struct sde_kms *sde_kms)
  609. {
  610. int i = 0;
  611. int ret = 0;
  612. if (!sde_kms)
  613. return -EINVAL;
  614. for (i = 0; i < sde_kms->splash_data.num_splash_displays; i++) {
  615. ret = _sde_kms_splash_mem_get(sde_kms,
  616. sde_kms->splash_data.splash_display[i].splash);
  617. if (ret)
  618. return ret;
  619. }
  620. return ret;
  621. }
  622. static int _sde_kms_splash_mem_put(struct sde_kms *sde_kms,
  623. struct sde_splash_mem *splash)
  624. {
  625. struct msm_mmu *mmu = NULL;
  626. int rc = 0;
  627. if (!sde_kms || !sde_kms->aspace[0] || !sde_kms->aspace[0]->mmu) {
  628. SDE_ERROR("invalid params\n");
  629. return -EINVAL;
  630. }
  631. mmu = sde_kms->aspace[0]->mmu;
  632. if (!splash || !splash->ref_cnt ||
  633. !mmu || !mmu->funcs || !mmu->funcs->one_to_one_unmap)
  634. return -EINVAL;
  635. splash->ref_cnt--;
  636. SDE_DEBUG("splash base:%lx refcnt:%d\n",
  637. splash->splash_buf_base, splash->ref_cnt);
  638. if (!splash->ref_cnt) {
  639. mmu->funcs->one_to_one_unmap(mmu, splash->splash_buf_base,
  640. splash->splash_buf_size);
  641. rc = _sde_kms_release_splash_buffer(splash->splash_buf_base,
  642. splash->splash_buf_size, splash->ramdump_base,
  643. splash->ramdump_size);
  644. splash->splash_buf_base = 0;
  645. splash->splash_buf_size = 0;
  646. }
  647. return rc;
  648. }
  649. static int _sde_kms_unmap_all_splash_regions(struct sde_kms *sde_kms)
  650. {
  651. int i = 0;
  652. int ret = 0;
  653. if (!sde_kms)
  654. return -EINVAL;
  655. for (i = 0; i < sde_kms->splash_data.num_splash_displays; i++) {
  656. ret = _sde_kms_splash_mem_put(sde_kms,
  657. sde_kms->splash_data.splash_display[i].splash);
  658. if (ret)
  659. return ret;
  660. }
  661. return ret;
  662. }
  663. static void sde_kms_prepare_commit(struct msm_kms *kms,
  664. struct drm_atomic_state *state)
  665. {
  666. struct sde_kms *sde_kms;
  667. struct msm_drm_private *priv;
  668. struct drm_device *dev;
  669. struct drm_encoder *encoder;
  670. struct drm_crtc *crtc;
  671. struct drm_crtc_state *crtc_state;
  672. int i, rc;
  673. if (!kms)
  674. return;
  675. sde_kms = to_sde_kms(kms);
  676. dev = sde_kms->dev;
  677. if (!dev || !dev->dev_private)
  678. return;
  679. priv = dev->dev_private;
  680. SDE_ATRACE_BEGIN("prepare_commit");
  681. rc = pm_runtime_get_sync(sde_kms->dev->dev);
  682. if (rc < 0) {
  683. SDE_ERROR("failed to enable power resources %d\n", rc);
  684. SDE_EVT32(rc, SDE_EVTLOG_ERROR);
  685. goto end;
  686. }
  687. if (sde_kms->first_kickoff) {
  688. sde_power_scale_reg_bus(&priv->phandle, VOTE_INDEX_HIGH, false);
  689. sde_kms->first_kickoff = false;
  690. }
  691. for_each_old_crtc_in_state(state, crtc, crtc_state, i) {
  692. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  693. head) {
  694. if (encoder->crtc != crtc)
  695. continue;
  696. sde_encoder_prepare_commit(encoder);
  697. }
  698. }
  699. /*
  700. * NOTE: for secure use cases we want to apply the new HW
  701. * configuration only after completing preparation for secure
  702. * transitions prepare below if any transtions is required.
  703. */
  704. sde_kms_prepare_secure_transition(kms, state);
  705. end:
  706. SDE_ATRACE_END("prepare_commit");
  707. }
  708. static void sde_kms_commit(struct msm_kms *kms,
  709. struct drm_atomic_state *old_state)
  710. {
  711. struct sde_kms *sde_kms;
  712. struct drm_crtc *crtc;
  713. struct drm_crtc_state *old_crtc_state;
  714. int i;
  715. if (!kms || !old_state)
  716. return;
  717. sde_kms = to_sde_kms(kms);
  718. if (!sde_kms_power_resource_is_enabled(sde_kms->dev)) {
  719. SDE_ERROR("power resource is not enabled\n");
  720. return;
  721. }
  722. SDE_ATRACE_BEGIN("sde_kms_commit");
  723. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  724. if (crtc->state->active) {
  725. SDE_EVT32(DRMID(crtc));
  726. sde_crtc_commit_kickoff(crtc, old_crtc_state);
  727. }
  728. }
  729. SDE_ATRACE_END("sde_kms_commit");
  730. }
  731. static void _sde_kms_free_splash_region(struct sde_kms *sde_kms,
  732. struct sde_splash_display *splash_display)
  733. {
  734. if (!sde_kms || !splash_display ||
  735. !sde_kms->splash_data.num_splash_displays)
  736. return;
  737. _sde_kms_splash_mem_put(sde_kms, splash_display->splash);
  738. sde_kms->splash_data.num_splash_displays--;
  739. SDE_DEBUG("cont_splash handoff done, remaining:%d\n",
  740. sde_kms->splash_data.num_splash_displays);
  741. memset(splash_display, 0x0, sizeof(struct sde_splash_display));
  742. }
  743. static void _sde_kms_release_splash_resource(struct sde_kms *sde_kms,
  744. struct drm_crtc *crtc)
  745. {
  746. struct msm_drm_private *priv;
  747. struct sde_splash_display *splash_display;
  748. int i;
  749. if (!sde_kms || !crtc)
  750. return;
  751. priv = sde_kms->dev->dev_private;
  752. if (!crtc->state->active || !sde_kms->splash_data.num_splash_displays)
  753. return;
  754. SDE_EVT32(DRMID(crtc), crtc->state->active,
  755. sde_kms->splash_data.num_splash_displays);
  756. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  757. splash_display = &sde_kms->splash_data.splash_display[i];
  758. if (splash_display->encoder &&
  759. crtc == splash_display->encoder->crtc)
  760. break;
  761. }
  762. if (i >= MAX_DSI_DISPLAYS)
  763. return;
  764. if (splash_display->cont_splash_enabled) {
  765. sde_encoder_update_caps_for_cont_splash(splash_display->encoder,
  766. splash_display, false);
  767. _sde_kms_free_splash_region(sde_kms, splash_display);
  768. }
  769. /* remove the votes if all displays are done with splash */
  770. if (!sde_kms->splash_data.num_splash_displays) {
  771. for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++)
  772. sde_power_data_bus_set_quota(&priv->phandle, i,
  773. SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA,
  774. SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA);
  775. pm_runtime_put_sync(sde_kms->dev->dev);
  776. }
  777. }
  778. static void sde_kms_complete_commit(struct msm_kms *kms,
  779. struct drm_atomic_state *old_state)
  780. {
  781. struct sde_kms *sde_kms;
  782. struct msm_drm_private *priv;
  783. struct drm_crtc *crtc;
  784. struct drm_crtc_state *old_crtc_state;
  785. struct drm_connector *connector;
  786. struct drm_connector_state *old_conn_state;
  787. int i, rc = 0;
  788. if (!kms || !old_state)
  789. return;
  790. sde_kms = to_sde_kms(kms);
  791. if (!sde_kms->dev || !sde_kms->dev->dev_private)
  792. return;
  793. priv = sde_kms->dev->dev_private;
  794. if (sde_kms_power_resource_is_enabled(sde_kms->dev) < 0) {
  795. SDE_ERROR("power resource is not enabled\n");
  796. return;
  797. }
  798. SDE_ATRACE_BEGIN("sde_kms_complete_commit");
  799. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  800. sde_crtc_complete_commit(crtc, old_crtc_state);
  801. /* complete secure transitions if any */
  802. if (sde_kms->smmu_state.transition_type == POST_COMMIT)
  803. _sde_kms_secure_ctrl(sde_kms, crtc, true);
  804. }
  805. for_each_old_connector_in_state(old_state, connector,
  806. old_conn_state, i) {
  807. struct sde_connector *c_conn;
  808. c_conn = to_sde_connector(connector);
  809. if (!c_conn->ops.post_kickoff)
  810. continue;
  811. rc = c_conn->ops.post_kickoff(connector);
  812. if (rc) {
  813. pr_err("Connector Post kickoff failed rc=%d\n",
  814. rc);
  815. }
  816. }
  817. pm_runtime_put_sync(sde_kms->dev->dev);
  818. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i)
  819. _sde_kms_release_splash_resource(sde_kms, crtc);
  820. SDE_EVT32_VERBOSE(SDE_EVTLOG_FUNC_EXIT);
  821. SDE_ATRACE_END("sde_kms_complete_commit");
  822. }
  823. static void sde_kms_wait_for_commit_done(struct msm_kms *kms,
  824. struct drm_crtc *crtc)
  825. {
  826. struct drm_encoder *encoder;
  827. struct drm_device *dev;
  828. int ret;
  829. if (!kms || !crtc || !crtc->state) {
  830. SDE_ERROR("invalid params\n");
  831. return;
  832. }
  833. dev = crtc->dev;
  834. if (!crtc->state->enable) {
  835. SDE_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
  836. return;
  837. }
  838. if (!crtc->state->active) {
  839. SDE_DEBUG("[crtc:%d] not active\n", crtc->base.id);
  840. return;
  841. }
  842. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  843. SDE_ERROR("power resource is not enabled\n");
  844. return;
  845. }
  846. SDE_ATRACE_BEGIN("sde_kms_wait_for_commit_done");
  847. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  848. if (encoder->crtc != crtc)
  849. continue;
  850. /*
  851. * Wait for post-flush if necessary to delay before
  852. * plane_cleanup. For example, wait for vsync in case of video
  853. * mode panels. This may be a no-op for command mode panels.
  854. */
  855. SDE_EVT32_VERBOSE(DRMID(crtc));
  856. ret = sde_encoder_wait_for_event(encoder, MSM_ENC_COMMIT_DONE);
  857. if (ret && ret != -EWOULDBLOCK) {
  858. SDE_ERROR("wait for commit done returned %d\n", ret);
  859. sde_crtc_request_frame_reset(crtc);
  860. break;
  861. }
  862. sde_crtc_complete_flip(crtc, NULL);
  863. }
  864. SDE_ATRACE_END("sde_ksm_wait_for_commit_done");
  865. }
  866. static void sde_kms_prepare_fence(struct msm_kms *kms,
  867. struct drm_atomic_state *old_state)
  868. {
  869. struct drm_crtc *crtc;
  870. struct drm_crtc_state *old_crtc_state;
  871. int i, rc;
  872. if (!kms || !old_state || !old_state->dev || !old_state->acquire_ctx) {
  873. SDE_ERROR("invalid argument(s)\n");
  874. return;
  875. }
  876. SDE_ATRACE_BEGIN("sde_kms_prepare_fence");
  877. retry:
  878. /* attempt to acquire ww mutex for connection */
  879. rc = drm_modeset_lock(&old_state->dev->mode_config.connection_mutex,
  880. old_state->acquire_ctx);
  881. if (rc == -EDEADLK) {
  882. drm_modeset_backoff(old_state->acquire_ctx);
  883. goto retry;
  884. }
  885. /* old_state actually contains updated crtc pointers */
  886. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  887. if (crtc->state->active || crtc->state->active_changed)
  888. sde_crtc_prepare_commit(crtc, old_crtc_state);
  889. }
  890. SDE_ATRACE_END("sde_kms_prepare_fence");
  891. }
  892. /**
  893. * _sde_kms_get_displays - query for underlying display handles and cache them
  894. * @sde_kms: Pointer to sde kms structure
  895. * Returns: Zero on success
  896. */
  897. static int _sde_kms_get_displays(struct sde_kms *sde_kms)
  898. {
  899. int rc = -ENOMEM;
  900. if (!sde_kms) {
  901. SDE_ERROR("invalid sde kms\n");
  902. return -EINVAL;
  903. }
  904. /* dsi */
  905. sde_kms->dsi_displays = NULL;
  906. sde_kms->dsi_display_count = dsi_display_get_num_of_displays();
  907. if (sde_kms->dsi_display_count) {
  908. sde_kms->dsi_displays = kcalloc(sde_kms->dsi_display_count,
  909. sizeof(void *),
  910. GFP_KERNEL);
  911. if (!sde_kms->dsi_displays) {
  912. SDE_ERROR("failed to allocate dsi displays\n");
  913. goto exit_deinit_dsi;
  914. }
  915. sde_kms->dsi_display_count =
  916. dsi_display_get_active_displays(sde_kms->dsi_displays,
  917. sde_kms->dsi_display_count);
  918. }
  919. /* wb */
  920. sde_kms->wb_displays = NULL;
  921. sde_kms->wb_display_count = sde_wb_get_num_of_displays();
  922. if (sde_kms->wb_display_count) {
  923. sde_kms->wb_displays = kcalloc(sde_kms->wb_display_count,
  924. sizeof(void *),
  925. GFP_KERNEL);
  926. if (!sde_kms->wb_displays) {
  927. SDE_ERROR("failed to allocate wb displays\n");
  928. goto exit_deinit_wb;
  929. }
  930. sde_kms->wb_display_count =
  931. wb_display_get_displays(sde_kms->wb_displays,
  932. sde_kms->wb_display_count);
  933. }
  934. /* dp */
  935. sde_kms->dp_displays = NULL;
  936. sde_kms->dp_display_count = dp_display_get_num_of_displays();
  937. if (sde_kms->dp_display_count) {
  938. sde_kms->dp_displays = kcalloc(sde_kms->dp_display_count,
  939. sizeof(void *), GFP_KERNEL);
  940. if (!sde_kms->dp_displays) {
  941. SDE_ERROR("failed to allocate dp displays\n");
  942. goto exit_deinit_dp;
  943. }
  944. sde_kms->dp_display_count =
  945. dp_display_get_displays(sde_kms->dp_displays,
  946. sde_kms->dp_display_count);
  947. sde_kms->dp_stream_count = dp_display_get_num_of_streams();
  948. }
  949. return 0;
  950. exit_deinit_dp:
  951. kfree(sde_kms->dp_displays);
  952. sde_kms->dp_stream_count = 0;
  953. sde_kms->dp_display_count = 0;
  954. sde_kms->dp_displays = NULL;
  955. exit_deinit_wb:
  956. kfree(sde_kms->wb_displays);
  957. sde_kms->wb_display_count = 0;
  958. sde_kms->wb_displays = NULL;
  959. exit_deinit_dsi:
  960. kfree(sde_kms->dsi_displays);
  961. sde_kms->dsi_display_count = 0;
  962. sde_kms->dsi_displays = NULL;
  963. return rc;
  964. }
  965. /**
  966. * _sde_kms_release_displays - release cache of underlying display handles
  967. * @sde_kms: Pointer to sde kms structure
  968. */
  969. static void _sde_kms_release_displays(struct sde_kms *sde_kms)
  970. {
  971. if (!sde_kms) {
  972. SDE_ERROR("invalid sde kms\n");
  973. return;
  974. }
  975. kfree(sde_kms->wb_displays);
  976. sde_kms->wb_displays = NULL;
  977. sde_kms->wb_display_count = 0;
  978. kfree(sde_kms->dsi_displays);
  979. sde_kms->dsi_displays = NULL;
  980. sde_kms->dsi_display_count = 0;
  981. }
  982. /**
  983. * _sde_kms_setup_displays - create encoders, bridges and connectors
  984. * for underlying displays
  985. * @dev: Pointer to drm device structure
  986. * @priv: Pointer to private drm device data
  987. * @sde_kms: Pointer to sde kms structure
  988. * Returns: Zero on success
  989. */
  990. static int _sde_kms_setup_displays(struct drm_device *dev,
  991. struct msm_drm_private *priv,
  992. struct sde_kms *sde_kms)
  993. {
  994. static const struct sde_connector_ops dsi_ops = {
  995. .set_info_blob = dsi_conn_set_info_blob,
  996. .detect = dsi_conn_detect,
  997. .get_modes = dsi_connector_get_modes,
  998. .pre_destroy = dsi_connector_put_modes,
  999. .mode_valid = dsi_conn_mode_valid,
  1000. .get_info = dsi_display_get_info,
  1001. .set_backlight = dsi_display_set_backlight,
  1002. .soft_reset = dsi_display_soft_reset,
  1003. .pre_kickoff = dsi_conn_pre_kickoff,
  1004. .clk_ctrl = dsi_display_clk_ctrl,
  1005. .set_power = dsi_display_set_power,
  1006. .get_mode_info = dsi_conn_get_mode_info,
  1007. .get_dst_format = dsi_display_get_dst_format,
  1008. .post_kickoff = dsi_conn_post_kickoff,
  1009. .check_status = dsi_display_check_status,
  1010. .enable_event = dsi_conn_enable_event,
  1011. .cmd_transfer = dsi_display_cmd_transfer,
  1012. .cont_splash_config = dsi_display_cont_splash_config,
  1013. .get_panel_vfp = dsi_display_get_panel_vfp,
  1014. .get_default_lms = dsi_display_get_default_lms,
  1015. };
  1016. static const struct sde_connector_ops wb_ops = {
  1017. .post_init = sde_wb_connector_post_init,
  1018. .set_info_blob = sde_wb_connector_set_info_blob,
  1019. .detect = sde_wb_connector_detect,
  1020. .get_modes = sde_wb_connector_get_modes,
  1021. .set_property = sde_wb_connector_set_property,
  1022. .get_info = sde_wb_get_info,
  1023. .soft_reset = NULL,
  1024. .get_mode_info = sde_wb_get_mode_info,
  1025. .get_dst_format = NULL,
  1026. .check_status = NULL,
  1027. .cmd_transfer = NULL,
  1028. .cont_splash_config = NULL,
  1029. .get_panel_vfp = NULL,
  1030. };
  1031. static const struct sde_connector_ops dp_ops = {
  1032. .post_init = dp_connector_post_init,
  1033. .detect = dp_connector_detect,
  1034. .get_modes = dp_connector_get_modes,
  1035. .atomic_check = dp_connector_atomic_check,
  1036. .mode_valid = dp_connector_mode_valid,
  1037. .get_info = dp_connector_get_info,
  1038. .get_mode_info = dp_connector_get_mode_info,
  1039. .post_open = dp_connector_post_open,
  1040. .check_status = NULL,
  1041. .set_colorspace = dp_connector_set_colorspace,
  1042. .config_hdr = dp_connector_config_hdr,
  1043. .cmd_transfer = NULL,
  1044. .cont_splash_config = NULL,
  1045. .get_panel_vfp = NULL,
  1046. .update_pps = dp_connector_update_pps,
  1047. };
  1048. struct msm_display_info info;
  1049. struct drm_encoder *encoder;
  1050. void *display, *connector;
  1051. int i, max_encoders;
  1052. int rc = 0;
  1053. if (!dev || !priv || !sde_kms) {
  1054. SDE_ERROR("invalid argument(s)\n");
  1055. return -EINVAL;
  1056. }
  1057. max_encoders = sde_kms->dsi_display_count + sde_kms->wb_display_count +
  1058. sde_kms->dp_display_count +
  1059. sde_kms->dp_stream_count;
  1060. if (max_encoders > ARRAY_SIZE(priv->encoders)) {
  1061. max_encoders = ARRAY_SIZE(priv->encoders);
  1062. SDE_ERROR("capping number of displays to %d", max_encoders);
  1063. }
  1064. /* dsi */
  1065. for (i = 0; i < sde_kms->dsi_display_count &&
  1066. priv->num_encoders < max_encoders; ++i) {
  1067. display = sde_kms->dsi_displays[i];
  1068. encoder = NULL;
  1069. memset(&info, 0x0, sizeof(info));
  1070. rc = dsi_display_get_info(NULL, &info, display);
  1071. if (rc) {
  1072. SDE_ERROR("dsi get_info %d failed\n", i);
  1073. continue;
  1074. }
  1075. encoder = sde_encoder_init(dev, &info);
  1076. if (IS_ERR_OR_NULL(encoder)) {
  1077. SDE_ERROR("encoder init failed for dsi %d\n", i);
  1078. continue;
  1079. }
  1080. rc = dsi_display_drm_bridge_init(display, encoder);
  1081. if (rc) {
  1082. SDE_ERROR("dsi bridge %d init failed, %d\n", i, rc);
  1083. sde_encoder_destroy(encoder);
  1084. continue;
  1085. }
  1086. connector = sde_connector_init(dev,
  1087. encoder,
  1088. dsi_display_get_drm_panel(display),
  1089. display,
  1090. &dsi_ops,
  1091. DRM_CONNECTOR_POLL_HPD,
  1092. DRM_MODE_CONNECTOR_DSI);
  1093. if (connector) {
  1094. priv->encoders[priv->num_encoders++] = encoder;
  1095. priv->connectors[priv->num_connectors++] = connector;
  1096. } else {
  1097. SDE_ERROR("dsi %d connector init failed\n", i);
  1098. dsi_display_drm_bridge_deinit(display);
  1099. sde_encoder_destroy(encoder);
  1100. continue;
  1101. }
  1102. rc = dsi_display_drm_ext_bridge_init(display,
  1103. encoder, connector);
  1104. if (rc) {
  1105. SDE_ERROR("dsi %d ext bridge init failed\n", rc);
  1106. dsi_display_drm_bridge_deinit(display);
  1107. sde_connector_destroy(connector);
  1108. sde_encoder_destroy(encoder);
  1109. }
  1110. }
  1111. /* wb */
  1112. for (i = 0; i < sde_kms->wb_display_count &&
  1113. priv->num_encoders < max_encoders; ++i) {
  1114. display = sde_kms->wb_displays[i];
  1115. encoder = NULL;
  1116. memset(&info, 0x0, sizeof(info));
  1117. rc = sde_wb_get_info(NULL, &info, display);
  1118. if (rc) {
  1119. SDE_ERROR("wb get_info %d failed\n", i);
  1120. continue;
  1121. }
  1122. encoder = sde_encoder_init(dev, &info);
  1123. if (IS_ERR_OR_NULL(encoder)) {
  1124. SDE_ERROR("encoder init failed for wb %d\n", i);
  1125. continue;
  1126. }
  1127. rc = sde_wb_drm_init(display, encoder);
  1128. if (rc) {
  1129. SDE_ERROR("wb bridge %d init failed, %d\n", i, rc);
  1130. sde_encoder_destroy(encoder);
  1131. continue;
  1132. }
  1133. connector = sde_connector_init(dev,
  1134. encoder,
  1135. 0,
  1136. display,
  1137. &wb_ops,
  1138. DRM_CONNECTOR_POLL_HPD,
  1139. DRM_MODE_CONNECTOR_VIRTUAL);
  1140. if (connector) {
  1141. priv->encoders[priv->num_encoders++] = encoder;
  1142. priv->connectors[priv->num_connectors++] = connector;
  1143. } else {
  1144. SDE_ERROR("wb %d connector init failed\n", i);
  1145. sde_wb_drm_deinit(display);
  1146. sde_encoder_destroy(encoder);
  1147. }
  1148. }
  1149. /* dp */
  1150. for (i = 0; i < sde_kms->dp_display_count &&
  1151. priv->num_encoders < max_encoders; ++i) {
  1152. int idx;
  1153. display = sde_kms->dp_displays[i];
  1154. encoder = NULL;
  1155. memset(&info, 0x0, sizeof(info));
  1156. rc = dp_connector_get_info(NULL, &info, display);
  1157. if (rc) {
  1158. SDE_ERROR("dp get_info %d failed\n", i);
  1159. continue;
  1160. }
  1161. encoder = sde_encoder_init(dev, &info);
  1162. if (IS_ERR_OR_NULL(encoder)) {
  1163. SDE_ERROR("dp encoder init failed %d\n", i);
  1164. continue;
  1165. }
  1166. rc = dp_drm_bridge_init(display, encoder);
  1167. if (rc) {
  1168. SDE_ERROR("dp bridge %d init failed, %d\n", i, rc);
  1169. sde_encoder_destroy(encoder);
  1170. continue;
  1171. }
  1172. connector = sde_connector_init(dev,
  1173. encoder,
  1174. NULL,
  1175. display,
  1176. &dp_ops,
  1177. DRM_CONNECTOR_POLL_HPD,
  1178. DRM_MODE_CONNECTOR_DisplayPort);
  1179. if (connector) {
  1180. priv->encoders[priv->num_encoders++] = encoder;
  1181. priv->connectors[priv->num_connectors++] = connector;
  1182. } else {
  1183. SDE_ERROR("dp %d connector init failed\n", i);
  1184. dp_drm_bridge_deinit(display);
  1185. sde_encoder_destroy(encoder);
  1186. }
  1187. /* update display cap to MST_MODE for DP MST encoders */
  1188. info.capabilities |= MSM_DISPLAY_CAP_MST_MODE;
  1189. for (idx = 0; idx < sde_kms->dp_stream_count; idx++) {
  1190. info.h_tile_instance[0] = idx;
  1191. encoder = sde_encoder_init(dev, &info);
  1192. if (IS_ERR_OR_NULL(encoder)) {
  1193. SDE_ERROR("dp mst encoder init failed %d\n", i);
  1194. continue;
  1195. }
  1196. rc = dp_mst_drm_bridge_init(display, encoder);
  1197. if (rc) {
  1198. SDE_ERROR("dp mst bridge %d init failed, %d\n",
  1199. i, rc);
  1200. sde_encoder_destroy(encoder);
  1201. continue;
  1202. }
  1203. priv->encoders[priv->num_encoders++] = encoder;
  1204. }
  1205. }
  1206. return 0;
  1207. }
  1208. static void _sde_kms_drm_obj_destroy(struct sde_kms *sde_kms)
  1209. {
  1210. struct msm_drm_private *priv;
  1211. int i;
  1212. if (!sde_kms) {
  1213. SDE_ERROR("invalid sde_kms\n");
  1214. return;
  1215. } else if (!sde_kms->dev) {
  1216. SDE_ERROR("invalid dev\n");
  1217. return;
  1218. } else if (!sde_kms->dev->dev_private) {
  1219. SDE_ERROR("invalid dev_private\n");
  1220. return;
  1221. }
  1222. priv = sde_kms->dev->dev_private;
  1223. for (i = 0; i < priv->num_crtcs; i++)
  1224. priv->crtcs[i]->funcs->destroy(priv->crtcs[i]);
  1225. priv->num_crtcs = 0;
  1226. for (i = 0; i < priv->num_planes; i++)
  1227. priv->planes[i]->funcs->destroy(priv->planes[i]);
  1228. priv->num_planes = 0;
  1229. for (i = 0; i < priv->num_connectors; i++)
  1230. priv->connectors[i]->funcs->destroy(priv->connectors[i]);
  1231. priv->num_connectors = 0;
  1232. for (i = 0; i < priv->num_encoders; i++)
  1233. priv->encoders[i]->funcs->destroy(priv->encoders[i]);
  1234. priv->num_encoders = 0;
  1235. _sde_kms_release_displays(sde_kms);
  1236. }
  1237. static int _sde_kms_drm_obj_init(struct sde_kms *sde_kms)
  1238. {
  1239. struct drm_device *dev;
  1240. struct drm_plane *primary_planes[MAX_PLANES], *plane;
  1241. struct drm_crtc *crtc;
  1242. struct msm_drm_private *priv;
  1243. struct sde_mdss_cfg *catalog;
  1244. int primary_planes_idx = 0, i, ret;
  1245. int max_crtc_count;
  1246. u32 sspp_id[MAX_PLANES];
  1247. u32 master_plane_id[MAX_PLANES];
  1248. u32 num_virt_planes = 0;
  1249. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  1250. SDE_ERROR("invalid sde_kms\n");
  1251. return -EINVAL;
  1252. }
  1253. dev = sde_kms->dev;
  1254. priv = dev->dev_private;
  1255. catalog = sde_kms->catalog;
  1256. ret = sde_core_irq_domain_add(sde_kms);
  1257. if (ret)
  1258. goto fail_irq;
  1259. /*
  1260. * Query for underlying display drivers, and create connectors,
  1261. * bridges and encoders for them.
  1262. */
  1263. if (!_sde_kms_get_displays(sde_kms))
  1264. (void)_sde_kms_setup_displays(dev, priv, sde_kms);
  1265. max_crtc_count = min(catalog->mixer_count, priv->num_encoders);
  1266. /* Create the planes */
  1267. for (i = 0; i < catalog->sspp_count; i++) {
  1268. bool primary = true;
  1269. if (catalog->sspp[i].features & BIT(SDE_SSPP_CURSOR)
  1270. || primary_planes_idx >= max_crtc_count)
  1271. primary = false;
  1272. plane = sde_plane_init(dev, catalog->sspp[i].id, primary,
  1273. (1UL << max_crtc_count) - 1, 0);
  1274. if (IS_ERR(plane)) {
  1275. SDE_ERROR("sde_plane_init failed\n");
  1276. ret = PTR_ERR(plane);
  1277. goto fail;
  1278. }
  1279. priv->planes[priv->num_planes++] = plane;
  1280. if (primary)
  1281. primary_planes[primary_planes_idx++] = plane;
  1282. if (sde_hw_sspp_multirect_enabled(&catalog->sspp[i]) &&
  1283. sde_is_custom_client()) {
  1284. int priority =
  1285. catalog->sspp[i].sblk->smart_dma_priority;
  1286. sspp_id[priority - 1] = catalog->sspp[i].id;
  1287. master_plane_id[priority - 1] = plane->base.id;
  1288. num_virt_planes++;
  1289. }
  1290. }
  1291. /* Initialize smart DMA virtual planes */
  1292. for (i = 0; i < num_virt_planes; i++) {
  1293. plane = sde_plane_init(dev, sspp_id[i], false,
  1294. (1UL << max_crtc_count) - 1, master_plane_id[i]);
  1295. if (IS_ERR(plane)) {
  1296. SDE_ERROR("sde_plane for virtual SSPP init failed\n");
  1297. ret = PTR_ERR(plane);
  1298. goto fail;
  1299. }
  1300. priv->planes[priv->num_planes++] = plane;
  1301. }
  1302. max_crtc_count = min(max_crtc_count, primary_planes_idx);
  1303. /* Create one CRTC per encoder */
  1304. for (i = 0; i < max_crtc_count; i++) {
  1305. crtc = sde_crtc_init(dev, primary_planes[i]);
  1306. if (IS_ERR(crtc)) {
  1307. ret = PTR_ERR(crtc);
  1308. goto fail;
  1309. }
  1310. priv->crtcs[priv->num_crtcs++] = crtc;
  1311. }
  1312. if (sde_is_custom_client()) {
  1313. /* All CRTCs are compatible with all planes */
  1314. for (i = 0; i < priv->num_planes; i++)
  1315. priv->planes[i]->possible_crtcs =
  1316. (1 << priv->num_crtcs) - 1;
  1317. }
  1318. /* All CRTCs are compatible with all encoders */
  1319. for (i = 0; i < priv->num_encoders; i++)
  1320. priv->encoders[i]->possible_crtcs = (1 << priv->num_crtcs) - 1;
  1321. return 0;
  1322. fail:
  1323. _sde_kms_drm_obj_destroy(sde_kms);
  1324. fail_irq:
  1325. sde_core_irq_domain_fini(sde_kms);
  1326. return ret;
  1327. }
  1328. /**
  1329. * sde_kms_timeline_status - provides current timeline status
  1330. * This API should be called without mode config lock.
  1331. * @dev: Pointer to drm device
  1332. */
  1333. void sde_kms_timeline_status(struct drm_device *dev)
  1334. {
  1335. struct drm_crtc *crtc;
  1336. struct drm_connector *conn;
  1337. struct drm_connector_list_iter conn_iter;
  1338. if (!dev) {
  1339. SDE_ERROR("invalid drm device node\n");
  1340. return;
  1341. }
  1342. drm_for_each_crtc(crtc, dev)
  1343. sde_crtc_timeline_status(crtc);
  1344. if (mutex_is_locked(&dev->mode_config.mutex)) {
  1345. /*
  1346. *Probably locked from last close dumping status anyway
  1347. */
  1348. SDE_ERROR("dumping conn_timeline without mode_config lock\n");
  1349. drm_connector_list_iter_begin(dev, &conn_iter);
  1350. drm_for_each_connector_iter(conn, &conn_iter)
  1351. sde_conn_timeline_status(conn);
  1352. drm_connector_list_iter_end(&conn_iter);
  1353. return;
  1354. }
  1355. mutex_lock(&dev->mode_config.mutex);
  1356. drm_connector_list_iter_begin(dev, &conn_iter);
  1357. drm_for_each_connector_iter(conn, &conn_iter)
  1358. sde_conn_timeline_status(conn);
  1359. drm_connector_list_iter_end(&conn_iter);
  1360. mutex_unlock(&dev->mode_config.mutex);
  1361. }
  1362. static int sde_kms_postinit(struct msm_kms *kms)
  1363. {
  1364. struct sde_kms *sde_kms = to_sde_kms(kms);
  1365. struct drm_device *dev;
  1366. struct drm_crtc *crtc;
  1367. int rc;
  1368. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  1369. SDE_ERROR("invalid sde_kms\n");
  1370. return -EINVAL;
  1371. }
  1372. dev = sde_kms->dev;
  1373. rc = _sde_debugfs_init(sde_kms);
  1374. if (rc)
  1375. SDE_ERROR("sde_debugfs init failed: %d\n", rc);
  1376. drm_for_each_crtc(crtc, dev)
  1377. sde_crtc_post_init(dev, crtc);
  1378. return rc;
  1379. }
  1380. static long sde_kms_round_pixclk(struct msm_kms *kms, unsigned long rate,
  1381. struct drm_encoder *encoder)
  1382. {
  1383. return rate;
  1384. }
  1385. static void _sde_kms_hw_destroy(struct sde_kms *sde_kms,
  1386. struct platform_device *pdev)
  1387. {
  1388. struct drm_device *dev;
  1389. struct msm_drm_private *priv;
  1390. int i;
  1391. if (!sde_kms || !pdev)
  1392. return;
  1393. dev = sde_kms->dev;
  1394. if (!dev)
  1395. return;
  1396. priv = dev->dev_private;
  1397. if (!priv)
  1398. return;
  1399. if (sde_kms->genpd_init) {
  1400. sde_kms->genpd_init = false;
  1401. pm_genpd_remove(&sde_kms->genpd);
  1402. of_genpd_del_provider(pdev->dev.of_node);
  1403. }
  1404. if (sde_kms->hw_intr)
  1405. sde_hw_intr_destroy(sde_kms->hw_intr);
  1406. sde_kms->hw_intr = NULL;
  1407. if (sde_kms->power_event)
  1408. sde_power_handle_unregister_event(
  1409. &priv->phandle, sde_kms->power_event);
  1410. _sde_kms_release_displays(sde_kms);
  1411. _sde_kms_unmap_all_splash_regions(sde_kms);
  1412. /* safe to call these more than once during shutdown */
  1413. _sde_debugfs_destroy(sde_kms);
  1414. _sde_kms_mmu_destroy(sde_kms);
  1415. if (sde_kms->catalog) {
  1416. for (i = 0; i < sde_kms->catalog->vbif_count; i++) {
  1417. u32 vbif_idx = sde_kms->catalog->vbif[i].id;
  1418. if ((vbif_idx < VBIF_MAX) && sde_kms->hw_vbif[vbif_idx])
  1419. sde_hw_vbif_destroy(sde_kms->hw_vbif[vbif_idx]);
  1420. }
  1421. }
  1422. if (sde_kms->rm_init)
  1423. sde_rm_destroy(&sde_kms->rm);
  1424. sde_kms->rm_init = false;
  1425. if (sde_kms->catalog)
  1426. sde_hw_catalog_deinit(sde_kms->catalog);
  1427. sde_kms->catalog = NULL;
  1428. if (sde_kms->sid)
  1429. msm_iounmap(pdev, sde_kms->sid);
  1430. sde_kms->sid = NULL;
  1431. if (sde_kms->sw_fuse)
  1432. msm_iounmap(pdev, sde_kms->sw_fuse);
  1433. sde_hw_sw_fuse_destroy(sde_kms->sw_fuse);
  1434. sde_kms->sw_fuse = NULL;
  1435. if (sde_kms->reg_dma)
  1436. msm_iounmap(pdev, sde_kms->reg_dma);
  1437. sde_kms->reg_dma = NULL;
  1438. if (sde_kms->vbif[VBIF_NRT])
  1439. msm_iounmap(pdev, sde_kms->vbif[VBIF_NRT]);
  1440. sde_kms->vbif[VBIF_NRT] = NULL;
  1441. if (sde_kms->vbif[VBIF_RT])
  1442. msm_iounmap(pdev, sde_kms->vbif[VBIF_RT]);
  1443. sde_kms->vbif[VBIF_RT] = NULL;
  1444. if (sde_kms->mmio)
  1445. msm_iounmap(pdev, sde_kms->mmio);
  1446. sde_kms->mmio = NULL;
  1447. sde_reg_dma_deinit();
  1448. }
  1449. int sde_kms_mmu_detach(struct sde_kms *sde_kms, bool secure_only)
  1450. {
  1451. int i;
  1452. if (!sde_kms)
  1453. return -EINVAL;
  1454. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  1455. struct msm_mmu *mmu;
  1456. struct msm_gem_address_space *aspace = sde_kms->aspace[i];
  1457. if (!aspace)
  1458. continue;
  1459. mmu = sde_kms->aspace[i]->mmu;
  1460. if (secure_only &&
  1461. !aspace->mmu->funcs->is_domain_secure(mmu))
  1462. continue;
  1463. /* cleanup aspace before detaching */
  1464. msm_gem_aspace_domain_attach_detach_update(aspace, true);
  1465. SDE_DEBUG("Detaching domain:%d\n", i);
  1466. aspace->mmu->funcs->detach(mmu, (const char **)iommu_ports,
  1467. ARRAY_SIZE(iommu_ports));
  1468. aspace->domain_attached = false;
  1469. }
  1470. return 0;
  1471. }
  1472. int sde_kms_mmu_attach(struct sde_kms *sde_kms, bool secure_only)
  1473. {
  1474. int i;
  1475. if (!sde_kms)
  1476. return -EINVAL;
  1477. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  1478. struct msm_mmu *mmu;
  1479. struct msm_gem_address_space *aspace = sde_kms->aspace[i];
  1480. if (!aspace)
  1481. continue;
  1482. mmu = sde_kms->aspace[i]->mmu;
  1483. if (secure_only &&
  1484. !aspace->mmu->funcs->is_domain_secure(mmu))
  1485. continue;
  1486. SDE_DEBUG("Attaching domain:%d\n", i);
  1487. aspace->mmu->funcs->attach(mmu, (const char **)iommu_ports,
  1488. ARRAY_SIZE(iommu_ports));
  1489. aspace->domain_attached = true;
  1490. msm_gem_aspace_domain_attach_detach_update(aspace, false);
  1491. }
  1492. return 0;
  1493. }
  1494. static void sde_kms_destroy(struct msm_kms *kms)
  1495. {
  1496. struct sde_kms *sde_kms;
  1497. struct drm_device *dev;
  1498. if (!kms) {
  1499. SDE_ERROR("invalid kms\n");
  1500. return;
  1501. }
  1502. sde_kms = to_sde_kms(kms);
  1503. dev = sde_kms->dev;
  1504. if (!dev || !dev->dev) {
  1505. SDE_ERROR("invalid device\n");
  1506. return;
  1507. }
  1508. _sde_kms_hw_destroy(sde_kms, to_platform_device(dev->dev));
  1509. kfree(sde_kms);
  1510. }
  1511. static void _sde_kms_plane_force_remove(struct drm_plane *plane,
  1512. struct drm_atomic_state *state)
  1513. {
  1514. struct drm_plane_state *plane_state;
  1515. int ret = 0;
  1516. plane_state = drm_atomic_get_plane_state(state, plane);
  1517. if (IS_ERR(plane_state)) {
  1518. ret = PTR_ERR(plane_state);
  1519. SDE_ERROR("error %d getting plane %d state\n",
  1520. ret, plane->base.id);
  1521. return;
  1522. }
  1523. plane->old_fb = plane->fb;
  1524. SDE_DEBUG("disabling plane %d\n", plane->base.id);
  1525. ret = __drm_atomic_helper_disable_plane(plane, plane_state);
  1526. if (ret != 0)
  1527. SDE_ERROR("error %d disabling plane %d\n", ret,
  1528. plane->base.id);
  1529. }
  1530. static int _sde_kms_remove_fbs(struct sde_kms *sde_kms, struct drm_file *file,
  1531. struct drm_atomic_state *state)
  1532. {
  1533. struct drm_device *dev = sde_kms->dev;
  1534. struct drm_framebuffer *fb, *tfb;
  1535. struct list_head fbs;
  1536. struct drm_plane *plane;
  1537. int ret = 0;
  1538. u32 plane_mask = 0;
  1539. INIT_LIST_HEAD(&fbs);
  1540. list_for_each_entry_safe(fb, tfb, &file->fbs, filp_head) {
  1541. if (drm_framebuffer_read_refcount(fb) > 1) {
  1542. list_move_tail(&fb->filp_head, &fbs);
  1543. drm_for_each_plane(plane, dev) {
  1544. if (plane->fb == fb) {
  1545. plane_mask |=
  1546. 1 << drm_plane_index(plane);
  1547. _sde_kms_plane_force_remove(
  1548. plane, state);
  1549. }
  1550. }
  1551. } else {
  1552. list_del_init(&fb->filp_head);
  1553. drm_framebuffer_put(fb);
  1554. }
  1555. }
  1556. if (list_empty(&fbs)) {
  1557. SDE_DEBUG("skip commit as no fb(s)\n");
  1558. drm_atomic_state_put(state);
  1559. return 0;
  1560. }
  1561. SDE_DEBUG("committing after removing all the pipes\n");
  1562. ret = drm_atomic_commit(state);
  1563. if (ret) {
  1564. /*
  1565. * move the fbs back to original list, so it would be
  1566. * handled during drm_release
  1567. */
  1568. list_for_each_entry_safe(fb, tfb, &fbs, filp_head)
  1569. list_move_tail(&fb->filp_head, &file->fbs);
  1570. SDE_ERROR("atomic commit failed in preclose, ret:%d\n", ret);
  1571. goto end;
  1572. }
  1573. while (!list_empty(&fbs)) {
  1574. fb = list_first_entry(&fbs, typeof(*fb), filp_head);
  1575. list_del_init(&fb->filp_head);
  1576. drm_framebuffer_put(fb);
  1577. }
  1578. end:
  1579. return ret;
  1580. }
  1581. static void sde_kms_preclose(struct msm_kms *kms, struct drm_file *file)
  1582. {
  1583. struct sde_kms *sde_kms = to_sde_kms(kms);
  1584. struct drm_device *dev = sde_kms->dev;
  1585. struct msm_drm_private *priv = dev->dev_private;
  1586. unsigned int i;
  1587. struct drm_atomic_state *state = NULL;
  1588. struct drm_modeset_acquire_ctx ctx;
  1589. int ret = 0;
  1590. /* cancel pending flip event */
  1591. for (i = 0; i < priv->num_crtcs; i++)
  1592. sde_crtc_complete_flip(priv->crtcs[i], file);
  1593. drm_modeset_acquire_init(&ctx, 0);
  1594. retry:
  1595. ret = drm_modeset_lock_all_ctx(dev, &ctx);
  1596. if (ret == -EDEADLK) {
  1597. drm_modeset_backoff(&ctx);
  1598. goto retry;
  1599. } else if (WARN_ON(ret)) {
  1600. goto end;
  1601. }
  1602. state = drm_atomic_state_alloc(dev);
  1603. if (!state) {
  1604. ret = -ENOMEM;
  1605. goto end;
  1606. }
  1607. state->acquire_ctx = &ctx;
  1608. for (i = 0; i < TEARDOWN_DEADLOCK_RETRY_MAX; i++) {
  1609. ret = _sde_kms_remove_fbs(sde_kms, file, state);
  1610. if (ret != -EDEADLK)
  1611. break;
  1612. drm_atomic_state_clear(state);
  1613. drm_modeset_backoff(&ctx);
  1614. }
  1615. end:
  1616. if (state)
  1617. drm_atomic_state_put(state);
  1618. SDE_DEBUG("sde preclose done, ret:%d\n", ret);
  1619. drm_modeset_drop_locks(&ctx);
  1620. drm_modeset_acquire_fini(&ctx);
  1621. }
  1622. static int _sde_kms_helper_reset_custom_properties(struct sde_kms *sde_kms,
  1623. struct drm_atomic_state *state)
  1624. {
  1625. struct drm_device *dev = sde_kms->dev;
  1626. struct drm_plane *plane;
  1627. struct drm_plane_state *plane_state;
  1628. struct drm_crtc *crtc;
  1629. struct drm_crtc_state *crtc_state;
  1630. struct drm_connector *conn;
  1631. struct drm_connector_state *conn_state;
  1632. struct drm_connector_list_iter conn_iter;
  1633. int ret = 0;
  1634. drm_for_each_plane(plane, dev) {
  1635. plane_state = drm_atomic_get_plane_state(state, plane);
  1636. if (IS_ERR(plane_state)) {
  1637. ret = PTR_ERR(plane_state);
  1638. SDE_ERROR("error %d getting plane %d state\n",
  1639. ret, DRMID(plane));
  1640. return ret;
  1641. }
  1642. ret = sde_plane_helper_reset_custom_properties(plane,
  1643. plane_state);
  1644. if (ret) {
  1645. SDE_ERROR("error %d resetting plane props %d\n",
  1646. ret, DRMID(plane));
  1647. return ret;
  1648. }
  1649. }
  1650. drm_for_each_crtc(crtc, dev) {
  1651. crtc_state = drm_atomic_get_crtc_state(state, crtc);
  1652. if (IS_ERR(crtc_state)) {
  1653. ret = PTR_ERR(crtc_state);
  1654. SDE_ERROR("error %d getting crtc %d state\n",
  1655. ret, DRMID(crtc));
  1656. return ret;
  1657. }
  1658. ret = sde_crtc_helper_reset_custom_properties(crtc, crtc_state);
  1659. if (ret) {
  1660. SDE_ERROR("error %d resetting crtc props %d\n",
  1661. ret, DRMID(crtc));
  1662. return ret;
  1663. }
  1664. }
  1665. drm_connector_list_iter_begin(dev, &conn_iter);
  1666. drm_for_each_connector_iter(conn, &conn_iter) {
  1667. conn_state = drm_atomic_get_connector_state(state, conn);
  1668. if (IS_ERR(conn_state)) {
  1669. ret = PTR_ERR(conn_state);
  1670. SDE_ERROR("error %d getting connector %d state\n",
  1671. ret, DRMID(conn));
  1672. return ret;
  1673. }
  1674. ret = sde_connector_helper_reset_custom_properties(conn,
  1675. conn_state);
  1676. if (ret) {
  1677. SDE_ERROR("error %d resetting connector props %d\n",
  1678. ret, DRMID(conn));
  1679. return ret;
  1680. }
  1681. }
  1682. drm_connector_list_iter_end(&conn_iter);
  1683. return ret;
  1684. }
  1685. static void sde_kms_lastclose(struct msm_kms *kms,
  1686. struct drm_modeset_acquire_ctx *ctx)
  1687. {
  1688. struct sde_kms *sde_kms;
  1689. struct drm_device *dev;
  1690. struct drm_atomic_state *state;
  1691. int ret, i;
  1692. if (!kms) {
  1693. SDE_ERROR("invalid argument\n");
  1694. return;
  1695. }
  1696. sde_kms = to_sde_kms(kms);
  1697. dev = sde_kms->dev;
  1698. state = drm_atomic_state_alloc(dev);
  1699. if (!state)
  1700. return;
  1701. state->acquire_ctx = ctx;
  1702. for (i = 0; i < TEARDOWN_DEADLOCK_RETRY_MAX; i++) {
  1703. /* add reset of custom properties to the state */
  1704. ret = _sde_kms_helper_reset_custom_properties(sde_kms, state);
  1705. if (ret)
  1706. break;
  1707. ret = drm_atomic_commit(state);
  1708. if (ret != -EDEADLK)
  1709. break;
  1710. drm_atomic_state_clear(state);
  1711. drm_modeset_backoff(ctx);
  1712. SDE_DEBUG("deadlock backoff on attempt %d\n", i);
  1713. }
  1714. if (ret)
  1715. SDE_ERROR("failed to run last close: %d\n", ret);
  1716. drm_atomic_state_put(state);
  1717. }
  1718. static int sde_kms_check_secure_transition(struct msm_kms *kms,
  1719. struct drm_atomic_state *state)
  1720. {
  1721. struct sde_kms *sde_kms;
  1722. struct drm_device *dev;
  1723. struct drm_crtc *crtc;
  1724. struct drm_crtc *cur_crtc = NULL, *global_crtc = NULL;
  1725. struct drm_crtc_state *crtc_state;
  1726. int active_crtc_cnt = 0, global_active_crtc_cnt = 0;
  1727. bool sec_session = false, global_sec_session = false;
  1728. uint32_t fb_ns = 0, fb_sec = 0, fb_sec_dir = 0;
  1729. int i;
  1730. if (!kms || !state) {
  1731. return -EINVAL;
  1732. SDE_ERROR("invalid arguments\n");
  1733. }
  1734. sde_kms = to_sde_kms(kms);
  1735. dev = sde_kms->dev;
  1736. /* iterate state object for active secure/non-secure crtc */
  1737. for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
  1738. if (!crtc_state->active)
  1739. continue;
  1740. active_crtc_cnt++;
  1741. sde_crtc_state_find_plane_fb_modes(crtc_state, &fb_ns,
  1742. &fb_sec, &fb_sec_dir);
  1743. if (fb_sec_dir)
  1744. sec_session = true;
  1745. cur_crtc = crtc;
  1746. }
  1747. /* iterate global list for active and secure/non-secure crtc */
  1748. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  1749. if (!crtc->state->active)
  1750. continue;
  1751. global_active_crtc_cnt++;
  1752. /* update only when crtc is not the same as current crtc */
  1753. if (crtc != cur_crtc) {
  1754. fb_ns = fb_sec = fb_sec_dir = 0;
  1755. sde_crtc_find_plane_fb_modes(crtc, &fb_ns,
  1756. &fb_sec, &fb_sec_dir);
  1757. if (fb_sec_dir)
  1758. global_sec_session = true;
  1759. global_crtc = crtc;
  1760. }
  1761. }
  1762. if (!global_sec_session && !sec_session)
  1763. return 0;
  1764. /*
  1765. * - fail crtc commit, if secure-camera/secure-ui session is
  1766. * in-progress in any other display
  1767. * - fail secure-camera/secure-ui crtc commit, if any other display
  1768. * session is in-progress
  1769. */
  1770. if ((global_active_crtc_cnt > MAX_ALLOWED_CRTC_CNT_DURING_SECURE) ||
  1771. (active_crtc_cnt > MAX_ALLOWED_CRTC_CNT_DURING_SECURE)) {
  1772. SDE_ERROR(
  1773. "crtc%d secure check failed global_active:%d active:%d\n",
  1774. cur_crtc ? cur_crtc->base.id : -1,
  1775. global_active_crtc_cnt, active_crtc_cnt);
  1776. return -EPERM;
  1777. /*
  1778. * As only one crtc is allowed during secure session, the crtc
  1779. * in this commit should match with the global crtc
  1780. */
  1781. } else if (global_crtc && cur_crtc && (global_crtc != cur_crtc)) {
  1782. SDE_ERROR("crtc%d-sec%d not allowed during crtc%d-sec%d\n",
  1783. cur_crtc->base.id, sec_session,
  1784. global_crtc->base.id, global_sec_session);
  1785. return -EPERM;
  1786. }
  1787. return 0;
  1788. }
  1789. static int sde_kms_atomic_check(struct msm_kms *kms,
  1790. struct drm_atomic_state *state)
  1791. {
  1792. struct sde_kms *sde_kms;
  1793. struct drm_device *dev;
  1794. int ret;
  1795. if (!kms || !state)
  1796. return -EINVAL;
  1797. sde_kms = to_sde_kms(kms);
  1798. dev = sde_kms->dev;
  1799. SDE_ATRACE_BEGIN("atomic_check");
  1800. if (sde_kms_is_suspend_blocked(dev)) {
  1801. SDE_DEBUG("suspended, skip atomic_check\n");
  1802. ret = -EBUSY;
  1803. goto end;
  1804. }
  1805. ret = drm_atomic_helper_check(dev, state);
  1806. if (ret)
  1807. goto end;
  1808. /*
  1809. * Check if any secure transition(moving CRTC between secure and
  1810. * non-secure state and vice-versa) is allowed or not. when moving
  1811. * to secure state, planes with fb_mode set to dir_translated only can
  1812. * be staged on the CRTC, and only one CRTC can be active during
  1813. * Secure state
  1814. */
  1815. ret = sde_kms_check_secure_transition(kms, state);
  1816. end:
  1817. SDE_ATRACE_END("atomic_check");
  1818. return ret;
  1819. }
  1820. static struct msm_gem_address_space*
  1821. _sde_kms_get_address_space(struct msm_kms *kms,
  1822. unsigned int domain)
  1823. {
  1824. struct sde_kms *sde_kms;
  1825. if (!kms) {
  1826. SDE_ERROR("invalid kms\n");
  1827. return NULL;
  1828. }
  1829. sde_kms = to_sde_kms(kms);
  1830. if (!sde_kms) {
  1831. SDE_ERROR("invalid sde_kms\n");
  1832. return NULL;
  1833. }
  1834. if (domain >= MSM_SMMU_DOMAIN_MAX)
  1835. return NULL;
  1836. return (sde_kms->aspace[domain] &&
  1837. sde_kms->aspace[domain]->domain_attached) ?
  1838. sde_kms->aspace[domain] : NULL;
  1839. }
  1840. static struct device *_sde_kms_get_address_space_device(struct msm_kms *kms,
  1841. unsigned int domain)
  1842. {
  1843. struct msm_gem_address_space *aspace =
  1844. _sde_kms_get_address_space(kms, domain);
  1845. return (aspace && aspace->domain_attached) ?
  1846. msm_gem_get_aspace_device(aspace) : NULL;
  1847. }
  1848. static void _sde_kms_post_open(struct msm_kms *kms, struct drm_file *file)
  1849. {
  1850. struct drm_device *dev = NULL;
  1851. struct sde_kms *sde_kms = NULL;
  1852. struct drm_connector *connector = NULL;
  1853. struct drm_connector_list_iter conn_iter;
  1854. struct sde_connector *sde_conn = NULL;
  1855. if (!kms) {
  1856. SDE_ERROR("invalid kms\n");
  1857. return;
  1858. }
  1859. sde_kms = to_sde_kms(kms);
  1860. dev = sde_kms->dev;
  1861. if (!dev) {
  1862. SDE_ERROR("invalid device\n");
  1863. return;
  1864. }
  1865. if (!dev->mode_config.poll_enabled)
  1866. return;
  1867. mutex_lock(&dev->mode_config.mutex);
  1868. drm_connector_list_iter_begin(dev, &conn_iter);
  1869. drm_for_each_connector_iter(connector, &conn_iter) {
  1870. /* Only handle HPD capable connectors. */
  1871. if (!(connector->polled & DRM_CONNECTOR_POLL_HPD))
  1872. continue;
  1873. sde_conn = to_sde_connector(connector);
  1874. if (sde_conn->ops.post_open)
  1875. sde_conn->ops.post_open(&sde_conn->base,
  1876. sde_conn->display);
  1877. }
  1878. drm_connector_list_iter_end(&conn_iter);
  1879. mutex_unlock(&dev->mode_config.mutex);
  1880. }
  1881. static int _sde_kms_update_planes_for_cont_splash(struct sde_kms *sde_kms,
  1882. struct sde_splash_display *splash_display,
  1883. struct drm_crtc *crtc)
  1884. {
  1885. struct msm_drm_private *priv;
  1886. struct drm_plane *plane;
  1887. struct sde_splash_mem *splash;
  1888. enum sde_sspp plane_id;
  1889. bool is_virtual;
  1890. int i, j;
  1891. if (!sde_kms || !splash_display || !crtc) {
  1892. SDE_ERROR("invalid input args\n");
  1893. return -EINVAL;
  1894. }
  1895. priv = sde_kms->dev->dev_private;
  1896. for (i = 0; i < priv->num_planes; i++) {
  1897. plane = priv->planes[i];
  1898. plane_id = sde_plane_pipe(plane);
  1899. is_virtual = is_sde_plane_virtual(plane);
  1900. splash = splash_display->splash;
  1901. for (j = 0; j < splash_display->pipe_cnt; j++) {
  1902. if ((plane_id != splash_display->pipes[j].sspp) ||
  1903. (splash_display->pipes[j].is_virtual
  1904. != is_virtual))
  1905. continue;
  1906. if (splash && sde_plane_validate_src_addr(plane,
  1907. splash->splash_buf_base,
  1908. splash->splash_buf_size)) {
  1909. SDE_ERROR("invalid adr on pipe:%d crtc:%d\n",
  1910. plane_id, crtc->base.id);
  1911. }
  1912. SDE_DEBUG("set crtc:%d for plane:%d rect:%d\n",
  1913. crtc->base.id, plane_id, is_virtual);
  1914. }
  1915. }
  1916. return 0;
  1917. }
  1918. static int sde_kms_cont_splash_config(struct msm_kms *kms)
  1919. {
  1920. void *display;
  1921. struct dsi_display *dsi_display;
  1922. struct msm_display_info info;
  1923. struct drm_encoder *encoder = NULL;
  1924. struct drm_crtc *crtc = NULL;
  1925. int i, rc = 0;
  1926. struct drm_display_mode *drm_mode = NULL;
  1927. struct drm_device *dev;
  1928. struct msm_drm_private *priv;
  1929. struct sde_kms *sde_kms;
  1930. struct drm_connector_list_iter conn_iter;
  1931. struct drm_connector *connector = NULL;
  1932. struct sde_connector *sde_conn = NULL;
  1933. struct sde_splash_display *splash_display;
  1934. if (!kms) {
  1935. SDE_ERROR("invalid kms\n");
  1936. return -EINVAL;
  1937. }
  1938. sde_kms = to_sde_kms(kms);
  1939. dev = sde_kms->dev;
  1940. if (!dev) {
  1941. SDE_ERROR("invalid device\n");
  1942. return -EINVAL;
  1943. }
  1944. if (!sde_kms->splash_data.num_splash_regions ||
  1945. !sde_kms->splash_data.num_splash_displays) {
  1946. DRM_INFO("cont_splash feature not enabled\n");
  1947. return rc;
  1948. }
  1949. DRM_INFO("cont_splash enabled in %d of %d display(s)\n",
  1950. sde_kms->splash_data.num_splash_displays,
  1951. sde_kms->dsi_display_count);
  1952. /* dsi */
  1953. for (i = 0; i < sde_kms->dsi_display_count; ++i) {
  1954. display = sde_kms->dsi_displays[i];
  1955. dsi_display = (struct dsi_display *)display;
  1956. splash_display = &sde_kms->splash_data.splash_display[i];
  1957. if (!splash_display->cont_splash_enabled) {
  1958. SDE_DEBUG("display->name = %s splash not enabled\n",
  1959. dsi_display->name);
  1960. continue;
  1961. }
  1962. SDE_DEBUG("display->name = %s\n", dsi_display->name);
  1963. if (dsi_display->bridge->base.encoder) {
  1964. encoder = dsi_display->bridge->base.encoder;
  1965. SDE_DEBUG("encoder name = %s\n", encoder->name);
  1966. }
  1967. memset(&info, 0x0, sizeof(info));
  1968. rc = dsi_display_get_info(NULL, &info, display);
  1969. if (rc) {
  1970. SDE_ERROR("dsi get_info %d failed\n", i);
  1971. encoder = NULL;
  1972. continue;
  1973. }
  1974. SDE_DEBUG("info.is_connected = %s, info.display_type = %d\n",
  1975. ((info.is_connected) ? "true" : "false"),
  1976. info.display_type);
  1977. if (!encoder) {
  1978. SDE_ERROR("encoder not initialized\n");
  1979. return -EINVAL;
  1980. }
  1981. priv = sde_kms->dev->dev_private;
  1982. encoder->crtc = priv->crtcs[i];
  1983. crtc = encoder->crtc;
  1984. splash_display->encoder = encoder;
  1985. SDE_DEBUG("for dsi-display:%d crtc id = %d enc id =%d\n",
  1986. i, crtc->base.id, encoder->base.id);
  1987. mutex_lock(&dev->mode_config.mutex);
  1988. drm_connector_list_iter_begin(dev, &conn_iter);
  1989. drm_for_each_connector_iter(connector, &conn_iter) {
  1990. /**
  1991. * SDE_KMS doesn't attach more than one encoder to
  1992. * a DSI connector. So it is safe to check only with
  1993. * the first encoder entry. Revisit this logic if we
  1994. * ever have to support continuous splash for
  1995. * external displays in MST configuration.
  1996. */
  1997. if (connector->encoder_ids[0] == encoder->base.id)
  1998. break;
  1999. }
  2000. drm_connector_list_iter_end(&conn_iter);
  2001. if (!connector) {
  2002. SDE_ERROR("connector not initialized\n");
  2003. mutex_unlock(&dev->mode_config.mutex);
  2004. return -EINVAL;
  2005. }
  2006. if (connector->funcs->fill_modes) {
  2007. connector->funcs->fill_modes(connector,
  2008. dev->mode_config.max_width,
  2009. dev->mode_config.max_height);
  2010. } else {
  2011. SDE_ERROR("fill_modes api not defined\n");
  2012. mutex_unlock(&dev->mode_config.mutex);
  2013. return -EINVAL;
  2014. }
  2015. mutex_unlock(&dev->mode_config.mutex);
  2016. crtc->state->encoder_mask = (1 << drm_encoder_index(encoder));
  2017. /* currently consider modes[0] as the preferred mode */
  2018. drm_mode = list_first_entry(&connector->modes,
  2019. struct drm_display_mode, head);
  2020. SDE_DEBUG("drm_mode->name = %s, id=%d, type=0x%x, flags=0x%x\n",
  2021. drm_mode->name, drm_mode->base.id,
  2022. drm_mode->type, drm_mode->flags);
  2023. /* Update CRTC drm structure */
  2024. crtc->state->active = true;
  2025. rc = drm_atomic_set_mode_for_crtc(crtc->state, drm_mode);
  2026. if (rc) {
  2027. SDE_ERROR("Failed: set mode for crtc. rc = %d\n", rc);
  2028. return rc;
  2029. }
  2030. drm_mode_copy(&crtc->state->adjusted_mode, drm_mode);
  2031. drm_mode_copy(&crtc->mode, drm_mode);
  2032. /* Update encoder structure */
  2033. sde_encoder_update_caps_for_cont_splash(encoder,
  2034. splash_display, true);
  2035. sde_crtc_update_cont_splash_settings(crtc);
  2036. sde_conn = to_sde_connector(connector);
  2037. if (sde_conn && sde_conn->ops.cont_splash_config)
  2038. sde_conn->ops.cont_splash_config(sde_conn->display);
  2039. rc = _sde_kms_update_planes_for_cont_splash(sde_kms,
  2040. splash_display, crtc);
  2041. if (rc) {
  2042. SDE_ERROR("Failed: updating plane status rc=%d\n", rc);
  2043. return rc;
  2044. }
  2045. }
  2046. return rc;
  2047. }
  2048. static bool sde_kms_check_for_splash(struct msm_kms *kms)
  2049. {
  2050. struct sde_kms *sde_kms;
  2051. if (!kms) {
  2052. SDE_ERROR("invalid kms\n");
  2053. return false;
  2054. }
  2055. sde_kms = to_sde_kms(kms);
  2056. return sde_kms->splash_data.num_splash_displays;
  2057. }
  2058. static int sde_kms_get_mixer_count(const struct msm_kms *kms,
  2059. const struct drm_display_mode *mode,
  2060. const struct msm_resource_caps_info *res, u32 *num_lm)
  2061. {
  2062. struct sde_kms *sde_kms;
  2063. s64 mode_clock_hz = 0;
  2064. s64 max_mdp_clock_hz = 0;
  2065. s64 mdp_fudge_factor = 0;
  2066. s64 temp = 0;
  2067. s64 htotal_fp = 0;
  2068. s64 vtotal_fp = 0;
  2069. s64 vrefresh_fp = 0;
  2070. if (!num_lm) {
  2071. SDE_ERROR("invalid num_lm pointer\n");
  2072. return -EINVAL;
  2073. }
  2074. *num_lm = 1;
  2075. if (!kms || !mode || !res) {
  2076. SDE_ERROR("invalid input args\n");
  2077. return -EINVAL;
  2078. }
  2079. sde_kms = to_sde_kms(kms);
  2080. max_mdp_clock_hz = drm_fixp_from_fraction(
  2081. sde_kms->perf.max_core_clk_rate, 1);
  2082. mdp_fudge_factor = drm_fixp_from_fraction(105, 100); /* 1.05 */
  2083. htotal_fp = drm_fixp_from_fraction(mode->htotal, 1);
  2084. vtotal_fp = drm_fixp_from_fraction(mode->vtotal, 1);
  2085. vrefresh_fp = drm_fixp_from_fraction(mode->vrefresh, 1);
  2086. temp = drm_fixp_mul(htotal_fp, vtotal_fp);
  2087. temp = drm_fixp_mul(temp, vrefresh_fp);
  2088. mode_clock_hz = drm_fixp_mul(temp, mdp_fudge_factor);
  2089. if (mode_clock_hz > max_mdp_clock_hz ||
  2090. mode->hdisplay > res->max_mixer_width)
  2091. *num_lm = 2;
  2092. SDE_DEBUG("[%s] h=%d, v=%d, fps=%d, max_mdp_clk_hz=%llu, num_lm=%d\n",
  2093. mode->name, mode->htotal, mode->vtotal, mode->vrefresh,
  2094. sde_kms->perf.max_core_clk_rate, *num_lm);
  2095. return 0;
  2096. }
  2097. static void _sde_kms_null_commit(struct drm_device *dev,
  2098. struct drm_encoder *enc)
  2099. {
  2100. struct drm_modeset_acquire_ctx ctx;
  2101. struct drm_connector *conn = NULL;
  2102. struct drm_connector *tmp_conn = NULL;
  2103. struct drm_connector_list_iter conn_iter;
  2104. struct drm_atomic_state *state = NULL;
  2105. struct drm_crtc_state *crtc_state = NULL;
  2106. struct drm_connector_state *conn_state = NULL;
  2107. int retry_cnt = 0;
  2108. int ret = 0;
  2109. drm_modeset_acquire_init(&ctx, 0);
  2110. retry:
  2111. ret = drm_modeset_lock_all_ctx(dev, &ctx);
  2112. if (ret == -EDEADLK && retry_cnt < SDE_KMS_MODESET_LOCK_MAX_TRIALS) {
  2113. drm_modeset_backoff(&ctx);
  2114. retry_cnt++;
  2115. udelay(SDE_KMS_MODESET_LOCK_TIMEOUT_US);
  2116. goto retry;
  2117. } else if (WARN_ON(ret)) {
  2118. goto end;
  2119. }
  2120. state = drm_atomic_state_alloc(dev);
  2121. if (!state) {
  2122. DRM_ERROR("failed to allocate atomic state, %d\n", ret);
  2123. goto end;
  2124. }
  2125. state->acquire_ctx = &ctx;
  2126. drm_connector_list_iter_begin(dev, &conn_iter);
  2127. drm_for_each_connector_iter(tmp_conn, &conn_iter) {
  2128. if (enc == tmp_conn->state->best_encoder) {
  2129. conn = tmp_conn;
  2130. break;
  2131. }
  2132. }
  2133. drm_connector_list_iter_end(&conn_iter);
  2134. if (!conn) {
  2135. SDE_ERROR("error in finding conn for enc:%d\n", DRMID(enc));
  2136. goto end;
  2137. }
  2138. crtc_state = drm_atomic_get_crtc_state(state, enc->crtc);
  2139. conn_state = drm_atomic_get_connector_state(state, conn);
  2140. if (IS_ERR(conn_state)) {
  2141. SDE_ERROR("error %d getting connector %d state\n",
  2142. ret, DRMID(conn));
  2143. goto end;
  2144. }
  2145. crtc_state->active = true;
  2146. ret = drm_atomic_set_crtc_for_connector(conn_state, enc->crtc);
  2147. if (ret)
  2148. SDE_ERROR("error %d setting the crtc\n", ret);
  2149. ret = drm_atomic_commit(state);
  2150. if (ret)
  2151. SDE_ERROR("Error %d doing the atomic commit\n", ret);
  2152. end:
  2153. if (state)
  2154. drm_atomic_state_put(state);
  2155. drm_modeset_drop_locks(&ctx);
  2156. drm_modeset_acquire_fini(&ctx);
  2157. }
  2158. static int sde_kms_pm_suspend(struct device *dev)
  2159. {
  2160. struct drm_device *ddev;
  2161. struct drm_modeset_acquire_ctx ctx;
  2162. struct drm_connector *conn;
  2163. struct drm_encoder *enc;
  2164. struct drm_connector_list_iter conn_iter;
  2165. struct drm_atomic_state *state = NULL;
  2166. struct sde_kms *sde_kms;
  2167. int ret = 0, num_crtcs = 0;
  2168. if (!dev)
  2169. return -EINVAL;
  2170. ddev = dev_get_drvdata(dev);
  2171. if (!ddev || !ddev_to_msm_kms(ddev))
  2172. return -EINVAL;
  2173. sde_kms = to_sde_kms(ddev_to_msm_kms(ddev));
  2174. SDE_EVT32(0);
  2175. /* disable hot-plug polling */
  2176. drm_kms_helper_poll_disable(ddev);
  2177. /* if a display stuck in CS trigger a null commit to complete handoff */
  2178. drm_for_each_encoder(enc, ddev) {
  2179. if (sde_encoder_in_cont_splash(enc) && enc->crtc)
  2180. _sde_kms_null_commit(ddev, enc);
  2181. }
  2182. /* acquire modeset lock(s) */
  2183. drm_modeset_acquire_init(&ctx, 0);
  2184. retry:
  2185. ret = drm_modeset_lock_all_ctx(ddev, &ctx);
  2186. if (ret)
  2187. goto unlock;
  2188. /* save current state for resume */
  2189. if (sde_kms->suspend_state)
  2190. drm_atomic_state_put(sde_kms->suspend_state);
  2191. sde_kms->suspend_state = drm_atomic_helper_duplicate_state(ddev, &ctx);
  2192. if (IS_ERR_OR_NULL(sde_kms->suspend_state)) {
  2193. ret = PTR_ERR(sde_kms->suspend_state);
  2194. DRM_ERROR("failed to back up suspend state, %d\n", ret);
  2195. sde_kms->suspend_state = NULL;
  2196. goto unlock;
  2197. }
  2198. /* create atomic state to disable all CRTCs */
  2199. state = drm_atomic_state_alloc(ddev);
  2200. if (!state) {
  2201. ret = -ENOMEM;
  2202. DRM_ERROR("failed to allocate crtc disable state, %d\n", ret);
  2203. goto unlock;
  2204. }
  2205. state->acquire_ctx = &ctx;
  2206. drm_connector_list_iter_begin(ddev, &conn_iter);
  2207. drm_for_each_connector_iter(conn, &conn_iter) {
  2208. struct drm_crtc_state *crtc_state;
  2209. uint64_t lp;
  2210. if (!conn->state || !conn->state->crtc ||
  2211. conn->dpms != DRM_MODE_DPMS_ON)
  2212. continue;
  2213. lp = sde_connector_get_lp(conn);
  2214. if (lp == SDE_MODE_DPMS_LP1) {
  2215. /* transition LP1->LP2 on pm suspend */
  2216. ret = sde_connector_set_property_for_commit(conn, state,
  2217. CONNECTOR_PROP_LP, SDE_MODE_DPMS_LP2);
  2218. if (ret) {
  2219. DRM_ERROR("failed to set lp2 for conn %d\n",
  2220. conn->base.id);
  2221. drm_connector_list_iter_end(&conn_iter);
  2222. goto unlock;
  2223. }
  2224. }
  2225. if (lp != SDE_MODE_DPMS_LP2) {
  2226. /* force CRTC to be inactive */
  2227. crtc_state = drm_atomic_get_crtc_state(state,
  2228. conn->state->crtc);
  2229. if (IS_ERR_OR_NULL(crtc_state)) {
  2230. DRM_ERROR("failed to get crtc %d state\n",
  2231. conn->state->crtc->base.id);
  2232. drm_connector_list_iter_end(&conn_iter);
  2233. goto unlock;
  2234. }
  2235. if (lp != SDE_MODE_DPMS_LP1)
  2236. crtc_state->active = false;
  2237. ++num_crtcs;
  2238. }
  2239. }
  2240. drm_connector_list_iter_end(&conn_iter);
  2241. /* check for nothing to do */
  2242. if (num_crtcs == 0) {
  2243. DRM_DEBUG("all crtcs are already in the off state\n");
  2244. sde_kms->suspend_block = true;
  2245. goto unlock;
  2246. }
  2247. /* commit the "disable all" state */
  2248. ret = drm_atomic_commit(state);
  2249. if (ret < 0) {
  2250. DRM_ERROR("failed to disable crtcs, %d\n", ret);
  2251. goto unlock;
  2252. }
  2253. sde_kms->suspend_block = true;
  2254. drm_connector_list_iter_begin(ddev, &conn_iter);
  2255. drm_for_each_connector_iter(conn, &conn_iter) {
  2256. uint64_t lp;
  2257. lp = sde_connector_get_lp(conn);
  2258. if (lp != SDE_MODE_DPMS_LP2)
  2259. continue;
  2260. ret = sde_encoder_wait_for_event(conn->encoder,
  2261. MSM_ENC_TX_COMPLETE);
  2262. if (ret && ret != -EWOULDBLOCK)
  2263. SDE_ERROR(
  2264. "[enc: %d] wait for commit done returned %d\n",
  2265. conn->encoder->base.id, ret);
  2266. else if (!ret)
  2267. sde_encoder_idle_request(conn->encoder);
  2268. }
  2269. drm_connector_list_iter_end(&conn_iter);
  2270. unlock:
  2271. if (state) {
  2272. drm_atomic_state_put(state);
  2273. state = NULL;
  2274. }
  2275. if (ret == -EDEADLK) {
  2276. drm_modeset_backoff(&ctx);
  2277. goto retry;
  2278. }
  2279. drm_modeset_drop_locks(&ctx);
  2280. drm_modeset_acquire_fini(&ctx);
  2281. return ret;
  2282. }
  2283. static int sde_kms_pm_resume(struct device *dev)
  2284. {
  2285. struct drm_device *ddev;
  2286. struct sde_kms *sde_kms;
  2287. struct drm_modeset_acquire_ctx ctx;
  2288. int ret, i;
  2289. if (!dev)
  2290. return -EINVAL;
  2291. ddev = dev_get_drvdata(dev);
  2292. if (!ddev || !ddev_to_msm_kms(ddev))
  2293. return -EINVAL;
  2294. sde_kms = to_sde_kms(ddev_to_msm_kms(ddev));
  2295. SDE_EVT32(sde_kms->suspend_state != NULL);
  2296. drm_mode_config_reset(ddev);
  2297. drm_modeset_acquire_init(&ctx, 0);
  2298. retry:
  2299. ret = drm_modeset_lock_all_ctx(ddev, &ctx);
  2300. if (ret == -EDEADLK) {
  2301. drm_modeset_backoff(&ctx);
  2302. goto retry;
  2303. } else if (WARN_ON(ret)) {
  2304. goto end;
  2305. }
  2306. sde_kms->suspend_block = false;
  2307. if (sde_kms->suspend_state) {
  2308. sde_kms->suspend_state->acquire_ctx = &ctx;
  2309. for (i = 0; i < TEARDOWN_DEADLOCK_RETRY_MAX; i++) {
  2310. ret = drm_atomic_helper_commit_duplicated_state(
  2311. sde_kms->suspend_state, &ctx);
  2312. if (ret != -EDEADLK)
  2313. break;
  2314. drm_modeset_backoff(&ctx);
  2315. }
  2316. if (ret < 0)
  2317. DRM_ERROR("failed to restore state, %d\n", ret);
  2318. drm_atomic_state_put(sde_kms->suspend_state);
  2319. sde_kms->suspend_state = NULL;
  2320. }
  2321. end:
  2322. drm_modeset_drop_locks(&ctx);
  2323. drm_modeset_acquire_fini(&ctx);
  2324. /* enable hot-plug polling */
  2325. drm_kms_helper_poll_enable(ddev);
  2326. return 0;
  2327. }
  2328. static const struct msm_kms_funcs kms_funcs = {
  2329. .hw_init = sde_kms_hw_init,
  2330. .postinit = sde_kms_postinit,
  2331. .irq_preinstall = sde_irq_preinstall,
  2332. .irq_postinstall = sde_irq_postinstall,
  2333. .irq_uninstall = sde_irq_uninstall,
  2334. .irq = sde_irq,
  2335. .preclose = sde_kms_preclose,
  2336. .lastclose = sde_kms_lastclose,
  2337. .prepare_fence = sde_kms_prepare_fence,
  2338. .prepare_commit = sde_kms_prepare_commit,
  2339. .commit = sde_kms_commit,
  2340. .complete_commit = sde_kms_complete_commit,
  2341. .wait_for_crtc_commit_done = sde_kms_wait_for_commit_done,
  2342. .wait_for_tx_complete = sde_kms_wait_for_frame_transfer_complete,
  2343. .enable_vblank = sde_kms_enable_vblank,
  2344. .disable_vblank = sde_kms_disable_vblank,
  2345. .check_modified_format = sde_format_check_modified_format,
  2346. .atomic_check = sde_kms_atomic_check,
  2347. .get_format = sde_get_msm_format,
  2348. .round_pixclk = sde_kms_round_pixclk,
  2349. .pm_suspend = sde_kms_pm_suspend,
  2350. .pm_resume = sde_kms_pm_resume,
  2351. .destroy = sde_kms_destroy,
  2352. .cont_splash_config = sde_kms_cont_splash_config,
  2353. .register_events = _sde_kms_register_events,
  2354. .get_address_space = _sde_kms_get_address_space,
  2355. .get_address_space_device = _sde_kms_get_address_space_device,
  2356. .postopen = _sde_kms_post_open,
  2357. .check_for_splash = sde_kms_check_for_splash,
  2358. .get_mixer_count = sde_kms_get_mixer_count,
  2359. };
  2360. /* the caller api needs to turn on clock before calling it */
  2361. static inline void _sde_kms_core_hw_rev_init(struct sde_kms *sde_kms)
  2362. {
  2363. sde_kms->core_rev = readl_relaxed(sde_kms->mmio + 0x0);
  2364. }
  2365. static int _sde_kms_mmu_destroy(struct sde_kms *sde_kms)
  2366. {
  2367. int i;
  2368. for (i = ARRAY_SIZE(sde_kms->aspace) - 1; i >= 0; i--) {
  2369. if (!sde_kms->aspace[i])
  2370. continue;
  2371. msm_gem_address_space_put(sde_kms->aspace[i]);
  2372. sde_kms->aspace[i] = NULL;
  2373. }
  2374. return 0;
  2375. }
  2376. static int _sde_kms_mmu_init(struct sde_kms *sde_kms)
  2377. {
  2378. struct msm_mmu *mmu;
  2379. int i, ret;
  2380. int early_map = 0;
  2381. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  2382. struct msm_gem_address_space *aspace;
  2383. mmu = msm_smmu_new(sde_kms->dev->dev, i);
  2384. if (IS_ERR(mmu)) {
  2385. ret = PTR_ERR(mmu);
  2386. SDE_DEBUG("failed to init iommu id %d: rc:%d\n",
  2387. i, ret);
  2388. continue;
  2389. }
  2390. aspace = msm_gem_smmu_address_space_create(sde_kms->dev,
  2391. mmu, "sde");
  2392. if (IS_ERR(aspace)) {
  2393. ret = PTR_ERR(aspace);
  2394. goto fail;
  2395. }
  2396. sde_kms->aspace[i] = aspace;
  2397. aspace->domain_attached = true;
  2398. /* Mapping splash memory block */
  2399. if ((i == MSM_SMMU_DOMAIN_UNSECURE) &&
  2400. sde_kms->splash_data.num_splash_regions) {
  2401. ret = _sde_kms_map_all_splash_regions(sde_kms);
  2402. if (ret) {
  2403. SDE_ERROR("failed to map ret:%d\n", ret);
  2404. goto fail;
  2405. }
  2406. }
  2407. /*
  2408. * disable early-map which would have been enabled during
  2409. * bootup by smmu through the device-tree hint for cont-spash
  2410. */
  2411. ret = mmu->funcs->set_attribute(mmu, DOMAIN_ATTR_EARLY_MAP,
  2412. &early_map);
  2413. if (ret) {
  2414. SDE_ERROR("failed to set_att ret:%d, early_map:%d\n",
  2415. ret, early_map);
  2416. goto early_map_fail;
  2417. }
  2418. }
  2419. return 0;
  2420. early_map_fail:
  2421. _sde_kms_unmap_all_splash_regions(sde_kms);
  2422. fail:
  2423. mmu->funcs->destroy(mmu);
  2424. _sde_kms_mmu_destroy(sde_kms);
  2425. return ret;
  2426. }
  2427. static void sde_kms_init_shared_hw(struct sde_kms *sde_kms)
  2428. {
  2429. if (!sde_kms || !sde_kms->hw_mdp || !sde_kms->catalog)
  2430. return;
  2431. if (sde_kms->hw_mdp->ops.reset_ubwc)
  2432. sde_kms->hw_mdp->ops.reset_ubwc(sde_kms->hw_mdp,
  2433. sde_kms->catalog);
  2434. sde_hw_sid_rotator_set(sde_kms->hw_sid);
  2435. }
  2436. static void _sde_kms_set_lutdma_vbif_remap(struct sde_kms *sde_kms)
  2437. {
  2438. struct sde_vbif_set_qos_params qos_params;
  2439. struct sde_mdss_cfg *catalog;
  2440. if (!sde_kms->catalog)
  2441. return;
  2442. catalog = sde_kms->catalog;
  2443. memset(&qos_params, 0, sizeof(qos_params));
  2444. qos_params.vbif_idx = catalog->dma_cfg.vbif_idx;
  2445. qos_params.xin_id = catalog->dma_cfg.xin_id;
  2446. qos_params.clk_ctrl = catalog->dma_cfg.clk_ctrl;
  2447. qos_params.client_type = VBIF_LUTDMA_CLIENT;
  2448. sde_vbif_set_qos_remap(sde_kms, &qos_params);
  2449. }
  2450. static void sde_kms_handle_power_event(u32 event_type, void *usr)
  2451. {
  2452. struct sde_kms *sde_kms = usr;
  2453. struct msm_kms *msm_kms;
  2454. msm_kms = &sde_kms->base;
  2455. if (!sde_kms)
  2456. return;
  2457. SDE_DEBUG("event_type:%d\n", event_type);
  2458. SDE_EVT32_VERBOSE(event_type);
  2459. if (event_type == SDE_POWER_EVENT_POST_ENABLE) {
  2460. sde_irq_update(msm_kms, true);
  2461. sde_vbif_init_memtypes(sde_kms);
  2462. sde_kms_init_shared_hw(sde_kms);
  2463. _sde_kms_set_lutdma_vbif_remap(sde_kms);
  2464. sde_kms->first_kickoff = true;
  2465. } else if (event_type == SDE_POWER_EVENT_PRE_DISABLE) {
  2466. sde_irq_update(msm_kms, false);
  2467. sde_kms->first_kickoff = false;
  2468. }
  2469. }
  2470. #define genpd_to_sde_kms(domain) container_of(domain, struct sde_kms, genpd)
  2471. static int sde_kms_pd_enable(struct generic_pm_domain *genpd)
  2472. {
  2473. struct sde_kms *sde_kms = genpd_to_sde_kms(genpd);
  2474. int rc = -EINVAL;
  2475. SDE_DEBUG("\n");
  2476. rc = pm_runtime_get_sync(sde_kms->dev->dev);
  2477. if (rc > 0)
  2478. rc = 0;
  2479. SDE_EVT32(rc, genpd->device_count);
  2480. return rc;
  2481. }
  2482. static int sde_kms_pd_disable(struct generic_pm_domain *genpd)
  2483. {
  2484. struct sde_kms *sde_kms = genpd_to_sde_kms(genpd);
  2485. SDE_DEBUG("\n");
  2486. pm_runtime_put_sync(sde_kms->dev->dev);
  2487. SDE_EVT32(genpd->device_count);
  2488. return 0;
  2489. }
  2490. static int _sde_kms_get_splash_data(struct sde_splash_data *data)
  2491. {
  2492. int i = 0;
  2493. int ret = 0;
  2494. struct device_node *parent, *node, *node1;
  2495. struct resource r, r1;
  2496. const char *node_name = "cont_splash_region";
  2497. struct sde_splash_mem *mem;
  2498. bool share_splash_mem = false;
  2499. int num_displays, num_regions;
  2500. struct sde_splash_display *splash_display;
  2501. if (!data)
  2502. return -EINVAL;
  2503. memset(data, 0, sizeof(*data));
  2504. parent = of_find_node_by_path("/reserved-memory");
  2505. if (!parent) {
  2506. SDE_ERROR("failed to find reserved-memory node\n");
  2507. return -EINVAL;
  2508. }
  2509. node = of_find_node_by_name(parent, node_name);
  2510. if (!node) {
  2511. SDE_DEBUG("failed to find node %s\n", node_name);
  2512. return -EINVAL;
  2513. }
  2514. node1 = of_find_node_by_name(parent, "disp_rdump_region");
  2515. if (!node1)
  2516. SDE_DEBUG("failed to find disp ramdump memory reservation\n");
  2517. /**
  2518. * Support sharing a single splash memory for all the built in displays
  2519. * and also independent splash region per displays. Incase of
  2520. * independent splash region for each connected display, dtsi node of
  2521. * cont_splash_region should be collection of all memory regions
  2522. * Ex: <r1.start r1.end r2.start r2.end ... rn.start, rn.end>
  2523. */
  2524. num_displays = dsi_display_get_num_of_displays();
  2525. num_regions = of_property_count_u64_elems(node, "reg") / 2;
  2526. data->num_splash_displays = num_displays;
  2527. SDE_DEBUG("splash mem num_regions:%d\n", num_regions);
  2528. if (num_displays > num_regions) {
  2529. share_splash_mem = true;
  2530. pr_info(":%d displays share same splash buf\n", num_displays);
  2531. }
  2532. for (i = 0; i < num_displays; i++) {
  2533. splash_display = &data->splash_display[i];
  2534. if (!i || !share_splash_mem) {
  2535. if (of_address_to_resource(node, i, &r)) {
  2536. SDE_ERROR("invalid data for:%s\n", node_name);
  2537. return -EINVAL;
  2538. }
  2539. mem = &data->splash_mem[i];
  2540. if (!node1 || of_address_to_resource(node1, i, &r1)) {
  2541. SDE_DEBUG("failed to find ramdump memory\n");
  2542. mem->ramdump_base = 0;
  2543. mem->ramdump_size = 0;
  2544. } else {
  2545. mem->ramdump_base = (unsigned long)r1.start;
  2546. mem->ramdump_size = (r1.end - r1.start) + 1;
  2547. }
  2548. mem->splash_buf_base = (unsigned long)r.start;
  2549. mem->splash_buf_size = (r.end - r.start) + 1;
  2550. mem->ref_cnt = 0;
  2551. splash_display->splash = mem;
  2552. data->num_splash_regions++;
  2553. } else {
  2554. data->splash_display[i].splash = &data->splash_mem[0];
  2555. }
  2556. SDE_DEBUG("splash mem for disp:%d add:%lx size:%x\n", (i + 1),
  2557. splash_display->splash->splash_buf_base,
  2558. splash_display->splash->splash_buf_size);
  2559. }
  2560. return ret;
  2561. }
  2562. static int _sde_kms_hw_init_ioremap(struct sde_kms *sde_kms,
  2563. struct platform_device *platformdev)
  2564. {
  2565. int rc = -EINVAL;
  2566. sde_kms->mmio = msm_ioremap(platformdev, "mdp_phys", "mdp_phys");
  2567. if (IS_ERR(sde_kms->mmio)) {
  2568. rc = PTR_ERR(sde_kms->mmio);
  2569. SDE_ERROR("mdp register memory map failed: %d\n", rc);
  2570. sde_kms->mmio = NULL;
  2571. goto error;
  2572. }
  2573. DRM_INFO("mapped mdp address space @%pK\n", sde_kms->mmio);
  2574. sde_kms->mmio_len = msm_iomap_size(platformdev, "mdp_phys");
  2575. rc = sde_dbg_reg_register_base(SDE_DBG_NAME, sde_kms->mmio,
  2576. sde_kms->mmio_len);
  2577. if (rc)
  2578. SDE_ERROR("dbg base register kms failed: %d\n", rc);
  2579. sde_kms->vbif[VBIF_RT] = msm_ioremap(platformdev, "vbif_phys",
  2580. "vbif_phys");
  2581. if (IS_ERR(sde_kms->vbif[VBIF_RT])) {
  2582. rc = PTR_ERR(sde_kms->vbif[VBIF_RT]);
  2583. SDE_ERROR("vbif register memory map failed: %d\n", rc);
  2584. sde_kms->vbif[VBIF_RT] = NULL;
  2585. goto error;
  2586. }
  2587. sde_kms->vbif_len[VBIF_RT] = msm_iomap_size(platformdev,
  2588. "vbif_phys");
  2589. rc = sde_dbg_reg_register_base("vbif_rt", sde_kms->vbif[VBIF_RT],
  2590. sde_kms->vbif_len[VBIF_RT]);
  2591. if (rc)
  2592. SDE_ERROR("dbg base register vbif_rt failed: %d\n", rc);
  2593. sde_kms->vbif[VBIF_NRT] = msm_ioremap(platformdev, "vbif_nrt_phys",
  2594. "vbif_nrt_phys");
  2595. if (IS_ERR(sde_kms->vbif[VBIF_NRT])) {
  2596. sde_kms->vbif[VBIF_NRT] = NULL;
  2597. SDE_DEBUG("VBIF NRT is not defined");
  2598. } else {
  2599. sde_kms->vbif_len[VBIF_NRT] = msm_iomap_size(platformdev,
  2600. "vbif_nrt_phys");
  2601. rc = sde_dbg_reg_register_base("vbif_nrt",
  2602. sde_kms->vbif[VBIF_NRT],
  2603. sde_kms->vbif_len[VBIF_NRT]);
  2604. if (rc)
  2605. SDE_ERROR("dbg base register vbif_nrt failed: %d\n",
  2606. rc);
  2607. }
  2608. sde_kms->reg_dma = msm_ioremap(platformdev, "regdma_phys",
  2609. "regdma_phys");
  2610. if (IS_ERR(sde_kms->reg_dma)) {
  2611. sde_kms->reg_dma = NULL;
  2612. SDE_DEBUG("REG_DMA is not defined");
  2613. } else {
  2614. sde_kms->reg_dma_len = msm_iomap_size(platformdev,
  2615. "regdma_phys");
  2616. rc = sde_dbg_reg_register_base("reg_dma",
  2617. sde_kms->reg_dma,
  2618. sde_kms->reg_dma_len);
  2619. if (rc)
  2620. SDE_ERROR("dbg base register reg_dma failed: %d\n",
  2621. rc);
  2622. }
  2623. sde_kms->sid = msm_ioremap(platformdev, "sid_phys",
  2624. "sid_phys");
  2625. if (IS_ERR(sde_kms->sid)) {
  2626. rc = PTR_ERR(sde_kms->sid);
  2627. SDE_ERROR("sid register memory map failed: %d\n", rc);
  2628. sde_kms->sid = NULL;
  2629. goto error;
  2630. }
  2631. sde_kms->sid_len = msm_iomap_size(platformdev, "sid_phys");
  2632. rc = sde_dbg_reg_register_base("sid", sde_kms->sid, sde_kms->sid_len);
  2633. if (rc)
  2634. SDE_ERROR("dbg base register sid failed: %d\n", rc);
  2635. sde_kms->sw_fuse = msm_ioremap(platformdev, "swfuse_phys",
  2636. "swfuse_phys");
  2637. if (IS_ERR(sde_kms->sw_fuse)) {
  2638. sde_kms->sw_fuse = NULL;
  2639. SDE_DEBUG("sw_fuse is not defined");
  2640. } else {
  2641. sde_kms->sw_fuse_len = msm_iomap_size(platformdev,
  2642. "swfuse_phys");
  2643. rc = sde_dbg_reg_register_base("sw_fuse", sde_kms->sw_fuse,
  2644. sde_kms->sw_fuse_len);
  2645. if (rc)
  2646. SDE_ERROR("dbg base register sw_fuse failed: %d\n", rc);
  2647. }
  2648. error:
  2649. return rc;
  2650. }
  2651. static int _sde_kms_hw_init_power_helper(struct drm_device *dev,
  2652. struct sde_kms *sde_kms)
  2653. {
  2654. int rc = 0;
  2655. if (of_find_property(dev->dev->of_node, "#power-domain-cells", NULL)) {
  2656. sde_kms->genpd.name = dev->unique;
  2657. sde_kms->genpd.power_off = sde_kms_pd_disable;
  2658. sde_kms->genpd.power_on = sde_kms_pd_enable;
  2659. rc = pm_genpd_init(&sde_kms->genpd, NULL, true);
  2660. if (rc < 0) {
  2661. SDE_ERROR("failed to init genpd provider %s: %d\n",
  2662. sde_kms->genpd.name, rc);
  2663. return rc;
  2664. }
  2665. rc = of_genpd_add_provider_simple(dev->dev->of_node,
  2666. &sde_kms->genpd);
  2667. if (rc < 0) {
  2668. SDE_ERROR("failed to add genpd provider %s: %d\n",
  2669. sde_kms->genpd.name, rc);
  2670. pm_genpd_remove(&sde_kms->genpd);
  2671. return rc;
  2672. }
  2673. sde_kms->genpd_init = true;
  2674. SDE_DEBUG("added genpd provider %s\n", sde_kms->genpd.name);
  2675. }
  2676. return rc;
  2677. }
  2678. static int _sde_kms_hw_init_blocks(struct sde_kms *sde_kms,
  2679. struct drm_device *dev,
  2680. struct msm_drm_private *priv)
  2681. {
  2682. struct sde_rm *rm = NULL;
  2683. int i, rc = -EINVAL;
  2684. for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++)
  2685. sde_power_data_bus_set_quota(&priv->phandle, i,
  2686. SDE_POWER_HANDLE_CONT_SPLASH_BUS_AB_QUOTA,
  2687. SDE_POWER_HANDLE_CONT_SPLASH_BUS_IB_QUOTA);
  2688. _sde_kms_core_hw_rev_init(sde_kms);
  2689. pr_info("sde hardware revision:0x%x\n", sde_kms->core_rev);
  2690. sde_kms->catalog = sde_hw_catalog_init(dev, sde_kms->core_rev);
  2691. if (IS_ERR_OR_NULL(sde_kms->catalog)) {
  2692. rc = PTR_ERR(sde_kms->catalog);
  2693. if (!sde_kms->catalog)
  2694. rc = -EINVAL;
  2695. SDE_ERROR("catalog init failed: %d\n", rc);
  2696. sde_kms->catalog = NULL;
  2697. goto power_error;
  2698. }
  2699. /* initialize power domain if defined */
  2700. rc = _sde_kms_hw_init_power_helper(dev, sde_kms);
  2701. if (rc) {
  2702. SDE_ERROR("_sde_kms_hw_init_power_helper failed: %d\n", rc);
  2703. goto genpd_err;
  2704. }
  2705. rc = _sde_kms_mmu_init(sde_kms);
  2706. if (rc) {
  2707. SDE_ERROR("sde_kms_mmu_init failed: %d\n", rc);
  2708. goto power_error;
  2709. }
  2710. /* Initialize reg dma block which is a singleton */
  2711. rc = sde_reg_dma_init(sde_kms->reg_dma, sde_kms->catalog,
  2712. sde_kms->dev);
  2713. if (rc) {
  2714. SDE_ERROR("failed: reg dma init failed\n");
  2715. goto power_error;
  2716. }
  2717. sde_dbg_init_dbg_buses(sde_kms->core_rev);
  2718. rm = &sde_kms->rm;
  2719. rc = sde_rm_init(rm, sde_kms->catalog, sde_kms->mmio,
  2720. sde_kms->dev);
  2721. if (rc) {
  2722. SDE_ERROR("rm init failed: %d\n", rc);
  2723. goto power_error;
  2724. }
  2725. sde_kms->rm_init = true;
  2726. sde_kms->hw_intr = sde_hw_intr_init(sde_kms->mmio, sde_kms->catalog);
  2727. if (IS_ERR_OR_NULL(sde_kms->hw_intr)) {
  2728. rc = PTR_ERR(sde_kms->hw_intr);
  2729. SDE_ERROR("hw_intr init failed: %d\n", rc);
  2730. sde_kms->hw_intr = NULL;
  2731. goto hw_intr_init_err;
  2732. }
  2733. /*
  2734. * Attempt continuous splash handoff only if reserved
  2735. * splash memory is found & release resources on any error
  2736. * in finding display hw config in splash
  2737. */
  2738. if (sde_kms->splash_data.num_splash_regions) {
  2739. struct sde_splash_display *display;
  2740. int ret, display_count =
  2741. sde_kms->splash_data.num_splash_displays;
  2742. ret = sde_rm_cont_splash_res_init(priv, &sde_kms->rm,
  2743. &sde_kms->splash_data, sde_kms->catalog);
  2744. for (i = 0; i < display_count; i++) {
  2745. display = &sde_kms->splash_data.splash_display[i];
  2746. /*
  2747. * free splash region on resource init failure and
  2748. * cont-splash disabled case
  2749. */
  2750. if (!display->cont_splash_enabled || ret)
  2751. _sde_kms_free_splash_region(sde_kms, display);
  2752. }
  2753. }
  2754. sde_kms->hw_mdp = sde_rm_get_mdp(&sde_kms->rm);
  2755. if (IS_ERR_OR_NULL(sde_kms->hw_mdp)) {
  2756. rc = PTR_ERR(sde_kms->hw_mdp);
  2757. if (!sde_kms->hw_mdp)
  2758. rc = -EINVAL;
  2759. SDE_ERROR("failed to get hw_mdp: %d\n", rc);
  2760. sde_kms->hw_mdp = NULL;
  2761. goto power_error;
  2762. }
  2763. for (i = 0; i < sde_kms->catalog->vbif_count; i++) {
  2764. u32 vbif_idx = sde_kms->catalog->vbif[i].id;
  2765. sde_kms->hw_vbif[i] = sde_hw_vbif_init(vbif_idx,
  2766. sde_kms->vbif[vbif_idx], sde_kms->catalog);
  2767. if (IS_ERR_OR_NULL(sde_kms->hw_vbif[vbif_idx])) {
  2768. rc = PTR_ERR(sde_kms->hw_vbif[vbif_idx]);
  2769. if (!sde_kms->hw_vbif[vbif_idx])
  2770. rc = -EINVAL;
  2771. SDE_ERROR("failed to init vbif %d: %d\n", vbif_idx, rc);
  2772. sde_kms->hw_vbif[vbif_idx] = NULL;
  2773. goto power_error;
  2774. }
  2775. }
  2776. if (sde_kms->catalog->uidle_cfg.uidle_rev) {
  2777. sde_kms->hw_uidle = sde_hw_uidle_init(UIDLE, sde_kms->mmio,
  2778. sde_kms->mmio_len, sde_kms->catalog);
  2779. if (IS_ERR_OR_NULL(sde_kms->hw_uidle)) {
  2780. rc = PTR_ERR(sde_kms->hw_uidle);
  2781. if (!sde_kms->hw_uidle)
  2782. rc = -EINVAL;
  2783. /* uidle is optional, so do not make it a fatal error */
  2784. SDE_ERROR("failed to init uidle rc:%d\n", rc);
  2785. sde_kms->hw_uidle = NULL;
  2786. rc = 0;
  2787. }
  2788. } else {
  2789. sde_kms->hw_uidle = NULL;
  2790. }
  2791. sde_kms->hw_sid = sde_hw_sid_init(sde_kms->sid,
  2792. sde_kms->sid_len, sde_kms->catalog);
  2793. if (IS_ERR(sde_kms->hw_sid)) {
  2794. SDE_ERROR("failed to init sid %ld\n", PTR_ERR(sde_kms->hw_sid));
  2795. sde_kms->hw_sid = NULL;
  2796. goto power_error;
  2797. }
  2798. rc = sde_core_perf_init(&sde_kms->perf, dev, sde_kms->catalog,
  2799. &priv->phandle, "core_clk");
  2800. if (rc) {
  2801. SDE_ERROR("failed to init perf %d\n", rc);
  2802. goto perf_err;
  2803. }
  2804. if (sde_kms->sw_fuse) {
  2805. sde_kms->hw_sw_fuse = sde_hw_sw_fuse_init(sde_kms->sw_fuse,
  2806. sde_kms->sw_fuse_len, sde_kms->catalog);
  2807. if (IS_ERR(sde_kms->hw_sw_fuse)) {
  2808. SDE_ERROR("failed to init sw_fuse %ld\n",
  2809. PTR_ERR(sde_kms->hw_sw_fuse));
  2810. sde_kms->hw_sw_fuse = NULL;
  2811. }
  2812. } else {
  2813. sde_kms->hw_sw_fuse = NULL;
  2814. }
  2815. /*
  2816. * _sde_kms_drm_obj_init should create the DRM related objects
  2817. * i.e. CRTCs, planes, encoders, connectors and so forth
  2818. */
  2819. rc = _sde_kms_drm_obj_init(sde_kms);
  2820. if (rc) {
  2821. SDE_ERROR("modeset init failed: %d\n", rc);
  2822. goto drm_obj_init_err;
  2823. }
  2824. return 0;
  2825. genpd_err:
  2826. drm_obj_init_err:
  2827. sde_core_perf_destroy(&sde_kms->perf);
  2828. hw_intr_init_err:
  2829. perf_err:
  2830. power_error:
  2831. return rc;
  2832. }
  2833. static int sde_kms_hw_init(struct msm_kms *kms)
  2834. {
  2835. struct sde_kms *sde_kms;
  2836. struct drm_device *dev;
  2837. struct msm_drm_private *priv;
  2838. struct platform_device *platformdev;
  2839. int i, rc = -EINVAL;
  2840. if (!kms) {
  2841. SDE_ERROR("invalid kms\n");
  2842. goto end;
  2843. }
  2844. sde_kms = to_sde_kms(kms);
  2845. dev = sde_kms->dev;
  2846. if (!dev || !dev->dev) {
  2847. SDE_ERROR("invalid device\n");
  2848. goto end;
  2849. }
  2850. platformdev = to_platform_device(dev->dev);
  2851. priv = dev->dev_private;
  2852. if (!priv) {
  2853. SDE_ERROR("invalid private data\n");
  2854. goto end;
  2855. }
  2856. rc = _sde_kms_hw_init_ioremap(sde_kms, platformdev);
  2857. if (rc)
  2858. goto error;
  2859. rc = _sde_kms_get_splash_data(&sde_kms->splash_data);
  2860. if (rc)
  2861. SDE_DEBUG("sde splash data fetch failed: %d\n", rc);
  2862. rc = pm_runtime_get_sync(sde_kms->dev->dev);
  2863. if (rc < 0) {
  2864. SDE_ERROR("resource enable failed: %d\n", rc);
  2865. goto error;
  2866. }
  2867. rc = _sde_kms_hw_init_blocks(sde_kms, dev, priv);
  2868. if (rc)
  2869. goto hw_init_err;
  2870. dev->mode_config.min_width = sde_kms->catalog->min_display_width;
  2871. dev->mode_config.min_height = sde_kms->catalog->min_display_height;
  2872. dev->mode_config.max_width = sde_kms->catalog->max_display_width;
  2873. dev->mode_config.max_height = sde_kms->catalog->max_display_height;
  2874. mutex_init(&sde_kms->secure_transition_lock);
  2875. atomic_set(&sde_kms->detach_sec_cb, 0);
  2876. atomic_set(&sde_kms->detach_all_cb, 0);
  2877. /*
  2878. * Support format modifiers for compression etc.
  2879. */
  2880. dev->mode_config.allow_fb_modifiers = true;
  2881. /*
  2882. * Handle (re)initializations during power enable
  2883. */
  2884. sde_kms_handle_power_event(SDE_POWER_EVENT_POST_ENABLE, sde_kms);
  2885. sde_kms->power_event = sde_power_handle_register_event(&priv->phandle,
  2886. SDE_POWER_EVENT_POST_ENABLE |
  2887. SDE_POWER_EVENT_PRE_DISABLE,
  2888. sde_kms_handle_power_event, sde_kms, "kms");
  2889. if (sde_kms->splash_data.num_splash_displays) {
  2890. SDE_DEBUG("Skipping MDP Resources disable\n");
  2891. } else {
  2892. for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++)
  2893. sde_power_data_bus_set_quota(&priv->phandle, i,
  2894. SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA,
  2895. SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA);
  2896. pm_runtime_put_sync(sde_kms->dev->dev);
  2897. }
  2898. return 0;
  2899. hw_init_err:
  2900. pm_runtime_put_sync(sde_kms->dev->dev);
  2901. error:
  2902. _sde_kms_hw_destroy(sde_kms, platformdev);
  2903. end:
  2904. return rc;
  2905. }
  2906. struct msm_kms *sde_kms_init(struct drm_device *dev)
  2907. {
  2908. struct msm_drm_private *priv;
  2909. struct sde_kms *sde_kms;
  2910. if (!dev || !dev->dev_private) {
  2911. SDE_ERROR("drm device node invalid\n");
  2912. return ERR_PTR(-EINVAL);
  2913. }
  2914. priv = dev->dev_private;
  2915. sde_kms = kzalloc(sizeof(*sde_kms), GFP_KERNEL);
  2916. if (!sde_kms) {
  2917. SDE_ERROR("failed to allocate sde kms\n");
  2918. return ERR_PTR(-ENOMEM);
  2919. }
  2920. msm_kms_init(&sde_kms->base, &kms_funcs);
  2921. sde_kms->dev = dev;
  2922. return &sde_kms->base;
  2923. }
  2924. static int _sde_kms_register_events(struct msm_kms *kms,
  2925. struct drm_mode_object *obj, u32 event, bool en)
  2926. {
  2927. int ret = 0;
  2928. struct drm_crtc *crtc = NULL;
  2929. struct drm_connector *conn = NULL;
  2930. struct sde_kms *sde_kms = NULL;
  2931. if (!kms || !obj) {
  2932. SDE_ERROR("invalid argument kms %pK obj %pK\n", kms, obj);
  2933. return -EINVAL;
  2934. }
  2935. sde_kms = to_sde_kms(kms);
  2936. switch (obj->type) {
  2937. case DRM_MODE_OBJECT_CRTC:
  2938. crtc = obj_to_crtc(obj);
  2939. ret = sde_crtc_register_custom_event(sde_kms, crtc, event, en);
  2940. break;
  2941. case DRM_MODE_OBJECT_CONNECTOR:
  2942. conn = obj_to_connector(obj);
  2943. ret = sde_connector_register_custom_event(sde_kms, conn, event,
  2944. en);
  2945. break;
  2946. }
  2947. return ret;
  2948. }
  2949. int sde_kms_handle_recovery(struct drm_encoder *encoder)
  2950. {
  2951. SDE_EVT32(DRMID(encoder), MSM_ENC_ACTIVE_REGION);
  2952. return sde_encoder_wait_for_event(encoder, MSM_ENC_ACTIVE_REGION);
  2953. }