6c483e3b23
Adding debug, info and error prefix for log messages in dsi files. To enable debug logs run "echo 0x1 > /sys/module/drm/parameters/debug" Change-Id: I438ac16954bd1d39450f8adeb7fb17f9ea6f8140 Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
302 líneas
9.5 KiB
C
302 líneas
9.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.
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*/
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#include <linux/math64.h>
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#include <linux/delay.h>
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#include "dsi_hw.h"
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#include "dsi_phy_hw.h"
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#define DSIPHY_CMN_REVISION_ID0 0x0000
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#define DSIPHY_CMN_REVISION_ID1 0x0004
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#define DSIPHY_CMN_REVISION_ID2 0x0008
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#define DSIPHY_CMN_REVISION_ID3 0x000C
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#define DSIPHY_CMN_CLK_CFG0 0x0010
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#define DSIPHY_CMN_CLK_CFG1 0x0014
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#define DSIPHY_CMN_GLBL_TEST_CTRL 0x0018
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#define DSIPHY_CMN_CTRL_0 0x001C
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#define DSIPHY_CMN_CTRL_1 0x0020
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#define DSIPHY_CMN_CAL_HW_TRIGGER 0x0024
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#define DSIPHY_CMN_CAL_SW_CFG0 0x0028
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#define DSIPHY_CMN_CAL_SW_CFG1 0x002C
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#define DSIPHY_CMN_CAL_SW_CFG2 0x0030
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#define DSIPHY_CMN_CAL_HW_CFG0 0x0034
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#define DSIPHY_CMN_CAL_HW_CFG1 0x0038
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#define DSIPHY_CMN_CAL_HW_CFG2 0x003C
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#define DSIPHY_CMN_CAL_HW_CFG3 0x0040
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#define DSIPHY_CMN_CAL_HW_CFG4 0x0044
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#define DSIPHY_CMN_PLL_CNTRL 0x0048
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#define DSIPHY_CMN_LDO_CNTRL 0x004C
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#define DSIPHY_CMN_REGULATOR_CAL_STATUS0 0x0064
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#define DSIPHY_CMN_REGULATOR_CAL_STATUS1 0x0068
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#define DSI_MDP_ULPS_CLAMP_ENABLE_OFF 0x0054
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/* n = 0..3 for data lanes and n = 4 for clock lane
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* t for count per lane
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*/
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#define DSIPHY_DLNX_CFG(n, t) \
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(0x100 + ((t) * 0x04) + ((n) * 0x80))
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#define DSIPHY_DLNX_TIMING_CTRL(n, t) \
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(0x118 + ((t) * 0x04) + ((n) * 0x80))
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#define DSIPHY_DLNX_STRENGTH_CTRL(n, t) \
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(0x138 + ((t) * 0x04) + ((n) * 0x80))
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#define DSIPHY_DLNX_TEST_DATAPATH(n) (0x110 + ((n) * 0x80))
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#define DSIPHY_DLNX_TEST_STR(n) (0x114 + ((n) * 0x80))
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#define DSIPHY_DLNX_BIST_POLY(n) (0x140 + ((n) * 0x80))
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#define DSIPHY_DLNX_BIST_SEED0(n) (0x144 + ((n) * 0x80))
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#define DSIPHY_DLNX_BIST_SEED1(n) (0x148 + ((n) * 0x80))
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#define DSIPHY_DLNX_BIST_HEAD(n) (0x14C + ((n) * 0x80))
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#define DSIPHY_DLNX_BIST_SOT(n) (0x150 + ((n) * 0x80))
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#define DSIPHY_DLNX_BIST_CTRL0(n) (0x154 + ((n) * 0x80))
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#define DSIPHY_DLNX_BIST_CTRL1(n) (0x158 + ((n) * 0x80))
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#define DSIPHY_DLNX_BIST_CTRL2(n) (0x15C + ((n) * 0x80))
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#define DSIPHY_DLNX_BIST_CTRL3(n) (0x160 + ((n) * 0x80))
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#define DSIPHY_DLNX_VREG_CNTRL(n) (0x164 + ((n) * 0x80))
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#define DSIPHY_DLNX_HSTX_STR_STATUS(n) (0x168 + ((n) * 0x80))
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#define DSIPHY_DLNX_BIST_STATUS0(n) (0x16C + ((n) * 0x80))
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#define DSIPHY_DLNX_BIST_STATUS1(n) (0x170 + ((n) * 0x80))
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#define DSIPHY_DLNX_BIST_STATUS2(n) (0x174 + ((n) * 0x80))
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#define DSIPHY_DLNX_BIST_STATUS3(n) (0x178 + ((n) * 0x80))
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#define DSIPHY_DLNX_MISR_STATUS(n) (0x17C + ((n) * 0x80))
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#define DSIPHY_PLL_CLKBUFLR_EN 0x041C
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#define DSIPHY_PLL_PLL_BANDGAP 0x0508
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/**
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* regulator_enable() - enable regulators for DSI PHY
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* @phy: Pointer to DSI PHY hardware object.
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* @reg_cfg: Regulator configuration for all DSI lanes.
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*/
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void dsi_phy_hw_v2_0_regulator_enable(struct dsi_phy_hw *phy,
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struct dsi_phy_per_lane_cfgs *reg_cfg)
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{
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int i;
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bool is_split_link = test_bit(DSI_PHY_SPLIT_LINK, phy->feature_map);
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for (i = DSI_LOGICAL_LANE_0; i < DSI_LANE_MAX; i++)
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DSI_W32(phy, DSIPHY_DLNX_VREG_CNTRL(i), reg_cfg->lane[i][0]);
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if (is_split_link)
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DSI_W32(phy, DSIPHY_DLNX_VREG_CNTRL(DSI_LOGICAL_CLOCK_LANE+1),
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reg_cfg->lane[DSI_LOGICAL_CLOCK_LANE][0]);
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/* make sure all values are written to hardware */
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wmb();
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DSI_PHY_DBG(phy, "Phy regulators enabled\n");
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}
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/**
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* regulator_disable() - disable regulators
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* @phy: Pointer to DSI PHY hardware object.
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*/
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void dsi_phy_hw_v2_0_regulator_disable(struct dsi_phy_hw *phy)
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{
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DSI_PHY_DBG(phy, "Phy regulators disabled\n");
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}
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/**
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* enable() - Enable PHY hardware
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* @phy: Pointer to DSI PHY hardware object.
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* @cfg: Per lane configurations for timing, strength and lane
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* configurations.
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*/
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void dsi_phy_hw_v2_0_enable(struct dsi_phy_hw *phy,
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struct dsi_phy_cfg *cfg)
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{
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int i, j;
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struct dsi_phy_per_lane_cfgs *lanecfg = &cfg->lanecfg;
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struct dsi_phy_per_lane_cfgs *timing = &cfg->timing;
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struct dsi_phy_per_lane_cfgs *strength = &cfg->strength;
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u32 data;
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bool is_split_link = test_bit(DSI_PHY_SPLIT_LINK, phy->feature_map);
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DSI_W32(phy, DSIPHY_CMN_LDO_CNTRL, 0x1C);
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DSI_W32(phy, DSIPHY_CMN_GLBL_TEST_CTRL, 0x1);
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for (i = DSI_LOGICAL_LANE_0; i < DSI_LANE_MAX; i++) {
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for (j = 0; j < lanecfg->count_per_lane; j++)
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DSI_W32(phy, DSIPHY_DLNX_CFG(i, j),
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lanecfg->lane[i][j]);
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DSI_W32(phy, DSIPHY_DLNX_TEST_STR(i), 0x88);
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for (j = 0; j < timing->count_per_lane; j++)
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DSI_W32(phy, DSIPHY_DLNX_TIMING_CTRL(i, j),
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timing->lane[i][j]);
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for (j = 0; j < strength->count_per_lane; j++)
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DSI_W32(phy, DSIPHY_DLNX_STRENGTH_CTRL(i, j),
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strength->lane[i][j]);
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}
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if (is_split_link) {
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i = DSI_LOGICAL_CLOCK_LANE;
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for (j = 0; j < lanecfg->count_per_lane; j++)
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DSI_W32(phy, DSIPHY_DLNX_CFG(i+1, j),
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lanecfg->lane[i][j]);
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DSI_W32(phy, DSIPHY_DLNX_TEST_STR(i+1), 0x0);
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DSI_W32(phy, DSIPHY_DLNX_TEST_DATAPATH(i+1), 0x88);
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for (j = 0; j < timing->count_per_lane; j++)
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DSI_W32(phy, DSIPHY_DLNX_TIMING_CTRL(i+1, j),
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timing->lane[i][j]);
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for (j = 0; j < strength->count_per_lane; j++)
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DSI_W32(phy, DSIPHY_DLNX_STRENGTH_CTRL(i+1, j),
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strength->lane[i][j]);
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/* enable split link for cmn clk cfg1 */
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data = DSI_R32(phy, DSIPHY_CMN_CLK_CFG1);
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data |= BIT(1);
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DSI_W32(phy, DSIPHY_CMN_CLK_CFG1, data);
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}
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/* make sure all values are written to hardware before enabling phy */
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wmb();
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DSI_W32(phy, DSIPHY_CMN_CTRL_1, 0x80);
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udelay(100);
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DSI_W32(phy, DSIPHY_CMN_CTRL_1, 0x00);
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data = DSI_R32(phy, DSIPHY_CMN_GLBL_TEST_CTRL);
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switch (cfg->pll_source) {
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case DSI_PLL_SOURCE_STANDALONE:
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DSI_W32(phy, DSIPHY_PLL_CLKBUFLR_EN, 0x01);
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data &= ~BIT(2);
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break;
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case DSI_PLL_SOURCE_NATIVE:
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DSI_W32(phy, DSIPHY_PLL_CLKBUFLR_EN, 0x03);
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data &= ~BIT(2);
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break;
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case DSI_PLL_SOURCE_NON_NATIVE:
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DSI_W32(phy, DSIPHY_PLL_CLKBUFLR_EN, 0x00);
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data |= BIT(2);
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break;
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default:
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break;
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}
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DSI_W32(phy, DSIPHY_CMN_GLBL_TEST_CTRL, data);
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/* Enable bias current for pll1 during split display case */
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if (cfg->pll_source == DSI_PLL_SOURCE_NON_NATIVE)
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DSI_W32(phy, DSIPHY_PLL_PLL_BANDGAP, 0x3);
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DSI_PHY_DBG(phy, "Phy enabled\n");
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}
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/**
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* disable() - Disable PHY hardware
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* @phy: Pointer to DSI PHY hardware object.
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*/
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void dsi_phy_hw_v2_0_disable(struct dsi_phy_hw *phy,
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struct dsi_phy_cfg *cfg)
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{
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DSI_W32(phy, DSIPHY_PLL_CLKBUFLR_EN, 0);
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DSI_W32(phy, DSIPHY_CMN_GLBL_TEST_CTRL, 0);
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DSI_W32(phy, DSIPHY_CMN_CTRL_0, 0);
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DSI_PHY_DBG(phy, "Phy disabled\n");
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}
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/**
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* dsi_phy_hw_v2_0_idle_on() - Enable DSI PHY hardware during idle screen
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* @phy: Pointer to DSI PHY hardware object.
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*/
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void dsi_phy_hw_v2_0_idle_on(struct dsi_phy_hw *phy, struct dsi_phy_cfg *cfg)
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{
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int i = 0, j;
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struct dsi_phy_per_lane_cfgs *strength = &cfg->strength;
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bool is_split_link = test_bit(DSI_PHY_SPLIT_LINK, phy->feature_map);
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for (i = DSI_LOGICAL_LANE_0; i < DSI_LANE_MAX; i++) {
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for (j = 0; j < strength->count_per_lane; j++)
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DSI_W32(phy, DSIPHY_DLNX_STRENGTH_CTRL(i, j),
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strength->lane[i][j]);
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}
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if (is_split_link) {
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i = DSI_LOGICAL_CLOCK_LANE;
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for (j = 0; j < strength->count_per_lane; j++)
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DSI_W32(phy, DSIPHY_DLNX_STRENGTH_CTRL(i+1, j),
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strength->lane[i][j]);
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}
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wmb(); /* make sure write happens */
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DSI_PHY_DBG(phy, "Phy enabled out of idle screen\n");
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}
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/**
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* dsi_phy_hw_v2_0_idle_off() - Disable DSI PHY hardware during idle screen
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* @phy: Pointer to DSI PHY hardware object.
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*/
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void dsi_phy_hw_v2_0_idle_off(struct dsi_phy_hw *phy)
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{
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int i = 0;
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bool is_split_link = test_bit(DSI_PHY_SPLIT_LINK, phy->feature_map);
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DSI_W32(phy, DSIPHY_CMN_CTRL_0, 0x7f);
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for (i = DSI_LOGICAL_LANE_0; i < DSI_LANE_MAX; i++)
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DSI_W32(phy, DSIPHY_DLNX_VREG_CNTRL(i), 0x1c);
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if (is_split_link)
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DSI_W32(phy, DSIPHY_DLNX_VREG_CNTRL(DSI_LOGICAL_CLOCK_LANE+1),
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0x1c);
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DSI_W32(phy, DSIPHY_CMN_LDO_CNTRL, 0x1C);
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for (i = DSI_LOGICAL_LANE_0; i < DSI_LANE_MAX; i++)
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DSI_W32(phy, DSIPHY_DLNX_STRENGTH_CTRL(i, 1), 0x0);
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if (is_split_link)
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DSI_W32(phy,
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DSIPHY_DLNX_STRENGTH_CTRL(DSI_LOGICAL_CLOCK_LANE+1, 1), 0x0);
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wmb(); /* make sure write happens */
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DSI_PHY_DBG(phy, "Phy disabled during idle screen\n");
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}
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int dsi_phy_hw_timing_val_v2_0(struct dsi_phy_per_lane_cfgs *timing_cfg,
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u32 *timing_val, u32 size)
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{
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int i = 0, j = 0;
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if (size != (DSI_LANE_MAX * DSI_MAX_SETTINGS)) {
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DSI_ERR("Unexpected timing array size %d\n", size);
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return -EINVAL;
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}
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for (i = DSI_LOGICAL_LANE_0; i < DSI_LANE_MAX; i++) {
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for (j = 0; j < DSI_MAX_SETTINGS; j++) {
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timing_cfg->lane[i][j] = *timing_val;
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timing_val++;
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}
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}
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return 0;
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}
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void dsi_phy_hw_v2_0_clamp_ctrl(struct dsi_phy_hw *phy, bool enable)
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{
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u32 clamp_reg = 0;
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if (!phy->phy_clamp_base) {
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DSI_PHY_DBG(phy, "phy_clamp_base NULL\n");
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return;
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}
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if (enable) {
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clamp_reg |= BIT(0);
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DSI_MISC_W32(phy, DSI_MDP_ULPS_CLAMP_ENABLE_OFF,
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clamp_reg);
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DSI_PHY_DBG(phy, "clamp enabled\n");
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} else {
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clamp_reg &= ~BIT(0);
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DSI_MISC_W32(phy, DSI_MDP_ULPS_CLAMP_ENABLE_OFF,
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clamp_reg);
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DSI_PHY_DBG(phy, "clamp disabled\n");
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}
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}
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