dsi_display.c 209 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788278927902791279227932794279527962797279827992800280128022803280428052806280728082809281028112812281328142815281628172818281928202821282228232824282528262827282828292830283128322833283428352836283728382839284028412842284328442845284628472848284928502851285228532854285528562857285828592860286128622863286428652866286728682869287028712872287328742875287628772878287928802881288228832884288528862887288828892890289128922893289428952896289728982899290029012902290329042905290629072908290929102911291229132914291529162917291829192920292129222923292429252926292729282929293029312932293329342935293629372938293929402941294229432944294529462947294829492950295129522953295429552956295729582959296029612962296329642965296629672968296929702971297229732974297529762977297829792980298129822983298429852986298729882989299029912992299329942995299629972998299930003001300230033004300530063007300830093010301130123013301430153016301730183019302030213022302330243025302630273028302930303031303230333034303530363037303830393040304130423043304430453046304730483049305030513052305330543055305630573058305930603061306230633064306530663067306830693070307130723073307430753076307730783079308030813082308330843085308630873088308930903091309230933094309530963097309830993100310131023103310431053106310731083109311031113112311331143115311631173118311931203121312231233124312531263127312831293130313131323133313431353136313731383139314031413142314331443145314631473148314931503151315231533154315531563157315831593160316131623163316431653166316731683169317031713172317331743175317631773178317931803181318231833184318531863187318831893190319131923193319431953196319731983199320032013202320332043205320632073208320932103211321232133214321532163217321832193220322132223223322432253226322732283229323032313232323332343235323632373238323932403241324232433244324532463247324832493250325132523253325432553256325732583259326032613262326332643265326632673268326932703271327232733274327532763277327832793280328132823283328432853286328732883289329032913292329332943295329632973298329933003301330233033304330533063307330833093310331133123313331433153316331733183319332033213322332333243325332633273328332933303331333233333334333533363337333833393340334133423343334433453346334733483349335033513352335333543355335633573358335933603361336233633364336533663367336833693370337133723373337433753376337733783379338033813382338333843385338633873388338933903391339233933394339533963397339833993400340134023403340434053406340734083409341034113412341334143415341634173418341934203421342234233424342534263427342834293430343134323433343434353436343734383439344034413442344334443445344634473448344934503451345234533454345534563457345834593460346134623463346434653466346734683469347034713472347334743475347634773478347934803481348234833484348534863487348834893490349134923493349434953496349734983499350035013502350335043505350635073508350935103511351235133514351535163517351835193520352135223523352435253526352735283529353035313532353335343535353635373538353935403541354235433544354535463547354835493550355135523553355435553556355735583559356035613562356335643565356635673568356935703571357235733574357535763577357835793580358135823583358435853586358735883589359035913592359335943595359635973598359936003601360236033604360536063607360836093610361136123613361436153616361736183619362036213622362336243625362636273628362936303631363236333634363536363637363836393640364136423643364436453646364736483649365036513652365336543655365636573658365936603661366236633664366536663667366836693670367136723673367436753676367736783679368036813682368336843685368636873688368936903691369236933694369536963697369836993700370137023703370437053706370737083709371037113712371337143715371637173718371937203721372237233724372537263727372837293730373137323733373437353736373737383739374037413742374337443745374637473748374937503751375237533754375537563757375837593760376137623763376437653766376737683769377037713772377337743775377637773778377937803781378237833784378537863787378837893790379137923793379437953796379737983799380038013802380338043805380638073808380938103811381238133814381538163817381838193820382138223823382438253826382738283829383038313832383338343835383638373838383938403841384238433844384538463847384838493850385138523853385438553856385738583859386038613862386338643865386638673868386938703871387238733874387538763877387838793880388138823883388438853886388738883889389038913892389338943895389638973898389939003901390239033904390539063907390839093910391139123913391439153916391739183919392039213922392339243925392639273928392939303931393239333934393539363937393839393940394139423943394439453946394739483949395039513952395339543955395639573958395939603961396239633964396539663967396839693970397139723973397439753976397739783979398039813982398339843985398639873988398939903991399239933994399539963997399839994000400140024003400440054006400740084009401040114012401340144015401640174018401940204021402240234024402540264027402840294030403140324033403440354036403740384039404040414042404340444045404640474048404940504051405240534054405540564057405840594060406140624063406440654066406740684069407040714072407340744075407640774078407940804081408240834084408540864087408840894090409140924093409440954096409740984099410041014102410341044105410641074108410941104111411241134114411541164117411841194120412141224123412441254126412741284129413041314132413341344135413641374138413941404141414241434144414541464147414841494150415141524153415441554156415741584159416041614162416341644165416641674168416941704171417241734174417541764177417841794180418141824183418441854186418741884189419041914192419341944195419641974198419942004201420242034204420542064207420842094210421142124213421442154216421742184219422042214222422342244225422642274228422942304231423242334234423542364237423842394240424142424243424442454246424742484249425042514252425342544255425642574258425942604261426242634264426542664267426842694270427142724273427442754276427742784279428042814282428342844285428642874288428942904291429242934294429542964297429842994300430143024303430443054306430743084309431043114312431343144315431643174318431943204321432243234324432543264327432843294330433143324333433443354336433743384339434043414342434343444345434643474348434943504351435243534354435543564357435843594360436143624363436443654366436743684369437043714372437343744375437643774378437943804381438243834384438543864387438843894390439143924393439443954396439743984399440044014402440344044405440644074408440944104411441244134414441544164417441844194420442144224423442444254426442744284429443044314432443344344435443644374438443944404441444244434444444544464447444844494450445144524453445444554456445744584459446044614462446344644465446644674468446944704471447244734474447544764477447844794480448144824483448444854486448744884489449044914492449344944495449644974498449945004501450245034504450545064507450845094510451145124513451445154516451745184519452045214522452345244525452645274528452945304531453245334534453545364537453845394540454145424543454445454546454745484549455045514552455345544555455645574558455945604561456245634564456545664567456845694570457145724573457445754576457745784579458045814582458345844585458645874588458945904591459245934594459545964597459845994600460146024603460446054606460746084609461046114612461346144615461646174618461946204621462246234624462546264627462846294630463146324633463446354636463746384639464046414642464346444645464646474648464946504651465246534654465546564657465846594660466146624663466446654666466746684669467046714672467346744675467646774678467946804681468246834684468546864687468846894690469146924693469446954696469746984699470047014702470347044705470647074708470947104711471247134714471547164717471847194720472147224723472447254726472747284729473047314732473347344735473647374738473947404741474247434744474547464747474847494750475147524753475447554756475747584759476047614762476347644765476647674768476947704771477247734774477547764777477847794780478147824783478447854786478747884789479047914792479347944795479647974798479948004801480248034804480548064807480848094810481148124813481448154816481748184819482048214822482348244825482648274828482948304831483248334834483548364837483848394840484148424843484448454846484748484849485048514852485348544855485648574858485948604861486248634864486548664867486848694870487148724873487448754876487748784879488048814882488348844885488648874888488948904891489248934894489548964897489848994900490149024903490449054906490749084909491049114912491349144915491649174918491949204921492249234924492549264927492849294930493149324933493449354936493749384939494049414942494349444945494649474948494949504951495249534954495549564957495849594960496149624963496449654966496749684969497049714972497349744975497649774978497949804981498249834984498549864987498849894990499149924993499449954996499749984999500050015002500350045005500650075008500950105011501250135014501550165017501850195020502150225023502450255026502750285029503050315032503350345035503650375038503950405041504250435044504550465047504850495050505150525053505450555056505750585059506050615062506350645065506650675068506950705071507250735074507550765077507850795080508150825083508450855086508750885089509050915092509350945095509650975098509951005101510251035104510551065107510851095110511151125113511451155116511751185119512051215122512351245125512651275128512951305131513251335134513551365137513851395140514151425143514451455146514751485149515051515152515351545155515651575158515951605161516251635164516551665167516851695170517151725173517451755176517751785179518051815182518351845185518651875188518951905191519251935194519551965197519851995200520152025203520452055206520752085209521052115212521352145215521652175218521952205221522252235224522552265227522852295230523152325233523452355236523752385239524052415242524352445245524652475248524952505251525252535254525552565257525852595260526152625263526452655266526752685269527052715272527352745275527652775278527952805281528252835284528552865287528852895290529152925293529452955296529752985299530053015302530353045305530653075308530953105311531253135314531553165317531853195320532153225323532453255326532753285329533053315332533353345335533653375338533953405341534253435344534553465347534853495350535153525353535453555356535753585359536053615362536353645365536653675368536953705371537253735374537553765377537853795380538153825383538453855386538753885389539053915392539353945395539653975398539954005401540254035404540554065407540854095410541154125413541454155416541754185419542054215422542354245425542654275428542954305431543254335434543554365437543854395440544154425443544454455446544754485449545054515452545354545455545654575458545954605461546254635464546554665467546854695470547154725473547454755476547754785479548054815482548354845485548654875488548954905491549254935494549554965497549854995500550155025503550455055506550755085509551055115512551355145515551655175518551955205521552255235524552555265527552855295530553155325533553455355536553755385539554055415542554355445545554655475548554955505551555255535554555555565557555855595560556155625563556455655566556755685569557055715572557355745575557655775578557955805581558255835584558555865587558855895590559155925593559455955596559755985599560056015602560356045605560656075608560956105611561256135614561556165617561856195620562156225623562456255626562756285629563056315632563356345635563656375638563956405641564256435644564556465647564856495650565156525653565456555656565756585659566056615662566356645665566656675668566956705671567256735674567556765677567856795680568156825683568456855686568756885689569056915692569356945695569656975698569957005701570257035704570557065707570857095710571157125713571457155716571757185719572057215722572357245725572657275728572957305731573257335734573557365737573857395740574157425743574457455746574757485749575057515752575357545755575657575758575957605761576257635764576557665767576857695770577157725773577457755776577757785779578057815782578357845785578657875788578957905791579257935794579557965797579857995800580158025803580458055806580758085809581058115812581358145815581658175818581958205821582258235824582558265827582858295830583158325833583458355836583758385839584058415842584358445845584658475848584958505851585258535854585558565857585858595860586158625863586458655866586758685869587058715872587358745875587658775878587958805881588258835884588558865887588858895890589158925893589458955896589758985899590059015902590359045905590659075908590959105911591259135914591559165917591859195920592159225923592459255926592759285929593059315932593359345935593659375938593959405941594259435944594559465947594859495950595159525953595459555956595759585959596059615962596359645965596659675968596959705971597259735974597559765977597859795980598159825983598459855986598759885989599059915992599359945995599659975998599960006001600260036004600560066007600860096010601160126013601460156016601760186019602060216022602360246025602660276028602960306031603260336034603560366037603860396040604160426043604460456046604760486049605060516052605360546055605660576058605960606061606260636064606560666067606860696070607160726073607460756076607760786079608060816082608360846085608660876088608960906091609260936094609560966097609860996100610161026103610461056106610761086109611061116112611361146115611661176118611961206121612261236124612561266127612861296130613161326133613461356136613761386139614061416142614361446145614661476148614961506151615261536154615561566157615861596160616161626163616461656166616761686169617061716172617361746175617661776178617961806181618261836184618561866187618861896190619161926193619461956196619761986199620062016202620362046205620662076208620962106211621262136214621562166217621862196220622162226223622462256226622762286229623062316232623362346235623662376238623962406241624262436244624562466247624862496250625162526253625462556256625762586259626062616262626362646265626662676268626962706271627262736274627562766277627862796280628162826283628462856286628762886289629062916292629362946295629662976298629963006301630263036304630563066307630863096310631163126313631463156316631763186319632063216322632363246325632663276328632963306331633263336334633563366337633863396340634163426343634463456346634763486349635063516352635363546355635663576358635963606361636263636364636563666367636863696370637163726373637463756376637763786379638063816382638363846385638663876388638963906391639263936394639563966397639863996400640164026403640464056406640764086409641064116412641364146415641664176418641964206421642264236424642564266427642864296430643164326433643464356436643764386439644064416442644364446445644664476448644964506451645264536454645564566457645864596460646164626463646464656466646764686469647064716472647364746475647664776478647964806481648264836484648564866487648864896490649164926493649464956496649764986499650065016502650365046505650665076508650965106511651265136514651565166517651865196520652165226523652465256526652765286529653065316532653365346535653665376538653965406541654265436544654565466547654865496550655165526553655465556556655765586559656065616562656365646565656665676568656965706571657265736574657565766577657865796580658165826583658465856586658765886589659065916592659365946595659665976598659966006601660266036604660566066607660866096610661166126613661466156616661766186619662066216622662366246625662666276628662966306631663266336634663566366637663866396640664166426643664466456646664766486649665066516652665366546655665666576658665966606661666266636664666566666667666866696670667166726673667466756676667766786679668066816682668366846685668666876688668966906691669266936694669566966697669866996700670167026703670467056706670767086709671067116712671367146715671667176718671967206721672267236724672567266727672867296730673167326733673467356736673767386739674067416742674367446745674667476748674967506751675267536754675567566757675867596760676167626763676467656766676767686769677067716772677367746775677667776778677967806781678267836784678567866787678867896790679167926793679467956796679767986799680068016802680368046805680668076808680968106811681268136814681568166817681868196820682168226823682468256826682768286829683068316832683368346835683668376838683968406841684268436844684568466847684868496850685168526853685468556856685768586859686068616862686368646865686668676868686968706871687268736874687568766877687868796880688168826883688468856886688768886889689068916892689368946895689668976898689969006901690269036904690569066907690869096910691169126913691469156916691769186919692069216922692369246925692669276928692969306931693269336934693569366937693869396940694169426943694469456946694769486949695069516952695369546955695669576958695969606961696269636964696569666967696869696970697169726973697469756976697769786979698069816982698369846985698669876988698969906991699269936994699569966997699869997000700170027003700470057006700770087009701070117012701370147015701670177018701970207021702270237024702570267027702870297030703170327033703470357036703770387039704070417042704370447045704670477048704970507051705270537054705570567057705870597060706170627063706470657066706770687069707070717072707370747075707670777078707970807081708270837084708570867087708870897090709170927093709470957096709770987099710071017102710371047105710671077108710971107111711271137114711571167117711871197120712171227123712471257126712771287129713071317132713371347135713671377138713971407141714271437144714571467147714871497150715171527153715471557156715771587159716071617162716371647165716671677168716971707171717271737174717571767177717871797180718171827183718471857186718771887189719071917192719371947195719671977198719972007201720272037204720572067207720872097210721172127213721472157216721772187219722072217222722372247225722672277228722972307231723272337234723572367237723872397240724172427243724472457246724772487249725072517252725372547255725672577258725972607261726272637264726572667267726872697270727172727273727472757276727772787279728072817282728372847285728672877288728972907291729272937294729572967297729872997300730173027303730473057306730773087309731073117312731373147315731673177318731973207321732273237324732573267327732873297330733173327333733473357336733773387339734073417342734373447345734673477348734973507351735273537354735573567357735873597360736173627363736473657366736773687369737073717372737373747375737673777378737973807381738273837384738573867387738873897390739173927393739473957396739773987399740074017402740374047405740674077408740974107411741274137414741574167417741874197420742174227423742474257426742774287429743074317432743374347435743674377438743974407441744274437444744574467447744874497450745174527453745474557456745774587459746074617462746374647465746674677468746974707471747274737474747574767477747874797480748174827483748474857486748774887489749074917492749374947495749674977498749975007501750275037504750575067507750875097510751175127513751475157516751775187519752075217522752375247525752675277528752975307531753275337534753575367537753875397540754175427543754475457546754775487549755075517552755375547555755675577558755975607561756275637564756575667567756875697570757175727573757475757576757775787579758075817582758375847585758675877588758975907591759275937594759575967597759875997600760176027603760476057606760776087609761076117612761376147615761676177618761976207621762276237624762576267627762876297630763176327633763476357636763776387639764076417642764376447645764676477648764976507651765276537654765576567657765876597660766176627663766476657666766776687669767076717672767376747675767676777678767976807681768276837684768576867687768876897690769176927693769476957696769776987699770077017702770377047705770677077708770977107711771277137714771577167717771877197720772177227723772477257726772777287729773077317732773377347735773677377738773977407741774277437744774577467747774877497750775177527753775477557756775777587759776077617762776377647765776677677768776977707771777277737774777577767777777877797780778177827783778477857786778777887789779077917792779377947795779677977798779978007801780278037804780578067807780878097810781178127813781478157816781778187819782078217822782378247825782678277828782978307831783278337834783578367837783878397840784178427843784478457846784778487849785078517852785378547855785678577858785978607861786278637864786578667867786878697870787178727873787478757876787778787879788078817882788378847885788678877888788978907891789278937894789578967897789878997900790179027903790479057906790779087909791079117912791379147915791679177918791979207921792279237924792579267927792879297930793179327933793479357936793779387939794079417942794379447945794679477948794979507951795279537954795579567957795879597960796179627963796479657966796779687969797079717972797379747975797679777978797979807981798279837984798579867987798879897990799179927993799479957996799779987999800080018002800380048005800680078008800980108011801280138014801580168017801880198020802180228023802480258026802780288029803080318032803380348035803680378038803980408041804280438044804580468047804880498050805180528053805480558056805780588059806080618062806380648065806680678068806980708071807280738074807580768077807880798080808180828083808480858086808780888089809080918092809380948095809680978098809981008101810281038104810581068107810881098110811181128113811481158116811781188119812081218122812381248125812681278128812981308131813281338134813581368137813881398140814181428143814481458146814781488149815081518152815381548155815681578158815981608161816281638164816581668167816881698170817181728173817481758176817781788179818081818182818381848185818681878188818981908191819281938194819581968197819881998200820182028203820482058206820782088209821082118212821382148215821682178218821982208221822282238224822582268227822882298230823182328233823482358236823782388239824082418242824382448245824682478248824982508251825282538254825582568257825882598260826182628263826482658266826782688269827082718272827382748275827682778278827982808281828282838284828582868287828882898290829182928293829482958296829782988299830083018302830383048305830683078308830983108311831283138314831583168317831883198320832183228323832483258326832783288329833083318332833383348335833683378338833983408341834283438344834583468347834883498350835183528353835483558356835783588359836083618362836383648365836683678368836983708371837283738374837583768377837883798380838183828383838483858386838783888389839083918392839383948395839683978398839984008401840284038404840584068407840884098410841184128413841484158416841784188419842084218422842384248425842684278428842984308431843284338434843584368437843884398440844184428443844484458446844784488449845084518452845384548455845684578458845984608461846284638464846584668467846884698470847184728473847484758476
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/list.h>
  6. #include <linux/of.h>
  7. #include <linux/of_gpio.h>
  8. #include <linux/err.h>
  9. #include "msm_drv.h"
  10. #include "sde_connector.h"
  11. #include "msm_mmu.h"
  12. #include "dsi_display.h"
  13. #include "dsi_panel.h"
  14. #include "dsi_ctrl.h"
  15. #include "dsi_ctrl_hw.h"
  16. #include "dsi_drm.h"
  17. #include "dsi_clk.h"
  18. #include "dsi_pwr.h"
  19. #include "sde_dbg.h"
  20. #include "dsi_parser.h"
  21. #define to_dsi_display(x) container_of(x, struct dsi_display, host)
  22. #define INT_BASE_10 10
  23. #define MISR_BUFF_SIZE 256
  24. #define ESD_MODE_STRING_MAX_LEN 256
  25. #define ESD_TRIGGER_STRING_MAX_LEN 10
  26. #define MAX_NAME_SIZE 64
  27. #define MAX_TE_RECHECKS 5
  28. #define DSI_CLOCK_BITRATE_RADIX 10
  29. #define MAX_TE_SOURCE_ID 2
  30. #define SEC_PANEL_NAME_MAX_LEN 256
  31. u8 dbgfs_tx_cmd_buf[SZ_4K];
  32. static char dsi_display_primary[MAX_CMDLINE_PARAM_LEN];
  33. static char dsi_display_secondary[MAX_CMDLINE_PARAM_LEN];
  34. static struct dsi_display_boot_param boot_displays[MAX_DSI_ACTIVE_DISPLAY] = {
  35. {.boot_param = dsi_display_primary},
  36. {.boot_param = dsi_display_secondary},
  37. };
  38. static const struct of_device_id dsi_display_dt_match[] = {
  39. {.compatible = "qcom,dsi-display"},
  40. {}
  41. };
  42. bool is_skip_op_required(struct dsi_display *display)
  43. {
  44. if (!display)
  45. return false;
  46. return (display->is_cont_splash_enabled || display->trusted_vm_env);
  47. }
  48. static void dsi_display_mask_ctrl_error_interrupts(struct dsi_display *display,
  49. u32 mask, bool enable)
  50. {
  51. int i;
  52. struct dsi_display_ctrl *ctrl;
  53. if (!display)
  54. return;
  55. display_for_each_ctrl(i, display) {
  56. ctrl = &display->ctrl[i];
  57. if (!ctrl)
  58. continue;
  59. dsi_ctrl_mask_error_status_interrupts(ctrl->ctrl, mask, enable);
  60. }
  61. }
  62. static int dsi_display_config_clk_gating(struct dsi_display *display,
  63. bool enable)
  64. {
  65. int rc = 0, i = 0;
  66. struct dsi_display_ctrl *mctrl, *ctrl;
  67. enum dsi_clk_gate_type clk_selection;
  68. enum dsi_clk_gate_type const default_clk_select = PIXEL_CLK | DSI_PHY;
  69. if (!display) {
  70. DSI_ERR("Invalid params\n");
  71. return -EINVAL;
  72. }
  73. if (display->panel->host_config.force_hs_clk_lane) {
  74. DSI_DEBUG("no dsi clock gating for continuous clock mode\n");
  75. return 0;
  76. }
  77. mctrl = &display->ctrl[display->clk_master_idx];
  78. if (!mctrl) {
  79. DSI_ERR("Invalid controller\n");
  80. return -EINVAL;
  81. }
  82. clk_selection = display->clk_gating_config;
  83. if (!enable) {
  84. /* for disable path, make sure to disable all clk gating */
  85. clk_selection = DSI_CLK_ALL;
  86. } else if (!clk_selection || clk_selection > DSI_CLK_NONE) {
  87. /* Default selection, no overrides */
  88. clk_selection = default_clk_select;
  89. } else if (clk_selection == DSI_CLK_NONE) {
  90. clk_selection = 0;
  91. }
  92. DSI_DEBUG("%s clock gating Byte:%s Pixel:%s PHY:%s\n",
  93. enable ? "Enabling" : "Disabling",
  94. clk_selection & BYTE_CLK ? "yes" : "no",
  95. clk_selection & PIXEL_CLK ? "yes" : "no",
  96. clk_selection & DSI_PHY ? "yes" : "no");
  97. rc = dsi_ctrl_config_clk_gating(mctrl->ctrl, enable, clk_selection);
  98. if (rc) {
  99. DSI_ERR("[%s] failed to %s clk gating for clocks %d, rc=%d\n",
  100. display->name, enable ? "enable" : "disable",
  101. clk_selection, rc);
  102. return rc;
  103. }
  104. display_for_each_ctrl(i, display) {
  105. ctrl = &display->ctrl[i];
  106. if (!ctrl->ctrl || (ctrl == mctrl))
  107. continue;
  108. /**
  109. * In Split DSI usecase we should not enable clock gating on
  110. * DSI PHY1 to ensure no display atrifacts are seen.
  111. */
  112. clk_selection &= ~DSI_PHY;
  113. rc = dsi_ctrl_config_clk_gating(ctrl->ctrl, enable,
  114. clk_selection);
  115. if (rc) {
  116. DSI_ERR("[%s] failed to %s clk gating for clocks %d, rc=%d\n",
  117. display->name, enable ? "enable" : "disable",
  118. clk_selection, rc);
  119. return rc;
  120. }
  121. }
  122. return 0;
  123. }
  124. static void dsi_display_set_ctrl_esd_check_flag(struct dsi_display *display,
  125. bool enable)
  126. {
  127. int i;
  128. struct dsi_display_ctrl *ctrl;
  129. if (!display)
  130. return;
  131. display_for_each_ctrl(i, display) {
  132. ctrl = &display->ctrl[i];
  133. if (!ctrl)
  134. continue;
  135. ctrl->ctrl->esd_check_underway = enable;
  136. }
  137. }
  138. static void dsi_display_ctrl_irq_update(struct dsi_display *display, bool en)
  139. {
  140. int i;
  141. struct dsi_display_ctrl *ctrl;
  142. if (!display)
  143. return;
  144. display_for_each_ctrl(i, display) {
  145. ctrl = &display->ctrl[i];
  146. if (!ctrl)
  147. continue;
  148. dsi_ctrl_irq_update(ctrl->ctrl, en);
  149. }
  150. }
  151. void dsi_rect_intersect(const struct dsi_rect *r1,
  152. const struct dsi_rect *r2,
  153. struct dsi_rect *result)
  154. {
  155. int l, t, r, b;
  156. if (!r1 || !r2 || !result)
  157. return;
  158. l = max(r1->x, r2->x);
  159. t = max(r1->y, r2->y);
  160. r = min((r1->x + r1->w), (r2->x + r2->w));
  161. b = min((r1->y + r1->h), (r2->y + r2->h));
  162. if (r <= l || b <= t) {
  163. memset(result, 0, sizeof(*result));
  164. } else {
  165. result->x = l;
  166. result->y = t;
  167. result->w = r - l;
  168. result->h = b - t;
  169. }
  170. }
  171. int dsi_display_set_backlight(struct drm_connector *connector,
  172. void *display, u32 bl_lvl)
  173. {
  174. struct dsi_display *dsi_display = display;
  175. struct dsi_panel *panel;
  176. u32 bl_scale, bl_scale_sv;
  177. u64 bl_temp;
  178. int rc = 0;
  179. if (dsi_display == NULL || dsi_display->panel == NULL)
  180. return -EINVAL;
  181. panel = dsi_display->panel;
  182. mutex_lock(&panel->panel_lock);
  183. if (!dsi_panel_initialized(panel)) {
  184. rc = -EINVAL;
  185. goto error;
  186. }
  187. panel->bl_config.bl_level = bl_lvl;
  188. /* scale backlight */
  189. bl_scale = panel->bl_config.bl_scale;
  190. bl_temp = bl_lvl * bl_scale / MAX_BL_SCALE_LEVEL;
  191. bl_scale_sv = panel->bl_config.bl_scale_sv;
  192. bl_temp = (u32)bl_temp * bl_scale_sv / MAX_SV_BL_SCALE_LEVEL;
  193. DSI_DEBUG("bl_scale = %u, bl_scale_sv = %u, bl_lvl = %u\n",
  194. bl_scale, bl_scale_sv, (u32)bl_temp);
  195. rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle,
  196. DSI_CORE_CLK, DSI_CLK_ON);
  197. if (rc) {
  198. DSI_ERR("[%s] failed to enable DSI core clocks, rc=%d\n",
  199. dsi_display->name, rc);
  200. goto error;
  201. }
  202. rc = dsi_panel_set_backlight(panel, (u32)bl_temp);
  203. if (rc)
  204. DSI_ERR("unable to set backlight\n");
  205. rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle,
  206. DSI_CORE_CLK, DSI_CLK_OFF);
  207. if (rc) {
  208. DSI_ERR("[%s] failed to disable DSI core clocks, rc=%d\n",
  209. dsi_display->name, rc);
  210. goto error;
  211. }
  212. error:
  213. mutex_unlock(&panel->panel_lock);
  214. return rc;
  215. }
  216. static int dsi_display_cmd_engine_enable(struct dsi_display *display)
  217. {
  218. int rc = 0;
  219. int i;
  220. struct dsi_display_ctrl *m_ctrl, *ctrl;
  221. bool skip_op = is_skip_op_required(display);
  222. m_ctrl = &display->ctrl[display->cmd_master_idx];
  223. mutex_lock(&m_ctrl->ctrl->ctrl_lock);
  224. if (display->cmd_engine_refcount > 0) {
  225. display->cmd_engine_refcount++;
  226. goto done;
  227. }
  228. rc = dsi_ctrl_set_cmd_engine_state(m_ctrl->ctrl,
  229. DSI_CTRL_ENGINE_ON, skip_op);
  230. if (rc) {
  231. DSI_ERR("[%s] enable mcmd engine failed, skip_op:%d rc:%d\n",
  232. display->name, skip_op, rc);
  233. goto done;
  234. }
  235. display_for_each_ctrl(i, display) {
  236. ctrl = &display->ctrl[i];
  237. if (!ctrl->ctrl || (ctrl == m_ctrl))
  238. continue;
  239. rc = dsi_ctrl_set_cmd_engine_state(ctrl->ctrl,
  240. DSI_CTRL_ENGINE_ON, skip_op);
  241. if (rc) {
  242. DSI_ERR(
  243. "[%s] enable cmd engine failed, skip_op:%d rc:%d\n",
  244. display->name, skip_op, rc);
  245. goto error_disable_master;
  246. }
  247. }
  248. display->cmd_engine_refcount++;
  249. goto done;
  250. error_disable_master:
  251. (void)dsi_ctrl_set_cmd_engine_state(m_ctrl->ctrl,
  252. DSI_CTRL_ENGINE_OFF, skip_op);
  253. done:
  254. mutex_unlock(&m_ctrl->ctrl->ctrl_lock);
  255. return rc;
  256. }
  257. static int dsi_display_cmd_engine_disable(struct dsi_display *display)
  258. {
  259. int rc = 0;
  260. int i;
  261. struct dsi_display_ctrl *m_ctrl, *ctrl;
  262. bool skip_op = is_skip_op_required(display);
  263. m_ctrl = &display->ctrl[display->cmd_master_idx];
  264. mutex_lock(&m_ctrl->ctrl->ctrl_lock);
  265. if (display->cmd_engine_refcount == 0) {
  266. DSI_ERR("[%s] Invalid refcount\n", display->name);
  267. goto done;
  268. } else if (display->cmd_engine_refcount > 1) {
  269. display->cmd_engine_refcount--;
  270. goto done;
  271. }
  272. display_for_each_ctrl(i, display) {
  273. ctrl = &display->ctrl[i];
  274. if (!ctrl->ctrl || (ctrl == m_ctrl))
  275. continue;
  276. rc = dsi_ctrl_set_cmd_engine_state(ctrl->ctrl,
  277. DSI_CTRL_ENGINE_OFF, skip_op);
  278. if (rc)
  279. DSI_ERR(
  280. "[%s] disable cmd engine failed, skip_op:%d rc:%d\n",
  281. display->name, skip_op, rc);
  282. }
  283. rc = dsi_ctrl_set_cmd_engine_state(m_ctrl->ctrl,
  284. DSI_CTRL_ENGINE_OFF, skip_op);
  285. if (rc) {
  286. DSI_ERR("[%s] disable mcmd engine failed, skip_op:%d rc:%d\n",
  287. display->name, skip_op, rc);
  288. goto error;
  289. }
  290. error:
  291. display->cmd_engine_refcount = 0;
  292. done:
  293. mutex_unlock(&m_ctrl->ctrl->ctrl_lock);
  294. return rc;
  295. }
  296. static void dsi_display_aspace_cb_locked(void *cb_data, bool is_detach)
  297. {
  298. struct dsi_display *display;
  299. struct dsi_display_ctrl *display_ctrl;
  300. int rc, cnt;
  301. if (!cb_data) {
  302. DSI_ERR("aspace cb called with invalid cb_data\n");
  303. return;
  304. }
  305. display = (struct dsi_display *)cb_data;
  306. /*
  307. * acquire panel_lock to make sure no commands are in-progress
  308. * while detaching the non-secure context banks
  309. */
  310. dsi_panel_acquire_panel_lock(display->panel);
  311. if (is_detach) {
  312. /* invalidate the stored iova */
  313. display->cmd_buffer_iova = 0;
  314. /* return the virtual address mapping */
  315. msm_gem_put_vaddr(display->tx_cmd_buf);
  316. msm_gem_vunmap(display->tx_cmd_buf, OBJ_LOCK_NORMAL);
  317. } else {
  318. rc = msm_gem_get_iova(display->tx_cmd_buf,
  319. display->aspace, &(display->cmd_buffer_iova));
  320. if (rc) {
  321. DSI_ERR("failed to get the iova rc %d\n", rc);
  322. goto end;
  323. }
  324. display->vaddr =
  325. (void *) msm_gem_get_vaddr(display->tx_cmd_buf);
  326. if (IS_ERR_OR_NULL(display->vaddr)) {
  327. DSI_ERR("failed to get va rc %d\n", rc);
  328. goto end;
  329. }
  330. }
  331. display_for_each_ctrl(cnt, display) {
  332. display_ctrl = &display->ctrl[cnt];
  333. display_ctrl->ctrl->cmd_buffer_size = display->cmd_buffer_size;
  334. display_ctrl->ctrl->cmd_buffer_iova = display->cmd_buffer_iova;
  335. display_ctrl->ctrl->vaddr = display->vaddr;
  336. display_ctrl->ctrl->secure_mode = is_detach;
  337. }
  338. end:
  339. /* release panel_lock */
  340. dsi_panel_release_panel_lock(display->panel);
  341. }
  342. static irqreturn_t dsi_display_panel_te_irq_handler(int irq, void *data)
  343. {
  344. struct dsi_display *display = (struct dsi_display *)data;
  345. /*
  346. * This irq handler is used for sole purpose of identifying
  347. * ESD attacks on panel and we can safely assume IRQ_HANDLED
  348. * in case of display not being initialized yet
  349. */
  350. if (!display)
  351. return IRQ_HANDLED;
  352. SDE_EVT32(SDE_EVTLOG_FUNC_CASE1);
  353. complete_all(&display->esd_te_gate);
  354. return IRQ_HANDLED;
  355. }
  356. static void dsi_display_change_te_irq_status(struct dsi_display *display,
  357. bool enable)
  358. {
  359. if (!display) {
  360. DSI_ERR("Invalid params\n");
  361. return;
  362. }
  363. /* Handle unbalanced irq enable/disable calls */
  364. if (enable && !display->is_te_irq_enabled) {
  365. enable_irq(gpio_to_irq(display->disp_te_gpio));
  366. display->is_te_irq_enabled = true;
  367. } else if (!enable && display->is_te_irq_enabled) {
  368. disable_irq(gpio_to_irq(display->disp_te_gpio));
  369. display->is_te_irq_enabled = false;
  370. }
  371. }
  372. static void dsi_display_register_te_irq(struct dsi_display *display)
  373. {
  374. int rc = 0;
  375. struct platform_device *pdev;
  376. struct device *dev;
  377. unsigned int te_irq;
  378. pdev = display->pdev;
  379. if (!pdev) {
  380. DSI_ERR("invalid platform device\n");
  381. return;
  382. }
  383. dev = &pdev->dev;
  384. if (!dev) {
  385. DSI_ERR("invalid device\n");
  386. return;
  387. }
  388. if (display->trusted_vm_env) {
  389. DSI_INFO("GPIO's are not enabled in trusted VM\n");
  390. return;
  391. }
  392. if (!gpio_is_valid(display->disp_te_gpio)) {
  393. rc = -EINVAL;
  394. goto error;
  395. }
  396. init_completion(&display->esd_te_gate);
  397. te_irq = gpio_to_irq(display->disp_te_gpio);
  398. /* Avoid deferred spurious irqs with disable_irq() */
  399. irq_set_status_flags(te_irq, IRQ_DISABLE_UNLAZY);
  400. rc = devm_request_irq(dev, te_irq, dsi_display_panel_te_irq_handler,
  401. IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
  402. "TE_GPIO", display);
  403. if (rc) {
  404. DSI_ERR("TE request_irq failed for ESD rc:%d\n", rc);
  405. irq_clear_status_flags(te_irq, IRQ_DISABLE_UNLAZY);
  406. goto error;
  407. }
  408. disable_irq(te_irq);
  409. display->is_te_irq_enabled = false;
  410. return;
  411. error:
  412. /* disable the TE based ESD check */
  413. DSI_WARN("Unable to register for TE IRQ\n");
  414. if (display->panel->esd_config.status_mode == ESD_MODE_PANEL_TE)
  415. display->panel->esd_config.esd_enabled = false;
  416. }
  417. /* Allocate memory for cmd dma tx buffer */
  418. static int dsi_host_alloc_cmd_tx_buffer(struct dsi_display *display)
  419. {
  420. int rc = 0, cnt = 0;
  421. struct dsi_display_ctrl *display_ctrl;
  422. display->tx_cmd_buf = msm_gem_new(display->drm_dev,
  423. SZ_4K,
  424. MSM_BO_UNCACHED);
  425. if ((display->tx_cmd_buf) == NULL) {
  426. DSI_ERR("Failed to allocate cmd tx buf memory\n");
  427. rc = -ENOMEM;
  428. goto error;
  429. }
  430. display->cmd_buffer_size = SZ_4K;
  431. display->aspace = msm_gem_smmu_address_space_get(
  432. display->drm_dev, MSM_SMMU_DOMAIN_UNSECURE);
  433. if (PTR_ERR(display->aspace) == -ENODEV) {
  434. display->aspace = NULL;
  435. DSI_DEBUG("IOMMU not present, relying on VRAM\n");
  436. } else if (IS_ERR_OR_NULL(display->aspace)) {
  437. rc = PTR_ERR(display->aspace);
  438. display->aspace = NULL;
  439. DSI_ERR("failed to get aspace %d\n", rc);
  440. goto free_gem;
  441. } else if (display->aspace) {
  442. /* register to aspace */
  443. rc = msm_gem_address_space_register_cb(display->aspace,
  444. dsi_display_aspace_cb_locked, (void *)display);
  445. if (rc) {
  446. DSI_ERR("failed to register callback %d\n", rc);
  447. goto free_gem;
  448. }
  449. }
  450. rc = msm_gem_get_iova(display->tx_cmd_buf, display->aspace,
  451. &(display->cmd_buffer_iova));
  452. if (rc) {
  453. DSI_ERR("failed to get the iova rc %d\n", rc);
  454. goto free_aspace_cb;
  455. }
  456. display->vaddr =
  457. (void *) msm_gem_get_vaddr(display->tx_cmd_buf);
  458. if (IS_ERR_OR_NULL(display->vaddr)) {
  459. DSI_ERR("failed to get va rc %d\n", rc);
  460. rc = -EINVAL;
  461. goto put_iova;
  462. }
  463. display_for_each_ctrl(cnt, display) {
  464. display_ctrl = &display->ctrl[cnt];
  465. display_ctrl->ctrl->cmd_buffer_size = SZ_4K;
  466. display_ctrl->ctrl->cmd_buffer_iova =
  467. display->cmd_buffer_iova;
  468. display_ctrl->ctrl->vaddr = display->vaddr;
  469. display_ctrl->ctrl->tx_cmd_buf = display->tx_cmd_buf;
  470. }
  471. return rc;
  472. put_iova:
  473. msm_gem_put_iova(display->tx_cmd_buf, display->aspace);
  474. free_aspace_cb:
  475. msm_gem_address_space_unregister_cb(display->aspace,
  476. dsi_display_aspace_cb_locked, display);
  477. free_gem:
  478. mutex_lock(&display->drm_dev->struct_mutex);
  479. msm_gem_free_object(display->tx_cmd_buf);
  480. mutex_unlock(&display->drm_dev->struct_mutex);
  481. error:
  482. return rc;
  483. }
  484. static bool dsi_display_validate_reg_read(struct dsi_panel *panel)
  485. {
  486. int i, j = 0;
  487. int len = 0, *lenp;
  488. int group = 0, count = 0;
  489. struct drm_panel_esd_config *config;
  490. if (!panel)
  491. return false;
  492. config = &(panel->esd_config);
  493. lenp = config->status_valid_params ?: config->status_cmds_rlen;
  494. count = config->status_cmd.count;
  495. for (i = 0; i < count; i++)
  496. len += lenp[i];
  497. for (i = 0; i < len; i++)
  498. j += len;
  499. for (j = 0; j < config->groups; ++j) {
  500. for (i = 0; i < len; ++i) {
  501. if (config->return_buf[i] !=
  502. config->status_value[group + i]) {
  503. DRM_ERROR("mismatch: 0x%x\n",
  504. config->return_buf[i]);
  505. break;
  506. }
  507. }
  508. if (i == len)
  509. return true;
  510. group += len;
  511. }
  512. return false;
  513. }
  514. static void dsi_display_parse_te_data(struct dsi_display *display)
  515. {
  516. struct platform_device *pdev;
  517. struct device *dev;
  518. int rc = 0;
  519. u32 val = 0;
  520. pdev = display->pdev;
  521. if (!pdev) {
  522. DSI_ERR("Invalid platform device\n");
  523. return;
  524. }
  525. dev = &pdev->dev;
  526. if (!dev) {
  527. DSI_ERR("Invalid platform device\n");
  528. return;
  529. }
  530. display->disp_te_gpio = of_get_named_gpio(dev->of_node,
  531. "qcom,platform-te-gpio", 0);
  532. if (display->fw)
  533. rc = dsi_parser_read_u32(display->parser_node,
  534. "qcom,panel-te-source", &val);
  535. else
  536. rc = of_property_read_u32(dev->of_node,
  537. "qcom,panel-te-source", &val);
  538. if (rc || (val > MAX_TE_SOURCE_ID)) {
  539. DSI_ERR("invalid vsync source selection\n");
  540. val = 0;
  541. }
  542. display->te_source = val;
  543. }
  544. static void dsi_display_set_cmd_tx_ctrl_flags(struct dsi_display *display,
  545. struct dsi_cmd_desc *cmd)
  546. {
  547. struct dsi_display_ctrl *ctrl, *m_ctrl;
  548. struct mipi_dsi_msg *msg = &cmd->msg;
  549. u32 flags = 0;
  550. int i = 0;
  551. m_ctrl = &display->ctrl[display->clk_master_idx];
  552. display_for_each_ctrl(i, display) {
  553. ctrl = &display->ctrl[i];
  554. if (!ctrl->ctrl)
  555. continue;
  556. /*
  557. * Set cmd transfer mode flags.
  558. * 1) Default selection is CMD fetch from memory.
  559. * 2) In secure session override and use FIFO rather than
  560. * memory.
  561. * 3) If cmd_len is greater than FIFO size non embedded mode of
  562. * tx is used.
  563. */
  564. flags = DSI_CTRL_CMD_FETCH_MEMORY;
  565. if (ctrl->ctrl->secure_mode) {
  566. flags &= ~DSI_CTRL_CMD_FETCH_MEMORY;
  567. flags |= DSI_CTRL_CMD_FIFO_STORE;
  568. } else if (msg->tx_len > DSI_EMBEDDED_MODE_DMA_MAX_SIZE_BYTES) {
  569. flags |= DSI_CTRL_CMD_NON_EMBEDDED_MODE;
  570. }
  571. /* Set flags needed for broadcast. Read commands are always unicast */
  572. if (!(msg->flags & MIPI_DSI_MSG_UNICAST_COMMAND) && (display->ctrl_count > 1))
  573. flags |= DSI_CTRL_CMD_BROADCAST | DSI_CTRL_CMD_DEFER_TRIGGER;
  574. /*
  575. * Set flags for command scheduling.
  576. * 1) In video mode command DMA scheduling is default.
  577. * 2) In command mode command DMA scheduling depends on message
  578. * flag and TE needs to be running.
  579. */
  580. if (display->panel->panel_mode == DSI_OP_VIDEO_MODE) {
  581. flags |= DSI_CTRL_CMD_CUSTOM_DMA_SCHED;
  582. } else {
  583. if (msg->flags & MIPI_DSI_MSG_CMD_DMA_SCHED)
  584. flags |= DSI_CTRL_CMD_CUSTOM_DMA_SCHED;
  585. if (!display->enabled)
  586. flags &= ~DSI_CTRL_CMD_CUSTOM_DMA_SCHED;
  587. }
  588. /* Set flags for last command */
  589. if (!(msg->flags & MIPI_DSI_MSG_BATCH_COMMAND))
  590. flags |= DSI_CTRL_CMD_LAST_COMMAND;
  591. /*
  592. * Set flags for asynchronous wait.
  593. * Asynchronous wait is supported in the following scenarios
  594. * 1) queue_cmd_waits is set by connector and
  595. * - commands are not sent using DSI FIFO memory
  596. * - commands are not sent in non-embedded mode
  597. * - not a video mode panel
  598. * - no explicit msg post_wait_ms is specified
  599. * - not a read command
  600. * 2) if async override msg flag is present
  601. */
  602. if (display->queue_cmd_waits)
  603. if (!(flags & DSI_CTRL_CMD_FIFO_STORE) &&
  604. !(flags & DSI_CTRL_CMD_NON_EMBEDDED_MODE) &&
  605. !(display->panel->panel_mode == DSI_OP_VIDEO_MODE) &&
  606. (cmd->post_wait_ms == 0) &&
  607. !(cmd->ctrl_flags & DSI_CTRL_CMD_READ))
  608. flags |= DSI_CTRL_CMD_ASYNC_WAIT;
  609. if (msg->flags & MIPI_DSI_MSG_ASYNC_OVERRIDE)
  610. flags |= DSI_CTRL_CMD_ASYNC_WAIT;
  611. }
  612. cmd->ctrl_flags |= flags;
  613. }
  614. static int dsi_display_read_status(struct dsi_display_ctrl *ctrl,
  615. struct dsi_display *display)
  616. {
  617. int i, rc = 0, count = 0, start = 0, *lenp;
  618. struct drm_panel_esd_config *config;
  619. struct dsi_cmd_desc *cmds;
  620. struct dsi_panel *panel;
  621. u32 flags = 0;
  622. if (!display->panel || !ctrl || !ctrl->ctrl)
  623. return -EINVAL;
  624. panel = display->panel;
  625. /*
  626. * When DSI controller is not in initialized state, we do not want to
  627. * report a false ESD failure and hence we defer until next read
  628. * happen.
  629. */
  630. if (!dsi_ctrl_validate_host_state(ctrl->ctrl))
  631. return 1;
  632. config = &(panel->esd_config);
  633. lenp = config->status_valid_params ?: config->status_cmds_rlen;
  634. count = config->status_cmd.count;
  635. cmds = config->status_cmd.cmds;
  636. flags = DSI_CTRL_CMD_READ;
  637. for (i = 0; i < count; ++i) {
  638. memset(config->status_buf, 0x0, SZ_4K);
  639. if (config->status_cmd.state == DSI_CMD_SET_STATE_LP)
  640. cmds[i].msg.flags |= MIPI_DSI_MSG_USE_LPM;
  641. cmds[i].msg.flags |= MIPI_DSI_MSG_UNICAST_COMMAND;
  642. cmds[i].msg.rx_buf = config->status_buf;
  643. cmds[i].msg.rx_len = config->status_cmds_rlen[i];
  644. cmds[i].ctrl_flags = flags;
  645. dsi_display_set_cmd_tx_ctrl_flags(display,&cmds[i]);
  646. rc = dsi_ctrl_cmd_transfer(ctrl->ctrl, &cmds[i]);
  647. if (rc <= 0) {
  648. DSI_ERR("rx cmd transfer failed rc=%d\n", rc);
  649. return rc;
  650. }
  651. memcpy(config->return_buf + start,
  652. config->status_buf, lenp[i]);
  653. start += lenp[i];
  654. }
  655. return rc;
  656. }
  657. static int dsi_display_validate_status(struct dsi_display_ctrl *ctrl,
  658. struct dsi_display *display)
  659. {
  660. int rc = 0;
  661. rc = dsi_display_read_status(ctrl, display);
  662. if (rc <= 0) {
  663. goto exit;
  664. } else {
  665. /*
  666. * panel status read successfully.
  667. * check for validity of the data read back.
  668. */
  669. rc = dsi_display_validate_reg_read(display->panel);
  670. if (!rc) {
  671. rc = -EINVAL;
  672. goto exit;
  673. }
  674. }
  675. exit:
  676. return rc;
  677. }
  678. static int dsi_display_status_reg_read(struct dsi_display *display)
  679. {
  680. int rc = 0, i;
  681. struct dsi_display_ctrl *m_ctrl, *ctrl;
  682. DSI_DEBUG(" ++\n");
  683. m_ctrl = &display->ctrl[display->cmd_master_idx];
  684. if (display->tx_cmd_buf == NULL) {
  685. rc = dsi_host_alloc_cmd_tx_buffer(display);
  686. if (rc) {
  687. DSI_ERR("failed to allocate cmd tx buffer memory\n");
  688. goto done;
  689. }
  690. }
  691. rc = dsi_display_cmd_engine_enable(display);
  692. if (rc) {
  693. DSI_ERR("cmd engine enable failed\n");
  694. return -EPERM;
  695. }
  696. rc = dsi_display_validate_status(m_ctrl, display);
  697. if (rc <= 0) {
  698. DSI_ERR("[%s] read status failed on master,rc=%d\n",
  699. display->name, rc);
  700. goto exit;
  701. }
  702. if (!display->panel->sync_broadcast_en)
  703. goto exit;
  704. display_for_each_ctrl(i, display) {
  705. ctrl = &display->ctrl[i];
  706. if (ctrl == m_ctrl)
  707. continue;
  708. rc = dsi_display_validate_status(ctrl, display);
  709. if (rc <= 0) {
  710. DSI_ERR("[%s] read status failed on slave,rc=%d\n",
  711. display->name, rc);
  712. goto exit;
  713. }
  714. }
  715. exit:
  716. dsi_display_cmd_engine_disable(display);
  717. done:
  718. return rc;
  719. }
  720. static int dsi_display_status_bta_request(struct dsi_display *display)
  721. {
  722. int rc = 0;
  723. DSI_DEBUG(" ++\n");
  724. /* TODO: trigger SW BTA and wait for acknowledgment */
  725. return rc;
  726. }
  727. static int dsi_display_status_check_te(struct dsi_display *display,
  728. int rechecks)
  729. {
  730. int rc = 1, i = 0;
  731. int const esd_te_timeout = msecs_to_jiffies(3*20);
  732. if (!rechecks)
  733. return rc;
  734. dsi_display_change_te_irq_status(display, true);
  735. for (i = 0; i < rechecks; i++) {
  736. reinit_completion(&display->esd_te_gate);
  737. if (!wait_for_completion_timeout(&display->esd_te_gate,
  738. esd_te_timeout)) {
  739. DSI_ERR("TE check failed\n");
  740. dsi_display_change_te_irq_status(display, false);
  741. return -EINVAL;
  742. }
  743. }
  744. dsi_display_change_te_irq_status(display, false);
  745. return rc;
  746. }
  747. int dsi_display_check_status(struct drm_connector *connector, void *display,
  748. bool te_check_override)
  749. {
  750. struct dsi_display *dsi_display = display;
  751. struct dsi_panel *panel;
  752. u32 status_mode;
  753. int rc = 0x1, ret;
  754. u32 mask;
  755. int te_rechecks = 1;
  756. if (!dsi_display || !dsi_display->panel)
  757. return -EINVAL;
  758. panel = dsi_display->panel;
  759. dsi_panel_acquire_panel_lock(panel);
  760. if (!panel->panel_initialized) {
  761. DSI_DEBUG("Panel not initialized\n");
  762. goto release_panel_lock;
  763. }
  764. /* Prevent another ESD check,when ESD recovery is underway */
  765. if (atomic_read(&panel->esd_recovery_pending))
  766. goto release_panel_lock;
  767. status_mode = panel->esd_config.status_mode;
  768. if ((status_mode == ESD_MODE_SW_SIM_SUCCESS) ||
  769. (dsi_display->sw_te_using_wd))
  770. goto release_panel_lock;
  771. if (status_mode == ESD_MODE_SW_SIM_FAILURE) {
  772. rc = -EINVAL;
  773. goto release_panel_lock;
  774. }
  775. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY, status_mode, te_check_override);
  776. if (te_check_override)
  777. te_rechecks = MAX_TE_RECHECKS;
  778. if ((dsi_display->trusted_vm_env) ||
  779. (panel->panel_mode == DSI_OP_VIDEO_MODE))
  780. te_rechecks = 0;
  781. ret = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle,
  782. DSI_ALL_CLKS, DSI_CLK_ON);
  783. if (ret)
  784. goto release_panel_lock;
  785. /* Mask error interrupts before attempting ESD read */
  786. mask = BIT(DSI_FIFO_OVERFLOW) | BIT(DSI_FIFO_UNDERFLOW);
  787. dsi_display_set_ctrl_esd_check_flag(dsi_display, true);
  788. dsi_display_mask_ctrl_error_interrupts(dsi_display, mask, true);
  789. if (status_mode == ESD_MODE_REG_READ) {
  790. rc = dsi_display_status_reg_read(dsi_display);
  791. } else if (status_mode == ESD_MODE_SW_BTA) {
  792. rc = dsi_display_status_bta_request(dsi_display);
  793. } else if (status_mode == ESD_MODE_PANEL_TE) {
  794. rc = dsi_display_status_check_te(dsi_display, te_rechecks);
  795. te_check_override = false;
  796. } else {
  797. DSI_WARN("Unsupported check status mode: %d\n", status_mode);
  798. panel->esd_config.esd_enabled = false;
  799. }
  800. if (rc <= 0 && te_check_override)
  801. rc = dsi_display_status_check_te(dsi_display, te_rechecks);
  802. /* Unmask error interrupts if check passed*/
  803. if (rc > 0) {
  804. dsi_display_set_ctrl_esd_check_flag(dsi_display, false);
  805. dsi_display_mask_ctrl_error_interrupts(dsi_display, mask,
  806. false);
  807. if (te_check_override && panel->esd_config.esd_enabled == false)
  808. rc = dsi_display_status_check_te(dsi_display,
  809. te_rechecks);
  810. }
  811. dsi_display_clk_ctrl(dsi_display->dsi_clk_handle,
  812. DSI_ALL_CLKS, DSI_CLK_OFF);
  813. /* Handle Panel failures during display disable sequence */
  814. if (rc <=0)
  815. atomic_set(&panel->esd_recovery_pending, 1);
  816. release_panel_lock:
  817. dsi_panel_release_panel_lock(panel);
  818. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT, rc);
  819. return rc;
  820. }
  821. static int dsi_display_ctrl_get_host_init_state(struct dsi_display *dsi_display,
  822. bool *state)
  823. {
  824. struct dsi_display_ctrl *ctrl;
  825. int i, rc = -EINVAL;
  826. display_for_each_ctrl(i, dsi_display) {
  827. ctrl = &dsi_display->ctrl[i];
  828. rc = dsi_ctrl_get_host_engine_init_state(ctrl->ctrl, state);
  829. if (rc)
  830. break;
  831. }
  832. return rc;
  833. }
  834. static int dsi_display_cmd_rx(struct dsi_display *display,
  835. struct dsi_cmd_desc *cmd)
  836. {
  837. struct dsi_display_ctrl *m_ctrl = NULL;
  838. u32 mask = 0, flags = 0;
  839. int rc = 0;
  840. if (!display || !display->panel)
  841. return -EINVAL;
  842. m_ctrl = &display->ctrl[display->cmd_master_idx];
  843. if (!m_ctrl || !m_ctrl->ctrl)
  844. return -EINVAL;
  845. /* acquire panel_lock to make sure no commands are in progress */
  846. dsi_panel_acquire_panel_lock(display->panel);
  847. if (!display->panel->panel_initialized) {
  848. DSI_DEBUG("panel not initialized\n");
  849. goto release_panel_lock;
  850. }
  851. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  852. DSI_ALL_CLKS, DSI_CLK_ON);
  853. if (rc)
  854. goto release_panel_lock;
  855. mask = BIT(DSI_FIFO_OVERFLOW) | BIT(DSI_FIFO_UNDERFLOW);
  856. dsi_display_mask_ctrl_error_interrupts(display, mask, true);
  857. rc = dsi_display_cmd_engine_enable(display);
  858. if (rc) {
  859. DSI_ERR("cmd engine enable failed rc = %d\n", rc);
  860. goto error;
  861. }
  862. flags = DSI_CTRL_CMD_READ;
  863. cmd->ctrl_flags = flags;
  864. dsi_display_set_cmd_tx_ctrl_flags(display, cmd);
  865. rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, cmd);
  866. if (rc <= 0)
  867. DSI_ERR("rx cmd transfer failed rc = %d\n", rc);
  868. dsi_display_cmd_engine_disable(display);
  869. error:
  870. dsi_display_mask_ctrl_error_interrupts(display, mask, false);
  871. dsi_display_clk_ctrl(display->dsi_clk_handle,
  872. DSI_ALL_CLKS, DSI_CLK_OFF);
  873. release_panel_lock:
  874. dsi_panel_release_panel_lock(display->panel);
  875. return rc;
  876. }
  877. int dsi_display_cmd_transfer(struct drm_connector *connector,
  878. void *display, const char *cmd_buf,
  879. u32 cmd_buf_len)
  880. {
  881. struct dsi_display *dsi_display = display;
  882. int rc = 0, cnt = 0, i = 0;
  883. bool state = false, transfer = false;
  884. struct dsi_panel_cmd_set *set;
  885. if (!dsi_display || !cmd_buf) {
  886. DSI_ERR("[DSI] invalid params\n");
  887. return -EINVAL;
  888. }
  889. DSI_DEBUG("[DSI] Display command transfer\n");
  890. if (!(cmd_buf[3] & MIPI_DSI_MSG_BATCH_COMMAND))
  891. transfer = true;
  892. mutex_lock(&dsi_display->display_lock);
  893. rc = dsi_display_ctrl_get_host_init_state(dsi_display, &state);
  894. /**
  895. * Handle scenario where a command transfer is initiated through
  896. * sysfs interface when device is in suepnd state.
  897. */
  898. if (!rc && !state) {
  899. pr_warn_ratelimited("Command xfer attempted while device is in suspend state\n"
  900. );
  901. rc = -EPERM;
  902. goto end;
  903. }
  904. if (rc || !state) {
  905. DSI_ERR("[DSI] Invalid host state %d rc %d\n",
  906. state, rc);
  907. rc = -EPERM;
  908. goto end;
  909. }
  910. /*
  911. * Reset the dbgfs buffer if the commands sent exceed the available
  912. * buffer size. For video mode, limiting the buffer size to 2K to
  913. * ensure no performance issues.
  914. */
  915. if (dsi_display->panel->panel_mode == DSI_OP_CMD_MODE) {
  916. if ((dsi_display->tx_cmd_buf_ndx + cmd_buf_len) > SZ_4K) {
  917. memset(dbgfs_tx_cmd_buf, 0, SZ_4K);
  918. dsi_display->tx_cmd_buf_ndx = 0;
  919. }
  920. } else {
  921. if ((dsi_display->tx_cmd_buf_ndx + cmd_buf_len) > SZ_2K) {
  922. memset(dbgfs_tx_cmd_buf, 0, SZ_4K);
  923. dsi_display->tx_cmd_buf_ndx = 0;
  924. }
  925. }
  926. memcpy(&dbgfs_tx_cmd_buf[dsi_display->tx_cmd_buf_ndx], cmd_buf,
  927. cmd_buf_len);
  928. dsi_display->tx_cmd_buf_ndx += cmd_buf_len;
  929. if (transfer) {
  930. struct dsi_cmd_desc *cmds;
  931. set = &dsi_display->cmd_set;
  932. set->count = 0;
  933. dsi_panel_get_cmd_pkt_count(dbgfs_tx_cmd_buf,
  934. dsi_display->tx_cmd_buf_ndx, &cnt);
  935. dsi_panel_alloc_cmd_packets(set, cnt);
  936. dsi_panel_create_cmd_packets(dbgfs_tx_cmd_buf,
  937. dsi_display->tx_cmd_buf_ndx, cnt, set->cmds);
  938. cmds = set->cmds;
  939. dsi_display->tx_cmd_buf_ndx = 0;
  940. for (i = 0; i < cnt; i++) {
  941. rc = dsi_host_transfer_sub(&dsi_display->host, cmds);
  942. if (rc < 0) {
  943. DSI_ERR("failed to send command, rc=%d\n", rc);
  944. break;
  945. }
  946. if (cmds->post_wait_ms)
  947. usleep_range(cmds->post_wait_ms*1000,
  948. ((cmds->post_wait_ms*1000)+10));
  949. cmds++;
  950. }
  951. memset(dbgfs_tx_cmd_buf, 0, SZ_4K);
  952. dsi_panel_destroy_cmd_packets(set);
  953. dsi_panel_dealloc_cmd_packets(set);
  954. }
  955. end:
  956. mutex_unlock(&dsi_display->display_lock);
  957. return rc;
  958. }
  959. static void _dsi_display_continuous_clk_ctrl(struct dsi_display *display,
  960. bool enable)
  961. {
  962. int i;
  963. struct dsi_display_ctrl *ctrl;
  964. if (!display || !display->panel->host_config.force_hs_clk_lane)
  965. return;
  966. display_for_each_ctrl(i, display) {
  967. ctrl = &display->ctrl[i];
  968. /*
  969. * For phy ver 4.0 chipsets, configure DSI controller and
  970. * DSI PHY to force clk lane to HS mode always whereas
  971. * for other phy ver chipsets, configure DSI controller only.
  972. */
  973. if (ctrl->phy->hw.ops.set_continuous_clk) {
  974. dsi_ctrl_hs_req_sel(ctrl->ctrl, true);
  975. dsi_ctrl_set_continuous_clk(ctrl->ctrl, enable);
  976. dsi_phy_set_continuous_clk(ctrl->phy, enable);
  977. } else {
  978. dsi_ctrl_set_continuous_clk(ctrl->ctrl, enable);
  979. }
  980. }
  981. }
  982. int dsi_display_cmd_receive(void *display, const char *cmd_buf,
  983. u32 cmd_buf_len, u8 *recv_buf, u32 recv_buf_len)
  984. {
  985. struct dsi_display *dsi_display = display;
  986. struct dsi_cmd_desc cmd = {};
  987. bool state = false;
  988. int rc = -1;
  989. if (!dsi_display || !cmd_buf || !recv_buf) {
  990. DSI_ERR("[DSI] invalid params\n");
  991. return -EINVAL;
  992. }
  993. rc = dsi_panel_create_cmd_packets(cmd_buf, cmd_buf_len, 1, &cmd);
  994. if (rc) {
  995. DSI_ERR("[DSI] command packet create failed, rc = %d\n", rc);
  996. return rc;
  997. }
  998. cmd.msg.rx_buf = recv_buf;
  999. cmd.msg.rx_len = recv_buf_len;
  1000. cmd.msg.flags |= MIPI_DSI_MSG_UNICAST_COMMAND;
  1001. mutex_lock(&dsi_display->display_lock);
  1002. rc = dsi_display_ctrl_get_host_init_state(dsi_display, &state);
  1003. if (rc || !state) {
  1004. DSI_ERR("[DSI] Invalid host state = %d rc = %d\n",
  1005. state, rc);
  1006. rc = -EPERM;
  1007. goto end;
  1008. }
  1009. rc = dsi_display_cmd_rx(dsi_display, &cmd);
  1010. if (rc <= 0)
  1011. DSI_ERR("[DSI] Display command receive failed, rc=%d\n", rc);
  1012. end:
  1013. mutex_unlock(&dsi_display->display_lock);
  1014. return rc;
  1015. }
  1016. int dsi_display_soft_reset(void *display)
  1017. {
  1018. struct dsi_display *dsi_display;
  1019. struct dsi_display_ctrl *ctrl;
  1020. int rc = 0;
  1021. int i;
  1022. if (!display)
  1023. return -EINVAL;
  1024. dsi_display = display;
  1025. display_for_each_ctrl(i, dsi_display) {
  1026. ctrl = &dsi_display->ctrl[i];
  1027. rc = dsi_ctrl_soft_reset(ctrl->ctrl);
  1028. if (rc) {
  1029. DSI_ERR("[%s] failed to soft reset host_%d, rc=%d\n",
  1030. dsi_display->name, i, rc);
  1031. break;
  1032. }
  1033. }
  1034. return rc;
  1035. }
  1036. enum dsi_pixel_format dsi_display_get_dst_format(
  1037. struct drm_connector *connector,
  1038. void *display)
  1039. {
  1040. enum dsi_pixel_format format = DSI_PIXEL_FORMAT_MAX;
  1041. struct dsi_display *dsi_display = (struct dsi_display *)display;
  1042. if (!dsi_display || !dsi_display->panel) {
  1043. DSI_ERR("Invalid params(s) dsi_display %pK, panel %pK\n",
  1044. dsi_display,
  1045. ((dsi_display) ? dsi_display->panel : NULL));
  1046. return format;
  1047. }
  1048. format = dsi_display->panel->host_config.dst_format;
  1049. return format;
  1050. }
  1051. static void _dsi_display_setup_misr(struct dsi_display *display)
  1052. {
  1053. int i;
  1054. display_for_each_ctrl(i, display) {
  1055. dsi_ctrl_setup_misr(display->ctrl[i].ctrl,
  1056. display->misr_enable,
  1057. display->misr_frame_count);
  1058. }
  1059. }
  1060. int dsi_display_set_power(struct drm_connector *connector,
  1061. int power_mode, void *disp)
  1062. {
  1063. struct dsi_display *display = disp;
  1064. int rc = 0;
  1065. if (!display || !display->panel) {
  1066. DSI_ERR("invalid display/panel\n");
  1067. return -EINVAL;
  1068. }
  1069. switch (power_mode) {
  1070. case SDE_MODE_DPMS_LP1:
  1071. rc = dsi_panel_set_lp1(display->panel);
  1072. break;
  1073. case SDE_MODE_DPMS_LP2:
  1074. rc = dsi_panel_set_lp2(display->panel);
  1075. break;
  1076. case SDE_MODE_DPMS_ON:
  1077. if ((display->panel->power_mode == SDE_MODE_DPMS_LP1) ||
  1078. (display->panel->power_mode == SDE_MODE_DPMS_LP2))
  1079. rc = dsi_panel_set_nolp(display->panel);
  1080. break;
  1081. case SDE_MODE_DPMS_OFF:
  1082. default:
  1083. return rc;
  1084. }
  1085. SDE_EVT32(display->panel->power_mode, power_mode, rc);
  1086. DSI_DEBUG("Power mode transition from %d to %d %s",
  1087. display->panel->power_mode, power_mode,
  1088. rc ? "failed" : "successful");
  1089. if (!rc)
  1090. display->panel->power_mode = power_mode;
  1091. return rc;
  1092. }
  1093. #ifdef CONFIG_DEBUG_FS
  1094. static bool dsi_display_is_te_based_esd(struct dsi_display *display)
  1095. {
  1096. u32 status_mode = 0;
  1097. if (!display->panel) {
  1098. DSI_ERR("Invalid panel data\n");
  1099. return false;
  1100. }
  1101. status_mode = display->panel->esd_config.status_mode;
  1102. if (status_mode == ESD_MODE_PANEL_TE &&
  1103. gpio_is_valid(display->disp_te_gpio))
  1104. return true;
  1105. return false;
  1106. }
  1107. static ssize_t debugfs_dump_info_read(struct file *file,
  1108. char __user *user_buf,
  1109. size_t user_len,
  1110. loff_t *ppos)
  1111. {
  1112. struct dsi_display *display = file->private_data;
  1113. char *buf;
  1114. u32 len = 0;
  1115. int i;
  1116. if (!display)
  1117. return -ENODEV;
  1118. if (*ppos)
  1119. return 0;
  1120. buf = kzalloc(SZ_4K, GFP_KERNEL);
  1121. if (!buf)
  1122. return -ENOMEM;
  1123. len += snprintf(buf + len, (SZ_4K - len), "name = %s\n", display->name);
  1124. len += snprintf(buf + len, (SZ_4K - len),
  1125. "\tResolution = %dx%d\n",
  1126. display->config.video_timing.h_active,
  1127. display->config.video_timing.v_active);
  1128. display_for_each_ctrl(i, display) {
  1129. len += snprintf(buf + len, (SZ_4K - len),
  1130. "\tCTRL_%d:\n\t\tctrl = %s\n\t\tphy = %s\n",
  1131. i, display->ctrl[i].ctrl->name,
  1132. display->ctrl[i].phy->name);
  1133. }
  1134. len += snprintf(buf + len, (SZ_4K - len),
  1135. "\tPanel = %s\n", display->panel->name);
  1136. len += snprintf(buf + len, (SZ_4K - len),
  1137. "\tClock master = %s\n",
  1138. display->ctrl[display->clk_master_idx].ctrl->name);
  1139. if (len > user_len)
  1140. len = user_len;
  1141. if (copy_to_user(user_buf, buf, len)) {
  1142. kfree(buf);
  1143. return -EFAULT;
  1144. }
  1145. *ppos += len;
  1146. kfree(buf);
  1147. return len;
  1148. }
  1149. static ssize_t debugfs_misr_setup(struct file *file,
  1150. const char __user *user_buf,
  1151. size_t user_len,
  1152. loff_t *ppos)
  1153. {
  1154. struct dsi_display *display = file->private_data;
  1155. char *buf;
  1156. int rc = 0;
  1157. size_t len;
  1158. u32 enable, frame_count;
  1159. if (!display)
  1160. return -ENODEV;
  1161. if (*ppos)
  1162. return 0;
  1163. buf = kzalloc(MISR_BUFF_SIZE, GFP_KERNEL);
  1164. if (!buf)
  1165. return -ENOMEM;
  1166. /* leave room for termination char */
  1167. len = min_t(size_t, user_len, MISR_BUFF_SIZE - 1);
  1168. if (copy_from_user(buf, user_buf, len)) {
  1169. rc = -EINVAL;
  1170. goto error;
  1171. }
  1172. buf[len] = '\0'; /* terminate the string */
  1173. if (sscanf(buf, "%u %u", &enable, &frame_count) != 2) {
  1174. rc = -EINVAL;
  1175. goto error;
  1176. }
  1177. display->misr_enable = enable;
  1178. display->misr_frame_count = frame_count;
  1179. mutex_lock(&display->display_lock);
  1180. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  1181. DSI_CORE_CLK, DSI_CLK_ON);
  1182. if (rc) {
  1183. DSI_ERR("[%s] failed to enable DSI core clocks, rc=%d\n",
  1184. display->name, rc);
  1185. goto unlock;
  1186. }
  1187. _dsi_display_setup_misr(display);
  1188. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  1189. DSI_CORE_CLK, DSI_CLK_OFF);
  1190. if (rc) {
  1191. DSI_ERR("[%s] failed to disable DSI core clocks, rc=%d\n",
  1192. display->name, rc);
  1193. goto unlock;
  1194. }
  1195. rc = user_len;
  1196. unlock:
  1197. mutex_unlock(&display->display_lock);
  1198. error:
  1199. kfree(buf);
  1200. return rc;
  1201. }
  1202. static ssize_t debugfs_misr_read(struct file *file,
  1203. char __user *user_buf,
  1204. size_t user_len,
  1205. loff_t *ppos)
  1206. {
  1207. struct dsi_display *display = file->private_data;
  1208. char *buf;
  1209. u32 len = 0;
  1210. int rc = 0;
  1211. struct dsi_ctrl *dsi_ctrl;
  1212. int i;
  1213. u32 misr;
  1214. size_t max_len = min_t(size_t, user_len, MISR_BUFF_SIZE);
  1215. if (!display)
  1216. return -ENODEV;
  1217. if (*ppos)
  1218. return 0;
  1219. buf = kzalloc(max_len, GFP_KERNEL);
  1220. if (ZERO_OR_NULL_PTR(buf))
  1221. return -ENOMEM;
  1222. mutex_lock(&display->display_lock);
  1223. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  1224. DSI_CORE_CLK, DSI_CLK_ON);
  1225. if (rc) {
  1226. DSI_ERR("[%s] failed to enable DSI core clocks, rc=%d\n",
  1227. display->name, rc);
  1228. goto error;
  1229. }
  1230. display_for_each_ctrl(i, display) {
  1231. dsi_ctrl = display->ctrl[i].ctrl;
  1232. misr = dsi_ctrl_collect_misr(display->ctrl[i].ctrl);
  1233. len += snprintf((buf + len), max_len - len,
  1234. "DSI_%d MISR: 0x%x\n", dsi_ctrl->cell_index, misr);
  1235. if (len >= max_len)
  1236. break;
  1237. }
  1238. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  1239. DSI_CORE_CLK, DSI_CLK_OFF);
  1240. if (rc) {
  1241. DSI_ERR("[%s] failed to disable DSI core clocks, rc=%d\n",
  1242. display->name, rc);
  1243. goto error;
  1244. }
  1245. if (copy_to_user(user_buf, buf, max_len)) {
  1246. rc = -EFAULT;
  1247. goto error;
  1248. }
  1249. *ppos += len;
  1250. error:
  1251. mutex_unlock(&display->display_lock);
  1252. kfree(buf);
  1253. return len;
  1254. }
  1255. static ssize_t debugfs_esd_trigger_check(struct file *file,
  1256. const char __user *user_buf,
  1257. size_t user_len,
  1258. loff_t *ppos)
  1259. {
  1260. struct dsi_display *display = file->private_data;
  1261. char *buf;
  1262. int rc = 0;
  1263. struct drm_panel_esd_config *esd_config = &display->panel->esd_config;
  1264. u32 esd_trigger;
  1265. size_t len;
  1266. if (!display)
  1267. return -ENODEV;
  1268. if (*ppos)
  1269. return 0;
  1270. if (user_len > sizeof(u32))
  1271. return -EINVAL;
  1272. if (!user_len || !user_buf)
  1273. return -EINVAL;
  1274. if (!display->panel ||
  1275. atomic_read(&display->panel->esd_recovery_pending))
  1276. return user_len;
  1277. if (!esd_config->esd_enabled) {
  1278. DSI_ERR("ESD feature is not enabled\n");
  1279. return -EINVAL;
  1280. }
  1281. buf = kzalloc(ESD_TRIGGER_STRING_MAX_LEN, GFP_KERNEL);
  1282. if (!buf)
  1283. return -ENOMEM;
  1284. len = min_t(size_t, user_len, ESD_TRIGGER_STRING_MAX_LEN - 1);
  1285. if (copy_from_user(buf, user_buf, len)) {
  1286. rc = -EINVAL;
  1287. goto error;
  1288. }
  1289. buf[len] = '\0'; /* terminate the string */
  1290. if (kstrtouint(buf, 10, &esd_trigger)) {
  1291. rc = -EINVAL;
  1292. goto error;
  1293. }
  1294. if (esd_trigger != 1) {
  1295. rc = -EINVAL;
  1296. goto error;
  1297. }
  1298. display->esd_trigger = esd_trigger;
  1299. if (display->esd_trigger) {
  1300. DSI_INFO("ESD attack triggered by user\n");
  1301. rc = dsi_panel_trigger_esd_attack(display->panel,
  1302. display->trusted_vm_env);
  1303. if (rc) {
  1304. DSI_ERR("Failed to trigger ESD attack\n");
  1305. goto error;
  1306. }
  1307. }
  1308. rc = len;
  1309. error:
  1310. kfree(buf);
  1311. return rc;
  1312. }
  1313. static ssize_t debugfs_alter_esd_check_mode(struct file *file,
  1314. const char __user *user_buf,
  1315. size_t user_len,
  1316. loff_t *ppos)
  1317. {
  1318. struct dsi_display *display = file->private_data;
  1319. struct drm_panel_esd_config *esd_config;
  1320. char *buf;
  1321. int rc = 0;
  1322. size_t len;
  1323. if (!display)
  1324. return -ENODEV;
  1325. if (*ppos)
  1326. return 0;
  1327. buf = kzalloc(ESD_MODE_STRING_MAX_LEN, GFP_KERNEL);
  1328. if (ZERO_OR_NULL_PTR(buf))
  1329. return -ENOMEM;
  1330. len = min_t(size_t, user_len, ESD_MODE_STRING_MAX_LEN - 1);
  1331. if (copy_from_user(buf, user_buf, len)) {
  1332. rc = -EINVAL;
  1333. goto error;
  1334. }
  1335. buf[len] = '\0'; /* terminate the string */
  1336. if (!display->panel) {
  1337. rc = -EINVAL;
  1338. goto error;
  1339. }
  1340. esd_config = &display->panel->esd_config;
  1341. if (!esd_config) {
  1342. DSI_ERR("Invalid panel esd config\n");
  1343. rc = -EINVAL;
  1344. goto error;
  1345. }
  1346. if (!esd_config->esd_enabled) {
  1347. rc = -EINVAL;
  1348. goto error;
  1349. }
  1350. if (!strcmp(buf, "te_signal_check\n")) {
  1351. if (display->panel->panel_mode == DSI_OP_VIDEO_MODE) {
  1352. DSI_INFO("TE based ESD check for Video Mode panels is not allowed\n");
  1353. rc = -EINVAL;
  1354. goto error;
  1355. }
  1356. DSI_INFO("ESD check is switched to TE mode by user\n");
  1357. esd_config->status_mode = ESD_MODE_PANEL_TE;
  1358. dsi_display_change_te_irq_status(display, true);
  1359. }
  1360. if (!strcmp(buf, "reg_read\n")) {
  1361. DSI_INFO("ESD check is switched to reg read by user\n");
  1362. rc = dsi_panel_parse_esd_reg_read_configs(display->panel);
  1363. if (rc) {
  1364. DSI_ERR("failed to alter esd check mode,rc=%d\n",
  1365. rc);
  1366. rc = user_len;
  1367. goto error;
  1368. }
  1369. esd_config->status_mode = ESD_MODE_REG_READ;
  1370. if (dsi_display_is_te_based_esd(display))
  1371. dsi_display_change_te_irq_status(display, false);
  1372. }
  1373. if (!strcmp(buf, "esd_sw_sim_success\n"))
  1374. esd_config->status_mode = ESD_MODE_SW_SIM_SUCCESS;
  1375. if (!strcmp(buf, "esd_sw_sim_failure\n"))
  1376. esd_config->status_mode = ESD_MODE_SW_SIM_FAILURE;
  1377. rc = len;
  1378. error:
  1379. kfree(buf);
  1380. return rc;
  1381. }
  1382. static ssize_t debugfs_read_esd_check_mode(struct file *file,
  1383. char __user *user_buf,
  1384. size_t user_len,
  1385. loff_t *ppos)
  1386. {
  1387. struct dsi_display *display = file->private_data;
  1388. struct drm_panel_esd_config *esd_config;
  1389. char *buf;
  1390. int rc = 0;
  1391. size_t len = 0;
  1392. if (!display)
  1393. return -ENODEV;
  1394. if (*ppos)
  1395. return 0;
  1396. if (!display->panel) {
  1397. DSI_ERR("invalid panel data\n");
  1398. return -EINVAL;
  1399. }
  1400. buf = kzalloc(ESD_MODE_STRING_MAX_LEN, GFP_KERNEL);
  1401. if (ZERO_OR_NULL_PTR(buf))
  1402. return -ENOMEM;
  1403. esd_config = &display->panel->esd_config;
  1404. if (!esd_config) {
  1405. DSI_ERR("Invalid panel esd config\n");
  1406. rc = -EINVAL;
  1407. goto error;
  1408. }
  1409. len = min_t(size_t, user_len, ESD_MODE_STRING_MAX_LEN - 1);
  1410. if (!esd_config->esd_enabled) {
  1411. rc = snprintf(buf, len, "ESD feature not enabled");
  1412. goto output_mode;
  1413. }
  1414. switch (esd_config->status_mode) {
  1415. case ESD_MODE_REG_READ:
  1416. rc = snprintf(buf, len, "reg_read");
  1417. break;
  1418. case ESD_MODE_PANEL_TE:
  1419. rc = snprintf(buf, len, "te_signal_check");
  1420. break;
  1421. case ESD_MODE_SW_SIM_FAILURE:
  1422. rc = snprintf(buf, len, "esd_sw_sim_failure");
  1423. break;
  1424. case ESD_MODE_SW_SIM_SUCCESS:
  1425. rc = snprintf(buf, len, "esd_sw_sim_success");
  1426. break;
  1427. default:
  1428. rc = snprintf(buf, len, "invalid");
  1429. break;
  1430. }
  1431. output_mode:
  1432. if (!rc) {
  1433. rc = -EINVAL;
  1434. goto error;
  1435. }
  1436. if (copy_to_user(user_buf, buf, len)) {
  1437. rc = -EFAULT;
  1438. goto error;
  1439. }
  1440. *ppos += len;
  1441. error:
  1442. kfree(buf);
  1443. return len;
  1444. }
  1445. static ssize_t debugfs_update_cmd_scheduling_params(struct file *file,
  1446. const char __user *user_buf,
  1447. size_t user_len,
  1448. loff_t *ppos)
  1449. {
  1450. struct dsi_display *display = file->private_data;
  1451. struct dsi_display_ctrl *display_ctrl;
  1452. char *buf;
  1453. int rc = 0;
  1454. u32 line = 0, window = 0;
  1455. size_t len;
  1456. int i;
  1457. if (!display)
  1458. return -ENODEV;
  1459. if (*ppos)
  1460. return 0;
  1461. buf = kzalloc(256, GFP_KERNEL);
  1462. if (ZERO_OR_NULL_PTR(buf))
  1463. return -ENOMEM;
  1464. len = min_t(size_t, user_len, 255);
  1465. if (copy_from_user(buf, user_buf, len)) {
  1466. rc = -EINVAL;
  1467. goto error;
  1468. }
  1469. buf[len] = '\0'; /* terminate the string */
  1470. if (sscanf(buf, "%d %d", &line, &window) != 2)
  1471. return -EFAULT;
  1472. display_for_each_ctrl(i, display) {
  1473. struct dsi_ctrl *ctrl;
  1474. display_ctrl = &display->ctrl[i];
  1475. if (!display_ctrl->ctrl)
  1476. continue;
  1477. ctrl = display_ctrl->ctrl;
  1478. ctrl->host_config.common_config.dma_sched_line = line;
  1479. ctrl->host_config.common_config.dma_sched_window = window;
  1480. }
  1481. rc = len;
  1482. error:
  1483. kfree(buf);
  1484. return rc;
  1485. }
  1486. static ssize_t debugfs_read_cmd_scheduling_params(struct file *file,
  1487. char __user *user_buf,
  1488. size_t user_len,
  1489. loff_t *ppos)
  1490. {
  1491. struct dsi_display *display = file->private_data;
  1492. struct dsi_display_ctrl *m_ctrl;
  1493. struct dsi_ctrl *ctrl;
  1494. char *buf;
  1495. u32 len = 0;
  1496. int rc = 0;
  1497. size_t max_len = min_t(size_t, user_len, SZ_4K);
  1498. if (!display)
  1499. return -ENODEV;
  1500. if (*ppos)
  1501. return 0;
  1502. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1503. ctrl = m_ctrl->ctrl;
  1504. buf = kzalloc(max_len, GFP_KERNEL);
  1505. if (ZERO_OR_NULL_PTR(buf))
  1506. return -ENOMEM;
  1507. len += scnprintf(buf, max_len, "Schedule command window start: %d\n",
  1508. ctrl->host_config.common_config.dma_sched_line);
  1509. len += scnprintf((buf + len), max_len - len,
  1510. "Schedule command window width: %d\n",
  1511. ctrl->host_config.common_config.dma_sched_window);
  1512. if (len > max_len)
  1513. len = max_len;
  1514. if (copy_to_user(user_buf, buf, len)) {
  1515. rc = -EFAULT;
  1516. goto error;
  1517. }
  1518. *ppos += len;
  1519. error:
  1520. kfree(buf);
  1521. return len;
  1522. }
  1523. static const struct file_operations dump_info_fops = {
  1524. .open = simple_open,
  1525. .read = debugfs_dump_info_read,
  1526. };
  1527. static const struct file_operations misr_data_fops = {
  1528. .open = simple_open,
  1529. .read = debugfs_misr_read,
  1530. .write = debugfs_misr_setup,
  1531. };
  1532. static const struct file_operations esd_trigger_fops = {
  1533. .open = simple_open,
  1534. .write = debugfs_esd_trigger_check,
  1535. };
  1536. static const struct file_operations esd_check_mode_fops = {
  1537. .open = simple_open,
  1538. .write = debugfs_alter_esd_check_mode,
  1539. .read = debugfs_read_esd_check_mode,
  1540. };
  1541. static const struct file_operations dsi_command_scheduling_fops = {
  1542. .open = simple_open,
  1543. .write = debugfs_update_cmd_scheduling_params,
  1544. .read = debugfs_read_cmd_scheduling_params,
  1545. };
  1546. static int dsi_display_debugfs_init(struct dsi_display *display)
  1547. {
  1548. int rc = 0;
  1549. struct dentry *dir, *dump_file, *misr_data;
  1550. char name[MAX_NAME_SIZE];
  1551. char panel_name[SEC_PANEL_NAME_MAX_LEN];
  1552. char secondary_panel_str[] = "_secondary";
  1553. int i;
  1554. strlcpy(panel_name, display->name, SEC_PANEL_NAME_MAX_LEN);
  1555. if (strcmp(display->display_type, "secondary") == 0)
  1556. strlcat(panel_name, secondary_panel_str, SEC_PANEL_NAME_MAX_LEN);
  1557. dir = debugfs_create_dir(panel_name, NULL);
  1558. if (IS_ERR_OR_NULL(dir)) {
  1559. rc = PTR_ERR(dir);
  1560. DSI_ERR("[%s] debugfs create dir failed, rc = %d\n",
  1561. display->name, rc);
  1562. goto error;
  1563. }
  1564. dump_file = debugfs_create_file("dump_info",
  1565. 0400,
  1566. dir,
  1567. display,
  1568. &dump_info_fops);
  1569. if (IS_ERR_OR_NULL(dump_file)) {
  1570. rc = PTR_ERR(dump_file);
  1571. DSI_ERR("[%s] debugfs create dump info file failed, rc=%d\n",
  1572. display->name, rc);
  1573. goto error_remove_dir;
  1574. }
  1575. dump_file = debugfs_create_file("esd_trigger",
  1576. 0644,
  1577. dir,
  1578. display,
  1579. &esd_trigger_fops);
  1580. if (IS_ERR_OR_NULL(dump_file)) {
  1581. rc = PTR_ERR(dump_file);
  1582. DSI_ERR("[%s] debugfs for esd trigger file failed, rc=%d\n",
  1583. display->name, rc);
  1584. goto error_remove_dir;
  1585. }
  1586. dump_file = debugfs_create_file("esd_check_mode",
  1587. 0644,
  1588. dir,
  1589. display,
  1590. &esd_check_mode_fops);
  1591. if (IS_ERR_OR_NULL(dump_file)) {
  1592. rc = PTR_ERR(dump_file);
  1593. DSI_ERR("[%s] debugfs for esd check mode failed, rc=%d\n",
  1594. display->name, rc);
  1595. goto error_remove_dir;
  1596. }
  1597. dump_file = debugfs_create_file("cmd_sched_params",
  1598. 0644,
  1599. dir,
  1600. display,
  1601. &dsi_command_scheduling_fops);
  1602. if (IS_ERR_OR_NULL(dump_file)) {
  1603. rc = PTR_ERR(dump_file);
  1604. DSI_ERR("[%s] debugfs for cmd scheduling file failed, rc=%d\n",
  1605. display->name, rc);
  1606. goto error_remove_dir;
  1607. }
  1608. misr_data = debugfs_create_file("misr_data",
  1609. 0600,
  1610. dir,
  1611. display,
  1612. &misr_data_fops);
  1613. if (IS_ERR_OR_NULL(misr_data)) {
  1614. rc = PTR_ERR(misr_data);
  1615. DSI_ERR("[%s] debugfs create misr datafile failed, rc=%d\n",
  1616. display->name, rc);
  1617. goto error_remove_dir;
  1618. }
  1619. display_for_each_ctrl(i, display) {
  1620. struct msm_dsi_phy *phy = display->ctrl[i].phy;
  1621. if (!phy || !phy->name)
  1622. continue;
  1623. snprintf(name, ARRAY_SIZE(name),
  1624. "%s_allow_phy_power_off", phy->name);
  1625. dump_file = debugfs_create_bool(name, 0600, dir,
  1626. &phy->allow_phy_power_off);
  1627. if (IS_ERR_OR_NULL(dump_file)) {
  1628. rc = PTR_ERR(dump_file);
  1629. DSI_ERR("[%s] debugfs create %s failed, rc=%d\n",
  1630. display->name, name, rc);
  1631. goto error_remove_dir;
  1632. }
  1633. snprintf(name, ARRAY_SIZE(name),
  1634. "%s_regulator_min_datarate_bps", phy->name);
  1635. debugfs_create_u32(name, 0600, dir, &phy->regulator_min_datarate_bps);
  1636. }
  1637. if (!debugfs_create_bool("ulps_feature_enable", 0600, dir,
  1638. &display->panel->ulps_feature_enabled)) {
  1639. DSI_ERR("[%s] debugfs create ulps feature enable file failed\n",
  1640. display->name);
  1641. goto error_remove_dir;
  1642. }
  1643. if (!debugfs_create_bool("ulps_suspend_feature_enable", 0600, dir,
  1644. &display->panel->ulps_suspend_enabled)) {
  1645. DSI_ERR("[%s] debugfs create ulps-suspend feature enable file failed\n",
  1646. display->name);
  1647. goto error_remove_dir;
  1648. }
  1649. if (!debugfs_create_bool("ulps_status", 0400, dir,
  1650. &display->ulps_enabled)) {
  1651. DSI_ERR("[%s] debugfs create ulps status file failed\n",
  1652. display->name);
  1653. goto error_remove_dir;
  1654. }
  1655. debugfs_create_u32("clk_gating_config", 0600, dir, &display->clk_gating_config);
  1656. display->root = dir;
  1657. dsi_parser_dbg_init(display->parser, dir);
  1658. return rc;
  1659. error_remove_dir:
  1660. debugfs_remove(dir);
  1661. error:
  1662. return rc;
  1663. }
  1664. static int dsi_display_debugfs_deinit(struct dsi_display *display)
  1665. {
  1666. debugfs_remove_recursive(display->root);
  1667. return 0;
  1668. }
  1669. #else
  1670. static int dsi_display_debugfs_init(struct dsi_display *display)
  1671. {
  1672. return 0;
  1673. }
  1674. static int dsi_display_debugfs_deinit(struct dsi_display *display)
  1675. {
  1676. return 0;
  1677. }
  1678. #endif /* CONFIG_DEBUG_FS */
  1679. static void adjust_timing_by_ctrl_count(const struct dsi_display *display,
  1680. struct dsi_display_mode *mode)
  1681. {
  1682. struct dsi_host_common_cfg *host = &display->panel->host_config;
  1683. bool is_split_link = host->split_link.split_link_enabled;
  1684. u32 sublinks_count = host->split_link.num_sublinks;
  1685. if (is_split_link && sublinks_count > 1) {
  1686. mode->timing.h_active /= sublinks_count;
  1687. mode->timing.h_front_porch /= sublinks_count;
  1688. mode->timing.h_sync_width /= sublinks_count;
  1689. mode->timing.h_back_porch /= sublinks_count;
  1690. mode->timing.h_skew /= sublinks_count;
  1691. mode->pixel_clk_khz /= sublinks_count;
  1692. } else {
  1693. if (mode->priv_info->dsc_enabled)
  1694. mode->priv_info->dsc.config.pic_width =
  1695. mode->timing.h_active;
  1696. mode->timing.h_active /= display->ctrl_count;
  1697. mode->timing.h_front_porch /= display->ctrl_count;
  1698. mode->timing.h_sync_width /= display->ctrl_count;
  1699. mode->timing.h_back_porch /= display->ctrl_count;
  1700. mode->timing.h_skew /= display->ctrl_count;
  1701. mode->pixel_clk_khz /= display->ctrl_count;
  1702. }
  1703. }
  1704. static int dsi_display_is_ulps_req_valid(struct dsi_display *display,
  1705. bool enable)
  1706. {
  1707. /* TODO: make checks based on cont. splash */
  1708. DSI_DEBUG("checking ulps req validity\n");
  1709. if (atomic_read(&display->panel->esd_recovery_pending)) {
  1710. DSI_DEBUG("%s: ESD recovery sequence underway\n", __func__);
  1711. return false;
  1712. }
  1713. if (!dsi_panel_ulps_feature_enabled(display->panel) &&
  1714. !display->panel->ulps_suspend_enabled) {
  1715. DSI_DEBUG("%s: ULPS feature is not enabled\n", __func__);
  1716. return false;
  1717. }
  1718. if (!dsi_panel_initialized(display->panel) &&
  1719. !display->panel->ulps_suspend_enabled) {
  1720. DSI_DEBUG("%s: panel not yet initialized\n", __func__);
  1721. return false;
  1722. }
  1723. if (enable && display->ulps_enabled) {
  1724. DSI_DEBUG("ULPS already enabled\n");
  1725. return false;
  1726. } else if (!enable && !display->ulps_enabled) {
  1727. DSI_DEBUG("ULPS already disabled\n");
  1728. return false;
  1729. }
  1730. /*
  1731. * No need to enter ULPS when transitioning from splash screen to
  1732. * boot animation or trusted vm environments since it is expected
  1733. * that the clocks would be turned right back on.
  1734. */
  1735. if (enable && is_skip_op_required(display))
  1736. return false;
  1737. return true;
  1738. }
  1739. /**
  1740. * dsi_display_set_ulps() - set ULPS state for DSI lanes.
  1741. * @dsi_display: DSI display handle.
  1742. * @enable: enable/disable ULPS.
  1743. *
  1744. * ULPS can be enabled/disabled after DSI host engine is turned on.
  1745. *
  1746. * Return: error code.
  1747. */
  1748. static int dsi_display_set_ulps(struct dsi_display *display, bool enable)
  1749. {
  1750. int rc = 0;
  1751. int i = 0;
  1752. struct dsi_display_ctrl *m_ctrl, *ctrl;
  1753. if (!display) {
  1754. DSI_ERR("Invalid params\n");
  1755. return -EINVAL;
  1756. }
  1757. if (!dsi_display_is_ulps_req_valid(display, enable)) {
  1758. DSI_DEBUG("%s: skipping ULPS config, enable=%d\n",
  1759. __func__, enable);
  1760. return 0;
  1761. }
  1762. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1763. /*
  1764. * ULPS entry-exit can be either through the DSI controller or
  1765. * the DSI PHY depending on hardware variation. For some chipsets,
  1766. * both controller version and phy version ulps entry-exit ops can
  1767. * be present. To handle such cases, send ulps request through PHY,
  1768. * if ulps request is handled in PHY, then no need to send request
  1769. * through controller.
  1770. */
  1771. rc = dsi_phy_set_ulps(m_ctrl->phy, &display->config, enable,
  1772. display->clamp_enabled);
  1773. if (rc == DSI_PHY_ULPS_ERROR) {
  1774. DSI_ERR("Ulps PHY state change(%d) failed\n", enable);
  1775. return -EINVAL;
  1776. }
  1777. else if (rc == DSI_PHY_ULPS_HANDLED) {
  1778. display_for_each_ctrl(i, display) {
  1779. ctrl = &display->ctrl[i];
  1780. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1781. continue;
  1782. rc = dsi_phy_set_ulps(ctrl->phy, &display->config,
  1783. enable, display->clamp_enabled);
  1784. if (rc == DSI_PHY_ULPS_ERROR) {
  1785. DSI_ERR("Ulps PHY state change(%d) failed\n",
  1786. enable);
  1787. return -EINVAL;
  1788. }
  1789. }
  1790. }
  1791. else if (rc == DSI_PHY_ULPS_NOT_HANDLED) {
  1792. rc = dsi_ctrl_set_ulps(m_ctrl->ctrl, enable);
  1793. if (rc) {
  1794. DSI_ERR("Ulps controller state change(%d) failed\n",
  1795. enable);
  1796. return rc;
  1797. }
  1798. display_for_each_ctrl(i, display) {
  1799. ctrl = &display->ctrl[i];
  1800. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1801. continue;
  1802. rc = dsi_ctrl_set_ulps(ctrl->ctrl, enable);
  1803. if (rc) {
  1804. DSI_ERR("Ulps controller state change(%d) failed\n",
  1805. enable);
  1806. return rc;
  1807. }
  1808. }
  1809. }
  1810. display->ulps_enabled = enable;
  1811. return 0;
  1812. }
  1813. /**
  1814. * dsi_display_set_clamp() - set clamp state for DSI IO.
  1815. * @dsi_display: DSI display handle.
  1816. * @enable: enable/disable clamping.
  1817. *
  1818. * Return: error code.
  1819. */
  1820. static int dsi_display_set_clamp(struct dsi_display *display, bool enable)
  1821. {
  1822. int rc = 0;
  1823. int i = 0;
  1824. struct dsi_display_ctrl *m_ctrl, *ctrl;
  1825. bool ulps_enabled = false;
  1826. if (!display) {
  1827. DSI_ERR("Invalid params\n");
  1828. return -EINVAL;
  1829. }
  1830. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1831. ulps_enabled = display->ulps_enabled;
  1832. /*
  1833. * Clamp control can be either through the DSI controller or
  1834. * the DSI PHY depending on hardware variation
  1835. */
  1836. rc = dsi_ctrl_set_clamp_state(m_ctrl->ctrl, enable, ulps_enabled);
  1837. if (rc) {
  1838. DSI_ERR("DSI ctrl clamp state change(%d) failed\n", enable);
  1839. return rc;
  1840. }
  1841. rc = dsi_phy_set_clamp_state(m_ctrl->phy, enable);
  1842. if (rc) {
  1843. DSI_ERR("DSI phy clamp state change(%d) failed\n", enable);
  1844. return rc;
  1845. }
  1846. display_for_each_ctrl(i, display) {
  1847. ctrl = &display->ctrl[i];
  1848. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1849. continue;
  1850. rc = dsi_ctrl_set_clamp_state(ctrl->ctrl, enable, ulps_enabled);
  1851. if (rc) {
  1852. DSI_ERR("DSI Clamp state change(%d) failed\n", enable);
  1853. return rc;
  1854. }
  1855. rc = dsi_phy_set_clamp_state(ctrl->phy, enable);
  1856. if (rc) {
  1857. DSI_ERR("DSI phy clamp state change(%d) failed\n",
  1858. enable);
  1859. return rc;
  1860. }
  1861. DSI_DEBUG("Clamps %s for ctrl%d\n",
  1862. enable ? "enabled" : "disabled", i);
  1863. }
  1864. display->clamp_enabled = enable;
  1865. return 0;
  1866. }
  1867. /**
  1868. * dsi_display_setup_ctrl() - setup DSI controller.
  1869. * @dsi_display: DSI display handle.
  1870. *
  1871. * Return: error code.
  1872. */
  1873. static int dsi_display_ctrl_setup(struct dsi_display *display)
  1874. {
  1875. int rc = 0;
  1876. int i = 0;
  1877. struct dsi_display_ctrl *ctrl, *m_ctrl;
  1878. if (!display) {
  1879. DSI_ERR("Invalid params\n");
  1880. return -EINVAL;
  1881. }
  1882. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1883. rc = dsi_ctrl_setup(m_ctrl->ctrl);
  1884. if (rc) {
  1885. DSI_ERR("DSI controller setup failed\n");
  1886. return rc;
  1887. }
  1888. display_for_each_ctrl(i, display) {
  1889. ctrl = &display->ctrl[i];
  1890. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1891. continue;
  1892. rc = dsi_ctrl_setup(ctrl->ctrl);
  1893. if (rc) {
  1894. DSI_ERR("DSI controller setup failed\n");
  1895. return rc;
  1896. }
  1897. }
  1898. return 0;
  1899. }
  1900. static int dsi_display_phy_enable(struct dsi_display *display);
  1901. /**
  1902. * dsi_display_phy_idle_on() - enable DSI PHY while coming out of idle screen.
  1903. * @dsi_display: DSI display handle.
  1904. * @mmss_clamp: True if clamp is enabled.
  1905. *
  1906. * Return: error code.
  1907. */
  1908. static int dsi_display_phy_idle_on(struct dsi_display *display,
  1909. bool mmss_clamp)
  1910. {
  1911. int rc = 0;
  1912. int i = 0;
  1913. struct dsi_display_ctrl *m_ctrl, *ctrl;
  1914. if (!display) {
  1915. DSI_ERR("Invalid params\n");
  1916. return -EINVAL;
  1917. }
  1918. if (mmss_clamp && !display->phy_idle_power_off) {
  1919. dsi_display_phy_enable(display);
  1920. return 0;
  1921. }
  1922. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1923. rc = dsi_phy_idle_ctrl(m_ctrl->phy, true);
  1924. if (rc) {
  1925. DSI_ERR("DSI controller setup failed\n");
  1926. return rc;
  1927. }
  1928. display_for_each_ctrl(i, display) {
  1929. ctrl = &display->ctrl[i];
  1930. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1931. continue;
  1932. rc = dsi_phy_idle_ctrl(ctrl->phy, true);
  1933. if (rc) {
  1934. DSI_ERR("DSI controller setup failed\n");
  1935. return rc;
  1936. }
  1937. }
  1938. display->phy_idle_power_off = false;
  1939. return 0;
  1940. }
  1941. /**
  1942. * dsi_display_phy_idle_off() - disable DSI PHY while going to idle screen.
  1943. * @dsi_display: DSI display handle.
  1944. *
  1945. * Return: error code.
  1946. */
  1947. static int dsi_display_phy_idle_off(struct dsi_display *display)
  1948. {
  1949. int rc = 0;
  1950. int i = 0;
  1951. struct dsi_display_ctrl *m_ctrl, *ctrl;
  1952. if (!display) {
  1953. DSI_ERR("Invalid params\n");
  1954. return -EINVAL;
  1955. }
  1956. display_for_each_ctrl(i, display) {
  1957. struct msm_dsi_phy *phy = display->ctrl[i].phy;
  1958. if (!phy)
  1959. continue;
  1960. if (!phy->allow_phy_power_off) {
  1961. DSI_DEBUG("phy doesn't support this feature\n");
  1962. return 0;
  1963. }
  1964. }
  1965. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1966. rc = dsi_phy_idle_ctrl(m_ctrl->phy, false);
  1967. if (rc) {
  1968. DSI_ERR("[%s] failed to enable cmd engine, rc=%d\n",
  1969. display->name, rc);
  1970. return rc;
  1971. }
  1972. display_for_each_ctrl(i, display) {
  1973. ctrl = &display->ctrl[i];
  1974. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1975. continue;
  1976. rc = dsi_phy_idle_ctrl(ctrl->phy, false);
  1977. if (rc) {
  1978. DSI_ERR("DSI controller setup failed\n");
  1979. return rc;
  1980. }
  1981. }
  1982. display->phy_idle_power_off = true;
  1983. return 0;
  1984. }
  1985. void dsi_display_enable_event(struct drm_connector *connector,
  1986. struct dsi_display *display,
  1987. uint32_t event_idx, struct dsi_event_cb_info *event_info,
  1988. bool enable)
  1989. {
  1990. uint32_t irq_status_idx = DSI_STATUS_INTERRUPT_COUNT;
  1991. int i;
  1992. if (!display) {
  1993. DSI_ERR("invalid display\n");
  1994. return;
  1995. }
  1996. if (event_info)
  1997. event_info->event_idx = event_idx;
  1998. switch (event_idx) {
  1999. case SDE_CONN_EVENT_VID_DONE:
  2000. irq_status_idx = DSI_SINT_VIDEO_MODE_FRAME_DONE;
  2001. break;
  2002. case SDE_CONN_EVENT_CMD_DONE:
  2003. irq_status_idx = DSI_SINT_CMD_FRAME_DONE;
  2004. break;
  2005. case SDE_CONN_EVENT_VID_FIFO_OVERFLOW:
  2006. case SDE_CONN_EVENT_CMD_FIFO_UNDERFLOW:
  2007. if (event_info) {
  2008. display_for_each_ctrl(i, display)
  2009. display->ctrl[i].ctrl->recovery_cb =
  2010. *event_info;
  2011. }
  2012. break;
  2013. case SDE_CONN_EVENT_PANEL_ID:
  2014. if (event_info)
  2015. display_for_each_ctrl(i, display)
  2016. display->ctrl[i].ctrl->panel_id_cb
  2017. = *event_info;
  2018. break;
  2019. default:
  2020. /* nothing to do */
  2021. DSI_DEBUG("[%s] unhandled event %d\n", display->name, event_idx);
  2022. return;
  2023. }
  2024. if (enable) {
  2025. display_for_each_ctrl(i, display)
  2026. dsi_ctrl_enable_status_interrupt(
  2027. display->ctrl[i].ctrl, irq_status_idx,
  2028. event_info);
  2029. } else {
  2030. display_for_each_ctrl(i, display)
  2031. dsi_ctrl_disable_status_interrupt(
  2032. display->ctrl[i].ctrl, irq_status_idx);
  2033. }
  2034. }
  2035. static int dsi_display_ctrl_power_on(struct dsi_display *display)
  2036. {
  2037. int rc = 0;
  2038. int i;
  2039. struct dsi_display_ctrl *ctrl;
  2040. /* Sequence does not matter for split dsi usecases */
  2041. display_for_each_ctrl(i, display) {
  2042. ctrl = &display->ctrl[i];
  2043. if (!ctrl->ctrl)
  2044. continue;
  2045. rc = dsi_ctrl_set_power_state(ctrl->ctrl,
  2046. DSI_CTRL_POWER_VREG_ON);
  2047. if (rc) {
  2048. DSI_ERR("[%s] Failed to set power state, rc=%d\n",
  2049. ctrl->ctrl->name, rc);
  2050. goto error;
  2051. }
  2052. }
  2053. return rc;
  2054. error:
  2055. for (i = i - 1; i >= 0; i--) {
  2056. ctrl = &display->ctrl[i];
  2057. if (!ctrl->ctrl)
  2058. continue;
  2059. (void)dsi_ctrl_set_power_state(ctrl->ctrl,
  2060. DSI_CTRL_POWER_VREG_OFF);
  2061. }
  2062. return rc;
  2063. }
  2064. static int dsi_display_ctrl_power_off(struct dsi_display *display)
  2065. {
  2066. int rc = 0;
  2067. int i;
  2068. struct dsi_display_ctrl *ctrl;
  2069. /* Sequence does not matter for split dsi usecases */
  2070. display_for_each_ctrl(i, display) {
  2071. ctrl = &display->ctrl[i];
  2072. if (!ctrl->ctrl)
  2073. continue;
  2074. rc = dsi_ctrl_set_power_state(ctrl->ctrl,
  2075. DSI_CTRL_POWER_VREG_OFF);
  2076. if (rc) {
  2077. DSI_ERR("[%s] Failed to power off, rc=%d\n",
  2078. ctrl->ctrl->name, rc);
  2079. goto error;
  2080. }
  2081. }
  2082. error:
  2083. return rc;
  2084. }
  2085. static void dsi_display_parse_cmdline_topology(struct dsi_display *display,
  2086. unsigned int display_type)
  2087. {
  2088. char *boot_str = NULL;
  2089. char *str = NULL;
  2090. char *sw_te = NULL;
  2091. unsigned long cmdline_topology = NO_OVERRIDE;
  2092. unsigned long cmdline_timing = NO_OVERRIDE;
  2093. unsigned long panel_id = NO_OVERRIDE;
  2094. if (display_type >= MAX_DSI_ACTIVE_DISPLAY) {
  2095. DSI_ERR("display_type=%d not supported\n", display_type);
  2096. goto end;
  2097. }
  2098. if (display_type == DSI_PRIMARY)
  2099. boot_str = dsi_display_primary;
  2100. else
  2101. boot_str = dsi_display_secondary;
  2102. sw_te = strnstr(boot_str, ":sim-swte", strlen(boot_str));
  2103. if (sw_te)
  2104. display->sw_te_using_wd = true;
  2105. str = strnstr(boot_str, ":panelid", strlen(boot_str));
  2106. if (str) {
  2107. if (kstrtol(str + strlen(":panelid"), INT_BASE_10,
  2108. (unsigned long *)&panel_id)) {
  2109. DSI_INFO("panel id not found: %s\n", boot_str);
  2110. } else {
  2111. DSI_INFO("panel id found: %lx\n", panel_id);
  2112. display->panel_id = panel_id;
  2113. }
  2114. }
  2115. str = strnstr(boot_str, ":config", strlen(boot_str));
  2116. if (str) {
  2117. if (sscanf(str, ":config%lu", &cmdline_topology) != 1) {
  2118. DSI_ERR("invalid config index override: %s\n",
  2119. boot_str);
  2120. goto end;
  2121. }
  2122. }
  2123. str = strnstr(boot_str, ":timing", strlen(boot_str));
  2124. if (str) {
  2125. if (sscanf(str, ":timing%lu", &cmdline_timing) != 1) {
  2126. DSI_ERR("invalid timing index override: %s\n",
  2127. boot_str);
  2128. cmdline_topology = NO_OVERRIDE;
  2129. goto end;
  2130. }
  2131. }
  2132. DSI_DEBUG("successfully parsed command line topology and timing\n");
  2133. end:
  2134. display->cmdline_topology = cmdline_topology;
  2135. display->cmdline_timing = cmdline_timing;
  2136. }
  2137. /**
  2138. * dsi_display_parse_boot_display_selection()- Parse DSI boot display name
  2139. *
  2140. * Return: returns error status
  2141. */
  2142. static int dsi_display_parse_boot_display_selection(void)
  2143. {
  2144. char *pos = NULL;
  2145. char disp_buf[MAX_CMDLINE_PARAM_LEN] = {'\0'};
  2146. int i, j;
  2147. for (i = 0; i < MAX_DSI_ACTIVE_DISPLAY; i++) {
  2148. strlcpy(disp_buf, boot_displays[i].boot_param,
  2149. MAX_CMDLINE_PARAM_LEN);
  2150. pos = strnstr(disp_buf, ":", MAX_CMDLINE_PARAM_LEN);
  2151. /* Use ':' as a delimiter to retrieve the display name */
  2152. if (!pos) {
  2153. DSI_DEBUG("display name[%s]is not valid\n", disp_buf);
  2154. continue;
  2155. }
  2156. for (j = 0; (disp_buf + j) < pos; j++)
  2157. boot_displays[i].name[j] = *(disp_buf + j);
  2158. boot_displays[i].name[j] = '\0';
  2159. boot_displays[i].boot_disp_en = true;
  2160. }
  2161. return 0;
  2162. }
  2163. static int dsi_display_phy_power_on(struct dsi_display *display)
  2164. {
  2165. int rc = 0;
  2166. int i;
  2167. struct dsi_display_ctrl *ctrl;
  2168. /* Sequence does not matter for split dsi usecases */
  2169. display_for_each_ctrl(i, display) {
  2170. ctrl = &display->ctrl[i];
  2171. if (!ctrl->ctrl)
  2172. continue;
  2173. rc = dsi_phy_set_power_state(ctrl->phy, true);
  2174. if (rc) {
  2175. DSI_ERR("[%s] Failed to set power state, rc=%d\n",
  2176. ctrl->phy->name, rc);
  2177. goto error;
  2178. }
  2179. }
  2180. return rc;
  2181. error:
  2182. for (i = i - 1; i >= 0; i--) {
  2183. ctrl = &display->ctrl[i];
  2184. if (!ctrl->phy)
  2185. continue;
  2186. (void)dsi_phy_set_power_state(ctrl->phy, false);
  2187. }
  2188. return rc;
  2189. }
  2190. static int dsi_display_phy_power_off(struct dsi_display *display)
  2191. {
  2192. int rc = 0;
  2193. int i;
  2194. struct dsi_display_ctrl *ctrl;
  2195. /* Sequence does not matter for split dsi usecases */
  2196. display_for_each_ctrl(i, display) {
  2197. ctrl = &display->ctrl[i];
  2198. if (!ctrl->phy)
  2199. continue;
  2200. rc = dsi_phy_set_power_state(ctrl->phy, false);
  2201. if (rc) {
  2202. DSI_ERR("[%s] Failed to power off, rc=%d\n",
  2203. ctrl->ctrl->name, rc);
  2204. goto error;
  2205. }
  2206. }
  2207. error:
  2208. return rc;
  2209. }
  2210. static int dsi_display_set_clk_src(struct dsi_display *display, bool set_xo)
  2211. {
  2212. int rc = 0;
  2213. int i;
  2214. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2215. struct dsi_ctrl_clk_info *info;
  2216. if (display->trusted_vm_env)
  2217. return 0;
  2218. /*
  2219. * In case of split DSI usecases, the clock for master controller should
  2220. * be enabled before the other controller. Master controller in the
  2221. * clock context refers to the controller that sources the clock. While turning off the
  2222. * clocks, the source is set to xo.
  2223. */
  2224. m_ctrl = &display->ctrl[display->clk_master_idx];
  2225. info = &m_ctrl->ctrl->clk_info;
  2226. if (!set_xo)
  2227. rc = dsi_ctrl_set_clock_source(m_ctrl->ctrl, &display->clock_info.pll_clks);
  2228. else if ((info->xo_clk.byte_clk) && (info->xo_clk.pixel_clk))
  2229. rc = dsi_ctrl_set_clock_source(m_ctrl->ctrl, &info->xo_clk);
  2230. if (rc) {
  2231. DSI_ERR("[%s] failed to set source clocks for master, rc=%d\n", display->name, rc);
  2232. return rc;
  2233. }
  2234. /* Set source for the rest of the controllers */
  2235. display_for_each_ctrl(i, display) {
  2236. ctrl = &display->ctrl[i];
  2237. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2238. continue;
  2239. info = &ctrl->ctrl->clk_info;
  2240. if (!set_xo)
  2241. rc = dsi_ctrl_set_clock_source(ctrl->ctrl, &display->clock_info.pll_clks);
  2242. else if ((info->xo_clk.byte_clk) && (info->xo_clk.pixel_clk))
  2243. rc = dsi_ctrl_set_clock_source(ctrl->ctrl, &info->xo_clk);
  2244. if (rc) {
  2245. DSI_ERR("[%s] failed to set source clocks, rc=%d\n", display->name, rc);
  2246. return rc;
  2247. }
  2248. }
  2249. return 0;
  2250. }
  2251. int dsi_display_phy_pll_toggle(void *priv, bool prepare)
  2252. {
  2253. int rc = 0;
  2254. struct dsi_display *display = priv;
  2255. struct dsi_display_ctrl *m_ctrl;
  2256. if (!display) {
  2257. DSI_ERR("invalid arguments\n");
  2258. return -EINVAL;
  2259. }
  2260. rc = dsi_display_set_clk_src(display, !prepare);
  2261. m_ctrl = &display->ctrl[display->clk_master_idx];
  2262. if (!m_ctrl->phy) {
  2263. DSI_ERR("[%s] PHY not found\n", display->name);
  2264. return -EINVAL;
  2265. }
  2266. rc = dsi_phy_pll_toggle(m_ctrl->phy, prepare);
  2267. return rc;
  2268. }
  2269. int dsi_display_phy_configure(void *priv, bool commit)
  2270. {
  2271. int rc = 0;
  2272. struct dsi_display *display = priv;
  2273. struct dsi_display_ctrl *m_ctrl;
  2274. struct dsi_pll_resource *pll_res;
  2275. struct dsi_ctrl *ctrl;
  2276. if (!display) {
  2277. DSI_ERR("invalid arguments\n");
  2278. return -EINVAL;
  2279. }
  2280. m_ctrl = &display->ctrl[display->clk_master_idx];
  2281. if ((!m_ctrl->phy) || (!m_ctrl->ctrl)) {
  2282. DSI_ERR("[%s] PHY not found\n", display->name);
  2283. return -EINVAL;
  2284. }
  2285. pll_res = m_ctrl->phy->pll;
  2286. if (!pll_res) {
  2287. DSI_ERR("[%s] PLL res not found\n", display->name);
  2288. return -EINVAL;
  2289. }
  2290. ctrl = m_ctrl->ctrl;
  2291. pll_res->byteclk_rate = ctrl->clk_freq.byte_clk_rate;
  2292. pll_res->pclk_rate = ctrl->clk_freq.pix_clk_rate;
  2293. rc = dsi_phy_configure(m_ctrl->phy, commit);
  2294. return rc;
  2295. }
  2296. static int dsi_display_phy_reset_config(struct dsi_display *display,
  2297. bool enable)
  2298. {
  2299. int rc = 0;
  2300. int i;
  2301. struct dsi_display_ctrl *ctrl;
  2302. display_for_each_ctrl(i, display) {
  2303. ctrl = &display->ctrl[i];
  2304. rc = dsi_ctrl_phy_reset_config(ctrl->ctrl, enable);
  2305. if (rc) {
  2306. DSI_ERR("[%s] failed to %s phy reset, rc=%d\n",
  2307. display->name, enable ? "mask" : "unmask", rc);
  2308. return rc;
  2309. }
  2310. }
  2311. return 0;
  2312. }
  2313. static void dsi_display_toggle_resync_fifo(struct dsi_display *display)
  2314. {
  2315. struct dsi_display_ctrl *ctrl;
  2316. int i;
  2317. if (!display)
  2318. return;
  2319. display_for_each_ctrl(i, display) {
  2320. ctrl = &display->ctrl[i];
  2321. dsi_phy_toggle_resync_fifo(ctrl->phy);
  2322. }
  2323. /*
  2324. * After retime buffer synchronization we need to turn of clk_en_sel
  2325. * bit on each phy. Avoid this for Cphy.
  2326. */
  2327. if (display->panel->host_config.phy_type == DSI_PHY_TYPE_CPHY)
  2328. return;
  2329. display_for_each_ctrl(i, display) {
  2330. ctrl = &display->ctrl[i];
  2331. dsi_phy_reset_clk_en_sel(ctrl->phy);
  2332. }
  2333. }
  2334. static int dsi_display_ctrl_update(struct dsi_display *display)
  2335. {
  2336. int rc = 0;
  2337. int i;
  2338. struct dsi_display_ctrl *ctrl;
  2339. display_for_each_ctrl(i, display) {
  2340. ctrl = &display->ctrl[i];
  2341. rc = dsi_ctrl_host_timing_update(ctrl->ctrl);
  2342. if (rc) {
  2343. DSI_ERR("[%s] failed to update host_%d, rc=%d\n",
  2344. display->name, i, rc);
  2345. goto error_host_deinit;
  2346. }
  2347. }
  2348. return 0;
  2349. error_host_deinit:
  2350. for (i = i - 1; i >= 0; i--) {
  2351. ctrl = &display->ctrl[i];
  2352. (void)dsi_ctrl_host_deinit(ctrl->ctrl);
  2353. }
  2354. return rc;
  2355. }
  2356. static int dsi_display_ctrl_init(struct dsi_display *display)
  2357. {
  2358. int rc = 0;
  2359. int i;
  2360. struct dsi_display_ctrl *ctrl;
  2361. bool skip_op = is_skip_op_required(display);
  2362. /* when ULPS suspend feature is enabled, we will keep the lanes in
  2363. * ULPS during suspend state and clamp DSI phy. Hence while resuming
  2364. * we will programe DSI controller as part of core clock enable.
  2365. * After that we should not re-configure DSI controller again here for
  2366. * usecases where we are resuming from ulps suspend as it might put
  2367. * the HW in bad state.
  2368. */
  2369. if (!display->panel->ulps_suspend_enabled || !display->ulps_enabled) {
  2370. display_for_each_ctrl(i, display) {
  2371. ctrl = &display->ctrl[i];
  2372. rc = dsi_ctrl_host_init(ctrl->ctrl, skip_op);
  2373. if (rc) {
  2374. DSI_ERR(
  2375. "[%s] failed to init host_%d, skip_op=%d, rc=%d\n",
  2376. display->name, i, skip_op, rc);
  2377. goto error_host_deinit;
  2378. }
  2379. }
  2380. } else {
  2381. display_for_each_ctrl(i, display) {
  2382. ctrl = &display->ctrl[i];
  2383. rc = dsi_ctrl_update_host_state(ctrl->ctrl,
  2384. DSI_CTRL_OP_HOST_INIT,
  2385. true);
  2386. if (rc)
  2387. DSI_DEBUG("host init update failed rc=%d\n",
  2388. rc);
  2389. }
  2390. }
  2391. return rc;
  2392. error_host_deinit:
  2393. for (i = i - 1; i >= 0; i--) {
  2394. ctrl = &display->ctrl[i];
  2395. (void)dsi_ctrl_host_deinit(ctrl->ctrl);
  2396. }
  2397. return rc;
  2398. }
  2399. static int dsi_display_ctrl_deinit(struct dsi_display *display)
  2400. {
  2401. int rc = 0;
  2402. int i;
  2403. struct dsi_display_ctrl *ctrl;
  2404. display_for_each_ctrl(i, display) {
  2405. ctrl = &display->ctrl[i];
  2406. rc = dsi_ctrl_host_deinit(ctrl->ctrl);
  2407. if (rc) {
  2408. DSI_ERR("[%s] failed to deinit host_%d, rc=%d\n",
  2409. display->name, i, rc);
  2410. }
  2411. }
  2412. return rc;
  2413. }
  2414. static int dsi_display_ctrl_host_enable(struct dsi_display *display)
  2415. {
  2416. int rc = 0;
  2417. int i;
  2418. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2419. bool skip_op = is_skip_op_required(display);
  2420. m_ctrl = &display->ctrl[display->cmd_master_idx];
  2421. rc = dsi_ctrl_set_host_engine_state(m_ctrl->ctrl,
  2422. DSI_CTRL_ENGINE_ON, skip_op);
  2423. if (rc) {
  2424. DSI_ERR("[%s]enable host engine failed, skip_op:%d rc:%d\n",
  2425. display->name, skip_op, rc);
  2426. goto error;
  2427. }
  2428. display_for_each_ctrl(i, display) {
  2429. ctrl = &display->ctrl[i];
  2430. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2431. continue;
  2432. rc = dsi_ctrl_set_host_engine_state(ctrl->ctrl,
  2433. DSI_CTRL_ENGINE_ON, skip_op);
  2434. if (rc) {
  2435. DSI_ERR(
  2436. "[%s] enable host engine failed, skip_op:%d rc:%d\n",
  2437. display->name, skip_op, rc);
  2438. goto error_disable_master;
  2439. }
  2440. }
  2441. return rc;
  2442. error_disable_master:
  2443. (void)dsi_ctrl_set_host_engine_state(m_ctrl->ctrl,
  2444. DSI_CTRL_ENGINE_OFF, skip_op);
  2445. error:
  2446. return rc;
  2447. }
  2448. static int dsi_display_ctrl_host_disable(struct dsi_display *display)
  2449. {
  2450. int rc = 0;
  2451. int i;
  2452. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2453. bool skip_op = is_skip_op_required(display);
  2454. m_ctrl = &display->ctrl[display->cmd_master_idx];
  2455. /*
  2456. * For platforms where ULPS is controlled by DSI controller block,
  2457. * do not disable dsi controller block if lanes are to be
  2458. * kept in ULPS during suspend. So just update the SW state
  2459. * and return early.
  2460. */
  2461. if (display->panel->ulps_suspend_enabled &&
  2462. !m_ctrl->phy->hw.ops.ulps_ops.ulps_request) {
  2463. display_for_each_ctrl(i, display) {
  2464. ctrl = &display->ctrl[i];
  2465. rc = dsi_ctrl_update_host_state(ctrl->ctrl,
  2466. DSI_CTRL_OP_HOST_ENGINE,
  2467. false);
  2468. if (rc)
  2469. DSI_DEBUG("host state update failed %d\n", rc);
  2470. }
  2471. return rc;
  2472. }
  2473. display_for_each_ctrl(i, display) {
  2474. ctrl = &display->ctrl[i];
  2475. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2476. continue;
  2477. rc = dsi_ctrl_set_host_engine_state(ctrl->ctrl,
  2478. DSI_CTRL_ENGINE_OFF, skip_op);
  2479. if (rc)
  2480. DSI_ERR(
  2481. "[%s] disable host engine failed, skip_op:%d rc:%d\n",
  2482. display->name, skip_op, rc);
  2483. }
  2484. rc = dsi_ctrl_set_host_engine_state(m_ctrl->ctrl,
  2485. DSI_CTRL_ENGINE_OFF, skip_op);
  2486. if (rc) {
  2487. DSI_ERR("[%s] disable mhost engine failed, skip_op:%d rc:%d\n",
  2488. display->name, skip_op, rc);
  2489. goto error;
  2490. }
  2491. error:
  2492. return rc;
  2493. }
  2494. static int dsi_display_vid_engine_enable(struct dsi_display *display)
  2495. {
  2496. int rc = 0;
  2497. int i;
  2498. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2499. bool skip_op = is_skip_op_required(display);
  2500. m_ctrl = &display->ctrl[display->video_master_idx];
  2501. rc = dsi_ctrl_set_vid_engine_state(m_ctrl->ctrl,
  2502. DSI_CTRL_ENGINE_ON, skip_op);
  2503. if (rc) {
  2504. DSI_ERR("[%s] enable mvid engine failed, skip_op:%d rc:%d\n",
  2505. display->name, skip_op, rc);
  2506. goto error;
  2507. }
  2508. display_for_each_ctrl(i, display) {
  2509. ctrl = &display->ctrl[i];
  2510. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2511. continue;
  2512. rc = dsi_ctrl_set_vid_engine_state(ctrl->ctrl,
  2513. DSI_CTRL_ENGINE_ON, skip_op);
  2514. if (rc) {
  2515. DSI_ERR(
  2516. "[%s] enable vid engine failed, skip_op:%d rc:%d\n",
  2517. display->name, skip_op, rc);
  2518. goto error_disable_master;
  2519. }
  2520. }
  2521. return rc;
  2522. error_disable_master:
  2523. (void)dsi_ctrl_set_vid_engine_state(m_ctrl->ctrl,
  2524. DSI_CTRL_ENGINE_OFF, skip_op);
  2525. error:
  2526. return rc;
  2527. }
  2528. static int dsi_display_vid_engine_disable(struct dsi_display *display)
  2529. {
  2530. int rc = 0;
  2531. int i;
  2532. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2533. bool skip_op = is_skip_op_required(display);
  2534. m_ctrl = &display->ctrl[display->video_master_idx];
  2535. display_for_each_ctrl(i, display) {
  2536. ctrl = &display->ctrl[i];
  2537. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2538. continue;
  2539. rc = dsi_ctrl_set_vid_engine_state(ctrl->ctrl,
  2540. DSI_CTRL_ENGINE_OFF, skip_op);
  2541. if (rc)
  2542. DSI_ERR(
  2543. "[%s] disable vid engine failed, skip_op:%d rc:%d\n",
  2544. display->name, skip_op, rc);
  2545. }
  2546. rc = dsi_ctrl_set_vid_engine_state(m_ctrl->ctrl,
  2547. DSI_CTRL_ENGINE_OFF, skip_op);
  2548. if (rc)
  2549. DSI_ERR("[%s] disable mvid engine failed, skip_op:%d rc:%d\n",
  2550. display->name, skip_op, rc);
  2551. return rc;
  2552. }
  2553. static int dsi_display_phy_enable(struct dsi_display *display)
  2554. {
  2555. int rc = 0;
  2556. int i;
  2557. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2558. enum dsi_phy_pll_source m_src = DSI_PLL_SOURCE_STANDALONE;
  2559. bool skip_op = is_skip_op_required(display);
  2560. m_ctrl = &display->ctrl[display->clk_master_idx];
  2561. if (display->ctrl_count > 1)
  2562. m_src = DSI_PLL_SOURCE_NATIVE;
  2563. rc = dsi_phy_enable(m_ctrl->phy, &display->config,
  2564. m_src, true, skip_op);
  2565. if (rc) {
  2566. DSI_ERR("[%s] failed to enable DSI PHY, skip_op=%d rc=%d\n",
  2567. display->name, skip_op, rc);
  2568. goto error;
  2569. }
  2570. display_for_each_ctrl(i, display) {
  2571. ctrl = &display->ctrl[i];
  2572. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2573. continue;
  2574. rc = dsi_phy_enable(ctrl->phy, &display->config,
  2575. DSI_PLL_SOURCE_NON_NATIVE, true, skip_op);
  2576. if (rc) {
  2577. DSI_ERR(
  2578. "[%s] failed to enable DSI PHY, skip_op: %d rc=%d\n",
  2579. display->name, skip_op, rc);
  2580. goto error_disable_master;
  2581. }
  2582. }
  2583. return rc;
  2584. error_disable_master:
  2585. (void)dsi_phy_disable(m_ctrl->phy, skip_op);
  2586. error:
  2587. return rc;
  2588. }
  2589. static int dsi_display_phy_disable(struct dsi_display *display)
  2590. {
  2591. int rc = 0;
  2592. int i;
  2593. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2594. bool skip_op = is_skip_op_required(display);
  2595. m_ctrl = &display->ctrl[display->clk_master_idx];
  2596. display_for_each_ctrl(i, display) {
  2597. ctrl = &display->ctrl[i];
  2598. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2599. continue;
  2600. rc = dsi_phy_disable(ctrl->phy, skip_op);
  2601. if (rc)
  2602. DSI_ERR(
  2603. "[%s] failed to disable DSI PHY, skip_op=%d rc=%d\n",
  2604. display->name, skip_op, rc);
  2605. }
  2606. rc = dsi_phy_disable(m_ctrl->phy, skip_op);
  2607. if (rc)
  2608. DSI_ERR("[%s] failed to disable DSI PHY, skip_op=%d rc=%d\n",
  2609. display->name, skip_op, rc);
  2610. return rc;
  2611. }
  2612. static int dsi_display_wake_up(struct dsi_display *display)
  2613. {
  2614. return 0;
  2615. }
  2616. static void dsi_display_mask_overflow(struct dsi_display *display, u32 flags,
  2617. bool enable)
  2618. {
  2619. struct dsi_display_ctrl *ctrl;
  2620. int i;
  2621. if (!(flags & DSI_CTRL_CMD_LAST_COMMAND))
  2622. return;
  2623. display_for_each_ctrl(i, display) {
  2624. ctrl = &display->ctrl[i];
  2625. if (!ctrl)
  2626. continue;
  2627. dsi_ctrl_mask_overflow(ctrl->ctrl, enable);
  2628. }
  2629. }
  2630. static int dsi_display_broadcast_cmd(struct dsi_display *display, struct dsi_cmd_desc *cmd)
  2631. {
  2632. int rc = 0;
  2633. struct dsi_display_ctrl *ctrl, *m_ctrl;
  2634. int i;
  2635. /*
  2636. * 1. Setup commands in FIFO
  2637. * 2. Trigger commands
  2638. */
  2639. m_ctrl = &display->ctrl[display->cmd_master_idx];
  2640. dsi_display_mask_overflow(display, cmd->ctrl_flags, true);
  2641. cmd->ctrl_flags |= DSI_CTRL_CMD_BROADCAST_MASTER;
  2642. rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, cmd);
  2643. if (rc) {
  2644. DSI_ERR("[%s] cmd transfer failed on master,rc=%d\n",
  2645. display->name, rc);
  2646. goto error;
  2647. }
  2648. cmd->ctrl_flags &= ~DSI_CTRL_CMD_BROADCAST_MASTER;
  2649. display_for_each_ctrl(i, display) {
  2650. ctrl = &display->ctrl[i];
  2651. if (ctrl == m_ctrl)
  2652. continue;
  2653. rc = dsi_ctrl_cmd_transfer(ctrl->ctrl, cmd);
  2654. if (rc) {
  2655. DSI_ERR("[%s] cmd transfer failed, rc=%d\n",
  2656. display->name, rc);
  2657. goto error;
  2658. }
  2659. rc = dsi_ctrl_cmd_tx_trigger(ctrl->ctrl, cmd->ctrl_flags);
  2660. if (rc) {
  2661. DSI_ERR("[%s] cmd trigger failed, rc=%d\n",
  2662. display->name, rc);
  2663. goto error;
  2664. }
  2665. }
  2666. rc = dsi_ctrl_cmd_tx_trigger(m_ctrl->ctrl, cmd->ctrl_flags | DSI_CTRL_CMD_BROADCAST_MASTER);
  2667. if (rc) {
  2668. DSI_ERR("[%s] cmd trigger failed for master, rc=%d\n",
  2669. display->name, rc);
  2670. goto error;
  2671. }
  2672. error:
  2673. dsi_display_mask_overflow(display, cmd->ctrl_flags, false);
  2674. return rc;
  2675. }
  2676. static int dsi_display_phy_sw_reset(struct dsi_display *display)
  2677. {
  2678. int rc = 0;
  2679. int i;
  2680. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2681. /*
  2682. * For continuous splash and trusted vm environment,
  2683. * ctrl states are updated separately and hence we do
  2684. * an early return
  2685. */
  2686. if (is_skip_op_required(display)) {
  2687. DSI_DEBUG(
  2688. "cont splash/trusted vm use case, phy sw reset not required\n");
  2689. return 0;
  2690. }
  2691. m_ctrl = &display->ctrl[display->cmd_master_idx];
  2692. rc = dsi_ctrl_phy_sw_reset(m_ctrl->ctrl);
  2693. if (rc) {
  2694. DSI_ERR("[%s] failed to reset phy, rc=%d\n", display->name, rc);
  2695. goto error;
  2696. }
  2697. display_for_each_ctrl(i, display) {
  2698. ctrl = &display->ctrl[i];
  2699. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2700. continue;
  2701. rc = dsi_ctrl_phy_sw_reset(ctrl->ctrl);
  2702. if (rc) {
  2703. DSI_ERR("[%s] failed to reset phy, rc=%d\n",
  2704. display->name, rc);
  2705. goto error;
  2706. }
  2707. }
  2708. error:
  2709. return rc;
  2710. }
  2711. static int dsi_host_attach(struct mipi_dsi_host *host,
  2712. struct mipi_dsi_device *dsi)
  2713. {
  2714. return 0;
  2715. }
  2716. static int dsi_host_detach(struct mipi_dsi_host *host,
  2717. struct mipi_dsi_device *dsi)
  2718. {
  2719. return 0;
  2720. }
  2721. int dsi_host_transfer_sub(struct mipi_dsi_host *host, struct dsi_cmd_desc *cmd)
  2722. {
  2723. struct dsi_display *display;
  2724. int rc = 0, ret = 0;
  2725. if (!host || !cmd) {
  2726. DSI_ERR("Invalid params\n");
  2727. return 0;
  2728. }
  2729. display = to_dsi_display(host);
  2730. /* Avoid sending DCS commands when ESD recovery is pending */
  2731. if (atomic_read(&display->panel->esd_recovery_pending)) {
  2732. DSI_DEBUG("ESD recovery pending\n");
  2733. return 0;
  2734. }
  2735. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  2736. DSI_ALL_CLKS, DSI_CLK_ON);
  2737. if (rc) {
  2738. DSI_ERR("[%s] failed to enable all DSI clocks, rc=%d\n",
  2739. display->name, rc);
  2740. goto error;
  2741. }
  2742. rc = dsi_display_wake_up(display);
  2743. if (rc) {
  2744. DSI_ERR("[%s] failed to wake up display, rc=%d\n",
  2745. display->name, rc);
  2746. goto error_disable_clks;
  2747. }
  2748. rc = dsi_display_cmd_engine_enable(display);
  2749. if (rc) {
  2750. DSI_ERR("[%s] failed to enable cmd engine, rc=%d\n",
  2751. display->name, rc);
  2752. goto error_disable_clks;
  2753. }
  2754. if (display->tx_cmd_buf == NULL) {
  2755. rc = dsi_host_alloc_cmd_tx_buffer(display);
  2756. if (rc) {
  2757. DSI_ERR("failed to allocate cmd tx buffer memory\n");
  2758. goto error_disable_cmd_engine;
  2759. }
  2760. }
  2761. dsi_display_set_cmd_tx_ctrl_flags(display, cmd);
  2762. if (cmd->ctrl_flags & DSI_CTRL_CMD_BROADCAST) {
  2763. rc = dsi_display_broadcast_cmd(display, cmd);
  2764. if (rc) {
  2765. DSI_ERR("[%s] cmd broadcast failed, rc=%d\n", display->name, rc);
  2766. goto error_disable_cmd_engine;
  2767. }
  2768. } else {
  2769. int idx = cmd->ctrl;
  2770. rc = dsi_ctrl_cmd_transfer(display->ctrl[idx].ctrl, cmd);
  2771. if (rc) {
  2772. DSI_ERR("[%s] cmd transfer failed, rc=%d\n",
  2773. display->name, rc);
  2774. goto error_disable_cmd_engine;
  2775. }
  2776. }
  2777. error_disable_cmd_engine:
  2778. ret = dsi_display_cmd_engine_disable(display);
  2779. if (ret) {
  2780. DSI_ERR("[%s]failed to disable DSI cmd engine, rc=%d\n",
  2781. display->name, ret);
  2782. }
  2783. error_disable_clks:
  2784. ret = dsi_display_clk_ctrl(display->dsi_clk_handle,
  2785. DSI_ALL_CLKS, DSI_CLK_OFF);
  2786. if (ret) {
  2787. DSI_ERR("[%s] failed to disable all DSI clocks, rc=%d\n",
  2788. display->name, ret);
  2789. }
  2790. error:
  2791. return rc;
  2792. }
  2793. static ssize_t dsi_host_transfer(struct mipi_dsi_host *host, const struct mipi_dsi_msg *msg)
  2794. {
  2795. int rc = 0;
  2796. struct dsi_cmd_desc cmd;
  2797. if (!msg) {
  2798. DSI_ERR("Invalid params\n");
  2799. return 0;
  2800. }
  2801. memcpy(&cmd.msg, msg, sizeof(*msg));
  2802. cmd.ctrl = 0;
  2803. cmd.post_wait_ms = 0;
  2804. cmd.ctrl_flags = 0;
  2805. rc = dsi_host_transfer_sub(host, &cmd);
  2806. return rc;
  2807. }
  2808. static struct mipi_dsi_host_ops dsi_host_ops = {
  2809. .attach = dsi_host_attach,
  2810. .detach = dsi_host_detach,
  2811. .transfer = dsi_host_transfer,
  2812. };
  2813. static int dsi_display_mipi_host_init(struct dsi_display *display)
  2814. {
  2815. int rc = 0;
  2816. struct mipi_dsi_host *host = &display->host;
  2817. host->dev = &display->pdev->dev;
  2818. host->ops = &dsi_host_ops;
  2819. rc = mipi_dsi_host_register(host);
  2820. if (rc) {
  2821. DSI_ERR("[%s] failed to register mipi dsi host, rc=%d\n",
  2822. display->name, rc);
  2823. goto error;
  2824. }
  2825. error:
  2826. return rc;
  2827. }
  2828. static int dsi_display_mipi_host_deinit(struct dsi_display *display)
  2829. {
  2830. int rc = 0;
  2831. struct mipi_dsi_host *host = &display->host;
  2832. mipi_dsi_host_unregister(host);
  2833. host->dev = NULL;
  2834. host->ops = NULL;
  2835. return rc;
  2836. }
  2837. static bool dsi_display_check_prefix(const char *clk_prefix,
  2838. const char *clk_name)
  2839. {
  2840. return !!strnstr(clk_name, clk_prefix, strlen(clk_name));
  2841. }
  2842. static int dsi_display_get_clocks_count(struct dsi_display *display,
  2843. char *dsi_clk_name)
  2844. {
  2845. if (display->fw)
  2846. return dsi_parser_count_strings(display->parser_node,
  2847. dsi_clk_name);
  2848. else
  2849. return of_property_count_strings(display->panel_node,
  2850. dsi_clk_name);
  2851. }
  2852. static void dsi_display_get_clock_name(struct dsi_display *display,
  2853. char *dsi_clk_name, int index,
  2854. const char **clk_name)
  2855. {
  2856. if (display->fw)
  2857. dsi_parser_read_string_index(display->parser_node,
  2858. dsi_clk_name, index, clk_name);
  2859. else
  2860. of_property_read_string_index(display->panel_node,
  2861. dsi_clk_name, index, clk_name);
  2862. }
  2863. static int dsi_display_clocks_init(struct dsi_display *display)
  2864. {
  2865. int i, rc = 0, num_clk = 0;
  2866. const char *clk_name;
  2867. const char *pll_byte = "pll_byte", *pll_dsi = "pll_dsi";
  2868. struct clk *dsi_clk;
  2869. struct dsi_clk_link_set *pll = &display->clock_info.pll_clks;
  2870. char *dsi_clock_name;
  2871. if (!strcmp(display->display_type, "primary"))
  2872. dsi_clock_name = "qcom,dsi-select-clocks";
  2873. else
  2874. dsi_clock_name = "qcom,dsi-select-sec-clocks";
  2875. num_clk = dsi_display_get_clocks_count(display, dsi_clock_name);
  2876. for (i = 0; i < num_clk; i++) {
  2877. dsi_display_get_clock_name(display, dsi_clock_name, i,
  2878. &clk_name);
  2879. DSI_DEBUG("clock name:%s\n", clk_name);
  2880. dsi_clk = devm_clk_get(&display->pdev->dev, clk_name);
  2881. if (IS_ERR_OR_NULL(dsi_clk)) {
  2882. rc = PTR_ERR(dsi_clk);
  2883. DSI_ERR("failed to get %s, rc=%d\n", clk_name, rc);
  2884. if (dsi_display_check_prefix(pll_byte, clk_name)) {
  2885. pll->byte_clk = NULL;
  2886. goto error;
  2887. }
  2888. if (dsi_display_check_prefix(pll_dsi, clk_name)) {
  2889. pll->pixel_clk = NULL;
  2890. goto error;
  2891. }
  2892. }
  2893. if (dsi_display_check_prefix(pll_byte, clk_name)) {
  2894. pll->byte_clk = dsi_clk;
  2895. continue;
  2896. }
  2897. if (dsi_display_check_prefix(pll_dsi, clk_name)) {
  2898. pll->pixel_clk = dsi_clk;
  2899. continue;
  2900. }
  2901. }
  2902. return 0;
  2903. error:
  2904. return rc;
  2905. }
  2906. static int dsi_display_clk_ctrl_cb(void *priv,
  2907. struct dsi_clk_ctrl_info clk_state_info)
  2908. {
  2909. int rc = 0;
  2910. struct dsi_display *display = NULL;
  2911. void *clk_handle = NULL;
  2912. if (!priv) {
  2913. DSI_ERR("Invalid params\n");
  2914. return -EINVAL;
  2915. }
  2916. display = priv;
  2917. if (clk_state_info.client == DSI_CLK_REQ_MDP_CLIENT) {
  2918. clk_handle = display->mdp_clk_handle;
  2919. } else if (clk_state_info.client == DSI_CLK_REQ_DSI_CLIENT) {
  2920. clk_handle = display->dsi_clk_handle;
  2921. } else {
  2922. DSI_ERR("invalid clk handle, return error\n");
  2923. return -EINVAL;
  2924. }
  2925. /*
  2926. * TODO: Wait for CMD_MDP_DONE interrupt if MDP client tries
  2927. * to turn off DSI clocks.
  2928. */
  2929. rc = dsi_display_clk_ctrl(clk_handle,
  2930. clk_state_info.clk_type, clk_state_info.clk_state);
  2931. if (rc) {
  2932. DSI_ERR("[%s] failed to %d DSI %d clocks, rc=%d\n",
  2933. display->name, clk_state_info.clk_state,
  2934. clk_state_info.clk_type, rc);
  2935. return rc;
  2936. }
  2937. return 0;
  2938. }
  2939. static void dsi_display_ctrl_isr_configure(struct dsi_display *display, bool en)
  2940. {
  2941. int i;
  2942. struct dsi_display_ctrl *ctrl;
  2943. if (!display)
  2944. return;
  2945. display_for_each_ctrl(i, display) {
  2946. ctrl = &display->ctrl[i];
  2947. if (!ctrl)
  2948. continue;
  2949. dsi_ctrl_isr_configure(ctrl->ctrl, en);
  2950. }
  2951. }
  2952. int dsi_pre_clkoff_cb(void *priv,
  2953. enum dsi_clk_type clk,
  2954. enum dsi_lclk_type l_type,
  2955. enum dsi_clk_state new_state)
  2956. {
  2957. int rc = 0, i;
  2958. struct dsi_display *display = priv;
  2959. struct dsi_display_ctrl *ctrl;
  2960. /*
  2961. * If Idle Power Collapse occurs immediately after a CMD
  2962. * transfer with an asynchronous wait for DMA done, ensure
  2963. * that the work queued is scheduled and completed before turning
  2964. * off the clocks and disabling interrupts to validate the command
  2965. * transfer.
  2966. */
  2967. display_for_each_ctrl(i, display) {
  2968. ctrl = &display->ctrl[i];
  2969. if (!ctrl->ctrl || !ctrl->ctrl->dma_wait_queued)
  2970. continue;
  2971. flush_workqueue(display->dma_cmd_workq);
  2972. cancel_work_sync(&ctrl->ctrl->dma_cmd_wait);
  2973. ctrl->ctrl->dma_wait_queued = false;
  2974. }
  2975. if ((clk & DSI_LINK_CLK) && (new_state == DSI_CLK_OFF) &&
  2976. (l_type & DSI_LINK_LP_CLK)) {
  2977. /*
  2978. * If continuous clock is enabled then disable it
  2979. * before entering into ULPS Mode.
  2980. */
  2981. if (display->panel->host_config.force_hs_clk_lane)
  2982. _dsi_display_continuous_clk_ctrl(display, false);
  2983. /*
  2984. * If ULPS feature is enabled, enter ULPS first.
  2985. * However, when blanking the panel, we should enter ULPS
  2986. * only if ULPS during suspend feature is enabled.
  2987. */
  2988. if (!dsi_panel_initialized(display->panel)) {
  2989. if (display->panel->ulps_suspend_enabled)
  2990. rc = dsi_display_set_ulps(display, true);
  2991. } else if (dsi_panel_ulps_feature_enabled(display->panel)) {
  2992. rc = dsi_display_set_ulps(display, true);
  2993. }
  2994. if (rc)
  2995. DSI_ERR("%s: failed enable ulps, rc = %d\n",
  2996. __func__, rc);
  2997. }
  2998. if ((clk & DSI_LINK_CLK) && (new_state == DSI_CLK_OFF) &&
  2999. (l_type & DSI_LINK_HS_CLK)) {
  3000. /*
  3001. * PHY clock gating should be disabled before the PLL and the
  3002. * branch clocks are turned off. Otherwise, it is possible that
  3003. * the clock RCGs may not be turned off correctly resulting
  3004. * in clock warnings.
  3005. */
  3006. rc = dsi_display_config_clk_gating(display, false);
  3007. if (rc)
  3008. DSI_ERR("[%s] failed to disable clk gating, rc=%d\n",
  3009. display->name, rc);
  3010. }
  3011. if ((clk & DSI_CORE_CLK) && (new_state == DSI_CLK_OFF)) {
  3012. /*
  3013. * Enable DSI clamps only if entering idle power collapse or
  3014. * when ULPS during suspend is enabled..
  3015. */
  3016. if (dsi_panel_initialized(display->panel) ||
  3017. display->panel->ulps_suspend_enabled) {
  3018. dsi_display_phy_idle_off(display);
  3019. rc = dsi_display_set_clamp(display, true);
  3020. if (rc)
  3021. DSI_ERR("%s: Failed to enable dsi clamps. rc=%d\n",
  3022. __func__, rc);
  3023. rc = dsi_display_phy_reset_config(display, false);
  3024. if (rc)
  3025. DSI_ERR("%s: Failed to reset phy, rc=%d\n",
  3026. __func__, rc);
  3027. } else {
  3028. /* Make sure that controller is not in ULPS state when
  3029. * the DSI link is not active.
  3030. */
  3031. rc = dsi_display_set_ulps(display, false);
  3032. if (rc)
  3033. DSI_ERR("%s: failed to disable ulps. rc=%d\n",
  3034. __func__, rc);
  3035. }
  3036. /* dsi will not be able to serve irqs from here on */
  3037. dsi_display_ctrl_irq_update(display, false);
  3038. /* cache the MISR values */
  3039. display_for_each_ctrl(i, display) {
  3040. ctrl = &display->ctrl[i];
  3041. if (!ctrl->ctrl)
  3042. continue;
  3043. dsi_ctrl_cache_misr(ctrl->ctrl);
  3044. }
  3045. }
  3046. return rc;
  3047. }
  3048. int dsi_post_clkon_cb(void *priv,
  3049. enum dsi_clk_type clk,
  3050. enum dsi_lclk_type l_type,
  3051. enum dsi_clk_state curr_state)
  3052. {
  3053. int rc = 0;
  3054. struct dsi_display *display = priv;
  3055. bool mmss_clamp = false;
  3056. if ((clk & DSI_LINK_CLK) && (l_type & DSI_LINK_LP_CLK)) {
  3057. mmss_clamp = display->clamp_enabled;
  3058. /*
  3059. * controller setup is needed if coming out of idle
  3060. * power collapse with clamps enabled.
  3061. */
  3062. if (mmss_clamp)
  3063. dsi_display_ctrl_setup(display);
  3064. /*
  3065. * Phy setup is needed if coming out of idle
  3066. * power collapse with clamps enabled.
  3067. */
  3068. if (display->phy_idle_power_off || mmss_clamp)
  3069. dsi_display_phy_idle_on(display, mmss_clamp);
  3070. if (display->ulps_enabled && mmss_clamp) {
  3071. /*
  3072. * ULPS Entry Request. This is needed if the lanes were
  3073. * in ULPS prior to power collapse, since after
  3074. * power collapse and reset, the DSI controller resets
  3075. * back to idle state and not ULPS. This ulps entry
  3076. * request will transition the state of the DSI
  3077. * controller to ULPS which will match the state of the
  3078. * DSI phy. This needs to be done prior to disabling
  3079. * the DSI clamps.
  3080. *
  3081. * Also, reset the ulps flag so that ulps_config
  3082. * function would reconfigure the controller state to
  3083. * ULPS.
  3084. */
  3085. display->ulps_enabled = false;
  3086. rc = dsi_display_set_ulps(display, true);
  3087. if (rc) {
  3088. DSI_ERR("%s: Failed to enter ULPS. rc=%d\n",
  3089. __func__, rc);
  3090. goto error;
  3091. }
  3092. }
  3093. rc = dsi_display_phy_reset_config(display, true);
  3094. if (rc) {
  3095. DSI_ERR("%s: Failed to reset phy, rc=%d\n",
  3096. __func__, rc);
  3097. goto error;
  3098. }
  3099. rc = dsi_display_set_clamp(display, false);
  3100. if (rc) {
  3101. DSI_ERR("%s: Failed to disable dsi clamps. rc=%d\n",
  3102. __func__, rc);
  3103. goto error;
  3104. }
  3105. }
  3106. if ((clk & DSI_LINK_CLK) && (l_type & DSI_LINK_HS_CLK)) {
  3107. /*
  3108. * Toggle the resync FIFO everytime clock changes, except
  3109. * when cont-splash screen transition is going on.
  3110. * Toggling resync FIFO during cont splash transition
  3111. * can lead to blinks on the display.
  3112. */
  3113. if (!display->is_cont_splash_enabled)
  3114. dsi_display_toggle_resync_fifo(display);
  3115. if (display->ulps_enabled) {
  3116. rc = dsi_display_set_ulps(display, false);
  3117. if (rc) {
  3118. DSI_ERR("%s: failed to disable ulps, rc= %d\n",
  3119. __func__, rc);
  3120. goto error;
  3121. }
  3122. }
  3123. if (display->panel->host_config.force_hs_clk_lane)
  3124. _dsi_display_continuous_clk_ctrl(display, true);
  3125. rc = dsi_display_config_clk_gating(display, true);
  3126. if (rc) {
  3127. DSI_ERR("[%s] failed to enable clk gating %d\n",
  3128. display->name, rc);
  3129. goto error;
  3130. }
  3131. }
  3132. /* enable dsi to serve irqs */
  3133. if (clk & DSI_CORE_CLK)
  3134. dsi_display_ctrl_irq_update(display, true);
  3135. error:
  3136. return rc;
  3137. }
  3138. int dsi_post_clkoff_cb(void *priv,
  3139. enum dsi_clk_type clk_type,
  3140. enum dsi_lclk_type l_type,
  3141. enum dsi_clk_state curr_state)
  3142. {
  3143. int rc = 0;
  3144. struct dsi_display *display = priv;
  3145. if (!display) {
  3146. DSI_ERR("%s: Invalid arg\n", __func__);
  3147. return -EINVAL;
  3148. }
  3149. if ((clk_type & DSI_CORE_CLK) &&
  3150. (curr_state == DSI_CLK_OFF)) {
  3151. rc = dsi_display_phy_power_off(display);
  3152. if (rc)
  3153. DSI_ERR("[%s] failed to power off PHY, rc=%d\n",
  3154. display->name, rc);
  3155. rc = dsi_display_ctrl_power_off(display);
  3156. if (rc)
  3157. DSI_ERR("[%s] failed to power DSI vregs, rc=%d\n",
  3158. display->name, rc);
  3159. }
  3160. return rc;
  3161. }
  3162. int dsi_pre_clkon_cb(void *priv,
  3163. enum dsi_clk_type clk_type,
  3164. enum dsi_lclk_type l_type,
  3165. enum dsi_clk_state new_state)
  3166. {
  3167. int rc = 0;
  3168. struct dsi_display *display = priv;
  3169. if (!display) {
  3170. DSI_ERR("%s: invalid input\n", __func__);
  3171. return -EINVAL;
  3172. }
  3173. if ((clk_type & DSI_CORE_CLK) && (new_state == DSI_CLK_ON)) {
  3174. /*
  3175. * Enable DSI core power
  3176. * 1.> PANEL_PM are controlled as part of
  3177. * panel_power_ctrl. Needed not be handled here.
  3178. * 2.> CTRL_PM need to be enabled/disabled
  3179. * only during unblank/blank. Their state should
  3180. * not be changed during static screen.
  3181. */
  3182. DSI_DEBUG("updating power states for ctrl and phy\n");
  3183. rc = dsi_display_ctrl_power_on(display);
  3184. if (rc) {
  3185. DSI_ERR("[%s] failed to power on dsi controllers, rc=%d\n",
  3186. display->name, rc);
  3187. return rc;
  3188. }
  3189. rc = dsi_display_phy_power_on(display);
  3190. if (rc) {
  3191. DSI_ERR("[%s] failed to power on dsi phy, rc = %d\n",
  3192. display->name, rc);
  3193. return rc;
  3194. }
  3195. DSI_DEBUG("%s: Enable DSI core power\n", __func__);
  3196. }
  3197. return rc;
  3198. }
  3199. static void __set_lane_map_v2(u8 *lane_map_v2,
  3200. enum dsi_phy_data_lanes lane0,
  3201. enum dsi_phy_data_lanes lane1,
  3202. enum dsi_phy_data_lanes lane2,
  3203. enum dsi_phy_data_lanes lane3)
  3204. {
  3205. lane_map_v2[DSI_LOGICAL_LANE_0] = lane0;
  3206. lane_map_v2[DSI_LOGICAL_LANE_1] = lane1;
  3207. lane_map_v2[DSI_LOGICAL_LANE_2] = lane2;
  3208. lane_map_v2[DSI_LOGICAL_LANE_3] = lane3;
  3209. }
  3210. static int dsi_display_parse_lane_map(struct dsi_display *display)
  3211. {
  3212. int rc = 0, i = 0;
  3213. const char *data;
  3214. u8 temp[DSI_LANE_MAX - 1];
  3215. if (!display) {
  3216. DSI_ERR("invalid params\n");
  3217. return -EINVAL;
  3218. }
  3219. /* lane-map-v2 supersedes lane-map-v1 setting */
  3220. rc = of_property_read_u8_array(display->pdev->dev.of_node,
  3221. "qcom,lane-map-v2", temp, (DSI_LANE_MAX - 1));
  3222. if (!rc) {
  3223. for (i = DSI_LOGICAL_LANE_0; i < (DSI_LANE_MAX - 1); i++)
  3224. display->lane_map.lane_map_v2[i] = BIT(temp[i]);
  3225. return 0;
  3226. } else if (rc != EINVAL) {
  3227. DSI_DEBUG("Incorrect mapping, configure default\n");
  3228. goto set_default;
  3229. }
  3230. /* lane-map older version, for DSI controller version < 2.0 */
  3231. data = of_get_property(display->pdev->dev.of_node,
  3232. "qcom,lane-map", NULL);
  3233. if (!data)
  3234. goto set_default;
  3235. if (!strcmp(data, "lane_map_3012")) {
  3236. display->lane_map.lane_map_v1 = DSI_LANE_MAP_3012;
  3237. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3238. DSI_PHYSICAL_LANE_1,
  3239. DSI_PHYSICAL_LANE_2,
  3240. DSI_PHYSICAL_LANE_3,
  3241. DSI_PHYSICAL_LANE_0);
  3242. } else if (!strcmp(data, "lane_map_2301")) {
  3243. display->lane_map.lane_map_v1 = DSI_LANE_MAP_2301;
  3244. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3245. DSI_PHYSICAL_LANE_2,
  3246. DSI_PHYSICAL_LANE_3,
  3247. DSI_PHYSICAL_LANE_0,
  3248. DSI_PHYSICAL_LANE_1);
  3249. } else if (!strcmp(data, "lane_map_1230")) {
  3250. display->lane_map.lane_map_v1 = DSI_LANE_MAP_1230;
  3251. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3252. DSI_PHYSICAL_LANE_3,
  3253. DSI_PHYSICAL_LANE_0,
  3254. DSI_PHYSICAL_LANE_1,
  3255. DSI_PHYSICAL_LANE_2);
  3256. } else if (!strcmp(data, "lane_map_0321")) {
  3257. display->lane_map.lane_map_v1 = DSI_LANE_MAP_0321;
  3258. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3259. DSI_PHYSICAL_LANE_0,
  3260. DSI_PHYSICAL_LANE_3,
  3261. DSI_PHYSICAL_LANE_2,
  3262. DSI_PHYSICAL_LANE_1);
  3263. } else if (!strcmp(data, "lane_map_1032")) {
  3264. display->lane_map.lane_map_v1 = DSI_LANE_MAP_1032;
  3265. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3266. DSI_PHYSICAL_LANE_1,
  3267. DSI_PHYSICAL_LANE_0,
  3268. DSI_PHYSICAL_LANE_3,
  3269. DSI_PHYSICAL_LANE_2);
  3270. } else if (!strcmp(data, "lane_map_2103")) {
  3271. display->lane_map.lane_map_v1 = DSI_LANE_MAP_2103;
  3272. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3273. DSI_PHYSICAL_LANE_2,
  3274. DSI_PHYSICAL_LANE_1,
  3275. DSI_PHYSICAL_LANE_0,
  3276. DSI_PHYSICAL_LANE_3);
  3277. } else if (!strcmp(data, "lane_map_3210")) {
  3278. display->lane_map.lane_map_v1 = DSI_LANE_MAP_3210;
  3279. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3280. DSI_PHYSICAL_LANE_3,
  3281. DSI_PHYSICAL_LANE_2,
  3282. DSI_PHYSICAL_LANE_1,
  3283. DSI_PHYSICAL_LANE_0);
  3284. } else {
  3285. DSI_WARN("%s: invalid lane map %s specified. defaulting to lane_map0123\n",
  3286. __func__, data);
  3287. goto set_default;
  3288. }
  3289. return 0;
  3290. set_default:
  3291. /* default lane mapping */
  3292. __set_lane_map_v2(display->lane_map.lane_map_v2, DSI_PHYSICAL_LANE_0,
  3293. DSI_PHYSICAL_LANE_1, DSI_PHYSICAL_LANE_2, DSI_PHYSICAL_LANE_3);
  3294. display->lane_map.lane_map_v1 = DSI_LANE_MAP_0123;
  3295. return 0;
  3296. }
  3297. static int dsi_display_get_phandle_index(
  3298. struct dsi_display *display,
  3299. const char *propname, int count, int index)
  3300. {
  3301. struct device_node *disp_node = display->panel_node;
  3302. u32 *val = NULL;
  3303. int rc = 0;
  3304. val = kcalloc(count, sizeof(*val), GFP_KERNEL);
  3305. if (ZERO_OR_NULL_PTR(val)) {
  3306. rc = -ENOMEM;
  3307. goto end;
  3308. }
  3309. if (index >= count)
  3310. goto end;
  3311. if (display->fw)
  3312. rc = dsi_parser_read_u32_array(display->parser_node,
  3313. propname, val, count);
  3314. else
  3315. rc = of_property_read_u32_array(disp_node, propname,
  3316. val, count);
  3317. if (rc)
  3318. goto end;
  3319. rc = val[index];
  3320. DSI_DEBUG("%s index=%d\n", propname, rc);
  3321. end:
  3322. kfree(val);
  3323. return rc;
  3324. }
  3325. static int dsi_display_get_phandle_count(struct dsi_display *display,
  3326. const char *propname)
  3327. {
  3328. if (display->fw)
  3329. return dsi_parser_count_u32_elems(display->parser_node,
  3330. propname);
  3331. else
  3332. return of_property_count_u32_elems(display->panel_node,
  3333. propname);
  3334. }
  3335. static int dsi_display_parse_dt(struct dsi_display *display)
  3336. {
  3337. int i, rc = 0;
  3338. u32 phy_count = 0;
  3339. struct device_node *of_node = display->pdev->dev.of_node;
  3340. char *dsi_ctrl_name, *dsi_phy_name;
  3341. if (!strcmp(display->display_type, "primary")) {
  3342. dsi_ctrl_name = "qcom,dsi-ctrl-num";
  3343. dsi_phy_name = "qcom,dsi-phy-num";
  3344. } else {
  3345. dsi_ctrl_name = "qcom,dsi-sec-ctrl-num";
  3346. dsi_phy_name = "qcom,dsi-sec-phy-num";
  3347. }
  3348. display->ctrl_count = dsi_display_get_phandle_count(display,
  3349. dsi_ctrl_name);
  3350. phy_count = dsi_display_get_phandle_count(display, dsi_phy_name);
  3351. DSI_DEBUG("ctrl count=%d, phy count=%d\n",
  3352. display->ctrl_count, phy_count);
  3353. if (!phy_count || !display->ctrl_count) {
  3354. DSI_ERR("no ctrl/phys found\n");
  3355. rc = -ENODEV;
  3356. goto error;
  3357. }
  3358. if (phy_count != display->ctrl_count) {
  3359. DSI_ERR("different ctrl and phy counts\n");
  3360. rc = -ENODEV;
  3361. goto error;
  3362. }
  3363. display_for_each_ctrl(i, display) {
  3364. struct dsi_display_ctrl *ctrl = &display->ctrl[i];
  3365. int index;
  3366. index = dsi_display_get_phandle_index(display, dsi_ctrl_name,
  3367. display->ctrl_count, i);
  3368. ctrl->ctrl_of_node = of_parse_phandle(of_node,
  3369. "qcom,dsi-ctrl", index);
  3370. of_node_put(ctrl->ctrl_of_node);
  3371. index = dsi_display_get_phandle_index(display, dsi_phy_name,
  3372. display->ctrl_count, i);
  3373. ctrl->phy_of_node = of_parse_phandle(of_node,
  3374. "qcom,dsi-phy", index);
  3375. of_node_put(ctrl->phy_of_node);
  3376. }
  3377. /* Parse TE data */
  3378. dsi_display_parse_te_data(display);
  3379. /* Parse all external bridges from port 0 */
  3380. display_for_each_ctrl(i, display) {
  3381. display->ext_bridge[i].node_of =
  3382. of_graph_get_remote_node(of_node, 0, i);
  3383. if (display->ext_bridge[i].node_of)
  3384. display->ext_bridge_cnt++;
  3385. else
  3386. break;
  3387. }
  3388. DSI_DEBUG("success\n");
  3389. error:
  3390. return rc;
  3391. }
  3392. static int dsi_display_validate_resources(struct dsi_display *display)
  3393. {
  3394. int rc = 0;
  3395. int i;
  3396. struct dsi_display_ctrl *ctrl;
  3397. display_for_each_ctrl(i, display) {
  3398. ctrl = &display->ctrl[i];
  3399. ctrl->ctrl = dsi_ctrl_get(ctrl->ctrl_of_node);
  3400. if (IS_ERR_OR_NULL(ctrl->ctrl)) {
  3401. rc = PTR_ERR(ctrl->ctrl);
  3402. DSI_ERR("failed to get dsi controller, rc=%d\n", rc);
  3403. ctrl->ctrl = NULL;
  3404. goto error;
  3405. }
  3406. ctrl->phy = dsi_phy_get(ctrl->phy_of_node);
  3407. if (IS_ERR_OR_NULL(ctrl->phy)) {
  3408. rc = PTR_ERR(ctrl->phy);
  3409. DSI_ERR("failed to get phy controller, rc=%d\n", rc);
  3410. dsi_ctrl_put(ctrl->ctrl);
  3411. ctrl->phy = NULL;
  3412. goto error;
  3413. }
  3414. }
  3415. return rc;
  3416. error:
  3417. for (i = i - 1; i >= 0; i--) {
  3418. ctrl = &display->ctrl[i];
  3419. dsi_ctrl_put(ctrl->ctrl);
  3420. dsi_phy_put(ctrl->phy);
  3421. }
  3422. return -EPROBE_DEFER;
  3423. }
  3424. static int dsi_display_res_init(struct dsi_display *display)
  3425. {
  3426. int rc = 0;
  3427. int i;
  3428. display->panel = dsi_panel_get(&display->pdev->dev,
  3429. display->panel_node,
  3430. display->parser_node,
  3431. display->display_type,
  3432. display->cmdline_topology,
  3433. display->trusted_vm_env);
  3434. if (IS_ERR_OR_NULL(display->panel)) {
  3435. rc = PTR_ERR(display->panel);
  3436. DSI_ERR("failed to get panel, rc=%d\n", rc);
  3437. display->panel = NULL;
  3438. goto error;
  3439. }
  3440. display_for_each_ctrl(i, display) {
  3441. struct msm_dsi_phy *phy = display->ctrl[i].phy;
  3442. phy->cfg.force_clk_lane_hs =
  3443. display->panel->host_config.force_hs_clk_lane;
  3444. phy->cfg.phy_type =
  3445. display->panel->host_config.phy_type;
  3446. }
  3447. rc = dsi_display_parse_lane_map(display);
  3448. if (rc) {
  3449. DSI_ERR("Lane map not found, rc=%d\n", rc);
  3450. goto error;
  3451. }
  3452. rc = dsi_display_clocks_init(display);
  3453. if (rc) {
  3454. DSI_ERR("Failed to parse clock data, rc=%d\n", rc);
  3455. goto error;
  3456. }
  3457. /**
  3458. * In trusted vm, the connectors will not be enabled
  3459. * until the HW resources are assigned and accepted.
  3460. */
  3461. if (display->trusted_vm_env)
  3462. display->is_active = false;
  3463. else
  3464. display->is_active = true;
  3465. error:
  3466. return rc;
  3467. }
  3468. static int dsi_display_res_deinit(struct dsi_display *display)
  3469. {
  3470. int rc = 0;
  3471. int i;
  3472. struct dsi_display_ctrl *ctrl;
  3473. display_for_each_ctrl(i, display) {
  3474. ctrl = &display->ctrl[i];
  3475. dsi_phy_put(ctrl->phy);
  3476. dsi_ctrl_put(ctrl->ctrl);
  3477. }
  3478. if (display->panel)
  3479. dsi_panel_put(display->panel);
  3480. return rc;
  3481. }
  3482. static int dsi_display_validate_mode_set(struct dsi_display *display,
  3483. struct dsi_display_mode *mode,
  3484. u32 flags)
  3485. {
  3486. int rc = 0;
  3487. int i;
  3488. struct dsi_display_ctrl *ctrl;
  3489. /*
  3490. * To set a mode:
  3491. * 1. Controllers should be turned off.
  3492. * 2. Link clocks should be off.
  3493. * 3. Phy should be disabled.
  3494. */
  3495. display_for_each_ctrl(i, display) {
  3496. ctrl = &display->ctrl[i];
  3497. if ((ctrl->power_state > DSI_CTRL_POWER_VREG_ON) ||
  3498. (ctrl->phy_enabled)) {
  3499. rc = -EINVAL;
  3500. goto error;
  3501. }
  3502. }
  3503. error:
  3504. return rc;
  3505. }
  3506. static bool dsi_display_is_seamless_dfps_possible(
  3507. const struct dsi_display *display,
  3508. const struct dsi_display_mode *tgt,
  3509. const enum dsi_dfps_type dfps_type)
  3510. {
  3511. struct dsi_display_mode *cur;
  3512. if (!display || !tgt || !display->panel) {
  3513. DSI_ERR("Invalid params\n");
  3514. return false;
  3515. }
  3516. cur = display->panel->cur_mode;
  3517. if (cur->timing.h_active != tgt->timing.h_active) {
  3518. DSI_DEBUG("timing.h_active differs %d %d\n",
  3519. cur->timing.h_active, tgt->timing.h_active);
  3520. return false;
  3521. }
  3522. if (cur->timing.h_back_porch != tgt->timing.h_back_porch) {
  3523. DSI_DEBUG("timing.h_back_porch differs %d %d\n",
  3524. cur->timing.h_back_porch,
  3525. tgt->timing.h_back_porch);
  3526. return false;
  3527. }
  3528. if (cur->timing.h_sync_width != tgt->timing.h_sync_width) {
  3529. DSI_DEBUG("timing.h_sync_width differs %d %d\n",
  3530. cur->timing.h_sync_width,
  3531. tgt->timing.h_sync_width);
  3532. return false;
  3533. }
  3534. if (cur->timing.h_front_porch != tgt->timing.h_front_porch) {
  3535. DSI_DEBUG("timing.h_front_porch differs %d %d\n",
  3536. cur->timing.h_front_porch,
  3537. tgt->timing.h_front_porch);
  3538. if (dfps_type != DSI_DFPS_IMMEDIATE_HFP)
  3539. return false;
  3540. }
  3541. if (cur->timing.h_skew != tgt->timing.h_skew) {
  3542. DSI_DEBUG("timing.h_skew differs %d %d\n",
  3543. cur->timing.h_skew,
  3544. tgt->timing.h_skew);
  3545. return false;
  3546. }
  3547. /* skip polarity comparison */
  3548. if (cur->timing.v_active != tgt->timing.v_active) {
  3549. DSI_DEBUG("timing.v_active differs %d %d\n",
  3550. cur->timing.v_active,
  3551. tgt->timing.v_active);
  3552. return false;
  3553. }
  3554. if (cur->timing.v_back_porch != tgt->timing.v_back_porch) {
  3555. DSI_DEBUG("timing.v_back_porch differs %d %d\n",
  3556. cur->timing.v_back_porch,
  3557. tgt->timing.v_back_porch);
  3558. return false;
  3559. }
  3560. if (cur->timing.v_sync_width != tgt->timing.v_sync_width) {
  3561. DSI_DEBUG("timing.v_sync_width differs %d %d\n",
  3562. cur->timing.v_sync_width,
  3563. tgt->timing.v_sync_width);
  3564. return false;
  3565. }
  3566. if (cur->timing.v_front_porch != tgt->timing.v_front_porch) {
  3567. DSI_DEBUG("timing.v_front_porch differs %d %d\n",
  3568. cur->timing.v_front_porch,
  3569. tgt->timing.v_front_porch);
  3570. if (dfps_type != DSI_DFPS_IMMEDIATE_VFP)
  3571. return false;
  3572. }
  3573. /* skip polarity comparison */
  3574. if (cur->timing.refresh_rate == tgt->timing.refresh_rate)
  3575. DSI_DEBUG("timing.refresh_rate identical %d %d\n",
  3576. cur->timing.refresh_rate,
  3577. tgt->timing.refresh_rate);
  3578. if (cur->pixel_clk_khz != tgt->pixel_clk_khz)
  3579. DSI_DEBUG("pixel_clk_khz differs %d %d\n",
  3580. cur->pixel_clk_khz, tgt->pixel_clk_khz);
  3581. if (cur->dsi_mode_flags != tgt->dsi_mode_flags)
  3582. DSI_DEBUG("flags differs %d %d\n",
  3583. cur->dsi_mode_flags, tgt->dsi_mode_flags);
  3584. return true;
  3585. }
  3586. void dsi_display_update_byte_intf_div(struct dsi_display *display)
  3587. {
  3588. struct dsi_host_common_cfg *config;
  3589. struct dsi_display_ctrl *m_ctrl;
  3590. int phy_ver;
  3591. m_ctrl = &display->ctrl[display->cmd_master_idx];
  3592. config = &display->panel->host_config;
  3593. phy_ver = dsi_phy_get_version(m_ctrl->phy);
  3594. if (phy_ver <= DSI_PHY_VERSION_2_0)
  3595. config->byte_intf_clk_div = 1;
  3596. else
  3597. config->byte_intf_clk_div = 2;
  3598. }
  3599. static int dsi_display_update_dsi_bitrate(struct dsi_display *display,
  3600. u32 bit_clk_rate)
  3601. {
  3602. int rc = 0;
  3603. int i;
  3604. DSI_DEBUG("%s:bit rate:%d\n", __func__, bit_clk_rate);
  3605. if (!display->panel) {
  3606. DSI_ERR("Invalid params\n");
  3607. return -EINVAL;
  3608. }
  3609. if (bit_clk_rate == 0) {
  3610. DSI_ERR("Invalid bit clock rate\n");
  3611. return -EINVAL;
  3612. }
  3613. display->config.bit_clk_rate_hz = bit_clk_rate;
  3614. display_for_each_ctrl(i, display) {
  3615. struct dsi_display_ctrl *dsi_disp_ctrl = &display->ctrl[i];
  3616. struct dsi_ctrl *ctrl = dsi_disp_ctrl->ctrl;
  3617. u32 num_of_lanes = 0, bpp, byte_intf_clk_div;
  3618. u64 bit_rate, pclk_rate, bit_rate_per_lane, byte_clk_rate,
  3619. byte_intf_clk_rate;
  3620. u32 bits_per_symbol = 16, num_of_symbols = 7; /* For Cphy */
  3621. struct dsi_host_common_cfg *host_cfg;
  3622. mutex_lock(&ctrl->ctrl_lock);
  3623. host_cfg = &display->panel->host_config;
  3624. if (host_cfg->data_lanes & DSI_DATA_LANE_0)
  3625. num_of_lanes++;
  3626. if (host_cfg->data_lanes & DSI_DATA_LANE_1)
  3627. num_of_lanes++;
  3628. if (host_cfg->data_lanes & DSI_DATA_LANE_2)
  3629. num_of_lanes++;
  3630. if (host_cfg->data_lanes & DSI_DATA_LANE_3)
  3631. num_of_lanes++;
  3632. if (num_of_lanes == 0) {
  3633. DSI_ERR("Invalid lane count\n");
  3634. rc = -EINVAL;
  3635. goto error;
  3636. }
  3637. bpp = dsi_pixel_format_to_bpp(host_cfg->dst_format);
  3638. bit_rate = display->config.bit_clk_rate_hz * num_of_lanes;
  3639. bit_rate_per_lane = bit_rate;
  3640. do_div(bit_rate_per_lane, num_of_lanes);
  3641. pclk_rate = bit_rate;
  3642. do_div(pclk_rate, bpp);
  3643. if (host_cfg->phy_type == DSI_PHY_TYPE_DPHY) {
  3644. bit_rate_per_lane = bit_rate;
  3645. do_div(bit_rate_per_lane, num_of_lanes);
  3646. byte_clk_rate = bit_rate_per_lane;
  3647. do_div(byte_clk_rate, 8);
  3648. byte_intf_clk_rate = byte_clk_rate;
  3649. byte_intf_clk_div = host_cfg->byte_intf_clk_div;
  3650. do_div(byte_intf_clk_rate, byte_intf_clk_div);
  3651. } else {
  3652. bit_rate_per_lane = bit_clk_rate;
  3653. pclk_rate *= bits_per_symbol;
  3654. do_div(pclk_rate, num_of_symbols);
  3655. byte_clk_rate = bit_clk_rate;
  3656. do_div(byte_clk_rate, num_of_symbols);
  3657. /* For CPHY, byte_intf_clk is same as byte_clk */
  3658. byte_intf_clk_rate = byte_clk_rate;
  3659. }
  3660. DSI_DEBUG("bit_clk_rate = %llu, bit_clk_rate_per_lane = %llu\n",
  3661. bit_rate, bit_rate_per_lane);
  3662. DSI_DEBUG("byte_clk_rate = %llu, byte_intf_clk_rate = %llu\n",
  3663. byte_clk_rate, byte_intf_clk_rate);
  3664. DSI_DEBUG("pclk_rate = %llu\n", pclk_rate);
  3665. SDE_EVT32(i, bit_rate, byte_clk_rate, pclk_rate);
  3666. ctrl->clk_freq.byte_clk_rate = byte_clk_rate;
  3667. ctrl->clk_freq.byte_intf_clk_rate = byte_intf_clk_rate;
  3668. ctrl->clk_freq.pix_clk_rate = pclk_rate;
  3669. rc = dsi_clk_set_link_frequencies(display->dsi_clk_handle,
  3670. ctrl->clk_freq, ctrl->cell_index);
  3671. if (rc) {
  3672. DSI_ERR("Failed to update link frequencies\n");
  3673. goto error;
  3674. }
  3675. ctrl->host_config.bit_clk_rate_hz = bit_clk_rate;
  3676. error:
  3677. mutex_unlock(&ctrl->ctrl_lock);
  3678. /* TODO: recover ctrl->clk_freq in case of failure */
  3679. if (rc)
  3680. return rc;
  3681. }
  3682. return 0;
  3683. }
  3684. static void _dsi_display_calc_pipe_delay(struct dsi_display *display,
  3685. struct dsi_dyn_clk_delay *delay,
  3686. struct dsi_display_mode *mode)
  3687. {
  3688. u32 esc_clk_rate_hz;
  3689. u32 pclk_to_esc_ratio, byte_to_esc_ratio, hr_bit_to_esc_ratio;
  3690. u32 hsync_period = 0;
  3691. struct dsi_display_ctrl *m_ctrl;
  3692. struct dsi_ctrl *dsi_ctrl;
  3693. struct dsi_phy_cfg *cfg;
  3694. int phy_ver;
  3695. m_ctrl = &display->ctrl[display->clk_master_idx];
  3696. dsi_ctrl = m_ctrl->ctrl;
  3697. cfg = &(m_ctrl->phy->cfg);
  3698. esc_clk_rate_hz = dsi_ctrl->clk_freq.esc_clk_rate;
  3699. pclk_to_esc_ratio = (dsi_ctrl->clk_freq.pix_clk_rate /
  3700. esc_clk_rate_hz);
  3701. byte_to_esc_ratio = (dsi_ctrl->clk_freq.byte_clk_rate /
  3702. esc_clk_rate_hz);
  3703. hr_bit_to_esc_ratio = ((dsi_ctrl->clk_freq.byte_clk_rate * 4) /
  3704. esc_clk_rate_hz);
  3705. hsync_period = dsi_h_total_dce(&mode->timing);
  3706. delay->pipe_delay = (hsync_period + 1) / pclk_to_esc_ratio;
  3707. if (!display->panel->video_config.eof_bllp_lp11_en)
  3708. delay->pipe_delay += (17 / pclk_to_esc_ratio) +
  3709. ((21 + (display->config.common_config.t_clk_pre + 1) +
  3710. (display->config.common_config.t_clk_post + 1)) /
  3711. byte_to_esc_ratio) +
  3712. ((((cfg->timing.lane_v3[8] >> 1) + 1) +
  3713. ((cfg->timing.lane_v3[6] >> 1) + 1) +
  3714. ((cfg->timing.lane_v3[3] * 4) +
  3715. (cfg->timing.lane_v3[5] >> 1) + 1) +
  3716. ((cfg->timing.lane_v3[7] >> 1) + 1) +
  3717. ((cfg->timing.lane_v3[1] >> 1) + 1) +
  3718. ((cfg->timing.lane_v3[4] >> 1) + 1)) /
  3719. hr_bit_to_esc_ratio);
  3720. delay->pipe_delay2 = 0;
  3721. if (display->panel->host_config.force_hs_clk_lane)
  3722. delay->pipe_delay2 = (6 / byte_to_esc_ratio) +
  3723. ((((cfg->timing.lane_v3[1] >> 1) + 1) +
  3724. ((cfg->timing.lane_v3[4] >> 1) + 1)) /
  3725. hr_bit_to_esc_ratio);
  3726. /*
  3727. * 100us pll delay recommended for phy ver 2.0 and 3.0
  3728. * 25us pll delay recommended for phy ver 4.0
  3729. */
  3730. phy_ver = dsi_phy_get_version(m_ctrl->phy);
  3731. if (phy_ver <= DSI_PHY_VERSION_3_0)
  3732. delay->pll_delay = 100;
  3733. else
  3734. delay->pll_delay = 25;
  3735. delay->pll_delay = ((delay->pll_delay * esc_clk_rate_hz) / 1000000);
  3736. }
  3737. /*
  3738. * dsi_display_is_type_cphy - check if panel type is cphy
  3739. * @display: Pointer to private display structure
  3740. * Returns: True if panel type is cphy
  3741. */
  3742. static inline bool dsi_display_is_type_cphy(struct dsi_display *display)
  3743. {
  3744. return (display->panel->host_config.phy_type ==
  3745. DSI_PHY_TYPE_CPHY) ? true : false;
  3746. }
  3747. static int _dsi_display_dyn_update_clks(struct dsi_display *display,
  3748. struct link_clk_freq *bkp_freq)
  3749. {
  3750. int rc = 0, i;
  3751. u8 ctrl_version;
  3752. struct dsi_display_ctrl *m_ctrl, *ctrl;
  3753. struct dsi_dyn_clk_caps *dyn_clk_caps;
  3754. struct dsi_clk_link_set *enable_clk;
  3755. m_ctrl = &display->ctrl[display->clk_master_idx];
  3756. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  3757. ctrl_version = m_ctrl->ctrl->version;
  3758. enable_clk = &display->clock_info.pll_clks;
  3759. dsi_clk_prepare_enable(enable_clk);
  3760. dsi_display_phy_configure(display, false);
  3761. display_for_each_ctrl(i, display) {
  3762. ctrl = &display->ctrl[i];
  3763. if (!ctrl->ctrl)
  3764. continue;
  3765. rc = dsi_clk_set_byte_clk_rate(display->dsi_clk_handle,
  3766. ctrl->ctrl->clk_freq.byte_clk_rate,
  3767. ctrl->ctrl->clk_freq.byte_intf_clk_rate, i);
  3768. if (rc) {
  3769. DSI_ERR("failed to set byte rate for index:%d\n", i);
  3770. goto recover_byte_clk;
  3771. }
  3772. rc = dsi_clk_set_pixel_clk_rate(display->dsi_clk_handle,
  3773. ctrl->ctrl->clk_freq.pix_clk_rate, i);
  3774. if (rc) {
  3775. DSI_ERR("failed to set pix rate for index:%d\n", i);
  3776. goto recover_pix_clk;
  3777. }
  3778. }
  3779. display_for_each_ctrl(i, display) {
  3780. ctrl = &display->ctrl[i];
  3781. if (ctrl == m_ctrl)
  3782. continue;
  3783. dsi_phy_dynamic_refresh_trigger(ctrl->phy, false);
  3784. }
  3785. dsi_phy_dynamic_refresh_trigger(m_ctrl->phy, true);
  3786. /*
  3787. * Don't wait for dynamic refresh done for dsi ctrl greater than 2.5
  3788. * and with constant fps, as dynamic refresh will applied with
  3789. * next mdp intf ctrl flush.
  3790. */
  3791. if ((ctrl_version >= DSI_CTRL_VERSION_2_5) &&
  3792. (dyn_clk_caps->maintain_const_fps))
  3793. goto defer_dfps_wait;
  3794. /* wait for dynamic refresh done */
  3795. display_for_each_ctrl(i, display) {
  3796. ctrl = &display->ctrl[i];
  3797. rc = dsi_ctrl_wait4dynamic_refresh_done(ctrl->ctrl);
  3798. if (rc) {
  3799. DSI_ERR("wait4dynamic refresh failed for dsi:%d\n", i);
  3800. goto recover_pix_clk;
  3801. } else {
  3802. DSI_INFO("dynamic refresh done on dsi: %s\n",
  3803. i ? "slave" : "master");
  3804. }
  3805. }
  3806. display_for_each_ctrl(i, display) {
  3807. ctrl = &display->ctrl[i];
  3808. dsi_phy_dynamic_refresh_clear(ctrl->phy);
  3809. }
  3810. defer_dfps_wait:
  3811. if (rc)
  3812. DSI_ERR("could not switch back to src clks %d\n", rc);
  3813. dsi_clk_disable_unprepare(enable_clk);
  3814. return rc;
  3815. recover_pix_clk:
  3816. display_for_each_ctrl(i, display) {
  3817. ctrl = &display->ctrl[i];
  3818. if (!ctrl->ctrl)
  3819. continue;
  3820. dsi_clk_set_pixel_clk_rate(display->dsi_clk_handle,
  3821. bkp_freq->pix_clk_rate, i);
  3822. }
  3823. recover_byte_clk:
  3824. display_for_each_ctrl(i, display) {
  3825. ctrl = &display->ctrl[i];
  3826. if (!ctrl->ctrl)
  3827. continue;
  3828. dsi_clk_set_byte_clk_rate(display->dsi_clk_handle,
  3829. bkp_freq->byte_clk_rate,
  3830. bkp_freq->byte_intf_clk_rate, i);
  3831. }
  3832. return rc;
  3833. }
  3834. static int dsi_display_dynamic_clk_switch_vid(struct dsi_display *display,
  3835. struct dsi_display_mode *mode)
  3836. {
  3837. int rc = 0, mask, i;
  3838. struct dsi_display_ctrl *m_ctrl, *ctrl;
  3839. struct dsi_dyn_clk_delay delay;
  3840. struct link_clk_freq bkp_freq;
  3841. dsi_panel_acquire_panel_lock(display->panel);
  3842. m_ctrl = &display->ctrl[display->clk_master_idx];
  3843. dsi_display_clk_ctrl(display->dsi_clk_handle, DSI_ALL_CLKS, DSI_CLK_ON);
  3844. /* mask PLL unlock, FIFO overflow and underflow errors */
  3845. mask = BIT(DSI_PLL_UNLOCK_ERR) | BIT(DSI_FIFO_UNDERFLOW) |
  3846. BIT(DSI_FIFO_OVERFLOW);
  3847. dsi_display_mask_ctrl_error_interrupts(display, mask, true);
  3848. /* update the phy timings based on new mode */
  3849. display_for_each_ctrl(i, display) {
  3850. ctrl = &display->ctrl[i];
  3851. dsi_phy_update_phy_timings(ctrl->phy, &display->config);
  3852. }
  3853. /* back up existing rates to handle failure case */
  3854. bkp_freq.byte_clk_rate = m_ctrl->ctrl->clk_freq.byte_clk_rate;
  3855. bkp_freq.byte_intf_clk_rate = m_ctrl->ctrl->clk_freq.byte_intf_clk_rate;
  3856. bkp_freq.pix_clk_rate = m_ctrl->ctrl->clk_freq.pix_clk_rate;
  3857. bkp_freq.esc_clk_rate = m_ctrl->ctrl->clk_freq.esc_clk_rate;
  3858. rc = dsi_display_update_dsi_bitrate(display, mode->timing.clk_rate_hz);
  3859. if (rc) {
  3860. DSI_ERR("failed set link frequencies %d\n", rc);
  3861. goto exit;
  3862. }
  3863. /* calculate pipe delays */
  3864. _dsi_display_calc_pipe_delay(display, &delay, mode);
  3865. /* configure dynamic refresh ctrl registers */
  3866. display_for_each_ctrl(i, display) {
  3867. ctrl = &display->ctrl[i];
  3868. if (!ctrl->phy)
  3869. continue;
  3870. if (ctrl == m_ctrl)
  3871. dsi_phy_config_dynamic_refresh(ctrl->phy, &delay, true);
  3872. else
  3873. dsi_phy_config_dynamic_refresh(ctrl->phy, &delay,
  3874. false);
  3875. }
  3876. rc = _dsi_display_dyn_update_clks(display, &bkp_freq);
  3877. exit:
  3878. dsi_display_mask_ctrl_error_interrupts(display, mask, false);
  3879. dsi_display_clk_ctrl(display->dsi_clk_handle, DSI_ALL_CLKS,
  3880. DSI_CLK_OFF);
  3881. /* store newly calculated phy timings in mode private info */
  3882. dsi_phy_dyn_refresh_cache_phy_timings(m_ctrl->phy,
  3883. mode->priv_info->phy_timing_val,
  3884. mode->priv_info->phy_timing_len);
  3885. dsi_panel_release_panel_lock(display->panel);
  3886. return rc;
  3887. }
  3888. static int dsi_display_dynamic_clk_configure_cmd(struct dsi_display *display,
  3889. int clk_rate)
  3890. {
  3891. int rc = 0;
  3892. if (clk_rate <= 0) {
  3893. DSI_ERR("%s: bitrate should be greater than 0\n", __func__);
  3894. return -EINVAL;
  3895. }
  3896. if (clk_rate == display->cached_clk_rate) {
  3897. DSI_INFO("%s: ignore duplicated DSI clk setting\n", __func__);
  3898. return rc;
  3899. }
  3900. display->cached_clk_rate = clk_rate;
  3901. rc = dsi_display_update_dsi_bitrate(display, clk_rate);
  3902. if (!rc) {
  3903. DSI_DEBUG("%s: bit clk is ready to be configured to '%d'\n",
  3904. __func__, clk_rate);
  3905. atomic_set(&display->clkrate_change_pending, 1);
  3906. } else {
  3907. DSI_ERR("%s: Failed to prepare to configure '%d'. rc = %d\n",
  3908. __func__, clk_rate, rc);
  3909. /* Caching clock failed, so don't go on doing so. */
  3910. atomic_set(&display->clkrate_change_pending, 0);
  3911. display->cached_clk_rate = 0;
  3912. }
  3913. return rc;
  3914. }
  3915. static int dsi_display_dfps_update(struct dsi_display *display,
  3916. struct dsi_display_mode *dsi_mode)
  3917. {
  3918. struct dsi_mode_info *timing;
  3919. struct dsi_display_ctrl *m_ctrl, *ctrl;
  3920. struct dsi_display_mode *panel_mode;
  3921. struct dsi_dfps_capabilities dfps_caps;
  3922. int rc = 0;
  3923. int i = 0;
  3924. struct dsi_dyn_clk_caps *dyn_clk_caps;
  3925. if (!display || !dsi_mode || !display->panel) {
  3926. DSI_ERR("Invalid params\n");
  3927. return -EINVAL;
  3928. }
  3929. timing = &dsi_mode->timing;
  3930. dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
  3931. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  3932. if (!dfps_caps.dfps_support && !dyn_clk_caps->maintain_const_fps) {
  3933. DSI_ERR("dfps or constant fps not supported\n");
  3934. return -ENOTSUPP;
  3935. }
  3936. if (dfps_caps.type == DSI_DFPS_IMMEDIATE_CLK) {
  3937. DSI_ERR("dfps clock method not supported\n");
  3938. return -ENOTSUPP;
  3939. }
  3940. /* For split DSI, update the clock master first */
  3941. DSI_DEBUG("configuring seamless dynamic fps\n\n");
  3942. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  3943. m_ctrl = &display->ctrl[display->clk_master_idx];
  3944. rc = dsi_ctrl_async_timing_update(m_ctrl->ctrl, timing);
  3945. if (rc) {
  3946. DSI_ERR("[%s] failed to dfps update host_%d, rc=%d\n",
  3947. display->name, i, rc);
  3948. goto error;
  3949. }
  3950. /* Update the rest of the controllers */
  3951. display_for_each_ctrl(i, display) {
  3952. ctrl = &display->ctrl[i];
  3953. if (!ctrl->ctrl || (ctrl == m_ctrl))
  3954. continue;
  3955. rc = dsi_ctrl_async_timing_update(ctrl->ctrl, timing);
  3956. if (rc) {
  3957. DSI_ERR("[%s] failed to dfps update host_%d, rc=%d\n",
  3958. display->name, i, rc);
  3959. goto error;
  3960. }
  3961. }
  3962. panel_mode = display->panel->cur_mode;
  3963. memcpy(panel_mode, dsi_mode, sizeof(*panel_mode));
  3964. /*
  3965. * dsi_mode_flags flags are used to communicate with other drm driver
  3966. * components, and are transient. They aren't inherently part of the
  3967. * display panel's mode and shouldn't be saved into the cached currently
  3968. * active mode.
  3969. */
  3970. panel_mode->dsi_mode_flags = 0;
  3971. error:
  3972. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  3973. return rc;
  3974. }
  3975. static int dsi_display_dfps_calc_front_porch(
  3976. u32 old_fps,
  3977. u32 new_fps,
  3978. u32 a_total,
  3979. u32 b_total,
  3980. u32 b_fp,
  3981. u32 *b_fp_out)
  3982. {
  3983. s32 b_fp_new;
  3984. int add_porches, diff;
  3985. if (!b_fp_out) {
  3986. DSI_ERR("Invalid params\n");
  3987. return -EINVAL;
  3988. }
  3989. if (!a_total || !new_fps) {
  3990. DSI_ERR("Invalid pixel total or new fps in mode request\n");
  3991. return -EINVAL;
  3992. }
  3993. /*
  3994. * Keep clock, other porches constant, use new fps, calc front porch
  3995. * new_vtotal = old_vtotal * (old_fps / new_fps )
  3996. * new_vfp - old_vfp = new_vtotal - old_vtotal
  3997. * new_vfp = old_vfp + old_vtotal * ((old_fps - new_fps)/ new_fps)
  3998. */
  3999. diff = abs(old_fps - new_fps);
  4000. add_porches = mult_frac(b_total, diff, new_fps);
  4001. if (old_fps > new_fps)
  4002. b_fp_new = b_fp + add_porches;
  4003. else
  4004. b_fp_new = b_fp - add_porches;
  4005. DSI_DEBUG("fps %u a %u b %u b_fp %u new_fp %d\n",
  4006. new_fps, a_total, b_total, b_fp, b_fp_new);
  4007. if (b_fp_new < 0) {
  4008. DSI_ERR("Invalid new_hfp calcluated%d\n", b_fp_new);
  4009. return -EINVAL;
  4010. }
  4011. /**
  4012. * TODO: To differentiate from clock method when communicating to the
  4013. * other components, perhaps we should set clk here to original value
  4014. */
  4015. *b_fp_out = b_fp_new;
  4016. return 0;
  4017. }
  4018. /**
  4019. * dsi_display_get_dfps_timing() - Get the new dfps values.
  4020. * @display: DSI display handle.
  4021. * @adj_mode: Mode value structure to be changed.
  4022. * It contains old timing values and latest fps value.
  4023. * New timing values are updated based on new fps.
  4024. * @curr_refresh_rate: Current fps rate.
  4025. * If zero , current fps rate is taken from
  4026. * display->panel->cur_mode.
  4027. * Return: error code.
  4028. */
  4029. static int dsi_display_get_dfps_timing(struct dsi_display *display,
  4030. struct dsi_display_mode *adj_mode,
  4031. u32 curr_refresh_rate)
  4032. {
  4033. struct dsi_dfps_capabilities dfps_caps;
  4034. struct dsi_display_mode per_ctrl_mode;
  4035. struct dsi_mode_info *timing;
  4036. struct dsi_ctrl *m_ctrl;
  4037. int rc = 0;
  4038. if (!display || !adj_mode) {
  4039. DSI_ERR("Invalid params\n");
  4040. return -EINVAL;
  4041. }
  4042. m_ctrl = display->ctrl[display->clk_master_idx].ctrl;
  4043. dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
  4044. if (!dfps_caps.dfps_support) {
  4045. DSI_ERR("dfps not supported by panel\n");
  4046. return -EINVAL;
  4047. }
  4048. per_ctrl_mode = *adj_mode;
  4049. adjust_timing_by_ctrl_count(display, &per_ctrl_mode);
  4050. if (!curr_refresh_rate) {
  4051. if (!dsi_display_is_seamless_dfps_possible(display,
  4052. &per_ctrl_mode, dfps_caps.type)) {
  4053. DSI_ERR("seamless dynamic fps not supported for mode\n");
  4054. return -EINVAL;
  4055. }
  4056. if (display->panel->cur_mode) {
  4057. curr_refresh_rate =
  4058. display->panel->cur_mode->timing.refresh_rate;
  4059. } else {
  4060. DSI_ERR("cur_mode is not initialized\n");
  4061. return -EINVAL;
  4062. }
  4063. }
  4064. /* TODO: Remove this direct reference to the dsi_ctrl */
  4065. timing = &per_ctrl_mode.timing;
  4066. switch (dfps_caps.type) {
  4067. case DSI_DFPS_IMMEDIATE_VFP:
  4068. rc = dsi_display_dfps_calc_front_porch(
  4069. curr_refresh_rate,
  4070. timing->refresh_rate,
  4071. dsi_h_total_dce(timing),
  4072. DSI_V_TOTAL(timing),
  4073. timing->v_front_porch,
  4074. &adj_mode->timing.v_front_porch);
  4075. SDE_EVT32(SDE_EVTLOG_FUNC_CASE1, DSI_DFPS_IMMEDIATE_VFP,
  4076. curr_refresh_rate, timing->refresh_rate,
  4077. timing->v_front_porch, adj_mode->timing.v_front_porch);
  4078. break;
  4079. case DSI_DFPS_IMMEDIATE_HFP:
  4080. rc = dsi_display_dfps_calc_front_porch(
  4081. curr_refresh_rate,
  4082. timing->refresh_rate,
  4083. DSI_V_TOTAL(timing),
  4084. dsi_h_total_dce(timing),
  4085. timing->h_front_porch,
  4086. &adj_mode->timing.h_front_porch);
  4087. SDE_EVT32(SDE_EVTLOG_FUNC_CASE2, DSI_DFPS_IMMEDIATE_HFP,
  4088. curr_refresh_rate, timing->refresh_rate,
  4089. timing->h_front_porch, adj_mode->timing.h_front_porch);
  4090. if (!rc)
  4091. adj_mode->timing.h_front_porch *= display->ctrl_count;
  4092. break;
  4093. default:
  4094. DSI_ERR("Unsupported DFPS mode %d\n", dfps_caps.type);
  4095. rc = -ENOTSUPP;
  4096. }
  4097. return rc;
  4098. }
  4099. static bool dsi_display_validate_mode_seamless(struct dsi_display *display,
  4100. struct dsi_display_mode *adj_mode)
  4101. {
  4102. int rc = 0;
  4103. if (!display || !adj_mode) {
  4104. DSI_ERR("Invalid params\n");
  4105. return false;
  4106. }
  4107. /* Currently the only seamless transition is dynamic fps */
  4108. rc = dsi_display_get_dfps_timing(display, adj_mode, 0);
  4109. if (rc) {
  4110. DSI_DEBUG("Dynamic FPS not supported for seamless\n");
  4111. } else {
  4112. DSI_DEBUG("Mode switch is seamless Dynamic FPS\n");
  4113. adj_mode->dsi_mode_flags |= DSI_MODE_FLAG_DFPS |
  4114. DSI_MODE_FLAG_VBLANK_PRE_MODESET;
  4115. }
  4116. return rc;
  4117. }
  4118. static void dsi_display_validate_dms_fps(struct dsi_display_mode *cur_mode,
  4119. struct dsi_display_mode *to_mode)
  4120. {
  4121. u32 cur_fps, to_fps;
  4122. u32 cur_h_active, to_h_active;
  4123. u32 cur_v_active, to_v_active;
  4124. cur_fps = cur_mode->timing.refresh_rate;
  4125. to_fps = to_mode->timing.refresh_rate;
  4126. cur_h_active = cur_mode->timing.h_active;
  4127. cur_v_active = cur_mode->timing.v_active;
  4128. to_h_active = to_mode->timing.h_active;
  4129. to_v_active = to_mode->timing.v_active;
  4130. if ((cur_h_active == to_h_active) && (cur_v_active == to_v_active) &&
  4131. (cur_fps != to_fps)) {
  4132. to_mode->dsi_mode_flags |= DSI_MODE_FLAG_DMS_FPS;
  4133. DSI_DEBUG("DMS Modeset with FPS change\n");
  4134. } else {
  4135. to_mode->dsi_mode_flags &= ~DSI_MODE_FLAG_DMS_FPS;
  4136. }
  4137. }
  4138. static int dsi_display_set_mode_sub(struct dsi_display *display,
  4139. struct dsi_display_mode *mode,
  4140. u32 flags)
  4141. {
  4142. int rc = 0, clk_rate = 0;
  4143. int i;
  4144. struct dsi_display_ctrl *ctrl;
  4145. struct dsi_display_ctrl *mctrl;
  4146. struct dsi_display_mode_priv_info *priv_info;
  4147. bool commit_phy_timing = false;
  4148. struct dsi_dyn_clk_caps *dyn_clk_caps;
  4149. priv_info = mode->priv_info;
  4150. if (!priv_info) {
  4151. DSI_ERR("[%s] failed to get private info of the display mode\n",
  4152. display->name);
  4153. return -EINVAL;
  4154. }
  4155. SDE_EVT32(mode->dsi_mode_flags, display->panel->panel_mode);
  4156. if (mode->dsi_mode_flags & DSI_MODE_FLAG_POMS_TO_VID)
  4157. display->panel->panel_mode = DSI_OP_VIDEO_MODE;
  4158. else if (mode->dsi_mode_flags & DSI_MODE_FLAG_POMS_TO_CMD)
  4159. display->panel->panel_mode = DSI_OP_CMD_MODE;
  4160. rc = dsi_panel_get_host_cfg_for_mode(display->panel,
  4161. mode,
  4162. &display->config);
  4163. if (rc) {
  4164. DSI_ERR("[%s] failed to get host config for mode, rc=%d\n",
  4165. display->name, rc);
  4166. goto error;
  4167. }
  4168. memcpy(&display->config.lane_map, &display->lane_map,
  4169. sizeof(display->lane_map));
  4170. mctrl = &display->ctrl[display->clk_master_idx];
  4171. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  4172. if (mode->dsi_mode_flags &
  4173. (DSI_MODE_FLAG_DFPS | DSI_MODE_FLAG_VRR)) {
  4174. display_for_each_ctrl(i, display) {
  4175. ctrl = &display->ctrl[i];
  4176. if (!ctrl->ctrl || (ctrl != mctrl))
  4177. continue;
  4178. ctrl->ctrl->hw.ops.set_timing_db(&ctrl->ctrl->hw,
  4179. true);
  4180. dsi_phy_dynamic_refresh_clear(ctrl->phy);
  4181. if ((ctrl->ctrl->version >= DSI_CTRL_VERSION_2_5) &&
  4182. (dyn_clk_caps->maintain_const_fps)) {
  4183. dsi_phy_dynamic_refresh_trigger_sel(ctrl->phy,
  4184. true);
  4185. }
  4186. }
  4187. rc = dsi_display_dfps_update(display, mode);
  4188. if (rc) {
  4189. DSI_ERR("[%s]DSI dfps update failed, rc=%d\n",
  4190. display->name, rc);
  4191. goto error;
  4192. }
  4193. display_for_each_ctrl(i, display) {
  4194. ctrl = &display->ctrl[i];
  4195. rc = dsi_ctrl_update_host_config(ctrl->ctrl,
  4196. &display->config, mode, mode->dsi_mode_flags,
  4197. display->dsi_clk_handle);
  4198. if (rc) {
  4199. DSI_ERR("failed to update ctrl config\n");
  4200. goto error;
  4201. }
  4202. }
  4203. if (priv_info->phy_timing_len) {
  4204. display_for_each_ctrl(i, display) {
  4205. ctrl = &display->ctrl[i];
  4206. rc = dsi_phy_set_timing_params(ctrl->phy,
  4207. priv_info->phy_timing_val,
  4208. priv_info->phy_timing_len,
  4209. commit_phy_timing);
  4210. if (rc)
  4211. DSI_ERR("Fail to add timing params\n");
  4212. }
  4213. }
  4214. if (!(mode->dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK))
  4215. return rc;
  4216. }
  4217. if (mode->dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK) {
  4218. if (display->panel->panel_mode == DSI_OP_VIDEO_MODE) {
  4219. rc = dsi_display_dynamic_clk_switch_vid(display, mode);
  4220. if (rc)
  4221. DSI_ERR("dynamic clk change failed %d\n", rc);
  4222. /*
  4223. * skip rest of the opearations since
  4224. * dsi_display_dynamic_clk_switch_vid() already takes
  4225. * care of them.
  4226. */
  4227. return rc;
  4228. } else if (display->panel->panel_mode == DSI_OP_CMD_MODE) {
  4229. clk_rate = mode->timing.clk_rate_hz;
  4230. rc = dsi_display_dynamic_clk_configure_cmd(display,
  4231. clk_rate);
  4232. if (rc) {
  4233. DSI_ERR("Failed to configure dynamic clk\n");
  4234. return rc;
  4235. }
  4236. }
  4237. }
  4238. display_for_each_ctrl(i, display) {
  4239. ctrl = &display->ctrl[i];
  4240. rc = dsi_ctrl_update_host_config(ctrl->ctrl, &display->config,
  4241. mode, mode->dsi_mode_flags,
  4242. display->dsi_clk_handle);
  4243. if (rc) {
  4244. DSI_ERR("[%s] failed to update ctrl config, rc=%d\n",
  4245. display->name, rc);
  4246. goto error;
  4247. }
  4248. }
  4249. if ((mode->dsi_mode_flags & DSI_MODE_FLAG_DMS) &&
  4250. (display->panel->panel_mode == DSI_OP_CMD_MODE)) {
  4251. u64 cur_bitclk = display->panel->cur_mode->timing.clk_rate_hz;
  4252. u64 to_bitclk = mode->timing.clk_rate_hz;
  4253. commit_phy_timing = true;
  4254. /* No need to set clkrate pending flag if clocks are same */
  4255. if ((!cur_bitclk && !to_bitclk) || (cur_bitclk != to_bitclk))
  4256. atomic_set(&display->clkrate_change_pending, 1);
  4257. dsi_display_validate_dms_fps(display->panel->cur_mode, mode);
  4258. }
  4259. if (priv_info->phy_timing_len) {
  4260. display_for_each_ctrl(i, display) {
  4261. ctrl = &display->ctrl[i];
  4262. rc = dsi_phy_set_timing_params(ctrl->phy,
  4263. priv_info->phy_timing_val,
  4264. priv_info->phy_timing_len,
  4265. commit_phy_timing);
  4266. if (rc)
  4267. DSI_ERR("failed to add DSI PHY timing params\n");
  4268. }
  4269. }
  4270. error:
  4271. return rc;
  4272. }
  4273. /**
  4274. * _dsi_display_dev_init - initializes the display device
  4275. * Initialization will acquire references to the resources required for the
  4276. * display hardware to function.
  4277. * @display: Handle to the display
  4278. * Returns: Zero on success
  4279. */
  4280. static int _dsi_display_dev_init(struct dsi_display *display)
  4281. {
  4282. int rc = 0;
  4283. if (!display) {
  4284. DSI_ERR("invalid display\n");
  4285. return -EINVAL;
  4286. }
  4287. if (!display->panel_node && !display->fw)
  4288. return 0;
  4289. mutex_lock(&display->display_lock);
  4290. display->parser = dsi_parser_get(&display->pdev->dev);
  4291. if (display->fw && display->parser)
  4292. display->parser_node = dsi_parser_get_head_node(
  4293. display->parser, display->fw->data,
  4294. display->fw->size);
  4295. rc = dsi_display_res_init(display);
  4296. if (rc) {
  4297. DSI_ERR("[%s] failed to initialize resources, rc=%d\n",
  4298. display->name, rc);
  4299. goto error;
  4300. }
  4301. error:
  4302. mutex_unlock(&display->display_lock);
  4303. return rc;
  4304. }
  4305. /**
  4306. * _dsi_display_dev_deinit - deinitializes the display device
  4307. * All the resources acquired during device init will be released.
  4308. * @display: Handle to the display
  4309. * Returns: Zero on success
  4310. */
  4311. static int _dsi_display_dev_deinit(struct dsi_display *display)
  4312. {
  4313. int rc = 0;
  4314. if (!display) {
  4315. DSI_ERR("invalid display\n");
  4316. return -EINVAL;
  4317. }
  4318. mutex_lock(&display->display_lock);
  4319. rc = dsi_display_res_deinit(display);
  4320. if (rc)
  4321. DSI_ERR("[%s] failed to deinitialize resource, rc=%d\n",
  4322. display->name, rc);
  4323. mutex_unlock(&display->display_lock);
  4324. return rc;
  4325. }
  4326. /**
  4327. * dsi_display_cont_splash_res_disable() - Disable resource votes added in probe
  4328. * @dsi_display: Pointer to dsi display
  4329. * Returns: Zero on success
  4330. */
  4331. int dsi_display_cont_splash_res_disable(void *dsi_display)
  4332. {
  4333. struct dsi_display *display = dsi_display;
  4334. int rc = 0;
  4335. /* Remove the panel vote that was added during dsi display probe */
  4336. rc = dsi_pwr_enable_regulator(&display->panel->power_info, false);
  4337. if (rc)
  4338. DSI_ERR("[%s] failed to disable vregs, rc=%d\n",
  4339. display->panel->name, rc);
  4340. return rc;
  4341. }
  4342. /**
  4343. * dsi_display_cont_splash_config() - Initialize resources for continuous splash
  4344. * @dsi_display: Pointer to dsi display
  4345. * Returns: Zero on success
  4346. */
  4347. int dsi_display_cont_splash_config(void *dsi_display)
  4348. {
  4349. struct dsi_display *display = dsi_display;
  4350. int rc = 0;
  4351. /* Vote for gdsc required to read register address space */
  4352. if (!display) {
  4353. DSI_ERR("invalid input display param\n");
  4354. return -EINVAL;
  4355. }
  4356. rc = pm_runtime_get_sync(display->drm_dev->dev);
  4357. if (rc < 0) {
  4358. DSI_ERR("failed to vote gdsc for continuous splash, rc=%d\n",
  4359. rc);
  4360. return rc;
  4361. }
  4362. mutex_lock(&display->display_lock);
  4363. display->is_cont_splash_enabled = true;
  4364. /* Update splash status for clock manager */
  4365. dsi_display_clk_mngr_update_splash_status(display->clk_mngr,
  4366. display->is_cont_splash_enabled);
  4367. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY, display->is_cont_splash_enabled);
  4368. /* Set up ctrl isr before enabling core clk */
  4369. dsi_display_ctrl_isr_configure(display, true);
  4370. /* Vote for Core clk and link clk. Votes on ctrl and phy
  4371. * regulator are inplicit from pre clk on callback
  4372. */
  4373. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  4374. DSI_ALL_CLKS, DSI_CLK_ON);
  4375. if (rc) {
  4376. DSI_ERR("[%s] failed to enable DSI link clocks, rc=%d\n",
  4377. display->name, rc);
  4378. goto clk_manager_update;
  4379. }
  4380. mutex_unlock(&display->display_lock);
  4381. /* Set the current brightness level */
  4382. dsi_panel_bl_handoff(display->panel);
  4383. return rc;
  4384. clk_manager_update:
  4385. dsi_display_ctrl_isr_configure(display, false);
  4386. /* Update splash status for clock manager */
  4387. dsi_display_clk_mngr_update_splash_status(display->clk_mngr,
  4388. false);
  4389. pm_runtime_put_sync(display->drm_dev->dev);
  4390. display->is_cont_splash_enabled = false;
  4391. mutex_unlock(&display->display_lock);
  4392. return rc;
  4393. }
  4394. /**
  4395. * dsi_display_splash_res_cleanup() - cleanup for continuous splash
  4396. * @display: Pointer to dsi display
  4397. * Returns: Zero on success
  4398. */
  4399. int dsi_display_splash_res_cleanup(struct dsi_display *display)
  4400. {
  4401. int rc = 0;
  4402. if (!display->is_cont_splash_enabled)
  4403. return 0;
  4404. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  4405. DSI_ALL_CLKS, DSI_CLK_OFF);
  4406. if (rc)
  4407. DSI_ERR("[%s] failed to disable DSI link clocks, rc=%d\n",
  4408. display->name, rc);
  4409. pm_runtime_put_sync(display->drm_dev->dev);
  4410. display->is_cont_splash_enabled = false;
  4411. /* Update splash status for clock manager */
  4412. dsi_display_clk_mngr_update_splash_status(display->clk_mngr,
  4413. display->is_cont_splash_enabled);
  4414. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT, display->is_cont_splash_enabled);
  4415. return rc;
  4416. }
  4417. static int dsi_display_force_update_dsi_clk(struct dsi_display *display)
  4418. {
  4419. int rc = 0;
  4420. rc = dsi_display_link_clk_force_update_ctrl(display->dsi_clk_handle);
  4421. if (!rc) {
  4422. DSI_DEBUG("dsi bit clk has been configured to %d\n",
  4423. display->cached_clk_rate);
  4424. atomic_set(&display->clkrate_change_pending, 0);
  4425. } else {
  4426. DSI_ERR("Failed to configure dsi bit clock '%d'. rc = %d\n",
  4427. display->cached_clk_rate, rc);
  4428. }
  4429. return rc;
  4430. }
  4431. static int dsi_display_validate_split_link(struct dsi_display *display)
  4432. {
  4433. int i, rc = 0;
  4434. struct dsi_display_ctrl *ctrl;
  4435. struct dsi_host_common_cfg *host = &display->panel->host_config;
  4436. if (!host->split_link.split_link_enabled)
  4437. return 0;
  4438. if (display->panel->panel_mode == DSI_OP_CMD_MODE) {
  4439. DSI_ERR("[%s] split link is not supported in command mode\n",
  4440. display->name);
  4441. rc = -ENOTSUPP;
  4442. goto error;
  4443. }
  4444. display_for_each_ctrl(i, display) {
  4445. ctrl = &display->ctrl[i];
  4446. if (!ctrl->ctrl->split_link_supported) {
  4447. DSI_ERR("[%s] split link is not supported by hw\n",
  4448. display->name);
  4449. rc = -ENOTSUPP;
  4450. goto error;
  4451. }
  4452. set_bit(DSI_PHY_SPLIT_LINK, ctrl->phy->hw.feature_map);
  4453. }
  4454. DSI_DEBUG("Split link is enabled\n");
  4455. return 0;
  4456. error:
  4457. host->split_link.split_link_enabled = false;
  4458. return rc;
  4459. }
  4460. static int dsi_display_get_io_resources(struct msm_io_res *io_res, void *data)
  4461. {
  4462. int rc = 0;
  4463. struct dsi_display *display;
  4464. if (!data)
  4465. return -EINVAL;
  4466. rc = dsi_ctrl_get_io_resources(io_res);
  4467. if (rc)
  4468. goto end;
  4469. rc = dsi_phy_get_io_resources(io_res);
  4470. if (rc)
  4471. goto end;
  4472. display = (struct dsi_display *)data;
  4473. rc = dsi_panel_get_io_resources(display->panel, io_res);
  4474. end:
  4475. return rc;
  4476. }
  4477. static int dsi_display_pre_release(void *data)
  4478. {
  4479. if (!data)
  4480. return -EINVAL;
  4481. dsi_display_ctrl_irq_update((struct dsi_display *)data, false);
  4482. return 0;
  4483. }
  4484. static int dsi_display_pre_acquire(void *data)
  4485. {
  4486. if (!data)
  4487. return -EINVAL;
  4488. dsi_display_ctrl_irq_update((struct dsi_display *)data, true);
  4489. return 0;
  4490. }
  4491. /**
  4492. * dsi_display_bind - bind dsi device with controlling device
  4493. * @dev: Pointer to base of platform device
  4494. * @master: Pointer to container of drm device
  4495. * @data: Pointer to private data
  4496. * Returns: Zero on success
  4497. */
  4498. static int dsi_display_bind(struct device *dev,
  4499. struct device *master,
  4500. void *data)
  4501. {
  4502. struct dsi_display_ctrl *display_ctrl;
  4503. struct drm_device *drm;
  4504. struct dsi_display *display;
  4505. struct dsi_clk_info info;
  4506. struct clk_ctrl_cb clk_cb;
  4507. void *handle = NULL;
  4508. struct platform_device *pdev = to_platform_device(dev);
  4509. char *client1 = "dsi_clk_client";
  4510. char *client2 = "mdp_event_client";
  4511. struct msm_vm_ops vm_event_ops = {
  4512. .vm_get_io_resources = dsi_display_get_io_resources,
  4513. .vm_pre_hw_release = dsi_display_pre_release,
  4514. .vm_post_hw_acquire = dsi_display_pre_acquire,
  4515. };
  4516. int i, rc = 0;
  4517. if (!dev || !pdev || !master) {
  4518. DSI_ERR("invalid param(s), dev %pK, pdev %pK, master %pK\n",
  4519. dev, pdev, master);
  4520. return -EINVAL;
  4521. }
  4522. drm = dev_get_drvdata(master);
  4523. display = platform_get_drvdata(pdev);
  4524. if (!drm || !display) {
  4525. DSI_ERR("invalid param(s), drm %pK, display %pK\n",
  4526. drm, display);
  4527. return -EINVAL;
  4528. }
  4529. if (!display->panel_node && !display->fw)
  4530. return 0;
  4531. if (!display->fw)
  4532. display->name = display->panel_node->name;
  4533. /* defer bind if ext bridge driver is not loaded */
  4534. if (display->panel && display->panel->host_config.ext_bridge_mode) {
  4535. for (i = 0; i < display->ext_bridge_cnt; i++) {
  4536. if (!of_drm_find_bridge(
  4537. display->ext_bridge[i].node_of)) {
  4538. DSI_DEBUG("defer for bridge[%d] %s\n", i,
  4539. display->ext_bridge[i].node_of->full_name);
  4540. return -EPROBE_DEFER;
  4541. }
  4542. }
  4543. }
  4544. mutex_lock(&display->display_lock);
  4545. rc = dsi_display_validate_split_link(display);
  4546. if (rc) {
  4547. DSI_ERR("[%s] split link validation failed, rc=%d\n",
  4548. display->name, rc);
  4549. goto error;
  4550. }
  4551. rc = dsi_display_debugfs_init(display);
  4552. if (rc) {
  4553. DSI_ERR("[%s] debugfs init failed, rc=%d\n", display->name, rc);
  4554. goto error;
  4555. }
  4556. atomic_set(&display->clkrate_change_pending, 0);
  4557. display->cached_clk_rate = 0;
  4558. memset(&info, 0x0, sizeof(info));
  4559. display_for_each_ctrl(i, display) {
  4560. display_ctrl = &display->ctrl[i];
  4561. rc = dsi_ctrl_drv_init(display_ctrl->ctrl, display->root);
  4562. if (rc) {
  4563. DSI_ERR("[%s] failed to initialize ctrl[%d], rc=%d\n",
  4564. display->name, i, rc);
  4565. goto error_ctrl_deinit;
  4566. }
  4567. display_ctrl->ctrl->horiz_index = i;
  4568. rc = dsi_phy_drv_init(display_ctrl->phy);
  4569. if (rc) {
  4570. DSI_ERR("[%s] Failed to initialize phy[%d], rc=%d\n",
  4571. display->name, i, rc);
  4572. (void)dsi_ctrl_drv_deinit(display_ctrl->ctrl);
  4573. goto error_ctrl_deinit;
  4574. }
  4575. display_ctrl->ctrl->dma_cmd_workq = display->dma_cmd_workq;
  4576. memcpy(&info.c_clks[i],
  4577. (&display_ctrl->ctrl->clk_info.core_clks),
  4578. sizeof(struct dsi_core_clk_info));
  4579. memcpy(&info.l_hs_clks[i],
  4580. (&display_ctrl->ctrl->clk_info.hs_link_clks),
  4581. sizeof(struct dsi_link_hs_clk_info));
  4582. memcpy(&info.l_lp_clks[i],
  4583. (&display_ctrl->ctrl->clk_info.lp_link_clks),
  4584. sizeof(struct dsi_link_lp_clk_info));
  4585. info.c_clks[i].drm = drm;
  4586. info.ctrl_index[i] = display_ctrl->ctrl->cell_index;
  4587. }
  4588. info.pre_clkoff_cb = dsi_pre_clkoff_cb;
  4589. info.pre_clkon_cb = dsi_pre_clkon_cb;
  4590. info.post_clkoff_cb = dsi_post_clkoff_cb;
  4591. info.post_clkon_cb = dsi_post_clkon_cb;
  4592. info.phy_config_cb = dsi_display_phy_configure;
  4593. info.phy_pll_toggle_cb = dsi_display_phy_pll_toggle;
  4594. info.priv_data = display;
  4595. info.master_ndx = display->clk_master_idx;
  4596. info.dsi_ctrl_count = display->ctrl_count;
  4597. snprintf(info.name, MAX_STRING_LEN,
  4598. "DSI_MNGR-%s", display->name);
  4599. display->clk_mngr = dsi_display_clk_mngr_register(&info);
  4600. if (IS_ERR_OR_NULL(display->clk_mngr)) {
  4601. rc = PTR_ERR(display->clk_mngr);
  4602. display->clk_mngr = NULL;
  4603. DSI_ERR("dsi clock registration failed, rc = %d\n", rc);
  4604. goto error_ctrl_deinit;
  4605. }
  4606. handle = dsi_register_clk_handle(display->clk_mngr, client1);
  4607. if (IS_ERR_OR_NULL(handle)) {
  4608. rc = PTR_ERR(handle);
  4609. DSI_ERR("failed to register %s client, rc = %d\n",
  4610. client1, rc);
  4611. goto error_clk_deinit;
  4612. } else {
  4613. display->dsi_clk_handle = handle;
  4614. }
  4615. handle = dsi_register_clk_handle(display->clk_mngr, client2);
  4616. if (IS_ERR_OR_NULL(handle)) {
  4617. rc = PTR_ERR(handle);
  4618. DSI_ERR("failed to register %s client, rc = %d\n",
  4619. client2, rc);
  4620. goto error_clk_client_deinit;
  4621. } else {
  4622. display->mdp_clk_handle = handle;
  4623. }
  4624. clk_cb.priv = display;
  4625. clk_cb.dsi_clk_cb = dsi_display_clk_ctrl_cb;
  4626. display_for_each_ctrl(i, display) {
  4627. display_ctrl = &display->ctrl[i];
  4628. rc = dsi_ctrl_clk_cb_register(display_ctrl->ctrl, &clk_cb);
  4629. if (rc) {
  4630. DSI_ERR("[%s] failed to register ctrl clk_cb[%d], rc=%d\n",
  4631. display->name, i, rc);
  4632. goto error_ctrl_deinit;
  4633. }
  4634. rc = dsi_phy_clk_cb_register(display_ctrl->phy, &clk_cb);
  4635. if (rc) {
  4636. DSI_ERR("[%s] failed to register phy clk_cb[%d], rc=%d\n",
  4637. display->name, i, rc);
  4638. goto error_ctrl_deinit;
  4639. }
  4640. }
  4641. dsi_display_update_byte_intf_div(display);
  4642. rc = dsi_display_mipi_host_init(display);
  4643. if (rc) {
  4644. DSI_ERR("[%s] failed to initialize mipi host, rc=%d\n",
  4645. display->name, rc);
  4646. goto error_ctrl_deinit;
  4647. }
  4648. rc = dsi_panel_drv_init(display->panel, &display->host);
  4649. if (rc) {
  4650. if (rc != -EPROBE_DEFER)
  4651. DSI_ERR("[%s] failed to initialize panel driver, rc=%d\n",
  4652. display->name, rc);
  4653. goto error_host_deinit;
  4654. }
  4655. DSI_INFO("Successfully bind display panel '%s'\n", display->name);
  4656. display->drm_dev = drm;
  4657. display_for_each_ctrl(i, display) {
  4658. display_ctrl = &display->ctrl[i];
  4659. if (!display_ctrl->phy || !display_ctrl->ctrl)
  4660. continue;
  4661. display_ctrl->ctrl->drm_dev = drm;
  4662. rc = dsi_phy_set_clk_freq(display_ctrl->phy,
  4663. &display_ctrl->ctrl->clk_freq);
  4664. if (rc) {
  4665. DSI_ERR("[%s] failed to set phy clk freq, rc=%d\n",
  4666. display->name, rc);
  4667. goto error;
  4668. }
  4669. }
  4670. /* register te irq handler */
  4671. dsi_display_register_te_irq(display);
  4672. msm_register_vm_event(master, dev, &vm_event_ops, (void *)display);
  4673. goto error;
  4674. error_host_deinit:
  4675. (void)dsi_display_mipi_host_deinit(display);
  4676. error_clk_client_deinit:
  4677. (void)dsi_deregister_clk_handle(display->dsi_clk_handle);
  4678. error_clk_deinit:
  4679. (void)dsi_display_clk_mngr_deregister(display->clk_mngr);
  4680. error_ctrl_deinit:
  4681. for (i = i - 1; i >= 0; i--) {
  4682. display_ctrl = &display->ctrl[i];
  4683. (void)dsi_phy_drv_deinit(display_ctrl->phy);
  4684. (void)dsi_ctrl_drv_deinit(display_ctrl->ctrl);
  4685. }
  4686. (void)dsi_display_debugfs_deinit(display);
  4687. error:
  4688. mutex_unlock(&display->display_lock);
  4689. return rc;
  4690. }
  4691. /**
  4692. * dsi_display_unbind - unbind dsi from controlling device
  4693. * @dev: Pointer to base of platform device
  4694. * @master: Pointer to container of drm device
  4695. * @data: Pointer to private data
  4696. */
  4697. static void dsi_display_unbind(struct device *dev,
  4698. struct device *master, void *data)
  4699. {
  4700. struct dsi_display_ctrl *display_ctrl;
  4701. struct dsi_display *display;
  4702. struct platform_device *pdev = to_platform_device(dev);
  4703. int i, rc = 0;
  4704. if (!dev || !pdev || !master) {
  4705. DSI_ERR("invalid param(s)\n");
  4706. return;
  4707. }
  4708. display = platform_get_drvdata(pdev);
  4709. if (!display || !display->panel_node) {
  4710. DSI_ERR("invalid display\n");
  4711. return;
  4712. }
  4713. mutex_lock(&display->display_lock);
  4714. rc = dsi_display_mipi_host_deinit(display);
  4715. if (rc)
  4716. DSI_ERR("[%s] failed to deinit mipi hosts, rc=%d\n",
  4717. display->name,
  4718. rc);
  4719. display_for_each_ctrl(i, display) {
  4720. display_ctrl = &display->ctrl[i];
  4721. rc = dsi_phy_drv_deinit(display_ctrl->phy);
  4722. if (rc)
  4723. DSI_ERR("[%s] failed to deinit phy%d driver, rc=%d\n",
  4724. display->name, i, rc);
  4725. display->ctrl->ctrl->dma_cmd_workq = NULL;
  4726. rc = dsi_ctrl_drv_deinit(display_ctrl->ctrl);
  4727. if (rc)
  4728. DSI_ERR("[%s] failed to deinit ctrl%d driver, rc=%d\n",
  4729. display->name, i, rc);
  4730. }
  4731. atomic_set(&display->clkrate_change_pending, 0);
  4732. (void)dsi_display_debugfs_deinit(display);
  4733. mutex_unlock(&display->display_lock);
  4734. }
  4735. static const struct component_ops dsi_display_comp_ops = {
  4736. .bind = dsi_display_bind,
  4737. .unbind = dsi_display_unbind,
  4738. };
  4739. static struct platform_driver dsi_display_driver = {
  4740. .probe = dsi_display_dev_probe,
  4741. .remove = dsi_display_dev_remove,
  4742. .driver = {
  4743. .name = "msm-dsi-display",
  4744. .of_match_table = dsi_display_dt_match,
  4745. .suppress_bind_attrs = true,
  4746. },
  4747. };
  4748. static int dsi_display_init(struct dsi_display *display)
  4749. {
  4750. int rc = 0;
  4751. struct platform_device *pdev = display->pdev;
  4752. rc = _dsi_display_dev_init(display);
  4753. if (rc) {
  4754. DSI_ERR("device init failed, rc=%d\n", rc);
  4755. goto end;
  4756. }
  4757. /*
  4758. * Vote on panel regulator is added to make sure panel regulators
  4759. * are ON for cont-splash enabled usecase.
  4760. * This panel regulator vote will be removed only in:
  4761. * 1) device suspend when cont-splash is enabled.
  4762. * 2) cont_splash_res_disable() when cont-splash is disabled.
  4763. * For GKI, adding this vote will make sure that sync_state
  4764. * kernel driver doesn't disable the panel regulators after
  4765. * dsi probe is complete.
  4766. */
  4767. if (display->panel) {
  4768. rc = dsi_pwr_enable_regulator(&display->panel->power_info,
  4769. true);
  4770. if (rc) {
  4771. DSI_ERR("[%s] failed to enable vregs, rc=%d\n",
  4772. display->panel->name, rc);
  4773. return rc;
  4774. }
  4775. }
  4776. rc = component_add(&pdev->dev, &dsi_display_comp_ops);
  4777. if (rc)
  4778. DSI_ERR("component add failed, rc=%d\n", rc);
  4779. DSI_DEBUG("component add success: %s\n", display->name);
  4780. end:
  4781. return rc;
  4782. }
  4783. static void dsi_display_firmware_display(const struct firmware *fw,
  4784. void *context)
  4785. {
  4786. struct dsi_display *display = context;
  4787. if (fw) {
  4788. DSI_INFO("reading data from firmware, size=%zd\n",
  4789. fw->size);
  4790. display->fw = fw;
  4791. if (!strcmp(display->display_type, "primary"))
  4792. display->name = "dsi_firmware_display";
  4793. else if (!strcmp(display->display_type, "secondary"))
  4794. display->name = "dsi_firmware_display_secondary";
  4795. } else {
  4796. DSI_INFO("no firmware available, fallback to device node\n");
  4797. }
  4798. if (dsi_display_init(display))
  4799. return;
  4800. DSI_DEBUG("success\n");
  4801. }
  4802. int dsi_display_dev_probe(struct platform_device *pdev)
  4803. {
  4804. struct dsi_display *display = NULL;
  4805. struct device_node *node = NULL, *panel_node = NULL, *mdp_node = NULL;
  4806. int rc = 0, index = DSI_PRIMARY;
  4807. bool firm_req = false;
  4808. struct dsi_display_boot_param *boot_disp;
  4809. if (!pdev || !pdev->dev.of_node) {
  4810. DSI_ERR("pdev not found\n");
  4811. rc = -ENODEV;
  4812. goto end;
  4813. }
  4814. display = devm_kzalloc(&pdev->dev, sizeof(*display), GFP_KERNEL);
  4815. if (!display) {
  4816. rc = -ENOMEM;
  4817. goto end;
  4818. }
  4819. mutex_init(&display->display_lock);
  4820. display->dma_cmd_workq = create_singlethread_workqueue(
  4821. "dsi_dma_cmd_workq");
  4822. if (!display->dma_cmd_workq) {
  4823. DSI_ERR("failed to create work queue\n");
  4824. rc = -EINVAL;
  4825. goto end;
  4826. }
  4827. mdp_node = of_parse_phandle(pdev->dev.of_node, "qcom,mdp", 0);
  4828. if (!mdp_node) {
  4829. DSI_ERR("mdp_node not found\n");
  4830. rc = -ENODEV;
  4831. goto end;
  4832. }
  4833. display->trusted_vm_env = of_property_read_bool(mdp_node,
  4834. "qcom,sde-trusted-vm-env");
  4835. if (display->trusted_vm_env)
  4836. DSI_INFO("Display enabled with trusted vm path\n");
  4837. /* initialize panel id to UINT64_MAX */
  4838. display->panel_id = ~0x0;
  4839. display->display_type = of_get_property(pdev->dev.of_node,
  4840. "label", NULL);
  4841. if (!display->display_type)
  4842. display->display_type = "primary";
  4843. if (!strcmp(display->display_type, "secondary"))
  4844. index = DSI_SECONDARY;
  4845. boot_disp = &boot_displays[index];
  4846. node = pdev->dev.of_node;
  4847. if (boot_disp->boot_disp_en) {
  4848. /* The panel name should be same as UEFI name index */
  4849. panel_node = of_find_node_by_name(mdp_node, boot_disp->name);
  4850. if (!panel_node)
  4851. DSI_WARN("panel_node %s not found\n", boot_disp->name);
  4852. } else {
  4853. panel_node = of_parse_phandle(node,
  4854. "qcom,dsi-default-panel", 0);
  4855. if (!panel_node)
  4856. DSI_WARN("default panel not found\n");
  4857. }
  4858. boot_disp->node = pdev->dev.of_node;
  4859. boot_disp->disp = display;
  4860. display->panel_node = panel_node;
  4861. display->pdev = pdev;
  4862. display->boot_disp = boot_disp;
  4863. dsi_display_parse_cmdline_topology(display, index);
  4864. platform_set_drvdata(pdev, display);
  4865. rc = dsi_display_parse_dt(display);
  4866. if (rc) {
  4867. DSI_ERR("[%s] failed to parse dt, rc=%d\n", display->name, rc);
  4868. goto end;
  4869. }
  4870. rc = dsi_display_validate_resources(display);
  4871. if (rc) {
  4872. DSI_ERR("[%s] needed resources not probed yet, rc=%d\n",
  4873. display->name, rc);
  4874. goto end;
  4875. }
  4876. /* initialize display in firmware callback */
  4877. if (!boot_disp->boot_disp_en &&
  4878. IS_ENABLED(CONFIG_DSI_PARSER) &&
  4879. !display->trusted_vm_env) {
  4880. if (!strcmp(display->display_type, "primary"))
  4881. firm_req = !request_firmware_nowait(
  4882. THIS_MODULE, 1, "dsi_prop",
  4883. &pdev->dev, GFP_KERNEL, display,
  4884. dsi_display_firmware_display);
  4885. else if (!strcmp(display->display_type, "secondary"))
  4886. firm_req = !request_firmware_nowait(
  4887. THIS_MODULE, 1, "dsi_prop_sec",
  4888. &pdev->dev, GFP_KERNEL, display,
  4889. dsi_display_firmware_display);
  4890. }
  4891. if (!firm_req) {
  4892. rc = dsi_display_init(display);
  4893. if (rc)
  4894. goto end;
  4895. }
  4896. return 0;
  4897. end:
  4898. if (display) {
  4899. mutex_destroy(&display->display_lock);
  4900. devm_kfree(&pdev->dev, display);
  4901. }
  4902. return rc;
  4903. }
  4904. int dsi_display_dev_remove(struct platform_device *pdev)
  4905. {
  4906. int rc = 0, i = 0;
  4907. struct dsi_display *display;
  4908. struct dsi_display_ctrl *ctrl;
  4909. if (!pdev) {
  4910. DSI_ERR("Invalid device\n");
  4911. return -EINVAL;
  4912. }
  4913. display = platform_get_drvdata(pdev);
  4914. /* decrement ref count */
  4915. of_node_put(display->panel_node);
  4916. if (display->dma_cmd_workq) {
  4917. flush_workqueue(display->dma_cmd_workq);
  4918. destroy_workqueue(display->dma_cmd_workq);
  4919. display->dma_cmd_workq = NULL;
  4920. display_for_each_ctrl(i, display) {
  4921. ctrl = &display->ctrl[i];
  4922. if (!ctrl->ctrl)
  4923. continue;
  4924. ctrl->ctrl->dma_cmd_workq = NULL;
  4925. }
  4926. }
  4927. (void)_dsi_display_dev_deinit(display);
  4928. platform_set_drvdata(pdev, NULL);
  4929. devm_kfree(&pdev->dev, display);
  4930. return rc;
  4931. }
  4932. int dsi_display_get_num_of_displays(void)
  4933. {
  4934. int i, count = 0;
  4935. for (i = 0; i < MAX_DSI_ACTIVE_DISPLAY; i++) {
  4936. struct dsi_display *display = boot_displays[i].disp;
  4937. if ((display && display->panel_node) ||
  4938. (display && display->fw))
  4939. count++;
  4940. }
  4941. return count;
  4942. }
  4943. int dsi_display_get_active_displays(void **display_array, u32 max_display_count)
  4944. {
  4945. int index = 0, count = 0;
  4946. if (!display_array || !max_display_count) {
  4947. DSI_ERR("invalid params\n");
  4948. return 0;
  4949. }
  4950. for (index = 0; index < MAX_DSI_ACTIVE_DISPLAY; index++) {
  4951. struct dsi_display *display = boot_displays[index].disp;
  4952. if ((display && display->panel_node) ||
  4953. (display && display->fw))
  4954. display_array[count++] = display;
  4955. }
  4956. return count;
  4957. }
  4958. void dsi_display_set_active_state(struct dsi_display *display, bool is_active)
  4959. {
  4960. if (!display)
  4961. return;
  4962. mutex_lock(&display->display_lock);
  4963. display->is_active = is_active;
  4964. mutex_unlock(&display->display_lock);
  4965. }
  4966. int dsi_display_drm_bridge_init(struct dsi_display *display,
  4967. struct drm_encoder *enc)
  4968. {
  4969. int rc = 0;
  4970. struct dsi_bridge *bridge;
  4971. struct msm_drm_private *priv = NULL;
  4972. if (!display || !display->drm_dev || !enc) {
  4973. DSI_ERR("invalid param(s)\n");
  4974. return -EINVAL;
  4975. }
  4976. mutex_lock(&display->display_lock);
  4977. priv = display->drm_dev->dev_private;
  4978. if (!priv) {
  4979. DSI_ERR("Private data is not present\n");
  4980. rc = -EINVAL;
  4981. goto error;
  4982. }
  4983. if (display->bridge) {
  4984. DSI_ERR("display is already initialize\n");
  4985. goto error;
  4986. }
  4987. bridge = dsi_drm_bridge_init(display, display->drm_dev, enc);
  4988. if (IS_ERR_OR_NULL(bridge)) {
  4989. rc = PTR_ERR(bridge);
  4990. DSI_ERR("[%s] brige init failed, %d\n", display->name, rc);
  4991. goto error;
  4992. }
  4993. display->bridge = bridge;
  4994. priv->bridges[priv->num_bridges++] = &bridge->base;
  4995. error:
  4996. mutex_unlock(&display->display_lock);
  4997. return rc;
  4998. }
  4999. int dsi_display_drm_bridge_deinit(struct dsi_display *display)
  5000. {
  5001. int rc = 0;
  5002. if (!display) {
  5003. DSI_ERR("Invalid params\n");
  5004. return -EINVAL;
  5005. }
  5006. mutex_lock(&display->display_lock);
  5007. dsi_drm_bridge_cleanup(display->bridge);
  5008. display->bridge = NULL;
  5009. mutex_unlock(&display->display_lock);
  5010. return rc;
  5011. }
  5012. /* Hook functions to call external connector, pointer validation is
  5013. * done in dsi_display_drm_ext_bridge_init.
  5014. */
  5015. static enum drm_connector_status dsi_display_drm_ext_detect(
  5016. struct drm_connector *connector,
  5017. bool force,
  5018. void *disp)
  5019. {
  5020. struct dsi_display *display = disp;
  5021. return display->ext_conn->funcs->detect(display->ext_conn, force);
  5022. }
  5023. static int dsi_display_drm_ext_get_modes(
  5024. struct drm_connector *connector, void *disp,
  5025. const struct msm_resource_caps_info *avail_res)
  5026. {
  5027. struct dsi_display *display = disp;
  5028. struct drm_display_mode *pmode, *pt;
  5029. int count;
  5030. /* if there are modes defined in panel, ignore external modes */
  5031. if (display->panel->num_timing_nodes)
  5032. return dsi_connector_get_modes(connector, disp, avail_res);
  5033. count = display->ext_conn->helper_private->get_modes(
  5034. display->ext_conn);
  5035. list_for_each_entry_safe(pmode, pt,
  5036. &display->ext_conn->probed_modes, head) {
  5037. list_move_tail(&pmode->head, &connector->probed_modes);
  5038. }
  5039. connector->display_info = display->ext_conn->display_info;
  5040. return count;
  5041. }
  5042. static enum drm_mode_status dsi_display_drm_ext_mode_valid(
  5043. struct drm_connector *connector,
  5044. struct drm_display_mode *mode,
  5045. void *disp, const struct msm_resource_caps_info *avail_res)
  5046. {
  5047. struct dsi_display *display = disp;
  5048. enum drm_mode_status status;
  5049. /* always do internal mode_valid check */
  5050. status = dsi_conn_mode_valid(connector, mode, disp, avail_res);
  5051. if (status != MODE_OK)
  5052. return status;
  5053. return display->ext_conn->helper_private->mode_valid(
  5054. display->ext_conn, mode);
  5055. }
  5056. static int dsi_display_drm_ext_atomic_check(struct drm_connector *connector,
  5057. void *disp,
  5058. struct drm_atomic_state *state)
  5059. {
  5060. struct dsi_display *display = disp;
  5061. struct drm_connector_state *c_state;
  5062. c_state = drm_atomic_get_new_connector_state(state, connector);
  5063. return display->ext_conn->helper_private->atomic_check(
  5064. display->ext_conn, state);
  5065. }
  5066. static int dsi_display_ext_get_info(struct drm_connector *connector,
  5067. struct msm_display_info *info, void *disp)
  5068. {
  5069. struct dsi_display *display;
  5070. int i;
  5071. if (!info || !disp) {
  5072. DSI_ERR("invalid params\n");
  5073. return -EINVAL;
  5074. }
  5075. display = disp;
  5076. if (!display->panel) {
  5077. DSI_ERR("invalid display panel\n");
  5078. return -EINVAL;
  5079. }
  5080. mutex_lock(&display->display_lock);
  5081. memset(info, 0, sizeof(struct msm_display_info));
  5082. info->intf_type = DRM_MODE_CONNECTOR_DSI;
  5083. info->num_of_h_tiles = display->ctrl_count;
  5084. for (i = 0; i < info->num_of_h_tiles; i++)
  5085. info->h_tile_instance[i] = display->ctrl[i].ctrl->cell_index;
  5086. info->is_connected = connector->status != connector_status_disconnected;
  5087. if (!strcmp(display->display_type, "primary"))
  5088. info->display_type = SDE_CONNECTOR_PRIMARY;
  5089. else if (!strcmp(display->display_type, "secondary"))
  5090. info->display_type = SDE_CONNECTOR_SECONDARY;
  5091. info->capabilities |= (MSM_DISPLAY_CAP_VID_MODE |
  5092. MSM_DISPLAY_CAP_EDID | MSM_DISPLAY_CAP_HOT_PLUG);
  5093. info->curr_panel_mode = MSM_DISPLAY_VIDEO_MODE;
  5094. mutex_unlock(&display->display_lock);
  5095. return 0;
  5096. }
  5097. static int dsi_display_ext_get_mode_info(struct drm_connector *connector,
  5098. const struct drm_display_mode *drm_mode,
  5099. struct msm_mode_info *mode_info,
  5100. void *display, const struct msm_resource_caps_info *avail_res)
  5101. {
  5102. struct msm_display_topology *topology;
  5103. if (!drm_mode || !mode_info ||
  5104. !avail_res || !avail_res->max_mixer_width)
  5105. return -EINVAL;
  5106. memset(mode_info, 0, sizeof(*mode_info));
  5107. mode_info->frame_rate = drm_mode_vrefresh(drm_mode);
  5108. mode_info->vtotal = drm_mode->vtotal;
  5109. topology = &mode_info->topology;
  5110. topology->num_lm = (avail_res->max_mixer_width
  5111. <= drm_mode->hdisplay) ? 2 : 1;
  5112. topology->num_enc = 0;
  5113. topology->num_intf = topology->num_lm;
  5114. mode_info->comp_info.comp_type = MSM_DISPLAY_COMPRESSION_NONE;
  5115. return 0;
  5116. }
  5117. static struct dsi_display_ext_bridge *dsi_display_ext_get_bridge(
  5118. struct drm_bridge *bridge)
  5119. {
  5120. struct msm_drm_private *priv;
  5121. struct sde_kms *sde_kms;
  5122. struct drm_connector *conn;
  5123. struct drm_connector_list_iter conn_iter;
  5124. struct sde_connector *sde_conn;
  5125. struct dsi_display *display;
  5126. struct dsi_display_ext_bridge *dsi_bridge = NULL;
  5127. int i;
  5128. if (!bridge || !bridge->encoder) {
  5129. SDE_ERROR("invalid argument\n");
  5130. return NULL;
  5131. }
  5132. priv = bridge->dev->dev_private;
  5133. sde_kms = to_sde_kms(priv->kms);
  5134. drm_connector_list_iter_begin(sde_kms->dev, &conn_iter);
  5135. drm_for_each_connector_iter(conn, &conn_iter) {
  5136. sde_conn = to_sde_connector(conn);
  5137. if (sde_conn->encoder == bridge->encoder) {
  5138. display = sde_conn->display;
  5139. display_for_each_ctrl(i, display) {
  5140. if (display->ext_bridge[i].bridge == bridge) {
  5141. dsi_bridge = &display->ext_bridge[i];
  5142. break;
  5143. }
  5144. }
  5145. }
  5146. }
  5147. drm_connector_list_iter_end(&conn_iter);
  5148. return dsi_bridge;
  5149. }
  5150. static void dsi_display_drm_ext_adjust_timing(
  5151. const struct dsi_display *display,
  5152. struct drm_display_mode *mode)
  5153. {
  5154. mode->hdisplay /= display->ctrl_count;
  5155. mode->hsync_start /= display->ctrl_count;
  5156. mode->hsync_end /= display->ctrl_count;
  5157. mode->htotal /= display->ctrl_count;
  5158. mode->hskew /= display->ctrl_count;
  5159. mode->clock /= display->ctrl_count;
  5160. }
  5161. static enum drm_mode_status dsi_display_drm_ext_bridge_mode_valid(
  5162. struct drm_bridge *bridge,
  5163. const struct drm_display_info *info,
  5164. const struct drm_display_mode *mode)
  5165. {
  5166. struct dsi_display_ext_bridge *ext_bridge;
  5167. struct drm_display_mode tmp;
  5168. ext_bridge = dsi_display_ext_get_bridge(bridge);
  5169. if (!ext_bridge)
  5170. return MODE_ERROR;
  5171. tmp = *mode;
  5172. dsi_display_drm_ext_adjust_timing(ext_bridge->display, &tmp);
  5173. return ext_bridge->orig_funcs->mode_valid(bridge, info, &tmp);
  5174. }
  5175. static bool dsi_display_drm_ext_bridge_mode_fixup(
  5176. struct drm_bridge *bridge,
  5177. const struct drm_display_mode *mode,
  5178. struct drm_display_mode *adjusted_mode)
  5179. {
  5180. struct dsi_display_ext_bridge *ext_bridge;
  5181. struct drm_display_mode tmp;
  5182. ext_bridge = dsi_display_ext_get_bridge(bridge);
  5183. if (!ext_bridge)
  5184. return false;
  5185. tmp = *mode;
  5186. dsi_display_drm_ext_adjust_timing(ext_bridge->display, &tmp);
  5187. return ext_bridge->orig_funcs->mode_fixup(bridge, &tmp, &tmp);
  5188. }
  5189. static void dsi_display_drm_ext_bridge_mode_set(
  5190. struct drm_bridge *bridge,
  5191. const struct drm_display_mode *mode,
  5192. const struct drm_display_mode *adjusted_mode)
  5193. {
  5194. struct dsi_display_ext_bridge *ext_bridge;
  5195. struct drm_display_mode tmp;
  5196. ext_bridge = dsi_display_ext_get_bridge(bridge);
  5197. if (!ext_bridge)
  5198. return;
  5199. tmp = *mode;
  5200. dsi_display_drm_ext_adjust_timing(ext_bridge->display, &tmp);
  5201. ext_bridge->orig_funcs->mode_set(bridge, &tmp, &tmp);
  5202. }
  5203. static int dsi_host_ext_attach(struct mipi_dsi_host *host,
  5204. struct mipi_dsi_device *dsi)
  5205. {
  5206. struct dsi_display *display = to_dsi_display(host);
  5207. struct dsi_panel *panel;
  5208. if (!host || !dsi || !display->panel) {
  5209. DSI_ERR("Invalid param\n");
  5210. return -EINVAL;
  5211. }
  5212. DSI_DEBUG("DSI[%s]: channel=%d, lanes=%d, format=%d, mode_flags=%lx\n",
  5213. dsi->name, dsi->channel, dsi->lanes,
  5214. dsi->format, dsi->mode_flags);
  5215. panel = display->panel;
  5216. panel->host_config.data_lanes = 0;
  5217. if (dsi->lanes > 0)
  5218. panel->host_config.data_lanes |= DSI_DATA_LANE_0;
  5219. if (dsi->lanes > 1)
  5220. panel->host_config.data_lanes |= DSI_DATA_LANE_1;
  5221. if (dsi->lanes > 2)
  5222. panel->host_config.data_lanes |= DSI_DATA_LANE_2;
  5223. if (dsi->lanes > 3)
  5224. panel->host_config.data_lanes |= DSI_DATA_LANE_3;
  5225. switch (dsi->format) {
  5226. case MIPI_DSI_FMT_RGB888:
  5227. panel->host_config.dst_format = DSI_PIXEL_FORMAT_RGB888;
  5228. break;
  5229. case MIPI_DSI_FMT_RGB666:
  5230. panel->host_config.dst_format = DSI_PIXEL_FORMAT_RGB666_LOOSE;
  5231. break;
  5232. case MIPI_DSI_FMT_RGB666_PACKED:
  5233. panel->host_config.dst_format = DSI_PIXEL_FORMAT_RGB666;
  5234. break;
  5235. case MIPI_DSI_FMT_RGB565:
  5236. default:
  5237. panel->host_config.dst_format = DSI_PIXEL_FORMAT_RGB565;
  5238. break;
  5239. }
  5240. if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
  5241. panel->panel_mode = DSI_OP_VIDEO_MODE;
  5242. if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
  5243. panel->video_config.traffic_mode =
  5244. DSI_VIDEO_TRAFFIC_BURST_MODE;
  5245. else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
  5246. panel->video_config.traffic_mode =
  5247. DSI_VIDEO_TRAFFIC_SYNC_PULSES;
  5248. else
  5249. panel->video_config.traffic_mode =
  5250. DSI_VIDEO_TRAFFIC_SYNC_START_EVENTS;
  5251. panel->video_config.hsa_lp11_en =
  5252. dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSA;
  5253. panel->video_config.hbp_lp11_en =
  5254. dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP;
  5255. panel->video_config.hfp_lp11_en =
  5256. dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP;
  5257. panel->video_config.pulse_mode_hsa_he =
  5258. dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE;
  5259. } else {
  5260. panel->panel_mode = DSI_OP_CMD_MODE;
  5261. DSI_ERR("command mode not supported by ext bridge\n");
  5262. return -ENOTSUPP;
  5263. }
  5264. panel->bl_config.type = DSI_BACKLIGHT_UNKNOWN;
  5265. return 0;
  5266. }
  5267. static struct mipi_dsi_host_ops dsi_host_ext_ops = {
  5268. .attach = dsi_host_ext_attach,
  5269. .detach = dsi_host_detach,
  5270. .transfer = dsi_host_transfer,
  5271. };
  5272. struct drm_panel *dsi_display_get_drm_panel(struct dsi_display *display)
  5273. {
  5274. if (!display || !display->panel) {
  5275. pr_err("invalid param(s)\n");
  5276. return NULL;
  5277. }
  5278. return &display->panel->drm_panel;
  5279. }
  5280. int dsi_display_drm_ext_bridge_init(struct dsi_display *display,
  5281. struct drm_encoder *encoder, struct drm_connector *connector)
  5282. {
  5283. struct drm_device *drm;
  5284. struct drm_bridge *bridge;
  5285. struct drm_bridge *ext_bridge;
  5286. struct drm_connector *ext_conn;
  5287. struct sde_connector *sde_conn;
  5288. struct drm_bridge *prev_bridge;
  5289. int rc = 0, i;
  5290. if (!display || !encoder || !connector)
  5291. return -EINVAL;
  5292. drm = encoder->dev;
  5293. bridge = drm_bridge_chain_get_first_bridge(encoder);
  5294. sde_conn = to_sde_connector(connector);
  5295. prev_bridge = bridge;
  5296. if (display->panel && !display->panel->host_config.ext_bridge_mode)
  5297. return 0;
  5298. for (i = 0; i < display->ext_bridge_cnt; i++) {
  5299. struct dsi_display_ext_bridge *ext_bridge_info =
  5300. &display->ext_bridge[i];
  5301. struct drm_encoder *c_encoder;
  5302. /* return if ext bridge is already initialized */
  5303. if (ext_bridge_info->bridge)
  5304. return 0;
  5305. ext_bridge = of_drm_find_bridge(ext_bridge_info->node_of);
  5306. if (IS_ERR_OR_NULL(ext_bridge)) {
  5307. rc = PTR_ERR(ext_bridge);
  5308. DSI_ERR("failed to find ext bridge\n");
  5309. goto error;
  5310. }
  5311. /* override functions for mode adjustment */
  5312. if (display->ext_bridge_cnt > 1) {
  5313. ext_bridge_info->bridge_funcs = *ext_bridge->funcs;
  5314. if (ext_bridge->funcs->mode_fixup)
  5315. ext_bridge_info->bridge_funcs.mode_fixup =
  5316. dsi_display_drm_ext_bridge_mode_fixup;
  5317. if (ext_bridge->funcs->mode_valid)
  5318. ext_bridge_info->bridge_funcs.mode_valid =
  5319. dsi_display_drm_ext_bridge_mode_valid;
  5320. if (ext_bridge->funcs->mode_set)
  5321. ext_bridge_info->bridge_funcs.mode_set =
  5322. dsi_display_drm_ext_bridge_mode_set;
  5323. ext_bridge_info->orig_funcs = ext_bridge->funcs;
  5324. ext_bridge->funcs = &ext_bridge_info->bridge_funcs;
  5325. }
  5326. rc = drm_bridge_attach(encoder, ext_bridge, prev_bridge, 0);
  5327. if (rc) {
  5328. DSI_ERR("[%s] ext brige attach failed, %d\n",
  5329. display->name, rc);
  5330. goto error;
  5331. }
  5332. ext_bridge_info->display = display;
  5333. ext_bridge_info->bridge = ext_bridge;
  5334. prev_bridge = ext_bridge;
  5335. /* ext bridge will init its own connector during attach,
  5336. * we need to extract it out of the connector list
  5337. */
  5338. spin_lock_irq(&drm->mode_config.connector_list_lock);
  5339. ext_conn = list_last_entry(&drm->mode_config.connector_list,
  5340. struct drm_connector, head);
  5341. drm_connector_for_each_possible_encoder(ext_conn, c_encoder)
  5342. break;
  5343. if (!c_encoder) {
  5344. DSI_ERR("failed to get encoder\n");
  5345. rc = PTR_ERR(c_encoder);
  5346. spin_unlock_irq(&drm->mode_config.connector_list_lock);
  5347. goto error;
  5348. }
  5349. if (ext_conn && ext_conn != connector &&
  5350. c_encoder->base.id == bridge->encoder->base.id) {
  5351. list_del_init(&ext_conn->head);
  5352. display->ext_conn = ext_conn;
  5353. }
  5354. spin_unlock_irq(&drm->mode_config.connector_list_lock);
  5355. /* if there is no valid external connector created, or in split
  5356. * mode, default setting is used from panel defined in DT file.
  5357. */
  5358. if (!display->ext_conn ||
  5359. !display->ext_conn->funcs ||
  5360. !display->ext_conn->helper_private ||
  5361. display->ext_bridge_cnt > 1) {
  5362. display->ext_conn = NULL;
  5363. continue;
  5364. }
  5365. /* otherwise, hook up the functions to use external connector */
  5366. if (display->ext_conn->funcs->detect)
  5367. sde_conn->ops.detect = dsi_display_drm_ext_detect;
  5368. if (display->ext_conn->helper_private->get_modes)
  5369. sde_conn->ops.get_modes =
  5370. dsi_display_drm_ext_get_modes;
  5371. if (display->ext_conn->helper_private->mode_valid)
  5372. sde_conn->ops.mode_valid =
  5373. dsi_display_drm_ext_mode_valid;
  5374. if (display->ext_conn->helper_private->atomic_check)
  5375. sde_conn->ops.atomic_check =
  5376. dsi_display_drm_ext_atomic_check;
  5377. sde_conn->ops.get_info =
  5378. dsi_display_ext_get_info;
  5379. sde_conn->ops.get_mode_info =
  5380. dsi_display_ext_get_mode_info;
  5381. /* add support to attach/detach */
  5382. display->host.ops = &dsi_host_ext_ops;
  5383. }
  5384. return 0;
  5385. error:
  5386. return rc;
  5387. }
  5388. int dsi_display_get_info(struct drm_connector *connector,
  5389. struct msm_display_info *info, void *disp)
  5390. {
  5391. struct dsi_display *display;
  5392. struct dsi_panel_phy_props phy_props;
  5393. struct dsi_host_common_cfg *host;
  5394. int i, rc;
  5395. if (!info || !disp) {
  5396. DSI_ERR("invalid params\n");
  5397. return -EINVAL;
  5398. }
  5399. display = disp;
  5400. if (!display->panel) {
  5401. DSI_ERR("invalid display panel\n");
  5402. return -EINVAL;
  5403. }
  5404. mutex_lock(&display->display_lock);
  5405. rc = dsi_panel_get_phy_props(display->panel, &phy_props);
  5406. if (rc) {
  5407. DSI_ERR("[%s] failed to get panel phy props, rc=%d\n",
  5408. display->name, rc);
  5409. goto error;
  5410. }
  5411. memset(info, 0, sizeof(struct msm_display_info));
  5412. info->intf_type = DRM_MODE_CONNECTOR_DSI;
  5413. info->num_of_h_tiles = display->ctrl_count;
  5414. for (i = 0; i < info->num_of_h_tiles; i++)
  5415. info->h_tile_instance[i] = display->ctrl[i].ctrl->cell_index;
  5416. info->is_connected = display->is_active;
  5417. if (!strcmp(display->display_type, "primary"))
  5418. info->display_type = SDE_CONNECTOR_PRIMARY;
  5419. else if (!strcmp(display->display_type, "secondary"))
  5420. info->display_type = SDE_CONNECTOR_SECONDARY;
  5421. info->width_mm = phy_props.panel_width_mm;
  5422. info->height_mm = phy_props.panel_height_mm;
  5423. info->max_width = 1920;
  5424. info->max_height = 1080;
  5425. info->qsync_min_fps =
  5426. display->panel->qsync_caps.qsync_min_fps;
  5427. info->has_qsync_min_fps_list =
  5428. (display->panel->qsync_caps.qsync_min_fps_list_len > 0) ?
  5429. true : false;
  5430. info->poms_align_vsync = display->panel->poms_align_vsync;
  5431. switch (display->panel->panel_mode) {
  5432. case DSI_OP_VIDEO_MODE:
  5433. info->curr_panel_mode = MSM_DISPLAY_VIDEO_MODE;
  5434. info->capabilities |= MSM_DISPLAY_CAP_VID_MODE;
  5435. if (display->panel->panel_mode_switch_enabled)
  5436. info->capabilities |= MSM_DISPLAY_CAP_CMD_MODE;
  5437. break;
  5438. case DSI_OP_CMD_MODE:
  5439. info->curr_panel_mode = MSM_DISPLAY_CMD_MODE;
  5440. info->capabilities |= MSM_DISPLAY_CAP_CMD_MODE;
  5441. if (display->panel->panel_mode_switch_enabled)
  5442. info->capabilities |= MSM_DISPLAY_CAP_VID_MODE;
  5443. info->is_te_using_watchdog_timer =
  5444. display->panel->te_using_watchdog_timer |
  5445. display->sw_te_using_wd;
  5446. break;
  5447. default:
  5448. DSI_ERR("unknwown dsi panel mode %d\n",
  5449. display->panel->panel_mode);
  5450. break;
  5451. }
  5452. if (display->panel->esd_config.esd_enabled &&
  5453. !display->sw_te_using_wd)
  5454. info->capabilities |= MSM_DISPLAY_ESD_ENABLED;
  5455. info->te_source = display->te_source;
  5456. host = &display->panel->host_config;
  5457. if (host->split_link.split_link_enabled)
  5458. info->capabilities |= MSM_DISPLAY_SPLIT_LINK;
  5459. info->dsc_count = display->panel->dsc_count;
  5460. info->lm_count = display->panel->lm_count;
  5461. error:
  5462. mutex_unlock(&display->display_lock);
  5463. return rc;
  5464. }
  5465. int dsi_display_get_mode_count(struct dsi_display *display,
  5466. u32 *count)
  5467. {
  5468. if (!display || !display->panel) {
  5469. DSI_ERR("invalid display:%d panel:%d\n", display != NULL,
  5470. display ? display->panel != NULL : 0);
  5471. return -EINVAL;
  5472. }
  5473. mutex_lock(&display->display_lock);
  5474. *count = display->panel->num_display_modes;
  5475. mutex_unlock(&display->display_lock);
  5476. return 0;
  5477. }
  5478. void dsi_display_adjust_mode_timing(struct dsi_display *display,
  5479. struct dsi_display_mode *dsi_mode,
  5480. int lanes, int bpp)
  5481. {
  5482. u64 new_htotal, new_vtotal, htotal, vtotal, old_htotal, div;
  5483. struct dsi_dyn_clk_caps *dyn_clk_caps;
  5484. u32 bits_per_symbol = 16, num_of_symbols = 7; /* For Cphy */
  5485. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  5486. /* Constant FPS is not supported on command mode */
  5487. if (!(dsi_mode->panel_mode_caps & DSI_OP_VIDEO_MODE))
  5488. return;
  5489. if (!dyn_clk_caps->maintain_const_fps)
  5490. return;
  5491. /*
  5492. * When there is a dynamic clock switch, there is small change
  5493. * in FPS. To compensate for this difference in FPS, hfp or vfp
  5494. * is adjusted. It has been assumed that the refined porch values
  5495. * are supported by the panel. This logic can be enhanced further
  5496. * in future by taking min/max porches supported by the panel.
  5497. */
  5498. switch (dyn_clk_caps->type) {
  5499. case DSI_DYN_CLK_TYPE_CONST_FPS_ADJUST_HFP:
  5500. vtotal = DSI_V_TOTAL(&dsi_mode->timing);
  5501. old_htotal = dsi_h_total_dce(&dsi_mode->timing);
  5502. do_div(old_htotal, display->ctrl_count);
  5503. new_htotal = dsi_mode->timing.clk_rate_hz * lanes;
  5504. div = bpp * vtotal * dsi_mode->timing.refresh_rate;
  5505. if (dsi_display_is_type_cphy(display)) {
  5506. new_htotal = new_htotal * bits_per_symbol;
  5507. div = div * num_of_symbols;
  5508. }
  5509. do_div(new_htotal, div);
  5510. if (old_htotal > new_htotal)
  5511. dsi_mode->timing.h_front_porch -=
  5512. ((old_htotal - new_htotal) * display->ctrl_count);
  5513. else
  5514. dsi_mode->timing.h_front_porch +=
  5515. ((new_htotal - old_htotal) * display->ctrl_count);
  5516. break;
  5517. case DSI_DYN_CLK_TYPE_CONST_FPS_ADJUST_VFP:
  5518. htotal = dsi_h_total_dce(&dsi_mode->timing);
  5519. do_div(htotal, display->ctrl_count);
  5520. new_vtotal = dsi_mode->timing.clk_rate_hz * lanes;
  5521. div = bpp * htotal * dsi_mode->timing.refresh_rate;
  5522. if (dsi_display_is_type_cphy(display)) {
  5523. new_vtotal = new_vtotal * bits_per_symbol;
  5524. div = div * num_of_symbols;
  5525. }
  5526. do_div(new_vtotal, div);
  5527. dsi_mode->timing.v_front_porch = new_vtotal -
  5528. dsi_mode->timing.v_back_porch -
  5529. dsi_mode->timing.v_sync_width -
  5530. dsi_mode->timing.v_active;
  5531. break;
  5532. default:
  5533. break;
  5534. }
  5535. }
  5536. static void _dsi_display_populate_bit_clks(struct dsi_display *display,
  5537. int start, int end, u32 *mode_idx)
  5538. {
  5539. struct dsi_dyn_clk_caps *dyn_clk_caps;
  5540. struct dsi_display_mode *src, *dst;
  5541. struct dsi_host_common_cfg *cfg;
  5542. struct dsi_display_mode_priv_info *priv_info;
  5543. int i, j, total_modes, bpp, lanes = 0;
  5544. size_t size = 0;
  5545. if (!display || !mode_idx)
  5546. return;
  5547. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  5548. if (!dyn_clk_caps->dyn_clk_support)
  5549. return;
  5550. cfg = &(display->panel->host_config);
  5551. bpp = dsi_pixel_format_to_bpp(cfg->dst_format);
  5552. if (cfg->data_lanes & DSI_DATA_LANE_0)
  5553. lanes++;
  5554. if (cfg->data_lanes & DSI_DATA_LANE_1)
  5555. lanes++;
  5556. if (cfg->data_lanes & DSI_DATA_LANE_2)
  5557. lanes++;
  5558. if (cfg->data_lanes & DSI_DATA_LANE_3)
  5559. lanes++;
  5560. total_modes = display->panel->num_display_modes;
  5561. for (i = start; i < end; i++) {
  5562. src = &display->modes[i];
  5563. if (!src)
  5564. return;
  5565. /*
  5566. * TODO: currently setting the first bit rate in
  5567. * the list as preferred rate. But ideally should
  5568. * be based on user or device tree preferrence.
  5569. */
  5570. src->timing.clk_rate_hz = dyn_clk_caps->bit_clk_list[0];
  5571. dsi_display_adjust_mode_timing(display, src, lanes, bpp);
  5572. src->pixel_clk_khz =
  5573. div_u64(src->timing.clk_rate_hz * lanes, bpp);
  5574. src->pixel_clk_khz /= 1000;
  5575. src->pixel_clk_khz *= display->ctrl_count;
  5576. }
  5577. for (i = 1; i < dyn_clk_caps->bit_clk_list_len; i++) {
  5578. if (*mode_idx >= total_modes)
  5579. return;
  5580. for (j = start; j < end; j++) {
  5581. src = &display->modes[j];
  5582. dst = &display->modes[*mode_idx];
  5583. if (!src || !dst) {
  5584. DSI_ERR("invalid mode index\n");
  5585. return;
  5586. }
  5587. memcpy(dst, src, sizeof(struct dsi_display_mode));
  5588. size = sizeof(struct dsi_display_mode_priv_info);
  5589. priv_info = kzalloc(size, GFP_KERNEL);
  5590. dst->priv_info = priv_info;
  5591. if (dst->priv_info)
  5592. memcpy(dst->priv_info, src->priv_info, size);
  5593. dst->timing.clk_rate_hz = dyn_clk_caps->bit_clk_list[i];
  5594. dsi_display_adjust_mode_timing(display, dst, lanes,
  5595. bpp);
  5596. dst->panel_mode_caps = DSI_OP_VIDEO_MODE;
  5597. dst->pixel_clk_khz =
  5598. div_u64(dst->timing.clk_rate_hz * lanes, bpp);
  5599. dst->pixel_clk_khz /= 1000;
  5600. dst->pixel_clk_khz *= display->ctrl_count;
  5601. (*mode_idx)++;
  5602. }
  5603. }
  5604. }
  5605. void dsi_display_put_mode(struct dsi_display *display,
  5606. struct dsi_display_mode *mode)
  5607. {
  5608. dsi_panel_put_mode(mode);
  5609. }
  5610. int dsi_display_get_modes(struct dsi_display *display,
  5611. struct dsi_display_mode **out_modes)
  5612. {
  5613. struct dsi_dfps_capabilities dfps_caps;
  5614. struct dsi_display_ctrl *ctrl;
  5615. struct dsi_host_common_cfg *host = &display->panel->host_config;
  5616. bool is_split_link, support_cmd_mode, support_video_mode;
  5617. u32 num_dfps_rates, timing_mode_count, display_mode_count;
  5618. u32 sublinks_count, mode_idx, array_idx = 0;
  5619. struct dsi_dyn_clk_caps *dyn_clk_caps;
  5620. int i, start, end, rc = -EINVAL;
  5621. if (!display || !out_modes) {
  5622. DSI_ERR("Invalid params\n");
  5623. return -EINVAL;
  5624. }
  5625. *out_modes = NULL;
  5626. ctrl = &display->ctrl[0];
  5627. mutex_lock(&display->display_lock);
  5628. if (display->modes)
  5629. goto exit;
  5630. display_mode_count = display->panel->num_display_modes;
  5631. display->modes = kcalloc(display_mode_count, sizeof(*display->modes),
  5632. GFP_KERNEL);
  5633. if (!display->modes) {
  5634. rc = -ENOMEM;
  5635. goto error;
  5636. }
  5637. rc = dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
  5638. if (rc) {
  5639. DSI_ERR("[%s] failed to get dfps caps from panel\n",
  5640. display->name);
  5641. goto error;
  5642. }
  5643. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  5644. timing_mode_count = display->panel->num_timing_nodes;
  5645. /* Validate command line timing */
  5646. if ((display->cmdline_timing != NO_OVERRIDE) &&
  5647. (display->cmdline_timing >= timing_mode_count))
  5648. display->cmdline_timing = NO_OVERRIDE;
  5649. for (mode_idx = 0; mode_idx < timing_mode_count; mode_idx++) {
  5650. struct dsi_display_mode display_mode;
  5651. int topology_override = NO_OVERRIDE;
  5652. bool is_preferred = false;
  5653. u32 frame_threshold_us = ctrl->ctrl->frame_threshold_time_us;
  5654. if (display->cmdline_timing == mode_idx) {
  5655. topology_override = display->cmdline_topology;
  5656. is_preferred = true;
  5657. }
  5658. memset(&display_mode, 0, sizeof(display_mode));
  5659. rc = dsi_panel_get_mode(display->panel, mode_idx,
  5660. &display_mode,
  5661. topology_override);
  5662. if (rc) {
  5663. DSI_ERR("[%s] failed to get mode idx %d from panel\n",
  5664. display->name, mode_idx);
  5665. goto error;
  5666. }
  5667. support_cmd_mode = display_mode.panel_mode_caps & DSI_OP_CMD_MODE;
  5668. support_video_mode = display_mode.panel_mode_caps & DSI_OP_VIDEO_MODE;
  5669. /* Setup widebus support */
  5670. display_mode.priv_info->widebus_support =
  5671. ctrl->ctrl->hw.widebus_support;
  5672. num_dfps_rates = ((!dfps_caps.dfps_support ||
  5673. !support_video_mode) ? 1 : dfps_caps.dfps_list_len);
  5674. /* Calculate dsi frame transfer time */
  5675. if (support_cmd_mode) {
  5676. dsi_panel_calc_dsi_transfer_time(
  5677. &display->panel->host_config,
  5678. &display_mode, frame_threshold_us);
  5679. display_mode.priv_info->dsi_transfer_time_us =
  5680. display_mode.timing.dsi_transfer_time_us;
  5681. display_mode.priv_info->min_dsi_clk_hz =
  5682. display_mode.timing.min_dsi_clk_hz;
  5683. display_mode.priv_info->mdp_transfer_time_us =
  5684. display_mode.timing.mdp_transfer_time_us;
  5685. }
  5686. is_split_link = host->split_link.split_link_enabled;
  5687. sublinks_count = host->split_link.num_sublinks;
  5688. if (is_split_link && sublinks_count > 1) {
  5689. display_mode.timing.h_active *= sublinks_count;
  5690. display_mode.timing.h_front_porch *= sublinks_count;
  5691. display_mode.timing.h_sync_width *= sublinks_count;
  5692. display_mode.timing.h_back_porch *= sublinks_count;
  5693. display_mode.timing.h_skew *= sublinks_count;
  5694. display_mode.pixel_clk_khz *= sublinks_count;
  5695. } else {
  5696. display_mode.timing.h_active *= display->ctrl_count;
  5697. display_mode.timing.h_front_porch *=
  5698. display->ctrl_count;
  5699. display_mode.timing.h_sync_width *=
  5700. display->ctrl_count;
  5701. display_mode.timing.h_back_porch *=
  5702. display->ctrl_count;
  5703. display_mode.timing.h_skew *= display->ctrl_count;
  5704. display_mode.pixel_clk_khz *= display->ctrl_count;
  5705. }
  5706. start = array_idx;
  5707. for (i = 0; i < num_dfps_rates; i++) {
  5708. struct dsi_display_mode *sub_mode =
  5709. &display->modes[array_idx];
  5710. u32 curr_refresh_rate;
  5711. if (!sub_mode) {
  5712. DSI_ERR("invalid mode data\n");
  5713. rc = -EFAULT;
  5714. goto error;
  5715. }
  5716. memcpy(sub_mode, &display_mode, sizeof(display_mode));
  5717. array_idx++;
  5718. if (!dfps_caps.dfps_support || !support_video_mode)
  5719. continue;
  5720. curr_refresh_rate = sub_mode->timing.refresh_rate;
  5721. sub_mode->timing.refresh_rate = dfps_caps.dfps_list[i];
  5722. dsi_display_get_dfps_timing(display, sub_mode,
  5723. curr_refresh_rate);
  5724. sub_mode->panel_mode_caps = DSI_OP_VIDEO_MODE;
  5725. }
  5726. end = array_idx;
  5727. _dsi_display_populate_bit_clks(display, start, end, &array_idx);
  5728. if (is_preferred) {
  5729. /* Set first timing sub mode as preferred mode */
  5730. display->modes[start].is_preferred = true;
  5731. }
  5732. }
  5733. exit:
  5734. *out_modes = display->modes;
  5735. rc = 0;
  5736. error:
  5737. if (rc)
  5738. kfree(display->modes);
  5739. mutex_unlock(&display->display_lock);
  5740. return rc;
  5741. }
  5742. int dsi_display_get_panel_vfp(void *dsi_display,
  5743. int h_active, int v_active)
  5744. {
  5745. int i, rc = 0;
  5746. u32 count, refresh_rate = 0;
  5747. struct dsi_dfps_capabilities dfps_caps;
  5748. struct dsi_display *display = (struct dsi_display *)dsi_display;
  5749. struct dsi_host_common_cfg *host;
  5750. if (!display || !display->panel)
  5751. return -EINVAL;
  5752. mutex_lock(&display->display_lock);
  5753. count = display->panel->num_display_modes;
  5754. if (display->panel->cur_mode)
  5755. refresh_rate = display->panel->cur_mode->timing.refresh_rate;
  5756. dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
  5757. if (dfps_caps.dfps_support)
  5758. refresh_rate = dfps_caps.max_refresh_rate;
  5759. if (!refresh_rate) {
  5760. mutex_unlock(&display->display_lock);
  5761. DSI_ERR("Null Refresh Rate\n");
  5762. return -EINVAL;
  5763. }
  5764. host = &display->panel->host_config;
  5765. if (host->split_link.split_link_enabled)
  5766. h_active *= host->split_link.num_sublinks;
  5767. else
  5768. h_active *= display->ctrl_count;
  5769. for (i = 0; i < count; i++) {
  5770. struct dsi_display_mode *m = &display->modes[i];
  5771. if (m && v_active == m->timing.v_active &&
  5772. h_active == m->timing.h_active &&
  5773. refresh_rate == m->timing.refresh_rate) {
  5774. rc = m->timing.v_front_porch;
  5775. break;
  5776. }
  5777. }
  5778. mutex_unlock(&display->display_lock);
  5779. return rc;
  5780. }
  5781. int dsi_display_get_default_lms(void *dsi_display, u32 *num_lm)
  5782. {
  5783. struct dsi_display *display = (struct dsi_display *)dsi_display;
  5784. u32 count, i;
  5785. int rc = 0;
  5786. *num_lm = 0;
  5787. mutex_lock(&display->display_lock);
  5788. count = display->panel->num_display_modes;
  5789. mutex_unlock(&display->display_lock);
  5790. if (!display->modes) {
  5791. struct dsi_display_mode *m;
  5792. rc = dsi_display_get_modes(display, &m);
  5793. if (rc)
  5794. return rc;
  5795. }
  5796. mutex_lock(&display->display_lock);
  5797. for (i = 0; i < count; i++) {
  5798. struct dsi_display_mode *m = &display->modes[i];
  5799. *num_lm = max(m->priv_info->topology.num_lm, *num_lm);
  5800. }
  5801. mutex_unlock(&display->display_lock);
  5802. return rc;
  5803. }
  5804. int dsi_display_get_qsync_min_fps(void *display_dsi, u32 mode_fps)
  5805. {
  5806. struct dsi_display *display = (struct dsi_display *)display_dsi;
  5807. struct dsi_panel *panel;
  5808. u32 i;
  5809. if (display == NULL || display->panel == NULL)
  5810. return -EINVAL;
  5811. panel = display->panel;
  5812. for (i = 0; i < panel->dfps_caps.dfps_list_len; i++) {
  5813. if (panel->dfps_caps.dfps_list[i] == mode_fps)
  5814. return panel->qsync_caps.qsync_min_fps_list[i];
  5815. }
  5816. SDE_EVT32(mode_fps);
  5817. DSI_DEBUG("Invalid mode_fps %d\n", mode_fps);
  5818. return -EINVAL;
  5819. }
  5820. int dsi_display_find_mode(struct dsi_display *display,
  5821. const struct dsi_display_mode *cmp,
  5822. struct dsi_display_mode **out_mode)
  5823. {
  5824. u32 count, i;
  5825. int rc;
  5826. if (!display || !out_mode)
  5827. return -EINVAL;
  5828. *out_mode = NULL;
  5829. mutex_lock(&display->display_lock);
  5830. count = display->panel->num_display_modes;
  5831. mutex_unlock(&display->display_lock);
  5832. if (!display->modes) {
  5833. struct dsi_display_mode *m;
  5834. rc = dsi_display_get_modes(display, &m);
  5835. if (rc)
  5836. return rc;
  5837. }
  5838. mutex_lock(&display->display_lock);
  5839. for (i = 0; i < count; i++) {
  5840. struct dsi_display_mode *m = &display->modes[i];
  5841. if (cmp->timing.v_active == m->timing.v_active &&
  5842. cmp->timing.h_active == m->timing.h_active &&
  5843. cmp->timing.refresh_rate == m->timing.refresh_rate) {
  5844. *out_mode = m;
  5845. rc = 0;
  5846. break;
  5847. }
  5848. }
  5849. mutex_unlock(&display->display_lock);
  5850. if (!*out_mode) {
  5851. DSI_ERR("[%s] failed to find mode for v_active %u h_active %u fps %u pclk %u\n",
  5852. display->name, cmp->timing.v_active,
  5853. cmp->timing.h_active, cmp->timing.refresh_rate,
  5854. cmp->pixel_clk_khz);
  5855. rc = -ENOENT;
  5856. }
  5857. return rc;
  5858. }
  5859. static inline bool dsi_display_mode_switch_dfps(struct dsi_display_mode *cur,
  5860. struct dsi_display_mode *adj)
  5861. {
  5862. /*
  5863. * If there is a change in the hfp or vfp of the current and adjoining
  5864. * mode,then either it is a dfps mode switch or dynamic clk change with
  5865. * constant fps.
  5866. */
  5867. if ((cur->timing.h_front_porch != adj->timing.h_front_porch) ||
  5868. (cur->timing.v_front_porch != adj->timing.v_front_porch))
  5869. return true;
  5870. else
  5871. return false;
  5872. }
  5873. /**
  5874. * dsi_display_validate_mode_change() - Validate mode change case.
  5875. * @display: DSI display handle.
  5876. * @cur_mode: Current mode.
  5877. * @adj_mode: Mode to be set.
  5878. * MSM_MODE_FLAG_SEAMLESS_VRR flag is set if there
  5879. * is change in hfp or vfp but vactive and hactive are same.
  5880. * DSI_MODE_FLAG_DYN_CLK flag is set if there
  5881. * is change in clk but vactive and hactive are same.
  5882. * Return: error code.
  5883. */
  5884. int dsi_display_validate_mode_change(struct dsi_display *display,
  5885. struct dsi_display_mode *cur_mode,
  5886. struct dsi_display_mode *adj_mode)
  5887. {
  5888. int rc = 0;
  5889. struct dsi_dfps_capabilities dfps_caps;
  5890. struct dsi_dyn_clk_caps *dyn_clk_caps;
  5891. struct sde_connector *sde_conn;
  5892. if (!display || !adj_mode || !display->drm_conn) {
  5893. DSI_ERR("Invalid params\n");
  5894. return -EINVAL;
  5895. }
  5896. if (!display->panel || !display->panel->cur_mode) {
  5897. DSI_DEBUG("Current panel mode not set\n");
  5898. return rc;
  5899. }
  5900. if ((cur_mode->timing.v_active != adj_mode->timing.v_active) ||
  5901. (cur_mode->timing.h_active != adj_mode->timing.h_active)) {
  5902. DSI_DEBUG("Avoid VRR and POMS when resolution is changed\n");
  5903. return rc;
  5904. }
  5905. sde_conn = to_sde_connector(display->drm_conn);
  5906. mutex_lock(&display->display_lock);
  5907. if (sde_conn->expected_panel_mode == MSM_DISPLAY_VIDEO_MODE &&
  5908. display->config.panel_mode == DSI_OP_CMD_MODE) {
  5909. adj_mode->dsi_mode_flags |= DSI_MODE_FLAG_POMS_TO_VID;
  5910. DSI_DEBUG("Panel operating mode change to video detected\n");
  5911. } else if (sde_conn->expected_panel_mode == MSM_DISPLAY_CMD_MODE &&
  5912. display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  5913. adj_mode->dsi_mode_flags |= DSI_MODE_FLAG_POMS_TO_CMD;
  5914. DSI_DEBUG("Panel operating mode change to command detected\n");
  5915. } else {
  5916. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  5917. /* dfps and dynamic clock with const fps use case */
  5918. if (dsi_display_mode_switch_dfps(cur_mode, adj_mode)) {
  5919. dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
  5920. if (dfps_caps.dfps_support ||
  5921. dyn_clk_caps->maintain_const_fps) {
  5922. DSI_DEBUG("Mode switch is seamless variable refresh\n");
  5923. adj_mode->dsi_mode_flags |= DSI_MODE_FLAG_VRR;
  5924. SDE_EVT32(SDE_EVTLOG_FUNC_CASE1,
  5925. cur_mode->timing.refresh_rate,
  5926. adj_mode->timing.refresh_rate,
  5927. cur_mode->timing.h_front_porch,
  5928. adj_mode->timing.h_front_porch,
  5929. cur_mode->timing.v_front_porch,
  5930. adj_mode->timing.v_front_porch);
  5931. }
  5932. }
  5933. /* dynamic clk change use case */
  5934. if (cur_mode->pixel_clk_khz != adj_mode->pixel_clk_khz) {
  5935. if (dyn_clk_caps->dyn_clk_support) {
  5936. DSI_DEBUG("dynamic clk change detected\n");
  5937. if ((adj_mode->dsi_mode_flags &
  5938. DSI_MODE_FLAG_VRR) &&
  5939. (!dyn_clk_caps->maintain_const_fps)) {
  5940. DSI_ERR("dfps and dyn clk not supported in same commit\n");
  5941. rc = -ENOTSUPP;
  5942. goto error;
  5943. }
  5944. adj_mode->dsi_mode_flags |=
  5945. DSI_MODE_FLAG_DYN_CLK;
  5946. SDE_EVT32(SDE_EVTLOG_FUNC_CASE2,
  5947. cur_mode->pixel_clk_khz,
  5948. adj_mode->pixel_clk_khz);
  5949. }
  5950. }
  5951. }
  5952. error:
  5953. mutex_unlock(&display->display_lock);
  5954. return rc;
  5955. }
  5956. int dsi_display_validate_mode(struct dsi_display *display,
  5957. struct dsi_display_mode *mode,
  5958. u32 flags)
  5959. {
  5960. int rc = 0;
  5961. int i;
  5962. struct dsi_display_ctrl *ctrl;
  5963. struct dsi_display_mode adj_mode;
  5964. if (!display || !mode) {
  5965. DSI_ERR("Invalid params\n");
  5966. return -EINVAL;
  5967. }
  5968. mutex_lock(&display->display_lock);
  5969. adj_mode = *mode;
  5970. adjust_timing_by_ctrl_count(display, &adj_mode);
  5971. rc = dsi_panel_validate_mode(display->panel, &adj_mode);
  5972. if (rc) {
  5973. DSI_ERR("[%s] panel mode validation failed, rc=%d\n",
  5974. display->name, rc);
  5975. goto error;
  5976. }
  5977. display_for_each_ctrl(i, display) {
  5978. ctrl = &display->ctrl[i];
  5979. rc = dsi_ctrl_validate_timing(ctrl->ctrl, &adj_mode.timing);
  5980. if (rc) {
  5981. DSI_ERR("[%s] ctrl mode validation failed, rc=%d\n",
  5982. display->name, rc);
  5983. goto error;
  5984. }
  5985. rc = dsi_phy_validate_mode(ctrl->phy, &adj_mode.timing);
  5986. if (rc) {
  5987. DSI_ERR("[%s] phy mode validation failed, rc=%d\n",
  5988. display->name, rc);
  5989. goto error;
  5990. }
  5991. }
  5992. if ((flags & DSI_VALIDATE_FLAG_ALLOW_ADJUST) &&
  5993. (mode->dsi_mode_flags & DSI_MODE_FLAG_SEAMLESS)) {
  5994. rc = dsi_display_validate_mode_seamless(display, mode);
  5995. if (rc) {
  5996. DSI_ERR("[%s] seamless not possible rc=%d\n",
  5997. display->name, rc);
  5998. goto error;
  5999. }
  6000. }
  6001. error:
  6002. mutex_unlock(&display->display_lock);
  6003. return rc;
  6004. }
  6005. int dsi_display_set_mode(struct dsi_display *display,
  6006. struct dsi_display_mode *mode,
  6007. u32 flags)
  6008. {
  6009. int rc = 0;
  6010. struct dsi_display_mode adj_mode;
  6011. struct dsi_mode_info timing;
  6012. if (!display || !mode || !display->panel) {
  6013. DSI_ERR("Invalid params\n");
  6014. return -EINVAL;
  6015. }
  6016. mutex_lock(&display->display_lock);
  6017. adj_mode = *mode;
  6018. timing = adj_mode.timing;
  6019. adjust_timing_by_ctrl_count(display, &adj_mode);
  6020. if (!display->panel->cur_mode) {
  6021. display->panel->cur_mode =
  6022. kzalloc(sizeof(struct dsi_display_mode), GFP_KERNEL);
  6023. if (!display->panel->cur_mode) {
  6024. rc = -ENOMEM;
  6025. goto error;
  6026. }
  6027. }
  6028. /*For dynamic DSI setting, use specified clock rate */
  6029. if (display->cached_clk_rate > 0)
  6030. adj_mode.priv_info->clk_rate_hz = display->cached_clk_rate;
  6031. rc = dsi_display_validate_mode_set(display, &adj_mode, flags);
  6032. if (rc) {
  6033. DSI_ERR("[%s] mode cannot be set\n", display->name);
  6034. goto error;
  6035. }
  6036. rc = dsi_display_set_mode_sub(display, &adj_mode, flags);
  6037. if (rc) {
  6038. DSI_ERR("[%s] failed to set mode\n", display->name);
  6039. goto error;
  6040. }
  6041. DSI_INFO("mdp_transfer_time=%d, hactive=%d, vactive=%d, fps=%d\n",
  6042. adj_mode.priv_info->mdp_transfer_time_us,
  6043. timing.h_active, timing.v_active, timing.refresh_rate);
  6044. SDE_EVT32(adj_mode.priv_info->mdp_transfer_time_us,
  6045. timing.h_active, timing.v_active, timing.refresh_rate);
  6046. memcpy(display->panel->cur_mode, &adj_mode, sizeof(adj_mode));
  6047. error:
  6048. mutex_unlock(&display->display_lock);
  6049. return rc;
  6050. }
  6051. int dsi_display_set_tpg_state(struct dsi_display *display, bool enable)
  6052. {
  6053. int rc = 0;
  6054. int i;
  6055. struct dsi_display_ctrl *ctrl;
  6056. if (!display) {
  6057. DSI_ERR("Invalid params\n");
  6058. return -EINVAL;
  6059. }
  6060. display_for_each_ctrl(i, display) {
  6061. ctrl = &display->ctrl[i];
  6062. rc = dsi_ctrl_set_tpg_state(ctrl->ctrl, enable);
  6063. if (rc) {
  6064. DSI_ERR("[%s] failed to set tpg state for host_%d\n",
  6065. display->name, i);
  6066. goto error;
  6067. }
  6068. }
  6069. display->is_tpg_enabled = enable;
  6070. error:
  6071. return rc;
  6072. }
  6073. static int dsi_display_pre_switch(struct dsi_display *display)
  6074. {
  6075. int rc = 0;
  6076. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  6077. DSI_CORE_CLK, DSI_CLK_ON);
  6078. if (rc) {
  6079. DSI_ERR("[%s] failed to enable DSI core clocks, rc=%d\n",
  6080. display->name, rc);
  6081. goto error;
  6082. }
  6083. rc = dsi_display_ctrl_update(display);
  6084. if (rc) {
  6085. DSI_ERR("[%s] failed to update DSI controller, rc=%d\n",
  6086. display->name, rc);
  6087. goto error_ctrl_clk_off;
  6088. }
  6089. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  6090. DSI_LINK_CLK, DSI_CLK_ON);
  6091. if (rc) {
  6092. DSI_ERR("[%s] failed to enable DSI link clocks, rc=%d\n",
  6093. display->name, rc);
  6094. goto error_ctrl_deinit;
  6095. }
  6096. goto error;
  6097. error_ctrl_deinit:
  6098. (void)dsi_display_ctrl_deinit(display);
  6099. error_ctrl_clk_off:
  6100. (void)dsi_display_clk_ctrl(display->dsi_clk_handle,
  6101. DSI_CORE_CLK, DSI_CLK_OFF);
  6102. error:
  6103. return rc;
  6104. }
  6105. static bool _dsi_display_validate_host_state(struct dsi_display *display)
  6106. {
  6107. int i;
  6108. struct dsi_display_ctrl *ctrl;
  6109. display_for_each_ctrl(i, display) {
  6110. ctrl = &display->ctrl[i];
  6111. if (!ctrl->ctrl)
  6112. continue;
  6113. if (!dsi_ctrl_validate_host_state(ctrl->ctrl))
  6114. return false;
  6115. }
  6116. return true;
  6117. }
  6118. static void dsi_display_handle_fifo_underflow(struct work_struct *work)
  6119. {
  6120. struct dsi_display *display = NULL;
  6121. display = container_of(work, struct dsi_display, fifo_underflow_work);
  6122. if (!display || !display->panel ||
  6123. atomic_read(&display->panel->esd_recovery_pending)) {
  6124. DSI_DEBUG("Invalid recovery use case\n");
  6125. return;
  6126. }
  6127. mutex_lock(&display->display_lock);
  6128. if (!_dsi_display_validate_host_state(display)) {
  6129. mutex_unlock(&display->display_lock);
  6130. return;
  6131. }
  6132. DSI_INFO("handle DSI FIFO underflow error\n");
  6133. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6134. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6135. DSI_ALL_CLKS, DSI_CLK_ON);
  6136. dsi_display_soft_reset(display);
  6137. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6138. DSI_ALL_CLKS, DSI_CLK_OFF);
  6139. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  6140. mutex_unlock(&display->display_lock);
  6141. }
  6142. static void dsi_display_handle_fifo_overflow(struct work_struct *work)
  6143. {
  6144. struct dsi_display *display = NULL;
  6145. struct dsi_display_ctrl *ctrl;
  6146. int i, rc;
  6147. int mask = BIT(20); /* clock lane */
  6148. int (*cb_func)(void *event_usr_ptr,
  6149. uint32_t event_idx, uint32_t instance_idx,
  6150. uint32_t data0, uint32_t data1,
  6151. uint32_t data2, uint32_t data3);
  6152. void *data;
  6153. u32 version = 0;
  6154. display = container_of(work, struct dsi_display, fifo_overflow_work);
  6155. if (!display || !display->panel ||
  6156. (display->panel->panel_mode != DSI_OP_VIDEO_MODE) ||
  6157. atomic_read(&display->panel->esd_recovery_pending)) {
  6158. DSI_DEBUG("Invalid recovery use case\n");
  6159. return;
  6160. }
  6161. mutex_lock(&display->display_lock);
  6162. if (!_dsi_display_validate_host_state(display)) {
  6163. mutex_unlock(&display->display_lock);
  6164. return;
  6165. }
  6166. DSI_INFO("handle DSI FIFO overflow error\n");
  6167. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6168. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6169. DSI_ALL_CLKS, DSI_CLK_ON);
  6170. /*
  6171. * below recovery sequence is not applicable to
  6172. * hw version 2.0.0, 2.1.0 and 2.2.0, so return early.
  6173. */
  6174. ctrl = &display->ctrl[display->clk_master_idx];
  6175. version = dsi_ctrl_get_hw_version(ctrl->ctrl);
  6176. if (!version || (version < 0x20020001))
  6177. goto end;
  6178. /* reset ctrl and lanes */
  6179. display_for_each_ctrl(i, display) {
  6180. ctrl = &display->ctrl[i];
  6181. rc = dsi_ctrl_reset(ctrl->ctrl, mask);
  6182. rc = dsi_phy_lane_reset(ctrl->phy);
  6183. }
  6184. /* wait for display line count to be in active area */
  6185. ctrl = &display->ctrl[display->clk_master_idx];
  6186. if (ctrl->ctrl->recovery_cb.event_cb) {
  6187. cb_func = ctrl->ctrl->recovery_cb.event_cb;
  6188. data = ctrl->ctrl->recovery_cb.event_usr_ptr;
  6189. rc = cb_func(data, SDE_CONN_EVENT_VID_FIFO_OVERFLOW,
  6190. display->clk_master_idx, 0, 0, 0, 0);
  6191. if (rc < 0) {
  6192. DSI_DEBUG("sde callback failed\n");
  6193. goto end;
  6194. }
  6195. }
  6196. /* Enable Video mode for DSI controller */
  6197. display_for_each_ctrl(i, display) {
  6198. ctrl = &display->ctrl[i];
  6199. dsi_ctrl_vid_engine_en(ctrl->ctrl, true);
  6200. }
  6201. /*
  6202. * Add sufficient delay to make sure
  6203. * pixel transmission has started
  6204. */
  6205. udelay(200);
  6206. end:
  6207. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6208. DSI_ALL_CLKS, DSI_CLK_OFF);
  6209. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  6210. mutex_unlock(&display->display_lock);
  6211. }
  6212. static void dsi_display_handle_lp_rx_timeout(struct work_struct *work)
  6213. {
  6214. struct dsi_display *display = NULL;
  6215. struct dsi_display_ctrl *ctrl;
  6216. int i, rc;
  6217. int mask = (BIT(20) | (0xF << 16)); /* clock lane and 4 data lane */
  6218. int (*cb_func)(void *event_usr_ptr,
  6219. uint32_t event_idx, uint32_t instance_idx,
  6220. uint32_t data0, uint32_t data1,
  6221. uint32_t data2, uint32_t data3);
  6222. void *data;
  6223. u32 version = 0;
  6224. display = container_of(work, struct dsi_display, lp_rx_timeout_work);
  6225. if (!display || !display->panel ||
  6226. (display->panel->panel_mode != DSI_OP_VIDEO_MODE) ||
  6227. atomic_read(&display->panel->esd_recovery_pending)) {
  6228. DSI_DEBUG("Invalid recovery use case\n");
  6229. return;
  6230. }
  6231. mutex_lock(&display->display_lock);
  6232. if (!_dsi_display_validate_host_state(display)) {
  6233. mutex_unlock(&display->display_lock);
  6234. return;
  6235. }
  6236. DSI_INFO("handle DSI LP RX Timeout error\n");
  6237. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6238. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6239. DSI_ALL_CLKS, DSI_CLK_ON);
  6240. /*
  6241. * below recovery sequence is not applicable to
  6242. * hw version 2.0.0, 2.1.0 and 2.2.0, so return early.
  6243. */
  6244. ctrl = &display->ctrl[display->clk_master_idx];
  6245. version = dsi_ctrl_get_hw_version(ctrl->ctrl);
  6246. if (!version || (version < 0x20020001))
  6247. goto end;
  6248. /* reset ctrl and lanes */
  6249. display_for_each_ctrl(i, display) {
  6250. ctrl = &display->ctrl[i];
  6251. rc = dsi_ctrl_reset(ctrl->ctrl, mask);
  6252. rc = dsi_phy_lane_reset(ctrl->phy);
  6253. }
  6254. ctrl = &display->ctrl[display->clk_master_idx];
  6255. if (ctrl->ctrl->recovery_cb.event_cb) {
  6256. cb_func = ctrl->ctrl->recovery_cb.event_cb;
  6257. data = ctrl->ctrl->recovery_cb.event_usr_ptr;
  6258. rc = cb_func(data, SDE_CONN_EVENT_VID_FIFO_OVERFLOW,
  6259. display->clk_master_idx, 0, 0, 0, 0);
  6260. if (rc < 0) {
  6261. DSI_DEBUG("Target is in suspend/shutdown\n");
  6262. goto end;
  6263. }
  6264. }
  6265. /* Enable Video mode for DSI controller */
  6266. display_for_each_ctrl(i, display) {
  6267. ctrl = &display->ctrl[i];
  6268. dsi_ctrl_vid_engine_en(ctrl->ctrl, true);
  6269. }
  6270. /*
  6271. * Add sufficient delay to make sure
  6272. * pixel transmission as started
  6273. */
  6274. udelay(200);
  6275. end:
  6276. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6277. DSI_ALL_CLKS, DSI_CLK_OFF);
  6278. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  6279. mutex_unlock(&display->display_lock);
  6280. }
  6281. static int dsi_display_cb_error_handler(void *data,
  6282. uint32_t event_idx, uint32_t instance_idx,
  6283. uint32_t data0, uint32_t data1,
  6284. uint32_t data2, uint32_t data3)
  6285. {
  6286. struct dsi_display *display = data;
  6287. if (!display || !(display->err_workq))
  6288. return -EINVAL;
  6289. switch (event_idx) {
  6290. case DSI_FIFO_UNDERFLOW:
  6291. queue_work(display->err_workq, &display->fifo_underflow_work);
  6292. break;
  6293. case DSI_FIFO_OVERFLOW:
  6294. queue_work(display->err_workq, &display->fifo_overflow_work);
  6295. break;
  6296. case DSI_LP_Rx_TIMEOUT:
  6297. queue_work(display->err_workq, &display->lp_rx_timeout_work);
  6298. break;
  6299. default:
  6300. DSI_WARN("unhandled error interrupt: %d\n", event_idx);
  6301. break;
  6302. }
  6303. return 0;
  6304. }
  6305. static void dsi_display_register_error_handler(struct dsi_display *display)
  6306. {
  6307. int i = 0;
  6308. struct dsi_display_ctrl *ctrl;
  6309. struct dsi_event_cb_info event_info;
  6310. if (!display)
  6311. return;
  6312. display->err_workq = create_singlethread_workqueue("dsi_err_workq");
  6313. if (!display->err_workq) {
  6314. DSI_ERR("failed to create dsi workq!\n");
  6315. return;
  6316. }
  6317. INIT_WORK(&display->fifo_underflow_work,
  6318. dsi_display_handle_fifo_underflow);
  6319. INIT_WORK(&display->fifo_overflow_work,
  6320. dsi_display_handle_fifo_overflow);
  6321. INIT_WORK(&display->lp_rx_timeout_work,
  6322. dsi_display_handle_lp_rx_timeout);
  6323. memset(&event_info, 0, sizeof(event_info));
  6324. event_info.event_cb = dsi_display_cb_error_handler;
  6325. event_info.event_usr_ptr = display;
  6326. display_for_each_ctrl(i, display) {
  6327. ctrl = &display->ctrl[i];
  6328. ctrl->ctrl->irq_info.irq_err_cb = event_info;
  6329. }
  6330. }
  6331. static void dsi_display_unregister_error_handler(struct dsi_display *display)
  6332. {
  6333. int i = 0;
  6334. struct dsi_display_ctrl *ctrl;
  6335. if (!display)
  6336. return;
  6337. display_for_each_ctrl(i, display) {
  6338. ctrl = &display->ctrl[i];
  6339. memset(&ctrl->ctrl->irq_info.irq_err_cb,
  6340. 0, sizeof(struct dsi_event_cb_info));
  6341. }
  6342. if (display->err_workq) {
  6343. destroy_workqueue(display->err_workq);
  6344. display->err_workq = NULL;
  6345. }
  6346. }
  6347. int dsi_display_prepare(struct dsi_display *display)
  6348. {
  6349. int rc = 0;
  6350. struct dsi_display_mode *mode;
  6351. if (!display) {
  6352. DSI_ERR("Invalid params\n");
  6353. return -EINVAL;
  6354. }
  6355. if (!display->panel->cur_mode) {
  6356. DSI_ERR("no valid mode set for the display\n");
  6357. return -EINVAL;
  6358. }
  6359. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6360. mutex_lock(&display->display_lock);
  6361. mode = display->panel->cur_mode;
  6362. dsi_display_set_ctrl_esd_check_flag(display, false);
  6363. /* Set up ctrl isr before enabling core clk */
  6364. if (!display->trusted_vm_env)
  6365. dsi_display_ctrl_isr_configure(display, true);
  6366. if (mode->dsi_mode_flags & DSI_MODE_FLAG_DMS) {
  6367. if (display->is_cont_splash_enabled &&
  6368. display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  6369. DSI_ERR("DMS not supported on first frame\n");
  6370. rc = -EINVAL;
  6371. goto error;
  6372. }
  6373. if (!is_skip_op_required(display)) {
  6374. /* update dsi ctrl for new mode */
  6375. rc = dsi_display_pre_switch(display);
  6376. if (rc)
  6377. DSI_ERR("[%s] panel pre-switch failed, rc=%d\n",
  6378. display->name, rc);
  6379. goto error;
  6380. }
  6381. }
  6382. if (!display->poms_pending &&
  6383. (!is_skip_op_required(display))) {
  6384. /*
  6385. * For continuous splash/trusted vm, we skip panel
  6386. * pre prepare since the regulator vote is already
  6387. * taken care in splash resource init
  6388. */
  6389. rc = dsi_panel_pre_prepare(display->panel);
  6390. if (rc) {
  6391. DSI_ERR("[%s] panel pre-prepare failed, rc=%d\n",
  6392. display->name, rc);
  6393. goto error;
  6394. }
  6395. }
  6396. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  6397. DSI_CORE_CLK, DSI_CLK_ON);
  6398. if (rc) {
  6399. DSI_ERR("[%s] failed to enable DSI core clocks, rc=%d\n",
  6400. display->name, rc);
  6401. goto error_panel_post_unprep;
  6402. }
  6403. /*
  6404. * If ULPS during suspend feature is enabled, then DSI PHY was
  6405. * left on during suspend. In this case, we do not need to reset/init
  6406. * PHY. This would have already been done when the CORE clocks are
  6407. * turned on. However, if cont splash is disabled, the first time DSI
  6408. * is powered on, phy init needs to be done unconditionally.
  6409. */
  6410. if (!display->panel->ulps_suspend_enabled || !display->ulps_enabled) {
  6411. rc = dsi_display_phy_sw_reset(display);
  6412. if (rc) {
  6413. DSI_ERR("[%s] failed to reset phy, rc=%d\n",
  6414. display->name, rc);
  6415. goto error_ctrl_clk_off;
  6416. }
  6417. rc = dsi_display_phy_enable(display);
  6418. if (rc) {
  6419. DSI_ERR("[%s] failed to enable DSI PHY, rc=%d\n",
  6420. display->name, rc);
  6421. goto error_ctrl_clk_off;
  6422. }
  6423. }
  6424. rc = dsi_display_ctrl_init(display);
  6425. if (rc) {
  6426. DSI_ERR("[%s] failed to setup DSI controller, rc=%d\n",
  6427. display->name, rc);
  6428. goto error_phy_disable;
  6429. }
  6430. /* Set up DSI ERROR event callback */
  6431. dsi_display_register_error_handler(display);
  6432. rc = dsi_display_ctrl_host_enable(display);
  6433. if (rc) {
  6434. DSI_ERR("[%s] failed to enable DSI host, rc=%d\n",
  6435. display->name, rc);
  6436. goto error_ctrl_deinit;
  6437. }
  6438. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  6439. DSI_LINK_CLK, DSI_CLK_ON);
  6440. if (rc) {
  6441. DSI_ERR("[%s] failed to enable DSI link clocks, rc=%d\n",
  6442. display->name, rc);
  6443. goto error_host_engine_off;
  6444. }
  6445. if (!is_skip_op_required(display)) {
  6446. /*
  6447. * For continuous splash/trusted vm, skip panel prepare and
  6448. * ctl reset since the pnael and ctrl is already in active
  6449. * state and panel on commands are not needed
  6450. */
  6451. rc = dsi_display_soft_reset(display);
  6452. if (rc) {
  6453. DSI_ERR("[%s] failed soft reset, rc=%d\n",
  6454. display->name, rc);
  6455. goto error_ctrl_link_off;
  6456. }
  6457. if (!display->poms_pending) {
  6458. rc = dsi_panel_prepare(display->panel);
  6459. if (rc) {
  6460. DSI_ERR("[%s] panel prepare failed, rc=%d\n",
  6461. display->name, rc);
  6462. goto error_ctrl_link_off;
  6463. }
  6464. }
  6465. }
  6466. goto error;
  6467. error_ctrl_link_off:
  6468. (void)dsi_display_clk_ctrl(display->dsi_clk_handle,
  6469. DSI_LINK_CLK, DSI_CLK_OFF);
  6470. error_host_engine_off:
  6471. (void)dsi_display_ctrl_host_disable(display);
  6472. error_ctrl_deinit:
  6473. (void)dsi_display_ctrl_deinit(display);
  6474. error_phy_disable:
  6475. (void)dsi_display_phy_disable(display);
  6476. error_ctrl_clk_off:
  6477. (void)dsi_display_clk_ctrl(display->dsi_clk_handle,
  6478. DSI_CORE_CLK, DSI_CLK_OFF);
  6479. error_panel_post_unprep:
  6480. (void)dsi_panel_post_unprepare(display->panel);
  6481. error:
  6482. mutex_unlock(&display->display_lock);
  6483. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  6484. return rc;
  6485. }
  6486. static int dsi_display_calc_ctrl_roi(const struct dsi_display *display,
  6487. const struct dsi_display_ctrl *ctrl,
  6488. const struct msm_roi_list *req_rois,
  6489. struct dsi_rect *out_roi)
  6490. {
  6491. const struct dsi_rect *bounds = &ctrl->ctrl->mode_bounds;
  6492. struct dsi_display_mode *cur_mode;
  6493. struct msm_roi_caps *roi_caps;
  6494. struct dsi_rect req_roi = { 0 };
  6495. int rc = 0;
  6496. cur_mode = display->panel->cur_mode;
  6497. if (!cur_mode)
  6498. return 0;
  6499. roi_caps = &cur_mode->priv_info->roi_caps;
  6500. if (req_rois->num_rects > roi_caps->num_roi) {
  6501. DSI_ERR("request for %d rois greater than max %d\n",
  6502. req_rois->num_rects,
  6503. roi_caps->num_roi);
  6504. rc = -EINVAL;
  6505. goto exit;
  6506. }
  6507. /**
  6508. * if no rois, user wants to reset back to full resolution
  6509. * note: h_active is already divided by ctrl_count
  6510. */
  6511. if (!req_rois->num_rects) {
  6512. *out_roi = *bounds;
  6513. goto exit;
  6514. }
  6515. /* intersect with the bounds */
  6516. req_roi.x = req_rois->roi[0].x1;
  6517. req_roi.y = req_rois->roi[0].y1;
  6518. req_roi.w = req_rois->roi[0].x2 - req_rois->roi[0].x1;
  6519. req_roi.h = req_rois->roi[0].y2 - req_rois->roi[0].y1;
  6520. dsi_rect_intersect(&req_roi, bounds, out_roi);
  6521. exit:
  6522. /* adjust the ctrl origin to be top left within the ctrl */
  6523. out_roi->x = out_roi->x - bounds->x;
  6524. DSI_DEBUG("ctrl%d:%d: req (%d,%d,%d,%d) bnd (%d,%d,%d,%d) out (%d,%d,%d,%d)\n",
  6525. ctrl->dsi_ctrl_idx, ctrl->ctrl->cell_index,
  6526. req_roi.x, req_roi.y, req_roi.w, req_roi.h,
  6527. bounds->x, bounds->y, bounds->w, bounds->h,
  6528. out_roi->x, out_roi->y, out_roi->w, out_roi->h);
  6529. return rc;
  6530. }
  6531. static int dsi_display_qsync(struct dsi_display *display, bool enable)
  6532. {
  6533. int i;
  6534. int rc = 0;
  6535. if (!display->panel->qsync_caps.qsync_min_fps) {
  6536. DSI_ERR("%s:ERROR: qsync set, but no fps\n", __func__);
  6537. return 0;
  6538. }
  6539. mutex_lock(&display->display_lock);
  6540. display_for_each_ctrl(i, display) {
  6541. if (enable) {
  6542. /* send the commands to enable qsync */
  6543. rc = dsi_panel_send_qsync_on_dcs(display->panel, i);
  6544. if (rc) {
  6545. DSI_ERR("fail qsync ON cmds rc:%d\n", rc);
  6546. goto exit;
  6547. }
  6548. } else {
  6549. /* send the commands to enable qsync */
  6550. rc = dsi_panel_send_qsync_off_dcs(display->panel, i);
  6551. if (rc) {
  6552. DSI_ERR("fail qsync OFF cmds rc:%d\n", rc);
  6553. goto exit;
  6554. }
  6555. }
  6556. dsi_ctrl_setup_avr(display->ctrl[i].ctrl, enable);
  6557. }
  6558. exit:
  6559. SDE_EVT32(enable, display->panel->qsync_caps.qsync_min_fps, rc);
  6560. mutex_unlock(&display->display_lock);
  6561. return rc;
  6562. }
  6563. static int dsi_display_set_roi(struct dsi_display *display,
  6564. struct msm_roi_list *rois)
  6565. {
  6566. struct dsi_display_mode *cur_mode;
  6567. struct msm_roi_caps *roi_caps;
  6568. int rc = 0;
  6569. int i;
  6570. if (!display || !rois || !display->panel)
  6571. return -EINVAL;
  6572. cur_mode = display->panel->cur_mode;
  6573. if (!cur_mode)
  6574. return 0;
  6575. roi_caps = &cur_mode->priv_info->roi_caps;
  6576. if (!roi_caps->enabled)
  6577. return 0;
  6578. display_for_each_ctrl(i, display) {
  6579. struct dsi_display_ctrl *ctrl = &display->ctrl[i];
  6580. struct dsi_rect ctrl_roi;
  6581. bool changed = false;
  6582. rc = dsi_display_calc_ctrl_roi(display, ctrl, rois, &ctrl_roi);
  6583. if (rc) {
  6584. DSI_ERR("dsi_display_calc_ctrl_roi failed rc %d\n", rc);
  6585. return rc;
  6586. }
  6587. rc = dsi_ctrl_set_roi(ctrl->ctrl, &ctrl_roi, &changed);
  6588. if (rc) {
  6589. DSI_ERR("dsi_ctrl_set_roi failed rc %d\n", rc);
  6590. return rc;
  6591. }
  6592. if (!changed)
  6593. continue;
  6594. /* send the new roi to the panel via dcs commands */
  6595. rc = dsi_panel_send_roi_dcs(display->panel, i, &ctrl_roi);
  6596. if (rc) {
  6597. DSI_ERR("dsi_panel_set_roi failed rc %d\n", rc);
  6598. return rc;
  6599. }
  6600. /* re-program the ctrl with the timing based on the new roi */
  6601. rc = dsi_ctrl_timing_setup(ctrl->ctrl);
  6602. if (rc) {
  6603. DSI_ERR("dsi_ctrl_setup failed rc %d\n", rc);
  6604. return rc;
  6605. }
  6606. }
  6607. return rc;
  6608. }
  6609. int dsi_display_pre_kickoff(struct drm_connector *connector,
  6610. struct dsi_display *display,
  6611. struct msm_display_kickoff_params *params)
  6612. {
  6613. int rc = 0, ret = 0;
  6614. int i;
  6615. /* check and setup MISR */
  6616. if (display->misr_enable)
  6617. _dsi_display_setup_misr(display);
  6618. /* dynamic DSI clock setting */
  6619. if (atomic_read(&display->clkrate_change_pending)) {
  6620. mutex_lock(&display->display_lock);
  6621. /*
  6622. * acquire panel_lock to make sure no commands are in progress
  6623. */
  6624. dsi_panel_acquire_panel_lock(display->panel);
  6625. /*
  6626. * Wait for DSI command engine not to be busy sending data
  6627. * from display engine.
  6628. * If waiting fails, return "rc" instead of below "ret" so as
  6629. * not to impact DRM commit. The clock updating would be
  6630. * deferred to the next DRM commit.
  6631. */
  6632. display_for_each_ctrl(i, display) {
  6633. struct dsi_ctrl *ctrl = display->ctrl[i].ctrl;
  6634. ret = dsi_ctrl_wait_for_cmd_mode_mdp_idle(ctrl);
  6635. if (ret)
  6636. goto wait_failure;
  6637. }
  6638. /*
  6639. * Don't check the return value so as not to impact DRM commit
  6640. * when error occurs.
  6641. */
  6642. (void)dsi_display_force_update_dsi_clk(display);
  6643. wait_failure:
  6644. /* release panel_lock */
  6645. dsi_panel_release_panel_lock(display->panel);
  6646. mutex_unlock(&display->display_lock);
  6647. }
  6648. if (!ret)
  6649. rc = dsi_display_set_roi(display, params->rois);
  6650. return rc;
  6651. }
  6652. int dsi_display_config_ctrl_for_cont_splash(struct dsi_display *display)
  6653. {
  6654. int rc = 0;
  6655. if (!display || !display->panel) {
  6656. DSI_ERR("Invalid params\n");
  6657. return -EINVAL;
  6658. }
  6659. if (!display->panel->cur_mode) {
  6660. DSI_ERR("no valid mode set for the display\n");
  6661. return -EINVAL;
  6662. }
  6663. if (display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  6664. rc = dsi_display_vid_engine_enable(display);
  6665. if (rc) {
  6666. DSI_ERR("[%s]failed to enable DSI video engine, rc=%d\n",
  6667. display->name, rc);
  6668. goto error_out;
  6669. }
  6670. } else if (display->config.panel_mode == DSI_OP_CMD_MODE) {
  6671. rc = dsi_display_cmd_engine_enable(display);
  6672. if (rc) {
  6673. DSI_ERR("[%s]failed to enable DSI cmd engine, rc=%d\n",
  6674. display->name, rc);
  6675. goto error_out;
  6676. }
  6677. } else {
  6678. DSI_ERR("[%s] Invalid configuration\n", display->name);
  6679. rc = -EINVAL;
  6680. }
  6681. error_out:
  6682. return rc;
  6683. }
  6684. int dsi_display_pre_commit(void *display,
  6685. struct msm_display_conn_params *params)
  6686. {
  6687. bool enable = false;
  6688. int rc = 0;
  6689. if (!display || !params) {
  6690. pr_err("Invalid params\n");
  6691. return -EINVAL;
  6692. }
  6693. if (params->qsync_update) {
  6694. enable = (params->qsync_mode > 0) ? true : false;
  6695. rc = dsi_display_qsync(display, enable);
  6696. if (rc)
  6697. pr_err("%s failed to send qsync commands\n",
  6698. __func__);
  6699. SDE_EVT32(params->qsync_mode, rc);
  6700. }
  6701. return rc;
  6702. }
  6703. static void dsi_display_panel_id_notification(struct dsi_display *display)
  6704. {
  6705. if (display->panel_id != ~0x0 &&
  6706. display->ctrl[0].ctrl->panel_id_cb.event_cb) {
  6707. display->ctrl[0].ctrl->panel_id_cb.event_cb(
  6708. display->ctrl[0].ctrl->panel_id_cb.event_usr_ptr,
  6709. display->ctrl[0].ctrl->panel_id_cb.event_idx,
  6710. 0, ((display->panel_id & 0xffffffff00000000) >> 31),
  6711. (display->panel_id & 0xffffffff), 0, 0);
  6712. }
  6713. }
  6714. int dsi_display_enable(struct dsi_display *display)
  6715. {
  6716. int rc = 0;
  6717. struct dsi_display_mode *mode;
  6718. if (!display || !display->panel) {
  6719. DSI_ERR("Invalid params\n");
  6720. return -EINVAL;
  6721. }
  6722. if (!display->panel->cur_mode) {
  6723. DSI_ERR("no valid mode set for the display\n");
  6724. return -EINVAL;
  6725. }
  6726. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6727. /*
  6728. * Engine states and panel states are populated during splash
  6729. * resource/trusted vm and hence we return early
  6730. */
  6731. if (is_skip_op_required(display)) {
  6732. dsi_display_config_ctrl_for_cont_splash(display);
  6733. rc = dsi_display_splash_res_cleanup(display);
  6734. if (rc) {
  6735. DSI_ERR("Continuous splash res cleanup failed, rc=%d\n",
  6736. rc);
  6737. return -EINVAL;
  6738. }
  6739. display->panel->panel_initialized = true;
  6740. DSI_DEBUG("cont splash enabled, display enable not required\n");
  6741. dsi_display_panel_id_notification(display);
  6742. return 0;
  6743. }
  6744. mutex_lock(&display->display_lock);
  6745. mode = display->panel->cur_mode;
  6746. if (mode->dsi_mode_flags & DSI_MODE_FLAG_DMS) {
  6747. rc = dsi_panel_post_switch(display->panel);
  6748. if (rc) {
  6749. DSI_ERR("[%s] failed to switch DSI panel mode, rc=%d\n",
  6750. display->name, rc);
  6751. goto error;
  6752. }
  6753. } else if (!display->poms_pending) {
  6754. rc = dsi_panel_enable(display->panel);
  6755. if (rc) {
  6756. DSI_ERR("[%s] failed to enable DSI panel, rc=%d\n",
  6757. display->name, rc);
  6758. goto error;
  6759. }
  6760. }
  6761. dsi_display_panel_id_notification(display);
  6762. /* Block sending pps command if modeset is due to fps difference */
  6763. if ((mode->priv_info->dsc_enabled ||
  6764. mode->priv_info->vdc_enabled) &&
  6765. !(mode->dsi_mode_flags & DSI_MODE_FLAG_DMS_FPS)) {
  6766. rc = dsi_panel_update_pps(display->panel);
  6767. if (rc) {
  6768. DSI_ERR("[%s] panel pps cmd update failed, rc=%d\n",
  6769. display->name, rc);
  6770. goto error;
  6771. }
  6772. }
  6773. if (mode->dsi_mode_flags & DSI_MODE_FLAG_DMS) {
  6774. rc = dsi_panel_switch(display->panel);
  6775. if (rc)
  6776. DSI_ERR("[%s] failed to switch DSI panel mode, rc=%d\n",
  6777. display->name, rc);
  6778. goto error;
  6779. }
  6780. if (display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  6781. DSI_DEBUG("%s:enable video timing eng\n", __func__);
  6782. rc = dsi_display_vid_engine_enable(display);
  6783. if (rc) {
  6784. DSI_ERR("[%s]failed to enable DSI video engine, rc=%d\n",
  6785. display->name, rc);
  6786. goto error_disable_panel;
  6787. }
  6788. } else if (display->config.panel_mode == DSI_OP_CMD_MODE) {
  6789. DSI_DEBUG("%s:enable command timing eng\n", __func__);
  6790. rc = dsi_display_cmd_engine_enable(display);
  6791. if (rc) {
  6792. DSI_ERR("[%s]failed to enable DSI cmd engine, rc=%d\n",
  6793. display->name, rc);
  6794. goto error_disable_panel;
  6795. }
  6796. } else {
  6797. DSI_ERR("[%s] Invalid configuration\n", display->name);
  6798. rc = -EINVAL;
  6799. goto error_disable_panel;
  6800. }
  6801. goto error;
  6802. error_disable_panel:
  6803. (void)dsi_panel_disable(display->panel);
  6804. error:
  6805. mutex_unlock(&display->display_lock);
  6806. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  6807. return rc;
  6808. }
  6809. int dsi_display_post_enable(struct dsi_display *display)
  6810. {
  6811. int rc = 0;
  6812. if (!display) {
  6813. DSI_ERR("Invalid params\n");
  6814. return -EINVAL;
  6815. }
  6816. mutex_lock(&display->display_lock);
  6817. if (display->panel->cur_mode->dsi_mode_flags &
  6818. DSI_MODE_FLAG_POMS_TO_CMD) {
  6819. dsi_panel_switch_cmd_mode_in(display->panel);
  6820. } else if (display->panel->cur_mode->dsi_mode_flags &
  6821. DSI_MODE_FLAG_POMS_TO_VID)
  6822. dsi_panel_switch_video_mode_in(display->panel);
  6823. else {
  6824. rc = dsi_panel_post_enable(display->panel);
  6825. if (rc)
  6826. DSI_ERR("[%s] panel post-enable failed, rc=%d\n",
  6827. display->name, rc);
  6828. }
  6829. /* remove the clk vote for CMD mode panels */
  6830. if (display->config.panel_mode == DSI_OP_CMD_MODE)
  6831. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6832. DSI_ALL_CLKS, DSI_CLK_OFF);
  6833. mutex_unlock(&display->display_lock);
  6834. return rc;
  6835. }
  6836. int dsi_display_pre_disable(struct dsi_display *display)
  6837. {
  6838. int rc = 0;
  6839. if (!display) {
  6840. DSI_ERR("Invalid params\n");
  6841. return -EINVAL;
  6842. }
  6843. mutex_lock(&display->display_lock);
  6844. /* enable the clk vote for CMD mode panels */
  6845. if (display->config.panel_mode == DSI_OP_CMD_MODE)
  6846. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6847. DSI_ALL_CLKS, DSI_CLK_ON);
  6848. if (display->poms_pending) {
  6849. if (display->config.panel_mode == DSI_OP_CMD_MODE)
  6850. dsi_panel_switch_cmd_mode_out(display->panel);
  6851. if (display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  6852. /*
  6853. * Add unbalanced vote for clock & cmd engine to enable
  6854. * async trigger of pre video to cmd mode switch.
  6855. */
  6856. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  6857. DSI_ALL_CLKS, DSI_CLK_ON);
  6858. if (rc) {
  6859. DSI_ERR("[%s]failed to enable all clocks,rc=%d",
  6860. display->name, rc);
  6861. goto exit;
  6862. }
  6863. rc = dsi_display_cmd_engine_enable(display);
  6864. if (rc) {
  6865. DSI_ERR("[%s]failed to enable cmd engine,rc=%d",
  6866. display->name, rc);
  6867. goto error_disable_clks;
  6868. }
  6869. dsi_panel_switch_video_mode_out(display->panel);
  6870. }
  6871. } else {
  6872. rc = dsi_panel_pre_disable(display->panel);
  6873. if (rc)
  6874. DSI_ERR("[%s] panel pre-disable failed, rc=%d\n",
  6875. display->name, rc);
  6876. }
  6877. goto exit;
  6878. error_disable_clks:
  6879. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  6880. DSI_ALL_CLKS, DSI_CLK_OFF);
  6881. if (rc)
  6882. DSI_ERR("[%s] failed to disable all DSI clocks, rc=%d\n",
  6883. display->name, rc);
  6884. exit:
  6885. mutex_unlock(&display->display_lock);
  6886. return rc;
  6887. }
  6888. static void dsi_display_handle_poms_te(struct work_struct *work)
  6889. {
  6890. struct dsi_display *display = NULL;
  6891. struct delayed_work *dw = to_delayed_work(work);
  6892. struct mipi_dsi_device *dsi = NULL;
  6893. struct dsi_panel *panel = NULL;
  6894. int rc = 0;
  6895. display = container_of(dw, struct dsi_display, poms_te_work);
  6896. if (!display || !display->panel) {
  6897. DSI_ERR("Invalid params\n");
  6898. return;
  6899. }
  6900. panel = display->panel;
  6901. mutex_lock(&panel->panel_lock);
  6902. if (!dsi_panel_initialized(panel)) {
  6903. rc = -EINVAL;
  6904. goto error;
  6905. }
  6906. dsi = &panel->mipi_device;
  6907. rc = mipi_dsi_dcs_set_tear_off(dsi);
  6908. error:
  6909. mutex_unlock(&panel->panel_lock);
  6910. if (rc < 0)
  6911. DSI_ERR("failed to set tear off\n");
  6912. }
  6913. int dsi_display_disable(struct dsi_display *display)
  6914. {
  6915. int rc = 0;
  6916. if (!display) {
  6917. DSI_ERR("Invalid params\n");
  6918. return -EINVAL;
  6919. }
  6920. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6921. mutex_lock(&display->display_lock);
  6922. /* cancel delayed work */
  6923. if (display->poms_pending &&
  6924. display->panel->poms_align_vsync)
  6925. cancel_delayed_work_sync(&display->poms_te_work);
  6926. rc = dsi_display_wake_up(display);
  6927. if (rc)
  6928. DSI_ERR("[%s] display wake up failed, rc=%d\n",
  6929. display->name, rc);
  6930. if (display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  6931. rc = dsi_display_vid_engine_disable(display);
  6932. if (rc)
  6933. DSI_ERR("[%s]failed to disable DSI vid engine, rc=%d\n",
  6934. display->name, rc);
  6935. } else if (display->config.panel_mode == DSI_OP_CMD_MODE) {
  6936. /**
  6937. * On POMS request , disable panel TE through
  6938. * delayed work queue.
  6939. */
  6940. if (display->poms_pending &&
  6941. display->panel->poms_align_vsync) {
  6942. INIT_DELAYED_WORK(&display->poms_te_work,
  6943. dsi_display_handle_poms_te);
  6944. queue_delayed_work(system_wq,
  6945. &display->poms_te_work,
  6946. msecs_to_jiffies(100));
  6947. }
  6948. rc = dsi_display_cmd_engine_disable(display);
  6949. if (rc)
  6950. DSI_ERR("[%s]failed to disable DSI cmd engine, rc=%d\n",
  6951. display->name, rc);
  6952. } else {
  6953. DSI_ERR("[%s] Invalid configuration\n", display->name);
  6954. rc = -EINVAL;
  6955. }
  6956. if (!display->poms_pending && !is_skip_op_required(display)) {
  6957. rc = dsi_panel_disable(display->panel);
  6958. if (rc)
  6959. DSI_ERR("[%s] failed to disable DSI panel, rc=%d\n",
  6960. display->name, rc);
  6961. }
  6962. if (is_skip_op_required(display)) {
  6963. /* applicable only for trusted vm */
  6964. display->panel->panel_initialized = false;
  6965. display->panel->power_mode = SDE_MODE_DPMS_OFF;
  6966. }
  6967. mutex_unlock(&display->display_lock);
  6968. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  6969. return rc;
  6970. }
  6971. int dsi_display_update_pps(char *pps_cmd, void *disp)
  6972. {
  6973. struct dsi_display *display;
  6974. if (pps_cmd == NULL || disp == NULL) {
  6975. DSI_ERR("Invalid parameter\n");
  6976. return -EINVAL;
  6977. }
  6978. display = disp;
  6979. mutex_lock(&display->display_lock);
  6980. memcpy(display->panel->dce_pps_cmd, pps_cmd, DSI_CMD_PPS_SIZE);
  6981. mutex_unlock(&display->display_lock);
  6982. return 0;
  6983. }
  6984. int dsi_display_dump_clks_state(struct dsi_display *display)
  6985. {
  6986. int rc = 0;
  6987. if (!display) {
  6988. DSI_ERR("invalid display argument\n");
  6989. return -EINVAL;
  6990. }
  6991. if (!display->clk_mngr) {
  6992. DSI_ERR("invalid clk manager\n");
  6993. return -EINVAL;
  6994. }
  6995. if (!display->dsi_clk_handle || !display->mdp_clk_handle) {
  6996. DSI_ERR("invalid clk handles\n");
  6997. return -EINVAL;
  6998. }
  6999. mutex_lock(&display->display_lock);
  7000. rc = dsi_display_dump_clk_handle_state(display->dsi_clk_handle);
  7001. if (rc) {
  7002. DSI_ERR("failed to dump dsi clock state\n");
  7003. goto end;
  7004. }
  7005. rc = dsi_display_dump_clk_handle_state(display->mdp_clk_handle);
  7006. if (rc) {
  7007. DSI_ERR("failed to dump mdp clock state\n");
  7008. goto end;
  7009. }
  7010. end:
  7011. mutex_unlock(&display->display_lock);
  7012. return rc;
  7013. }
  7014. int dsi_display_unprepare(struct dsi_display *display)
  7015. {
  7016. int rc = 0, i;
  7017. struct dsi_display_ctrl *ctrl;
  7018. if (!display) {
  7019. DSI_ERR("Invalid params\n");
  7020. return -EINVAL;
  7021. }
  7022. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  7023. mutex_lock(&display->display_lock);
  7024. rc = dsi_display_wake_up(display);
  7025. if (rc)
  7026. DSI_ERR("[%s] display wake up failed, rc=%d\n",
  7027. display->name, rc);
  7028. if (!display->poms_pending && !is_skip_op_required(display)) {
  7029. rc = dsi_panel_unprepare(display->panel);
  7030. if (rc)
  7031. DSI_ERR("[%s] panel unprepare failed, rc=%d\n",
  7032. display->name, rc);
  7033. }
  7034. /* Remove additional vote added for pre_mode_switch_to_cmd */
  7035. if (display->poms_pending &&
  7036. display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  7037. display_for_each_ctrl(i, display) {
  7038. ctrl = &display->ctrl[i];
  7039. if (!ctrl->ctrl || !ctrl->ctrl->dma_wait_queued)
  7040. continue;
  7041. flush_workqueue(display->dma_cmd_workq);
  7042. cancel_work_sync(&ctrl->ctrl->dma_cmd_wait);
  7043. ctrl->ctrl->dma_wait_queued = false;
  7044. }
  7045. dsi_display_cmd_engine_disable(display);
  7046. dsi_display_clk_ctrl(display->dsi_clk_handle,
  7047. DSI_ALL_CLKS, DSI_CLK_OFF);
  7048. }
  7049. rc = dsi_display_ctrl_host_disable(display);
  7050. if (rc)
  7051. DSI_ERR("[%s] failed to disable DSI host, rc=%d\n",
  7052. display->name, rc);
  7053. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  7054. DSI_LINK_CLK, DSI_CLK_OFF);
  7055. if (rc)
  7056. DSI_ERR("[%s] failed to disable Link clocks, rc=%d\n",
  7057. display->name, rc);
  7058. rc = dsi_display_ctrl_deinit(display);
  7059. if (rc)
  7060. DSI_ERR("[%s] failed to deinit controller, rc=%d\n",
  7061. display->name, rc);
  7062. if (!display->panel->ulps_suspend_enabled) {
  7063. rc = dsi_display_phy_disable(display);
  7064. if (rc)
  7065. DSI_ERR("[%s] failed to disable DSI PHY, rc=%d\n",
  7066. display->name, rc);
  7067. }
  7068. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  7069. DSI_CORE_CLK, DSI_CLK_OFF);
  7070. if (rc)
  7071. DSI_ERR("[%s] failed to disable DSI clocks, rc=%d\n",
  7072. display->name, rc);
  7073. /* destrory dsi isr set up */
  7074. dsi_display_ctrl_isr_configure(display, false);
  7075. if (!display->poms_pending && !is_skip_op_required(display)) {
  7076. rc = dsi_panel_post_unprepare(display->panel);
  7077. if (rc)
  7078. DSI_ERR("[%s] panel post-unprepare failed, rc=%d\n",
  7079. display->name, rc);
  7080. }
  7081. mutex_unlock(&display->display_lock);
  7082. /* Free up DSI ERROR event callback */
  7083. dsi_display_unregister_error_handler(display);
  7084. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  7085. return rc;
  7086. }
  7087. void __init dsi_display_register(void)
  7088. {
  7089. dsi_phy_drv_register();
  7090. dsi_ctrl_drv_register();
  7091. dsi_display_parse_boot_display_selection();
  7092. platform_driver_register(&dsi_display_driver);
  7093. }
  7094. void __exit dsi_display_unregister(void)
  7095. {
  7096. platform_driver_unregister(&dsi_display_driver);
  7097. dsi_ctrl_drv_unregister();
  7098. dsi_phy_drv_unregister();
  7099. }
  7100. module_param_string(dsi_display0, dsi_display_primary, MAX_CMDLINE_PARAM_LEN,
  7101. 0600);
  7102. MODULE_PARM_DESC(dsi_display0,
  7103. "msm_drm.dsi_display0=<display node>:<configX> where <display node> is 'primary dsi display node name' and <configX> where x represents index in the topology list");
  7104. module_param_string(dsi_display1, dsi_display_secondary, MAX_CMDLINE_PARAM_LEN,
  7105. 0600);
  7106. MODULE_PARM_DESC(dsi_display1,
  7107. "msm_drm.dsi_display1=<display node>:<configX> where <display node> is 'secondary dsi display node name' and <configX> where x represents index in the topology list");