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android_kernel_...
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soc
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swr-slave-registers.h

swr-slave-registers.h 4.6 KB
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  1. /* SPDX-License-Identifier: GPL-2.0-only */
    2. 

  2. /*
    3. 

  3.  * Copyright (c) 2015, 2018-2020 The Linux Foundation. All rights reserved.
    4. 

  4.  */
    5. 

  5. 

  6. #ifndef _SWR_SLAVE_REGISTERS_H
    7. 

  7. #define _SWR_SLAVE_REGISTERS_H
    8. 

  8. 

  9. #define SWRS_BASE                               0x00
    10. 

  10. 

  11. #define SWRS_SCP_INT_STATUS_1                           (SWRS_BASE+0x0040)
    12. 

  12. #define SWRS_SCP_INT_CLEAR_1                            (SWRS_BASE+0x0040)
    13. 

  13. #define SWRS_SCP_INT_MASK_1                             (SWRS_BASE+0x0041)
    14. 

  14. #define SWRS_SCP_INT_STATUS_2                           (SWRS_BASE+0x0042)
    15. 

  15. #define SWRS_SCP_INT_STATUS_3                           (SWRS_BASE+0x0043)
    16. 

  16. #define SWRS_SCP_CONTROL                                (SWRS_BASE+0x0044)
    17. 

  17. #define SWRS_SCP_STATUS                                 (SWRS_BASE+0x0044)
    18. 

  18. #define SWRS_SCP_CLOCK_STOP_CONTROL                     (SWRS_BASE+0x0045)
    19. 

  19. #define SWRS_SCP_DEV_NUMBER                             (SWRS_BASE+0x0046)
    20. 

  20. #define SWRS_SCP_KEEPER_EN                              (SWRS_BASE+0x004A)
    21. 

  21. #define SWRS_SCP_DEVICE_ID_0                            (SWRS_BASE+0x0050)
    22. 

  22. #define SWRS_SCP_DEVICE_ID_1                            (SWRS_BASE+0x0051)
    23. 

  23. #define SWRS_SCP_DEVICE_ID_2                            (SWRS_BASE+0x0052)
    24. 

  24. #define SWRS_SCP_DEVICE_ID_3                            (SWRS_BASE+0x0053)
    25. 

  25. #define SWRS_SCP_DEVICE_ID_4                            (SWRS_BASE+0x0054)
    26. 

  26. #define SWRS_SCP_DEVICE_ID_5                            (SWRS_BASE+0x0055)
    27. 

  27. #define SWRS_SCP_FRAME_CTRL_BANK(m)                    (SWRS_BASE+0x0060+0x10*m)
    28. 

  28. #define SWRS_SCP_IMPDEF_SWR_INTERRUPT_DETECT_TYPE      (SWRS_BASE+0x00C8)
    29. 

  29. #define SWRS_SCP_HOST_CLK_DIV2_CTL_BANK(m)             (SWRS_BASE+0x00E0+0x10*m)
    30. 

  30. #define SWRS_DP_INT_STATUS(n)                          (SWRS_BASE+0x100+0x0100*n)
    31. 

  31. #define SWRS_DP_INT_STATUS_MASK(n)                     (SWRS_BASE+0x101+0x100*n)
    32. 

  32. #define SWRS_DP_PORT_CONTROL(n)                        (SWRS_BASE+0x102+0x100*n)
    33. 

  33. #define SWRS_DP_BLOCK_CONTROL_1(n)                     (SWRS_BASE+0x103+0x100*n)
    34. 

  34. #define SWRS_DP_PREPARE_STATUS(n)                      (SWRS_BASE+0x104+0x100*n)
    35. 

  35. #define SWRS_DP_PREPARE_CONTROL(n)                     (SWRS_BASE+0x105+0x100*n)
    36. 

  36. #define SWRS_DP_CHANNEL_ENABLE_BANK(n, m)       (SWRS_BASE+0x120+0x100*n+0x10*m)
    37. 

  37. #define SWRS_DP_BLOCK_CONTROL_2_BANK(n, m)      (SWRS_BASE+0x121+0x100*n+0x10*m)
    38. 

  38. #define SWRS_DP_SAMPLE_CONTROL_1_BANK(n, m)     (SWRS_BASE+0x122+0x100*n+0x10*m)
    39. 

  39. #define SWRS_DP_SAMPLE_CONTROL_2_BANK(n, m)     (SWRS_BASE+0x123+0x100*n+0x10*m)
    40. 

  40. #define SWRS_DP_OFFSET_CONTROL_1_BANK(n, m)     (SWRS_BASE+0x124+0x100*n+0x10*m)
    41. 

  41. #define SWRS_DP_OFFSET_CONTROL_2_BANK(n, m)     (SWRS_BASE+0x125+0x100*n+0x10*m)
    42. 

  42. #define SWRS_DP_HCONTROL_BANK(n, m)             (SWRS_BASE+0x126+0x100*n+0x10*m)
    43. 

  43. #define SWRS_DP_BLOCK_CONTROL_3_BANK(n, m)      (SWRS_BASE+0x127+0x100*n+0x10*m)
    44. 

  44. #define SWRS_DP_LANE_CONTROL_BANK(n, m)         (SWRS_BASE+0x128+0x100*n+0x10*m)
    45. 

  45. #define SWRS_DP_ALL_INT_STATUS                  (SWRS_BASE+0x0F00)
    46. 

  46. #define SWRS_DP_ALL_INT_STATUS_MASK             (SWRS_BASE+0x0F01)
    47. 

  47. #define SWRS_DP_ALL_PORT_CONTROL                (SWRS_BASE+0x0F02)
    48. 

  48. #define SWRS_DP_ALL_BLOCK_CONTROL_1             (SWRS_BASE+0x0F03)
    49. 

  49. #define SWRS_DP_ALL_PREPARE_STATUS              (SWRS_BASE+0x0F04)
    50. 

  50. #define SWRS_DP_ALL_PREPARE_CONTROL             (SWRS_BASE+0x0F05)
    51. 

  51. #define SWRS_DP_ALL_CHANNEL_ENABLE_BANK(m)             (SWRS_BASE+0x0F20+0x10*m)
    52. 

  52. #define SWRS_DP_ALL_BLOCK_CONTROL_2_BANK(m)            (SWRS_BASE+0x0F21+0x10*m)
    53. 

  53. #define SWRS_DP_ALL_SAMPLE_CONTROL_1_BANK(m)           (SWRS_BASE+0x0F22+0x10*m)
    54. 

  54. #define SWRS_DP_ALL_SAMPLE_CONTROL_2_BANK(m)           (SWRS_BASE+0x0F23+0x10*m)
    55. 

  55. #define SWRS_DP_ALL_OFFSET_CONTROL_1_BANK(m)           (SWRS_BASE+0x0F24+0x10*m)
    56. 

  56. #define SWRS_DP_ALL_OFFSET_CONTROL_2_BANK(m)           (SWRS_BASE+0x0F25+0x10*m)
    57. 

  57. #define SWRS_DP_ALL_HCONTROL_BANK(m)                   (SWRS_BASE+0x0F26+0x10*m)
    58. 

  58. #define SWRS_DP_ALL_BLOCK_CONTROL_3_BANK(m)            (SWRS_BASE+0x0F27+0x10*m)
    59. 

  59. #define SWRS_DP_ALL_LANE_CONTROL_BANK(m)               (SWRS_BASE+0x0F28+0x10*m)
    60. 

  60. #define SWRS_COMP_HW_VERSION_MAJOR      (SWRS_BASE+0x2000)
    61. 

  61. #define SWRS_COMP_HW_VERSION_MINOR      (SWRS_BASE+0x2001)
    62. 

  62. #define SWRS_COMP_HW_VERSION_STEP       (SWRS_BASE+0x2002)
    63. 

  63. #define SWRS_COMP_STATUS                (SWRS_BASE+0x2003)
    64. 

  64. #define SWRS_COMP_POWER_CFG             (SWRS_BASE+0x2004)
    65. 

  65. #define SWRS_COMP_FEATURE_CFG           (SWRS_BASE+0x2005)
    66. 

  66. #define SWRS_COMP_PARAMS                (SWRS_BASE+0x2006)
    67. 

  67. #define SWRS_TEST_BUS_CTL               (SWRS_BASE+0x2007)
    68. 

  68. #define SWRS_TEST_BUS_STATUS_LOW        (SWRS_BASE+0x200A)
    69. 

  69. #define SWRS_TEST_BUS_STATUS_HIGH       (SWRS_BASE+0x200B)
    70. 

  70. #define SWRS_LOOPBACK_CTL               (SWRS_BASE+0x2009)
    71. 

  71. 

  72. #endif /* _SWR_SLAVE_REGISTERS_H */
    73.