dp_tx.c 123 KB

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  1. /*
  2. * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "dp_htt.h"
  20. #include "hal_hw_headers.h"
  21. #include "dp_tx.h"
  22. #include "dp_tx_desc.h"
  23. #include "dp_peer.h"
  24. #include "dp_types.h"
  25. #include "hal_tx.h"
  26. #include "qdf_mem.h"
  27. #include "qdf_nbuf.h"
  28. #include "qdf_net_types.h"
  29. #include <wlan_cfg.h>
  30. #include "dp_ipa.h"
  31. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  32. #include "if_meta_hdr.h"
  33. #endif
  34. #include "enet.h"
  35. #include "dp_internal.h"
  36. #ifdef FEATURE_WDS
  37. #include "dp_txrx_wds.h"
  38. #endif
  39. #ifdef ATH_SUPPORT_IQUE
  40. #include "dp_txrx_me.h"
  41. #endif
  42. /* TODO Add support in TSO */
  43. #define DP_DESC_NUM_FRAG(x) 0
  44. /* disable TQM_BYPASS */
  45. #define TQM_BYPASS_WAR 0
  46. /* invalid peer id for reinject*/
  47. #define DP_INVALID_PEER 0XFFFE
  48. /*mapping between hal encrypt type and cdp_sec_type*/
  49. #define MAX_CDP_SEC_TYPE 12
  50. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  51. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  52. HAL_TX_ENCRYPT_TYPE_WEP_128,
  53. HAL_TX_ENCRYPT_TYPE_WEP_104,
  54. HAL_TX_ENCRYPT_TYPE_WEP_40,
  55. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  56. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  57. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  58. HAL_TX_ENCRYPT_TYPE_WAPI,
  59. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  60. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  61. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  62. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  63. #ifdef QCA_TX_LIMIT_CHECK
  64. /**
  65. * dp_tx_limit_check - Check if allocated tx descriptors reached
  66. * soc max limit and pdev max limit
  67. * @vdev: DP vdev handle
  68. *
  69. * Return: true if allocated tx descriptors reached max configured value, else
  70. * false
  71. */
  72. static inline bool
  73. dp_tx_limit_check(struct dp_vdev *vdev)
  74. {
  75. struct dp_pdev *pdev = vdev->pdev;
  76. struct dp_soc *soc = pdev->soc;
  77. if (qdf_atomic_read(&soc->num_tx_outstanding) >=
  78. soc->num_tx_allowed) {
  79. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  80. "%s: queued packets are more than max tx, drop the frame",
  81. __func__);
  82. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  83. return true;
  84. }
  85. if (qdf_atomic_read(&pdev->num_tx_outstanding) >=
  86. pdev->num_tx_allowed) {
  87. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  88. "%s: queued packets are more than max tx, drop the frame",
  89. __func__);
  90. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  91. return true;
  92. }
  93. return false;
  94. }
  95. /**
  96. * dp_tx_exception_limit_check - Check if allocated tx exception descriptors
  97. * reached soc max limit
  98. * @vdev: DP vdev handle
  99. *
  100. * Return: true if allocated tx descriptors reached max configured value, else
  101. * false
  102. */
  103. static inline bool
  104. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  105. {
  106. struct dp_pdev *pdev = vdev->pdev;
  107. struct dp_soc *soc = pdev->soc;
  108. if (qdf_atomic_read(&soc->num_tx_exception) >=
  109. soc->num_msdu_exception_desc) {
  110. dp_info("exc packets are more than max drop the exc pkt");
  111. DP_STATS_INC(vdev, tx_i.dropped.exc_desc_na.num, 1);
  112. return true;
  113. }
  114. return false;
  115. }
  116. /**
  117. * dp_tx_outstanding_inc - Increment outstanding tx desc values on pdev and soc
  118. * @vdev: DP pdev handle
  119. *
  120. * Return: void
  121. */
  122. static inline void
  123. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  124. {
  125. struct dp_soc *soc = pdev->soc;
  126. qdf_atomic_inc(&pdev->num_tx_outstanding);
  127. qdf_atomic_inc(&soc->num_tx_outstanding);
  128. }
  129. /**
  130. * dp_tx_outstanding__dec - Decrement outstanding tx desc values on pdev and soc
  131. * @vdev: DP pdev handle
  132. *
  133. * Return: void
  134. */
  135. static inline void
  136. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  137. {
  138. struct dp_soc *soc = pdev->soc;
  139. qdf_atomic_dec(&pdev->num_tx_outstanding);
  140. qdf_atomic_dec(&soc->num_tx_outstanding);
  141. }
  142. #else //QCA_TX_LIMIT_CHECK
  143. static inline bool
  144. dp_tx_limit_check(struct dp_vdev *vdev)
  145. {
  146. return false;
  147. }
  148. static inline bool
  149. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  150. {
  151. return false;
  152. }
  153. static inline void
  154. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  155. {
  156. qdf_atomic_inc(&pdev->num_tx_outstanding);
  157. }
  158. static inline void
  159. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  160. {
  161. qdf_atomic_dec(&pdev->num_tx_outstanding);
  162. }
  163. #endif //QCA_TX_LIMIT_CHECK
  164. #if defined(FEATURE_TSO)
  165. /**
  166. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  167. *
  168. * @soc - core txrx main context
  169. * @seg_desc - tso segment descriptor
  170. * @num_seg_desc - tso number segment descriptor
  171. */
  172. static void dp_tx_tso_unmap_segment(
  173. struct dp_soc *soc,
  174. struct qdf_tso_seg_elem_t *seg_desc,
  175. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  176. {
  177. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  178. if (qdf_unlikely(!seg_desc)) {
  179. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  180. __func__, __LINE__);
  181. qdf_assert(0);
  182. } else if (qdf_unlikely(!num_seg_desc)) {
  183. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  184. __func__, __LINE__);
  185. qdf_assert(0);
  186. } else {
  187. bool is_last_seg;
  188. /* no tso segment left to do dma unmap */
  189. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  190. return;
  191. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  192. true : false;
  193. qdf_nbuf_unmap_tso_segment(soc->osdev,
  194. seg_desc, is_last_seg);
  195. num_seg_desc->num_seg.tso_cmn_num_seg--;
  196. }
  197. }
  198. /**
  199. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  200. * back to the freelist
  201. *
  202. * @soc - soc device handle
  203. * @tx_desc - Tx software descriptor
  204. */
  205. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  206. struct dp_tx_desc_s *tx_desc)
  207. {
  208. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  209. if (qdf_unlikely(!tx_desc->tso_desc)) {
  210. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  211. "%s %d TSO desc is NULL!",
  212. __func__, __LINE__);
  213. qdf_assert(0);
  214. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  215. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  216. "%s %d TSO num desc is NULL!",
  217. __func__, __LINE__);
  218. qdf_assert(0);
  219. } else {
  220. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  221. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  222. /* Add the tso num segment into the free list */
  223. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  224. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  225. tx_desc->tso_num_desc);
  226. tx_desc->tso_num_desc = NULL;
  227. DP_STATS_INC(tx_desc->pdev, tso_stats.tso_comp, 1);
  228. }
  229. /* Add the tso segment into the free list*/
  230. dp_tx_tso_desc_free(soc,
  231. tx_desc->pool_id, tx_desc->tso_desc);
  232. tx_desc->tso_desc = NULL;
  233. }
  234. }
  235. #else
  236. static void dp_tx_tso_unmap_segment(
  237. struct dp_soc *soc,
  238. struct qdf_tso_seg_elem_t *seg_desc,
  239. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  240. {
  241. }
  242. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  243. struct dp_tx_desc_s *tx_desc)
  244. {
  245. }
  246. #endif
  247. /**
  248. * dp_tx_desc_release() - Release Tx Descriptor
  249. * @tx_desc : Tx Descriptor
  250. * @desc_pool_id: Descriptor Pool ID
  251. *
  252. * Deallocate all resources attached to Tx descriptor and free the Tx
  253. * descriptor.
  254. *
  255. * Return:
  256. */
  257. static void
  258. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  259. {
  260. struct dp_pdev *pdev = tx_desc->pdev;
  261. struct dp_soc *soc;
  262. uint8_t comp_status = 0;
  263. qdf_assert(pdev);
  264. soc = pdev->soc;
  265. dp_tx_outstanding_dec(pdev);
  266. if (tx_desc->frm_type == dp_tx_frm_tso)
  267. dp_tx_tso_desc_release(soc, tx_desc);
  268. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  269. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  270. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  271. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  272. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  273. qdf_atomic_dec(&soc->num_tx_exception);
  274. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  275. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  276. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  277. soc->hal_soc);
  278. else
  279. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  280. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  281. "Tx Completion Release desc %d status %d outstanding %d",
  282. tx_desc->id, comp_status,
  283. qdf_atomic_read(&pdev->num_tx_outstanding));
  284. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  285. return;
  286. }
  287. /**
  288. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  289. * @vdev: DP vdev Handle
  290. * @nbuf: skb
  291. * @msdu_info: msdu_info required to create HTT metadata
  292. *
  293. * Prepares and fills HTT metadata in the frame pre-header for special frames
  294. * that should be transmitted using varying transmit parameters.
  295. * There are 2 VDEV modes that currently needs this special metadata -
  296. * 1) Mesh Mode
  297. * 2) DSRC Mode
  298. *
  299. * Return: HTT metadata size
  300. *
  301. */
  302. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  303. struct dp_tx_msdu_info_s *msdu_info)
  304. {
  305. uint32_t *meta_data = msdu_info->meta_data;
  306. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  307. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  308. uint8_t htt_desc_size;
  309. /* Size rounded of multiple of 8 bytes */
  310. uint8_t htt_desc_size_aligned;
  311. uint8_t *hdr = NULL;
  312. /*
  313. * Metadata - HTT MSDU Extension header
  314. */
  315. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  316. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  317. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  318. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  319. meta_data[0])) {
  320. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  321. htt_desc_size_aligned)) {
  322. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  323. htt_desc_size_aligned);
  324. if (!nbuf) {
  325. /*
  326. * qdf_nbuf_realloc_headroom won't do skb_clone
  327. * as skb_realloc_headroom does. so, no free is
  328. * needed here.
  329. */
  330. DP_STATS_INC(vdev,
  331. tx_i.dropped.headroom_insufficient,
  332. 1);
  333. qdf_print(" %s[%d] skb_realloc_headroom failed",
  334. __func__, __LINE__);
  335. return 0;
  336. }
  337. }
  338. /* Fill and add HTT metaheader */
  339. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  340. if (!hdr) {
  341. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  342. "Error in filling HTT metadata");
  343. return 0;
  344. }
  345. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  346. } else if (vdev->opmode == wlan_op_mode_ocb) {
  347. /* Todo - Add support for DSRC */
  348. }
  349. return htt_desc_size_aligned;
  350. }
  351. /**
  352. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  353. * @tso_seg: TSO segment to process
  354. * @ext_desc: Pointer to MSDU extension descriptor
  355. *
  356. * Return: void
  357. */
  358. #if defined(FEATURE_TSO)
  359. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  360. void *ext_desc)
  361. {
  362. uint8_t num_frag;
  363. uint32_t tso_flags;
  364. /*
  365. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  366. * tcp_flag_mask
  367. *
  368. * Checksum enable flags are set in TCL descriptor and not in Extension
  369. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  370. */
  371. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  372. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  373. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  374. tso_seg->tso_flags.ip_len);
  375. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  376. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  377. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  378. uint32_t lo = 0;
  379. uint32_t hi = 0;
  380. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  381. (tso_seg->tso_frags[num_frag].length));
  382. qdf_dmaaddr_to_32s(
  383. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  384. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  385. tso_seg->tso_frags[num_frag].length);
  386. }
  387. return;
  388. }
  389. #else
  390. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  391. void *ext_desc)
  392. {
  393. return;
  394. }
  395. #endif
  396. #if defined(FEATURE_TSO)
  397. /**
  398. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  399. * allocated and free them
  400. *
  401. * @soc: soc handle
  402. * @free_seg: list of tso segments
  403. * @msdu_info: msdu descriptor
  404. *
  405. * Return - void
  406. */
  407. static void dp_tx_free_tso_seg_list(
  408. struct dp_soc *soc,
  409. struct qdf_tso_seg_elem_t *free_seg,
  410. struct dp_tx_msdu_info_s *msdu_info)
  411. {
  412. struct qdf_tso_seg_elem_t *next_seg;
  413. while (free_seg) {
  414. next_seg = free_seg->next;
  415. dp_tx_tso_desc_free(soc,
  416. msdu_info->tx_queue.desc_pool_id,
  417. free_seg);
  418. free_seg = next_seg;
  419. }
  420. }
  421. /**
  422. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  423. * allocated and free them
  424. *
  425. * @soc: soc handle
  426. * @free_num_seg: list of tso number segments
  427. * @msdu_info: msdu descriptor
  428. * Return - void
  429. */
  430. static void dp_tx_free_tso_num_seg_list(
  431. struct dp_soc *soc,
  432. struct qdf_tso_num_seg_elem_t *free_num_seg,
  433. struct dp_tx_msdu_info_s *msdu_info)
  434. {
  435. struct qdf_tso_num_seg_elem_t *next_num_seg;
  436. while (free_num_seg) {
  437. next_num_seg = free_num_seg->next;
  438. dp_tso_num_seg_free(soc,
  439. msdu_info->tx_queue.desc_pool_id,
  440. free_num_seg);
  441. free_num_seg = next_num_seg;
  442. }
  443. }
  444. /**
  445. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  446. * do dma unmap for each segment
  447. *
  448. * @soc: soc handle
  449. * @free_seg: list of tso segments
  450. * @num_seg_desc: tso number segment descriptor
  451. *
  452. * Return - void
  453. */
  454. static void dp_tx_unmap_tso_seg_list(
  455. struct dp_soc *soc,
  456. struct qdf_tso_seg_elem_t *free_seg,
  457. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  458. {
  459. struct qdf_tso_seg_elem_t *next_seg;
  460. if (qdf_unlikely(!num_seg_desc)) {
  461. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  462. return;
  463. }
  464. while (free_seg) {
  465. next_seg = free_seg->next;
  466. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  467. free_seg = next_seg;
  468. }
  469. }
  470. #ifdef FEATURE_TSO_STATS
  471. /**
  472. * dp_tso_get_stats_idx: Retrieve the tso packet id
  473. * @pdev - pdev handle
  474. *
  475. * Return: id
  476. */
  477. static uint32_t dp_tso_get_stats_idx(struct dp_pdev *pdev)
  478. {
  479. uint32_t stats_idx;
  480. stats_idx = (((uint32_t)qdf_atomic_inc_return(&pdev->tso_idx))
  481. % CDP_MAX_TSO_PACKETS);
  482. return stats_idx;
  483. }
  484. #else
  485. static int dp_tso_get_stats_idx(struct dp_pdev *pdev)
  486. {
  487. return 0;
  488. }
  489. #endif /* FEATURE_TSO_STATS */
  490. /**
  491. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  492. * free the tso segments descriptor and
  493. * tso num segments descriptor
  494. *
  495. * @soc: soc handle
  496. * @msdu_info: msdu descriptor
  497. * @tso_seg_unmap: flag to show if dma unmap is necessary
  498. *
  499. * Return - void
  500. */
  501. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  502. struct dp_tx_msdu_info_s *msdu_info,
  503. bool tso_seg_unmap)
  504. {
  505. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  506. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  507. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  508. tso_info->tso_num_seg_list;
  509. /* do dma unmap for each segment */
  510. if (tso_seg_unmap)
  511. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  512. /* free all tso number segment descriptor though looks only have 1 */
  513. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  514. /* free all tso segment descriptor */
  515. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  516. }
  517. /**
  518. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  519. * @vdev: virtual device handle
  520. * @msdu: network buffer
  521. * @msdu_info: meta data associated with the msdu
  522. *
  523. * Return: QDF_STATUS_SUCCESS success
  524. */
  525. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  526. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  527. {
  528. struct qdf_tso_seg_elem_t *tso_seg;
  529. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  530. struct dp_soc *soc = vdev->pdev->soc;
  531. struct dp_pdev *pdev = vdev->pdev;
  532. struct qdf_tso_info_t *tso_info;
  533. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  534. tso_info = &msdu_info->u.tso_info;
  535. tso_info->curr_seg = NULL;
  536. tso_info->tso_seg_list = NULL;
  537. tso_info->num_segs = num_seg;
  538. msdu_info->frm_type = dp_tx_frm_tso;
  539. tso_info->tso_num_seg_list = NULL;
  540. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  541. while (num_seg) {
  542. tso_seg = dp_tx_tso_desc_alloc(
  543. soc, msdu_info->tx_queue.desc_pool_id);
  544. if (tso_seg) {
  545. tso_seg->next = tso_info->tso_seg_list;
  546. tso_info->tso_seg_list = tso_seg;
  547. num_seg--;
  548. } else {
  549. dp_err_rl("Failed to alloc tso seg desc");
  550. DP_STATS_INC_PKT(vdev->pdev,
  551. tso_stats.tso_no_mem_dropped, 1,
  552. qdf_nbuf_len(msdu));
  553. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  554. return QDF_STATUS_E_NOMEM;
  555. }
  556. }
  557. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  558. tso_num_seg = dp_tso_num_seg_alloc(soc,
  559. msdu_info->tx_queue.desc_pool_id);
  560. if (tso_num_seg) {
  561. tso_num_seg->next = tso_info->tso_num_seg_list;
  562. tso_info->tso_num_seg_list = tso_num_seg;
  563. } else {
  564. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  565. __func__);
  566. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  567. return QDF_STATUS_E_NOMEM;
  568. }
  569. msdu_info->num_seg =
  570. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  571. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  572. msdu_info->num_seg);
  573. if (!(msdu_info->num_seg)) {
  574. /*
  575. * Free allocated TSO seg desc and number seg desc,
  576. * do unmap for segments if dma map has done.
  577. */
  578. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  579. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  580. return QDF_STATUS_E_INVAL;
  581. }
  582. tso_info->curr_seg = tso_info->tso_seg_list;
  583. tso_info->msdu_stats_idx = dp_tso_get_stats_idx(pdev);
  584. dp_tso_packet_update(pdev, tso_info->msdu_stats_idx,
  585. msdu, msdu_info->num_seg);
  586. dp_tso_segment_stats_update(pdev, tso_info->tso_seg_list,
  587. tso_info->msdu_stats_idx);
  588. dp_stats_tso_segment_histogram_update(pdev, msdu_info->num_seg);
  589. return QDF_STATUS_SUCCESS;
  590. }
  591. #else
  592. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  593. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  594. {
  595. return QDF_STATUS_E_NOMEM;
  596. }
  597. #endif
  598. /**
  599. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  600. * @vdev: DP Vdev handle
  601. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  602. * @desc_pool_id: Descriptor Pool ID
  603. *
  604. * Return:
  605. */
  606. static
  607. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  608. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  609. {
  610. uint8_t i;
  611. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  612. struct dp_tx_seg_info_s *seg_info;
  613. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  614. struct dp_soc *soc = vdev->pdev->soc;
  615. /* Allocate an extension descriptor */
  616. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  617. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  618. if (!msdu_ext_desc) {
  619. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  620. return NULL;
  621. }
  622. if (msdu_info->exception_fw &&
  623. qdf_unlikely(vdev->mesh_vdev)) {
  624. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  625. &msdu_info->meta_data[0],
  626. sizeof(struct htt_tx_msdu_desc_ext2_t));
  627. qdf_atomic_inc(&soc->num_tx_exception);
  628. }
  629. switch (msdu_info->frm_type) {
  630. case dp_tx_frm_sg:
  631. case dp_tx_frm_me:
  632. case dp_tx_frm_raw:
  633. seg_info = msdu_info->u.sg_info.curr_seg;
  634. /* Update the buffer pointers in MSDU Extension Descriptor */
  635. for (i = 0; i < seg_info->frag_cnt; i++) {
  636. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  637. seg_info->frags[i].paddr_lo,
  638. seg_info->frags[i].paddr_hi,
  639. seg_info->frags[i].len);
  640. }
  641. break;
  642. case dp_tx_frm_tso:
  643. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  644. &cached_ext_desc[0]);
  645. break;
  646. default:
  647. break;
  648. }
  649. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  650. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  651. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  652. msdu_ext_desc->vaddr);
  653. return msdu_ext_desc;
  654. }
  655. /**
  656. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  657. *
  658. * @skb: skb to be traced
  659. * @msdu_id: msdu_id of the packet
  660. * @vdev_id: vdev_id of the packet
  661. *
  662. * Return: None
  663. */
  664. #ifdef DP_DISABLE_TX_PKT_TRACE
  665. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  666. uint8_t vdev_id)
  667. {
  668. }
  669. #else
  670. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  671. uint8_t vdev_id)
  672. {
  673. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  674. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  675. DPTRACE(qdf_dp_trace_ptr(skb,
  676. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  677. QDF_TRACE_DEFAULT_PDEV_ID,
  678. qdf_nbuf_data_addr(skb),
  679. sizeof(qdf_nbuf_data(skb)),
  680. msdu_id, vdev_id));
  681. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  682. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  683. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  684. msdu_id, QDF_TX));
  685. }
  686. #endif
  687. /**
  688. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  689. * @vdev: DP vdev handle
  690. * @nbuf: skb
  691. * @desc_pool_id: Descriptor pool ID
  692. * @meta_data: Metadata to the fw
  693. * @tx_exc_metadata: Handle that holds exception path metadata
  694. * Allocate and prepare Tx descriptor with msdu information.
  695. *
  696. * Return: Pointer to Tx Descriptor on success,
  697. * NULL on failure
  698. */
  699. static
  700. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  701. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  702. struct dp_tx_msdu_info_s *msdu_info,
  703. struct cdp_tx_exception_metadata *tx_exc_metadata)
  704. {
  705. uint8_t align_pad;
  706. uint8_t is_exception = 0;
  707. uint8_t htt_hdr_size;
  708. struct dp_tx_desc_s *tx_desc;
  709. struct dp_pdev *pdev = vdev->pdev;
  710. struct dp_soc *soc = pdev->soc;
  711. if (dp_tx_limit_check(vdev))
  712. return NULL;
  713. /* Allocate software Tx descriptor */
  714. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  715. if (qdf_unlikely(!tx_desc)) {
  716. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  717. return NULL;
  718. }
  719. dp_tx_outstanding_inc(pdev);
  720. /* Initialize the SW tx descriptor */
  721. tx_desc->nbuf = nbuf;
  722. tx_desc->frm_type = dp_tx_frm_std;
  723. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  724. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  725. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  726. tx_desc->vdev = vdev;
  727. tx_desc->pdev = pdev;
  728. tx_desc->msdu_ext_desc = NULL;
  729. tx_desc->pkt_offset = 0;
  730. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  731. if (qdf_unlikely(vdev->multipass_en)) {
  732. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  733. goto failure;
  734. }
  735. /*
  736. * For special modes (vdev_type == ocb or mesh), data frames should be
  737. * transmitted using varying transmit parameters (tx spec) which include
  738. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  739. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  740. * These frames are sent as exception packets to firmware.
  741. *
  742. * HW requirement is that metadata should always point to a
  743. * 8-byte aligned address. So we add alignment pad to start of buffer.
  744. * HTT Metadata should be ensured to be multiple of 8-bytes,
  745. * to get 8-byte aligned start address along with align_pad added
  746. *
  747. * |-----------------------------|
  748. * | |
  749. * |-----------------------------| <-----Buffer Pointer Address given
  750. * | | ^ in HW descriptor (aligned)
  751. * | HTT Metadata | |
  752. * | | |
  753. * | | | Packet Offset given in descriptor
  754. * | | |
  755. * |-----------------------------| |
  756. * | Alignment Pad | v
  757. * |-----------------------------| <----- Actual buffer start address
  758. * | SKB Data | (Unaligned)
  759. * | |
  760. * | |
  761. * | |
  762. * | |
  763. * | |
  764. * |-----------------------------|
  765. */
  766. if (qdf_unlikely((msdu_info->exception_fw)) ||
  767. (vdev->opmode == wlan_op_mode_ocb) ||
  768. (tx_exc_metadata &&
  769. tx_exc_metadata->is_tx_sniffer)) {
  770. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  771. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  772. DP_STATS_INC(vdev,
  773. tx_i.dropped.headroom_insufficient, 1);
  774. goto failure;
  775. }
  776. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  777. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  778. "qdf_nbuf_push_head failed");
  779. goto failure;
  780. }
  781. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  782. msdu_info);
  783. if (htt_hdr_size == 0)
  784. goto failure;
  785. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  786. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  787. is_exception = 1;
  788. }
  789. #if !TQM_BYPASS_WAR
  790. if (is_exception || tx_exc_metadata)
  791. #endif
  792. {
  793. /* Temporary WAR due to TQM VP issues */
  794. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  795. qdf_atomic_inc(&soc->num_tx_exception);
  796. }
  797. return tx_desc;
  798. failure:
  799. dp_tx_desc_release(tx_desc, desc_pool_id);
  800. return NULL;
  801. }
  802. /**
  803. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  804. * @vdev: DP vdev handle
  805. * @nbuf: skb
  806. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  807. * @desc_pool_id : Descriptor Pool ID
  808. *
  809. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  810. * information. For frames wth fragments, allocate and prepare
  811. * an MSDU extension descriptor
  812. *
  813. * Return: Pointer to Tx Descriptor on success,
  814. * NULL on failure
  815. */
  816. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  817. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  818. uint8_t desc_pool_id)
  819. {
  820. struct dp_tx_desc_s *tx_desc;
  821. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  822. struct dp_pdev *pdev = vdev->pdev;
  823. struct dp_soc *soc = pdev->soc;
  824. if (dp_tx_limit_check(vdev))
  825. return NULL;
  826. /* Allocate software Tx descriptor */
  827. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  828. if (!tx_desc) {
  829. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  830. return NULL;
  831. }
  832. dp_tx_outstanding_inc(pdev);
  833. /* Initialize the SW tx descriptor */
  834. tx_desc->nbuf = nbuf;
  835. tx_desc->frm_type = msdu_info->frm_type;
  836. tx_desc->tx_encap_type = vdev->tx_encap_type;
  837. tx_desc->vdev = vdev;
  838. tx_desc->pdev = pdev;
  839. tx_desc->pkt_offset = 0;
  840. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  841. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  842. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  843. /* Handle scattered frames - TSO/SG/ME */
  844. /* Allocate and prepare an extension descriptor for scattered frames */
  845. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  846. if (!msdu_ext_desc) {
  847. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  848. "%s Tx Extension Descriptor Alloc Fail",
  849. __func__);
  850. goto failure;
  851. }
  852. #if TQM_BYPASS_WAR
  853. /* Temporary WAR due to TQM VP issues */
  854. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  855. qdf_atomic_inc(&soc->num_tx_exception);
  856. #endif
  857. if (qdf_unlikely(msdu_info->exception_fw))
  858. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  859. tx_desc->msdu_ext_desc = msdu_ext_desc;
  860. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  861. return tx_desc;
  862. failure:
  863. dp_tx_desc_release(tx_desc, desc_pool_id);
  864. return NULL;
  865. }
  866. /**
  867. * dp_tx_prepare_raw() - Prepare RAW packet TX
  868. * @vdev: DP vdev handle
  869. * @nbuf: buffer pointer
  870. * @seg_info: Pointer to Segment info Descriptor to be prepared
  871. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  872. * descriptor
  873. *
  874. * Return:
  875. */
  876. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  877. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  878. {
  879. qdf_nbuf_t curr_nbuf = NULL;
  880. uint16_t total_len = 0;
  881. qdf_dma_addr_t paddr;
  882. int32_t i;
  883. int32_t mapped_buf_num = 0;
  884. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  885. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  886. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  887. /* Continue only if frames are of DATA type */
  888. if (!DP_FRAME_IS_DATA(qos_wh)) {
  889. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  890. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  891. "Pkt. recd is of not data type");
  892. goto error;
  893. }
  894. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  895. if (vdev->raw_mode_war &&
  896. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  897. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  898. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  899. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  900. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  901. if (QDF_STATUS_SUCCESS !=
  902. qdf_nbuf_map_nbytes_single(vdev->osdev,
  903. curr_nbuf,
  904. QDF_DMA_TO_DEVICE,
  905. curr_nbuf->len)) {
  906. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  907. "%s dma map error ", __func__);
  908. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  909. mapped_buf_num = i;
  910. goto error;
  911. }
  912. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  913. seg_info->frags[i].paddr_lo = paddr;
  914. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  915. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  916. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  917. total_len += qdf_nbuf_len(curr_nbuf);
  918. }
  919. seg_info->frag_cnt = i;
  920. seg_info->total_len = total_len;
  921. seg_info->next = NULL;
  922. sg_info->curr_seg = seg_info;
  923. msdu_info->frm_type = dp_tx_frm_raw;
  924. msdu_info->num_seg = 1;
  925. return nbuf;
  926. error:
  927. i = 0;
  928. while (nbuf) {
  929. curr_nbuf = nbuf;
  930. if (i < mapped_buf_num) {
  931. qdf_nbuf_unmap_nbytes_single(vdev->osdev, curr_nbuf,
  932. QDF_DMA_TO_DEVICE,
  933. curr_nbuf->len);
  934. i++;
  935. }
  936. nbuf = qdf_nbuf_next(nbuf);
  937. qdf_nbuf_free(curr_nbuf);
  938. }
  939. return NULL;
  940. }
  941. /**
  942. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  943. * @soc: DP soc handle
  944. * @nbuf: Buffer pointer
  945. *
  946. * unmap the chain of nbufs that belong to this RAW frame.
  947. *
  948. * Return: None
  949. */
  950. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  951. qdf_nbuf_t nbuf)
  952. {
  953. qdf_nbuf_t cur_nbuf = nbuf;
  954. do {
  955. qdf_nbuf_unmap_nbytes_single(soc->osdev, cur_nbuf,
  956. QDF_DMA_TO_DEVICE,
  957. cur_nbuf->len);
  958. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  959. } while (cur_nbuf);
  960. }
  961. #ifdef VDEV_PEER_PROTOCOL_COUNT
  962. #define dp_vdev_peer_stats_update_protocol_cnt_tx(vdev_hdl, nbuf) \
  963. { \
  964. qdf_nbuf_t nbuf_local; \
  965. struct dp_vdev *vdev_local = vdev_hdl; \
  966. do { \
  967. if (qdf_likely(!((vdev_local)->peer_protocol_count_track))) \
  968. break; \
  969. nbuf_local = nbuf; \
  970. if (qdf_unlikely(((vdev_local)->tx_encap_type) == \
  971. htt_cmn_pkt_type_raw)) \
  972. break; \
  973. else if (qdf_unlikely(qdf_nbuf_is_nonlinear((nbuf_local)))) \
  974. break; \
  975. else if (qdf_nbuf_is_tso((nbuf_local))) \
  976. break; \
  977. dp_vdev_peer_stats_update_protocol_cnt((vdev_local), \
  978. (nbuf_local), \
  979. NULL, 1, 0); \
  980. } while (0); \
  981. }
  982. #else
  983. #define dp_vdev_peer_stats_update_protocol_cnt_tx(vdev_hdl, skb)
  984. #endif
  985. /**
  986. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  987. * @soc: DP Soc Handle
  988. * @vdev: DP vdev handle
  989. * @tx_desc: Tx Descriptor Handle
  990. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  991. * @fw_metadata: Metadata to send to Target Firmware along with frame
  992. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  993. * @tx_exc_metadata: Handle that holds exception path meta data
  994. *
  995. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  996. * from software Tx descriptor
  997. *
  998. * Return: QDF_STATUS_SUCCESS: success
  999. * QDF_STATUS_E_RESOURCES: Error return
  1000. */
  1001. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  1002. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  1003. uint16_t fw_metadata, uint8_t ring_id,
  1004. struct cdp_tx_exception_metadata
  1005. *tx_exc_metadata)
  1006. {
  1007. uint8_t type;
  1008. void *hal_tx_desc;
  1009. uint32_t *hal_tx_desc_cached;
  1010. /*
  1011. * Setting it initialization statically here to avoid
  1012. * a memset call jump with qdf_mem_set call
  1013. */
  1014. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES] = { 0 };
  1015. enum cdp_sec_type sec_type = ((tx_exc_metadata &&
  1016. tx_exc_metadata->sec_type != CDP_INVALID_SEC_TYPE) ?
  1017. tx_exc_metadata->sec_type : vdev->sec_type);
  1018. /* Return Buffer Manager ID */
  1019. uint8_t bm_id = dp_tx_get_rbm_id(soc, ring_id);
  1020. hal_ring_handle_t hal_ring_hdl = NULL;
  1021. QDF_STATUS status = QDF_STATUS_E_RESOURCES;
  1022. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id)) {
  1023. dp_err_rl("Invalid tx desc id:%d", tx_desc->id);
  1024. return QDF_STATUS_E_RESOURCES;
  1025. }
  1026. hal_tx_desc_cached = (void *) cached_desc;
  1027. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  1028. tx_desc->length = HAL_TX_EXT_DESC_WITH_META_DATA;
  1029. type = HAL_TX_BUF_TYPE_EXT_DESC;
  1030. tx_desc->dma_addr = tx_desc->msdu_ext_desc->paddr;
  1031. } else {
  1032. tx_desc->length = qdf_nbuf_len(tx_desc->nbuf) -
  1033. tx_desc->pkt_offset;
  1034. type = HAL_TX_BUF_TYPE_BUFFER;
  1035. tx_desc->dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  1036. }
  1037. qdf_assert_always(tx_desc->dma_addr);
  1038. hal_tx_desc_set_buf_addr(soc->hal_soc, hal_tx_desc_cached,
  1039. tx_desc->dma_addr, bm_id, tx_desc->id,
  1040. type);
  1041. hal_tx_desc_set_lmac_id(soc->hal_soc, hal_tx_desc_cached,
  1042. vdev->lmac_id);
  1043. hal_tx_desc_set_search_type(soc->hal_soc, hal_tx_desc_cached,
  1044. vdev->search_type);
  1045. hal_tx_desc_set_search_index(soc->hal_soc, hal_tx_desc_cached,
  1046. vdev->bss_ast_idx);
  1047. hal_tx_desc_set_dscp_tid_table_id(soc->hal_soc, hal_tx_desc_cached,
  1048. vdev->dscp_tid_map_id);
  1049. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  1050. sec_type_map[sec_type]);
  1051. hal_tx_desc_set_cache_set_num(soc->hal_soc, hal_tx_desc_cached,
  1052. (vdev->bss_ast_hash & 0xF));
  1053. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  1054. hal_tx_desc_set_buf_length(hal_tx_desc_cached, tx_desc->length);
  1055. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  1056. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  1057. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  1058. vdev->hal_desc_addr_search_flags);
  1059. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  1060. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  1061. /* verify checksum offload configuration*/
  1062. if ((wlan_cfg_get_checksum_offload(soc->wlan_cfg_ctx)) &&
  1063. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  1064. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  1065. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  1066. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  1067. }
  1068. if (tid != HTT_TX_EXT_TID_INVALID)
  1069. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  1070. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  1071. hal_tx_desc_set_mesh_en(soc->hal_soc, hal_tx_desc_cached, 1);
  1072. if (qdf_unlikely(vdev->pdev->delay_stats_flag))
  1073. tx_desc->timestamp = qdf_ktime_to_ms(qdf_ktime_get());
  1074. dp_verbose_debug("length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  1075. tx_desc->length, type, (uint64_t)tx_desc->dma_addr,
  1076. tx_desc->pkt_offset, tx_desc->id);
  1077. hal_ring_hdl = dp_tx_get_hal_ring_hdl(soc, ring_id);
  1078. if (qdf_unlikely(dp_tx_hal_ring_access_start(soc, hal_ring_hdl))) {
  1079. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1080. "%s %d : HAL RING Access Failed -- %pK",
  1081. __func__, __LINE__, hal_ring_hdl);
  1082. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  1083. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  1084. return status;
  1085. }
  1086. /* Sync cached descriptor with HW */
  1087. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_ring_hdl);
  1088. if (qdf_unlikely(!hal_tx_desc)) {
  1089. dp_verbose_debug("TCL ring full ring_id:%d", ring_id);
  1090. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  1091. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  1092. goto ring_access_fail;
  1093. }
  1094. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  1095. dp_vdev_peer_stats_update_protocol_cnt_tx(vdev, tx_desc->nbuf);
  1096. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  1097. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, tx_desc->length);
  1098. status = QDF_STATUS_SUCCESS;
  1099. ring_access_fail:
  1100. if (hif_pm_runtime_get(soc->hif_handle,
  1101. RTPM_ID_DW_TX_HW_ENQUEUE) == 0) {
  1102. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1103. hif_pm_runtime_put(soc->hif_handle,
  1104. RTPM_ID_DW_TX_HW_ENQUEUE);
  1105. } else {
  1106. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1107. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1108. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1109. }
  1110. return status;
  1111. }
  1112. /**
  1113. * dp_cce_classify() - Classify the frame based on CCE rules
  1114. * @vdev: DP vdev handle
  1115. * @nbuf: skb
  1116. *
  1117. * Classify frames based on CCE rules
  1118. * Return: bool( true if classified,
  1119. * else false)
  1120. */
  1121. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  1122. {
  1123. qdf_ether_header_t *eh = NULL;
  1124. uint16_t ether_type;
  1125. qdf_llc_t *llcHdr;
  1126. qdf_nbuf_t nbuf_clone = NULL;
  1127. qdf_dot3_qosframe_t *qos_wh = NULL;
  1128. /* for mesh packets don't do any classification */
  1129. if (qdf_unlikely(vdev->mesh_vdev))
  1130. return false;
  1131. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1132. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1133. ether_type = eh->ether_type;
  1134. llcHdr = (qdf_llc_t *)(nbuf->data +
  1135. sizeof(qdf_ether_header_t));
  1136. } else {
  1137. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1138. /* For encrypted packets don't do any classification */
  1139. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  1140. return false;
  1141. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  1142. if (qdf_unlikely(
  1143. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  1144. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  1145. ether_type = *(uint16_t *)(nbuf->data
  1146. + QDF_IEEE80211_4ADDR_HDR_LEN
  1147. + sizeof(qdf_llc_t)
  1148. - sizeof(ether_type));
  1149. llcHdr = (qdf_llc_t *)(nbuf->data +
  1150. QDF_IEEE80211_4ADDR_HDR_LEN);
  1151. } else {
  1152. ether_type = *(uint16_t *)(nbuf->data
  1153. + QDF_IEEE80211_3ADDR_HDR_LEN
  1154. + sizeof(qdf_llc_t)
  1155. - sizeof(ether_type));
  1156. llcHdr = (qdf_llc_t *)(nbuf->data +
  1157. QDF_IEEE80211_3ADDR_HDR_LEN);
  1158. }
  1159. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  1160. && (ether_type ==
  1161. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  1162. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  1163. return true;
  1164. }
  1165. }
  1166. return false;
  1167. }
  1168. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  1169. ether_type = *(uint16_t *)(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1170. sizeof(*llcHdr));
  1171. nbuf_clone = qdf_nbuf_clone(nbuf);
  1172. if (qdf_unlikely(nbuf_clone)) {
  1173. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  1174. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1175. qdf_nbuf_pull_head(nbuf_clone,
  1176. sizeof(qdf_net_vlanhdr_t));
  1177. }
  1178. }
  1179. } else {
  1180. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1181. nbuf_clone = qdf_nbuf_clone(nbuf);
  1182. if (qdf_unlikely(nbuf_clone)) {
  1183. qdf_nbuf_pull_head(nbuf_clone,
  1184. sizeof(qdf_net_vlanhdr_t));
  1185. }
  1186. }
  1187. }
  1188. if (qdf_unlikely(nbuf_clone))
  1189. nbuf = nbuf_clone;
  1190. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  1191. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  1192. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  1193. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  1194. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  1195. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  1196. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  1197. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  1198. if (qdf_unlikely(nbuf_clone))
  1199. qdf_nbuf_free(nbuf_clone);
  1200. return true;
  1201. }
  1202. if (qdf_unlikely(nbuf_clone))
  1203. qdf_nbuf_free(nbuf_clone);
  1204. return false;
  1205. }
  1206. /**
  1207. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1208. * @vdev: DP vdev handle
  1209. * @nbuf: skb
  1210. *
  1211. * Extract the DSCP or PCP information from frame and map into TID value.
  1212. *
  1213. * Return: void
  1214. */
  1215. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1216. struct dp_tx_msdu_info_s *msdu_info)
  1217. {
  1218. uint8_t tos = 0, dscp_tid_override = 0;
  1219. uint8_t *hdr_ptr, *L3datap;
  1220. uint8_t is_mcast = 0;
  1221. qdf_ether_header_t *eh = NULL;
  1222. qdf_ethervlan_header_t *evh = NULL;
  1223. uint16_t ether_type;
  1224. qdf_llc_t *llcHdr;
  1225. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1226. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1227. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1228. eh = (qdf_ether_header_t *)nbuf->data;
  1229. hdr_ptr = eh->ether_dhost;
  1230. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1231. } else {
  1232. qdf_dot3_qosframe_t *qos_wh =
  1233. (qdf_dot3_qosframe_t *) nbuf->data;
  1234. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1235. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1236. return;
  1237. }
  1238. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1239. ether_type = eh->ether_type;
  1240. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1241. /*
  1242. * Check if packet is dot3 or eth2 type.
  1243. */
  1244. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1245. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1246. sizeof(*llcHdr));
  1247. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1248. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1249. sizeof(*llcHdr);
  1250. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1251. + sizeof(*llcHdr) +
  1252. sizeof(qdf_net_vlanhdr_t));
  1253. } else {
  1254. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1255. sizeof(*llcHdr);
  1256. }
  1257. } else {
  1258. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1259. evh = (qdf_ethervlan_header_t *) eh;
  1260. ether_type = evh->ether_type;
  1261. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1262. }
  1263. }
  1264. /*
  1265. * Find priority from IP TOS DSCP field
  1266. */
  1267. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1268. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1269. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1270. /* Only for unicast frames */
  1271. if (!is_mcast) {
  1272. /* send it on VO queue */
  1273. msdu_info->tid = DP_VO_TID;
  1274. }
  1275. } else {
  1276. /*
  1277. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1278. * from TOS byte.
  1279. */
  1280. tos = ip->ip_tos;
  1281. dscp_tid_override = 1;
  1282. }
  1283. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1284. /* TODO
  1285. * use flowlabel
  1286. *igmpmld cases to be handled in phase 2
  1287. */
  1288. unsigned long ver_pri_flowlabel;
  1289. unsigned long pri;
  1290. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1291. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1292. DP_IPV6_PRIORITY_SHIFT;
  1293. tos = pri;
  1294. dscp_tid_override = 1;
  1295. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1296. msdu_info->tid = DP_VO_TID;
  1297. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1298. /* Only for unicast frames */
  1299. if (!is_mcast) {
  1300. /* send ucast arp on VO queue */
  1301. msdu_info->tid = DP_VO_TID;
  1302. }
  1303. }
  1304. /*
  1305. * Assign all MCAST packets to BE
  1306. */
  1307. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1308. if (is_mcast) {
  1309. tos = 0;
  1310. dscp_tid_override = 1;
  1311. }
  1312. }
  1313. if (dscp_tid_override == 1) {
  1314. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1315. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1316. }
  1317. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1318. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1319. return;
  1320. }
  1321. /**
  1322. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1323. * @vdev: DP vdev handle
  1324. * @nbuf: skb
  1325. *
  1326. * Software based TID classification is required when more than 2 DSCP-TID
  1327. * mapping tables are needed.
  1328. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1329. *
  1330. * Return: void
  1331. */
  1332. static inline void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1333. struct dp_tx_msdu_info_s *msdu_info)
  1334. {
  1335. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1336. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1337. if (pdev->soc && vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map)
  1338. return;
  1339. /* for mesh packets don't do any classification */
  1340. if (qdf_unlikely(vdev->mesh_vdev))
  1341. return;
  1342. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1343. }
  1344. #ifdef FEATURE_WLAN_TDLS
  1345. /**
  1346. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1347. * @tx_desc: TX descriptor
  1348. *
  1349. * Return: None
  1350. */
  1351. static void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1352. {
  1353. if (tx_desc->vdev) {
  1354. if (tx_desc->vdev->is_tdls_frame) {
  1355. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1356. tx_desc->vdev->is_tdls_frame = false;
  1357. }
  1358. }
  1359. }
  1360. /**
  1361. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1362. * @soc: dp_soc handle
  1363. * @tx_desc: TX descriptor
  1364. * @vdev: datapath vdev handle
  1365. *
  1366. * Return: None
  1367. */
  1368. static void dp_non_std_tx_comp_free_buff(struct dp_soc *soc,
  1369. struct dp_tx_desc_s *tx_desc,
  1370. struct dp_vdev *vdev)
  1371. {
  1372. struct hal_tx_completion_status ts = {0};
  1373. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1374. if (qdf_unlikely(!vdev)) {
  1375. dp_err_rl("vdev is null!");
  1376. goto error;
  1377. }
  1378. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  1379. if (vdev->tx_non_std_data_callback.func) {
  1380. qdf_nbuf_set_next(nbuf, NULL);
  1381. vdev->tx_non_std_data_callback.func(
  1382. vdev->tx_non_std_data_callback.ctxt,
  1383. nbuf, ts.status);
  1384. return;
  1385. } else {
  1386. dp_err_rl("callback func is null");
  1387. }
  1388. error:
  1389. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1390. qdf_nbuf_free(nbuf);
  1391. }
  1392. /**
  1393. * dp_tx_msdu_single_map() - do nbuf map
  1394. * @vdev: DP vdev handle
  1395. * @tx_desc: DP TX descriptor pointer
  1396. * @nbuf: skb pointer
  1397. *
  1398. * For TDLS frame, use qdf_nbuf_map_single() to align with the unmap
  1399. * operation done in other component.
  1400. *
  1401. * Return: QDF_STATUS
  1402. */
  1403. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1404. struct dp_tx_desc_s *tx_desc,
  1405. qdf_nbuf_t nbuf)
  1406. {
  1407. if (qdf_likely(!(tx_desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)))
  1408. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1409. nbuf,
  1410. QDF_DMA_TO_DEVICE,
  1411. nbuf->len);
  1412. else
  1413. return qdf_nbuf_map_single(vdev->osdev, nbuf,
  1414. QDF_DMA_TO_DEVICE);
  1415. }
  1416. #else
  1417. static inline void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1418. {
  1419. }
  1420. static inline void dp_non_std_tx_comp_free_buff(struct dp_soc *soc,
  1421. struct dp_tx_desc_s *tx_desc,
  1422. struct dp_vdev *vdev)
  1423. {
  1424. }
  1425. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1426. struct dp_tx_desc_s *tx_desc,
  1427. qdf_nbuf_t nbuf)
  1428. {
  1429. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1430. nbuf,
  1431. QDF_DMA_TO_DEVICE,
  1432. nbuf->len);
  1433. }
  1434. #endif
  1435. /**
  1436. * dp_tx_frame_is_drop() - checks if the packet is loopback
  1437. * @vdev: DP vdev handle
  1438. * @nbuf: skb
  1439. *
  1440. * Return: 1 if frame needs to be dropped else 0
  1441. */
  1442. int dp_tx_frame_is_drop(struct dp_vdev *vdev, uint8_t *srcmac, uint8_t *dstmac)
  1443. {
  1444. struct dp_pdev *pdev = NULL;
  1445. struct dp_ast_entry *src_ast_entry = NULL;
  1446. struct dp_ast_entry *dst_ast_entry = NULL;
  1447. struct dp_soc *soc = NULL;
  1448. qdf_assert(vdev);
  1449. pdev = vdev->pdev;
  1450. qdf_assert(pdev);
  1451. soc = pdev->soc;
  1452. dst_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1453. (soc, dstmac, vdev->pdev->pdev_id);
  1454. src_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1455. (soc, srcmac, vdev->pdev->pdev_id);
  1456. if (dst_ast_entry && src_ast_entry) {
  1457. if (dst_ast_entry->peer->peer_id ==
  1458. src_ast_entry->peer->peer_id)
  1459. return 1;
  1460. }
  1461. return 0;
  1462. }
  1463. /**
  1464. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1465. * @vdev: DP vdev handle
  1466. * @nbuf: skb
  1467. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1468. * @meta_data: Metadata to the fw
  1469. * @tx_q: Tx queue to be used for this Tx frame
  1470. * @peer_id: peer_id of the peer in case of NAWDS frames
  1471. * @tx_exc_metadata: Handle that holds exception path metadata
  1472. *
  1473. * Return: NULL on success,
  1474. * nbuf when it fails to send
  1475. */
  1476. qdf_nbuf_t
  1477. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1478. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1479. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1480. {
  1481. struct dp_pdev *pdev = vdev->pdev;
  1482. struct dp_soc *soc = pdev->soc;
  1483. struct dp_tx_desc_s *tx_desc;
  1484. QDF_STATUS status;
  1485. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1486. uint16_t htt_tcl_metadata = 0;
  1487. enum cdp_tx_sw_drop drop_code = TX_MAX_DROP;
  1488. uint8_t tid = msdu_info->tid;
  1489. struct cdp_tid_tx_stats *tid_stats = NULL;
  1490. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1491. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1492. msdu_info, tx_exc_metadata);
  1493. if (!tx_desc) {
  1494. dp_err_rl("Tx_desc prepare Fail vdev %pK queue %d",
  1495. vdev, tx_q->desc_pool_id);
  1496. drop_code = TX_DESC_ERR;
  1497. goto fail_return;
  1498. }
  1499. if (qdf_unlikely(soc->cce_disable)) {
  1500. if (dp_cce_classify(vdev, nbuf) == true) {
  1501. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1502. tid = DP_VO_TID;
  1503. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1504. }
  1505. }
  1506. dp_tx_update_tdls_flags(tx_desc);
  1507. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1508. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1509. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1510. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1511. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1512. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1513. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1514. peer_id);
  1515. } else
  1516. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1517. if (msdu_info->exception_fw)
  1518. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1519. dp_tx_desc_update_fast_comp_flag(soc, tx_desc,
  1520. !pdev->enhanced_stats_en);
  1521. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  1522. dp_tx_msdu_single_map(vdev, tx_desc, nbuf))) {
  1523. /* Handle failure */
  1524. dp_err("qdf_nbuf_map failed");
  1525. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  1526. drop_code = TX_DMA_MAP_ERR;
  1527. goto release_desc;
  1528. }
  1529. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1530. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  1531. htt_tcl_metadata, tx_q->ring_id, tx_exc_metadata);
  1532. if (status != QDF_STATUS_SUCCESS) {
  1533. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1534. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1535. __func__, tx_desc, tx_q->ring_id);
  1536. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  1537. QDF_DMA_TO_DEVICE,
  1538. nbuf->len);
  1539. drop_code = TX_HW_ENQUEUE;
  1540. goto release_desc;
  1541. }
  1542. return NULL;
  1543. release_desc:
  1544. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1545. fail_return:
  1546. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1547. tid_stats = &pdev->stats.tid_stats.
  1548. tid_tx_stats[tx_q->ring_id][tid];
  1549. tid_stats->swdrop_cnt[drop_code]++;
  1550. return nbuf;
  1551. }
  1552. /**
  1553. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1554. * @vdev: DP vdev handle
  1555. * @nbuf: skb
  1556. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1557. *
  1558. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1559. *
  1560. * Return: NULL on success,
  1561. * nbuf when it fails to send
  1562. */
  1563. #if QDF_LOCK_STATS
  1564. noinline
  1565. #else
  1566. #endif
  1567. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1568. struct dp_tx_msdu_info_s *msdu_info)
  1569. {
  1570. uint8_t i;
  1571. struct dp_pdev *pdev = vdev->pdev;
  1572. struct dp_soc *soc = pdev->soc;
  1573. struct dp_tx_desc_s *tx_desc;
  1574. bool is_cce_classified = false;
  1575. QDF_STATUS status;
  1576. uint16_t htt_tcl_metadata = 0;
  1577. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1578. struct cdp_tid_tx_stats *tid_stats = NULL;
  1579. if (qdf_unlikely(soc->cce_disable)) {
  1580. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1581. if (is_cce_classified) {
  1582. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1583. msdu_info->tid = DP_VO_TID;
  1584. }
  1585. }
  1586. if (msdu_info->frm_type == dp_tx_frm_me)
  1587. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1588. i = 0;
  1589. /* Print statement to track i and num_seg */
  1590. /*
  1591. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1592. * descriptors using information in msdu_info
  1593. */
  1594. while (i < msdu_info->num_seg) {
  1595. /*
  1596. * Setup Tx descriptor for an MSDU, and MSDU extension
  1597. * descriptor
  1598. */
  1599. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1600. tx_q->desc_pool_id);
  1601. if (!tx_desc) {
  1602. if (msdu_info->frm_type == dp_tx_frm_me) {
  1603. dp_tx_me_free_buf(pdev,
  1604. (void *)(msdu_info->u.sg_info
  1605. .curr_seg->frags[0].vaddr));
  1606. i++;
  1607. continue;
  1608. }
  1609. goto done;
  1610. }
  1611. if (msdu_info->frm_type == dp_tx_frm_me) {
  1612. tx_desc->me_buffer =
  1613. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1614. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1615. }
  1616. if (is_cce_classified)
  1617. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1618. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1619. if (msdu_info->exception_fw) {
  1620. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1621. }
  1622. /*
  1623. * Enqueue the Tx MSDU descriptor to HW for transmit
  1624. */
  1625. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  1626. htt_tcl_metadata, tx_q->ring_id, NULL);
  1627. if (status != QDF_STATUS_SUCCESS) {
  1628. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1629. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1630. __func__, tx_desc, tx_q->ring_id);
  1631. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1632. tid_stats = &pdev->stats.tid_stats.
  1633. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1634. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1635. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1636. if (msdu_info->frm_type == dp_tx_frm_me) {
  1637. i++;
  1638. continue;
  1639. }
  1640. goto done;
  1641. }
  1642. /*
  1643. * TODO
  1644. * if tso_info structure can be modified to have curr_seg
  1645. * as first element, following 2 blocks of code (for TSO and SG)
  1646. * can be combined into 1
  1647. */
  1648. /*
  1649. * For frames with multiple segments (TSO, ME), jump to next
  1650. * segment.
  1651. */
  1652. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1653. if (msdu_info->u.tso_info.curr_seg->next) {
  1654. msdu_info->u.tso_info.curr_seg =
  1655. msdu_info->u.tso_info.curr_seg->next;
  1656. /*
  1657. * If this is a jumbo nbuf, then increment the number of
  1658. * nbuf users for each additional segment of the msdu.
  1659. * This will ensure that the skb is freed only after
  1660. * receiving tx completion for all segments of an nbuf
  1661. */
  1662. qdf_nbuf_inc_users(nbuf);
  1663. /* Check with MCL if this is needed */
  1664. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1665. }
  1666. }
  1667. /*
  1668. * For Multicast-Unicast converted packets,
  1669. * each converted frame (for a client) is represented as
  1670. * 1 segment
  1671. */
  1672. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1673. (msdu_info->frm_type == dp_tx_frm_me)) {
  1674. if (msdu_info->u.sg_info.curr_seg->next) {
  1675. msdu_info->u.sg_info.curr_seg =
  1676. msdu_info->u.sg_info.curr_seg->next;
  1677. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1678. }
  1679. }
  1680. i++;
  1681. }
  1682. nbuf = NULL;
  1683. done:
  1684. return nbuf;
  1685. }
  1686. /**
  1687. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1688. * for SG frames
  1689. * @vdev: DP vdev handle
  1690. * @nbuf: skb
  1691. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1692. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1693. *
  1694. * Return: NULL on success,
  1695. * nbuf when it fails to send
  1696. */
  1697. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1698. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1699. {
  1700. uint32_t cur_frag, nr_frags;
  1701. qdf_dma_addr_t paddr;
  1702. struct dp_tx_sg_info_s *sg_info;
  1703. sg_info = &msdu_info->u.sg_info;
  1704. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1705. if (QDF_STATUS_SUCCESS !=
  1706. qdf_nbuf_map_nbytes_single(vdev->osdev, nbuf,
  1707. QDF_DMA_TO_DEVICE, nbuf->len)) {
  1708. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1709. "dma map error");
  1710. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1711. qdf_nbuf_free(nbuf);
  1712. return NULL;
  1713. }
  1714. paddr = qdf_nbuf_mapped_paddr_get(nbuf);
  1715. seg_info->frags[0].paddr_lo = paddr;
  1716. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  1717. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1718. seg_info->frags[0].vaddr = (void *) nbuf;
  1719. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1720. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1721. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1722. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1723. "frag dma map error");
  1724. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1725. qdf_nbuf_free(nbuf);
  1726. return NULL;
  1727. }
  1728. paddr = qdf_nbuf_get_tx_frag_paddr(nbuf);
  1729. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1730. seg_info->frags[cur_frag + 1].paddr_hi =
  1731. ((uint64_t) paddr) >> 32;
  1732. seg_info->frags[cur_frag + 1].len =
  1733. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1734. }
  1735. seg_info->frag_cnt = (cur_frag + 1);
  1736. seg_info->total_len = qdf_nbuf_len(nbuf);
  1737. seg_info->next = NULL;
  1738. sg_info->curr_seg = seg_info;
  1739. msdu_info->frm_type = dp_tx_frm_sg;
  1740. msdu_info->num_seg = 1;
  1741. return nbuf;
  1742. }
  1743. /**
  1744. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  1745. * @vdev: DP vdev handle
  1746. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1747. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  1748. *
  1749. * Return: NULL on failure,
  1750. * nbuf when extracted successfully
  1751. */
  1752. static
  1753. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  1754. struct dp_tx_msdu_info_s *msdu_info,
  1755. uint16_t ppdu_cookie)
  1756. {
  1757. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1758. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1759. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1760. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  1761. (msdu_info->meta_data[5], 1);
  1762. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  1763. (msdu_info->meta_data[5], 1);
  1764. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  1765. (msdu_info->meta_data[6], ppdu_cookie);
  1766. msdu_info->exception_fw = 1;
  1767. msdu_info->is_tx_sniffer = 1;
  1768. }
  1769. #ifdef MESH_MODE_SUPPORT
  1770. /**
  1771. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1772. and prepare msdu_info for mesh frames.
  1773. * @vdev: DP vdev handle
  1774. * @nbuf: skb
  1775. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1776. *
  1777. * Return: NULL on failure,
  1778. * nbuf when extracted successfully
  1779. */
  1780. static
  1781. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1782. struct dp_tx_msdu_info_s *msdu_info)
  1783. {
  1784. struct meta_hdr_s *mhdr;
  1785. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1786. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1787. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1788. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  1789. msdu_info->exception_fw = 0;
  1790. goto remove_meta_hdr;
  1791. }
  1792. msdu_info->exception_fw = 1;
  1793. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1794. meta_data->host_tx_desc_pool = 1;
  1795. meta_data->update_peer_cache = 1;
  1796. meta_data->learning_frame = 1;
  1797. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1798. meta_data->power = mhdr->power;
  1799. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1800. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1801. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1802. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1803. meta_data->dyn_bw = 1;
  1804. meta_data->valid_pwr = 1;
  1805. meta_data->valid_mcs_mask = 1;
  1806. meta_data->valid_nss_mask = 1;
  1807. meta_data->valid_preamble_type = 1;
  1808. meta_data->valid_retries = 1;
  1809. meta_data->valid_bw_info = 1;
  1810. }
  1811. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1812. meta_data->encrypt_type = 0;
  1813. meta_data->valid_encrypt_type = 1;
  1814. meta_data->learning_frame = 0;
  1815. }
  1816. meta_data->valid_key_flags = 1;
  1817. meta_data->key_flags = (mhdr->keyix & 0x3);
  1818. remove_meta_hdr:
  1819. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1820. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1821. "qdf_nbuf_pull_head failed");
  1822. qdf_nbuf_free(nbuf);
  1823. return NULL;
  1824. }
  1825. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1826. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1827. "%s , Meta hdr %0x %0x %0x %0x %0x %0x"
  1828. " tid %d to_fw %d",
  1829. __func__, msdu_info->meta_data[0],
  1830. msdu_info->meta_data[1],
  1831. msdu_info->meta_data[2],
  1832. msdu_info->meta_data[3],
  1833. msdu_info->meta_data[4],
  1834. msdu_info->meta_data[5],
  1835. msdu_info->tid, msdu_info->exception_fw);
  1836. return nbuf;
  1837. }
  1838. #else
  1839. static
  1840. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1841. struct dp_tx_msdu_info_s *msdu_info)
  1842. {
  1843. return nbuf;
  1844. }
  1845. #endif
  1846. /**
  1847. * dp_check_exc_metadata() - Checks if parameters are valid
  1848. * @tx_exc - holds all exception path parameters
  1849. *
  1850. * Returns true when all the parameters are valid else false
  1851. *
  1852. */
  1853. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  1854. {
  1855. bool invalid_tid = (tx_exc->tid > DP_MAX_TIDS && tx_exc->tid !=
  1856. HTT_INVALID_TID);
  1857. bool invalid_encap_type =
  1858. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  1859. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  1860. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  1861. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  1862. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  1863. tx_exc->ppdu_cookie == 0);
  1864. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  1865. invalid_cookie) {
  1866. return false;
  1867. }
  1868. return true;
  1869. }
  1870. /**
  1871. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  1872. * @soc: DP soc handle
  1873. * @vdev_id: id of DP vdev handle
  1874. * @nbuf: skb
  1875. * @tx_exc_metadata: Handle that holds exception path meta data
  1876. *
  1877. * Entry point for Core Tx layer (DP_TX) invoked from
  1878. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  1879. *
  1880. * Return: NULL on success,
  1881. * nbuf when it fails to send
  1882. */
  1883. qdf_nbuf_t
  1884. dp_tx_send_exception(struct cdp_soc_t *soc, uint8_t vdev_id, qdf_nbuf_t nbuf,
  1885. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1886. {
  1887. qdf_ether_header_t *eh = NULL;
  1888. struct dp_tx_msdu_info_s msdu_info;
  1889. struct dp_vdev *vdev =
  1890. dp_get_vdev_from_soc_vdev_id_wifi3((struct dp_soc *)soc,
  1891. vdev_id);
  1892. if (qdf_unlikely(!vdev))
  1893. goto fail;
  1894. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1895. if (!tx_exc_metadata)
  1896. goto fail;
  1897. msdu_info.tid = tx_exc_metadata->tid;
  1898. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1899. dp_verbose_debug("skb %pM", nbuf->data);
  1900. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1901. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  1902. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1903. "Invalid parameters in exception path");
  1904. goto fail;
  1905. }
  1906. /* Basic sanity checks for unsupported packets */
  1907. /* MESH mode */
  1908. if (qdf_unlikely(vdev->mesh_vdev)) {
  1909. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1910. "Mesh mode is not supported in exception path");
  1911. goto fail;
  1912. }
  1913. /* TSO or SG */
  1914. if (qdf_unlikely(qdf_nbuf_is_tso(nbuf)) ||
  1915. qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1916. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1917. "TSO and SG are not supported in exception path");
  1918. goto fail;
  1919. }
  1920. /* RAW */
  1921. if (qdf_unlikely(tx_exc_metadata->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1922. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1923. "Raw frame is not supported in exception path");
  1924. goto fail;
  1925. }
  1926. /* Mcast enhancement*/
  1927. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1928. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  1929. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  1930. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1931. "Ignoring mcast_enhancement_en which is set and sending the mcast packet to the FW");
  1932. }
  1933. }
  1934. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  1935. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  1936. qdf_nbuf_len(nbuf));
  1937. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  1938. tx_exc_metadata->ppdu_cookie);
  1939. }
  1940. /*
  1941. * Get HW Queue to use for this frame.
  1942. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1943. * dedicated for data and 1 for command.
  1944. * "queue_id" maps to one hardware ring.
  1945. * With each ring, we also associate a unique Tx descriptor pool
  1946. * to minimize lock contention for these resources.
  1947. */
  1948. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1949. /*
  1950. * Check exception descriptors
  1951. */
  1952. if (dp_tx_exception_limit_check(vdev))
  1953. goto fail;
  1954. /* Single linear frame */
  1955. /*
  1956. * If nbuf is a simple linear frame, use send_single function to
  1957. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1958. * SRNG. There is no need to setup a MSDU extension descriptor.
  1959. */
  1960. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  1961. tx_exc_metadata->peer_id, tx_exc_metadata);
  1962. return nbuf;
  1963. fail:
  1964. dp_verbose_debug("pkt send failed");
  1965. return nbuf;
  1966. }
  1967. /**
  1968. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  1969. * @soc: DP soc handle
  1970. * @vdev_id: DP vdev handle
  1971. * @nbuf: skb
  1972. *
  1973. * Entry point for Core Tx layer (DP_TX) invoked from
  1974. * hard_start_xmit in OSIF/HDD
  1975. *
  1976. * Return: NULL on success,
  1977. * nbuf when it fails to send
  1978. */
  1979. #ifdef MESH_MODE_SUPPORT
  1980. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc, uint8_t vdev_id,
  1981. qdf_nbuf_t nbuf)
  1982. {
  1983. struct meta_hdr_s *mhdr;
  1984. qdf_nbuf_t nbuf_mesh = NULL;
  1985. qdf_nbuf_t nbuf_clone = NULL;
  1986. struct dp_vdev *vdev;
  1987. uint8_t no_enc_frame = 0;
  1988. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  1989. if (!nbuf_mesh) {
  1990. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1991. "qdf_nbuf_unshare failed");
  1992. return nbuf;
  1993. }
  1994. vdev = dp_get_vdev_from_soc_vdev_id_wifi3((struct dp_soc *)soc,
  1995. vdev_id);
  1996. if (!vdev) {
  1997. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1998. "vdev is NULL for vdev_id %d", vdev_id);
  1999. return nbuf;
  2000. }
  2001. nbuf = nbuf_mesh;
  2002. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2003. if ((vdev->sec_type != cdp_sec_type_none) &&
  2004. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  2005. no_enc_frame = 1;
  2006. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  2007. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  2008. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  2009. !no_enc_frame) {
  2010. nbuf_clone = qdf_nbuf_clone(nbuf);
  2011. if (!nbuf_clone) {
  2012. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2013. "qdf_nbuf_clone failed");
  2014. return nbuf;
  2015. }
  2016. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  2017. }
  2018. if (nbuf_clone) {
  2019. if (!dp_tx_send(soc, vdev_id, nbuf_clone)) {
  2020. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2021. } else {
  2022. qdf_nbuf_free(nbuf_clone);
  2023. }
  2024. }
  2025. if (no_enc_frame)
  2026. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  2027. else
  2028. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  2029. nbuf = dp_tx_send(soc, vdev_id, nbuf);
  2030. if ((!nbuf) && no_enc_frame) {
  2031. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2032. }
  2033. return nbuf;
  2034. }
  2035. #else
  2036. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc, uint8_t vdev_id,
  2037. qdf_nbuf_t nbuf)
  2038. {
  2039. return dp_tx_send(soc, vdev_id, nbuf);
  2040. }
  2041. #endif
  2042. /**
  2043. * dp_tx_nawds_handler() - NAWDS handler
  2044. *
  2045. * @soc: DP soc handle
  2046. * @vdev_id: id of DP vdev handle
  2047. * @msdu_info: msdu_info required to create HTT metadata
  2048. * @nbuf: skb
  2049. *
  2050. * This API transfers the multicast frames with the peer id
  2051. * on NAWDS enabled peer.
  2052. * Return: none
  2053. */
  2054. static inline
  2055. void dp_tx_nawds_handler(struct cdp_soc_t *soc, struct dp_vdev *vdev,
  2056. struct dp_tx_msdu_info_s *msdu_info, qdf_nbuf_t nbuf)
  2057. {
  2058. struct dp_peer *peer = NULL;
  2059. qdf_nbuf_t nbuf_clone = NULL;
  2060. struct dp_soc *dp_soc = (struct dp_soc *)soc;
  2061. uint16_t peer_id = DP_INVALID_PEER;
  2062. struct dp_peer *sa_peer = NULL;
  2063. struct dp_ast_entry *ast_entry = NULL;
  2064. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2065. if (qdf_nbuf_get_tx_ftype(nbuf) == CB_FTYPE_INTRABSS_FWD) {
  2066. qdf_spin_lock_bh(&dp_soc->ast_lock);
  2067. ast_entry = dp_peer_ast_hash_find_by_pdevid
  2068. (dp_soc,
  2069. (uint8_t *)(eh->ether_shost),
  2070. vdev->pdev->pdev_id);
  2071. if (ast_entry)
  2072. sa_peer = ast_entry->peer;
  2073. qdf_spin_unlock_bh(&dp_soc->ast_lock);
  2074. }
  2075. qdf_spin_lock_bh(&dp_soc->peer_ref_mutex);
  2076. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2077. if (!peer->bss_peer && peer->nawds_enabled) {
  2078. peer_id = peer->peer_id;
  2079. /* Multicast packets needs to be
  2080. * dropped in case of intra bss forwarding
  2081. */
  2082. if (sa_peer == peer) {
  2083. QDF_TRACE(QDF_MODULE_ID_DP,
  2084. QDF_TRACE_LEVEL_DEBUG,
  2085. " %s: multicast packet", __func__);
  2086. DP_STATS_INC(peer, tx.nawds_mcast_drop, 1);
  2087. continue;
  2088. }
  2089. nbuf_clone = qdf_nbuf_clone(nbuf);
  2090. if (!nbuf_clone) {
  2091. QDF_TRACE(QDF_MODULE_ID_DP,
  2092. QDF_TRACE_LEVEL_ERROR,
  2093. FL("nbuf clone failed"));
  2094. break;
  2095. }
  2096. nbuf_clone = dp_tx_send_msdu_single(vdev, nbuf_clone,
  2097. msdu_info, peer_id,
  2098. NULL);
  2099. if (nbuf_clone) {
  2100. QDF_TRACE(QDF_MODULE_ID_DP,
  2101. QDF_TRACE_LEVEL_DEBUG,
  2102. FL("pkt send failed"));
  2103. qdf_nbuf_free(nbuf_clone);
  2104. } else {
  2105. if (peer_id != DP_INVALID_PEER)
  2106. DP_STATS_INC_PKT(peer, tx.nawds_mcast,
  2107. 1, qdf_nbuf_len(nbuf));
  2108. }
  2109. }
  2110. }
  2111. qdf_spin_unlock_bh(&dp_soc->peer_ref_mutex);
  2112. }
  2113. /**
  2114. * dp_tx_send() - Transmit a frame on a given VAP
  2115. * @soc: DP soc handle
  2116. * @vdev_id: id of DP vdev handle
  2117. * @nbuf: skb
  2118. *
  2119. * Entry point for Core Tx layer (DP_TX) invoked from
  2120. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  2121. * cases
  2122. *
  2123. * Return: NULL on success,
  2124. * nbuf when it fails to send
  2125. */
  2126. qdf_nbuf_t dp_tx_send(struct cdp_soc_t *soc, uint8_t vdev_id, qdf_nbuf_t nbuf)
  2127. {
  2128. uint16_t peer_id = HTT_INVALID_PEER;
  2129. /*
  2130. * doing a memzero is causing additional function call overhead
  2131. * so doing static stack clearing
  2132. */
  2133. struct dp_tx_msdu_info_s msdu_info = {0};
  2134. struct dp_vdev *vdev =
  2135. dp_get_vdev_from_soc_vdev_id_wifi3((struct dp_soc *)soc,
  2136. vdev_id);
  2137. if (qdf_unlikely(!vdev))
  2138. return nbuf;
  2139. dp_verbose_debug("skb %pM", nbuf->data);
  2140. /*
  2141. * Set Default Host TID value to invalid TID
  2142. * (TID override disabled)
  2143. */
  2144. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  2145. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2146. if (qdf_unlikely(vdev->mesh_vdev)) {
  2147. qdf_nbuf_t nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  2148. &msdu_info);
  2149. if (!nbuf_mesh) {
  2150. dp_verbose_debug("Extracting mesh metadata failed");
  2151. return nbuf;
  2152. }
  2153. nbuf = nbuf_mesh;
  2154. }
  2155. /*
  2156. * Get HW Queue to use for this frame.
  2157. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2158. * dedicated for data and 1 for command.
  2159. * "queue_id" maps to one hardware ring.
  2160. * With each ring, we also associate a unique Tx descriptor pool
  2161. * to minimize lock contention for these resources.
  2162. */
  2163. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2164. /*
  2165. * TCL H/W supports 2 DSCP-TID mapping tables.
  2166. * Table 1 - Default DSCP-TID mapping table
  2167. * Table 2 - 1 DSCP-TID override table
  2168. *
  2169. * If we need a different DSCP-TID mapping for this vap,
  2170. * call tid_classify to extract DSCP/ToS from frame and
  2171. * map to a TID and store in msdu_info. This is later used
  2172. * to fill in TCL Input descriptor (per-packet TID override).
  2173. */
  2174. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  2175. /*
  2176. * Classify the frame and call corresponding
  2177. * "prepare" function which extracts the segment (TSO)
  2178. * and fragmentation information (for TSO , SG, ME, or Raw)
  2179. * into MSDU_INFO structure which is later used to fill
  2180. * SW and HW descriptors.
  2181. */
  2182. if (qdf_nbuf_is_tso(nbuf)) {
  2183. dp_verbose_debug("TSO frame %pK", vdev);
  2184. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2185. qdf_nbuf_len(nbuf));
  2186. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2187. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2188. qdf_nbuf_len(nbuf));
  2189. return nbuf;
  2190. }
  2191. goto send_multiple;
  2192. }
  2193. /* SG */
  2194. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2195. struct dp_tx_seg_info_s seg_info = {0};
  2196. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2197. if (!nbuf)
  2198. return NULL;
  2199. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2200. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2201. qdf_nbuf_len(nbuf));
  2202. goto send_multiple;
  2203. }
  2204. #ifdef ATH_SUPPORT_IQUE
  2205. /* Mcast to Ucast Conversion*/
  2206. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  2207. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  2208. qdf_nbuf_data(nbuf);
  2209. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2210. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2211. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  2212. DP_STATS_INC_PKT(vdev,
  2213. tx_i.mcast_en.mcast_pkt, 1,
  2214. qdf_nbuf_len(nbuf));
  2215. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  2216. QDF_STATUS_SUCCESS) {
  2217. return NULL;
  2218. }
  2219. }
  2220. }
  2221. #endif
  2222. /* RAW */
  2223. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  2224. struct dp_tx_seg_info_s seg_info = {0};
  2225. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  2226. if (!nbuf)
  2227. return NULL;
  2228. dp_verbose_debug("Raw frame %pK", vdev);
  2229. goto send_multiple;
  2230. }
  2231. if (qdf_unlikely(vdev->nawds_enabled)) {
  2232. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  2233. qdf_nbuf_data(nbuf);
  2234. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost))
  2235. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf);
  2236. peer_id = DP_INVALID_PEER;
  2237. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2238. 1, qdf_nbuf_len(nbuf));
  2239. }
  2240. /* Single linear frame */
  2241. /*
  2242. * If nbuf is a simple linear frame, use send_single function to
  2243. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2244. * SRNG. There is no need to setup a MSDU extension descriptor.
  2245. */
  2246. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  2247. return nbuf;
  2248. send_multiple:
  2249. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2250. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  2251. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  2252. return nbuf;
  2253. }
  2254. /**
  2255. * dp_tx_reinject_handler() - Tx Reinject Handler
  2256. * @tx_desc: software descriptor head pointer
  2257. * @status : Tx completion status from HTT descriptor
  2258. *
  2259. * This function reinjects frames back to Target.
  2260. * Todo - Host queue needs to be added
  2261. *
  2262. * Return: none
  2263. */
  2264. static
  2265. void dp_tx_reinject_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2266. {
  2267. struct dp_vdev *vdev;
  2268. struct dp_peer *peer = NULL;
  2269. uint32_t peer_id = HTT_INVALID_PEER;
  2270. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2271. qdf_nbuf_t nbuf_copy = NULL;
  2272. struct dp_tx_msdu_info_s msdu_info;
  2273. struct dp_soc *soc = NULL;
  2274. #ifdef WDS_VENDOR_EXTENSION
  2275. int is_mcast = 0, is_ucast = 0;
  2276. int num_peers_3addr = 0;
  2277. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  2278. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  2279. #endif
  2280. vdev = tx_desc->vdev;
  2281. soc = vdev->pdev->soc;
  2282. qdf_assert(vdev);
  2283. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2284. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2285. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2286. "%s Tx reinject path", __func__);
  2287. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  2288. qdf_nbuf_len(tx_desc->nbuf));
  2289. #ifdef WDS_VENDOR_EXTENSION
  2290. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  2291. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  2292. } else {
  2293. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  2294. }
  2295. is_ucast = !is_mcast;
  2296. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2297. if (peer->bss_peer)
  2298. continue;
  2299. /* Detect wds peers that use 3-addr framing for mcast.
  2300. * if there are any, the bss_peer is used to send the
  2301. * the mcast frame using 3-addr format. all wds enabled
  2302. * peers that use 4-addr framing for mcast frames will
  2303. * be duplicated and sent as 4-addr frames below.
  2304. */
  2305. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  2306. num_peers_3addr = 1;
  2307. break;
  2308. }
  2309. }
  2310. #endif
  2311. if (qdf_unlikely(vdev->mesh_vdev)) {
  2312. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  2313. } else {
  2314. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2315. if ((peer->peer_id != HTT_INVALID_PEER) &&
  2316. #ifdef WDS_VENDOR_EXTENSION
  2317. /*
  2318. * . if 3-addr STA, then send on BSS Peer
  2319. * . if Peer WDS enabled and accept 4-addr mcast,
  2320. * send mcast on that peer only
  2321. * . if Peer WDS enabled and accept 4-addr ucast,
  2322. * send ucast on that peer only
  2323. */
  2324. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  2325. (peer->wds_enabled &&
  2326. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  2327. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  2328. #else
  2329. ((peer->bss_peer &&
  2330. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))))) {
  2331. #endif
  2332. peer_id = DP_INVALID_PEER;
  2333. nbuf_copy = qdf_nbuf_copy(nbuf);
  2334. if (!nbuf_copy) {
  2335. QDF_TRACE(QDF_MODULE_ID_DP,
  2336. QDF_TRACE_LEVEL_DEBUG,
  2337. FL("nbuf copy failed"));
  2338. break;
  2339. }
  2340. nbuf_copy = dp_tx_send_msdu_single(vdev,
  2341. nbuf_copy,
  2342. &msdu_info,
  2343. peer_id,
  2344. NULL);
  2345. if (nbuf_copy) {
  2346. QDF_TRACE(QDF_MODULE_ID_DP,
  2347. QDF_TRACE_LEVEL_DEBUG,
  2348. FL("pkt send failed"));
  2349. qdf_nbuf_free(nbuf_copy);
  2350. } else {
  2351. if (peer_id != DP_INVALID_PEER)
  2352. DP_STATS_INC_PKT(peer,
  2353. tx.nawds_mcast,
  2354. 1, qdf_nbuf_len(nbuf));
  2355. }
  2356. }
  2357. }
  2358. }
  2359. qdf_nbuf_free(nbuf);
  2360. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2361. }
  2362. /**
  2363. * dp_tx_inspect_handler() - Tx Inspect Handler
  2364. * @tx_desc: software descriptor head pointer
  2365. * @status : Tx completion status from HTT descriptor
  2366. *
  2367. * Handles Tx frames sent back to Host for inspection
  2368. * (ProxyARP)
  2369. *
  2370. * Return: none
  2371. */
  2372. static void dp_tx_inspect_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2373. {
  2374. struct dp_soc *soc;
  2375. struct dp_pdev *pdev = tx_desc->pdev;
  2376. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2377. "%s Tx inspect path",
  2378. __func__);
  2379. qdf_assert(pdev);
  2380. soc = pdev->soc;
  2381. DP_STATS_INC_PKT(tx_desc->vdev, tx_i.inspect_pkts, 1,
  2382. qdf_nbuf_len(tx_desc->nbuf));
  2383. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  2384. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2385. }
  2386. #ifdef FEATURE_PERPKT_INFO
  2387. /**
  2388. * dp_get_completion_indication_for_stack() - send completion to stack
  2389. * @soc : dp_soc handle
  2390. * @pdev: dp_pdev handle
  2391. * @peer: dp peer handle
  2392. * @ts: transmit completion status structure
  2393. * @netbuf: Buffer pointer for free
  2394. *
  2395. * This function is used for indication whether buffer needs to be
  2396. * sent to stack for freeing or not
  2397. */
  2398. QDF_STATUS
  2399. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2400. struct dp_pdev *pdev,
  2401. struct dp_peer *peer,
  2402. struct hal_tx_completion_status *ts,
  2403. qdf_nbuf_t netbuf,
  2404. uint64_t time_latency)
  2405. {
  2406. struct tx_capture_hdr *ppdu_hdr;
  2407. uint16_t peer_id = ts->peer_id;
  2408. uint32_t ppdu_id = ts->ppdu_id;
  2409. uint8_t first_msdu = ts->first_msdu;
  2410. uint8_t last_msdu = ts->last_msdu;
  2411. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode &&
  2412. !pdev->latency_capture_enable))
  2413. return QDF_STATUS_E_NOSUPPORT;
  2414. if (!peer) {
  2415. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2416. FL("Peer Invalid"));
  2417. return QDF_STATUS_E_INVAL;
  2418. }
  2419. if (pdev->mcopy_mode) {
  2420. if ((pdev->m_copy_id.tx_ppdu_id == ppdu_id) &&
  2421. (pdev->m_copy_id.tx_peer_id == peer_id)) {
  2422. return QDF_STATUS_E_INVAL;
  2423. }
  2424. pdev->m_copy_id.tx_ppdu_id = ppdu_id;
  2425. pdev->m_copy_id.tx_peer_id = peer_id;
  2426. }
  2427. if (!qdf_nbuf_push_head(netbuf, sizeof(struct tx_capture_hdr))) {
  2428. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2429. FL("No headroom"));
  2430. return QDF_STATUS_E_NOMEM;
  2431. }
  2432. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  2433. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  2434. QDF_MAC_ADDR_SIZE);
  2435. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  2436. QDF_MAC_ADDR_SIZE);
  2437. ppdu_hdr->ppdu_id = ppdu_id;
  2438. ppdu_hdr->peer_id = peer_id;
  2439. ppdu_hdr->first_msdu = first_msdu;
  2440. ppdu_hdr->last_msdu = last_msdu;
  2441. if (qdf_unlikely(pdev->latency_capture_enable)) {
  2442. ppdu_hdr->tsf = ts->tsf;
  2443. ppdu_hdr->time_latency = time_latency;
  2444. }
  2445. return QDF_STATUS_SUCCESS;
  2446. }
  2447. /**
  2448. * dp_send_completion_to_stack() - send completion to stack
  2449. * @soc : dp_soc handle
  2450. * @pdev: dp_pdev handle
  2451. * @peer_id: peer_id of the peer for which completion came
  2452. * @ppdu_id: ppdu_id
  2453. * @netbuf: Buffer pointer for free
  2454. *
  2455. * This function is used to send completion to stack
  2456. * to free buffer
  2457. */
  2458. void dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2459. uint16_t peer_id, uint32_t ppdu_id,
  2460. qdf_nbuf_t netbuf)
  2461. {
  2462. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  2463. netbuf, peer_id,
  2464. WDI_NO_VAL, pdev->pdev_id);
  2465. }
  2466. #else
  2467. static QDF_STATUS
  2468. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2469. struct dp_pdev *pdev,
  2470. struct dp_peer *peer,
  2471. struct hal_tx_completion_status *ts,
  2472. qdf_nbuf_t netbuf,
  2473. uint64_t time_latency)
  2474. {
  2475. return QDF_STATUS_E_NOSUPPORT;
  2476. }
  2477. static void
  2478. dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2479. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  2480. {
  2481. }
  2482. #endif
  2483. /**
  2484. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2485. * @soc: Soc handle
  2486. * @desc: software Tx descriptor to be processed
  2487. *
  2488. * Return: none
  2489. */
  2490. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  2491. struct dp_tx_desc_s *desc)
  2492. {
  2493. struct dp_vdev *vdev = desc->vdev;
  2494. qdf_nbuf_t nbuf = desc->nbuf;
  2495. /* nbuf already freed in vdev detach path */
  2496. if (!nbuf)
  2497. return;
  2498. /* If it is TDLS mgmt, don't unmap or free the frame */
  2499. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  2500. return dp_non_std_tx_comp_free_buff(soc, desc, vdev);
  2501. /* 0 : MSDU buffer, 1 : MLE */
  2502. if (desc->msdu_ext_desc) {
  2503. /* TSO free */
  2504. if (hal_tx_ext_desc_get_tso_enable(
  2505. desc->msdu_ext_desc->vaddr)) {
  2506. /* unmap eash TSO seg before free the nbuf */
  2507. dp_tx_tso_unmap_segment(soc, desc->tso_desc,
  2508. desc->tso_num_desc);
  2509. qdf_nbuf_free(nbuf);
  2510. return;
  2511. }
  2512. }
  2513. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf,
  2514. QDF_DMA_TO_DEVICE, nbuf->len);
  2515. if (qdf_unlikely(!vdev)) {
  2516. qdf_nbuf_free(nbuf);
  2517. return;
  2518. }
  2519. if (qdf_likely(!vdev->mesh_vdev))
  2520. qdf_nbuf_free(nbuf);
  2521. else {
  2522. if (desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  2523. qdf_nbuf_free(nbuf);
  2524. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  2525. } else
  2526. vdev->osif_tx_free_ext((nbuf));
  2527. }
  2528. }
  2529. #ifdef MESH_MODE_SUPPORT
  2530. /**
  2531. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2532. * in mesh meta header
  2533. * @tx_desc: software descriptor head pointer
  2534. * @ts: pointer to tx completion stats
  2535. * Return: none
  2536. */
  2537. static
  2538. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2539. struct hal_tx_completion_status *ts)
  2540. {
  2541. struct meta_hdr_s *mhdr;
  2542. qdf_nbuf_t netbuf = tx_desc->nbuf;
  2543. if (!tx_desc->msdu_ext_desc) {
  2544. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  2545. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2546. "netbuf %pK offset %d",
  2547. netbuf, tx_desc->pkt_offset);
  2548. return;
  2549. }
  2550. }
  2551. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2552. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2553. "netbuf %pK offset %lu", netbuf,
  2554. sizeof(struct meta_hdr_s));
  2555. return;
  2556. }
  2557. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  2558. mhdr->rssi = ts->ack_frame_rssi;
  2559. mhdr->band = tx_desc->pdev->operating_channel.band;
  2560. mhdr->channel = tx_desc->pdev->operating_channel.num;
  2561. }
  2562. #else
  2563. static
  2564. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2565. struct hal_tx_completion_status *ts)
  2566. {
  2567. }
  2568. #endif
  2569. /**
  2570. * dp_tx_compute_delay() - Compute and fill in all timestamps
  2571. * to pass in correct fields
  2572. *
  2573. * @vdev: pdev handle
  2574. * @tx_desc: tx descriptor
  2575. * @tid: tid value
  2576. * @ring_id: TCL or WBM ring number for transmit path
  2577. * Return: none
  2578. */
  2579. static void dp_tx_compute_delay(struct dp_vdev *vdev,
  2580. struct dp_tx_desc_s *tx_desc,
  2581. uint8_t tid, uint8_t ring_id)
  2582. {
  2583. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  2584. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  2585. if (qdf_likely(!vdev->pdev->delay_stats_flag))
  2586. return;
  2587. current_timestamp = qdf_ktime_to_ms(qdf_ktime_get());
  2588. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  2589. timestamp_hw_enqueue = tx_desc->timestamp;
  2590. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  2591. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  2592. timestamp_hw_enqueue);
  2593. interframe_delay = (uint32_t)(timestamp_ingress -
  2594. vdev->prev_tx_enq_tstamp);
  2595. /*
  2596. * Delay in software enqueue
  2597. */
  2598. dp_update_delay_stats(vdev->pdev, sw_enqueue_delay, tid,
  2599. CDP_DELAY_STATS_SW_ENQ, ring_id);
  2600. /*
  2601. * Delay between packet enqueued to HW and Tx completion
  2602. */
  2603. dp_update_delay_stats(vdev->pdev, fwhw_transmit_delay, tid,
  2604. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id);
  2605. /*
  2606. * Update interframe delay stats calculated at hardstart receive point.
  2607. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  2608. * interframe delay will not be calculate correctly for 1st frame.
  2609. * On the other side, this will help in avoiding extra per packet check
  2610. * of !vdev->prev_tx_enq_tstamp.
  2611. */
  2612. dp_update_delay_stats(vdev->pdev, interframe_delay, tid,
  2613. CDP_DELAY_STATS_TX_INTERFRAME, ring_id);
  2614. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  2615. }
  2616. #ifdef DISABLE_DP_STATS
  2617. static
  2618. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_peer *peer)
  2619. {
  2620. }
  2621. #else
  2622. static
  2623. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_peer *peer)
  2624. {
  2625. enum qdf_proto_subtype subtype = QDF_PROTO_INVALID;
  2626. DPTRACE(qdf_dp_track_noack_check(nbuf, &subtype));
  2627. if (subtype != QDF_PROTO_INVALID)
  2628. DP_STATS_INC(peer, tx.no_ack_count[subtype], 1);
  2629. }
  2630. #endif
  2631. /**
  2632. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  2633. * per wbm ring
  2634. *
  2635. * @tx_desc: software descriptor head pointer
  2636. * @ts: Tx completion status
  2637. * @peer: peer handle
  2638. * @ring_id: ring number
  2639. *
  2640. * Return: None
  2641. */
  2642. static inline void
  2643. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  2644. struct hal_tx_completion_status *ts,
  2645. struct dp_peer *peer, uint8_t ring_id)
  2646. {
  2647. struct dp_pdev *pdev = peer->vdev->pdev;
  2648. struct dp_soc *soc = NULL;
  2649. uint8_t mcs, pkt_type;
  2650. uint8_t tid = ts->tid;
  2651. uint32_t length;
  2652. struct cdp_tid_tx_stats *tid_stats;
  2653. if (!pdev)
  2654. return;
  2655. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2656. tid = CDP_MAX_DATA_TIDS - 1;
  2657. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  2658. soc = pdev->soc;
  2659. mcs = ts->mcs;
  2660. pkt_type = ts->pkt_type;
  2661. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  2662. dp_err("Release source is not from TQM");
  2663. return;
  2664. }
  2665. length = qdf_nbuf_len(tx_desc->nbuf);
  2666. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  2667. if (qdf_unlikely(pdev->delay_stats_flag))
  2668. dp_tx_compute_delay(peer->vdev, tx_desc, tid, ring_id);
  2669. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  2670. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  2671. DP_STATS_INCC_PKT(peer, tx.dropped.fw_rem, 1, length,
  2672. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2673. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  2674. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  2675. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  2676. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  2677. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  2678. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  2679. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  2680. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  2681. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  2682. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  2683. /*
  2684. * tx_failed is ideally supposed to be updated from HTT ppdu completion
  2685. * stats. But in IPQ807X/IPQ6018 chipsets owing to hw limitation there
  2686. * are no completions for failed cases. Hence updating tx_failed from
  2687. * data path. Please note that if tx_failed is fixed to be from ppdu,
  2688. * then this has to be removed
  2689. */
  2690. peer->stats.tx.tx_failed = peer->stats.tx.dropped.fw_rem.num +
  2691. peer->stats.tx.dropped.fw_rem_notx +
  2692. peer->stats.tx.dropped.fw_rem_tx +
  2693. peer->stats.tx.dropped.age_out +
  2694. peer->stats.tx.dropped.fw_reason1 +
  2695. peer->stats.tx.dropped.fw_reason2 +
  2696. peer->stats.tx.dropped.fw_reason3;
  2697. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  2698. tid_stats->tqm_status_cnt[ts->status]++;
  2699. }
  2700. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  2701. dp_update_no_ack_stats(tx_desc->nbuf, peer);
  2702. return;
  2703. }
  2704. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  2705. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  2706. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  2707. /*
  2708. * Following Rate Statistics are updated from HTT PPDU events from FW.
  2709. * Return from here if HTT PPDU events are enabled.
  2710. */
  2711. if (!(soc->process_tx_status))
  2712. return;
  2713. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2714. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  2715. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2716. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  2717. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2718. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2719. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2720. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2721. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2722. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2723. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2724. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2725. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2726. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2727. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2728. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2729. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2730. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2731. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2732. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2733. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  2734. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  2735. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  2736. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  2737. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  2738. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  2739. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  2740. #if defined(FEATURE_PERPKT_INFO) && WDI_EVENT_ENABLE
  2741. dp_wdi_event_handler(WDI_EVENT_UPDATE_DP_STATS, pdev->soc,
  2742. &peer->stats, ts->peer_id,
  2743. UPDATE_PEER_STATS, pdev->pdev_id);
  2744. #endif
  2745. }
  2746. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2747. /**
  2748. * dp_tx_flow_pool_lock() - take flow pool lock
  2749. * @soc: core txrx main context
  2750. * @tx_desc: tx desc
  2751. *
  2752. * Return: None
  2753. */
  2754. static inline
  2755. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  2756. struct dp_tx_desc_s *tx_desc)
  2757. {
  2758. struct dp_tx_desc_pool_s *pool;
  2759. uint8_t desc_pool_id;
  2760. desc_pool_id = tx_desc->pool_id;
  2761. pool = &soc->tx_desc[desc_pool_id];
  2762. qdf_spin_lock_bh(&pool->flow_pool_lock);
  2763. }
  2764. /**
  2765. * dp_tx_flow_pool_unlock() - release flow pool lock
  2766. * @soc: core txrx main context
  2767. * @tx_desc: tx desc
  2768. *
  2769. * Return: None
  2770. */
  2771. static inline
  2772. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  2773. struct dp_tx_desc_s *tx_desc)
  2774. {
  2775. struct dp_tx_desc_pool_s *pool;
  2776. uint8_t desc_pool_id;
  2777. desc_pool_id = tx_desc->pool_id;
  2778. pool = &soc->tx_desc[desc_pool_id];
  2779. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  2780. }
  2781. #else
  2782. static inline
  2783. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2784. {
  2785. }
  2786. static inline
  2787. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2788. {
  2789. }
  2790. #endif
  2791. /**
  2792. * dp_tx_notify_completion() - Notify tx completion for this desc
  2793. * @soc: core txrx main context
  2794. * @tx_desc: tx desc
  2795. * @netbuf: buffer
  2796. *
  2797. * Return: none
  2798. */
  2799. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  2800. struct dp_tx_desc_s *tx_desc,
  2801. qdf_nbuf_t netbuf)
  2802. {
  2803. void *osif_dev;
  2804. ol_txrx_completion_fp tx_compl_cbk = NULL;
  2805. qdf_assert(tx_desc);
  2806. dp_tx_flow_pool_lock(soc, tx_desc);
  2807. if (!tx_desc->vdev ||
  2808. !tx_desc->vdev->osif_vdev) {
  2809. dp_tx_flow_pool_unlock(soc, tx_desc);
  2810. return;
  2811. }
  2812. osif_dev = tx_desc->vdev->osif_vdev;
  2813. tx_compl_cbk = tx_desc->vdev->tx_comp;
  2814. dp_tx_flow_pool_unlock(soc, tx_desc);
  2815. if (tx_compl_cbk)
  2816. tx_compl_cbk(netbuf, osif_dev);
  2817. }
  2818. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  2819. * @pdev: pdev handle
  2820. * @tid: tid value
  2821. * @txdesc_ts: timestamp from txdesc
  2822. * @ppdu_id: ppdu id
  2823. *
  2824. * Return: none
  2825. */
  2826. #ifdef FEATURE_PERPKT_INFO
  2827. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2828. struct dp_peer *peer,
  2829. uint8_t tid,
  2830. uint64_t txdesc_ts,
  2831. uint32_t ppdu_id)
  2832. {
  2833. uint64_t delta_ms;
  2834. struct cdp_tx_sojourn_stats *sojourn_stats;
  2835. if (qdf_unlikely(pdev->enhanced_stats_en == 0))
  2836. return;
  2837. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  2838. tid >= CDP_DATA_TID_MAX))
  2839. return;
  2840. if (qdf_unlikely(!pdev->sojourn_buf))
  2841. return;
  2842. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  2843. qdf_nbuf_data(pdev->sojourn_buf);
  2844. sojourn_stats->cookie = (void *)peer->wlanstats_ctx;
  2845. delta_ms = qdf_ktime_to_ms(qdf_ktime_get()) -
  2846. txdesc_ts;
  2847. qdf_ewma_tx_lag_add(&peer->avg_sojourn_msdu[tid],
  2848. delta_ms);
  2849. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  2850. sojourn_stats->num_msdus[tid] = 1;
  2851. sojourn_stats->avg_sojourn_msdu[tid].internal =
  2852. peer->avg_sojourn_msdu[tid].internal;
  2853. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  2854. pdev->sojourn_buf, HTT_INVALID_PEER,
  2855. WDI_NO_VAL, pdev->pdev_id);
  2856. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  2857. sojourn_stats->num_msdus[tid] = 0;
  2858. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  2859. }
  2860. #else
  2861. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2862. struct dp_peer *peer,
  2863. uint8_t tid,
  2864. uint64_t txdesc_ts,
  2865. uint32_t ppdu_id)
  2866. {
  2867. }
  2868. #endif
  2869. /**
  2870. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  2871. * @soc: DP Soc handle
  2872. * @tx_desc: software Tx descriptor
  2873. * @ts : Tx completion status from HAL/HTT descriptor
  2874. *
  2875. * Return: none
  2876. */
  2877. static inline void
  2878. dp_tx_comp_process_desc(struct dp_soc *soc,
  2879. struct dp_tx_desc_s *desc,
  2880. struct hal_tx_completion_status *ts,
  2881. struct dp_peer *peer)
  2882. {
  2883. uint64_t time_latency = 0;
  2884. /*
  2885. * m_copy/tx_capture modes are not supported for
  2886. * scatter gather packets
  2887. */
  2888. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  2889. time_latency = (qdf_ktime_to_ms(qdf_ktime_get()) -
  2890. desc->timestamp);
  2891. }
  2892. if (!(desc->msdu_ext_desc)) {
  2893. if (QDF_STATUS_SUCCESS ==
  2894. dp_tx_add_to_comp_queue(soc, desc, ts, peer)) {
  2895. return;
  2896. }
  2897. if (QDF_STATUS_SUCCESS ==
  2898. dp_get_completion_indication_for_stack(soc,
  2899. desc->pdev,
  2900. peer, ts,
  2901. desc->nbuf,
  2902. time_latency)) {
  2903. qdf_nbuf_unmap_nbytes_single(soc->osdev, desc->nbuf,
  2904. QDF_DMA_TO_DEVICE,
  2905. desc->nbuf->len);
  2906. dp_send_completion_to_stack(soc,
  2907. desc->pdev,
  2908. ts->peer_id,
  2909. ts->ppdu_id,
  2910. desc->nbuf);
  2911. return;
  2912. }
  2913. }
  2914. dp_tx_comp_free_buf(soc, desc);
  2915. }
  2916. /**
  2917. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  2918. * @tx_desc: software descriptor head pointer
  2919. * @ts: Tx completion status
  2920. * @peer: peer handle
  2921. * @ring_id: ring number
  2922. *
  2923. * Return: none
  2924. */
  2925. static inline
  2926. void dp_tx_comp_process_tx_status(struct dp_tx_desc_s *tx_desc,
  2927. struct hal_tx_completion_status *ts,
  2928. struct dp_peer *peer, uint8_t ring_id)
  2929. {
  2930. uint32_t length;
  2931. qdf_ether_header_t *eh;
  2932. struct dp_soc *soc = NULL;
  2933. struct dp_vdev *vdev = tx_desc->vdev;
  2934. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2935. if (!vdev || !nbuf) {
  2936. dp_info_rl("invalid tx descriptor. vdev or nbuf NULL");
  2937. goto out;
  2938. }
  2939. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2940. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  2941. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  2942. QDF_TRACE_DEFAULT_PDEV_ID,
  2943. qdf_nbuf_data_addr(nbuf),
  2944. sizeof(qdf_nbuf_data(nbuf)),
  2945. tx_desc->id,
  2946. ts->status));
  2947. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2948. "-------------------- \n"
  2949. "Tx Completion Stats: \n"
  2950. "-------------------- \n"
  2951. "ack_frame_rssi = %d \n"
  2952. "first_msdu = %d \n"
  2953. "last_msdu = %d \n"
  2954. "msdu_part_of_amsdu = %d \n"
  2955. "rate_stats valid = %d \n"
  2956. "bw = %d \n"
  2957. "pkt_type = %d \n"
  2958. "stbc = %d \n"
  2959. "ldpc = %d \n"
  2960. "sgi = %d \n"
  2961. "mcs = %d \n"
  2962. "ofdma = %d \n"
  2963. "tones_in_ru = %d \n"
  2964. "tsf = %d \n"
  2965. "ppdu_id = %d \n"
  2966. "transmit_cnt = %d \n"
  2967. "tid = %d \n"
  2968. "peer_id = %d\n",
  2969. ts->ack_frame_rssi, ts->first_msdu,
  2970. ts->last_msdu, ts->msdu_part_of_amsdu,
  2971. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  2972. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  2973. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  2974. ts->transmit_cnt, ts->tid, ts->peer_id);
  2975. soc = vdev->pdev->soc;
  2976. /* Update SoC level stats */
  2977. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  2978. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2979. /* Update per-packet stats for mesh mode */
  2980. if (qdf_unlikely(vdev->mesh_vdev) &&
  2981. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  2982. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  2983. length = qdf_nbuf_len(nbuf);
  2984. /* Update peer level stats */
  2985. if (!peer) {
  2986. QDF_TRACE_DEBUG_RL(QDF_MODULE_ID_DP,
  2987. "peer is null or deletion in progress");
  2988. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  2989. goto out;
  2990. }
  2991. if (qdf_unlikely(peer->bss_peer && vdev->opmode == wlan_op_mode_ap)) {
  2992. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  2993. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  2994. if ((peer->vdev->tx_encap_type ==
  2995. htt_cmn_pkt_type_ethernet) &&
  2996. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  2997. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  2998. }
  2999. }
  3000. } else {
  3001. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  3002. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED)
  3003. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  3004. }
  3005. dp_tx_update_peer_stats(tx_desc, ts, peer, ring_id);
  3006. #ifdef QCA_SUPPORT_RDK_STATS
  3007. if (soc->wlanstats_enabled)
  3008. dp_tx_sojourn_stats_process(vdev->pdev, peer, ts->tid,
  3009. tx_desc->timestamp,
  3010. ts->ppdu_id);
  3011. #endif
  3012. out:
  3013. return;
  3014. }
  3015. /**
  3016. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  3017. * @soc: core txrx main context
  3018. * @comp_head: software descriptor head pointer
  3019. * @ring_id: ring number
  3020. *
  3021. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  3022. * and release the software descriptors after processing is complete
  3023. *
  3024. * Return: none
  3025. */
  3026. static void
  3027. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  3028. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  3029. {
  3030. struct dp_tx_desc_s *desc;
  3031. struct dp_tx_desc_s *next;
  3032. struct hal_tx_completion_status ts;
  3033. struct dp_peer *peer;
  3034. qdf_nbuf_t netbuf;
  3035. desc = comp_head;
  3036. while (desc) {
  3037. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  3038. struct dp_pdev *pdev = desc->pdev;
  3039. peer = dp_peer_find_by_id(soc, desc->peer_id);
  3040. if (qdf_likely(peer)) {
  3041. /*
  3042. * Increment peer statistics
  3043. * Minimal statistics update done here
  3044. */
  3045. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1,
  3046. desc->length);
  3047. if (desc->tx_status !=
  3048. HAL_TX_TQM_RR_FRAME_ACKED)
  3049. peer->stats.tx.tx_failed++;
  3050. dp_peer_unref_del_find_by_id(peer);
  3051. }
  3052. qdf_assert(pdev);
  3053. dp_tx_outstanding_dec(pdev);
  3054. /*
  3055. * Calling a QDF WRAPPER here is creating signifcant
  3056. * performance impact so avoided the wrapper call here
  3057. */
  3058. next = desc->next;
  3059. qdf_mem_unmap_nbytes_single(soc->osdev,
  3060. desc->dma_addr,
  3061. QDF_DMA_TO_DEVICE,
  3062. desc->length);
  3063. qdf_nbuf_free(desc->nbuf);
  3064. dp_tx_desc_free(soc, desc, desc->pool_id);
  3065. desc = next;
  3066. continue;
  3067. }
  3068. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  3069. peer = dp_peer_find_by_id(soc, ts.peer_id);
  3070. dp_tx_comp_process_tx_status(desc, &ts, peer, ring_id);
  3071. netbuf = desc->nbuf;
  3072. /* check tx complete notification */
  3073. if (QDF_NBUF_CB_TX_EXTRA_FRAG_FLAGS_NOTIFY_COMP(netbuf))
  3074. dp_tx_notify_completion(soc, desc, netbuf);
  3075. dp_tx_comp_process_desc(soc, desc, &ts, peer);
  3076. if (peer)
  3077. dp_peer_unref_del_find_by_id(peer);
  3078. next = desc->next;
  3079. dp_tx_desc_release(desc, desc->pool_id);
  3080. desc = next;
  3081. }
  3082. }
  3083. /**
  3084. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  3085. * @tx_desc: software descriptor head pointer
  3086. * @status : Tx completion status from HTT descriptor
  3087. * @ring_id: ring number
  3088. *
  3089. * This function will process HTT Tx indication messages from Target
  3090. *
  3091. * Return: none
  3092. */
  3093. static
  3094. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status,
  3095. uint8_t ring_id)
  3096. {
  3097. uint8_t tx_status;
  3098. struct dp_pdev *pdev;
  3099. struct dp_vdev *vdev;
  3100. struct dp_soc *soc;
  3101. struct hal_tx_completion_status ts = {0};
  3102. uint32_t *htt_desc = (uint32_t *)status;
  3103. struct dp_peer *peer;
  3104. struct cdp_tid_tx_stats *tid_stats = NULL;
  3105. struct htt_soc *htt_handle;
  3106. /*
  3107. * If the descriptor is already freed in vdev_detach,
  3108. * continue to next descriptor
  3109. */
  3110. if (!tx_desc->vdev && !tx_desc->flags) {
  3111. QDF_TRACE(QDF_MODULE_ID_DP,
  3112. QDF_TRACE_LEVEL_INFO,
  3113. "Descriptor freed in vdev_detach %d",
  3114. tx_desc->id);
  3115. return;
  3116. }
  3117. pdev = tx_desc->pdev;
  3118. soc = pdev->soc;
  3119. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  3120. QDF_TRACE(QDF_MODULE_ID_DP,
  3121. QDF_TRACE_LEVEL_INFO,
  3122. "pdev in down state %d",
  3123. tx_desc->id);
  3124. dp_tx_comp_free_buf(soc, tx_desc);
  3125. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3126. return;
  3127. }
  3128. qdf_assert(tx_desc->pdev);
  3129. vdev = tx_desc->vdev;
  3130. if (!vdev)
  3131. return;
  3132. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  3133. htt_handle = (struct htt_soc *)soc->htt_handle;
  3134. htt_wbm_event_record(htt_handle->htt_logger_handle, tx_status, status);
  3135. switch (tx_status) {
  3136. case HTT_TX_FW2WBM_TX_STATUS_OK:
  3137. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  3138. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  3139. {
  3140. uint8_t tid;
  3141. if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
  3142. ts.peer_id =
  3143. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
  3144. htt_desc[2]);
  3145. ts.tid =
  3146. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
  3147. htt_desc[2]);
  3148. } else {
  3149. ts.peer_id = HTT_INVALID_PEER;
  3150. ts.tid = HTT_INVALID_TID;
  3151. }
  3152. ts.ppdu_id =
  3153. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
  3154. htt_desc[1]);
  3155. ts.ack_frame_rssi =
  3156. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
  3157. htt_desc[1]);
  3158. ts.tsf = htt_desc[3];
  3159. ts.first_msdu = 1;
  3160. ts.last_msdu = 1;
  3161. tid = ts.tid;
  3162. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3163. tid = CDP_MAX_DATA_TIDS - 1;
  3164. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3165. if (qdf_unlikely(pdev->delay_stats_flag))
  3166. dp_tx_compute_delay(vdev, tx_desc, tid, ring_id);
  3167. if (tx_status < CDP_MAX_TX_HTT_STATUS) {
  3168. tid_stats->htt_status_cnt[tx_status]++;
  3169. }
  3170. peer = dp_peer_find_by_id(soc, ts.peer_id);
  3171. if (qdf_likely(peer))
  3172. dp_peer_unref_del_find_by_id(peer);
  3173. dp_tx_comp_process_tx_status(tx_desc, &ts, peer, ring_id);
  3174. dp_tx_comp_process_desc(soc, tx_desc, &ts, peer);
  3175. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3176. break;
  3177. }
  3178. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  3179. {
  3180. dp_tx_reinject_handler(tx_desc, status);
  3181. break;
  3182. }
  3183. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  3184. {
  3185. dp_tx_inspect_handler(tx_desc, status);
  3186. break;
  3187. }
  3188. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  3189. {
  3190. dp_tx_mec_handler(vdev, status);
  3191. break;
  3192. }
  3193. default:
  3194. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  3195. "%s Invalid HTT tx_status %d\n",
  3196. __func__, tx_status);
  3197. break;
  3198. }
  3199. }
  3200. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  3201. static inline
  3202. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  3203. {
  3204. bool limit_hit = false;
  3205. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  3206. limit_hit =
  3207. (num_reaped >= cfg->tx_comp_loop_pkt_limit) ? true : false;
  3208. if (limit_hit)
  3209. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  3210. return limit_hit;
  3211. }
  3212. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  3213. {
  3214. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  3215. }
  3216. #else
  3217. static inline
  3218. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  3219. {
  3220. return false;
  3221. }
  3222. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  3223. {
  3224. return false;
  3225. }
  3226. #endif
  3227. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  3228. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  3229. uint32_t quota)
  3230. {
  3231. void *tx_comp_hal_desc;
  3232. uint8_t buffer_src;
  3233. uint8_t pool_id;
  3234. uint32_t tx_desc_id;
  3235. struct dp_tx_desc_s *tx_desc = NULL;
  3236. struct dp_tx_desc_s *head_desc = NULL;
  3237. struct dp_tx_desc_s *tail_desc = NULL;
  3238. uint32_t num_processed = 0;
  3239. uint32_t count;
  3240. uint32_t num_avail_for_reap = 0;
  3241. bool force_break = false;
  3242. DP_HIST_INIT();
  3243. more_data:
  3244. /* Re-initialize local variables to be re-used */
  3245. head_desc = NULL;
  3246. tail_desc = NULL;
  3247. count = 0;
  3248. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  3249. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  3250. return 0;
  3251. }
  3252. num_avail_for_reap = hal_srng_dst_num_valid(soc->hal_soc, hal_ring_hdl, 0);
  3253. if (num_avail_for_reap >= quota)
  3254. num_avail_for_reap = quota;
  3255. dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap);
  3256. /* Find head descriptor from completion ring */
  3257. while (qdf_likely(num_avail_for_reap)) {
  3258. tx_comp_hal_desc = dp_srng_dst_get_next(soc, hal_ring_hdl);
  3259. if (qdf_unlikely(!tx_comp_hal_desc))
  3260. break;
  3261. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  3262. /* If this buffer was not released by TQM or FW, then it is not
  3263. * Tx completion indication, assert */
  3264. if (qdf_unlikely(buffer_src !=
  3265. HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  3266. (qdf_unlikely(buffer_src !=
  3267. HAL_TX_COMP_RELEASE_SOURCE_FW))) {
  3268. uint8_t wbm_internal_error;
  3269. dp_err_rl(
  3270. "Tx comp release_src != TQM | FW but from %d",
  3271. buffer_src);
  3272. hal_dump_comp_desc(tx_comp_hal_desc);
  3273. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  3274. /* When WBM sees NULL buffer_addr_info in any of
  3275. * ingress rings it sends an error indication,
  3276. * with wbm_internal_error=1, to a specific ring.
  3277. * The WBM2SW ring used to indicate these errors is
  3278. * fixed in HW, and that ring is being used as Tx
  3279. * completion ring. These errors are not related to
  3280. * Tx completions, and should just be ignored
  3281. */
  3282. wbm_internal_error = hal_get_wbm_internal_error(
  3283. soc->hal_soc,
  3284. tx_comp_hal_desc);
  3285. if (wbm_internal_error) {
  3286. dp_err_rl("Tx comp wbm_internal_error!!");
  3287. DP_STATS_INC(soc, tx.wbm_internal_error[WBM_INT_ERROR_ALL], 1);
  3288. if (HAL_TX_COMP_RELEASE_SOURCE_REO ==
  3289. buffer_src)
  3290. dp_handle_wbm_internal_error(
  3291. soc,
  3292. tx_comp_hal_desc,
  3293. hal_tx_comp_get_buffer_type(
  3294. tx_comp_hal_desc));
  3295. } else {
  3296. dp_err_rl("Tx comp wbm_internal_error false");
  3297. DP_STATS_INC(soc, tx.non_wbm_internal_err, 1);
  3298. }
  3299. continue;
  3300. }
  3301. /* Get descriptor id */
  3302. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  3303. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  3304. DP_TX_DESC_ID_POOL_OS;
  3305. /* Find Tx descriptor */
  3306. tx_desc = dp_tx_desc_find(soc, pool_id,
  3307. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  3308. DP_TX_DESC_ID_PAGE_OS,
  3309. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  3310. DP_TX_DESC_ID_OFFSET_OS);
  3311. /*
  3312. * If the release source is FW, process the HTT status
  3313. */
  3314. if (qdf_unlikely(buffer_src ==
  3315. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  3316. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  3317. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  3318. htt_tx_status);
  3319. dp_tx_process_htt_completion(tx_desc,
  3320. htt_tx_status, ring_id);
  3321. } else {
  3322. /*
  3323. * If the fast completion mode is enabled extended
  3324. * metadata from descriptor is not copied
  3325. */
  3326. if (qdf_likely(tx_desc->flags &
  3327. DP_TX_DESC_FLAG_SIMPLE)) {
  3328. tx_desc->peer_id =
  3329. hal_tx_comp_get_peer_id(tx_comp_hal_desc);
  3330. tx_desc->tx_status =
  3331. hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  3332. goto add_to_pool;
  3333. }
  3334. /*
  3335. * If the descriptor is already freed in vdev_detach,
  3336. * continue to next descriptor
  3337. */
  3338. if (qdf_unlikely(!tx_desc->vdev) &&
  3339. qdf_unlikely(!tx_desc->flags)) {
  3340. QDF_TRACE(QDF_MODULE_ID_DP,
  3341. QDF_TRACE_LEVEL_INFO,
  3342. "Descriptor freed in vdev_detach %d",
  3343. tx_desc_id);
  3344. continue;
  3345. }
  3346. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  3347. QDF_TRACE(QDF_MODULE_ID_DP,
  3348. QDF_TRACE_LEVEL_INFO,
  3349. "pdev in down state %d",
  3350. tx_desc_id);
  3351. dp_tx_comp_free_buf(soc, tx_desc);
  3352. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3353. goto next_desc;
  3354. }
  3355. /* Pool id is not matching. Error */
  3356. if (tx_desc->pool_id != pool_id) {
  3357. QDF_TRACE(QDF_MODULE_ID_DP,
  3358. QDF_TRACE_LEVEL_FATAL,
  3359. "Tx Comp pool id %d not matched %d",
  3360. pool_id, tx_desc->pool_id);
  3361. qdf_assert_always(0);
  3362. }
  3363. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  3364. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  3365. QDF_TRACE(QDF_MODULE_ID_DP,
  3366. QDF_TRACE_LEVEL_FATAL,
  3367. "Txdesc invalid, flgs = %x,id = %d",
  3368. tx_desc->flags, tx_desc_id);
  3369. qdf_assert_always(0);
  3370. }
  3371. /* Collect hw completion contents */
  3372. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  3373. &tx_desc->comp, 1);
  3374. add_to_pool:
  3375. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  3376. /* First ring descriptor on the cycle */
  3377. if (!head_desc) {
  3378. head_desc = tx_desc;
  3379. tail_desc = tx_desc;
  3380. }
  3381. tail_desc->next = tx_desc;
  3382. tx_desc->next = NULL;
  3383. tail_desc = tx_desc;
  3384. }
  3385. next_desc:
  3386. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  3387. /*
  3388. * Processed packet count is more than given quota
  3389. * stop to processing
  3390. */
  3391. count++;
  3392. if (dp_tx_comp_loop_pkt_limit_hit(soc, count))
  3393. break;
  3394. }
  3395. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  3396. /* Process the reaped descriptors */
  3397. if (head_desc)
  3398. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  3399. if (dp_tx_comp_enable_eol_data_check(soc)) {
  3400. if (num_processed >= quota)
  3401. force_break = true;
  3402. if (!force_break &&
  3403. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  3404. hal_ring_hdl)) {
  3405. DP_STATS_INC(soc, tx.hp_oos2, 1);
  3406. if (!hif_exec_should_yield(soc->hif_handle,
  3407. int_ctx->dp_intr_id))
  3408. goto more_data;
  3409. }
  3410. }
  3411. DP_TX_HIST_STATS_PER_PDEV();
  3412. return num_processed;
  3413. }
  3414. #ifdef FEATURE_WLAN_TDLS
  3415. qdf_nbuf_t dp_tx_non_std(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3416. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  3417. {
  3418. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3419. struct dp_vdev *vdev = dp_get_vdev_from_soc_vdev_id_wifi3(soc, vdev_id);
  3420. if (!vdev) {
  3421. dp_err("vdev handle for id %d is NULL", vdev_id);
  3422. return NULL;
  3423. }
  3424. if (tx_spec & OL_TX_SPEC_NO_FREE)
  3425. vdev->is_tdls_frame = true;
  3426. return dp_tx_send(soc_hdl, vdev_id, msdu_list);
  3427. }
  3428. #endif
  3429. /**
  3430. * dp_tx_vdev_attach() - attach vdev to dp tx
  3431. * @vdev: virtual device instance
  3432. *
  3433. * Return: QDF_STATUS_SUCCESS: success
  3434. * QDF_STATUS_E_RESOURCES: Error return
  3435. */
  3436. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  3437. {
  3438. int pdev_id;
  3439. /*
  3440. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  3441. */
  3442. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  3443. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  3444. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  3445. vdev->vdev_id);
  3446. pdev_id =
  3447. dp_get_target_pdev_id_for_host_pdev_id(vdev->pdev->soc,
  3448. vdev->pdev->pdev_id);
  3449. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata, pdev_id);
  3450. /*
  3451. * Set HTT Extension Valid bit to 0 by default
  3452. */
  3453. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  3454. dp_tx_vdev_update_search_flags(vdev);
  3455. return QDF_STATUS_SUCCESS;
  3456. }
  3457. #ifndef FEATURE_WDS
  3458. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  3459. {
  3460. return false;
  3461. }
  3462. #endif
  3463. /**
  3464. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  3465. * @vdev: virtual device instance
  3466. *
  3467. * Return: void
  3468. *
  3469. */
  3470. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  3471. {
  3472. struct dp_soc *soc = vdev->pdev->soc;
  3473. /*
  3474. * Enable both AddrY (SA based search) and AddrX (Da based search)
  3475. * for TDLS link
  3476. *
  3477. * Enable AddrY (SA based search) only for non-WDS STA and
  3478. * ProxySTA VAP (in HKv1) modes.
  3479. *
  3480. * In all other VAP modes, only DA based search should be
  3481. * enabled
  3482. */
  3483. if (vdev->opmode == wlan_op_mode_sta &&
  3484. vdev->tdls_link_connected)
  3485. vdev->hal_desc_addr_search_flags =
  3486. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  3487. else if ((vdev->opmode == wlan_op_mode_sta) &&
  3488. !dp_tx_da_search_override(vdev))
  3489. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  3490. else
  3491. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  3492. /* Set search type only when peer map v2 messaging is enabled
  3493. * as we will have the search index (AST hash) only when v2 is
  3494. * enabled
  3495. */
  3496. if (soc->is_peer_map_unmap_v2 && vdev->opmode == wlan_op_mode_sta)
  3497. vdev->search_type = HAL_TX_ADDR_INDEX_SEARCH;
  3498. else
  3499. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  3500. }
  3501. static inline bool
  3502. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  3503. struct dp_vdev *vdev,
  3504. struct dp_tx_desc_s *tx_desc)
  3505. {
  3506. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  3507. return false;
  3508. /*
  3509. * if vdev is given, then only check whether desc
  3510. * vdev match. if vdev is NULL, then check whether
  3511. * desc pdev match.
  3512. */
  3513. return vdev ? (tx_desc->vdev == vdev) : (tx_desc->pdev == pdev);
  3514. }
  3515. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3516. /**
  3517. * dp_tx_desc_flush() - release resources associated
  3518. * to TX Desc
  3519. *
  3520. * @dp_pdev: Handle to DP pdev structure
  3521. * @vdev: virtual device instance
  3522. * NULL: no specific Vdev is required and check all allcated TX desc
  3523. * on this pdev.
  3524. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  3525. *
  3526. * @force_free:
  3527. * true: flush the TX desc.
  3528. * false: only reset the Vdev in each allocated TX desc
  3529. * that associated to current Vdev.
  3530. *
  3531. * This function will go through the TX desc pool to flush
  3532. * the outstanding TX data or reset Vdev to NULL in associated TX
  3533. * Desc.
  3534. */
  3535. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  3536. bool force_free)
  3537. {
  3538. uint8_t i;
  3539. uint32_t j;
  3540. uint32_t num_desc, page_id, offset;
  3541. uint16_t num_desc_per_page;
  3542. struct dp_soc *soc = pdev->soc;
  3543. struct dp_tx_desc_s *tx_desc = NULL;
  3544. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3545. if (!vdev && !force_free) {
  3546. dp_err("Reset TX desc vdev, Vdev param is required!");
  3547. return;
  3548. }
  3549. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  3550. tx_desc_pool = &soc->tx_desc[i];
  3551. if (!(tx_desc_pool->pool_size) ||
  3552. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  3553. !(tx_desc_pool->desc_pages.cacheable_pages))
  3554. continue;
  3555. /*
  3556. * Add flow pool lock protection in case pool is freed
  3557. * due to all tx_desc is recycled when handle TX completion.
  3558. * this is not necessary when do force flush as:
  3559. * a. double lock will happen if dp_tx_desc_release is
  3560. * also trying to acquire it.
  3561. * b. dp interrupt has been disabled before do force TX desc
  3562. * flush in dp_pdev_deinit().
  3563. */
  3564. if (!force_free)
  3565. qdf_spin_lock_bh(&tx_desc_pool->flow_pool_lock);
  3566. num_desc = tx_desc_pool->pool_size;
  3567. num_desc_per_page =
  3568. tx_desc_pool->desc_pages.num_element_per_page;
  3569. for (j = 0; j < num_desc; j++) {
  3570. page_id = j / num_desc_per_page;
  3571. offset = j % num_desc_per_page;
  3572. if (qdf_unlikely(!(tx_desc_pool->
  3573. desc_pages.cacheable_pages)))
  3574. break;
  3575. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3576. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  3577. /*
  3578. * Free TX desc if force free is
  3579. * required, otherwise only reset vdev
  3580. * in this TX desc.
  3581. */
  3582. if (force_free) {
  3583. dp_tx_comp_free_buf(soc, tx_desc);
  3584. dp_tx_desc_release(tx_desc, i);
  3585. } else {
  3586. tx_desc->vdev = NULL;
  3587. }
  3588. }
  3589. }
  3590. if (!force_free)
  3591. qdf_spin_unlock_bh(&tx_desc_pool->flow_pool_lock);
  3592. }
  3593. }
  3594. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3595. /**
  3596. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  3597. *
  3598. * @soc: Handle to DP soc structure
  3599. * @tx_desc: pointer of one TX desc
  3600. * @desc_pool_id: TX Desc pool id
  3601. */
  3602. static inline void
  3603. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  3604. uint8_t desc_pool_id)
  3605. {
  3606. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  3607. tx_desc->vdev = NULL;
  3608. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  3609. }
  3610. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  3611. bool force_free)
  3612. {
  3613. uint8_t i, num_pool;
  3614. uint32_t j;
  3615. uint32_t num_desc, page_id, offset;
  3616. uint16_t num_desc_per_page;
  3617. struct dp_soc *soc = pdev->soc;
  3618. struct dp_tx_desc_s *tx_desc = NULL;
  3619. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3620. if (!vdev && !force_free) {
  3621. dp_err("Reset TX desc vdev, Vdev param is required!");
  3622. return;
  3623. }
  3624. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3625. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3626. for (i = 0; i < num_pool; i++) {
  3627. tx_desc_pool = &soc->tx_desc[i];
  3628. if (!tx_desc_pool->desc_pages.cacheable_pages)
  3629. continue;
  3630. num_desc_per_page =
  3631. tx_desc_pool->desc_pages.num_element_per_page;
  3632. for (j = 0; j < num_desc; j++) {
  3633. page_id = j / num_desc_per_page;
  3634. offset = j % num_desc_per_page;
  3635. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3636. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  3637. if (force_free) {
  3638. dp_tx_comp_free_buf(soc, tx_desc);
  3639. dp_tx_desc_release(tx_desc, i);
  3640. } else {
  3641. dp_tx_desc_reset_vdev(soc, tx_desc,
  3642. i);
  3643. }
  3644. }
  3645. }
  3646. }
  3647. }
  3648. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3649. /**
  3650. * dp_tx_vdev_detach() - detach vdev from dp tx
  3651. * @vdev: virtual device instance
  3652. *
  3653. * Return: QDF_STATUS_SUCCESS: success
  3654. * QDF_STATUS_E_RESOURCES: Error return
  3655. */
  3656. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  3657. {
  3658. struct dp_pdev *pdev = vdev->pdev;
  3659. /* Reset TX desc associated to this Vdev as NULL */
  3660. dp_tx_desc_flush(pdev, vdev, false);
  3661. dp_tx_vdev_multipass_deinit(vdev);
  3662. return QDF_STATUS_SUCCESS;
  3663. }
  3664. /**
  3665. * dp_tx_pdev_attach() - attach pdev to dp tx
  3666. * @pdev: physical device instance
  3667. *
  3668. * Return: QDF_STATUS_SUCCESS: success
  3669. * QDF_STATUS_E_RESOURCES: Error return
  3670. */
  3671. QDF_STATUS dp_tx_pdev_init(struct dp_pdev *pdev)
  3672. {
  3673. struct dp_soc *soc = pdev->soc;
  3674. /* Initialize Flow control counters */
  3675. qdf_atomic_init(&pdev->num_tx_outstanding);
  3676. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3677. /* Initialize descriptors in TCL Ring */
  3678. hal_tx_init_data_ring(soc->hal_soc,
  3679. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  3680. }
  3681. return QDF_STATUS_SUCCESS;
  3682. }
  3683. /**
  3684. * dp_tx_pdev_detach() - detach pdev from dp tx
  3685. * @pdev: physical device instance
  3686. *
  3687. * Return: QDF_STATUS_SUCCESS: success
  3688. * QDF_STATUS_E_RESOURCES: Error return
  3689. */
  3690. QDF_STATUS dp_tx_pdev_detach(struct dp_pdev *pdev)
  3691. {
  3692. /* flush TX outstanding data per pdev */
  3693. dp_tx_desc_flush(pdev, NULL, true);
  3694. dp_tx_me_exit(pdev);
  3695. return QDF_STATUS_SUCCESS;
  3696. }
  3697. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3698. /* Pools will be allocated dynamically */
  3699. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3700. int num_desc)
  3701. {
  3702. uint8_t i;
  3703. for (i = 0; i < num_pool; i++) {
  3704. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  3705. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  3706. }
  3707. return QDF_STATUS_SUCCESS;
  3708. }
  3709. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  3710. int num_desc)
  3711. {
  3712. return QDF_STATUS_SUCCESS;
  3713. }
  3714. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  3715. {
  3716. }
  3717. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3718. {
  3719. uint8_t i;
  3720. for (i = 0; i < num_pool; i++)
  3721. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  3722. }
  3723. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3724. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3725. int num_desc)
  3726. {
  3727. uint8_t i, count;
  3728. /* Allocate software Tx descriptor pools */
  3729. for (i = 0; i < num_pool; i++) {
  3730. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  3731. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3732. FL("Tx Desc Pool alloc %d failed %pK"),
  3733. i, soc);
  3734. goto fail;
  3735. }
  3736. }
  3737. return QDF_STATUS_SUCCESS;
  3738. fail:
  3739. for (count = 0; count < i; count++)
  3740. dp_tx_desc_pool_free(soc, count);
  3741. return QDF_STATUS_E_NOMEM;
  3742. }
  3743. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  3744. int num_desc)
  3745. {
  3746. uint8_t i;
  3747. for (i = 0; i < num_pool; i++) {
  3748. if (dp_tx_desc_pool_init(soc, i, num_desc)) {
  3749. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3750. FL("Tx Desc Pool init %d failed %pK"),
  3751. i, soc);
  3752. return QDF_STATUS_E_NOMEM;
  3753. }
  3754. }
  3755. return QDF_STATUS_SUCCESS;
  3756. }
  3757. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  3758. {
  3759. uint8_t i;
  3760. for (i = 0; i < num_pool; i++)
  3761. dp_tx_desc_pool_deinit(soc, i);
  3762. }
  3763. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3764. {
  3765. uint8_t i;
  3766. for (i = 0; i < num_pool; i++)
  3767. dp_tx_desc_pool_free(soc, i);
  3768. }
  3769. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3770. /**
  3771. * dp_tx_tso_cmn_desc_pool_deinit() - de-initialize TSO descriptors
  3772. * @soc: core txrx main context
  3773. * @num_pool: number of pools
  3774. *
  3775. */
  3776. void dp_tx_tso_cmn_desc_pool_deinit(struct dp_soc *soc, uint8_t num_pool)
  3777. {
  3778. dp_tx_tso_desc_pool_deinit(soc, num_pool);
  3779. dp_tx_tso_num_seg_pool_deinit(soc, num_pool);
  3780. }
  3781. /**
  3782. * dp_tx_tso_cmn_desc_pool_free() - free TSO descriptors
  3783. * @soc: core txrx main context
  3784. * @num_pool: number of pools
  3785. *
  3786. */
  3787. void dp_tx_tso_cmn_desc_pool_free(struct dp_soc *soc, uint8_t num_pool)
  3788. {
  3789. dp_tx_tso_desc_pool_free(soc, num_pool);
  3790. dp_tx_tso_num_seg_pool_free(soc, num_pool);
  3791. }
  3792. /**
  3793. * dp_soc_tx_desc_sw_pools_free() - free all TX descriptors
  3794. * @soc: core txrx main context
  3795. *
  3796. * This function frees all tx related descriptors as below
  3797. * 1. Regular TX descriptors (static pools)
  3798. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  3799. * 3. TSO descriptors
  3800. *
  3801. */
  3802. void dp_soc_tx_desc_sw_pools_free(struct dp_soc *soc)
  3803. {
  3804. uint8_t num_pool;
  3805. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3806. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  3807. dp_tx_ext_desc_pool_free(soc, num_pool);
  3808. dp_tx_delete_static_pools(soc, num_pool);
  3809. }
  3810. /**
  3811. * dp_soc_tx_desc_sw_pools_deinit() - de-initialize all TX descriptors
  3812. * @soc: core txrx main context
  3813. *
  3814. * This function de-initializes all tx related descriptors as below
  3815. * 1. Regular TX descriptors (static pools)
  3816. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  3817. * 3. TSO descriptors
  3818. *
  3819. */
  3820. void dp_soc_tx_desc_sw_pools_deinit(struct dp_soc *soc)
  3821. {
  3822. uint8_t num_pool;
  3823. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3824. dp_tx_flow_control_deinit(soc);
  3825. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  3826. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  3827. dp_tx_deinit_static_pools(soc, num_pool);
  3828. }
  3829. /**
  3830. * dp_tso_attach() - TSO attach handler
  3831. * @txrx_soc: Opaque Dp handle
  3832. *
  3833. * Reserve TSO descriptor buffers
  3834. *
  3835. * Return: QDF_STATUS_E_FAILURE on failure or
  3836. * QDF_STATUS_SUCCESS on success
  3837. */
  3838. QDF_STATUS dp_tx_tso_cmn_desc_pool_alloc(struct dp_soc *soc,
  3839. uint8_t num_pool,
  3840. uint16_t num_desc)
  3841. {
  3842. if (dp_tx_tso_desc_pool_alloc(soc, num_pool, num_desc)) {
  3843. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  3844. return QDF_STATUS_E_FAILURE;
  3845. }
  3846. if (dp_tx_tso_num_seg_pool_alloc(soc, num_pool, num_desc)) {
  3847. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  3848. num_pool, soc);
  3849. return QDF_STATUS_E_FAILURE;
  3850. }
  3851. return QDF_STATUS_SUCCESS;
  3852. }
  3853. /**
  3854. * dp_tx_tso_cmn_desc_pool_init() - TSO cmn desc pool init
  3855. * @soc: DP soc handle
  3856. * @num_pool: Number of pools
  3857. * @num_desc: Number of descriptors
  3858. *
  3859. * Initialize TSO descriptor pools
  3860. *
  3861. * Return: QDF_STATUS_E_FAILURE on failure or
  3862. * QDF_STATUS_SUCCESS on success
  3863. */
  3864. QDF_STATUS dp_tx_tso_cmn_desc_pool_init(struct dp_soc *soc,
  3865. uint8_t num_pool,
  3866. uint16_t num_desc)
  3867. {
  3868. if (dp_tx_tso_desc_pool_init(soc, num_pool, num_desc)) {
  3869. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  3870. return QDF_STATUS_E_FAILURE;
  3871. }
  3872. if (dp_tx_tso_num_seg_pool_init(soc, num_pool, num_desc)) {
  3873. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  3874. num_pool, soc);
  3875. return QDF_STATUS_E_FAILURE;
  3876. }
  3877. return QDF_STATUS_SUCCESS;
  3878. }
  3879. /**
  3880. * dp_soc_tx_desc_sw_pools_alloc() - Allocate tx descriptor pool memory
  3881. * @soc: core txrx main context
  3882. *
  3883. * This function allocates memory for following descriptor pools
  3884. * 1. regular sw tx descriptor pools (static pools)
  3885. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  3886. * 3. TSO descriptor pools
  3887. *
  3888. * Return: QDF_STATUS_SUCCESS: success
  3889. * QDF_STATUS_E_RESOURCES: Error return
  3890. */
  3891. QDF_STATUS dp_soc_tx_desc_sw_pools_alloc(struct dp_soc *soc)
  3892. {
  3893. uint8_t num_pool;
  3894. uint32_t num_desc;
  3895. uint32_t num_ext_desc;
  3896. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3897. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3898. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  3899. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3900. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  3901. __func__, num_pool, num_desc);
  3902. if ((num_pool > MAX_TXDESC_POOLS) ||
  3903. (num_desc > WLAN_CFG_NUM_TX_DESC_MAX))
  3904. goto fail1;
  3905. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  3906. goto fail1;
  3907. if (dp_tx_ext_desc_pool_alloc(soc, num_pool, num_ext_desc))
  3908. goto fail2;
  3909. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  3910. return QDF_STATUS_SUCCESS;
  3911. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  3912. goto fail3;
  3913. return QDF_STATUS_SUCCESS;
  3914. fail3:
  3915. dp_tx_ext_desc_pool_free(soc, num_pool);
  3916. fail2:
  3917. dp_tx_delete_static_pools(soc, num_pool);
  3918. fail1:
  3919. return QDF_STATUS_E_RESOURCES;
  3920. }
  3921. /**
  3922. * dp_soc_tx_desc_sw_pools_init() - Initialise TX descriptor pools
  3923. * @soc: core txrx main context
  3924. *
  3925. * This function initializes the following TX descriptor pools
  3926. * 1. regular sw tx descriptor pools (static pools)
  3927. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  3928. * 3. TSO descriptor pools
  3929. *
  3930. * Return: QDF_STATUS_SUCCESS: success
  3931. * QDF_STATUS_E_RESOURCES: Error return
  3932. */
  3933. QDF_STATUS dp_soc_tx_desc_sw_pools_init(struct dp_soc *soc)
  3934. {
  3935. uint8_t num_pool;
  3936. uint32_t num_desc;
  3937. uint32_t num_ext_desc;
  3938. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3939. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3940. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  3941. if (dp_tx_init_static_pools(soc, num_pool, num_desc))
  3942. goto fail1;
  3943. if (dp_tx_ext_desc_pool_init(soc, num_pool, num_ext_desc))
  3944. goto fail2;
  3945. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  3946. return QDF_STATUS_SUCCESS;
  3947. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  3948. goto fail3;
  3949. dp_tx_flow_control_init(soc);
  3950. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  3951. return QDF_STATUS_SUCCESS;
  3952. fail3:
  3953. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  3954. fail2:
  3955. dp_tx_deinit_static_pools(soc, num_pool);
  3956. fail1:
  3957. return QDF_STATUS_E_RESOURCES;
  3958. }
  3959. /**
  3960. * dp_tso_soc_attach() - Allocate and initialize TSO descriptors
  3961. * @txrx_soc: dp soc handle
  3962. *
  3963. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  3964. * QDF_STATUS_E_FAILURE
  3965. */
  3966. QDF_STATUS dp_tso_soc_attach(struct cdp_soc_t *txrx_soc)
  3967. {
  3968. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3969. uint8_t num_pool;
  3970. uint32_t num_desc;
  3971. uint32_t num_ext_desc;
  3972. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3973. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3974. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  3975. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  3976. return QDF_STATUS_E_FAILURE;
  3977. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  3978. return QDF_STATUS_E_FAILURE;
  3979. return QDF_STATUS_SUCCESS;
  3980. }
  3981. /**
  3982. * dp_tso_soc_detach() - de-initialize and free the TSO descriptors
  3983. * @txrx_soc: dp soc handle
  3984. *
  3985. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  3986. */
  3987. QDF_STATUS dp_tso_soc_detach(struct cdp_soc_t *txrx_soc)
  3988. {
  3989. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3990. uint8_t num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3991. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  3992. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  3993. return QDF_STATUS_SUCCESS;
  3994. }