dp_be_rx.c 35 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "cdp_txrx_cmn_struct.h"
  20. #include "hal_hw_headers.h"
  21. #include "dp_types.h"
  22. #include "dp_rx.h"
  23. #include "dp_be_rx.h"
  24. #include "dp_peer.h"
  25. #include "hal_rx.h"
  26. #include "hal_be_rx.h"
  27. #include "hal_api.h"
  28. #include "hal_be_api.h"
  29. #include "qdf_nbuf.h"
  30. #ifdef MESH_MODE_SUPPORT
  31. #include "if_meta_hdr.h"
  32. #endif
  33. #include "dp_internal.h"
  34. #include "dp_ipa.h"
  35. #ifdef FEATURE_WDS
  36. #include "dp_txrx_wds.h"
  37. #endif
  38. #include "dp_hist.h"
  39. #include "dp_rx_buffer_pool.h"
  40. #ifndef AST_OFFLOAD_ENABLE
  41. static void
  42. dp_rx_wds_learn(struct dp_soc *soc,
  43. struct dp_vdev *vdev,
  44. uint8_t *rx_tlv_hdr,
  45. struct dp_peer *peer,
  46. qdf_nbuf_t nbuf,
  47. struct hal_rx_msdu_metadata msdu_metadata)
  48. {
  49. /* WDS Source Port Learning */
  50. if (qdf_likely(vdev->wds_enabled))
  51. dp_rx_wds_srcport_learn(soc,
  52. rx_tlv_hdr,
  53. peer,
  54. nbuf,
  55. msdu_metadata);
  56. }
  57. #else
  58. #ifdef QCA_SUPPORT_WDS_EXTENDED
  59. /**
  60. * dp_wds_ext_peer_learn_be() - function to send event to control
  61. * path on receiving 1st 4-address frame from backhaul.
  62. * @soc: DP soc
  63. * @ta_peer: WDS repeater peer
  64. * @rx_tlv_hdr : start address of rx tlvs
  65. *
  66. * Return: void
  67. */
  68. static inline void dp_wds_ext_peer_learn_be(struct dp_soc *soc,
  69. struct dp_peer *ta_peer,
  70. uint8_t *rx_tlv_hdr)
  71. {
  72. uint8_t wds_ext_src_mac[QDF_MAC_ADDR_SIZE];
  73. /* instead of checking addr4 is valid or not in per packet path
  74. * check for init bit, which will be set on reception of
  75. * first addr4 valid packet.
  76. */
  77. if (!ta_peer->vdev->wds_ext_enabled ||
  78. qdf_atomic_test_bit(WDS_EXT_PEER_INIT_BIT, &ta_peer->wds_ext.init))
  79. return;
  80. if (hal_rx_get_mpdu_mac_ad4_valid(soc->hal_soc, rx_tlv_hdr)) {
  81. qdf_atomic_test_and_set_bit(WDS_EXT_PEER_INIT_BIT,
  82. &ta_peer->wds_ext.init);
  83. qdf_mem_copy(wds_ext_src_mac, &ta_peer->mac_addr.raw[0],
  84. QDF_MAC_ADDR_SIZE);
  85. soc->cdp_soc.ol_ops->rx_wds_ext_peer_learn(
  86. soc->ctrl_psoc,
  87. ta_peer->peer_id,
  88. ta_peer->vdev->vdev_id,
  89. wds_ext_src_mac);
  90. }
  91. }
  92. #else
  93. static inline void dp_wds_ext_peer_learn_be(struct dp_soc *soc,
  94. struct dp_peer *ta_peer,
  95. uint8_t *rx_tlv_hdr)
  96. {
  97. }
  98. #endif
  99. static void
  100. dp_rx_wds_learn(struct dp_soc *soc,
  101. struct dp_vdev *vdev,
  102. uint8_t *rx_tlv_hdr,
  103. struct dp_peer *ta_peer,
  104. qdf_nbuf_t nbuf,
  105. struct hal_rx_msdu_metadata msdu_metadata)
  106. {
  107. dp_wds_ext_peer_learn_be(soc, ta_peer, rx_tlv_hdr);
  108. }
  109. #endif
  110. /**
  111. * dp_rx_process_be() - Brain of the Rx processing functionality
  112. * Called from the bottom half (tasklet/NET_RX_SOFTIRQ)
  113. * @int_ctx: per interrupt context
  114. * @hal_ring: opaque pointer to the HAL Rx Ring, which will be serviced
  115. * @reo_ring_num: ring number (0, 1, 2 or 3) of the reo ring.
  116. * @quota: No. of units (packets) that can be serviced in one shot.
  117. *
  118. * This function implements the core of Rx functionality. This is
  119. * expected to handle only non-error frames.
  120. *
  121. * Return: uint32_t: No. of elements processed
  122. */
  123. uint32_t dp_rx_process_be(struct dp_intr *int_ctx,
  124. hal_ring_handle_t hal_ring_hdl, uint8_t reo_ring_num,
  125. uint32_t quota)
  126. {
  127. hal_ring_desc_t ring_desc;
  128. hal_soc_handle_t hal_soc;
  129. struct dp_rx_desc *rx_desc = NULL;
  130. qdf_nbuf_t nbuf, next;
  131. bool near_full;
  132. union dp_rx_desc_list_elem_t *head[MAX_PDEV_CNT];
  133. union dp_rx_desc_list_elem_t *tail[MAX_PDEV_CNT];
  134. uint32_t num_pending;
  135. uint32_t rx_bufs_used = 0, rx_buf_cookie;
  136. uint16_t msdu_len = 0;
  137. uint16_t peer_id;
  138. uint8_t vdev_id;
  139. struct dp_peer *peer;
  140. struct dp_vdev *vdev;
  141. uint32_t pkt_len = 0;
  142. struct hal_rx_mpdu_desc_info mpdu_desc_info;
  143. struct hal_rx_msdu_desc_info msdu_desc_info;
  144. enum hal_reo_error_status error;
  145. uint32_t peer_mdata;
  146. uint8_t *rx_tlv_hdr;
  147. uint32_t rx_bufs_reaped[MAX_PDEV_CNT];
  148. uint8_t mac_id = 0;
  149. struct dp_pdev *rx_pdev;
  150. struct dp_srng *dp_rxdma_srng;
  151. struct rx_desc_pool *rx_desc_pool;
  152. struct dp_soc *soc = int_ctx->soc;
  153. uint8_t core_id = 0;
  154. struct cdp_tid_rx_stats *tid_stats;
  155. qdf_nbuf_t nbuf_head;
  156. qdf_nbuf_t nbuf_tail;
  157. qdf_nbuf_t deliver_list_head;
  158. qdf_nbuf_t deliver_list_tail;
  159. uint32_t num_rx_bufs_reaped = 0;
  160. uint32_t intr_id;
  161. struct hif_opaque_softc *scn;
  162. int32_t tid = 0;
  163. bool is_prev_msdu_last = true;
  164. uint32_t num_entries_avail = 0;
  165. uint32_t rx_ol_pkt_cnt = 0;
  166. uint32_t num_entries = 0;
  167. struct hal_rx_msdu_metadata msdu_metadata;
  168. QDF_STATUS status;
  169. qdf_nbuf_t ebuf_head;
  170. qdf_nbuf_t ebuf_tail;
  171. uint8_t pkt_capture_offload = 0;
  172. struct dp_srng *rx_ring = &soc->reo_dest_ring[reo_ring_num];
  173. int max_reap_limit, ring_near_full;
  174. struct dp_soc *replenish_soc;
  175. DP_HIST_INIT();
  176. qdf_assert_always(soc && hal_ring_hdl);
  177. hal_soc = soc->hal_soc;
  178. qdf_assert_always(hal_soc);
  179. scn = soc->hif_handle;
  180. hif_pm_runtime_mark_dp_rx_busy(scn);
  181. intr_id = int_ctx->dp_intr_id;
  182. num_entries = hal_srng_get_num_entries(hal_soc, hal_ring_hdl);
  183. more_data:
  184. /* reset local variables here to be re-used in the function */
  185. nbuf_head = NULL;
  186. nbuf_tail = NULL;
  187. deliver_list_head = NULL;
  188. deliver_list_tail = NULL;
  189. peer = NULL;
  190. vdev = NULL;
  191. num_rx_bufs_reaped = 0;
  192. ebuf_head = NULL;
  193. ebuf_tail = NULL;
  194. ring_near_full = 0;
  195. max_reap_limit = dp_rx_get_loop_pkt_limit(soc);
  196. qdf_mem_zero(rx_bufs_reaped, sizeof(rx_bufs_reaped));
  197. qdf_mem_zero(&mpdu_desc_info, sizeof(mpdu_desc_info));
  198. qdf_mem_zero(&msdu_desc_info, sizeof(msdu_desc_info));
  199. qdf_mem_zero(head, sizeof(head));
  200. qdf_mem_zero(tail, sizeof(tail));
  201. ring_near_full = _dp_srng_test_and_update_nf_params(soc, rx_ring,
  202. &max_reap_limit);
  203. if (qdf_unlikely(dp_rx_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  204. /*
  205. * Need API to convert from hal_ring pointer to
  206. * Ring Type / Ring Id combo
  207. */
  208. DP_STATS_INC(soc, rx.err.hal_ring_access_fail, 1);
  209. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  210. FL("HAL RING Access Failed -- %pK"), hal_ring_hdl);
  211. goto done;
  212. }
  213. /*
  214. * start reaping the buffers from reo ring and queue
  215. * them in per vdev queue.
  216. * Process the received pkts in a different per vdev loop.
  217. */
  218. while (qdf_likely(quota &&
  219. (ring_desc = hal_srng_dst_peek(hal_soc,
  220. hal_ring_hdl)))) {
  221. error = HAL_RX_ERROR_STATUS_GET(ring_desc);
  222. if (qdf_unlikely(error == HAL_REO_ERROR_DETECTED)) {
  223. dp_rx_err("%pK: HAL RING 0x%pK:error %d",
  224. soc, hal_ring_hdl, error);
  225. DP_STATS_INC(soc, rx.err.hal_reo_error[reo_ring_num],
  226. 1);
  227. /* Don't know how to deal with this -- assert */
  228. qdf_assert(0);
  229. }
  230. dp_rx_ring_record_entry(soc, reo_ring_num, ring_desc);
  231. rx_buf_cookie = HAL_RX_REO_BUF_COOKIE_GET(ring_desc);
  232. status = dp_rx_cookie_check_and_invalidate(ring_desc);
  233. if (qdf_unlikely(QDF_IS_STATUS_ERROR(status))) {
  234. DP_STATS_INC(soc, rx.err.stale_cookie, 1);
  235. break;
  236. }
  237. rx_desc = (struct dp_rx_desc *)
  238. hal_rx_get_reo_desc_va(ring_desc);
  239. dp_rx_desc_sw_cc_check(soc, rx_buf_cookie, &rx_desc);
  240. status = dp_rx_desc_sanity(soc, hal_soc, hal_ring_hdl,
  241. ring_desc, rx_desc);
  242. if (QDF_IS_STATUS_ERROR(status)) {
  243. if (qdf_unlikely(rx_desc && rx_desc->nbuf)) {
  244. qdf_assert_always(!rx_desc->unmapped);
  245. dp_ipa_reo_ctx_buf_mapping_lock(
  246. soc,
  247. reo_ring_num);
  248. dp_ipa_handle_rx_buf_smmu_mapping(
  249. soc,
  250. rx_desc->nbuf,
  251. RX_DATA_BUFFER_SIZE,
  252. false);
  253. qdf_nbuf_unmap_nbytes_single(
  254. soc->osdev,
  255. rx_desc->nbuf,
  256. QDF_DMA_FROM_DEVICE,
  257. RX_DATA_BUFFER_SIZE);
  258. rx_desc->unmapped = 1;
  259. dp_ipa_reo_ctx_buf_mapping_unlock(
  260. soc,
  261. reo_ring_num);
  262. dp_rx_buffer_pool_nbuf_free(soc, rx_desc->nbuf,
  263. rx_desc->pool_id);
  264. dp_rx_add_to_free_desc_list(
  265. &head[rx_desc->pool_id],
  266. &tail[rx_desc->pool_id],
  267. rx_desc);
  268. }
  269. hal_srng_dst_get_next(hal_soc, hal_ring_hdl);
  270. continue;
  271. }
  272. /*
  273. * this is a unlikely scenario where the host is reaping
  274. * a descriptor which it already reaped just a while ago
  275. * but is yet to replenish it back to HW.
  276. * In this case host will dump the last 128 descriptors
  277. * including the software descriptor rx_desc and assert.
  278. */
  279. if (qdf_unlikely(!rx_desc->in_use)) {
  280. DP_STATS_INC(soc, rx.err.hal_reo_dest_dup, 1);
  281. dp_info_rl("Reaping rx_desc not in use!");
  282. dp_rx_dump_info_and_assert(soc, hal_ring_hdl,
  283. ring_desc, rx_desc);
  284. /* ignore duplicate RX desc and continue to process */
  285. /* Pop out the descriptor */
  286. hal_srng_dst_get_next(hal_soc, hal_ring_hdl);
  287. continue;
  288. }
  289. status = dp_rx_desc_nbuf_sanity_check(soc, ring_desc, rx_desc);
  290. if (qdf_unlikely(QDF_IS_STATUS_ERROR(status))) {
  291. DP_STATS_INC(soc, rx.err.nbuf_sanity_fail, 1);
  292. dp_info_rl("Nbuf sanity check failure!");
  293. dp_rx_dump_info_and_assert(soc, hal_ring_hdl,
  294. ring_desc, rx_desc);
  295. rx_desc->in_err_state = 1;
  296. hal_srng_dst_get_next(hal_soc, hal_ring_hdl);
  297. continue;
  298. }
  299. if (qdf_unlikely(!dp_rx_desc_check_magic(rx_desc))) {
  300. dp_err("Invalid rx_desc cookie=%d", rx_buf_cookie);
  301. DP_STATS_INC(soc, rx.err.rx_desc_invalid_magic, 1);
  302. dp_rx_dump_info_and_assert(soc, hal_ring_hdl,
  303. ring_desc, rx_desc);
  304. }
  305. /* Get MPDU DESC info */
  306. hal_rx_mpdu_desc_info_get_be(ring_desc, &mpdu_desc_info);
  307. /* Get MSDU DESC info */
  308. hal_rx_msdu_desc_info_get_be(ring_desc, &msdu_desc_info);
  309. if (qdf_unlikely(msdu_desc_info.msdu_flags &
  310. HAL_MSDU_F_MSDU_CONTINUATION)) {
  311. /* previous msdu has end bit set, so current one is
  312. * the new MPDU
  313. */
  314. if (is_prev_msdu_last) {
  315. /* Get number of entries available in HW ring */
  316. num_entries_avail =
  317. hal_srng_dst_num_valid(hal_soc,
  318. hal_ring_hdl, 1);
  319. /* For new MPDU check if we can read complete
  320. * MPDU by comparing the number of buffers
  321. * available and number of buffers needed to
  322. * reap this MPDU
  323. */
  324. if ((msdu_desc_info.msdu_len /
  325. (RX_DATA_BUFFER_SIZE -
  326. soc->rx_pkt_tlv_size) + 1) >
  327. num_entries_avail) {
  328. DP_STATS_INC(soc,
  329. rx.msdu_scatter_wait_break,
  330. 1);
  331. dp_rx_cookie_reset_invalid_bit(
  332. ring_desc);
  333. break;
  334. }
  335. is_prev_msdu_last = false;
  336. }
  337. }
  338. core_id = smp_processor_id();
  339. DP_STATS_INC(soc, rx.ring_packets[core_id][reo_ring_num], 1);
  340. if (mpdu_desc_info.mpdu_flags & HAL_MPDU_F_RETRY_BIT)
  341. qdf_nbuf_set_rx_retry_flag(rx_desc->nbuf, 1);
  342. if (qdf_unlikely(mpdu_desc_info.mpdu_flags &
  343. HAL_MPDU_F_RAW_AMPDU))
  344. qdf_nbuf_set_raw_frame(rx_desc->nbuf, 1);
  345. if (!is_prev_msdu_last &&
  346. msdu_desc_info.msdu_flags & HAL_MSDU_F_LAST_MSDU_IN_MPDU)
  347. is_prev_msdu_last = true;
  348. /* Pop out the descriptor*/
  349. hal_srng_dst_get_next(hal_soc, hal_ring_hdl);
  350. rx_bufs_reaped[rx_desc->pool_id]++;
  351. peer_mdata = mpdu_desc_info.peer_meta_data;
  352. QDF_NBUF_CB_RX_PEER_ID(rx_desc->nbuf) =
  353. dp_rx_peer_metadata_peer_id_get_be(soc, peer_mdata);
  354. QDF_NBUF_CB_RX_VDEV_ID(rx_desc->nbuf) =
  355. dp_rx_peer_metadata_vdev_id_get_be(soc, peer_mdata);
  356. /* to indicate whether this msdu is rx offload */
  357. pkt_capture_offload =
  358. DP_PEER_METADATA_OFFLOAD_GET_BE(peer_mdata);
  359. /*
  360. * save msdu flags first, last and continuation msdu in
  361. * nbuf->cb, also save mcbc, is_da_valid, is_sa_valid and
  362. * length to nbuf->cb. This ensures the info required for
  363. * per pkt processing is always in the same cache line.
  364. * This helps in improving throughput for smaller pkt
  365. * sizes.
  366. */
  367. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_FIRST_MSDU_IN_MPDU)
  368. qdf_nbuf_set_rx_chfrag_start(rx_desc->nbuf, 1);
  369. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_MSDU_CONTINUATION)
  370. qdf_nbuf_set_rx_chfrag_cont(rx_desc->nbuf, 1);
  371. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_LAST_MSDU_IN_MPDU)
  372. qdf_nbuf_set_rx_chfrag_end(rx_desc->nbuf, 1);
  373. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_DA_IS_MCBC)
  374. qdf_nbuf_set_da_mcbc(rx_desc->nbuf, 1);
  375. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_DA_IS_VALID)
  376. qdf_nbuf_set_da_valid(rx_desc->nbuf, 1);
  377. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_SA_IS_VALID)
  378. qdf_nbuf_set_sa_valid(rx_desc->nbuf, 1);
  379. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_INTRA_BSS)
  380. qdf_nbuf_set_intra_bss(rx_desc->nbuf, 1);
  381. if (qdf_likely(mpdu_desc_info.mpdu_flags &
  382. HAL_MPDU_F_QOS_CONTROL_VALID))
  383. qdf_nbuf_set_tid_val(rx_desc->nbuf, mpdu_desc_info.tid);
  384. /* set sw exception */
  385. qdf_nbuf_set_rx_reo_dest_ind_or_sw_excpt(
  386. rx_desc->nbuf,
  387. hal_rx_sw_exception_get_be(ring_desc));
  388. QDF_NBUF_CB_RX_PKT_LEN(rx_desc->nbuf) = msdu_desc_info.msdu_len;
  389. QDF_NBUF_CB_RX_CTX_ID(rx_desc->nbuf) = reo_ring_num;
  390. /*
  391. * move unmap after scattered msdu waiting break logic
  392. * in case double skb unmap happened.
  393. */
  394. rx_desc_pool = &soc->rx_desc_buf[rx_desc->pool_id];
  395. dp_ipa_reo_ctx_buf_mapping_lock(soc, reo_ring_num);
  396. dp_ipa_handle_rx_buf_smmu_mapping(soc, rx_desc->nbuf,
  397. rx_desc_pool->buf_size,
  398. false);
  399. qdf_nbuf_unmap_nbytes_single(soc->osdev, rx_desc->nbuf,
  400. QDF_DMA_FROM_DEVICE,
  401. rx_desc_pool->buf_size);
  402. rx_desc->unmapped = 1;
  403. dp_ipa_reo_ctx_buf_mapping_unlock(soc, reo_ring_num);
  404. DP_RX_PROCESS_NBUF(soc, nbuf_head, nbuf_tail, ebuf_head,
  405. ebuf_tail, rx_desc);
  406. /*
  407. * if continuation bit is set then we have MSDU spread
  408. * across multiple buffers, let us not decrement quota
  409. * till we reap all buffers of that MSDU.
  410. */
  411. if (qdf_likely(!qdf_nbuf_is_rx_chfrag_cont(rx_desc->nbuf)))
  412. quota -= 1;
  413. dp_rx_add_to_free_desc_list(&head[rx_desc->pool_id],
  414. &tail[rx_desc->pool_id], rx_desc);
  415. num_rx_bufs_reaped++;
  416. /*
  417. * only if complete msdu is received for scatter case,
  418. * then allow break.
  419. */
  420. if (is_prev_msdu_last &&
  421. dp_rx_reap_loop_pkt_limit_hit(soc, num_rx_bufs_reaped,
  422. max_reap_limit))
  423. break;
  424. }
  425. done:
  426. dp_rx_srng_access_end(int_ctx, soc, hal_ring_hdl);
  427. replenish_soc = dp_rx_replensih_soc_get(soc, reo_ring_num);
  428. for (mac_id = 0; mac_id < MAX_PDEV_CNT; mac_id++) {
  429. /*
  430. * continue with next mac_id if no pkts were reaped
  431. * from that pool
  432. */
  433. if (!rx_bufs_reaped[mac_id])
  434. continue;
  435. dp_rxdma_srng = &replenish_soc->rx_refill_buf_ring[mac_id];
  436. rx_desc_pool = &replenish_soc->rx_desc_buf[mac_id];
  437. dp_rx_buffers_replenish(replenish_soc, mac_id, dp_rxdma_srng,
  438. rx_desc_pool, rx_bufs_reaped[mac_id],
  439. &head[mac_id], &tail[mac_id]);
  440. }
  441. dp_verbose_debug("replenished %u\n", rx_bufs_reaped[0]);
  442. /* Peer can be NULL is case of LFR */
  443. if (qdf_likely(peer))
  444. vdev = NULL;
  445. /*
  446. * BIG loop where each nbuf is dequeued from global queue,
  447. * processed and queued back on a per vdev basis. These nbufs
  448. * are sent to stack as and when we run out of nbufs
  449. * or a new nbuf dequeued from global queue has a different
  450. * vdev when compared to previous nbuf.
  451. */
  452. nbuf = nbuf_head;
  453. while (nbuf) {
  454. next = nbuf->next;
  455. if (qdf_unlikely(dp_rx_is_raw_frame_dropped(nbuf))) {
  456. nbuf = next;
  457. DP_STATS_INC(soc, rx.err.raw_frm_drop, 1);
  458. continue;
  459. }
  460. rx_tlv_hdr = qdf_nbuf_data(nbuf);
  461. vdev_id = QDF_NBUF_CB_RX_VDEV_ID(nbuf);
  462. peer_id = QDF_NBUF_CB_RX_PEER_ID(nbuf);
  463. if (dp_rx_is_list_ready(deliver_list_head, vdev, peer,
  464. peer_id, vdev_id)) {
  465. dp_rx_deliver_to_stack(soc, vdev, peer,
  466. deliver_list_head,
  467. deliver_list_tail);
  468. deliver_list_head = NULL;
  469. deliver_list_tail = NULL;
  470. }
  471. /* Get TID from struct cb->tid_val, save to tid */
  472. if (qdf_nbuf_is_rx_chfrag_start(nbuf))
  473. tid = qdf_nbuf_get_tid_val(nbuf);
  474. if (qdf_unlikely(!peer)) {
  475. peer = dp_peer_get_ref_by_id(soc, peer_id,
  476. DP_MOD_ID_RX);
  477. } else if (peer && peer->peer_id != peer_id) {
  478. dp_peer_unref_delete(peer, DP_MOD_ID_RX);
  479. peer = dp_peer_get_ref_by_id(soc, peer_id,
  480. DP_MOD_ID_RX);
  481. }
  482. if (peer) {
  483. QDF_NBUF_CB_DP_TRACE_PRINT(nbuf) = false;
  484. qdf_dp_trace_set_track(nbuf, QDF_RX);
  485. QDF_NBUF_CB_RX_DP_TRACE(nbuf) = 1;
  486. QDF_NBUF_CB_RX_PACKET_TRACK(nbuf) =
  487. QDF_NBUF_RX_PKT_DATA_TRACK;
  488. }
  489. rx_bufs_used++;
  490. if (qdf_likely(peer)) {
  491. vdev = peer->vdev;
  492. } else {
  493. nbuf->next = NULL;
  494. dp_rx_deliver_to_pkt_capture_no_peer(
  495. soc, nbuf, pkt_capture_offload);
  496. if (!pkt_capture_offload)
  497. dp_rx_deliver_to_stack_no_peer(soc, nbuf);
  498. nbuf = next;
  499. continue;
  500. }
  501. if (qdf_unlikely(!vdev)) {
  502. qdf_nbuf_free(nbuf);
  503. nbuf = next;
  504. DP_STATS_INC(soc, rx.err.invalid_vdev, 1);
  505. continue;
  506. }
  507. /* when hlos tid override is enabled, save tid in
  508. * skb->priority
  509. */
  510. if (qdf_unlikely(vdev->skip_sw_tid_classification &
  511. DP_TXRX_HLOS_TID_OVERRIDE_ENABLED))
  512. qdf_nbuf_set_priority(nbuf, tid);
  513. rx_pdev = vdev->pdev;
  514. DP_RX_TID_SAVE(nbuf, tid);
  515. if (qdf_unlikely(rx_pdev->delay_stats_flag) ||
  516. qdf_unlikely(wlan_cfg_is_peer_ext_stats_enabled(
  517. soc->wlan_cfg_ctx)))
  518. qdf_nbuf_set_timestamp(nbuf);
  519. tid_stats =
  520. &rx_pdev->stats.tid_stats.tid_rx_stats[reo_ring_num][tid];
  521. /*
  522. * Check if DMA completed -- msdu_done is the last bit
  523. * to be written
  524. */
  525. if (qdf_unlikely(!qdf_nbuf_is_rx_chfrag_cont(nbuf) &&
  526. !hal_rx_attn_msdu_done_get(hal_soc,
  527. rx_tlv_hdr))) {
  528. dp_err("MSDU DONE failure");
  529. DP_STATS_INC(soc, rx.err.msdu_done_fail, 1);
  530. hal_rx_dump_pkt_tlvs(hal_soc, rx_tlv_hdr,
  531. QDF_TRACE_LEVEL_INFO);
  532. tid_stats->fail_cnt[MSDU_DONE_FAILURE]++;
  533. qdf_nbuf_free(nbuf);
  534. qdf_assert(0);
  535. nbuf = next;
  536. continue;
  537. }
  538. DP_HIST_PACKET_COUNT_INC(vdev->pdev->pdev_id);
  539. /*
  540. * First IF condition:
  541. * 802.11 Fragmented pkts are reinjected to REO
  542. * HW block as SG pkts and for these pkts we only
  543. * need to pull the RX TLVS header length.
  544. * Second IF condition:
  545. * The below condition happens when an MSDU is spread
  546. * across multiple buffers. This can happen in two cases
  547. * 1. The nbuf size is smaller then the received msdu.
  548. * ex: we have set the nbuf size to 2048 during
  549. * nbuf_alloc. but we received an msdu which is
  550. * 2304 bytes in size then this msdu is spread
  551. * across 2 nbufs.
  552. *
  553. * 2. AMSDUs when RAW mode is enabled.
  554. * ex: 1st MSDU is in 1st nbuf and 2nd MSDU is spread
  555. * across 1st nbuf and 2nd nbuf and last MSDU is
  556. * spread across 2nd nbuf and 3rd nbuf.
  557. *
  558. * for these scenarios let us create a skb frag_list and
  559. * append these buffers till the last MSDU of the AMSDU
  560. * Third condition:
  561. * This is the most likely case, we receive 802.3 pkts
  562. * decapsulated by HW, here we need to set the pkt length.
  563. */
  564. hal_rx_msdu_metadata_get(hal_soc, rx_tlv_hdr, &msdu_metadata);
  565. if (qdf_unlikely(qdf_nbuf_is_frag(nbuf))) {
  566. bool is_mcbc, is_sa_vld, is_da_vld;
  567. is_mcbc = hal_rx_msdu_end_da_is_mcbc_get(soc->hal_soc,
  568. rx_tlv_hdr);
  569. is_sa_vld =
  570. hal_rx_msdu_end_sa_is_valid_get(soc->hal_soc,
  571. rx_tlv_hdr);
  572. is_da_vld =
  573. hal_rx_msdu_end_da_is_valid_get(soc->hal_soc,
  574. rx_tlv_hdr);
  575. qdf_nbuf_set_da_mcbc(nbuf, is_mcbc);
  576. qdf_nbuf_set_da_valid(nbuf, is_da_vld);
  577. qdf_nbuf_set_sa_valid(nbuf, is_sa_vld);
  578. qdf_nbuf_pull_head(nbuf, soc->rx_pkt_tlv_size);
  579. } else if (qdf_nbuf_is_rx_chfrag_cont(nbuf)) {
  580. msdu_len = QDF_NBUF_CB_RX_PKT_LEN(nbuf);
  581. nbuf = dp_rx_sg_create(soc, nbuf);
  582. next = nbuf->next;
  583. if (qdf_nbuf_is_raw_frame(nbuf)) {
  584. DP_STATS_INC(vdev->pdev, rx_raw_pkts, 1);
  585. DP_STATS_INC_PKT(peer, rx.raw, 1, msdu_len);
  586. } else {
  587. qdf_nbuf_free(nbuf);
  588. DP_STATS_INC(soc, rx.err.scatter_msdu, 1);
  589. dp_info_rl("scatter msdu len %d, dropped",
  590. msdu_len);
  591. nbuf = next;
  592. continue;
  593. }
  594. } else {
  595. msdu_len = QDF_NBUF_CB_RX_PKT_LEN(nbuf);
  596. pkt_len = msdu_len +
  597. msdu_metadata.l3_hdr_pad +
  598. soc->rx_pkt_tlv_size;
  599. qdf_nbuf_set_pktlen(nbuf, pkt_len);
  600. dp_rx_skip_tlvs(soc, nbuf, msdu_metadata.l3_hdr_pad);
  601. }
  602. /*
  603. * process frame for mulitpass phrase processing
  604. */
  605. if (qdf_unlikely(vdev->multipass_en)) {
  606. if (dp_rx_multipass_process(peer, nbuf, tid) == false) {
  607. DP_STATS_INC(peer, rx.multipass_rx_pkt_drop, 1);
  608. qdf_nbuf_free(nbuf);
  609. nbuf = next;
  610. continue;
  611. }
  612. }
  613. if (!dp_wds_rx_policy_check(rx_tlv_hdr, vdev, peer)) {
  614. dp_rx_err("%pK: Policy Check Drop pkt", soc);
  615. tid_stats->fail_cnt[POLICY_CHECK_DROP]++;
  616. /* Drop & free packet */
  617. qdf_nbuf_free(nbuf);
  618. /* Statistics */
  619. nbuf = next;
  620. continue;
  621. }
  622. if (qdf_unlikely(peer && (peer->nawds_enabled) &&
  623. (qdf_nbuf_is_da_mcbc(nbuf)) &&
  624. (hal_rx_get_mpdu_mac_ad4_valid(soc->hal_soc,
  625. rx_tlv_hdr) ==
  626. false))) {
  627. tid_stats->fail_cnt[NAWDS_MCAST_DROP]++;
  628. DP_STATS_INC(peer, rx.nawds_mcast_drop, 1);
  629. qdf_nbuf_free(nbuf);
  630. nbuf = next;
  631. continue;
  632. }
  633. /*
  634. * Drop non-EAPOL frames from unauthorized peer.
  635. */
  636. if (qdf_likely(peer) && qdf_unlikely(!peer->authorize) &&
  637. !qdf_nbuf_is_raw_frame(nbuf)) {
  638. bool is_eapol = qdf_nbuf_is_ipv4_eapol_pkt(nbuf) ||
  639. qdf_nbuf_is_ipv4_wapi_pkt(nbuf);
  640. if (!is_eapol) {
  641. DP_STATS_INC(soc,
  642. rx.err.peer_unauth_rx_pkt_drop,
  643. 1);
  644. qdf_nbuf_free(nbuf);
  645. nbuf = next;
  646. continue;
  647. }
  648. }
  649. if (soc->process_rx_status)
  650. dp_rx_cksum_offload(vdev->pdev, nbuf, rx_tlv_hdr);
  651. /* Update the protocol tag in SKB based on CCE metadata */
  652. dp_rx_update_protocol_tag(soc, vdev, nbuf, rx_tlv_hdr,
  653. reo_ring_num, false, true);
  654. /* Update the flow tag in SKB based on FSE metadata */
  655. dp_rx_update_flow_tag(soc, vdev, nbuf, rx_tlv_hdr, true);
  656. dp_rx_msdu_stats_update(soc, nbuf, rx_tlv_hdr, peer,
  657. reo_ring_num, tid_stats);
  658. if (qdf_unlikely(vdev->mesh_vdev)) {
  659. if (dp_rx_filter_mesh_packets(vdev, nbuf, rx_tlv_hdr)
  660. == QDF_STATUS_SUCCESS) {
  661. dp_rx_info("%pK: mesh pkt filtered", soc);
  662. tid_stats->fail_cnt[MESH_FILTER_DROP]++;
  663. DP_STATS_INC(vdev->pdev, dropped.mesh_filter,
  664. 1);
  665. qdf_nbuf_free(nbuf);
  666. nbuf = next;
  667. continue;
  668. }
  669. dp_rx_fill_mesh_stats(vdev, nbuf, rx_tlv_hdr, peer);
  670. }
  671. if (qdf_likely(vdev->rx_decap_type ==
  672. htt_cmn_pkt_type_ethernet) &&
  673. qdf_likely(!vdev->mesh_vdev)) {
  674. dp_rx_wds_learn(soc, vdev,
  675. rx_tlv_hdr,
  676. peer,
  677. nbuf,
  678. msdu_metadata);
  679. /* Intrabss-fwd */
  680. if (dp_rx_check_ap_bridge(vdev))
  681. if (dp_rx_intrabss_fwd_be(soc, peer, rx_tlv_hdr,
  682. nbuf,
  683. msdu_metadata)) {
  684. nbuf = next;
  685. tid_stats->intrabss_cnt++;
  686. continue; /* Get next desc */
  687. }
  688. }
  689. dp_rx_fill_gro_info(soc, rx_tlv_hdr, nbuf, &rx_ol_pkt_cnt);
  690. dp_rx_update_stats(soc, nbuf);
  691. DP_RX_LIST_APPEND(deliver_list_head,
  692. deliver_list_tail,
  693. nbuf);
  694. DP_STATS_INC_PKT(peer, rx.to_stack, 1,
  695. QDF_NBUF_CB_RX_PKT_LEN(nbuf));
  696. if (qdf_unlikely(peer->in_twt))
  697. DP_STATS_INC_PKT(peer, rx.to_stack_twt, 1,
  698. QDF_NBUF_CB_RX_PKT_LEN(nbuf));
  699. tid_stats->delivered_to_stack++;
  700. nbuf = next;
  701. }
  702. if (qdf_likely(deliver_list_head)) {
  703. if (qdf_likely(peer)) {
  704. dp_rx_deliver_to_pkt_capture(soc, vdev->pdev, peer_id,
  705. pkt_capture_offload,
  706. deliver_list_head);
  707. if (!pkt_capture_offload)
  708. dp_rx_deliver_to_stack(soc, vdev, peer,
  709. deliver_list_head,
  710. deliver_list_tail);
  711. } else {
  712. nbuf = deliver_list_head;
  713. while (nbuf) {
  714. next = nbuf->next;
  715. nbuf->next = NULL;
  716. dp_rx_deliver_to_stack_no_peer(soc, nbuf);
  717. nbuf = next;
  718. }
  719. }
  720. }
  721. if (qdf_likely(peer))
  722. dp_peer_unref_delete(peer, DP_MOD_ID_RX);
  723. /*
  724. * If we are processing in near-full condition, there are 3 scenario
  725. * 1) Ring entries has reached critical state
  726. * 2) Ring entries are still near high threshold
  727. * 3) Ring entries are below the safe level
  728. *
  729. * One more loop will move the state to normal processing and yield
  730. */
  731. if (ring_near_full && quota)
  732. goto more_data;
  733. if (dp_rx_enable_eol_data_check(soc) && rx_bufs_used) {
  734. if (quota) {
  735. num_pending =
  736. dp_rx_srng_get_num_pending(hal_soc,
  737. hal_ring_hdl,
  738. num_entries,
  739. &near_full);
  740. if (num_pending) {
  741. DP_STATS_INC(soc, rx.hp_oos2, 1);
  742. if (!hif_exec_should_yield(scn, intr_id))
  743. goto more_data;
  744. if (qdf_unlikely(near_full)) {
  745. DP_STATS_INC(soc, rx.near_full, 1);
  746. goto more_data;
  747. }
  748. }
  749. }
  750. if (vdev && vdev->osif_fisa_flush)
  751. vdev->osif_fisa_flush(soc, reo_ring_num);
  752. if (vdev && vdev->osif_gro_flush && rx_ol_pkt_cnt) {
  753. vdev->osif_gro_flush(vdev->osif_vdev,
  754. reo_ring_num);
  755. }
  756. }
  757. /* Update histogram statistics by looping through pdev's */
  758. DP_RX_HIST_STATS_PER_PDEV();
  759. return rx_bufs_used; /* Assume no scale factor for now */
  760. }
  761. #ifdef RX_DESC_MULTI_PAGE_ALLOC
  762. /**
  763. * dp_rx_desc_pool_init_be_cc() - initial RX desc pool for cookie conversion
  764. * @soc: Handle to DP Soc structure
  765. * @rx_desc_pool: Rx descriptor pool handler
  766. * @pool_id: Rx descriptor pool ID
  767. *
  768. * Return: QDF_STATUS_SUCCESS - succeeded, others - failed
  769. */
  770. static QDF_STATUS
  771. dp_rx_desc_pool_init_be_cc(struct dp_soc *soc,
  772. struct rx_desc_pool *rx_desc_pool,
  773. uint32_t pool_id)
  774. {
  775. struct dp_hw_cookie_conversion_t *cc_ctx;
  776. struct dp_soc_be *be_soc;
  777. union dp_rx_desc_list_elem_t *rx_desc_elem;
  778. struct dp_spt_page_desc *page_desc;
  779. uint32_t ppt_idx = 0;
  780. uint32_t avail_entry_index = 0;
  781. if (!rx_desc_pool->pool_size) {
  782. dp_err("desc_num 0 !!");
  783. return QDF_STATUS_E_FAILURE;
  784. }
  785. be_soc = dp_get_be_soc_from_dp_soc(soc);
  786. cc_ctx = &be_soc->rx_cc_ctx[pool_id];
  787. page_desc = &cc_ctx->page_desc_base[0];
  788. rx_desc_elem = rx_desc_pool->freelist;
  789. while (rx_desc_elem) {
  790. if (avail_entry_index == 0) {
  791. if (ppt_idx >= cc_ctx->total_page_num) {
  792. dp_alert("insufficient secondary page tables");
  793. qdf_assert_always(0);
  794. }
  795. page_desc = &cc_ctx->page_desc_base[ppt_idx++];
  796. }
  797. /* put each RX Desc VA to SPT pages and
  798. * get corresponding ID
  799. */
  800. DP_CC_SPT_PAGE_UPDATE_VA(page_desc->page_v_addr,
  801. avail_entry_index,
  802. &rx_desc_elem->rx_desc);
  803. rx_desc_elem->rx_desc.cookie =
  804. dp_cc_desc_id_generate(page_desc->ppt_index,
  805. avail_entry_index);
  806. rx_desc_elem->rx_desc.pool_id = pool_id;
  807. rx_desc_elem->rx_desc.in_use = 0;
  808. rx_desc_elem = rx_desc_elem->next;
  809. avail_entry_index = (avail_entry_index + 1) &
  810. DP_CC_SPT_PAGE_MAX_ENTRIES_MASK;
  811. }
  812. return QDF_STATUS_SUCCESS;
  813. }
  814. #else
  815. static QDF_STATUS
  816. dp_rx_desc_pool_init_be_cc(struct dp_soc *soc,
  817. struct rx_desc_pool *rx_desc_pool,
  818. uint32_t pool_id)
  819. {
  820. struct dp_hw_cookie_conversion_t *cc_ctx;
  821. struct dp_soc_be *be_soc;
  822. struct dp_spt_page_desc *page_desc;
  823. uint32_t ppt_idx = 0;
  824. uint32_t avail_entry_index = 0;
  825. int i = 0;
  826. if (!rx_desc_pool->pool_size) {
  827. dp_err("desc_num 0 !!");
  828. return QDF_STATUS_E_FAILURE;
  829. }
  830. be_soc = dp_get_be_soc_from_dp_soc(soc);
  831. cc_ctx = &be_soc->rx_cc_ctx[pool_id];
  832. page_desc = &cc_ctx->page_desc_base[0];
  833. for (i = 0; i <= rx_desc_pool->pool_size - 1; i++) {
  834. if (i == rx_desc_pool->pool_size - 1)
  835. rx_desc_pool->array[i].next = NULL;
  836. else
  837. rx_desc_pool->array[i].next =
  838. &rx_desc_pool->array[i + 1];
  839. if (avail_entry_index == 0) {
  840. if (ppt_idx >= cc_ctx->total_page_num) {
  841. dp_alert("insufficient secondary page tables");
  842. qdf_assert_always(0);
  843. }
  844. page_desc = &cc_ctx->page_desc_base[ppt_idx++];
  845. }
  846. /* put each RX Desc VA to SPT pages and
  847. * get corresponding ID
  848. */
  849. DP_CC_SPT_PAGE_UPDATE_VA(page_desc->page_v_addr,
  850. avail_entry_index,
  851. &rx_desc_pool->array[i].rx_desc);
  852. rx_desc_pool->array[i].rx_desc.cookie =
  853. dp_cc_desc_id_generate(page_desc->ppt_index,
  854. avail_entry_index);
  855. rx_desc_pool->array[i].rx_desc.pool_id = pool_id;
  856. rx_desc_pool->array[i].rx_desc.in_use = 0;
  857. avail_entry_index = (avail_entry_index + 1) &
  858. DP_CC_SPT_PAGE_MAX_ENTRIES_MASK;
  859. }
  860. return QDF_STATUS_SUCCESS;
  861. }
  862. #endif
  863. static void
  864. dp_rx_desc_pool_deinit_be_cc(struct dp_soc *soc,
  865. struct rx_desc_pool *rx_desc_pool,
  866. uint32_t pool_id)
  867. {
  868. struct dp_spt_page_desc *page_desc;
  869. struct dp_soc_be *be_soc;
  870. int i = 0;
  871. struct dp_hw_cookie_conversion_t *cc_ctx;
  872. be_soc = dp_get_be_soc_from_dp_soc(soc);
  873. cc_ctx = &be_soc->rx_cc_ctx[pool_id];
  874. for (i = 0; i < cc_ctx->total_page_num; i++) {
  875. page_desc = &cc_ctx->page_desc_base[i];
  876. qdf_mem_zero(page_desc->page_v_addr, qdf_page_size);
  877. }
  878. }
  879. QDF_STATUS dp_rx_desc_pool_init_be(struct dp_soc *soc,
  880. struct rx_desc_pool *rx_desc_pool,
  881. uint32_t pool_id)
  882. {
  883. QDF_STATUS status = QDF_STATUS_SUCCESS;
  884. /* Only regular RX buffer desc pool use HW cookie conversion */
  885. if (rx_desc_pool->desc_type == DP_RX_DESC_BUF_TYPE) {
  886. dp_info("rx_desc_buf pool init");
  887. status = dp_rx_desc_pool_init_be_cc(soc,
  888. rx_desc_pool,
  889. pool_id);
  890. } else {
  891. dp_info("non_rx_desc_buf_pool init");
  892. status = dp_rx_desc_pool_init_generic(soc, rx_desc_pool,
  893. pool_id);
  894. }
  895. return status;
  896. }
  897. void dp_rx_desc_pool_deinit_be(struct dp_soc *soc,
  898. struct rx_desc_pool *rx_desc_pool,
  899. uint32_t pool_id)
  900. {
  901. if (rx_desc_pool->desc_type == DP_RX_DESC_BUF_TYPE)
  902. dp_rx_desc_pool_deinit_be_cc(soc, rx_desc_pool, pool_id);
  903. }
  904. #ifdef DP_FEATURE_HW_COOKIE_CONVERSION
  905. #ifdef DP_HW_COOKIE_CONVERT_EXCEPTION
  906. QDF_STATUS dp_wbm_get_rx_desc_from_hal_desc_be(struct dp_soc *soc,
  907. void *ring_desc,
  908. struct dp_rx_desc **r_rx_desc)
  909. {
  910. if (hal_rx_wbm_get_cookie_convert_done(ring_desc)) {
  911. /* HW cookie conversion done */
  912. *r_rx_desc = (struct dp_rx_desc *)
  913. hal_rx_wbm_get_desc_va(ring_desc);
  914. } else {
  915. /* SW do cookie conversion */
  916. uint32_t cookie = HAL_RX_BUF_COOKIE_GET(ring_desc);
  917. *r_rx_desc = (struct dp_rx_desc *)
  918. dp_cc_desc_find(soc, cookie);
  919. }
  920. return QDF_STATUS_SUCCESS;
  921. }
  922. #else
  923. QDF_STATUS dp_wbm_get_rx_desc_from_hal_desc_be(struct dp_soc *soc,
  924. void *ring_desc,
  925. struct dp_rx_desc **r_rx_desc)
  926. {
  927. *r_rx_desc = (struct dp_rx_desc *)
  928. hal_rx_wbm_get_desc_va(ring_desc);
  929. return QDF_STATUS_SUCCESS;
  930. }
  931. #endif /* DP_HW_COOKIE_CONVERT_EXCEPTION */
  932. #else
  933. QDF_STATUS dp_wbm_get_rx_desc_from_hal_desc_be(struct dp_soc *soc,
  934. void *ring_desc,
  935. struct dp_rx_desc **r_rx_desc)
  936. {
  937. /* SW do cookie conversion */
  938. uint32_t cookie = HAL_RX_BUF_COOKIE_GET(ring_desc);
  939. *r_rx_desc = (struct dp_rx_desc *)
  940. dp_cc_desc_find(soc, cookie);
  941. return QDF_STATUS_SUCCESS;
  942. }
  943. #endif /* DP_FEATURE_HW_COOKIE_CONVERSION */
  944. struct dp_rx_desc *dp_rx_desc_cookie_2_va_be(struct dp_soc *soc,
  945. uint32_t cookie)
  946. {
  947. return (struct dp_rx_desc *)dp_cc_desc_find(soc, cookie);
  948. }
  949. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  950. uint32_t dp_rx_nf_process(struct dp_intr *int_ctx,
  951. hal_ring_handle_t hal_ring_hdl,
  952. uint8_t reo_ring_num,
  953. uint32_t quota)
  954. {
  955. struct dp_soc *soc = int_ctx->soc;
  956. struct dp_srng *rx_ring = &soc->reo_dest_ring[reo_ring_num];
  957. uint32_t work_done = 0;
  958. if (dp_srng_get_near_full_level(soc, rx_ring) <
  959. DP_SRNG_THRESH_NEAR_FULL)
  960. return 0;
  961. qdf_atomic_set(&rx_ring->near_full, 1);
  962. work_done++;
  963. return work_done;
  964. }
  965. #endif
  966. #ifndef QCA_HOST_MODE_WIFI_DISABLED
  967. #ifdef WLAN_FEATURE_11BE_MLO
  968. /**
  969. * dp_rx_intrabss_fwd_mlo_allow() - check if MLO forwarding is allowed
  970. * @ta_peer: transmitter peer handle
  971. * @da_peer: destination peer handle
  972. *
  973. * Return: true - MLO forwarding case, false: not
  974. */
  975. static inline bool
  976. dp_rx_intrabss_fwd_mlo_allow(struct dp_peer *ta_peer,
  977. struct dp_peer *da_peer)
  978. {
  979. /* one of TA/DA peer should belong to MLO connection peer,
  980. * only MLD peer type is as expected
  981. */
  982. if (!IS_MLO_DP_MLD_PEER(ta_peer) &&
  983. !IS_MLO_DP_MLD_PEER(da_peer))
  984. return false;
  985. /* TA peer and DA peer's vdev should be partner MLO vdevs */
  986. if (dp_peer_find_mac_addr_cmp(&ta_peer->vdev->mld_mac_addr,
  987. &da_peer->vdev->mld_mac_addr))
  988. return false;
  989. return true;
  990. }
  991. #else
  992. static inline bool
  993. dp_rx_intrabss_fwd_mlo_allow(struct dp_peer *ta_peer,
  994. struct dp_peer *da_peer)
  995. {
  996. return false;
  997. }
  998. #endif
  999. #ifdef INTRA_BSS_FWD_OFFLOAD
  1000. /**
  1001. * dp_rx_intrabss_ucast_check_be() - Check if intrabss is allowed
  1002. for unicast frame
  1003. * @soc: SOC hanlde
  1004. * @nbuf: RX packet buffer
  1005. * @ta_peer: transmitter DP peer handle
  1006. * @msdu_metadata: MSDU meta data info
  1007. * @p_tx_vdev_id: get vdev id for Intra-BSS TX
  1008. *
  1009. * Return: true - intrabss allowed
  1010. false - not allow
  1011. */
  1012. static bool
  1013. dp_rx_intrabss_ucast_check_be(struct dp_soc *soc, qdf_nbuf_t nbuf,
  1014. struct dp_peer *ta_peer,
  1015. struct hal_rx_msdu_metadata *msdu_metadata,
  1016. uint8_t *p_tx_vdev_id)
  1017. {
  1018. uint16_t da_peer_id;
  1019. struct dp_peer *da_peer;
  1020. if (!qdf_nbuf_is_intra_bss(nbuf))
  1021. return false;
  1022. da_peer_id = dp_rx_peer_metadata_peer_id_get_be(
  1023. soc,
  1024. msdu_metadata->da_idx);
  1025. da_peer = dp_peer_get_ref_by_id(soc, da_peer_id, DP_MOD_ID_RX);
  1026. if (!da_peer)
  1027. return false;
  1028. *p_tx_vdev_id = da_peer->vdev->vdev_id;
  1029. dp_peer_unref_delete(da_peer, DP_MOD_ID_RX);
  1030. return true;
  1031. }
  1032. #else
  1033. static bool
  1034. dp_rx_intrabss_ucast_check_be(struct dp_soc *soc, qdf_nbuf_t nbuf,
  1035. struct dp_peer *ta_peer,
  1036. struct hal_rx_msdu_metadata *msdu_metadata,
  1037. uint8_t *p_tx_vdev_id)
  1038. {
  1039. uint16_t da_peer_id;
  1040. struct dp_peer *da_peer;
  1041. bool ret = false;
  1042. if (!qdf_nbuf_is_da_valid(nbuf) || qdf_nbuf_is_da_mcbc(nbuf))
  1043. return false;
  1044. da_peer_id = dp_rx_peer_metadata_peer_id_get_be(
  1045. soc,
  1046. msdu_metadata->da_idx);
  1047. da_peer = dp_peer_get_ref_by_id(soc, da_peer_id,
  1048. DP_MOD_ID_RX);
  1049. if (!da_peer)
  1050. return false;
  1051. *p_tx_vdev_id = da_peer->vdev->vdev_id;
  1052. /* If the source or destination peer in the isolation
  1053. * list then dont forward instead push to bridge stack.
  1054. */
  1055. if (dp_get_peer_isolation(ta_peer) ||
  1056. dp_get_peer_isolation(da_peer))
  1057. goto rel_da_peer;
  1058. if (da_peer->bss_peer || da_peer == ta_peer)
  1059. goto rel_da_peer;
  1060. /* Same vdev, support Inra-BSS */
  1061. if (da_peer->vdev == ta_peer->vdev) {
  1062. ret = true;
  1063. goto rel_da_peer;
  1064. }
  1065. /* MLO specific Intra-BSS check */
  1066. if (dp_rx_intrabss_fwd_mlo_allow(ta_peer, da_peer)) {
  1067. ret = true;
  1068. goto rel_da_peer;
  1069. }
  1070. rel_da_peer:
  1071. dp_peer_unref_delete(da_peer, DP_MOD_ID_RX);
  1072. return ret;
  1073. }
  1074. #endif
  1075. /*
  1076. * dp_rx_intrabss_fwd_be() - API for intrabss fwd. For EAPOL
  1077. * pkt with DA not equal to vdev mac addr, fwd is not allowed.
  1078. * @soc: core txrx main context
  1079. * @ta_peer: source peer entry
  1080. * @rx_tlv_hdr: start address of rx tlvs
  1081. * @nbuf: nbuf that has to be intrabss forwarded
  1082. * @msdu_metadata: msdu metadata
  1083. *
  1084. * Return: true if it is forwarded else false
  1085. */
  1086. bool dp_rx_intrabss_fwd_be(struct dp_soc *soc, struct dp_peer *ta_peer,
  1087. uint8_t *rx_tlv_hdr, qdf_nbuf_t nbuf,
  1088. struct hal_rx_msdu_metadata msdu_metadata)
  1089. {
  1090. uint8_t tx_vdev_id;
  1091. uint8_t tid = qdf_nbuf_get_tid_val(nbuf);
  1092. uint8_t ring_id = QDF_NBUF_CB_RX_CTX_ID(nbuf);
  1093. struct cdp_tid_rx_stats *tid_stats = &ta_peer->vdev->pdev->stats.
  1094. tid_stats.tid_rx_stats[ring_id][tid];
  1095. /* if it is a broadcast pkt (eg: ARP) and it is not its own
  1096. * source, then clone the pkt and send the cloned pkt for
  1097. * intra BSS forwarding and original pkt up the network stack
  1098. * Note: how do we handle multicast pkts. do we forward
  1099. * all multicast pkts as is or let a higher layer module
  1100. * like igmpsnoop decide whether to forward or not with
  1101. * Mcast enhancement.
  1102. */
  1103. if (qdf_nbuf_is_da_mcbc(nbuf) && !ta_peer->bss_peer)
  1104. return dp_rx_intrabss_mcbc_fwd(soc, ta_peer, rx_tlv_hdr,
  1105. nbuf, tid_stats);
  1106. if (dp_rx_intrabss_ucast_check_be(soc, nbuf, ta_peer,
  1107. &msdu_metadata, &tx_vdev_id))
  1108. return dp_rx_intrabss_ucast_fwd(soc, ta_peer, tx_vdev_id,
  1109. rx_tlv_hdr, nbuf, tid_stats);
  1110. return false;
  1111. }
  1112. #endif