msm_cvp_internal.h 9.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #ifndef _MSM_CVP_INTERNAL_H_
  6. #define _MSM_CVP_INTERNAL_H_
  7. #include <linux/atomic.h>
  8. #include <linux/sched.h>
  9. #include <linux/list.h>
  10. #include <linux/time.h>
  11. #include <linux/types.h>
  12. #include <linux/completion.h>
  13. #include <linux/wait.h>
  14. #include <linux/workqueue.h>
  15. #include <linux/interconnect.h>
  16. #include <linux/kref.h>
  17. #include <linux/cdev.h>
  18. #include <linux/slab.h>
  19. #include <linux/kthread.h>
  20. #include <linux/dma-mapping.h>
  21. #include "msm_cvp_core.h"
  22. #include <media/msm_eva_private.h>
  23. #include "cvp_hfi_api.h"
  24. #include "cvp_hfi_helper.h"
  25. #include <synx_api.h>
  26. #define MAX_SUPPORTED_INSTANCES 16
  27. #define MAX_DEBUGFS_NAME 50
  28. #define MAX_DSP_INIT_ATTEMPTS 16
  29. #define FENCE_WAIT_SIGNAL_TIMEOUT 100
  30. #define FENCE_WAIT_SIGNAL_RETRY_TIMES 20
  31. #define FENCE_BIT (1ULL << 63)
  32. #define FENCE_DMM_ICA_ENABLED_IDX 0
  33. #define FENCE_DMM_DS_IDX 1
  34. #define FENCE_DMM_OUTPUT_IDX 7
  35. #define SYS_MSG_START HAL_SYS_INIT_DONE
  36. #define SYS_MSG_END HAL_SYS_ERROR
  37. #define SESSION_MSG_START HAL_SESSION_EVENT_CHANGE
  38. #define SESSION_MSG_END HAL_SESSION_ERROR
  39. #define SYS_MSG_INDEX(__msg) (__msg - SYS_MSG_START)
  40. #define SESSION_MSG_INDEX(__msg) (__msg - SESSION_MSG_START)
  41. #define ARP_BUF_SIZE 0x300000
  42. #define CVP_RT_PRIO_THRESHOLD 1
  43. struct msm_cvp_inst;
  44. enum cvp_core_state {
  45. CVP_CORE_UNINIT = 0,
  46. CVP_CORE_INIT,
  47. CVP_CORE_INIT_DONE,
  48. };
  49. /*
  50. * Do not change the enum values unless
  51. * you know what you are doing
  52. */
  53. enum hw_block {
  54. CVP_FDU = 0x0001,
  55. CVP_ICA,
  56. CVP_MPU,
  57. CVP_OD
  58. };
  59. enum instance_state {
  60. MSM_CVP_CORE_UNINIT_DONE = 0x0001,
  61. MSM_CVP_CORE_INIT,
  62. MSM_CVP_CORE_INIT_DONE,
  63. MSM_CVP_OPEN,
  64. MSM_CVP_OPEN_DONE,
  65. MSM_CVP_CLOSE,
  66. MSM_CVP_CLOSE_DONE,
  67. MSM_CVP_CORE_UNINIT,
  68. MSM_CVP_CORE_INVALID
  69. };
  70. enum dsp_state {
  71. DSP_INVALID,
  72. DSP_UNINIT,
  73. DSP_PROBED,
  74. DSP_READY,
  75. DSP_SUSPEND,
  76. DSP_INACTIVE,
  77. };
  78. struct msm_cvp_common_data {
  79. char key[128];
  80. int value;
  81. };
  82. enum sku_version {
  83. SKU_VERSION_0 = 0,
  84. SKU_VERSION_1,
  85. SKU_VERSION_2,
  86. };
  87. enum vpu_version {
  88. VPU_VERSION_4 = 1,
  89. VPU_VERSION_5,
  90. };
  91. struct msm_cvp_ubwc_config_data {
  92. struct {
  93. u32 max_channel_override : 1;
  94. u32 mal_length_override : 1;
  95. u32 hb_override : 1;
  96. u32 bank_swzl_level_override : 1;
  97. u32 bank_spreading_override : 1;
  98. u32 reserved : 27;
  99. } override_bit_info;
  100. u32 max_channels;
  101. u32 mal_length;
  102. u32 highest_bank_bit;
  103. u32 bank_swzl_level;
  104. u32 bank_spreading;
  105. };
  106. struct msm_cvp_qos_setting {
  107. u32 axi_qos;
  108. u32 prioritylut_low;
  109. u32 prioritylut_high;
  110. u32 urgency_low;
  111. u32 dangerlut_low;
  112. u32 safelut_low;
  113. };
  114. struct msm_cvp_platform_data {
  115. struct msm_cvp_common_data *common_data;
  116. unsigned int common_data_length;
  117. unsigned int sku_version;
  118. uint32_t vpu_ver;
  119. unsigned int vm_id; /* pvm: 1; tvm: 2 */
  120. struct msm_cvp_ubwc_config_data *ubwc_config;
  121. struct msm_cvp_qos_setting *noc_qos;
  122. };
  123. struct msm_cvp_drv {
  124. struct mutex lock;
  125. struct list_head cores;
  126. int num_cores;
  127. struct dentry *debugfs_root;
  128. int thermal_level;
  129. u32 sku_version;
  130. struct kmem_cache *msg_cache;
  131. struct kmem_cache *frame_cache;
  132. struct kmem_cache *buf_cache;
  133. struct kmem_cache *smem_cache;
  134. char fw_version[CVP_VERSION_LENGTH];
  135. };
  136. enum profiling_points {
  137. SYS_INIT = 0,
  138. SESSION_INIT,
  139. LOAD_RESOURCES,
  140. FRAME_PROCESSING,
  141. FW_IDLE,
  142. MAX_PROFILING_POINTS,
  143. };
  144. struct cvp_clock_data {
  145. int buffer_counter;
  146. int load;
  147. int load_low;
  148. int load_norm;
  149. int load_high;
  150. int min_threshold;
  151. int max_threshold;
  152. unsigned long bitrate;
  153. unsigned long min_freq;
  154. unsigned long curr_freq;
  155. u32 ddr_bw;
  156. u32 sys_cache_bw;
  157. u32 operating_rate;
  158. u32 core_id;
  159. bool low_latency_mode;
  160. bool turbo_mode;
  161. };
  162. struct cvp_profile_data {
  163. int start;
  164. int stop;
  165. int cumulative;
  166. char name[64];
  167. int sampling;
  168. int average;
  169. };
  170. struct msm_cvp_debug {
  171. struct cvp_profile_data pdata[MAX_PROFILING_POINTS];
  172. int profile;
  173. int samples;
  174. };
  175. enum msm_cvp_modes {
  176. CVP_SECURE = BIT(0),
  177. CVP_TURBO = BIT(1),
  178. CVP_THUMBNAIL = BIT(2),
  179. CVP_LOW_POWER = BIT(3),
  180. CVP_REALTIME = BIT(4),
  181. };
  182. #define MAX_NUM_MSGS_PER_SESSION 128
  183. #define CVP_MAX_WAIT_TIME 2000
  184. struct cvp_session_msg {
  185. struct list_head node;
  186. struct cvp_hfi_msg_session_hdr_ext pkt;
  187. };
  188. struct cvp_session_queue {
  189. spinlock_t lock;
  190. enum queue_state state;
  191. unsigned int msg_count;
  192. struct list_head msgs;
  193. wait_queue_head_t wq;
  194. };
  195. #define CVP_CYCLE_STAT_SIZE 8
  196. struct cvp_cycle_stat {
  197. u32 busy[CVP_CYCLE_STAT_SIZE];
  198. u32 total;
  199. u32 idx;
  200. u32 size;
  201. };
  202. struct cvp_cycle_info {
  203. u32 sum_fps[HFI_MAX_HW_THREADS];
  204. u32 hi_ctrl_lim[HFI_MAX_HW_THREADS];
  205. u32 lo_ctrl_lim[HFI_MAX_HW_THREADS];
  206. struct cvp_cycle_stat cycle[HFI_MAX_HW_THREADS];
  207. unsigned long conf_freq;
  208. };
  209. struct cvp_session_prop {
  210. u32 type;
  211. u32 kernel_mask;
  212. u32 priority;
  213. u32 is_secure;
  214. u32 dsp_mask;
  215. u32 fthread_nr;
  216. u32 fdu_cycles;
  217. u32 od_cycles;
  218. u32 mpu_cycles;
  219. u32 ica_cycles;
  220. u32 fw_cycles;
  221. u32 fdu_op_cycles;
  222. u32 od_op_cycles;
  223. u32 mpu_op_cycles;
  224. u32 ica_op_cycles;
  225. u32 fw_op_cycles;
  226. u32 ddr_bw;
  227. u32 ddr_op_bw;
  228. u32 ddr_cache;
  229. u32 ddr_op_cache;
  230. u32 fps[HFI_MAX_HW_THREADS];
  231. u32 dump_offset;
  232. u32 dump_size;
  233. };
  234. enum cvp_event_t {
  235. CVP_NO_EVENT,
  236. CVP_SSR_EVENT = 1,
  237. CVP_SYS_ERROR_EVENT,
  238. CVP_MAX_CLIENTS_EVENT,
  239. CVP_HW_UNSUPPORTED_EVENT,
  240. CVP_INVALID_EVENT,
  241. CVP_DUMP_EVENT,
  242. };
  243. struct cvp_session_event {
  244. spinlock_t lock;
  245. enum cvp_event_t event;
  246. wait_queue_head_t wq;
  247. };
  248. #define MAX_ENTRIES 64
  249. struct smem_data {
  250. u32 size;
  251. u32 flags;
  252. u32 device_addr;
  253. u32 bitmap_index;
  254. u32 refcount;
  255. u32 pkt_type;
  256. u32 buf_idx;
  257. };
  258. struct cvp_buf_data {
  259. u32 device_addr;
  260. u32 size;
  261. };
  262. struct inst_snapshot {
  263. void *session;
  264. u32 smem_index;
  265. u32 dsp_index;
  266. u32 persist_index;
  267. struct smem_data smem_log[MAX_ENTRIES];
  268. struct cvp_buf_data dsp_buf_log[MAX_ENTRIES];
  269. struct cvp_buf_data persist_buf_log[MAX_ENTRIES];
  270. };
  271. struct cvp_noc_log {
  272. u32 used;
  273. u32 err_ctrl_swid_low;
  274. u32 err_ctrl_swid_high;
  275. u32 err_ctrl_mainctl_low;
  276. u32 err_ctrl_errvld_low;
  277. u32 err_ctrl_errclr_low;
  278. u32 err_ctrl_errlog0_low;
  279. u32 err_ctrl_errlog0_high;
  280. u32 err_ctrl_errlog1_low;
  281. u32 err_ctrl_errlog1_high;
  282. u32 err_ctrl_errlog2_low;
  283. u32 err_ctrl_errlog2_high;
  284. u32 err_ctrl_errlog3_low;
  285. u32 err_ctrl_errlog3_high;
  286. u32 err_core_swid_low;
  287. u32 err_core_swid_high;
  288. u32 err_core_mainctl_low;
  289. u32 err_core_errvld_low;
  290. u32 err_core_errclr_low;
  291. u32 err_core_errlog0_low;
  292. u32 err_core_errlog0_high;
  293. u32 err_core_errlog1_low;
  294. u32 err_core_errlog1_high;
  295. u32 err_core_errlog2_low;
  296. u32 err_core_errlog2_high;
  297. u32 err_core_errlog3_low;
  298. u32 err_core_errlog3_high;
  299. u32 arp_test_bus[16];
  300. u32 dma_test_bus[512];
  301. };
  302. struct cvp_debug_log {
  303. struct cvp_noc_log noc_log;
  304. u32 snapshot_index;
  305. struct inst_snapshot snapshot[16];
  306. };
  307. struct msm_cvp_core {
  308. struct list_head list;
  309. struct mutex lock;
  310. struct mutex clk_lock;
  311. int id;
  312. dev_t dev_num;
  313. struct cdev cdev;
  314. struct class *class;
  315. struct device *dev;
  316. struct cvp_hfi_device *device;
  317. struct msm_cvp_platform_data *platform_data;
  318. struct msm_cvp_synx_ops *synx_ftbl;
  319. struct list_head instances;
  320. struct dentry *debugfs_root;
  321. enum cvp_core_state state;
  322. struct completion completions[SYS_MSG_END - SYS_MSG_START + 1];
  323. enum msm_cvp_hfi_type hfi_type;
  324. struct msm_cvp_platform_resources resources;
  325. struct msm_cvp_capability *capabilities;
  326. struct delayed_work fw_unload_work;
  327. struct work_struct ssr_work;
  328. enum hal_ssr_trigger_type ssr_type;
  329. u32 smmu_fault_count;
  330. u32 last_fault_addr;
  331. u32 ssr_count;
  332. bool trigger_ssr;
  333. unsigned long curr_freq;
  334. unsigned long orig_core_sum;
  335. struct cvp_cycle_info dyn_clk;
  336. atomic64_t kernel_trans_id;
  337. struct cvp_debug_log log;
  338. };
  339. struct msm_cvp_inst {
  340. struct list_head list;
  341. struct list_head dsp_list;
  342. struct mutex sync_lock, lock;
  343. struct msm_cvp_core *core;
  344. enum session_type session_type;
  345. u32 process_id;
  346. struct task_struct *task;
  347. struct cvp_session_queue session_queue;
  348. struct cvp_session_queue session_queue_fence;
  349. struct cvp_session_event event_handler;
  350. void *session;
  351. enum instance_state state;
  352. struct msm_cvp_list freqs;
  353. struct msm_cvp_list persistbufs;
  354. struct cvp_dmamap_cache dma_cache;
  355. struct msm_cvp_list cvpdspbufs;
  356. struct msm_cvp_list cvpwnccbufs;
  357. struct msm_cvp_list frames;
  358. u32 cvpwnccbufs_num;
  359. struct msm_cvp_wncc_buffer* cvpwnccbufs_table;
  360. struct completion completions[SESSION_MSG_END - SESSION_MSG_START + 1];
  361. struct dentry *debugfs_root;
  362. struct msm_cvp_debug debug;
  363. struct cvp_clock_data clk_data;
  364. enum msm_cvp_modes flags;
  365. struct msm_cvp_capability capability;
  366. struct kref kref;
  367. struct cvp_session_prop prop;
  368. /* error_code will be cleared after being returned to user mode */
  369. u32 error_code;
  370. /* prev_error_code saves value of error_code before it's cleared */
  371. u32 prev_error_code;
  372. struct synx_session synx_session_id;
  373. struct cvp_fence_queue fence_cmd_queue;
  374. char proc_name[TASK_COMM_LEN];
  375. };
  376. extern struct msm_cvp_drv *cvp_driver;
  377. void cvp_handle_cmd_response(enum hal_command_response cmd, void *data);
  378. int msm_cvp_trigger_ssr(struct msm_cvp_core *core,
  379. enum hal_ssr_trigger_type type);
  380. int msm_cvp_noc_error_info(struct msm_cvp_core *core);
  381. void msm_cvp_comm_handle_thermal_event(void);
  382. void msm_cvp_fw_unload_handler(struct work_struct *work);
  383. void msm_cvp_ssr_handler(struct work_struct *work);
  384. /*
  385. * XXX: normally should be in msm_cvp_core.h, but that's meant for public APIs,
  386. * whereas this is private
  387. */
  388. int msm_cvp_destroy(struct msm_cvp_inst *inst);
  389. void *cvp_get_drv_data(struct device *dev);
  390. #endif