dp_tx.c 150 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "htt.h"
  20. #include "dp_htt.h"
  21. #include "hal_hw_headers.h"
  22. #include "dp_tx.h"
  23. #include "dp_tx_desc.h"
  24. #include "dp_peer.h"
  25. #include "dp_types.h"
  26. #include "hal_tx.h"
  27. #include "qdf_mem.h"
  28. #include "qdf_nbuf.h"
  29. #include "qdf_net_types.h"
  30. #include "qdf_module.h"
  31. #include <wlan_cfg.h>
  32. #include "dp_ipa.h"
  33. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  34. #include "if_meta_hdr.h"
  35. #endif
  36. #include "enet.h"
  37. #include "dp_internal.h"
  38. #ifdef ATH_SUPPORT_IQUE
  39. #include "dp_txrx_me.h"
  40. #endif
  41. #include "dp_hist.h"
  42. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  43. #include <dp_swlm.h>
  44. #endif
  45. #ifdef WIFI_MONITOR_SUPPORT
  46. #include <dp_mon.h>
  47. #endif
  48. #ifdef FEATURE_WDS
  49. #include "dp_txrx_wds.h"
  50. #endif
  51. #include "cdp_txrx_cmn_reg.h"
  52. /* Flag to skip CCE classify when mesh or tid override enabled */
  53. #define DP_TX_SKIP_CCE_CLASSIFY \
  54. (DP_TXRX_HLOS_TID_OVERRIDE_ENABLED | DP_TX_MESH_ENABLED)
  55. /* TODO Add support in TSO */
  56. #define DP_DESC_NUM_FRAG(x) 0
  57. /* disable TQM_BYPASS */
  58. #define TQM_BYPASS_WAR 0
  59. /* invalid peer id for reinject*/
  60. #define DP_INVALID_PEER 0XFFFE
  61. #define DP_RETRY_COUNT 7
  62. #ifdef WLAN_MCAST_MLO
  63. #define DP_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)\
  64. HTT_TX_TCL_METADATA_V2_PDEV_ID_SET(_var, _val)
  65. #define DP_TX_TCL_METADATA_VALID_HTT_SET(_var, _val) \
  66. HTT_TX_TCL_METADATA_V2_VALID_HTT_SET(_var, _val)
  67. #define DP_TX_TCL_METADATA_TYPE_SET(_var, _val) \
  68. HTT_TX_TCL_METADATA_TYPE_V2_SET(_var, _val)
  69. #define DP_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val) \
  70. HTT_TX_TCL_METADATA_V2_HOST_INSPECTED_SET(_var, _val)
  71. #define DP_TX_TCL_METADATA_PEER_ID_SET(_var, _val) \
  72. HTT_TX_TCL_METADATA_V2_PEER_ID_SET(_var, _val)
  73. #define DP_TX_TCL_METADATA_VDEV_ID_SET(_var, _val) \
  74. HTT_TX_TCL_METADATA_V2_VDEV_ID_SET(_var, _val)
  75. #define DP_TCL_METADATA_TYPE_PEER_BASED \
  76. HTT_TCL_METADATA_V2_TYPE_PEER_BASED
  77. #define DP_TCL_METADATA_TYPE_VDEV_BASED \
  78. HTT_TCL_METADATA_V2_TYPE_VDEV_BASED
  79. #else
  80. #define DP_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)\
  81. HTT_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)
  82. #define DP_TX_TCL_METADATA_VALID_HTT_SET(_var, _val) \
  83. HTT_TX_TCL_METADATA_VALID_HTT_SET(_var, _val)
  84. #define DP_TX_TCL_METADATA_TYPE_SET(_var, _val) \
  85. HTT_TX_TCL_METADATA_TYPE_SET(_var, _val)
  86. #define DP_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val) \
  87. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val)
  88. #define DP_TX_TCL_METADATA_PEER_ID_SET(_var, _val) \
  89. HTT_TX_TCL_METADATA_PEER_ID_SET(_var, _val)
  90. #define DP_TX_TCL_METADATA_VDEV_ID_SET(_var, _val) \
  91. HTT_TX_TCL_METADATA_VDEV_ID_SET(_var, _val)
  92. #define DP_TCL_METADATA_TYPE_PEER_BASED \
  93. HTT_TCL_METADATA_TYPE_PEER_BASED
  94. #define DP_TCL_METADATA_TYPE_VDEV_BASED \
  95. HTT_TCL_METADATA_TYPE_VDEV_BASED
  96. #endif
  97. /*mapping between hal encrypt type and cdp_sec_type*/
  98. uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  99. HAL_TX_ENCRYPT_TYPE_WEP_128,
  100. HAL_TX_ENCRYPT_TYPE_WEP_104,
  101. HAL_TX_ENCRYPT_TYPE_WEP_40,
  102. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  103. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  104. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  105. HAL_TX_ENCRYPT_TYPE_WAPI,
  106. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  107. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  108. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  109. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  110. qdf_export_symbol(sec_type_map);
  111. #ifdef CONFIG_WLAN_SYSFS_MEM_STATS
  112. /**
  113. * dp_update_tx_desc_stats - Update the increase or decrease in
  114. * outstanding tx desc count
  115. * values on pdev and soc
  116. * @vdev: DP pdev handle
  117. *
  118. * Return: void
  119. */
  120. static inline void
  121. dp_update_tx_desc_stats(struct dp_pdev *pdev)
  122. {
  123. int32_t tx_descs_cnt =
  124. qdf_atomic_read(&pdev->num_tx_outstanding);
  125. if (pdev->tx_descs_max < tx_descs_cnt)
  126. pdev->tx_descs_max = tx_descs_cnt;
  127. qdf_mem_tx_desc_cnt_update(pdev->num_tx_outstanding,
  128. pdev->tx_descs_max);
  129. }
  130. #else /* CONFIG_WLAN_SYSFS_MEM_STATS */
  131. static inline void
  132. dp_update_tx_desc_stats(struct dp_pdev *pdev)
  133. {
  134. }
  135. #endif /* CONFIG_WLAN_SYSFS_MEM_STATS */
  136. #if defined(WLAN_TX_PKT_CAPTURE_ENH) || defined(FEATURE_PERPKT_INFO)
  137. static inline
  138. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  139. {
  140. qdf_nbuf_unmap_nbytes_single(soc->osdev, desc->nbuf,
  141. QDF_DMA_TO_DEVICE,
  142. desc->nbuf->len);
  143. desc->flags |= DP_TX_DESC_FLAG_UNMAP_DONE;
  144. }
  145. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  146. {
  147. if (qdf_likely(!(desc->flags & DP_TX_DESC_FLAG_UNMAP_DONE)))
  148. qdf_nbuf_unmap_nbytes_single(soc->osdev, desc->nbuf,
  149. QDF_DMA_TO_DEVICE,
  150. desc->nbuf->len);
  151. }
  152. #else
  153. static inline
  154. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  155. {
  156. }
  157. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  158. {
  159. qdf_nbuf_unmap_nbytes_single(soc->osdev, desc->nbuf,
  160. QDF_DMA_TO_DEVICE, desc->nbuf->len);
  161. }
  162. #endif
  163. #ifdef QCA_TX_LIMIT_CHECK
  164. /**
  165. * dp_tx_limit_check - Check if allocated tx descriptors reached
  166. * soc max limit and pdev max limit
  167. * @vdev: DP vdev handle
  168. *
  169. * Return: true if allocated tx descriptors reached max configured value, else
  170. * false
  171. */
  172. static inline bool
  173. dp_tx_limit_check(struct dp_vdev *vdev)
  174. {
  175. struct dp_pdev *pdev = vdev->pdev;
  176. struct dp_soc *soc = pdev->soc;
  177. if (qdf_atomic_read(&soc->num_tx_outstanding) >=
  178. soc->num_tx_allowed) {
  179. dp_tx_info("queued packets are more than max tx, drop the frame");
  180. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  181. return true;
  182. }
  183. if (qdf_atomic_read(&pdev->num_tx_outstanding) >=
  184. pdev->num_tx_allowed) {
  185. dp_tx_info("queued packets are more than max tx, drop the frame");
  186. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  187. DP_STATS_INC(vdev, tx_i.dropped.desc_na_exc_outstand.num, 1);
  188. return true;
  189. }
  190. return false;
  191. }
  192. /**
  193. * dp_tx_exception_limit_check - Check if allocated tx exception descriptors
  194. * reached soc max limit
  195. * @vdev: DP vdev handle
  196. *
  197. * Return: true if allocated tx descriptors reached max configured value, else
  198. * false
  199. */
  200. static inline bool
  201. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  202. {
  203. struct dp_pdev *pdev = vdev->pdev;
  204. struct dp_soc *soc = pdev->soc;
  205. if (qdf_atomic_read(&soc->num_tx_exception) >=
  206. soc->num_msdu_exception_desc) {
  207. dp_info("exc packets are more than max drop the exc pkt");
  208. DP_STATS_INC(vdev, tx_i.dropped.exc_desc_na.num, 1);
  209. return true;
  210. }
  211. return false;
  212. }
  213. /**
  214. * dp_tx_outstanding_inc - Increment outstanding tx desc values on pdev and soc
  215. * @vdev: DP pdev handle
  216. *
  217. * Return: void
  218. */
  219. static inline void
  220. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  221. {
  222. struct dp_soc *soc = pdev->soc;
  223. qdf_atomic_inc(&pdev->num_tx_outstanding);
  224. qdf_atomic_inc(&soc->num_tx_outstanding);
  225. dp_update_tx_desc_stats(pdev);
  226. }
  227. /**
  228. * dp_tx_outstanding__dec - Decrement outstanding tx desc values on pdev and soc
  229. * @vdev: DP pdev handle
  230. *
  231. * Return: void
  232. */
  233. static inline void
  234. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  235. {
  236. struct dp_soc *soc = pdev->soc;
  237. qdf_atomic_dec(&pdev->num_tx_outstanding);
  238. qdf_atomic_dec(&soc->num_tx_outstanding);
  239. dp_update_tx_desc_stats(pdev);
  240. }
  241. #else //QCA_TX_LIMIT_CHECK
  242. static inline bool
  243. dp_tx_limit_check(struct dp_vdev *vdev)
  244. {
  245. return false;
  246. }
  247. static inline bool
  248. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  249. {
  250. return false;
  251. }
  252. static inline void
  253. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  254. {
  255. qdf_atomic_inc(&pdev->num_tx_outstanding);
  256. dp_update_tx_desc_stats(pdev);
  257. }
  258. static inline void
  259. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  260. {
  261. qdf_atomic_dec(&pdev->num_tx_outstanding);
  262. dp_update_tx_desc_stats(pdev);
  263. }
  264. #endif //QCA_TX_LIMIT_CHECK
  265. #ifdef WLAN_FEATURE_DP_TX_DESC_HISTORY
  266. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  267. {
  268. enum dp_tx_event_type type;
  269. if (flags & DP_TX_DESC_FLAG_FLUSH)
  270. type = DP_TX_DESC_FLUSH;
  271. else if (flags & DP_TX_DESC_FLAG_TX_COMP_ERR)
  272. type = DP_TX_COMP_UNMAP_ERR;
  273. else if (flags & DP_TX_DESC_FLAG_COMPLETED_TX)
  274. type = DP_TX_COMP_UNMAP;
  275. else
  276. type = DP_TX_DESC_UNMAP;
  277. return type;
  278. }
  279. static inline void
  280. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  281. qdf_nbuf_t skb, uint32_t sw_cookie,
  282. enum dp_tx_event_type type)
  283. {
  284. struct dp_tx_desc_event *entry;
  285. uint32_t idx;
  286. if (qdf_unlikely(!soc->tx_tcl_history || !soc->tx_comp_history))
  287. return;
  288. switch (type) {
  289. case DP_TX_COMP_UNMAP:
  290. case DP_TX_COMP_UNMAP_ERR:
  291. case DP_TX_COMP_MSDU_EXT:
  292. idx = dp_history_get_next_index(&soc->tx_comp_history->index,
  293. DP_TX_COMP_HISTORY_SIZE);
  294. entry = &soc->tx_comp_history->entry[idx];
  295. break;
  296. case DP_TX_DESC_MAP:
  297. case DP_TX_DESC_UNMAP:
  298. case DP_TX_DESC_COOKIE:
  299. case DP_TX_DESC_FLUSH:
  300. idx = dp_history_get_next_index(&soc->tx_tcl_history->index,
  301. DP_TX_TCL_HISTORY_SIZE);
  302. entry = &soc->tx_tcl_history->entry[idx];
  303. break;
  304. default:
  305. dp_info_rl("Invalid dp_tx_event_type: %d", type);
  306. return;
  307. }
  308. entry->skb = skb;
  309. entry->paddr = paddr;
  310. entry->sw_cookie = sw_cookie;
  311. entry->type = type;
  312. entry->ts = qdf_get_log_timestamp();
  313. }
  314. static inline void
  315. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  316. struct qdf_tso_seg_elem_t *tso_seg,
  317. qdf_nbuf_t skb, uint32_t sw_cookie,
  318. enum dp_tx_event_type type)
  319. {
  320. int i;
  321. for (i = 1; i < tso_seg->seg.num_frags; i++) {
  322. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[i].paddr,
  323. skb, sw_cookie, type);
  324. }
  325. if (!tso_seg->next)
  326. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[0].paddr,
  327. skb, 0xFFFFFFFF, type);
  328. }
  329. static inline void
  330. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  331. qdf_nbuf_t skb, uint32_t sw_cookie,
  332. enum dp_tx_event_type type)
  333. {
  334. struct qdf_tso_seg_elem_t *curr_seg = tso_info.tso_seg_list;
  335. uint32_t num_segs = tso_info.num_segs;
  336. while (num_segs) {
  337. dp_tx_tso_seg_history_add(soc, curr_seg, skb, sw_cookie, type);
  338. curr_seg = curr_seg->next;
  339. num_segs--;
  340. }
  341. }
  342. #else
  343. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  344. {
  345. return DP_TX_DESC_INVAL_EVT;
  346. }
  347. static inline void
  348. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  349. qdf_nbuf_t skb, uint32_t sw_cookie,
  350. enum dp_tx_event_type type)
  351. {
  352. }
  353. static inline void
  354. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  355. struct qdf_tso_seg_elem_t *tso_seg,
  356. qdf_nbuf_t skb, uint32_t sw_cookie,
  357. enum dp_tx_event_type type)
  358. {
  359. }
  360. static inline void
  361. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  362. qdf_nbuf_t skb, uint32_t sw_cookie,
  363. enum dp_tx_event_type type)
  364. {
  365. }
  366. #endif /* WLAN_FEATURE_DP_TX_DESC_HISTORY */
  367. static int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc);
  368. /**
  369. * dp_is_tput_high() - Check if throughput is high
  370. *
  371. * @soc - core txrx main context
  372. *
  373. * The current function is based of the RTPM tput policy variable where RTPM is
  374. * avoided based on throughput.
  375. */
  376. static inline int dp_is_tput_high(struct dp_soc *soc)
  377. {
  378. return dp_get_rtpm_tput_policy_requirement(soc);
  379. }
  380. #if defined(FEATURE_TSO)
  381. /**
  382. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  383. *
  384. * @soc - core txrx main context
  385. * @seg_desc - tso segment descriptor
  386. * @num_seg_desc - tso number segment descriptor
  387. */
  388. static void dp_tx_tso_unmap_segment(
  389. struct dp_soc *soc,
  390. struct qdf_tso_seg_elem_t *seg_desc,
  391. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  392. {
  393. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  394. if (qdf_unlikely(!seg_desc)) {
  395. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  396. __func__, __LINE__);
  397. qdf_assert(0);
  398. } else if (qdf_unlikely(!num_seg_desc)) {
  399. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  400. __func__, __LINE__);
  401. qdf_assert(0);
  402. } else {
  403. bool is_last_seg;
  404. /* no tso segment left to do dma unmap */
  405. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  406. return;
  407. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  408. true : false;
  409. qdf_nbuf_unmap_tso_segment(soc->osdev,
  410. seg_desc, is_last_seg);
  411. num_seg_desc->num_seg.tso_cmn_num_seg--;
  412. }
  413. }
  414. /**
  415. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  416. * back to the freelist
  417. *
  418. * @soc - soc device handle
  419. * @tx_desc - Tx software descriptor
  420. */
  421. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  422. struct dp_tx_desc_s *tx_desc)
  423. {
  424. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  425. if (qdf_unlikely(!tx_desc->msdu_ext_desc->tso_desc)) {
  426. dp_tx_err("SO desc is NULL!");
  427. qdf_assert(0);
  428. } else if (qdf_unlikely(!tx_desc->msdu_ext_desc->tso_num_desc)) {
  429. dp_tx_err("TSO num desc is NULL!");
  430. qdf_assert(0);
  431. } else {
  432. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  433. (struct qdf_tso_num_seg_elem_t *)tx_desc->
  434. msdu_ext_desc->tso_num_desc;
  435. /* Add the tso num segment into the free list */
  436. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  437. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  438. tx_desc->msdu_ext_desc->
  439. tso_num_desc);
  440. tx_desc->msdu_ext_desc->tso_num_desc = NULL;
  441. DP_STATS_INC(tx_desc->pdev, tso_stats.tso_comp, 1);
  442. }
  443. /* Add the tso segment into the free list*/
  444. dp_tx_tso_desc_free(soc,
  445. tx_desc->pool_id, tx_desc->msdu_ext_desc->
  446. tso_desc);
  447. tx_desc->msdu_ext_desc->tso_desc = NULL;
  448. }
  449. }
  450. #else
  451. static void dp_tx_tso_unmap_segment(
  452. struct dp_soc *soc,
  453. struct qdf_tso_seg_elem_t *seg_desc,
  454. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  455. {
  456. }
  457. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  458. struct dp_tx_desc_s *tx_desc)
  459. {
  460. }
  461. #endif
  462. /**
  463. * dp_tx_desc_release() - Release Tx Descriptor
  464. * @tx_desc : Tx Descriptor
  465. * @desc_pool_id: Descriptor Pool ID
  466. *
  467. * Deallocate all resources attached to Tx descriptor and free the Tx
  468. * descriptor.
  469. *
  470. * Return:
  471. */
  472. void
  473. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  474. {
  475. struct dp_pdev *pdev = tx_desc->pdev;
  476. struct dp_soc *soc;
  477. uint8_t comp_status = 0;
  478. qdf_assert(pdev);
  479. soc = pdev->soc;
  480. dp_tx_outstanding_dec(pdev);
  481. if (tx_desc->msdu_ext_desc) {
  482. if (tx_desc->frm_type == dp_tx_frm_tso)
  483. dp_tx_tso_desc_release(soc, tx_desc);
  484. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  485. dp_tx_me_free_buf(tx_desc->pdev,
  486. tx_desc->msdu_ext_desc->me_buffer);
  487. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  488. }
  489. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  490. qdf_atomic_dec(&soc->num_tx_exception);
  491. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  492. tx_desc->buffer_src)
  493. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  494. soc->hal_soc);
  495. else
  496. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  497. dp_tx_debug("Tx Completion Release desc %d status %d outstanding %d",
  498. tx_desc->id, comp_status,
  499. qdf_atomic_read(&pdev->num_tx_outstanding));
  500. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  501. return;
  502. }
  503. /**
  504. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  505. * @vdev: DP vdev Handle
  506. * @nbuf: skb
  507. * @msdu_info: msdu_info required to create HTT metadata
  508. *
  509. * Prepares and fills HTT metadata in the frame pre-header for special frames
  510. * that should be transmitted using varying transmit parameters.
  511. * There are 2 VDEV modes that currently needs this special metadata -
  512. * 1) Mesh Mode
  513. * 2) DSRC Mode
  514. *
  515. * Return: HTT metadata size
  516. *
  517. */
  518. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  519. struct dp_tx_msdu_info_s *msdu_info)
  520. {
  521. uint32_t *meta_data = msdu_info->meta_data;
  522. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  523. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  524. uint8_t htt_desc_size;
  525. /* Size rounded of multiple of 8 bytes */
  526. uint8_t htt_desc_size_aligned;
  527. uint8_t *hdr = NULL;
  528. /*
  529. * Metadata - HTT MSDU Extension header
  530. */
  531. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  532. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  533. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  534. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  535. meta_data[0])) {
  536. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  537. htt_desc_size_aligned)) {
  538. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  539. htt_desc_size_aligned);
  540. if (!nbuf) {
  541. /*
  542. * qdf_nbuf_realloc_headroom won't do skb_clone
  543. * as skb_realloc_headroom does. so, no free is
  544. * needed here.
  545. */
  546. DP_STATS_INC(vdev,
  547. tx_i.dropped.headroom_insufficient,
  548. 1);
  549. qdf_print(" %s[%d] skb_realloc_headroom failed",
  550. __func__, __LINE__);
  551. return 0;
  552. }
  553. }
  554. /* Fill and add HTT metaheader */
  555. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  556. if (!hdr) {
  557. dp_tx_err("Error in filling HTT metadata");
  558. return 0;
  559. }
  560. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  561. } else if (vdev->opmode == wlan_op_mode_ocb) {
  562. /* Todo - Add support for DSRC */
  563. }
  564. return htt_desc_size_aligned;
  565. }
  566. /**
  567. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  568. * @tso_seg: TSO segment to process
  569. * @ext_desc: Pointer to MSDU extension descriptor
  570. *
  571. * Return: void
  572. */
  573. #if defined(FEATURE_TSO)
  574. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  575. void *ext_desc)
  576. {
  577. uint8_t num_frag;
  578. uint32_t tso_flags;
  579. /*
  580. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  581. * tcp_flag_mask
  582. *
  583. * Checksum enable flags are set in TCL descriptor and not in Extension
  584. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  585. */
  586. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  587. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  588. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  589. tso_seg->tso_flags.ip_len);
  590. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  591. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  592. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  593. uint32_t lo = 0;
  594. uint32_t hi = 0;
  595. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  596. (tso_seg->tso_frags[num_frag].length));
  597. qdf_dmaaddr_to_32s(
  598. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  599. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  600. tso_seg->tso_frags[num_frag].length);
  601. }
  602. return;
  603. }
  604. #else
  605. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  606. void *ext_desc)
  607. {
  608. return;
  609. }
  610. #endif
  611. #if defined(FEATURE_TSO)
  612. /**
  613. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  614. * allocated and free them
  615. *
  616. * @soc: soc handle
  617. * @free_seg: list of tso segments
  618. * @msdu_info: msdu descriptor
  619. *
  620. * Return - void
  621. */
  622. static void dp_tx_free_tso_seg_list(
  623. struct dp_soc *soc,
  624. struct qdf_tso_seg_elem_t *free_seg,
  625. struct dp_tx_msdu_info_s *msdu_info)
  626. {
  627. struct qdf_tso_seg_elem_t *next_seg;
  628. while (free_seg) {
  629. next_seg = free_seg->next;
  630. dp_tx_tso_desc_free(soc,
  631. msdu_info->tx_queue.desc_pool_id,
  632. free_seg);
  633. free_seg = next_seg;
  634. }
  635. }
  636. /**
  637. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  638. * allocated and free them
  639. *
  640. * @soc: soc handle
  641. * @free_num_seg: list of tso number segments
  642. * @msdu_info: msdu descriptor
  643. * Return - void
  644. */
  645. static void dp_tx_free_tso_num_seg_list(
  646. struct dp_soc *soc,
  647. struct qdf_tso_num_seg_elem_t *free_num_seg,
  648. struct dp_tx_msdu_info_s *msdu_info)
  649. {
  650. struct qdf_tso_num_seg_elem_t *next_num_seg;
  651. while (free_num_seg) {
  652. next_num_seg = free_num_seg->next;
  653. dp_tso_num_seg_free(soc,
  654. msdu_info->tx_queue.desc_pool_id,
  655. free_num_seg);
  656. free_num_seg = next_num_seg;
  657. }
  658. }
  659. /**
  660. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  661. * do dma unmap for each segment
  662. *
  663. * @soc: soc handle
  664. * @free_seg: list of tso segments
  665. * @num_seg_desc: tso number segment descriptor
  666. *
  667. * Return - void
  668. */
  669. static void dp_tx_unmap_tso_seg_list(
  670. struct dp_soc *soc,
  671. struct qdf_tso_seg_elem_t *free_seg,
  672. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  673. {
  674. struct qdf_tso_seg_elem_t *next_seg;
  675. if (qdf_unlikely(!num_seg_desc)) {
  676. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  677. return;
  678. }
  679. while (free_seg) {
  680. next_seg = free_seg->next;
  681. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  682. free_seg = next_seg;
  683. }
  684. }
  685. #ifdef FEATURE_TSO_STATS
  686. /**
  687. * dp_tso_get_stats_idx: Retrieve the tso packet id
  688. * @pdev - pdev handle
  689. *
  690. * Return: id
  691. */
  692. static uint32_t dp_tso_get_stats_idx(struct dp_pdev *pdev)
  693. {
  694. uint32_t stats_idx;
  695. stats_idx = (((uint32_t)qdf_atomic_inc_return(&pdev->tso_idx))
  696. % CDP_MAX_TSO_PACKETS);
  697. return stats_idx;
  698. }
  699. #else
  700. static int dp_tso_get_stats_idx(struct dp_pdev *pdev)
  701. {
  702. return 0;
  703. }
  704. #endif /* FEATURE_TSO_STATS */
  705. /**
  706. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  707. * free the tso segments descriptor and
  708. * tso num segments descriptor
  709. *
  710. * @soc: soc handle
  711. * @msdu_info: msdu descriptor
  712. * @tso_seg_unmap: flag to show if dma unmap is necessary
  713. *
  714. * Return - void
  715. */
  716. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  717. struct dp_tx_msdu_info_s *msdu_info,
  718. bool tso_seg_unmap)
  719. {
  720. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  721. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  722. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  723. tso_info->tso_num_seg_list;
  724. /* do dma unmap for each segment */
  725. if (tso_seg_unmap)
  726. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  727. /* free all tso number segment descriptor though looks only have 1 */
  728. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  729. /* free all tso segment descriptor */
  730. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  731. }
  732. /**
  733. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  734. * @vdev: virtual device handle
  735. * @msdu: network buffer
  736. * @msdu_info: meta data associated with the msdu
  737. *
  738. * Return: QDF_STATUS_SUCCESS success
  739. */
  740. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  741. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  742. {
  743. struct qdf_tso_seg_elem_t *tso_seg;
  744. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  745. struct dp_soc *soc = vdev->pdev->soc;
  746. struct dp_pdev *pdev = vdev->pdev;
  747. struct qdf_tso_info_t *tso_info;
  748. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  749. tso_info = &msdu_info->u.tso_info;
  750. tso_info->curr_seg = NULL;
  751. tso_info->tso_seg_list = NULL;
  752. tso_info->num_segs = num_seg;
  753. msdu_info->frm_type = dp_tx_frm_tso;
  754. tso_info->tso_num_seg_list = NULL;
  755. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  756. while (num_seg) {
  757. tso_seg = dp_tx_tso_desc_alloc(
  758. soc, msdu_info->tx_queue.desc_pool_id);
  759. if (tso_seg) {
  760. tso_seg->next = tso_info->tso_seg_list;
  761. tso_info->tso_seg_list = tso_seg;
  762. num_seg--;
  763. } else {
  764. dp_err_rl("Failed to alloc tso seg desc");
  765. DP_STATS_INC_PKT(vdev->pdev,
  766. tso_stats.tso_no_mem_dropped, 1,
  767. qdf_nbuf_len(msdu));
  768. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  769. return QDF_STATUS_E_NOMEM;
  770. }
  771. }
  772. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  773. tso_num_seg = dp_tso_num_seg_alloc(soc,
  774. msdu_info->tx_queue.desc_pool_id);
  775. if (tso_num_seg) {
  776. tso_num_seg->next = tso_info->tso_num_seg_list;
  777. tso_info->tso_num_seg_list = tso_num_seg;
  778. } else {
  779. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  780. __func__);
  781. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  782. return QDF_STATUS_E_NOMEM;
  783. }
  784. msdu_info->num_seg =
  785. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  786. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  787. msdu_info->num_seg);
  788. if (!(msdu_info->num_seg)) {
  789. /*
  790. * Free allocated TSO seg desc and number seg desc,
  791. * do unmap for segments if dma map has done.
  792. */
  793. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  794. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  795. return QDF_STATUS_E_INVAL;
  796. }
  797. dp_tx_tso_history_add(soc, msdu_info->u.tso_info,
  798. msdu, 0, DP_TX_DESC_MAP);
  799. tso_info->curr_seg = tso_info->tso_seg_list;
  800. tso_info->msdu_stats_idx = dp_tso_get_stats_idx(pdev);
  801. dp_tso_packet_update(pdev, tso_info->msdu_stats_idx,
  802. msdu, msdu_info->num_seg);
  803. dp_tso_segment_stats_update(pdev, tso_info->tso_seg_list,
  804. tso_info->msdu_stats_idx);
  805. dp_stats_tso_segment_histogram_update(pdev, msdu_info->num_seg);
  806. return QDF_STATUS_SUCCESS;
  807. }
  808. #else
  809. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  810. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  811. {
  812. return QDF_STATUS_E_NOMEM;
  813. }
  814. #endif
  815. QDF_COMPILE_TIME_ASSERT(dp_tx_htt_metadata_len_check,
  816. (DP_TX_MSDU_INFO_META_DATA_DWORDS * 4 >=
  817. sizeof(struct htt_tx_msdu_desc_ext2_t)));
  818. /**
  819. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  820. * @vdev: DP Vdev handle
  821. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  822. * @desc_pool_id: Descriptor Pool ID
  823. *
  824. * Return:
  825. */
  826. static
  827. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  828. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  829. {
  830. uint8_t i;
  831. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  832. struct dp_tx_seg_info_s *seg_info;
  833. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  834. struct dp_soc *soc = vdev->pdev->soc;
  835. /* Allocate an extension descriptor */
  836. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  837. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  838. if (!msdu_ext_desc) {
  839. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  840. return NULL;
  841. }
  842. if (msdu_info->exception_fw &&
  843. qdf_unlikely(vdev->mesh_vdev)) {
  844. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  845. &msdu_info->meta_data[0],
  846. sizeof(struct htt_tx_msdu_desc_ext2_t));
  847. qdf_atomic_inc(&soc->num_tx_exception);
  848. msdu_ext_desc->flags |= DP_TX_EXT_DESC_FLAG_METADATA_VALID;
  849. }
  850. switch (msdu_info->frm_type) {
  851. case dp_tx_frm_sg:
  852. case dp_tx_frm_me:
  853. case dp_tx_frm_raw:
  854. seg_info = msdu_info->u.sg_info.curr_seg;
  855. /* Update the buffer pointers in MSDU Extension Descriptor */
  856. for (i = 0; i < seg_info->frag_cnt; i++) {
  857. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  858. seg_info->frags[i].paddr_lo,
  859. seg_info->frags[i].paddr_hi,
  860. seg_info->frags[i].len);
  861. }
  862. break;
  863. case dp_tx_frm_tso:
  864. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  865. &cached_ext_desc[0]);
  866. break;
  867. default:
  868. break;
  869. }
  870. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  871. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  872. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  873. msdu_ext_desc->vaddr);
  874. return msdu_ext_desc;
  875. }
  876. /**
  877. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  878. *
  879. * @skb: skb to be traced
  880. * @msdu_id: msdu_id of the packet
  881. * @vdev_id: vdev_id of the packet
  882. *
  883. * Return: None
  884. */
  885. #ifdef DP_DISABLE_TX_PKT_TRACE
  886. static void dp_tx_trace_pkt(struct dp_soc *soc,
  887. qdf_nbuf_t skb, uint16_t msdu_id,
  888. uint8_t vdev_id)
  889. {
  890. }
  891. #else
  892. static void dp_tx_trace_pkt(struct dp_soc *soc,
  893. qdf_nbuf_t skb, uint16_t msdu_id,
  894. uint8_t vdev_id)
  895. {
  896. if (dp_is_tput_high(soc))
  897. return;
  898. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  899. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  900. DPTRACE(qdf_dp_trace_ptr(skb,
  901. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  902. QDF_TRACE_DEFAULT_PDEV_ID,
  903. qdf_nbuf_data_addr(skb),
  904. sizeof(qdf_nbuf_data(skb)),
  905. msdu_id, vdev_id, 0));
  906. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  907. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  908. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  909. msdu_id, QDF_TX));
  910. }
  911. #endif
  912. #ifdef WLAN_DP_FEATURE_MARK_ICMP_REQ_TO_FW
  913. /**
  914. * dp_tx_is_nbuf_marked_exception() - Check if the packet has been marked as
  915. * exception by the upper layer (OS_IF)
  916. * @soc: DP soc handle
  917. * @nbuf: packet to be transmitted
  918. *
  919. * Returns: 1 if the packet is marked as exception,
  920. * 0, if the packet is not marked as exception.
  921. */
  922. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  923. qdf_nbuf_t nbuf)
  924. {
  925. return QDF_NBUF_CB_TX_PACKET_TO_FW(nbuf);
  926. }
  927. #else
  928. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  929. qdf_nbuf_t nbuf)
  930. {
  931. return 0;
  932. }
  933. #endif
  934. /**
  935. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  936. * @vdev: DP vdev handle
  937. * @nbuf: skb
  938. * @desc_pool_id: Descriptor pool ID
  939. * @meta_data: Metadata to the fw
  940. * @tx_exc_metadata: Handle that holds exception path metadata
  941. * Allocate and prepare Tx descriptor with msdu information.
  942. *
  943. * Return: Pointer to Tx Descriptor on success,
  944. * NULL on failure
  945. */
  946. static
  947. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  948. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  949. struct dp_tx_msdu_info_s *msdu_info,
  950. struct cdp_tx_exception_metadata *tx_exc_metadata)
  951. {
  952. uint8_t align_pad;
  953. uint8_t is_exception = 0;
  954. uint8_t htt_hdr_size;
  955. struct dp_tx_desc_s *tx_desc;
  956. struct dp_pdev *pdev = vdev->pdev;
  957. struct dp_soc *soc = pdev->soc;
  958. if (dp_tx_limit_check(vdev))
  959. return NULL;
  960. /* Allocate software Tx descriptor */
  961. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  962. if (qdf_unlikely(!tx_desc)) {
  963. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  964. DP_STATS_INC(vdev, tx_i.dropped.desc_na_exc_alloc_fail.num, 1);
  965. return NULL;
  966. }
  967. dp_tx_outstanding_inc(pdev);
  968. /* Initialize the SW tx descriptor */
  969. tx_desc->nbuf = nbuf;
  970. tx_desc->frm_type = dp_tx_frm_std;
  971. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  972. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  973. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  974. tx_desc->vdev_id = vdev->vdev_id;
  975. tx_desc->pdev = pdev;
  976. tx_desc->msdu_ext_desc = NULL;
  977. tx_desc->pkt_offset = 0;
  978. tx_desc->length = qdf_nbuf_headlen(nbuf);
  979. dp_tx_trace_pkt(soc, nbuf, tx_desc->id, vdev->vdev_id);
  980. if (qdf_unlikely(vdev->multipass_en)) {
  981. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  982. goto failure;
  983. }
  984. /* Packets marked by upper layer (OS-IF) to be sent to FW */
  985. if (dp_tx_is_nbuf_marked_exception(soc, nbuf))
  986. is_exception = 1;
  987. /*
  988. * For special modes (vdev_type == ocb or mesh), data frames should be
  989. * transmitted using varying transmit parameters (tx spec) which include
  990. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  991. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  992. * These frames are sent as exception packets to firmware.
  993. *
  994. * HW requirement is that metadata should always point to a
  995. * 8-byte aligned address. So we add alignment pad to start of buffer.
  996. * HTT Metadata should be ensured to be multiple of 8-bytes,
  997. * to get 8-byte aligned start address along with align_pad added
  998. *
  999. * |-----------------------------|
  1000. * | |
  1001. * |-----------------------------| <-----Buffer Pointer Address given
  1002. * | | ^ in HW descriptor (aligned)
  1003. * | HTT Metadata | |
  1004. * | | |
  1005. * | | | Packet Offset given in descriptor
  1006. * | | |
  1007. * |-----------------------------| |
  1008. * | Alignment Pad | v
  1009. * |-----------------------------| <----- Actual buffer start address
  1010. * | SKB Data | (Unaligned)
  1011. * | |
  1012. * | |
  1013. * | |
  1014. * | |
  1015. * | |
  1016. * |-----------------------------|
  1017. */
  1018. if (qdf_unlikely((msdu_info->exception_fw)) ||
  1019. (vdev->opmode == wlan_op_mode_ocb) ||
  1020. (tx_exc_metadata &&
  1021. tx_exc_metadata->is_tx_sniffer)) {
  1022. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  1023. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  1024. DP_STATS_INC(vdev,
  1025. tx_i.dropped.headroom_insufficient, 1);
  1026. goto failure;
  1027. }
  1028. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  1029. dp_tx_err("qdf_nbuf_push_head failed");
  1030. goto failure;
  1031. }
  1032. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  1033. msdu_info);
  1034. if (htt_hdr_size == 0)
  1035. goto failure;
  1036. tx_desc->length = qdf_nbuf_headlen(nbuf);
  1037. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  1038. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1039. is_exception = 1;
  1040. tx_desc->length -= tx_desc->pkt_offset;
  1041. }
  1042. #if !TQM_BYPASS_WAR
  1043. if (is_exception || tx_exc_metadata)
  1044. #endif
  1045. {
  1046. /* Temporary WAR due to TQM VP issues */
  1047. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1048. qdf_atomic_inc(&soc->num_tx_exception);
  1049. }
  1050. return tx_desc;
  1051. failure:
  1052. dp_tx_desc_release(tx_desc, desc_pool_id);
  1053. return NULL;
  1054. }
  1055. /**
  1056. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  1057. * @vdev: DP vdev handle
  1058. * @nbuf: skb
  1059. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  1060. * @desc_pool_id : Descriptor Pool ID
  1061. *
  1062. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  1063. * information. For frames wth fragments, allocate and prepare
  1064. * an MSDU extension descriptor
  1065. *
  1066. * Return: Pointer to Tx Descriptor on success,
  1067. * NULL on failure
  1068. */
  1069. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  1070. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  1071. uint8_t desc_pool_id)
  1072. {
  1073. struct dp_tx_desc_s *tx_desc;
  1074. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  1075. struct dp_pdev *pdev = vdev->pdev;
  1076. struct dp_soc *soc = pdev->soc;
  1077. if (dp_tx_limit_check(vdev))
  1078. return NULL;
  1079. /* Allocate software Tx descriptor */
  1080. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  1081. if (!tx_desc) {
  1082. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  1083. return NULL;
  1084. }
  1085. dp_tx_tso_seg_history_add(soc, msdu_info->u.tso_info.curr_seg,
  1086. nbuf, tx_desc->id, DP_TX_DESC_COOKIE);
  1087. dp_tx_outstanding_inc(pdev);
  1088. /* Initialize the SW tx descriptor */
  1089. tx_desc->nbuf = nbuf;
  1090. tx_desc->frm_type = msdu_info->frm_type;
  1091. tx_desc->tx_encap_type = vdev->tx_encap_type;
  1092. tx_desc->vdev_id = vdev->vdev_id;
  1093. tx_desc->pdev = pdev;
  1094. tx_desc->pkt_offset = 0;
  1095. dp_tx_trace_pkt(soc, nbuf, tx_desc->id, vdev->vdev_id);
  1096. /* Handle scattered frames - TSO/SG/ME */
  1097. /* Allocate and prepare an extension descriptor for scattered frames */
  1098. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  1099. if (!msdu_ext_desc) {
  1100. dp_tx_info("Tx Extension Descriptor Alloc Fail");
  1101. goto failure;
  1102. }
  1103. #if TQM_BYPASS_WAR
  1104. /* Temporary WAR due to TQM VP issues */
  1105. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1106. qdf_atomic_inc(&soc->num_tx_exception);
  1107. #endif
  1108. if (qdf_unlikely(msdu_info->exception_fw))
  1109. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1110. tx_desc->msdu_ext_desc = msdu_ext_desc;
  1111. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  1112. msdu_ext_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  1113. msdu_ext_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  1114. tx_desc->dma_addr = msdu_ext_desc->paddr;
  1115. if (msdu_ext_desc->flags & DP_TX_EXT_DESC_FLAG_METADATA_VALID)
  1116. tx_desc->length = HAL_TX_EXT_DESC_WITH_META_DATA;
  1117. else
  1118. tx_desc->length = HAL_TX_EXTENSION_DESC_LEN_BYTES;
  1119. return tx_desc;
  1120. failure:
  1121. dp_tx_desc_release(tx_desc, desc_pool_id);
  1122. return NULL;
  1123. }
  1124. /**
  1125. * dp_tx_prepare_raw() - Prepare RAW packet TX
  1126. * @vdev: DP vdev handle
  1127. * @nbuf: buffer pointer
  1128. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1129. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  1130. * descriptor
  1131. *
  1132. * Return:
  1133. */
  1134. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1135. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1136. {
  1137. qdf_nbuf_t curr_nbuf = NULL;
  1138. uint16_t total_len = 0;
  1139. qdf_dma_addr_t paddr;
  1140. int32_t i;
  1141. int32_t mapped_buf_num = 0;
  1142. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  1143. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1144. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  1145. /* Continue only if frames are of DATA type */
  1146. if (!DP_FRAME_IS_DATA(qos_wh)) {
  1147. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  1148. dp_tx_debug("Pkt. recd is of not data type");
  1149. goto error;
  1150. }
  1151. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  1152. if (vdev->raw_mode_war &&
  1153. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  1154. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  1155. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  1156. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  1157. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  1158. /*
  1159. * Number of nbuf's must not exceed the size of the frags
  1160. * array in seg_info.
  1161. */
  1162. if (i >= DP_TX_MAX_NUM_FRAGS) {
  1163. dp_err_rl("nbuf cnt exceeds the max number of segs");
  1164. DP_STATS_INC(vdev, tx_i.raw.num_frags_overflow_err, 1);
  1165. goto error;
  1166. }
  1167. if (QDF_STATUS_SUCCESS !=
  1168. qdf_nbuf_map_nbytes_single(vdev->osdev,
  1169. curr_nbuf,
  1170. QDF_DMA_TO_DEVICE,
  1171. curr_nbuf->len)) {
  1172. dp_tx_err("%s dma map error ", __func__);
  1173. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  1174. goto error;
  1175. }
  1176. /* Update the count of mapped nbuf's */
  1177. mapped_buf_num++;
  1178. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  1179. seg_info->frags[i].paddr_lo = paddr;
  1180. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  1181. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  1182. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  1183. total_len += qdf_nbuf_len(curr_nbuf);
  1184. }
  1185. seg_info->frag_cnt = i;
  1186. seg_info->total_len = total_len;
  1187. seg_info->next = NULL;
  1188. sg_info->curr_seg = seg_info;
  1189. msdu_info->frm_type = dp_tx_frm_raw;
  1190. msdu_info->num_seg = 1;
  1191. return nbuf;
  1192. error:
  1193. i = 0;
  1194. while (nbuf) {
  1195. curr_nbuf = nbuf;
  1196. if (i < mapped_buf_num) {
  1197. qdf_nbuf_unmap_nbytes_single(vdev->osdev, curr_nbuf,
  1198. QDF_DMA_TO_DEVICE,
  1199. curr_nbuf->len);
  1200. i++;
  1201. }
  1202. nbuf = qdf_nbuf_next(nbuf);
  1203. qdf_nbuf_free(curr_nbuf);
  1204. }
  1205. return NULL;
  1206. }
  1207. /**
  1208. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  1209. * @soc: DP soc handle
  1210. * @nbuf: Buffer pointer
  1211. *
  1212. * unmap the chain of nbufs that belong to this RAW frame.
  1213. *
  1214. * Return: None
  1215. */
  1216. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  1217. qdf_nbuf_t nbuf)
  1218. {
  1219. qdf_nbuf_t cur_nbuf = nbuf;
  1220. do {
  1221. qdf_nbuf_unmap_nbytes_single(soc->osdev, cur_nbuf,
  1222. QDF_DMA_TO_DEVICE,
  1223. cur_nbuf->len);
  1224. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  1225. } while (cur_nbuf);
  1226. }
  1227. #ifdef VDEV_PEER_PROTOCOL_COUNT
  1228. void dp_vdev_peer_stats_update_protocol_cnt_tx(struct dp_vdev *vdev_hdl,
  1229. qdf_nbuf_t nbuf)
  1230. {
  1231. qdf_nbuf_t nbuf_local;
  1232. struct dp_vdev *vdev_local = vdev_hdl;
  1233. do {
  1234. if (qdf_likely(!((vdev_local)->peer_protocol_count_track)))
  1235. break;
  1236. nbuf_local = nbuf;
  1237. if (qdf_unlikely(((vdev_local)->tx_encap_type) ==
  1238. htt_cmn_pkt_type_raw))
  1239. break;
  1240. else if (qdf_unlikely(qdf_nbuf_is_nonlinear((nbuf_local))))
  1241. break;
  1242. else if (qdf_nbuf_is_tso((nbuf_local)))
  1243. break;
  1244. dp_vdev_peer_stats_update_protocol_cnt((vdev_local),
  1245. (nbuf_local),
  1246. NULL, 1, 0);
  1247. } while (0);
  1248. }
  1249. #endif
  1250. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  1251. /**
  1252. * dp_tx_update_stats() - Update soc level tx stats
  1253. * @soc: DP soc handle
  1254. * @nbuf: packet being transmitted
  1255. *
  1256. * Returns: none
  1257. */
  1258. void dp_tx_update_stats(struct dp_soc *soc,
  1259. qdf_nbuf_t nbuf)
  1260. {
  1261. DP_STATS_INC_PKT(soc, tx.egress, 1, qdf_nbuf_len(nbuf));
  1262. }
  1263. int
  1264. dp_tx_attempt_coalescing(struct dp_soc *soc, struct dp_vdev *vdev,
  1265. struct dp_tx_desc_s *tx_desc,
  1266. uint8_t tid)
  1267. {
  1268. struct dp_swlm *swlm = &soc->swlm;
  1269. union swlm_data swlm_query_data;
  1270. struct dp_swlm_tcl_data tcl_data;
  1271. QDF_STATUS status;
  1272. int ret;
  1273. if (qdf_unlikely(!swlm->is_enabled))
  1274. return 0;
  1275. tcl_data.nbuf = tx_desc->nbuf;
  1276. tcl_data.tid = tid;
  1277. tcl_data.num_ll_connections = vdev->num_latency_critical_conn;
  1278. swlm_query_data.tcl_data = &tcl_data;
  1279. status = dp_swlm_tcl_pre_check(soc, &tcl_data);
  1280. if (QDF_IS_STATUS_ERROR(status)) {
  1281. dp_swlm_tcl_reset_session_data(soc);
  1282. DP_STATS_INC(swlm, tcl.coalesce_fail, 1);
  1283. return 0;
  1284. }
  1285. ret = dp_swlm_query_policy(soc, TCL_DATA, swlm_query_data);
  1286. if (ret) {
  1287. DP_STATS_INC(swlm, tcl.coalesce_success, 1);
  1288. } else {
  1289. DP_STATS_INC(swlm, tcl.coalesce_fail, 1);
  1290. }
  1291. return ret;
  1292. }
  1293. void
  1294. dp_tx_ring_access_end(struct dp_soc *soc, hal_ring_handle_t hal_ring_hdl,
  1295. int coalesce)
  1296. {
  1297. if (coalesce)
  1298. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1299. else
  1300. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1301. }
  1302. #endif
  1303. #ifdef FEATURE_RUNTIME_PM
  1304. static inline int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc)
  1305. {
  1306. return qdf_atomic_read(&soc->rtpm_high_tput_flag);
  1307. }
  1308. /**
  1309. * dp_tx_ring_access_end_wrapper() - Wrapper for ring access end
  1310. * @soc: Datapath soc handle
  1311. * @hal_ring_hdl: HAL ring handle
  1312. * @coalesce: Coalesce the current write or not
  1313. *
  1314. * Wrapper for HAL ring access end for data transmission for
  1315. * FEATURE_RUNTIME_PM
  1316. *
  1317. * Returns: none
  1318. */
  1319. void
  1320. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1321. hal_ring_handle_t hal_ring_hdl,
  1322. int coalesce)
  1323. {
  1324. int ret;
  1325. /*
  1326. * Avoid runtime get and put APIs under high throughput scenarios.
  1327. */
  1328. if (dp_get_rtpm_tput_policy_requirement(soc)) {
  1329. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1330. return;
  1331. }
  1332. ret = hif_pm_runtime_get(soc->hif_handle,
  1333. RTPM_ID_DW_TX_HW_ENQUEUE, true);
  1334. switch (ret) {
  1335. case 0:
  1336. if (hif_system_pm_state_check(soc->hif_handle)) {
  1337. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1338. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1339. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1340. } else {
  1341. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1342. }
  1343. hif_pm_runtime_put(soc->hif_handle,
  1344. RTPM_ID_DW_TX_HW_ENQUEUE);
  1345. break;
  1346. /*
  1347. * If hif_pm_runtime_get returns -EBUSY or -EINPROGRESS,
  1348. * take the dp runtime refcount using dp_runtime_get,
  1349. * check link state,if up, write TX ring HP, else just set flush event.
  1350. * In dp_runtime_resume, wait until dp runtime refcount becomes
  1351. * zero or time out, then flush pending tx.
  1352. */
  1353. case -EBUSY:
  1354. case -EINPROGRESS:
  1355. dp_runtime_get(soc);
  1356. if (hif_pm_get_link_state(soc->hif_handle) ==
  1357. HIF_PM_LINK_STATE_UP) {
  1358. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1359. } else {
  1360. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1361. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1362. qdf_atomic_inc(&soc->tx_pending_rtpm);
  1363. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1364. }
  1365. dp_runtime_put(soc);
  1366. break;
  1367. default:
  1368. dp_runtime_get(soc);
  1369. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1370. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1371. qdf_atomic_inc(&soc->tx_pending_rtpm);
  1372. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1373. dp_runtime_put(soc);
  1374. }
  1375. }
  1376. #else
  1377. #ifdef DP_POWER_SAVE
  1378. void
  1379. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1380. hal_ring_handle_t hal_ring_hdl,
  1381. int coalesce)
  1382. {
  1383. if (hif_system_pm_state_check(soc->hif_handle)) {
  1384. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1385. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1386. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1387. } else {
  1388. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1389. }
  1390. }
  1391. #endif
  1392. static inline int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc)
  1393. {
  1394. return 0;
  1395. }
  1396. #endif
  1397. /**
  1398. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1399. * @vdev: DP vdev handle
  1400. * @nbuf: skb
  1401. *
  1402. * Extract the DSCP or PCP information from frame and map into TID value.
  1403. *
  1404. * Return: void
  1405. */
  1406. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1407. struct dp_tx_msdu_info_s *msdu_info)
  1408. {
  1409. uint8_t tos = 0, dscp_tid_override = 0;
  1410. uint8_t *hdr_ptr, *L3datap;
  1411. uint8_t is_mcast = 0;
  1412. qdf_ether_header_t *eh = NULL;
  1413. qdf_ethervlan_header_t *evh = NULL;
  1414. uint16_t ether_type;
  1415. qdf_llc_t *llcHdr;
  1416. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1417. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1418. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1419. eh = (qdf_ether_header_t *)nbuf->data;
  1420. hdr_ptr = (uint8_t *)(eh->ether_dhost);
  1421. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1422. } else {
  1423. qdf_dot3_qosframe_t *qos_wh =
  1424. (qdf_dot3_qosframe_t *) nbuf->data;
  1425. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1426. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1427. return;
  1428. }
  1429. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1430. ether_type = eh->ether_type;
  1431. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1432. /*
  1433. * Check if packet is dot3 or eth2 type.
  1434. */
  1435. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1436. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1437. sizeof(*llcHdr));
  1438. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1439. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1440. sizeof(*llcHdr);
  1441. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1442. + sizeof(*llcHdr) +
  1443. sizeof(qdf_net_vlanhdr_t));
  1444. } else {
  1445. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1446. sizeof(*llcHdr);
  1447. }
  1448. } else {
  1449. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1450. evh = (qdf_ethervlan_header_t *) eh;
  1451. ether_type = evh->ether_type;
  1452. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1453. }
  1454. }
  1455. /*
  1456. * Find priority from IP TOS DSCP field
  1457. */
  1458. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1459. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1460. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1461. /* Only for unicast frames */
  1462. if (!is_mcast) {
  1463. /* send it on VO queue */
  1464. msdu_info->tid = DP_VO_TID;
  1465. }
  1466. } else {
  1467. /*
  1468. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1469. * from TOS byte.
  1470. */
  1471. tos = ip->ip_tos;
  1472. dscp_tid_override = 1;
  1473. }
  1474. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1475. /* TODO
  1476. * use flowlabel
  1477. *igmpmld cases to be handled in phase 2
  1478. */
  1479. unsigned long ver_pri_flowlabel;
  1480. unsigned long pri;
  1481. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1482. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1483. DP_IPV6_PRIORITY_SHIFT;
  1484. tos = pri;
  1485. dscp_tid_override = 1;
  1486. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1487. msdu_info->tid = DP_VO_TID;
  1488. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1489. /* Only for unicast frames */
  1490. if (!is_mcast) {
  1491. /* send ucast arp on VO queue */
  1492. msdu_info->tid = DP_VO_TID;
  1493. }
  1494. }
  1495. /*
  1496. * Assign all MCAST packets to BE
  1497. */
  1498. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1499. if (is_mcast) {
  1500. tos = 0;
  1501. dscp_tid_override = 1;
  1502. }
  1503. }
  1504. if (dscp_tid_override == 1) {
  1505. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1506. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1507. }
  1508. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1509. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1510. return;
  1511. }
  1512. /**
  1513. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1514. * @vdev: DP vdev handle
  1515. * @nbuf: skb
  1516. *
  1517. * Software based TID classification is required when more than 2 DSCP-TID
  1518. * mapping tables are needed.
  1519. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1520. *
  1521. * Return: void
  1522. */
  1523. static inline void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1524. struct dp_tx_msdu_info_s *msdu_info)
  1525. {
  1526. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1527. /*
  1528. * skip_sw_tid_classification flag will set in below cases-
  1529. * 1. vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map
  1530. * 2. hlos_tid_override enabled for vdev
  1531. * 3. mesh mode enabled for vdev
  1532. */
  1533. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1534. /* Update tid in msdu_info from skb priority */
  1535. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1536. & DP_TXRX_HLOS_TID_OVERRIDE_ENABLED)) {
  1537. uint32_t tid = qdf_nbuf_get_priority(nbuf);
  1538. if (tid == DP_TX_INVALID_QOS_TAG)
  1539. return;
  1540. msdu_info->tid = tid;
  1541. return;
  1542. }
  1543. return;
  1544. }
  1545. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1546. }
  1547. #ifdef FEATURE_WLAN_TDLS
  1548. /**
  1549. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1550. * @soc: datapath SOC
  1551. * @vdev: datapath vdev
  1552. * @tx_desc: TX descriptor
  1553. *
  1554. * Return: None
  1555. */
  1556. static void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1557. struct dp_vdev *vdev,
  1558. struct dp_tx_desc_s *tx_desc)
  1559. {
  1560. if (vdev) {
  1561. if (vdev->is_tdls_frame) {
  1562. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1563. vdev->is_tdls_frame = false;
  1564. }
  1565. }
  1566. }
  1567. static uint8_t dp_htt_tx_comp_get_status(struct dp_soc *soc, char *htt_desc)
  1568. {
  1569. uint8_t tx_status = HTT_TX_FW2WBM_TX_STATUS_MAX;
  1570. switch (soc->arch_id) {
  1571. case CDP_ARCH_TYPE_LI:
  1572. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  1573. break;
  1574. case CDP_ARCH_TYPE_BE:
  1575. tx_status = HTT_TX_WBM_COMPLETION_V3_TX_STATUS_GET(htt_desc[0]);
  1576. break;
  1577. default:
  1578. dp_err("Incorrect CDP_ARCH %d", soc->arch_id);
  1579. QDF_BUG(0);
  1580. }
  1581. return tx_status;
  1582. }
  1583. /**
  1584. * dp_non_std_htt_tx_comp_free_buff() - Free the non std tx packet buffer
  1585. * @soc: dp_soc handle
  1586. * @tx_desc: TX descriptor
  1587. * @vdev: datapath vdev handle
  1588. *
  1589. * Return: None
  1590. */
  1591. static void dp_non_std_htt_tx_comp_free_buff(struct dp_soc *soc,
  1592. struct dp_tx_desc_s *tx_desc)
  1593. {
  1594. uint8_t tx_status = 0;
  1595. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  1596. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1597. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1598. DP_MOD_ID_TDLS);
  1599. if (qdf_unlikely(!vdev)) {
  1600. dp_err_rl("vdev is null!");
  1601. goto error;
  1602. }
  1603. hal_tx_comp_get_htt_desc(&tx_desc->comp, htt_tx_status);
  1604. tx_status = dp_htt_tx_comp_get_status(soc, htt_tx_status);
  1605. dp_debug("vdev_id: %d tx_status: %d", tx_desc->vdev_id, tx_status);
  1606. if (vdev->tx_non_std_data_callback.func) {
  1607. qdf_nbuf_set_next(nbuf, NULL);
  1608. vdev->tx_non_std_data_callback.func(
  1609. vdev->tx_non_std_data_callback.ctxt,
  1610. nbuf, tx_status);
  1611. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1612. return;
  1613. } else {
  1614. dp_err_rl("callback func is null");
  1615. }
  1616. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1617. error:
  1618. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1619. qdf_nbuf_free(nbuf);
  1620. }
  1621. /**
  1622. * dp_tx_msdu_single_map() - do nbuf map
  1623. * @vdev: DP vdev handle
  1624. * @tx_desc: DP TX descriptor pointer
  1625. * @nbuf: skb pointer
  1626. *
  1627. * For TDLS frame, use qdf_nbuf_map_single() to align with the unmap
  1628. * operation done in other component.
  1629. *
  1630. * Return: QDF_STATUS
  1631. */
  1632. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1633. struct dp_tx_desc_s *tx_desc,
  1634. qdf_nbuf_t nbuf)
  1635. {
  1636. if (qdf_likely(!(tx_desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)))
  1637. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1638. nbuf,
  1639. QDF_DMA_TO_DEVICE,
  1640. nbuf->len);
  1641. else
  1642. return qdf_nbuf_map_single(vdev->osdev, nbuf,
  1643. QDF_DMA_TO_DEVICE);
  1644. }
  1645. #else
  1646. static inline void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1647. struct dp_vdev *vdev,
  1648. struct dp_tx_desc_s *tx_desc)
  1649. {
  1650. }
  1651. static inline void dp_non_std_htt_tx_comp_free_buff(struct dp_soc *soc,
  1652. struct dp_tx_desc_s *tx_desc)
  1653. {
  1654. }
  1655. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1656. struct dp_tx_desc_s *tx_desc,
  1657. qdf_nbuf_t nbuf)
  1658. {
  1659. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1660. nbuf,
  1661. QDF_DMA_TO_DEVICE,
  1662. nbuf->len);
  1663. }
  1664. #endif
  1665. #if defined(QCA_DP_TX_NBUF_NO_MAP_UNMAP) && !defined(BUILD_X86)
  1666. static inline
  1667. qdf_dma_addr_t dp_tx_nbuf_map(struct dp_vdev *vdev,
  1668. struct dp_tx_desc_s *tx_desc,
  1669. qdf_nbuf_t nbuf)
  1670. {
  1671. qdf_nbuf_dma_clean_range((void *)nbuf->data,
  1672. (void *)(nbuf->data + nbuf->len));
  1673. return (qdf_dma_addr_t)qdf_mem_virt_to_phys(nbuf->data);
  1674. }
  1675. static inline
  1676. void dp_tx_nbuf_unmap(struct dp_soc *soc,
  1677. struct dp_tx_desc_s *desc)
  1678. {
  1679. }
  1680. #else
  1681. static inline
  1682. qdf_dma_addr_t dp_tx_nbuf_map(struct dp_vdev *vdev,
  1683. struct dp_tx_desc_s *tx_desc,
  1684. qdf_nbuf_t nbuf)
  1685. {
  1686. QDF_STATUS ret = QDF_STATUS_E_FAILURE;
  1687. ret = dp_tx_msdu_single_map(vdev, tx_desc, nbuf);
  1688. if (qdf_unlikely(QDF_IS_STATUS_ERROR(ret)))
  1689. return 0;
  1690. return qdf_nbuf_mapped_paddr_get(nbuf);
  1691. }
  1692. static inline
  1693. void dp_tx_nbuf_unmap(struct dp_soc *soc,
  1694. struct dp_tx_desc_s *desc)
  1695. {
  1696. qdf_nbuf_unmap_nbytes_single_paddr(soc->osdev,
  1697. desc->nbuf,
  1698. desc->dma_addr,
  1699. QDF_DMA_TO_DEVICE,
  1700. desc->length);
  1701. }
  1702. #endif
  1703. #ifdef MESH_MODE_SUPPORT
  1704. /**
  1705. * dp_tx_update_mesh_flags() - Update descriptor flags for mesh VAP
  1706. * @soc: datapath SOC
  1707. * @vdev: datapath vdev
  1708. * @tx_desc: TX descriptor
  1709. *
  1710. * Return: None
  1711. */
  1712. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1713. struct dp_vdev *vdev,
  1714. struct dp_tx_desc_s *tx_desc)
  1715. {
  1716. if (qdf_unlikely(vdev->mesh_vdev))
  1717. tx_desc->flags |= DP_TX_DESC_FLAG_MESH_MODE;
  1718. }
  1719. /**
  1720. * dp_mesh_tx_comp_free_buff() - Free the mesh tx packet buffer
  1721. * @soc: dp_soc handle
  1722. * @tx_desc: TX descriptor
  1723. * @vdev: datapath vdev handle
  1724. *
  1725. * Return: None
  1726. */
  1727. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1728. struct dp_tx_desc_s *tx_desc)
  1729. {
  1730. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1731. struct dp_vdev *vdev = NULL;
  1732. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  1733. qdf_nbuf_free(nbuf);
  1734. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  1735. } else {
  1736. vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1737. DP_MOD_ID_MESH);
  1738. if (vdev && vdev->osif_tx_free_ext)
  1739. vdev->osif_tx_free_ext((nbuf));
  1740. else
  1741. qdf_nbuf_free(nbuf);
  1742. if (vdev)
  1743. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  1744. }
  1745. }
  1746. #else
  1747. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1748. struct dp_vdev *vdev,
  1749. struct dp_tx_desc_s *tx_desc)
  1750. {
  1751. }
  1752. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1753. struct dp_tx_desc_s *tx_desc)
  1754. {
  1755. }
  1756. #endif
  1757. /**
  1758. * dp_tx_frame_is_drop() - checks if the packet is loopback
  1759. * @vdev: DP vdev handle
  1760. * @nbuf: skb
  1761. *
  1762. * Return: 1 if frame needs to be dropped else 0
  1763. */
  1764. int dp_tx_frame_is_drop(struct dp_vdev *vdev, uint8_t *srcmac, uint8_t *dstmac)
  1765. {
  1766. struct dp_pdev *pdev = NULL;
  1767. struct dp_ast_entry *src_ast_entry = NULL;
  1768. struct dp_ast_entry *dst_ast_entry = NULL;
  1769. struct dp_soc *soc = NULL;
  1770. qdf_assert(vdev);
  1771. pdev = vdev->pdev;
  1772. qdf_assert(pdev);
  1773. soc = pdev->soc;
  1774. dst_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1775. (soc, dstmac, vdev->pdev->pdev_id);
  1776. src_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1777. (soc, srcmac, vdev->pdev->pdev_id);
  1778. if (dst_ast_entry && src_ast_entry) {
  1779. if (dst_ast_entry->peer_id ==
  1780. src_ast_entry->peer_id)
  1781. return 1;
  1782. }
  1783. return 0;
  1784. }
  1785. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  1786. defined(WLAN_MCAST_MLO)
  1787. /* MLO peer id for reinject*/
  1788. #define DP_MLO_MCAST_REINJECT_PEER_ID 0XFFFD
  1789. /* MLO vdev id inc offset */
  1790. #define DP_MLO_VDEV_ID_OFFSET 0x80
  1791. static inline void
  1792. dp_tx_update_mcast_param(uint16_t peer_id,
  1793. uint16_t *htt_tcl_metadata,
  1794. struct dp_vdev *vdev,
  1795. struct dp_tx_msdu_info_s *msdu_info)
  1796. {
  1797. if (peer_id == DP_MLO_MCAST_REINJECT_PEER_ID) {
  1798. *htt_tcl_metadata = 0;
  1799. DP_TX_TCL_METADATA_TYPE_SET(
  1800. *htt_tcl_metadata,
  1801. HTT_TCL_METADATA_V2_TYPE_GLOBAL_SEQ_BASED);
  1802. HTT_TX_TCL_METADATA_GLBL_SEQ_NO_SET(*htt_tcl_metadata,
  1803. msdu_info->gsn);
  1804. msdu_info->vdev_id = vdev->vdev_id + DP_MLO_VDEV_ID_OFFSET;
  1805. } else {
  1806. msdu_info->vdev_id = vdev->vdev_id;
  1807. }
  1808. }
  1809. #else
  1810. static inline void
  1811. dp_tx_update_mcast_param(uint16_t peer_id,
  1812. uint16_t *htt_tcl_metadata,
  1813. struct dp_vdev *vdev,
  1814. struct dp_tx_msdu_info_s *msdu_info)
  1815. {
  1816. }
  1817. #endif
  1818. /**
  1819. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1820. * @vdev: DP vdev handle
  1821. * @nbuf: skb
  1822. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1823. * @meta_data: Metadata to the fw
  1824. * @tx_q: Tx queue to be used for this Tx frame
  1825. * @peer_id: peer_id of the peer in case of NAWDS frames
  1826. * @tx_exc_metadata: Handle that holds exception path metadata
  1827. *
  1828. * Return: NULL on success,
  1829. * nbuf when it fails to send
  1830. */
  1831. qdf_nbuf_t
  1832. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1833. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1834. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1835. {
  1836. struct dp_pdev *pdev = vdev->pdev;
  1837. struct dp_soc *soc = pdev->soc;
  1838. struct dp_tx_desc_s *tx_desc;
  1839. QDF_STATUS status;
  1840. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1841. uint16_t htt_tcl_metadata = 0;
  1842. enum cdp_tx_sw_drop drop_code = TX_MAX_DROP;
  1843. uint8_t tid = msdu_info->tid;
  1844. struct cdp_tid_tx_stats *tid_stats = NULL;
  1845. qdf_dma_addr_t paddr;
  1846. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1847. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1848. msdu_info, tx_exc_metadata);
  1849. if (!tx_desc) {
  1850. dp_err_rl("Tx_desc prepare Fail vdev %pK queue %d",
  1851. vdev, tx_q->desc_pool_id);
  1852. drop_code = TX_DESC_ERR;
  1853. goto fail_return;
  1854. }
  1855. dp_tx_update_tdls_flags(soc, vdev, tx_desc);
  1856. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1857. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1858. DP_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1859. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1860. DP_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1861. DP_TCL_METADATA_TYPE_PEER_BASED);
  1862. DP_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1863. peer_id);
  1864. } else
  1865. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1866. if (msdu_info->exception_fw)
  1867. DP_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1868. dp_tx_desc_update_fast_comp_flag(soc, tx_desc,
  1869. !pdev->enhanced_stats_en);
  1870. dp_tx_update_mesh_flags(soc, vdev, tx_desc);
  1871. paddr = dp_tx_nbuf_map(vdev, tx_desc, nbuf);
  1872. if (!paddr) {
  1873. /* Handle failure */
  1874. dp_err("qdf_nbuf_map failed");
  1875. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  1876. drop_code = TX_DMA_MAP_ERR;
  1877. goto release_desc;
  1878. }
  1879. tx_desc->dma_addr = paddr;
  1880. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  1881. tx_desc->id, DP_TX_DESC_MAP);
  1882. dp_tx_update_mcast_param(peer_id, &htt_tcl_metadata, vdev, msdu_info);
  1883. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1884. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  1885. htt_tcl_metadata,
  1886. tx_exc_metadata, msdu_info);
  1887. if (status != QDF_STATUS_SUCCESS) {
  1888. dp_tx_err_rl("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1889. tx_desc, tx_q->ring_id);
  1890. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  1891. tx_desc->id, DP_TX_DESC_UNMAP);
  1892. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  1893. QDF_DMA_TO_DEVICE,
  1894. nbuf->len);
  1895. drop_code = TX_HW_ENQUEUE;
  1896. goto release_desc;
  1897. }
  1898. return NULL;
  1899. release_desc:
  1900. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1901. fail_return:
  1902. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1903. tid_stats = &pdev->stats.tid_stats.
  1904. tid_tx_stats[tx_q->ring_id][tid];
  1905. tid_stats->swdrop_cnt[drop_code]++;
  1906. return nbuf;
  1907. }
  1908. /**
  1909. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  1910. * @soc: Soc handle
  1911. * @desc: software Tx descriptor to be processed
  1912. *
  1913. * Return: none
  1914. */
  1915. void dp_tx_comp_free_buf(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1916. {
  1917. qdf_nbuf_t nbuf = desc->nbuf;
  1918. enum dp_tx_event_type type = dp_tx_get_event_type(desc->flags);
  1919. /* nbuf already freed in vdev detach path */
  1920. if (!nbuf)
  1921. return;
  1922. /* If it is TDLS mgmt, don't unmap or free the frame */
  1923. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  1924. return dp_non_std_htt_tx_comp_free_buff(soc, desc);
  1925. /* 0 : MSDU buffer, 1 : MLE */
  1926. if (desc->msdu_ext_desc) {
  1927. /* TSO free */
  1928. if (hal_tx_ext_desc_get_tso_enable(
  1929. desc->msdu_ext_desc->vaddr)) {
  1930. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  1931. desc->id, DP_TX_COMP_MSDU_EXT);
  1932. dp_tx_tso_seg_history_add(soc,
  1933. desc->msdu_ext_desc->tso_desc,
  1934. desc->nbuf, desc->id, type);
  1935. /* unmap eash TSO seg before free the nbuf */
  1936. dp_tx_tso_unmap_segment(soc,
  1937. desc->msdu_ext_desc->tso_desc,
  1938. desc->msdu_ext_desc->
  1939. tso_num_desc);
  1940. qdf_nbuf_free(nbuf);
  1941. return;
  1942. }
  1943. if (qdf_unlikely(desc->frm_type == dp_tx_frm_sg)) {
  1944. void *msdu_ext_desc = desc->msdu_ext_desc->vaddr;
  1945. qdf_dma_addr_t iova;
  1946. uint32_t frag_len;
  1947. uint32_t i;
  1948. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf,
  1949. QDF_DMA_TO_DEVICE,
  1950. qdf_nbuf_headlen(nbuf));
  1951. for (i = 1; i < DP_TX_MAX_NUM_FRAGS; i++) {
  1952. hal_tx_ext_desc_get_frag_info(msdu_ext_desc, i,
  1953. &iova,
  1954. &frag_len);
  1955. if (!iova || !frag_len)
  1956. break;
  1957. qdf_mem_unmap_page(soc->osdev, iova, frag_len,
  1958. QDF_DMA_TO_DEVICE);
  1959. }
  1960. qdf_nbuf_free(nbuf);
  1961. return;
  1962. }
  1963. }
  1964. /* If it's ME frame, dont unmap the cloned nbuf's */
  1965. if ((desc->flags & DP_TX_DESC_FLAG_ME) && qdf_nbuf_is_cloned(nbuf))
  1966. goto nbuf_free;
  1967. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf, desc->id, type);
  1968. dp_tx_unmap(soc, desc);
  1969. if (desc->flags & DP_TX_DESC_FLAG_MESH_MODE)
  1970. return dp_mesh_tx_comp_free_buff(soc, desc);
  1971. nbuf_free:
  1972. qdf_nbuf_free(nbuf);
  1973. }
  1974. /**
  1975. * dp_tx_sg_unmap_buf() - Unmap scatter gather fragments
  1976. * @soc: DP soc handle
  1977. * @nbuf: skb
  1978. * @msdu_info: MSDU info
  1979. *
  1980. * Return: None
  1981. */
  1982. static inline void
  1983. dp_tx_sg_unmap_buf(struct dp_soc *soc, qdf_nbuf_t nbuf,
  1984. struct dp_tx_msdu_info_s *msdu_info)
  1985. {
  1986. uint32_t cur_idx;
  1987. struct dp_tx_seg_info_s *seg = msdu_info->u.sg_info.curr_seg;
  1988. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE,
  1989. qdf_nbuf_headlen(nbuf));
  1990. for (cur_idx = 1; cur_idx < seg->frag_cnt; cur_idx++)
  1991. qdf_mem_unmap_page(soc->osdev, (qdf_dma_addr_t)
  1992. (seg->frags[cur_idx].paddr_lo | ((uint64_t)
  1993. seg->frags[cur_idx].paddr_hi) << 32),
  1994. seg->frags[cur_idx].len,
  1995. QDF_DMA_TO_DEVICE);
  1996. }
  1997. /**
  1998. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1999. * @vdev: DP vdev handle
  2000. * @nbuf: skb
  2001. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  2002. *
  2003. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  2004. *
  2005. * Return: NULL on success,
  2006. * nbuf when it fails to send
  2007. */
  2008. #if QDF_LOCK_STATS
  2009. noinline
  2010. #else
  2011. #endif
  2012. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2013. struct dp_tx_msdu_info_s *msdu_info)
  2014. {
  2015. uint32_t i;
  2016. struct dp_pdev *pdev = vdev->pdev;
  2017. struct dp_soc *soc = pdev->soc;
  2018. struct dp_tx_desc_s *tx_desc;
  2019. bool is_cce_classified = false;
  2020. QDF_STATUS status;
  2021. uint16_t htt_tcl_metadata = 0;
  2022. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  2023. struct cdp_tid_tx_stats *tid_stats = NULL;
  2024. uint8_t prep_desc_fail = 0, hw_enq_fail = 0;
  2025. if (msdu_info->frm_type == dp_tx_frm_me)
  2026. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2027. i = 0;
  2028. /* Print statement to track i and num_seg */
  2029. /*
  2030. * For each segment (maps to 1 MSDU) , prepare software and hardware
  2031. * descriptors using information in msdu_info
  2032. */
  2033. while (i < msdu_info->num_seg) {
  2034. /*
  2035. * Setup Tx descriptor for an MSDU, and MSDU extension
  2036. * descriptor
  2037. */
  2038. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  2039. tx_q->desc_pool_id);
  2040. if (!tx_desc) {
  2041. if (msdu_info->frm_type == dp_tx_frm_me) {
  2042. prep_desc_fail++;
  2043. dp_tx_me_free_buf(pdev,
  2044. (void *)(msdu_info->u.sg_info
  2045. .curr_seg->frags[0].vaddr));
  2046. if (prep_desc_fail == msdu_info->num_seg) {
  2047. /*
  2048. * Unmap is needed only if descriptor
  2049. * preparation failed for all segments.
  2050. */
  2051. qdf_nbuf_unmap(soc->osdev,
  2052. msdu_info->u.sg_info.
  2053. curr_seg->nbuf,
  2054. QDF_DMA_TO_DEVICE);
  2055. }
  2056. /*
  2057. * Free the nbuf for the current segment
  2058. * and make it point to the next in the list.
  2059. * For me, there are as many segments as there
  2060. * are no of clients.
  2061. */
  2062. qdf_nbuf_free(msdu_info->u.sg_info
  2063. .curr_seg->nbuf);
  2064. if (msdu_info->u.sg_info.curr_seg->next) {
  2065. msdu_info->u.sg_info.curr_seg =
  2066. msdu_info->u.sg_info
  2067. .curr_seg->next;
  2068. nbuf = msdu_info->u.sg_info
  2069. .curr_seg->nbuf;
  2070. }
  2071. i++;
  2072. continue;
  2073. }
  2074. if (msdu_info->frm_type == dp_tx_frm_tso) {
  2075. dp_tx_tso_seg_history_add(
  2076. soc,
  2077. msdu_info->u.tso_info.curr_seg,
  2078. nbuf, 0, DP_TX_DESC_UNMAP);
  2079. dp_tx_tso_unmap_segment(soc,
  2080. msdu_info->u.tso_info.
  2081. curr_seg,
  2082. msdu_info->u.tso_info.
  2083. tso_num_seg_list);
  2084. if (msdu_info->u.tso_info.curr_seg->next) {
  2085. msdu_info->u.tso_info.curr_seg =
  2086. msdu_info->u.tso_info.curr_seg->next;
  2087. i++;
  2088. continue;
  2089. }
  2090. }
  2091. if (msdu_info->frm_type == dp_tx_frm_sg)
  2092. dp_tx_sg_unmap_buf(soc, nbuf, msdu_info);
  2093. goto done;
  2094. }
  2095. if (msdu_info->frm_type == dp_tx_frm_me) {
  2096. tx_desc->msdu_ext_desc->me_buffer =
  2097. (struct dp_tx_me_buf_t *)msdu_info->
  2098. u.sg_info.curr_seg->frags[0].vaddr;
  2099. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  2100. }
  2101. if (is_cce_classified)
  2102. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  2103. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2104. if (msdu_info->exception_fw) {
  2105. DP_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  2106. }
  2107. /*
  2108. * For frames with multiple segments (TSO, ME), jump to next
  2109. * segment.
  2110. */
  2111. if (msdu_info->frm_type == dp_tx_frm_tso) {
  2112. if (msdu_info->u.tso_info.curr_seg->next) {
  2113. msdu_info->u.tso_info.curr_seg =
  2114. msdu_info->u.tso_info.curr_seg->next;
  2115. /*
  2116. * If this is a jumbo nbuf, then increment the
  2117. * number of nbuf users for each additional
  2118. * segment of the msdu. This will ensure that
  2119. * the skb is freed only after receiving tx
  2120. * completion for all segments of an nbuf
  2121. */
  2122. qdf_nbuf_inc_users(nbuf);
  2123. /* Check with MCL if this is needed */
  2124. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf;
  2125. */
  2126. }
  2127. }
  2128. dp_tx_update_mcast_param(DP_INVALID_PEER,
  2129. &htt_tcl_metadata,
  2130. vdev,
  2131. msdu_info);
  2132. /*
  2133. * Enqueue the Tx MSDU descriptor to HW for transmit
  2134. */
  2135. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  2136. htt_tcl_metadata,
  2137. NULL, msdu_info);
  2138. if (status != QDF_STATUS_SUCCESS) {
  2139. dp_info_rl("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  2140. tx_desc, tx_q->ring_id);
  2141. dp_tx_get_tid(vdev, nbuf, msdu_info);
  2142. tid_stats = &pdev->stats.tid_stats.
  2143. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  2144. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  2145. if (msdu_info->frm_type == dp_tx_frm_me) {
  2146. hw_enq_fail++;
  2147. if (hw_enq_fail == msdu_info->num_seg) {
  2148. /*
  2149. * Unmap is needed only if enqueue
  2150. * failed for all segments.
  2151. */
  2152. qdf_nbuf_unmap(soc->osdev,
  2153. msdu_info->u.sg_info.
  2154. curr_seg->nbuf,
  2155. QDF_DMA_TO_DEVICE);
  2156. }
  2157. /*
  2158. * Free the nbuf for the current segment
  2159. * and make it point to the next in the list.
  2160. * For me, there are as many segments as there
  2161. * are no of clients.
  2162. */
  2163. qdf_nbuf_free(msdu_info->u.sg_info
  2164. .curr_seg->nbuf);
  2165. if (msdu_info->u.sg_info.curr_seg->next) {
  2166. msdu_info->u.sg_info.curr_seg =
  2167. msdu_info->u.sg_info
  2168. .curr_seg->next;
  2169. nbuf = msdu_info->u.sg_info
  2170. .curr_seg->nbuf;
  2171. } else
  2172. break;
  2173. i++;
  2174. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2175. continue;
  2176. }
  2177. /*
  2178. * For TSO frames, the nbuf users increment done for
  2179. * the current segment has to be reverted, since the
  2180. * hw enqueue for this segment failed
  2181. */
  2182. if (msdu_info->frm_type == dp_tx_frm_tso &&
  2183. msdu_info->u.tso_info.curr_seg) {
  2184. /*
  2185. * unmap and free current,
  2186. * retransmit remaining segments
  2187. */
  2188. dp_tx_comp_free_buf(soc, tx_desc);
  2189. i++;
  2190. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2191. continue;
  2192. }
  2193. if (msdu_info->frm_type == dp_tx_frm_sg)
  2194. dp_tx_sg_unmap_buf(soc, nbuf, msdu_info);
  2195. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2196. goto done;
  2197. }
  2198. /*
  2199. * TODO
  2200. * if tso_info structure can be modified to have curr_seg
  2201. * as first element, following 2 blocks of code (for TSO and SG)
  2202. * can be combined into 1
  2203. */
  2204. /*
  2205. * For Multicast-Unicast converted packets,
  2206. * each converted frame (for a client) is represented as
  2207. * 1 segment
  2208. */
  2209. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  2210. (msdu_info->frm_type == dp_tx_frm_me)) {
  2211. if (msdu_info->u.sg_info.curr_seg->next) {
  2212. msdu_info->u.sg_info.curr_seg =
  2213. msdu_info->u.sg_info.curr_seg->next;
  2214. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2215. } else
  2216. break;
  2217. }
  2218. i++;
  2219. }
  2220. nbuf = NULL;
  2221. done:
  2222. return nbuf;
  2223. }
  2224. /**
  2225. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  2226. * for SG frames
  2227. * @vdev: DP vdev handle
  2228. * @nbuf: skb
  2229. * @seg_info: Pointer to Segment info Descriptor to be prepared
  2230. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2231. *
  2232. * Return: NULL on success,
  2233. * nbuf when it fails to send
  2234. */
  2235. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2236. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  2237. {
  2238. uint32_t cur_frag, nr_frags, i;
  2239. qdf_dma_addr_t paddr;
  2240. struct dp_tx_sg_info_s *sg_info;
  2241. sg_info = &msdu_info->u.sg_info;
  2242. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  2243. if (QDF_STATUS_SUCCESS !=
  2244. qdf_nbuf_map_nbytes_single(vdev->osdev, nbuf,
  2245. QDF_DMA_TO_DEVICE,
  2246. qdf_nbuf_headlen(nbuf))) {
  2247. dp_tx_err("dma map error");
  2248. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2249. qdf_nbuf_free(nbuf);
  2250. return NULL;
  2251. }
  2252. paddr = qdf_nbuf_mapped_paddr_get(nbuf);
  2253. seg_info->frags[0].paddr_lo = paddr;
  2254. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  2255. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  2256. seg_info->frags[0].vaddr = (void *) nbuf;
  2257. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  2258. if (QDF_STATUS_SUCCESS != qdf_nbuf_frag_map(vdev->osdev,
  2259. nbuf, 0,
  2260. QDF_DMA_TO_DEVICE,
  2261. cur_frag)) {
  2262. dp_tx_err("frag dma map error");
  2263. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2264. goto map_err;
  2265. }
  2266. paddr = qdf_nbuf_get_tx_frag_paddr(nbuf);
  2267. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  2268. seg_info->frags[cur_frag + 1].paddr_hi =
  2269. ((uint64_t) paddr) >> 32;
  2270. seg_info->frags[cur_frag + 1].len =
  2271. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  2272. }
  2273. seg_info->frag_cnt = (cur_frag + 1);
  2274. seg_info->total_len = qdf_nbuf_len(nbuf);
  2275. seg_info->next = NULL;
  2276. sg_info->curr_seg = seg_info;
  2277. msdu_info->frm_type = dp_tx_frm_sg;
  2278. msdu_info->num_seg = 1;
  2279. return nbuf;
  2280. map_err:
  2281. /* restore paddr into nbuf before calling unmap */
  2282. qdf_nbuf_mapped_paddr_set(nbuf,
  2283. (qdf_dma_addr_t)(seg_info->frags[0].paddr_lo |
  2284. ((uint64_t)
  2285. seg_info->frags[0].paddr_hi) << 32));
  2286. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  2287. QDF_DMA_TO_DEVICE,
  2288. seg_info->frags[0].len);
  2289. for (i = 1; i <= cur_frag; i++) {
  2290. qdf_mem_unmap_page(vdev->osdev, (qdf_dma_addr_t)
  2291. (seg_info->frags[i].paddr_lo | ((uint64_t)
  2292. seg_info->frags[i].paddr_hi) << 32),
  2293. seg_info->frags[i].len,
  2294. QDF_DMA_TO_DEVICE);
  2295. }
  2296. qdf_nbuf_free(nbuf);
  2297. return NULL;
  2298. }
  2299. /**
  2300. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  2301. * @vdev: DP vdev handle
  2302. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2303. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  2304. *
  2305. * Return: NULL on failure,
  2306. * nbuf when extracted successfully
  2307. */
  2308. static
  2309. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  2310. struct dp_tx_msdu_info_s *msdu_info,
  2311. uint16_t ppdu_cookie)
  2312. {
  2313. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2314. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2315. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2316. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  2317. (msdu_info->meta_data[5], 1);
  2318. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  2319. (msdu_info->meta_data[5], 1);
  2320. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  2321. (msdu_info->meta_data[6], ppdu_cookie);
  2322. msdu_info->exception_fw = 1;
  2323. msdu_info->is_tx_sniffer = 1;
  2324. }
  2325. #ifdef MESH_MODE_SUPPORT
  2326. /**
  2327. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  2328. and prepare msdu_info for mesh frames.
  2329. * @vdev: DP vdev handle
  2330. * @nbuf: skb
  2331. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2332. *
  2333. * Return: NULL on failure,
  2334. * nbuf when extracted successfully
  2335. */
  2336. static
  2337. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2338. struct dp_tx_msdu_info_s *msdu_info)
  2339. {
  2340. struct meta_hdr_s *mhdr;
  2341. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2342. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2343. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2344. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  2345. msdu_info->exception_fw = 0;
  2346. goto remove_meta_hdr;
  2347. }
  2348. msdu_info->exception_fw = 1;
  2349. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2350. meta_data->host_tx_desc_pool = 1;
  2351. meta_data->update_peer_cache = 1;
  2352. meta_data->learning_frame = 1;
  2353. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  2354. meta_data->power = mhdr->power;
  2355. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  2356. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  2357. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  2358. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  2359. meta_data->dyn_bw = 1;
  2360. meta_data->valid_pwr = 1;
  2361. meta_data->valid_mcs_mask = 1;
  2362. meta_data->valid_nss_mask = 1;
  2363. meta_data->valid_preamble_type = 1;
  2364. meta_data->valid_retries = 1;
  2365. meta_data->valid_bw_info = 1;
  2366. }
  2367. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  2368. meta_data->encrypt_type = 0;
  2369. meta_data->valid_encrypt_type = 1;
  2370. meta_data->learning_frame = 0;
  2371. }
  2372. meta_data->valid_key_flags = 1;
  2373. meta_data->key_flags = (mhdr->keyix & 0x3);
  2374. remove_meta_hdr:
  2375. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2376. dp_tx_err("qdf_nbuf_pull_head failed");
  2377. qdf_nbuf_free(nbuf);
  2378. return NULL;
  2379. }
  2380. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  2381. dp_tx_info("Meta hdr %0x %0x %0x %0x %0x %0x"
  2382. " tid %d to_fw %d",
  2383. msdu_info->meta_data[0],
  2384. msdu_info->meta_data[1],
  2385. msdu_info->meta_data[2],
  2386. msdu_info->meta_data[3],
  2387. msdu_info->meta_data[4],
  2388. msdu_info->meta_data[5],
  2389. msdu_info->tid, msdu_info->exception_fw);
  2390. return nbuf;
  2391. }
  2392. #else
  2393. static
  2394. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2395. struct dp_tx_msdu_info_s *msdu_info)
  2396. {
  2397. return nbuf;
  2398. }
  2399. #endif
  2400. /**
  2401. * dp_check_exc_metadata() - Checks if parameters are valid
  2402. * @tx_exc - holds all exception path parameters
  2403. *
  2404. * Returns true when all the parameters are valid else false
  2405. *
  2406. */
  2407. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  2408. {
  2409. bool invalid_tid = (tx_exc->tid >= DP_MAX_TIDS && tx_exc->tid !=
  2410. HTT_INVALID_TID);
  2411. bool invalid_encap_type =
  2412. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  2413. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  2414. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  2415. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  2416. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  2417. tx_exc->ppdu_cookie == 0);
  2418. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  2419. invalid_cookie) {
  2420. return false;
  2421. }
  2422. return true;
  2423. }
  2424. #ifdef ATH_SUPPORT_IQUE
  2425. /**
  2426. * dp_tx_mcast_enhance() - Multicast enhancement on TX
  2427. * @vdev: vdev handle
  2428. * @nbuf: skb
  2429. *
  2430. * Return: true on success,
  2431. * false on failure
  2432. */
  2433. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2434. {
  2435. qdf_ether_header_t *eh;
  2436. /* Mcast to Ucast Conversion*/
  2437. if (qdf_likely(!vdev->mcast_enhancement_en))
  2438. return true;
  2439. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2440. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2441. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2442. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  2443. qdf_nbuf_set_next(nbuf, NULL);
  2444. DP_STATS_INC_PKT(vdev, tx_i.mcast_en.mcast_pkt, 1,
  2445. qdf_nbuf_len(nbuf));
  2446. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  2447. QDF_STATUS_SUCCESS) {
  2448. return false;
  2449. }
  2450. if (qdf_unlikely(vdev->igmp_mcast_enhanc_en > 0)) {
  2451. if (dp_tx_prepare_send_igmp_me(vdev, nbuf) ==
  2452. QDF_STATUS_SUCCESS) {
  2453. return false;
  2454. }
  2455. }
  2456. }
  2457. return true;
  2458. }
  2459. #else
  2460. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2461. {
  2462. return true;
  2463. }
  2464. #endif
  2465. /**
  2466. * dp_tx_per_pkt_vdev_id_check() - vdev id check for frame
  2467. * @nbuf: qdf_nbuf_t
  2468. * @vdev: struct dp_vdev *
  2469. *
  2470. * Allow packet for processing only if it is for peer client which is
  2471. * connected with same vap. Drop packet if client is connected to
  2472. * different vap.
  2473. *
  2474. * Return: QDF_STATUS
  2475. */
  2476. static inline QDF_STATUS
  2477. dp_tx_per_pkt_vdev_id_check(qdf_nbuf_t nbuf, struct dp_vdev *vdev)
  2478. {
  2479. struct dp_ast_entry *dst_ast_entry = NULL;
  2480. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2481. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) ||
  2482. DP_FRAME_IS_BROADCAST((eh)->ether_dhost))
  2483. return QDF_STATUS_SUCCESS;
  2484. qdf_spin_lock_bh(&vdev->pdev->soc->ast_lock);
  2485. dst_ast_entry = dp_peer_ast_hash_find_by_vdevid(vdev->pdev->soc,
  2486. eh->ether_dhost,
  2487. vdev->vdev_id);
  2488. /* If there is no ast entry, return failure */
  2489. if (qdf_unlikely(!dst_ast_entry)) {
  2490. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2491. return QDF_STATUS_E_FAILURE;
  2492. }
  2493. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2494. return QDF_STATUS_SUCCESS;
  2495. }
  2496. /**
  2497. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  2498. * @soc: DP soc handle
  2499. * @vdev_id: id of DP vdev handle
  2500. * @nbuf: skb
  2501. * @tx_exc_metadata: Handle that holds exception path meta data
  2502. *
  2503. * Entry point for Core Tx layer (DP_TX) invoked from
  2504. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2505. *
  2506. * Return: NULL on success,
  2507. * nbuf when it fails to send
  2508. */
  2509. qdf_nbuf_t
  2510. dp_tx_send_exception(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2511. qdf_nbuf_t nbuf,
  2512. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2513. {
  2514. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2515. qdf_ether_header_t *eh = NULL;
  2516. struct dp_tx_msdu_info_s msdu_info;
  2517. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2518. DP_MOD_ID_TX_EXCEPTION);
  2519. if (qdf_unlikely(!vdev))
  2520. goto fail;
  2521. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2522. if (!tx_exc_metadata)
  2523. goto fail;
  2524. msdu_info.tid = tx_exc_metadata->tid;
  2525. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2526. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2527. QDF_MAC_ADDR_REF(nbuf->data));
  2528. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2529. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  2530. dp_tx_err("Invalid parameters in exception path");
  2531. goto fail;
  2532. }
  2533. /* Basic sanity checks for unsupported packets */
  2534. /* MESH mode */
  2535. if (qdf_unlikely(vdev->mesh_vdev)) {
  2536. dp_tx_err("Mesh mode is not supported in exception path");
  2537. goto fail;
  2538. }
  2539. /*
  2540. * Classify the frame and call corresponding
  2541. * "prepare" function which extracts the segment (TSO)
  2542. * and fragmentation information (for TSO , SG, ME, or Raw)
  2543. * into MSDU_INFO structure which is later used to fill
  2544. * SW and HW descriptors.
  2545. */
  2546. if (qdf_nbuf_is_tso(nbuf)) {
  2547. dp_verbose_debug("TSO frame %pK", vdev);
  2548. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2549. qdf_nbuf_len(nbuf));
  2550. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2551. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2552. qdf_nbuf_len(nbuf));
  2553. goto fail;
  2554. }
  2555. goto send_multiple;
  2556. }
  2557. /* SG */
  2558. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2559. struct dp_tx_seg_info_s seg_info = {0};
  2560. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2561. if (!nbuf)
  2562. goto fail;
  2563. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2564. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2565. qdf_nbuf_len(nbuf));
  2566. goto send_multiple;
  2567. }
  2568. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  2569. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  2570. qdf_nbuf_len(nbuf));
  2571. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  2572. tx_exc_metadata->ppdu_cookie);
  2573. }
  2574. /*
  2575. * Get HW Queue to use for this frame.
  2576. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2577. * dedicated for data and 1 for command.
  2578. * "queue_id" maps to one hardware ring.
  2579. * With each ring, we also associate a unique Tx descriptor pool
  2580. * to minimize lock contention for these resources.
  2581. */
  2582. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2583. /*
  2584. * Check exception descriptors
  2585. */
  2586. if (dp_tx_exception_limit_check(vdev))
  2587. goto fail;
  2588. /* Single linear frame */
  2589. /*
  2590. * If nbuf is a simple linear frame, use send_single function to
  2591. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2592. * SRNG. There is no need to setup a MSDU extension descriptor.
  2593. */
  2594. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2595. tx_exc_metadata->peer_id, tx_exc_metadata);
  2596. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2597. return nbuf;
  2598. send_multiple:
  2599. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2600. fail:
  2601. if (vdev)
  2602. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2603. dp_verbose_debug("pkt send failed");
  2604. return nbuf;
  2605. }
  2606. /**
  2607. * dp_tx_send_exception_vdev_id_check() - Transmit a frame on a given VAP
  2608. * in exception path in special case to avoid regular exception path chk.
  2609. * @soc: DP soc handle
  2610. * @vdev_id: id of DP vdev handle
  2611. * @nbuf: skb
  2612. * @tx_exc_metadata: Handle that holds exception path meta data
  2613. *
  2614. * Entry point for Core Tx layer (DP_TX) invoked from
  2615. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2616. *
  2617. * Return: NULL on success,
  2618. * nbuf when it fails to send
  2619. */
  2620. qdf_nbuf_t
  2621. dp_tx_send_exception_vdev_id_check(struct cdp_soc_t *soc_hdl,
  2622. uint8_t vdev_id, qdf_nbuf_t nbuf,
  2623. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2624. {
  2625. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2626. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2627. DP_MOD_ID_TX_EXCEPTION);
  2628. if (qdf_unlikely(!vdev))
  2629. goto fail;
  2630. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  2631. == QDF_STATUS_E_FAILURE)) {
  2632. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  2633. goto fail;
  2634. }
  2635. /* Unref count as it will agin be taken inside dp_tx_exception */
  2636. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2637. return dp_tx_send_exception(soc_hdl, vdev_id, nbuf, tx_exc_metadata);
  2638. fail:
  2639. if (vdev)
  2640. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2641. dp_verbose_debug("pkt send failed");
  2642. return nbuf;
  2643. }
  2644. /**
  2645. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  2646. * @soc: DP soc handle
  2647. * @vdev_id: DP vdev handle
  2648. * @nbuf: skb
  2649. *
  2650. * Entry point for Core Tx layer (DP_TX) invoked from
  2651. * hard_start_xmit in OSIF/HDD
  2652. *
  2653. * Return: NULL on success,
  2654. * nbuf when it fails to send
  2655. */
  2656. #ifdef MESH_MODE_SUPPORT
  2657. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2658. qdf_nbuf_t nbuf)
  2659. {
  2660. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2661. struct meta_hdr_s *mhdr;
  2662. qdf_nbuf_t nbuf_mesh = NULL;
  2663. qdf_nbuf_t nbuf_clone = NULL;
  2664. struct dp_vdev *vdev;
  2665. uint8_t no_enc_frame = 0;
  2666. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  2667. if (!nbuf_mesh) {
  2668. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2669. "qdf_nbuf_unshare failed");
  2670. return nbuf;
  2671. }
  2672. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_MESH);
  2673. if (!vdev) {
  2674. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2675. "vdev is NULL for vdev_id %d", vdev_id);
  2676. return nbuf;
  2677. }
  2678. nbuf = nbuf_mesh;
  2679. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2680. if ((vdev->sec_type != cdp_sec_type_none) &&
  2681. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  2682. no_enc_frame = 1;
  2683. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  2684. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  2685. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  2686. !no_enc_frame) {
  2687. nbuf_clone = qdf_nbuf_clone(nbuf);
  2688. if (!nbuf_clone) {
  2689. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2690. "qdf_nbuf_clone failed");
  2691. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2692. return nbuf;
  2693. }
  2694. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  2695. }
  2696. if (nbuf_clone) {
  2697. if (!dp_tx_send(soc_hdl, vdev_id, nbuf_clone)) {
  2698. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2699. } else {
  2700. qdf_nbuf_free(nbuf_clone);
  2701. }
  2702. }
  2703. if (no_enc_frame)
  2704. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  2705. else
  2706. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  2707. nbuf = dp_tx_send(soc_hdl, vdev_id, nbuf);
  2708. if ((!nbuf) && no_enc_frame) {
  2709. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2710. }
  2711. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2712. return nbuf;
  2713. }
  2714. #else
  2715. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc, uint8_t vdev_id,
  2716. qdf_nbuf_t nbuf)
  2717. {
  2718. return dp_tx_send(soc, vdev_id, nbuf);
  2719. }
  2720. #endif
  2721. /**
  2722. * dp_tx_nawds_handler() - NAWDS handler
  2723. *
  2724. * @soc: DP soc handle
  2725. * @vdev_id: id of DP vdev handle
  2726. * @msdu_info: msdu_info required to create HTT metadata
  2727. * @nbuf: skb
  2728. *
  2729. * This API transfers the multicast frames with the peer id
  2730. * on NAWDS enabled peer.
  2731. * Return: none
  2732. */
  2733. static inline
  2734. void dp_tx_nawds_handler(struct dp_soc *soc, struct dp_vdev *vdev,
  2735. struct dp_tx_msdu_info_s *msdu_info, qdf_nbuf_t nbuf)
  2736. {
  2737. struct dp_peer *peer = NULL;
  2738. qdf_nbuf_t nbuf_clone = NULL;
  2739. uint16_t peer_id = DP_INVALID_PEER;
  2740. uint16_t sa_peer_id = DP_INVALID_PEER;
  2741. struct dp_ast_entry *ast_entry = NULL;
  2742. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2743. struct dp_txrx_peer *txrx_peer;
  2744. if (!soc->ast_offload_support) {
  2745. if (qdf_nbuf_get_tx_ftype(nbuf) == CB_FTYPE_INTRABSS_FWD) {
  2746. qdf_spin_lock_bh(&soc->ast_lock);
  2747. ast_entry = dp_peer_ast_hash_find_by_pdevid
  2748. (soc,
  2749. (uint8_t *)(eh->ether_shost),
  2750. vdev->pdev->pdev_id);
  2751. if (ast_entry)
  2752. sa_peer_id = ast_entry->peer_id;
  2753. qdf_spin_unlock_bh(&soc->ast_lock);
  2754. }
  2755. } else {
  2756. if ((qdf_nbuf_get_tx_ftype(nbuf) == CB_FTYPE_INTRABSS_FWD) &&
  2757. qdf_nbuf_get_tx_fctx(nbuf))
  2758. sa_peer_id = *(uint32_t *)qdf_nbuf_get_tx_fctx(nbuf);
  2759. }
  2760. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2761. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2762. txrx_peer = dp_get_txrx_peer(peer);
  2763. if (!txrx_peer)
  2764. continue;
  2765. if (!txrx_peer->bss_peer && txrx_peer->nawds_enabled) {
  2766. peer_id = peer->peer_id;
  2767. /* Multicast packets needs to be
  2768. * dropped in case of intra bss forwarding
  2769. */
  2770. if (sa_peer_id == peer->peer_id) {
  2771. dp_tx_debug("multicast packet");
  2772. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  2773. tx.nawds_mcast_drop,
  2774. 1);
  2775. continue;
  2776. }
  2777. nbuf_clone = qdf_nbuf_clone(nbuf);
  2778. if (!nbuf_clone) {
  2779. QDF_TRACE(QDF_MODULE_ID_DP,
  2780. QDF_TRACE_LEVEL_ERROR,
  2781. FL("nbuf clone failed"));
  2782. break;
  2783. }
  2784. nbuf_clone = dp_tx_send_msdu_single(vdev, nbuf_clone,
  2785. msdu_info, peer_id,
  2786. NULL);
  2787. if (nbuf_clone) {
  2788. dp_tx_debug("pkt send failed");
  2789. qdf_nbuf_free(nbuf_clone);
  2790. } else {
  2791. if (peer_id != DP_INVALID_PEER) {
  2792. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  2793. tx.nawds_mcast,
  2794. 1, qdf_nbuf_len(nbuf));
  2795. }
  2796. }
  2797. }
  2798. }
  2799. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2800. }
  2801. #ifdef QCA_DP_TX_NBUF_AND_NBUF_DATA_PREFETCH
  2802. static inline
  2803. void dp_tx_prefetch_nbuf_data(qdf_nbuf_t nbuf)
  2804. {
  2805. if (nbuf) {
  2806. qdf_prefetch(&nbuf->len);
  2807. qdf_prefetch(&nbuf->data);
  2808. }
  2809. }
  2810. #else
  2811. static inline
  2812. void dp_tx_prefetch_nbuf_data(qdf_nbuf_t nbuf)
  2813. {
  2814. }
  2815. #endif
  2816. /**
  2817. * dp_tx_send() - Transmit a frame on a given VAP
  2818. * @soc: DP soc handle
  2819. * @vdev_id: id of DP vdev handle
  2820. * @nbuf: skb
  2821. *
  2822. * Entry point for Core Tx layer (DP_TX) invoked from
  2823. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  2824. * cases
  2825. *
  2826. * Return: NULL on success,
  2827. * nbuf when it fails to send
  2828. */
  2829. qdf_nbuf_t dp_tx_send(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2830. qdf_nbuf_t nbuf)
  2831. {
  2832. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2833. uint16_t peer_id = HTT_INVALID_PEER;
  2834. /*
  2835. * doing a memzero is causing additional function call overhead
  2836. * so doing static stack clearing
  2837. */
  2838. struct dp_tx_msdu_info_s msdu_info = {0};
  2839. struct dp_vdev *vdev = NULL;
  2840. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  2841. return nbuf;
  2842. /*
  2843. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  2844. * this in per packet path.
  2845. *
  2846. * As in this path vdev memory is already protected with netdev
  2847. * tx lock
  2848. */
  2849. vdev = soc->vdev_id_map[vdev_id];
  2850. if (qdf_unlikely(!vdev))
  2851. return nbuf;
  2852. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2853. QDF_MAC_ADDR_REF(nbuf->data));
  2854. /*
  2855. * Set Default Host TID value to invalid TID
  2856. * (TID override disabled)
  2857. */
  2858. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  2859. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2860. if (qdf_unlikely(vdev->mesh_vdev)) {
  2861. qdf_nbuf_t nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  2862. &msdu_info);
  2863. if (!nbuf_mesh) {
  2864. dp_verbose_debug("Extracting mesh metadata failed");
  2865. return nbuf;
  2866. }
  2867. nbuf = nbuf_mesh;
  2868. }
  2869. /*
  2870. * Get HW Queue to use for this frame.
  2871. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2872. * dedicated for data and 1 for command.
  2873. * "queue_id" maps to one hardware ring.
  2874. * With each ring, we also associate a unique Tx descriptor pool
  2875. * to minimize lock contention for these resources.
  2876. */
  2877. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2878. /*
  2879. * TCL H/W supports 2 DSCP-TID mapping tables.
  2880. * Table 1 - Default DSCP-TID mapping table
  2881. * Table 2 - 1 DSCP-TID override table
  2882. *
  2883. * If we need a different DSCP-TID mapping for this vap,
  2884. * call tid_classify to extract DSCP/ToS from frame and
  2885. * map to a TID and store in msdu_info. This is later used
  2886. * to fill in TCL Input descriptor (per-packet TID override).
  2887. */
  2888. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  2889. /*
  2890. * Classify the frame and call corresponding
  2891. * "prepare" function which extracts the segment (TSO)
  2892. * and fragmentation information (for TSO , SG, ME, or Raw)
  2893. * into MSDU_INFO structure which is later used to fill
  2894. * SW and HW descriptors.
  2895. */
  2896. if (qdf_nbuf_is_tso(nbuf)) {
  2897. dp_verbose_debug("TSO frame %pK", vdev);
  2898. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2899. qdf_nbuf_len(nbuf));
  2900. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2901. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2902. qdf_nbuf_len(nbuf));
  2903. return nbuf;
  2904. }
  2905. goto send_multiple;
  2906. }
  2907. /* SG */
  2908. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2909. if (qdf_nbuf_get_nr_frags(nbuf) > DP_TX_MAX_NUM_FRAGS - 1) {
  2910. if (qdf_unlikely(qdf_nbuf_linearize(nbuf)))
  2911. return nbuf;
  2912. } else {
  2913. struct dp_tx_seg_info_s seg_info = {0};
  2914. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info,
  2915. &msdu_info);
  2916. if (!nbuf)
  2917. return NULL;
  2918. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2919. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2920. qdf_nbuf_len(nbuf));
  2921. goto send_multiple;
  2922. }
  2923. }
  2924. if (qdf_unlikely(!dp_tx_mcast_enhance(vdev, nbuf)))
  2925. return NULL;
  2926. /* RAW */
  2927. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  2928. struct dp_tx_seg_info_s seg_info = {0};
  2929. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  2930. if (!nbuf)
  2931. return NULL;
  2932. dp_verbose_debug("Raw frame %pK", vdev);
  2933. goto send_multiple;
  2934. }
  2935. if (qdf_unlikely(vdev->nawds_enabled)) {
  2936. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  2937. qdf_nbuf_data(nbuf);
  2938. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost))
  2939. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf);
  2940. peer_id = DP_INVALID_PEER;
  2941. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2942. 1, qdf_nbuf_len(nbuf));
  2943. }
  2944. /* Single linear frame */
  2945. /*
  2946. * If nbuf is a simple linear frame, use send_single function to
  2947. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2948. * SRNG. There is no need to setup a MSDU extension descriptor.
  2949. */
  2950. dp_tx_prefetch_nbuf_data(nbuf);
  2951. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  2952. return nbuf;
  2953. send_multiple:
  2954. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2955. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  2956. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  2957. return nbuf;
  2958. }
  2959. /**
  2960. * dp_tx_send_vdev_id_check() - Transmit a frame on a given VAP in special
  2961. * case to vaoid check in perpkt path.
  2962. * @soc: DP soc handle
  2963. * @vdev_id: id of DP vdev handle
  2964. * @nbuf: skb
  2965. *
  2966. * Entry point for Core Tx layer (DP_TX) invoked from
  2967. * hard_start_xmit in OSIF/HDD to transmit packet through dp_tx_send
  2968. * with special condition to avoid per pkt check in dp_tx_send
  2969. *
  2970. * Return: NULL on success,
  2971. * nbuf when it fails to send
  2972. */
  2973. qdf_nbuf_t dp_tx_send_vdev_id_check(struct cdp_soc_t *soc_hdl,
  2974. uint8_t vdev_id, qdf_nbuf_t nbuf)
  2975. {
  2976. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2977. struct dp_vdev *vdev = NULL;
  2978. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  2979. return nbuf;
  2980. /*
  2981. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  2982. * this in per packet path.
  2983. *
  2984. * As in this path vdev memory is already protected with netdev
  2985. * tx lock
  2986. */
  2987. vdev = soc->vdev_id_map[vdev_id];
  2988. if (qdf_unlikely(!vdev))
  2989. return nbuf;
  2990. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  2991. == QDF_STATUS_E_FAILURE)) {
  2992. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  2993. return nbuf;
  2994. }
  2995. return dp_tx_send(soc_hdl, vdev_id, nbuf);
  2996. }
  2997. #ifdef UMAC_SUPPORT_PROXY_ARP
  2998. /**
  2999. * dp_tx_proxy_arp() - Tx proxy arp handler
  3000. * @vdev: datapath vdev handle
  3001. * @buf: sk buffer
  3002. *
  3003. * Return: status
  3004. */
  3005. static inline
  3006. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  3007. {
  3008. if (vdev->osif_proxy_arp)
  3009. return vdev->osif_proxy_arp(vdev->osif_vdev, nbuf);
  3010. /*
  3011. * when UMAC_SUPPORT_PROXY_ARP is defined, we expect
  3012. * osif_proxy_arp has a valid function pointer assigned
  3013. * to it
  3014. */
  3015. dp_tx_err("valid function pointer for osif_proxy_arp is expected!!\n");
  3016. return QDF_STATUS_NOT_INITIALIZED;
  3017. }
  3018. #else
  3019. /**
  3020. * dp_tx_proxy_arp() - Tx proxy arp handler
  3021. * @vdev: datapath vdev handle
  3022. * @buf: sk buffer
  3023. *
  3024. * This function always return 0 when UMAC_SUPPORT_PROXY_ARP
  3025. * is not defined.
  3026. *
  3027. * Return: status
  3028. */
  3029. static inline
  3030. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  3031. {
  3032. return QDF_STATUS_SUCCESS;
  3033. }
  3034. #endif
  3035. /**
  3036. * dp_tx_reinject_handler() - Tx Reinject Handler
  3037. * @soc: datapath soc handle
  3038. * @vdev: datapath vdev handle
  3039. * @tx_desc: software descriptor head pointer
  3040. * @status : Tx completion status from HTT descriptor
  3041. * @reinject_reason : reinject reason from HTT descriptor
  3042. *
  3043. * This function reinjects frames back to Target.
  3044. * Todo - Host queue needs to be added
  3045. *
  3046. * Return: none
  3047. */
  3048. void dp_tx_reinject_handler(struct dp_soc *soc,
  3049. struct dp_vdev *vdev,
  3050. struct dp_tx_desc_s *tx_desc,
  3051. uint8_t *status,
  3052. uint8_t reinject_reason)
  3053. {
  3054. struct dp_peer *peer = NULL;
  3055. uint32_t peer_id = HTT_INVALID_PEER;
  3056. qdf_nbuf_t nbuf = tx_desc->nbuf;
  3057. qdf_nbuf_t nbuf_copy = NULL;
  3058. struct dp_tx_msdu_info_s msdu_info;
  3059. #ifdef WDS_VENDOR_EXTENSION
  3060. int is_mcast = 0, is_ucast = 0;
  3061. int num_peers_3addr = 0;
  3062. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  3063. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  3064. #endif
  3065. struct dp_txrx_peer *txrx_peer;
  3066. qdf_assert(vdev);
  3067. dp_tx_debug("Tx reinject path");
  3068. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  3069. qdf_nbuf_len(tx_desc->nbuf));
  3070. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP)
  3071. #ifdef WLAN_MCAST_MLO
  3072. if (reinject_reason == HTT_TX_FW2WBM_REINJECT_REASON_MLO_MCAST) {
  3073. if (soc->arch_ops.dp_tx_mcast_handler)
  3074. soc->arch_ops.dp_tx_mcast_handler(soc, vdev, nbuf);
  3075. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3076. return;
  3077. }
  3078. #endif
  3079. #endif
  3080. #ifdef WDS_VENDOR_EXTENSION
  3081. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  3082. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  3083. } else {
  3084. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  3085. }
  3086. is_ucast = !is_mcast;
  3087. qdf_spin_lock_bh(&vdev->peer_list_lock);
  3088. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3089. txrx_peer = dp_get_txrx_peer(peer);
  3090. if (!txrx_peer || txrx_peer->bss_peer)
  3091. continue;
  3092. /* Detect wds peers that use 3-addr framing for mcast.
  3093. * if there are any, the bss_peer is used to send the
  3094. * the mcast frame using 3-addr format. all wds enabled
  3095. * peers that use 4-addr framing for mcast frames will
  3096. * be duplicated and sent as 4-addr frames below.
  3097. */
  3098. if (!txrx_peer->wds_enabled ||
  3099. !txrx_peer->wds_ecm.wds_tx_mcast_4addr) {
  3100. num_peers_3addr = 1;
  3101. break;
  3102. }
  3103. }
  3104. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  3105. #endif
  3106. if (qdf_unlikely(vdev->mesh_vdev)) {
  3107. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  3108. } else {
  3109. qdf_spin_lock_bh(&vdev->peer_list_lock);
  3110. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3111. txrx_peer = dp_get_txrx_peer(peer);
  3112. if (!txrx_peer)
  3113. continue;
  3114. if ((txrx_peer->peer_id != HTT_INVALID_PEER) &&
  3115. #ifdef WDS_VENDOR_EXTENSION
  3116. /*
  3117. * . if 3-addr STA, then send on BSS Peer
  3118. * . if Peer WDS enabled and accept 4-addr mcast,
  3119. * send mcast on that peer only
  3120. * . if Peer WDS enabled and accept 4-addr ucast,
  3121. * send ucast on that peer only
  3122. */
  3123. ((txrx_peer->bss_peer && num_peers_3addr && is_mcast) ||
  3124. (txrx_peer->wds_enabled &&
  3125. ((is_mcast && txrx_peer->wds_ecm.wds_tx_mcast_4addr) ||
  3126. (is_ucast &&
  3127. txrx_peer->wds_ecm.wds_tx_ucast_4addr))))) {
  3128. #else
  3129. (txrx_peer->bss_peer &&
  3130. (dp_tx_proxy_arp(vdev, nbuf) == QDF_STATUS_SUCCESS))) {
  3131. #endif
  3132. peer_id = DP_INVALID_PEER;
  3133. nbuf_copy = qdf_nbuf_copy(nbuf);
  3134. if (!nbuf_copy) {
  3135. dp_tx_debug("nbuf copy failed");
  3136. break;
  3137. }
  3138. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  3139. dp_tx_get_queue(vdev, nbuf,
  3140. &msdu_info.tx_queue);
  3141. nbuf_copy = dp_tx_send_msdu_single(vdev,
  3142. nbuf_copy,
  3143. &msdu_info,
  3144. peer_id,
  3145. NULL);
  3146. if (nbuf_copy) {
  3147. dp_tx_debug("pkt send failed");
  3148. qdf_nbuf_free(nbuf_copy);
  3149. }
  3150. }
  3151. }
  3152. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  3153. }
  3154. qdf_nbuf_free(nbuf);
  3155. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3156. }
  3157. /**
  3158. * dp_tx_inspect_handler() - Tx Inspect Handler
  3159. * @soc: datapath soc handle
  3160. * @vdev: datapath vdev handle
  3161. * @tx_desc: software descriptor head pointer
  3162. * @status : Tx completion status from HTT descriptor
  3163. *
  3164. * Handles Tx frames sent back to Host for inspection
  3165. * (ProxyARP)
  3166. *
  3167. * Return: none
  3168. */
  3169. void dp_tx_inspect_handler(struct dp_soc *soc,
  3170. struct dp_vdev *vdev,
  3171. struct dp_tx_desc_s *tx_desc,
  3172. uint8_t *status)
  3173. {
  3174. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3175. "%s Tx inspect path",
  3176. __func__);
  3177. DP_STATS_INC_PKT(vdev, tx_i.inspect_pkts, 1,
  3178. qdf_nbuf_len(tx_desc->nbuf));
  3179. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  3180. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3181. }
  3182. #ifdef MESH_MODE_SUPPORT
  3183. /**
  3184. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  3185. * in mesh meta header
  3186. * @tx_desc: software descriptor head pointer
  3187. * @ts: pointer to tx completion stats
  3188. * Return: none
  3189. */
  3190. static
  3191. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3192. struct hal_tx_completion_status *ts)
  3193. {
  3194. qdf_nbuf_t netbuf = tx_desc->nbuf;
  3195. if (!tx_desc->msdu_ext_desc) {
  3196. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  3197. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3198. "netbuf %pK offset %d",
  3199. netbuf, tx_desc->pkt_offset);
  3200. return;
  3201. }
  3202. }
  3203. }
  3204. #else
  3205. static
  3206. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3207. struct hal_tx_completion_status *ts)
  3208. {
  3209. }
  3210. #endif
  3211. #ifdef QCA_PEER_EXT_STATS
  3212. /*
  3213. * dp_tx_compute_tid_delay() - Compute per TID delay
  3214. * @stats: Per TID delay stats
  3215. * @tx_desc: Software Tx descriptor
  3216. *
  3217. * Compute the software enqueue and hw enqueue delays and
  3218. * update the respective histograms
  3219. *
  3220. * Return: void
  3221. */
  3222. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  3223. struct dp_tx_desc_s *tx_desc)
  3224. {
  3225. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  3226. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3227. uint32_t sw_enqueue_delay, fwhw_transmit_delay;
  3228. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3229. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3230. timestamp_hw_enqueue = tx_desc->timestamp;
  3231. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3232. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3233. timestamp_hw_enqueue);
  3234. /*
  3235. * Update the Tx software enqueue delay and HW enque-Completion delay.
  3236. */
  3237. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  3238. dp_hist_update_stats(&tx_delay->hwtx_delay, fwhw_transmit_delay);
  3239. }
  3240. /*
  3241. * dp_tx_update_peer_delay_stats() - Update the peer delay stats
  3242. * @txrx_peer: DP peer context
  3243. * @tx_desc: Tx software descriptor
  3244. * @tid: Transmission ID
  3245. * @ring_id: Rx CPU context ID/CPU_ID
  3246. *
  3247. * Update the peer extended stats. These are enhanced other
  3248. * delay stats per msdu level.
  3249. *
  3250. * Return: void
  3251. */
  3252. static void dp_tx_update_peer_delay_stats(struct dp_txrx_peer *txrx_peer,
  3253. struct dp_tx_desc_s *tx_desc,
  3254. uint8_t tid, uint8_t ring_id)
  3255. {
  3256. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  3257. struct dp_soc *soc = NULL;
  3258. struct dp_peer_delay_stats *delay_stats = NULL;
  3259. soc = pdev->soc;
  3260. if (qdf_likely(!wlan_cfg_is_peer_ext_stats_enabled(soc->wlan_cfg_ctx)))
  3261. return;
  3262. delay_stats = txrx_peer->delay_stats;
  3263. qdf_assert(delay_stats);
  3264. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  3265. /*
  3266. * For non-TID packets use the TID 9
  3267. */
  3268. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3269. tid = CDP_MAX_DATA_TIDS - 1;
  3270. dp_tx_compute_tid_delay(&delay_stats->delay_tid_stats[tid][ring_id],
  3271. tx_desc);
  3272. }
  3273. #else
  3274. static inline void dp_tx_update_peer_delay_stats(struct dp_txrx_peer *txrx_peer,
  3275. struct dp_tx_desc_s *tx_desc,
  3276. uint8_t tid, uint8_t ring_id)
  3277. {
  3278. }
  3279. #endif
  3280. /**
  3281. * dp_tx_compute_delay() - Compute and fill in all timestamps
  3282. * to pass in correct fields
  3283. *
  3284. * @vdev: pdev handle
  3285. * @tx_desc: tx descriptor
  3286. * @tid: tid value
  3287. * @ring_id: TCL or WBM ring number for transmit path
  3288. * Return: none
  3289. */
  3290. void dp_tx_compute_delay(struct dp_vdev *vdev, struct dp_tx_desc_s *tx_desc,
  3291. uint8_t tid, uint8_t ring_id)
  3292. {
  3293. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3294. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  3295. if (qdf_likely(!vdev->pdev->delay_stats_flag))
  3296. return;
  3297. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3298. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3299. timestamp_hw_enqueue = tx_desc->timestamp;
  3300. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3301. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3302. timestamp_hw_enqueue);
  3303. interframe_delay = (uint32_t)(timestamp_ingress -
  3304. vdev->prev_tx_enq_tstamp);
  3305. /*
  3306. * Delay in software enqueue
  3307. */
  3308. dp_update_delay_stats(vdev->pdev, sw_enqueue_delay, tid,
  3309. CDP_DELAY_STATS_SW_ENQ, ring_id);
  3310. /*
  3311. * Delay between packet enqueued to HW and Tx completion
  3312. */
  3313. dp_update_delay_stats(vdev->pdev, fwhw_transmit_delay, tid,
  3314. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id);
  3315. /*
  3316. * Update interframe delay stats calculated at hardstart receive point.
  3317. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  3318. * interframe delay will not be calculate correctly for 1st frame.
  3319. * On the other side, this will help in avoiding extra per packet check
  3320. * of !vdev->prev_tx_enq_tstamp.
  3321. */
  3322. dp_update_delay_stats(vdev->pdev, interframe_delay, tid,
  3323. CDP_DELAY_STATS_TX_INTERFRAME, ring_id);
  3324. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  3325. }
  3326. #ifdef DISABLE_DP_STATS
  3327. static
  3328. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf,
  3329. struct dp_txrx_peer *txrx_peer)
  3330. {
  3331. }
  3332. #else
  3333. static inline void
  3334. dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_txrx_peer *txrx_peer)
  3335. {
  3336. enum qdf_proto_subtype subtype = QDF_PROTO_INVALID;
  3337. DPTRACE(qdf_dp_track_noack_check(nbuf, &subtype));
  3338. if (subtype != QDF_PROTO_INVALID)
  3339. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.no_ack_count[subtype],
  3340. 1);
  3341. }
  3342. #endif
  3343. #ifndef QCA_ENHANCED_STATS_SUPPORT
  3344. /**
  3345. * dp_tx_update_peer_extd_stats()- Update Tx extended path stats for peer
  3346. *
  3347. * @ts: Tx compltion status
  3348. * @txrx_peer: datapath txrx_peer handle
  3349. *
  3350. * Return: void
  3351. */
  3352. static inline void
  3353. dp_tx_update_peer_extd_stats(struct hal_tx_completion_status *ts,
  3354. struct dp_txrx_peer *txrx_peer)
  3355. {
  3356. uint8_t mcs, pkt_type;
  3357. mcs = ts->mcs;
  3358. pkt_type = ts->pkt_type;
  3359. DP_PEER_EXTD_STATS_INCC(txrx_peer,
  3360. tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3361. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  3362. DP_PEER_EXTD_STATS_INCC(txrx_peer,
  3363. tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3364. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  3365. DP_PEER_EXTD_STATS_INCC(txrx_peer,
  3366. tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3367. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  3368. DP_PEER_EXTD_STATS_INCC(txrx_peer,
  3369. tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3370. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  3371. DP_PEER_EXTD_STATS_INCC(txrx_peer,
  3372. tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3373. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  3374. DP_PEER_EXTD_STATS_INCC(txrx_peer,
  3375. tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3376. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  3377. DP_PEER_EXTD_STATS_INCC(txrx_peer,
  3378. tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3379. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  3380. DP_PEER_EXTD_STATS_INCC(txrx_peer,
  3381. tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3382. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  3383. DP_PEER_EXTD_STATS_INCC(txrx_peer,
  3384. tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3385. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  3386. DP_PEER_EXTD_STATS_INCC(txrx_peer,
  3387. tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3388. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  3389. DP_PEER_EXTD_STATS_INC(txrx_peer, tx.sgi_count[ts->sgi], 1);
  3390. DP_PEER_EXTD_STATS_INC(txrx_peer, tx.bw[ts->bw], 1);
  3391. DP_PEER_EXTD_STATS_UPD(txrx_peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  3392. DP_PEER_EXTD_STATS_INC(txrx_peer,
  3393. tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  3394. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.stbc, 1, ts->stbc);
  3395. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.ldpc, 1, ts->ldpc);
  3396. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.retries, 1, ts->transmit_cnt > 1);
  3397. if (ts->first_msdu) {
  3398. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.retries_mpdu, 1,
  3399. ts->transmit_cnt > 1);
  3400. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.mpdu_success_with_retries,
  3401. qdf_do_div(ts->transmit_cnt, DP_RETRY_COUNT),
  3402. ts->transmit_cnt > DP_RETRY_COUNT);
  3403. }
  3404. }
  3405. #else
  3406. static inline void
  3407. dp_tx_update_peer_extd_stats(struct hal_tx_completion_status *ts,
  3408. struct dp_txrx_peer *txrx_peer)
  3409. {
  3410. }
  3411. #endif
  3412. /**
  3413. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  3414. * per wbm ring
  3415. *
  3416. * @tx_desc: software descriptor head pointer
  3417. * @ts: Tx completion status
  3418. * @peer: peer handle
  3419. * @ring_id: ring number
  3420. *
  3421. * Return: None
  3422. */
  3423. static inline void
  3424. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  3425. struct hal_tx_completion_status *ts,
  3426. struct dp_txrx_peer *txrx_peer, uint8_t ring_id)
  3427. {
  3428. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  3429. struct dp_soc *soc = NULL;
  3430. uint8_t tid = ts->tid;
  3431. uint32_t length;
  3432. struct cdp_tid_tx_stats *tid_stats;
  3433. if (!pdev)
  3434. return;
  3435. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3436. tid = CDP_MAX_DATA_TIDS - 1;
  3437. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3438. soc = pdev->soc;
  3439. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  3440. dp_err("Release source is not from TQM");
  3441. return;
  3442. }
  3443. length = qdf_nbuf_len(tx_desc->nbuf);
  3444. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  3445. if (qdf_unlikely(pdev->delay_stats_flag))
  3446. dp_tx_compute_delay(txrx_peer->vdev, tx_desc, tid, ring_id);
  3447. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.dropped.age_out, 1,
  3448. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  3449. DP_PEER_PER_PKT_STATS_INCC_PKT(txrx_peer, tx.dropped.fw_rem, 1, length,
  3450. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  3451. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.dropped.fw_rem_notx, 1,
  3452. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  3453. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.dropped.fw_rem_tx, 1,
  3454. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  3455. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.dropped.fw_reason1, 1,
  3456. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  3457. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.dropped.fw_reason2, 1,
  3458. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  3459. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.dropped.fw_reason3, 1,
  3460. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  3461. /*
  3462. * tx_failed is ideally supposed to be updated from HTT ppdu completion
  3463. * stats. But in IPQ807X/IPQ6018 chipsets owing to hw limitation there
  3464. * are no completions for failed cases. Hence updating tx_failed from
  3465. * data path. Please note that if tx_failed is fixed to be from ppdu,
  3466. * then this has to be removed
  3467. */
  3468. txrx_peer->tx_failed =
  3469. txrx_peer->stats.per_pkt_stats.tx.dropped.fw_rem.num +
  3470. txrx_peer->stats.per_pkt_stats.tx.dropped.fw_rem_notx +
  3471. txrx_peer->stats.per_pkt_stats.tx.dropped.fw_rem_tx +
  3472. txrx_peer->stats.per_pkt_stats.tx.dropped.age_out +
  3473. txrx_peer->stats.per_pkt_stats.tx.dropped.fw_reason1 +
  3474. txrx_peer->stats.per_pkt_stats.tx.dropped.fw_reason2 +
  3475. txrx_peer->stats.per_pkt_stats.tx.dropped.fw_reason3;
  3476. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  3477. tid_stats->tqm_status_cnt[ts->status]++;
  3478. }
  3479. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  3480. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.failed_retry_count, 1,
  3481. ts->transmit_cnt > DP_RETRY_COUNT);
  3482. dp_update_no_ack_stats(tx_desc->nbuf, txrx_peer);
  3483. return;
  3484. }
  3485. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.retry_count, 1,
  3486. ts->transmit_cnt > 1);
  3487. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.multiple_retry_count, 1,
  3488. ts->transmit_cnt > 2);
  3489. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.ofdma, 1, ts->ofdma);
  3490. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.amsdu_cnt, 1,
  3491. ts->msdu_part_of_amsdu);
  3492. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.non_amsdu_cnt, 1,
  3493. !ts->msdu_part_of_amsdu);
  3494. txrx_peer->stats.per_pkt_stats.tx.last_tx_ts = qdf_system_ticks();
  3495. dp_tx_update_peer_extd_stats(ts, txrx_peer);
  3496. }
  3497. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3498. /**
  3499. * dp_tx_flow_pool_lock() - take flow pool lock
  3500. * @soc: core txrx main context
  3501. * @tx_desc: tx desc
  3502. *
  3503. * Return: None
  3504. */
  3505. static inline
  3506. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  3507. struct dp_tx_desc_s *tx_desc)
  3508. {
  3509. struct dp_tx_desc_pool_s *pool;
  3510. uint8_t desc_pool_id;
  3511. desc_pool_id = tx_desc->pool_id;
  3512. pool = &soc->tx_desc[desc_pool_id];
  3513. qdf_spin_lock_bh(&pool->flow_pool_lock);
  3514. }
  3515. /**
  3516. * dp_tx_flow_pool_unlock() - release flow pool lock
  3517. * @soc: core txrx main context
  3518. * @tx_desc: tx desc
  3519. *
  3520. * Return: None
  3521. */
  3522. static inline
  3523. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  3524. struct dp_tx_desc_s *tx_desc)
  3525. {
  3526. struct dp_tx_desc_pool_s *pool;
  3527. uint8_t desc_pool_id;
  3528. desc_pool_id = tx_desc->pool_id;
  3529. pool = &soc->tx_desc[desc_pool_id];
  3530. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  3531. }
  3532. #else
  3533. static inline
  3534. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3535. {
  3536. }
  3537. static inline
  3538. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3539. {
  3540. }
  3541. #endif
  3542. /**
  3543. * dp_tx_notify_completion() - Notify tx completion for this desc
  3544. * @soc: core txrx main context
  3545. * @vdev: datapath vdev handle
  3546. * @tx_desc: tx desc
  3547. * @netbuf: buffer
  3548. * @status: tx status
  3549. *
  3550. * Return: none
  3551. */
  3552. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  3553. struct dp_vdev *vdev,
  3554. struct dp_tx_desc_s *tx_desc,
  3555. qdf_nbuf_t netbuf,
  3556. uint8_t status)
  3557. {
  3558. void *osif_dev;
  3559. ol_txrx_completion_fp tx_compl_cbk = NULL;
  3560. uint16_t flag = BIT(QDF_TX_RX_STATUS_DOWNLOAD_SUCC);
  3561. qdf_assert(tx_desc);
  3562. dp_tx_flow_pool_lock(soc, tx_desc);
  3563. if (!vdev ||
  3564. !vdev->osif_vdev) {
  3565. dp_tx_flow_pool_unlock(soc, tx_desc);
  3566. return;
  3567. }
  3568. osif_dev = vdev->osif_vdev;
  3569. tx_compl_cbk = vdev->tx_comp;
  3570. dp_tx_flow_pool_unlock(soc, tx_desc);
  3571. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3572. flag |= BIT(QDF_TX_RX_STATUS_OK);
  3573. if (tx_compl_cbk)
  3574. tx_compl_cbk(netbuf, osif_dev, flag);
  3575. }
  3576. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  3577. * @pdev: pdev handle
  3578. * @tid: tid value
  3579. * @txdesc_ts: timestamp from txdesc
  3580. * @ppdu_id: ppdu id
  3581. *
  3582. * Return: none
  3583. */
  3584. #ifdef FEATURE_PERPKT_INFO
  3585. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3586. struct dp_txrx_peer *txrx_peer,
  3587. uint8_t tid,
  3588. uint64_t txdesc_ts,
  3589. uint32_t ppdu_id)
  3590. {
  3591. uint64_t delta_ms;
  3592. struct cdp_tx_sojourn_stats *sojourn_stats;
  3593. struct dp_peer *primary_link_peer = NULL;
  3594. struct dp_soc *link_peer_soc = NULL;
  3595. if (qdf_unlikely(!pdev->enhanced_stats_en))
  3596. return;
  3597. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  3598. tid >= CDP_DATA_TID_MAX))
  3599. return;
  3600. if (qdf_unlikely(!pdev->sojourn_buf))
  3601. return;
  3602. primary_link_peer = dp_get_primary_link_peer_by_id(pdev->soc,
  3603. txrx_peer->peer_id,
  3604. DP_MOD_ID_TX_COMP);
  3605. if (qdf_unlikely(!primary_link_peer))
  3606. return;
  3607. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  3608. qdf_nbuf_data(pdev->sojourn_buf);
  3609. link_peer_soc = primary_link_peer->vdev->pdev->soc;
  3610. sojourn_stats->cookie = (void *)
  3611. dp_monitor_peer_get_rdkstats_ctx(link_peer_soc,
  3612. primary_link_peer);
  3613. delta_ms = qdf_ktime_to_ms(qdf_ktime_real_get()) -
  3614. txdesc_ts;
  3615. qdf_ewma_tx_lag_add(&txrx_peer->stats.per_pkt_stats.tx.avg_sojourn_msdu[tid],
  3616. delta_ms);
  3617. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  3618. sojourn_stats->num_msdus[tid] = 1;
  3619. sojourn_stats->avg_sojourn_msdu[tid].internal =
  3620. txrx_peer->stats.per_pkt_stats.tx.avg_sojourn_msdu[tid].internal;
  3621. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  3622. pdev->sojourn_buf, HTT_INVALID_PEER,
  3623. WDI_NO_VAL, pdev->pdev_id);
  3624. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  3625. sojourn_stats->num_msdus[tid] = 0;
  3626. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  3627. dp_peer_unref_delete(primary_link_peer, DP_MOD_ID_TX_COMP);
  3628. }
  3629. #else
  3630. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3631. struct dp_txrx_peer *txrx_peer,
  3632. uint8_t tid,
  3633. uint64_t txdesc_ts,
  3634. uint32_t ppdu_id)
  3635. {
  3636. }
  3637. #endif
  3638. #ifdef WLAN_FEATURE_PKT_CAPTURE_V2
  3639. /**
  3640. * dp_send_completion_to_pkt_capture() - send tx completion to packet capture
  3641. * @soc: dp_soc handle
  3642. * @desc: Tx Descriptor
  3643. * @ts: HAL Tx completion descriptor contents
  3644. *
  3645. * This function is used to send tx completion to packet capture
  3646. */
  3647. void dp_send_completion_to_pkt_capture(struct dp_soc *soc,
  3648. struct dp_tx_desc_s *desc,
  3649. struct hal_tx_completion_status *ts)
  3650. {
  3651. dp_wdi_event_handler(WDI_EVENT_PKT_CAPTURE_TX_DATA, soc,
  3652. desc, ts->peer_id,
  3653. WDI_NO_VAL, desc->pdev->pdev_id);
  3654. }
  3655. #endif
  3656. /**
  3657. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  3658. * @soc: DP Soc handle
  3659. * @tx_desc: software Tx descriptor
  3660. * @ts : Tx completion status from HAL/HTT descriptor
  3661. *
  3662. * Return: none
  3663. */
  3664. void
  3665. dp_tx_comp_process_desc(struct dp_soc *soc,
  3666. struct dp_tx_desc_s *desc,
  3667. struct hal_tx_completion_status *ts,
  3668. struct dp_txrx_peer *txrx_peer)
  3669. {
  3670. uint64_t time_latency = 0;
  3671. uint16_t peer_id = DP_INVALID_PEER_ID;
  3672. /*
  3673. * m_copy/tx_capture modes are not supported for
  3674. * scatter gather packets
  3675. */
  3676. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  3677. time_latency = (qdf_ktime_to_ms(qdf_ktime_real_get()) -
  3678. desc->timestamp);
  3679. }
  3680. dp_send_completion_to_pkt_capture(soc, desc, ts);
  3681. if (dp_tx_pkt_tracepoints_enabled())
  3682. qdf_trace_dp_packet(desc->nbuf, QDF_TX,
  3683. desc->msdu_ext_desc ?
  3684. desc->msdu_ext_desc->tso_desc : NULL,
  3685. desc->timestamp);
  3686. if (!(desc->msdu_ext_desc)) {
  3687. dp_tx_enh_unmap(soc, desc);
  3688. if (txrx_peer)
  3689. peer_id = txrx_peer->peer_id;
  3690. if (QDF_STATUS_SUCCESS ==
  3691. dp_monitor_tx_add_to_comp_queue(soc, desc, ts, peer_id)) {
  3692. return;
  3693. }
  3694. if (QDF_STATUS_SUCCESS ==
  3695. dp_get_completion_indication_for_stack(soc,
  3696. desc->pdev,
  3697. txrx_peer, ts,
  3698. desc->nbuf,
  3699. time_latency)) {
  3700. dp_send_completion_to_stack(soc,
  3701. desc->pdev,
  3702. ts->peer_id,
  3703. ts->ppdu_id,
  3704. desc->nbuf);
  3705. return;
  3706. }
  3707. }
  3708. desc->flags |= DP_TX_DESC_FLAG_COMPLETED_TX;
  3709. dp_tx_comp_free_buf(soc, desc);
  3710. }
  3711. #ifdef DISABLE_DP_STATS
  3712. /**
  3713. * dp_tx_update_connectivity_stats() - update tx connectivity stats
  3714. * @soc: core txrx main context
  3715. * @tx_desc: tx desc
  3716. * @status: tx status
  3717. *
  3718. * Return: none
  3719. */
  3720. static inline
  3721. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3722. struct dp_vdev *vdev,
  3723. struct dp_tx_desc_s *tx_desc,
  3724. uint8_t status)
  3725. {
  3726. }
  3727. #else
  3728. static inline
  3729. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3730. struct dp_vdev *vdev,
  3731. struct dp_tx_desc_s *tx_desc,
  3732. uint8_t status)
  3733. {
  3734. void *osif_dev;
  3735. ol_txrx_stats_rx_fp stats_cbk;
  3736. uint8_t pkt_type;
  3737. qdf_assert(tx_desc);
  3738. if (!vdev ||
  3739. !vdev->osif_vdev ||
  3740. !vdev->stats_cb)
  3741. return;
  3742. osif_dev = vdev->osif_vdev;
  3743. stats_cbk = vdev->stats_cb;
  3744. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_HOST_FW_SENT, &pkt_type);
  3745. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3746. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_ACK_CNT,
  3747. &pkt_type);
  3748. }
  3749. #endif
  3750. #ifdef WLAN_FEATURE_TSF_UPLINK_DELAY
  3751. void dp_set_delta_tsf(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3752. uint32_t delta_tsf)
  3753. {
  3754. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3755. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3756. DP_MOD_ID_CDP);
  3757. if (!vdev) {
  3758. dp_err_rl("vdev %d does not exist", vdev_id);
  3759. return;
  3760. }
  3761. vdev->delta_tsf = delta_tsf;
  3762. dp_debug("vdev id %u delta_tsf %u", vdev_id, delta_tsf);
  3763. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  3764. }
  3765. QDF_STATUS dp_set_tsf_ul_delay_report(struct cdp_soc_t *soc_hdl,
  3766. uint8_t vdev_id, bool enable)
  3767. {
  3768. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3769. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3770. DP_MOD_ID_CDP);
  3771. if (!vdev) {
  3772. dp_err_rl("vdev %d does not exist", vdev_id);
  3773. return QDF_STATUS_E_FAILURE;
  3774. }
  3775. qdf_atomic_set(&vdev->ul_delay_report, enable);
  3776. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  3777. return QDF_STATUS_SUCCESS;
  3778. }
  3779. QDF_STATUS dp_get_uplink_delay(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3780. uint32_t *val)
  3781. {
  3782. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3783. struct dp_vdev *vdev;
  3784. uint32_t delay_accum;
  3785. uint32_t pkts_accum;
  3786. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_CDP);
  3787. if (!vdev) {
  3788. dp_err_rl("vdev %d does not exist", vdev_id);
  3789. return QDF_STATUS_E_FAILURE;
  3790. }
  3791. if (!qdf_atomic_read(&vdev->ul_delay_report)) {
  3792. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  3793. return QDF_STATUS_E_FAILURE;
  3794. }
  3795. /* Average uplink delay based on current accumulated values */
  3796. delay_accum = qdf_atomic_read(&vdev->ul_delay_accum);
  3797. pkts_accum = qdf_atomic_read(&vdev->ul_pkts_accum);
  3798. *val = delay_accum / pkts_accum;
  3799. dp_debug("uplink_delay %u delay_accum %u pkts_accum %u", *val,
  3800. delay_accum, pkts_accum);
  3801. /* Reset accumulated values to 0 */
  3802. qdf_atomic_set(&vdev->ul_delay_accum, 0);
  3803. qdf_atomic_set(&vdev->ul_pkts_accum, 0);
  3804. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  3805. return QDF_STATUS_SUCCESS;
  3806. }
  3807. static void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  3808. struct hal_tx_completion_status *ts)
  3809. {
  3810. uint32_t buffer_ts;
  3811. uint32_t delta_tsf;
  3812. uint32_t ul_delay;
  3813. /* Tx_rate_stats_info_valid is 0 and tsf is invalid then */
  3814. if (!ts->valid)
  3815. return;
  3816. if (qdf_unlikely(!vdev)) {
  3817. dp_info_rl("vdev is null or delete in progrss");
  3818. return;
  3819. }
  3820. if (!qdf_atomic_read(&vdev->ul_delay_report))
  3821. return;
  3822. delta_tsf = vdev->delta_tsf;
  3823. /* buffer_timestamp is in units of 1024 us and is [31:13] of
  3824. * WBM_RELEASE_RING_4. After left shift 10 bits, it's
  3825. * valid up to 29 bits.
  3826. */
  3827. buffer_ts = ts->buffer_timestamp << 10;
  3828. ul_delay = ts->tsf - buffer_ts - delta_tsf;
  3829. ul_delay &= 0x1FFFFFFF; /* mask 29 BITS */
  3830. if (ul_delay > 0x1000000) {
  3831. dp_info_rl("----------------------\n"
  3832. "Tx completion status:\n"
  3833. "----------------------\n"
  3834. "release_src = %d\n"
  3835. "ppdu_id = 0x%x\n"
  3836. "release_reason = %d\n"
  3837. "tsf = %u (0x%x)\n"
  3838. "buffer_timestamp = %u (0x%x)\n"
  3839. "delta_tsf = %u (0x%x)\n",
  3840. ts->release_src, ts->ppdu_id, ts->status,
  3841. ts->tsf, ts->tsf, ts->buffer_timestamp,
  3842. ts->buffer_timestamp, delta_tsf, delta_tsf);
  3843. return;
  3844. }
  3845. ul_delay /= 1000; /* in unit of ms */
  3846. qdf_atomic_add(ul_delay, &vdev->ul_delay_accum);
  3847. qdf_atomic_inc(&vdev->ul_pkts_accum);
  3848. }
  3849. #else /* !WLAN_FEATURE_TSF_UPLINK_DELAY */
  3850. static inline
  3851. void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  3852. struct hal_tx_completion_status *ts)
  3853. {
  3854. }
  3855. #endif /* WLAN_FEATURE_TSF_UPLINK_DELAY */
  3856. /**
  3857. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  3858. * @soc: DP soc handle
  3859. * @tx_desc: software descriptor head pointer
  3860. * @ts: Tx completion status
  3861. * @txrx_peer: txrx peer handle
  3862. * @ring_id: ring number
  3863. *
  3864. * Return: none
  3865. */
  3866. void dp_tx_comp_process_tx_status(struct dp_soc *soc,
  3867. struct dp_tx_desc_s *tx_desc,
  3868. struct hal_tx_completion_status *ts,
  3869. struct dp_txrx_peer *txrx_peer,
  3870. uint8_t ring_id)
  3871. {
  3872. uint32_t length;
  3873. qdf_ether_header_t *eh;
  3874. struct dp_vdev *vdev = NULL;
  3875. qdf_nbuf_t nbuf = tx_desc->nbuf;
  3876. enum qdf_dp_tx_rx_status dp_status;
  3877. if (!nbuf) {
  3878. dp_info_rl("invalid tx descriptor. nbuf NULL");
  3879. goto out;
  3880. }
  3881. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  3882. length = qdf_nbuf_len(nbuf);
  3883. dp_status = dp_tx_hw_to_qdf(ts->status);
  3884. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  3885. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  3886. QDF_TRACE_DEFAULT_PDEV_ID,
  3887. qdf_nbuf_data_addr(nbuf),
  3888. sizeof(qdf_nbuf_data(nbuf)),
  3889. tx_desc->id, ts->status, dp_status));
  3890. dp_tx_comp_debug("-------------------- \n"
  3891. "Tx Completion Stats: \n"
  3892. "-------------------- \n"
  3893. "ack_frame_rssi = %d \n"
  3894. "first_msdu = %d \n"
  3895. "last_msdu = %d \n"
  3896. "msdu_part_of_amsdu = %d \n"
  3897. "rate_stats valid = %d \n"
  3898. "bw = %d \n"
  3899. "pkt_type = %d \n"
  3900. "stbc = %d \n"
  3901. "ldpc = %d \n"
  3902. "sgi = %d \n"
  3903. "mcs = %d \n"
  3904. "ofdma = %d \n"
  3905. "tones_in_ru = %d \n"
  3906. "tsf = %d \n"
  3907. "ppdu_id = %d \n"
  3908. "transmit_cnt = %d \n"
  3909. "tid = %d \n"
  3910. "peer_id = %d\n"
  3911. "tx_status = %d\n",
  3912. ts->ack_frame_rssi, ts->first_msdu,
  3913. ts->last_msdu, ts->msdu_part_of_amsdu,
  3914. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  3915. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  3916. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  3917. ts->transmit_cnt, ts->tid, ts->peer_id,
  3918. ts->status);
  3919. /* Update SoC level stats */
  3920. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  3921. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  3922. if (!txrx_peer) {
  3923. dp_info_rl("peer is null or deletion in progress");
  3924. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  3925. goto out;
  3926. }
  3927. vdev = txrx_peer->vdev;
  3928. dp_tx_update_connectivity_stats(soc, vdev, tx_desc, ts->status);
  3929. dp_tx_update_uplink_delay(soc, vdev, ts);
  3930. /* Update per-packet stats for mesh mode */
  3931. if (qdf_unlikely(vdev->mesh_vdev) &&
  3932. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  3933. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  3934. /* Update peer level stats */
  3935. if (qdf_unlikely(txrx_peer->bss_peer &&
  3936. vdev->opmode == wlan_op_mode_ap)) {
  3937. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  3938. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.mcast, 1,
  3939. length);
  3940. if (txrx_peer->vdev->tx_encap_type ==
  3941. htt_cmn_pkt_type_ethernet &&
  3942. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  3943. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  3944. tx.bcast, 1,
  3945. length);
  3946. }
  3947. }
  3948. } else {
  3949. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.ucast, 1, length);
  3950. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED) {
  3951. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.tx_success,
  3952. 1, length);
  3953. if (qdf_unlikely(txrx_peer->in_twt)) {
  3954. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  3955. tx.tx_success_twt,
  3956. 1, length);
  3957. }
  3958. }
  3959. }
  3960. dp_tx_update_peer_stats(tx_desc, ts, txrx_peer, ring_id);
  3961. dp_tx_update_peer_delay_stats(txrx_peer, tx_desc, ts->tid, ring_id);
  3962. #ifdef QCA_SUPPORT_RDK_STATS
  3963. if (soc->rdkstats_enabled)
  3964. dp_tx_sojourn_stats_process(vdev->pdev, txrx_peer, ts->tid,
  3965. tx_desc->timestamp,
  3966. ts->ppdu_id);
  3967. #endif
  3968. out:
  3969. return;
  3970. }
  3971. #if defined(QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT) && \
  3972. defined(QCA_ENHANCED_STATS_SUPPORT)
  3973. /*
  3974. * dp_tx_update_peer_basic_stats(): Update peer basic stats
  3975. * @txrx_peer: Datapath txrx_peer handle
  3976. * @length: Length of the packet
  3977. * @tx_status: Tx status from TQM/FW
  3978. * @update: enhanced flag value present in dp_pdev
  3979. *
  3980. * Return: none
  3981. */
  3982. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  3983. uint32_t length, uint8_t tx_status,
  3984. bool update)
  3985. {
  3986. if ((!txrx_peer->hw_txrx_stats_en) || update) {
  3987. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  3988. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  3989. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  3990. }
  3991. }
  3992. #elif defined(QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT)
  3993. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  3994. uint32_t length, uint8_t tx_status,
  3995. bool update)
  3996. {
  3997. if (!peer->hw_txrx_stats_en) {
  3998. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  3999. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4000. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4001. }
  4002. }
  4003. #else
  4004. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4005. uint32_t length, uint8_t tx_status,
  4006. bool update)
  4007. {
  4008. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4009. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4010. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4011. }
  4012. #endif
  4013. /*
  4014. * dp_tx_prefetch_next_nbuf_data(): Prefetch nbuf and nbuf data
  4015. * @nbuf: skb buffer
  4016. *
  4017. * Return: none
  4018. */
  4019. #ifdef QCA_DP_RX_NBUF_AND_NBUF_DATA_PREFETCH
  4020. static inline
  4021. void dp_tx_prefetch_next_nbuf_data(struct dp_tx_desc_s *next)
  4022. {
  4023. qdf_nbuf_t nbuf = NULL;
  4024. if (next)
  4025. nbuf = next->nbuf;
  4026. if (nbuf) {
  4027. /* prefetch skb->next and first few bytes of skb->cb */
  4028. qdf_prefetch(nbuf);
  4029. /* prefetch skb fields present in different cachelines */
  4030. qdf_prefetch(&nbuf->len);
  4031. qdf_prefetch(&nbuf->users);
  4032. }
  4033. }
  4034. #else
  4035. static inline
  4036. void dp_tx_prefetch_next_nbuf_data(struct dp_tx_desc_s *next)
  4037. {
  4038. }
  4039. #endif
  4040. /**
  4041. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  4042. * @soc: core txrx main context
  4043. * @comp_head: software descriptor head pointer
  4044. * @ring_id: ring number
  4045. *
  4046. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  4047. * and release the software descriptors after processing is complete
  4048. *
  4049. * Return: none
  4050. */
  4051. static void
  4052. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  4053. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  4054. {
  4055. struct dp_tx_desc_s *desc;
  4056. struct dp_tx_desc_s *next;
  4057. struct hal_tx_completion_status ts;
  4058. struct dp_txrx_peer *txrx_peer = NULL;
  4059. uint16_t peer_id = DP_INVALID_PEER;
  4060. qdf_nbuf_t netbuf;
  4061. dp_txrx_ref_handle txrx_ref_handle = NULL;
  4062. desc = comp_head;
  4063. while (desc) {
  4064. next = desc->next;
  4065. dp_tx_prefetch_next_nbuf_data(next);
  4066. if (peer_id != desc->peer_id) {
  4067. if (txrx_peer)
  4068. dp_txrx_peer_unref_delete(txrx_ref_handle,
  4069. DP_MOD_ID_TX_COMP);
  4070. peer_id = desc->peer_id;
  4071. txrx_peer =
  4072. dp_txrx_peer_get_ref_by_id(soc, peer_id,
  4073. &txrx_ref_handle,
  4074. DP_MOD_ID_TX_COMP);
  4075. }
  4076. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  4077. struct dp_pdev *pdev = desc->pdev;
  4078. if (qdf_likely(txrx_peer))
  4079. dp_tx_update_peer_basic_stats(txrx_peer,
  4080. desc->length,
  4081. desc->tx_status,
  4082. false);
  4083. qdf_assert(pdev);
  4084. dp_tx_outstanding_dec(pdev);
  4085. /*
  4086. * Calling a QDF WRAPPER here is creating signifcant
  4087. * performance impact so avoided the wrapper call here
  4088. */
  4089. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  4090. desc->id, DP_TX_COMP_UNMAP);
  4091. dp_tx_nbuf_unmap(soc, desc);
  4092. qdf_nbuf_free(desc->nbuf);
  4093. dp_tx_desc_free(soc, desc, desc->pool_id);
  4094. desc = next;
  4095. continue;
  4096. }
  4097. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  4098. dp_tx_comp_process_tx_status(soc, desc, &ts, txrx_peer,
  4099. ring_id);
  4100. netbuf = desc->nbuf;
  4101. /* check tx complete notification */
  4102. if (txrx_peer && qdf_nbuf_tx_notify_comp_get(netbuf))
  4103. dp_tx_notify_completion(soc, txrx_peer->vdev, desc,
  4104. netbuf, ts.status);
  4105. dp_tx_comp_process_desc(soc, desc, &ts, txrx_peer);
  4106. dp_tx_desc_release(desc, desc->pool_id);
  4107. desc = next;
  4108. }
  4109. if (txrx_peer)
  4110. dp_txrx_peer_unref_delete(txrx_ref_handle, DP_MOD_ID_TX_COMP);
  4111. }
  4112. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  4113. static inline
  4114. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  4115. int max_reap_limit)
  4116. {
  4117. bool limit_hit = false;
  4118. limit_hit =
  4119. (num_reaped >= max_reap_limit) ? true : false;
  4120. if (limit_hit)
  4121. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  4122. return limit_hit;
  4123. }
  4124. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  4125. {
  4126. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  4127. }
  4128. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  4129. {
  4130. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  4131. return cfg->tx_comp_loop_pkt_limit;
  4132. }
  4133. #else
  4134. static inline
  4135. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  4136. int max_reap_limit)
  4137. {
  4138. return false;
  4139. }
  4140. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  4141. {
  4142. return false;
  4143. }
  4144. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  4145. {
  4146. return 0;
  4147. }
  4148. #endif
  4149. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  4150. static inline int
  4151. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  4152. int *max_reap_limit)
  4153. {
  4154. return soc->arch_ops.dp_srng_test_and_update_nf_params(soc, dp_srng,
  4155. max_reap_limit);
  4156. }
  4157. #else
  4158. static inline int
  4159. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  4160. int *max_reap_limit)
  4161. {
  4162. return 0;
  4163. }
  4164. #endif
  4165. #ifdef DP_TX_TRACKING
  4166. void dp_tx_desc_check_corruption(struct dp_tx_desc_s *tx_desc)
  4167. {
  4168. if ((tx_desc->magic != DP_TX_MAGIC_PATTERN_INUSE) &&
  4169. (tx_desc->magic != DP_TX_MAGIC_PATTERN_FREE)) {
  4170. dp_err_rl("tx_desc %u is corrupted", tx_desc->id);
  4171. qdf_trigger_self_recovery(NULL, QDF_TX_DESC_LEAK);
  4172. }
  4173. }
  4174. #endif
  4175. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  4176. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  4177. uint32_t quota)
  4178. {
  4179. void *tx_comp_hal_desc;
  4180. void *last_prefetched_hw_desc = NULL;
  4181. struct dp_tx_desc_s *last_prefetched_sw_desc = NULL;
  4182. hal_soc_handle_t hal_soc;
  4183. uint8_t buffer_src;
  4184. struct dp_tx_desc_s *tx_desc = NULL;
  4185. struct dp_tx_desc_s *head_desc = NULL;
  4186. struct dp_tx_desc_s *tail_desc = NULL;
  4187. uint32_t num_processed = 0;
  4188. uint32_t count;
  4189. uint32_t num_avail_for_reap = 0;
  4190. bool force_break = false;
  4191. struct dp_srng *tx_comp_ring = &soc->tx_comp_ring[ring_id];
  4192. int max_reap_limit, ring_near_full;
  4193. DP_HIST_INIT();
  4194. more_data:
  4195. hal_soc = soc->hal_soc;
  4196. /* Re-initialize local variables to be re-used */
  4197. head_desc = NULL;
  4198. tail_desc = NULL;
  4199. count = 0;
  4200. max_reap_limit = dp_tx_comp_get_loop_pkt_limit(soc);
  4201. ring_near_full = dp_srng_test_and_update_nf_params(soc, tx_comp_ring,
  4202. &max_reap_limit);
  4203. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  4204. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  4205. return 0;
  4206. }
  4207. num_avail_for_reap = hal_srng_dst_num_valid(hal_soc, hal_ring_hdl, 0);
  4208. if (num_avail_for_reap >= quota)
  4209. num_avail_for_reap = quota;
  4210. dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap);
  4211. last_prefetched_hw_desc = dp_srng_dst_prefetch(hal_soc, hal_ring_hdl,
  4212. num_avail_for_reap);
  4213. /* Find head descriptor from completion ring */
  4214. while (qdf_likely(num_avail_for_reap--)) {
  4215. tx_comp_hal_desc = dp_srng_dst_get_next(soc, hal_ring_hdl);
  4216. if (qdf_unlikely(!tx_comp_hal_desc))
  4217. break;
  4218. buffer_src = hal_tx_comp_get_buffer_source(hal_soc,
  4219. tx_comp_hal_desc);
  4220. /* If this buffer was not released by TQM or FW, then it is not
  4221. * Tx completion indication, assert */
  4222. if (qdf_unlikely(buffer_src !=
  4223. HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  4224. (qdf_unlikely(buffer_src !=
  4225. HAL_TX_COMP_RELEASE_SOURCE_FW))) {
  4226. uint8_t wbm_internal_error;
  4227. dp_err_rl(
  4228. "Tx comp release_src != TQM | FW but from %d",
  4229. buffer_src);
  4230. hal_dump_comp_desc(tx_comp_hal_desc);
  4231. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  4232. /* When WBM sees NULL buffer_addr_info in any of
  4233. * ingress rings it sends an error indication,
  4234. * with wbm_internal_error=1, to a specific ring.
  4235. * The WBM2SW ring used to indicate these errors is
  4236. * fixed in HW, and that ring is being used as Tx
  4237. * completion ring. These errors are not related to
  4238. * Tx completions, and should just be ignored
  4239. */
  4240. wbm_internal_error = hal_get_wbm_internal_error(
  4241. hal_soc,
  4242. tx_comp_hal_desc);
  4243. if (wbm_internal_error) {
  4244. dp_err_rl("Tx comp wbm_internal_error!!");
  4245. DP_STATS_INC(soc, tx.wbm_internal_error[WBM_INT_ERROR_ALL], 1);
  4246. if (HAL_TX_COMP_RELEASE_SOURCE_REO ==
  4247. buffer_src)
  4248. dp_handle_wbm_internal_error(
  4249. soc,
  4250. tx_comp_hal_desc,
  4251. hal_tx_comp_get_buffer_type(
  4252. tx_comp_hal_desc));
  4253. } else {
  4254. dp_err_rl("Tx comp wbm_internal_error false");
  4255. DP_STATS_INC(soc, tx.non_wbm_internal_err, 1);
  4256. }
  4257. continue;
  4258. }
  4259. soc->arch_ops.tx_comp_get_params_from_hal_desc(soc,
  4260. tx_comp_hal_desc,
  4261. &tx_desc);
  4262. if (!tx_desc) {
  4263. dp_err("unable to retrieve tx_desc!");
  4264. QDF_BUG(0);
  4265. continue;
  4266. }
  4267. tx_desc->buffer_src = buffer_src;
  4268. /*
  4269. * If the release source is FW, process the HTT status
  4270. */
  4271. if (qdf_unlikely(buffer_src ==
  4272. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  4273. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  4274. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  4275. htt_tx_status);
  4276. /* Collect hw completion contents */
  4277. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  4278. &tx_desc->comp, 1);
  4279. soc->arch_ops.dp_tx_process_htt_completion(
  4280. soc,
  4281. tx_desc,
  4282. htt_tx_status,
  4283. ring_id);
  4284. } else {
  4285. tx_desc->tx_status =
  4286. hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  4287. tx_desc->buffer_src = buffer_src;
  4288. /*
  4289. * If the fast completion mode is enabled extended
  4290. * metadata from descriptor is not copied
  4291. */
  4292. if (qdf_likely(tx_desc->flags &
  4293. DP_TX_DESC_FLAG_SIMPLE))
  4294. goto add_to_pool;
  4295. /*
  4296. * If the descriptor is already freed in vdev_detach,
  4297. * continue to next descriptor
  4298. */
  4299. if (qdf_unlikely
  4300. ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) &&
  4301. !tx_desc->flags)) {
  4302. dp_tx_comp_info_rl("Descriptor freed in vdev_detach %d",
  4303. tx_desc->id);
  4304. DP_STATS_INC(soc, tx.tx_comp_exception, 1);
  4305. dp_tx_desc_check_corruption(tx_desc);
  4306. continue;
  4307. }
  4308. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  4309. dp_tx_comp_info_rl("pdev in down state %d",
  4310. tx_desc->id);
  4311. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  4312. dp_tx_comp_free_buf(soc, tx_desc);
  4313. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  4314. goto next_desc;
  4315. }
  4316. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  4317. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  4318. dp_tx_comp_alert("Txdesc invalid, flgs = %x,id = %d",
  4319. tx_desc->flags, tx_desc->id);
  4320. qdf_assert_always(0);
  4321. }
  4322. /* Collect hw completion contents */
  4323. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  4324. &tx_desc->comp, 1);
  4325. add_to_pool:
  4326. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  4327. /* First ring descriptor on the cycle */
  4328. if (!head_desc) {
  4329. head_desc = tx_desc;
  4330. tail_desc = tx_desc;
  4331. }
  4332. tail_desc->next = tx_desc;
  4333. tx_desc->next = NULL;
  4334. tail_desc = tx_desc;
  4335. }
  4336. next_desc:
  4337. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  4338. /*
  4339. * Processed packet count is more than given quota
  4340. * stop to processing
  4341. */
  4342. count++;
  4343. dp_tx_prefetch_hw_sw_nbuf_desc(soc, hal_soc,
  4344. num_avail_for_reap,
  4345. hal_ring_hdl,
  4346. &last_prefetched_hw_desc,
  4347. &last_prefetched_sw_desc);
  4348. if (dp_tx_comp_loop_pkt_limit_hit(soc, count, max_reap_limit))
  4349. break;
  4350. }
  4351. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  4352. /* Process the reaped descriptors */
  4353. if (head_desc)
  4354. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  4355. /*
  4356. * If we are processing in near-full condition, there are 3 scenario
  4357. * 1) Ring entries has reached critical state
  4358. * 2) Ring entries are still near high threshold
  4359. * 3) Ring entries are below the safe level
  4360. *
  4361. * One more loop will move te state to normal processing and yield
  4362. */
  4363. if (ring_near_full)
  4364. goto more_data;
  4365. if (dp_tx_comp_enable_eol_data_check(soc)) {
  4366. if (num_processed >= quota)
  4367. force_break = true;
  4368. if (!force_break &&
  4369. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  4370. hal_ring_hdl)) {
  4371. DP_STATS_INC(soc, tx.hp_oos2, 1);
  4372. if (!hif_exec_should_yield(soc->hif_handle,
  4373. int_ctx->dp_intr_id))
  4374. goto more_data;
  4375. }
  4376. }
  4377. DP_TX_HIST_STATS_PER_PDEV();
  4378. return num_processed;
  4379. }
  4380. #ifdef FEATURE_WLAN_TDLS
  4381. qdf_nbuf_t dp_tx_non_std(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4382. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  4383. {
  4384. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4385. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4386. DP_MOD_ID_TDLS);
  4387. if (!vdev) {
  4388. dp_err("vdev handle for id %d is NULL", vdev_id);
  4389. return NULL;
  4390. }
  4391. if (tx_spec & OL_TX_SPEC_NO_FREE)
  4392. vdev->is_tdls_frame = true;
  4393. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  4394. return dp_tx_send(soc_hdl, vdev_id, msdu_list);
  4395. }
  4396. #endif
  4397. /**
  4398. * dp_tx_vdev_attach() - attach vdev to dp tx
  4399. * @vdev: virtual device instance
  4400. *
  4401. * Return: QDF_STATUS_SUCCESS: success
  4402. * QDF_STATUS_E_RESOURCES: Error return
  4403. */
  4404. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  4405. {
  4406. int pdev_id;
  4407. /*
  4408. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  4409. */
  4410. DP_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  4411. DP_TCL_METADATA_TYPE_VDEV_BASED);
  4412. DP_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  4413. vdev->vdev_id);
  4414. pdev_id =
  4415. dp_get_target_pdev_id_for_host_pdev_id(vdev->pdev->soc,
  4416. vdev->pdev->pdev_id);
  4417. DP_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata, pdev_id);
  4418. /*
  4419. * Set HTT Extension Valid bit to 0 by default
  4420. */
  4421. DP_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  4422. dp_tx_vdev_update_search_flags(vdev);
  4423. return QDF_STATUS_SUCCESS;
  4424. }
  4425. #ifndef FEATURE_WDS
  4426. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  4427. {
  4428. return false;
  4429. }
  4430. #endif
  4431. /**
  4432. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  4433. * @vdev: virtual device instance
  4434. *
  4435. * Return: void
  4436. *
  4437. */
  4438. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  4439. {
  4440. struct dp_soc *soc = vdev->pdev->soc;
  4441. /*
  4442. * Enable both AddrY (SA based search) and AddrX (Da based search)
  4443. * for TDLS link
  4444. *
  4445. * Enable AddrY (SA based search) only for non-WDS STA and
  4446. * ProxySTA VAP (in HKv1) modes.
  4447. *
  4448. * In all other VAP modes, only DA based search should be
  4449. * enabled
  4450. */
  4451. if (vdev->opmode == wlan_op_mode_sta &&
  4452. vdev->tdls_link_connected)
  4453. vdev->hal_desc_addr_search_flags =
  4454. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  4455. else if ((vdev->opmode == wlan_op_mode_sta) &&
  4456. !dp_tx_da_search_override(vdev))
  4457. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  4458. else
  4459. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  4460. if (vdev->opmode == wlan_op_mode_sta)
  4461. vdev->search_type = soc->sta_mode_search_policy;
  4462. else
  4463. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  4464. }
  4465. static inline bool
  4466. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  4467. struct dp_vdev *vdev,
  4468. struct dp_tx_desc_s *tx_desc)
  4469. {
  4470. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  4471. return false;
  4472. /*
  4473. * if vdev is given, then only check whether desc
  4474. * vdev match. if vdev is NULL, then check whether
  4475. * desc pdev match.
  4476. */
  4477. return vdev ? (tx_desc->vdev_id == vdev->vdev_id) :
  4478. (tx_desc->pdev == pdev);
  4479. }
  4480. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4481. /**
  4482. * dp_tx_desc_flush() - release resources associated
  4483. * to TX Desc
  4484. *
  4485. * @dp_pdev: Handle to DP pdev structure
  4486. * @vdev: virtual device instance
  4487. * NULL: no specific Vdev is required and check all allcated TX desc
  4488. * on this pdev.
  4489. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  4490. *
  4491. * @force_free:
  4492. * true: flush the TX desc.
  4493. * false: only reset the Vdev in each allocated TX desc
  4494. * that associated to current Vdev.
  4495. *
  4496. * This function will go through the TX desc pool to flush
  4497. * the outstanding TX data or reset Vdev to NULL in associated TX
  4498. * Desc.
  4499. */
  4500. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  4501. bool force_free)
  4502. {
  4503. uint8_t i;
  4504. uint32_t j;
  4505. uint32_t num_desc, page_id, offset;
  4506. uint16_t num_desc_per_page;
  4507. struct dp_soc *soc = pdev->soc;
  4508. struct dp_tx_desc_s *tx_desc = NULL;
  4509. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  4510. if (!vdev && !force_free) {
  4511. dp_err("Reset TX desc vdev, Vdev param is required!");
  4512. return;
  4513. }
  4514. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  4515. tx_desc_pool = &soc->tx_desc[i];
  4516. if (!(tx_desc_pool->pool_size) ||
  4517. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  4518. !(tx_desc_pool->desc_pages.cacheable_pages))
  4519. continue;
  4520. /*
  4521. * Add flow pool lock protection in case pool is freed
  4522. * due to all tx_desc is recycled when handle TX completion.
  4523. * this is not necessary when do force flush as:
  4524. * a. double lock will happen if dp_tx_desc_release is
  4525. * also trying to acquire it.
  4526. * b. dp interrupt has been disabled before do force TX desc
  4527. * flush in dp_pdev_deinit().
  4528. */
  4529. if (!force_free)
  4530. qdf_spin_lock_bh(&tx_desc_pool->flow_pool_lock);
  4531. num_desc = tx_desc_pool->pool_size;
  4532. num_desc_per_page =
  4533. tx_desc_pool->desc_pages.num_element_per_page;
  4534. for (j = 0; j < num_desc; j++) {
  4535. page_id = j / num_desc_per_page;
  4536. offset = j % num_desc_per_page;
  4537. if (qdf_unlikely(!(tx_desc_pool->
  4538. desc_pages.cacheable_pages)))
  4539. break;
  4540. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  4541. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  4542. /*
  4543. * Free TX desc if force free is
  4544. * required, otherwise only reset vdev
  4545. * in this TX desc.
  4546. */
  4547. if (force_free) {
  4548. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  4549. dp_tx_comp_free_buf(soc, tx_desc);
  4550. dp_tx_desc_release(tx_desc, i);
  4551. } else {
  4552. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  4553. }
  4554. }
  4555. }
  4556. if (!force_free)
  4557. qdf_spin_unlock_bh(&tx_desc_pool->flow_pool_lock);
  4558. }
  4559. }
  4560. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  4561. /**
  4562. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  4563. *
  4564. * @soc: Handle to DP soc structure
  4565. * @tx_desc: pointer of one TX desc
  4566. * @desc_pool_id: TX Desc pool id
  4567. */
  4568. static inline void
  4569. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  4570. uint8_t desc_pool_id)
  4571. {
  4572. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  4573. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  4574. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  4575. }
  4576. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  4577. bool force_free)
  4578. {
  4579. uint8_t i, num_pool;
  4580. uint32_t j;
  4581. uint32_t num_desc, page_id, offset;
  4582. uint16_t num_desc_per_page;
  4583. struct dp_soc *soc = pdev->soc;
  4584. struct dp_tx_desc_s *tx_desc = NULL;
  4585. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  4586. if (!vdev && !force_free) {
  4587. dp_err("Reset TX desc vdev, Vdev param is required!");
  4588. return;
  4589. }
  4590. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4591. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4592. for (i = 0; i < num_pool; i++) {
  4593. tx_desc_pool = &soc->tx_desc[i];
  4594. if (!tx_desc_pool->desc_pages.cacheable_pages)
  4595. continue;
  4596. num_desc_per_page =
  4597. tx_desc_pool->desc_pages.num_element_per_page;
  4598. for (j = 0; j < num_desc; j++) {
  4599. page_id = j / num_desc_per_page;
  4600. offset = j % num_desc_per_page;
  4601. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  4602. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  4603. if (force_free) {
  4604. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  4605. dp_tx_comp_free_buf(soc, tx_desc);
  4606. dp_tx_desc_release(tx_desc, i);
  4607. } else {
  4608. dp_tx_desc_reset_vdev(soc, tx_desc,
  4609. i);
  4610. }
  4611. }
  4612. }
  4613. }
  4614. }
  4615. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  4616. /**
  4617. * dp_tx_vdev_detach() - detach vdev from dp tx
  4618. * @vdev: virtual device instance
  4619. *
  4620. * Return: QDF_STATUS_SUCCESS: success
  4621. * QDF_STATUS_E_RESOURCES: Error return
  4622. */
  4623. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  4624. {
  4625. struct dp_pdev *pdev = vdev->pdev;
  4626. /* Reset TX desc associated to this Vdev as NULL */
  4627. dp_tx_desc_flush(pdev, vdev, false);
  4628. return QDF_STATUS_SUCCESS;
  4629. }
  4630. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4631. /* Pools will be allocated dynamically */
  4632. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  4633. int num_desc)
  4634. {
  4635. uint8_t i;
  4636. for (i = 0; i < num_pool; i++) {
  4637. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  4638. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  4639. }
  4640. return QDF_STATUS_SUCCESS;
  4641. }
  4642. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  4643. int num_desc)
  4644. {
  4645. return QDF_STATUS_SUCCESS;
  4646. }
  4647. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  4648. {
  4649. }
  4650. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  4651. {
  4652. uint8_t i;
  4653. for (i = 0; i < num_pool; i++)
  4654. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  4655. }
  4656. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  4657. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  4658. int num_desc)
  4659. {
  4660. uint8_t i, count;
  4661. /* Allocate software Tx descriptor pools */
  4662. for (i = 0; i < num_pool; i++) {
  4663. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  4664. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4665. FL("Tx Desc Pool alloc %d failed %pK"),
  4666. i, soc);
  4667. goto fail;
  4668. }
  4669. }
  4670. return QDF_STATUS_SUCCESS;
  4671. fail:
  4672. for (count = 0; count < i; count++)
  4673. dp_tx_desc_pool_free(soc, count);
  4674. return QDF_STATUS_E_NOMEM;
  4675. }
  4676. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  4677. int num_desc)
  4678. {
  4679. uint8_t i;
  4680. for (i = 0; i < num_pool; i++) {
  4681. if (dp_tx_desc_pool_init(soc, i, num_desc)) {
  4682. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4683. FL("Tx Desc Pool init %d failed %pK"),
  4684. i, soc);
  4685. return QDF_STATUS_E_NOMEM;
  4686. }
  4687. }
  4688. return QDF_STATUS_SUCCESS;
  4689. }
  4690. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  4691. {
  4692. uint8_t i;
  4693. for (i = 0; i < num_pool; i++)
  4694. dp_tx_desc_pool_deinit(soc, i);
  4695. }
  4696. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  4697. {
  4698. uint8_t i;
  4699. for (i = 0; i < num_pool; i++)
  4700. dp_tx_desc_pool_free(soc, i);
  4701. }
  4702. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  4703. /**
  4704. * dp_tx_tso_cmn_desc_pool_deinit() - de-initialize TSO descriptors
  4705. * @soc: core txrx main context
  4706. * @num_pool: number of pools
  4707. *
  4708. */
  4709. void dp_tx_tso_cmn_desc_pool_deinit(struct dp_soc *soc, uint8_t num_pool)
  4710. {
  4711. dp_tx_tso_desc_pool_deinit(soc, num_pool);
  4712. dp_tx_tso_num_seg_pool_deinit(soc, num_pool);
  4713. }
  4714. /**
  4715. * dp_tx_tso_cmn_desc_pool_free() - free TSO descriptors
  4716. * @soc: core txrx main context
  4717. * @num_pool: number of pools
  4718. *
  4719. */
  4720. void dp_tx_tso_cmn_desc_pool_free(struct dp_soc *soc, uint8_t num_pool)
  4721. {
  4722. dp_tx_tso_desc_pool_free(soc, num_pool);
  4723. dp_tx_tso_num_seg_pool_free(soc, num_pool);
  4724. }
  4725. /**
  4726. * dp_soc_tx_desc_sw_pools_free() - free all TX descriptors
  4727. * @soc: core txrx main context
  4728. *
  4729. * This function frees all tx related descriptors as below
  4730. * 1. Regular TX descriptors (static pools)
  4731. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  4732. * 3. TSO descriptors
  4733. *
  4734. */
  4735. void dp_soc_tx_desc_sw_pools_free(struct dp_soc *soc)
  4736. {
  4737. uint8_t num_pool;
  4738. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4739. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  4740. dp_tx_ext_desc_pool_free(soc, num_pool);
  4741. dp_tx_delete_static_pools(soc, num_pool);
  4742. }
  4743. /**
  4744. * dp_soc_tx_desc_sw_pools_deinit() - de-initialize all TX descriptors
  4745. * @soc: core txrx main context
  4746. *
  4747. * This function de-initializes all tx related descriptors as below
  4748. * 1. Regular TX descriptors (static pools)
  4749. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  4750. * 3. TSO descriptors
  4751. *
  4752. */
  4753. void dp_soc_tx_desc_sw_pools_deinit(struct dp_soc *soc)
  4754. {
  4755. uint8_t num_pool;
  4756. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4757. dp_tx_flow_control_deinit(soc);
  4758. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  4759. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  4760. dp_tx_deinit_static_pools(soc, num_pool);
  4761. }
  4762. /**
  4763. * dp_tso_attach() - TSO attach handler
  4764. * @txrx_soc: Opaque Dp handle
  4765. *
  4766. * Reserve TSO descriptor buffers
  4767. *
  4768. * Return: QDF_STATUS_E_FAILURE on failure or
  4769. * QDF_STATUS_SUCCESS on success
  4770. */
  4771. QDF_STATUS dp_tx_tso_cmn_desc_pool_alloc(struct dp_soc *soc,
  4772. uint8_t num_pool,
  4773. uint16_t num_desc)
  4774. {
  4775. if (dp_tx_tso_desc_pool_alloc(soc, num_pool, num_desc)) {
  4776. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  4777. return QDF_STATUS_E_FAILURE;
  4778. }
  4779. if (dp_tx_tso_num_seg_pool_alloc(soc, num_pool, num_desc)) {
  4780. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  4781. num_pool, soc);
  4782. return QDF_STATUS_E_FAILURE;
  4783. }
  4784. return QDF_STATUS_SUCCESS;
  4785. }
  4786. /**
  4787. * dp_tx_tso_cmn_desc_pool_init() - TSO cmn desc pool init
  4788. * @soc: DP soc handle
  4789. * @num_pool: Number of pools
  4790. * @num_desc: Number of descriptors
  4791. *
  4792. * Initialize TSO descriptor pools
  4793. *
  4794. * Return: QDF_STATUS_E_FAILURE on failure or
  4795. * QDF_STATUS_SUCCESS on success
  4796. */
  4797. QDF_STATUS dp_tx_tso_cmn_desc_pool_init(struct dp_soc *soc,
  4798. uint8_t num_pool,
  4799. uint16_t num_desc)
  4800. {
  4801. if (dp_tx_tso_desc_pool_init(soc, num_pool, num_desc)) {
  4802. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  4803. return QDF_STATUS_E_FAILURE;
  4804. }
  4805. if (dp_tx_tso_num_seg_pool_init(soc, num_pool, num_desc)) {
  4806. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  4807. num_pool, soc);
  4808. return QDF_STATUS_E_FAILURE;
  4809. }
  4810. return QDF_STATUS_SUCCESS;
  4811. }
  4812. /**
  4813. * dp_soc_tx_desc_sw_pools_alloc() - Allocate tx descriptor pool memory
  4814. * @soc: core txrx main context
  4815. *
  4816. * This function allocates memory for following descriptor pools
  4817. * 1. regular sw tx descriptor pools (static pools)
  4818. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  4819. * 3. TSO descriptor pools
  4820. *
  4821. * Return: QDF_STATUS_SUCCESS: success
  4822. * QDF_STATUS_E_RESOURCES: Error return
  4823. */
  4824. QDF_STATUS dp_soc_tx_desc_sw_pools_alloc(struct dp_soc *soc)
  4825. {
  4826. uint8_t num_pool;
  4827. uint32_t num_desc;
  4828. uint32_t num_ext_desc;
  4829. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4830. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4831. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4832. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4833. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  4834. __func__, num_pool, num_desc);
  4835. if ((num_pool > MAX_TXDESC_POOLS) ||
  4836. (num_desc > WLAN_CFG_NUM_TX_DESC_MAX))
  4837. goto fail1;
  4838. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  4839. goto fail1;
  4840. if (dp_tx_ext_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4841. goto fail2;
  4842. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  4843. return QDF_STATUS_SUCCESS;
  4844. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4845. goto fail3;
  4846. return QDF_STATUS_SUCCESS;
  4847. fail3:
  4848. dp_tx_ext_desc_pool_free(soc, num_pool);
  4849. fail2:
  4850. dp_tx_delete_static_pools(soc, num_pool);
  4851. fail1:
  4852. return QDF_STATUS_E_RESOURCES;
  4853. }
  4854. /**
  4855. * dp_soc_tx_desc_sw_pools_init() - Initialise TX descriptor pools
  4856. * @soc: core txrx main context
  4857. *
  4858. * This function initializes the following TX descriptor pools
  4859. * 1. regular sw tx descriptor pools (static pools)
  4860. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  4861. * 3. TSO descriptor pools
  4862. *
  4863. * Return: QDF_STATUS_SUCCESS: success
  4864. * QDF_STATUS_E_RESOURCES: Error return
  4865. */
  4866. QDF_STATUS dp_soc_tx_desc_sw_pools_init(struct dp_soc *soc)
  4867. {
  4868. uint8_t num_pool;
  4869. uint32_t num_desc;
  4870. uint32_t num_ext_desc;
  4871. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4872. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4873. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4874. if (dp_tx_init_static_pools(soc, num_pool, num_desc))
  4875. goto fail1;
  4876. if (dp_tx_ext_desc_pool_init(soc, num_pool, num_ext_desc))
  4877. goto fail2;
  4878. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  4879. return QDF_STATUS_SUCCESS;
  4880. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  4881. goto fail3;
  4882. dp_tx_flow_control_init(soc);
  4883. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  4884. return QDF_STATUS_SUCCESS;
  4885. fail3:
  4886. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  4887. fail2:
  4888. dp_tx_deinit_static_pools(soc, num_pool);
  4889. fail1:
  4890. return QDF_STATUS_E_RESOURCES;
  4891. }
  4892. /**
  4893. * dp_tso_soc_attach() - Allocate and initialize TSO descriptors
  4894. * @txrx_soc: dp soc handle
  4895. *
  4896. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  4897. * QDF_STATUS_E_FAILURE
  4898. */
  4899. QDF_STATUS dp_tso_soc_attach(struct cdp_soc_t *txrx_soc)
  4900. {
  4901. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  4902. uint8_t num_pool;
  4903. uint32_t num_desc;
  4904. uint32_t num_ext_desc;
  4905. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4906. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4907. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4908. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4909. return QDF_STATUS_E_FAILURE;
  4910. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  4911. return QDF_STATUS_E_FAILURE;
  4912. return QDF_STATUS_SUCCESS;
  4913. }
  4914. /**
  4915. * dp_tso_soc_detach() - de-initialize and free the TSO descriptors
  4916. * @txrx_soc: dp soc handle
  4917. *
  4918. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  4919. */
  4920. QDF_STATUS dp_tso_soc_detach(struct cdp_soc_t *txrx_soc)
  4921. {
  4922. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  4923. uint8_t num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4924. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  4925. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  4926. return QDF_STATUS_SUCCESS;
  4927. }