sde_plane.c 130 KB

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  1. /*
  2. * Copyright (C) 2014-2020 The Linux Foundation. All rights reserved.
  3. * Copyright (C) 2013 Red Hat
  4. * Author: Rob Clark <[email protected]>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  19. #include <linux/debugfs.h>
  20. #include <linux/dma-buf.h>
  21. #include <drm/sde_drm.h>
  22. #include <drm/msm_drm_pp.h>
  23. #include "msm_prop.h"
  24. #include "msm_drv.h"
  25. #include "sde_kms.h"
  26. #include "sde_fence.h"
  27. #include "sde_formats.h"
  28. #include "sde_hw_sspp.h"
  29. #include "sde_hw_catalog_format.h"
  30. #include "sde_trace.h"
  31. #include "sde_crtc.h"
  32. #include "sde_vbif.h"
  33. #include "sde_plane.h"
  34. #include "sde_color_processing.h"
  35. #define SDE_DEBUG_PLANE(pl, fmt, ...) SDE_DEBUG("plane%d " fmt,\
  36. (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
  37. #define SDE_ERROR_PLANE(pl, fmt, ...) SDE_ERROR("plane%d " fmt,\
  38. (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
  39. #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci))
  40. #define PHASE_STEP_SHIFT 21
  41. #define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT))
  42. #define PHASE_RESIDUAL 15
  43. #define SHARP_STRENGTH_DEFAULT 32
  44. #define SHARP_EDGE_THR_DEFAULT 112
  45. #define SHARP_SMOOTH_THR_DEFAULT 8
  46. #define SHARP_NOISE_THR_DEFAULT 2
  47. #define SDE_NAME_SIZE 12
  48. #define SDE_PLANE_COLOR_FILL_FLAG BIT(31)
  49. #define TIME_MULTIPLEX_RECT(r0, r1, buffer_lines) \
  50. ((r0).y >= ((r1).y + (r1).h + buffer_lines))
  51. /* multirect rect index */
  52. enum {
  53. R0,
  54. R1,
  55. R_MAX
  56. };
  57. #define SDE_QSEED_DEFAULT_DYN_EXP 0x0
  58. #define DEFAULT_REFRESH_RATE 60
  59. /**
  60. * enum sde_plane_qos - Different qos configurations for each pipe
  61. *
  62. * @SDE_PLANE_QOS_VBLANK_CTRL: Setup VBLANK qos for the pipe.
  63. * @SDE_PLANE_QOS_VBLANK_AMORTIZE: Enables Amortization within pipe.
  64. * this configuration is mutually exclusive from VBLANK_CTRL.
  65. * @SDE_PLANE_QOS_PANIC_CTRL: Setup panic for the pipe.
  66. */
  67. enum sde_plane_qos {
  68. SDE_PLANE_QOS_VBLANK_CTRL = BIT(0),
  69. SDE_PLANE_QOS_VBLANK_AMORTIZE = BIT(1),
  70. SDE_PLANE_QOS_PANIC_CTRL = BIT(2),
  71. };
  72. /*
  73. * struct sde_plane - local sde plane structure
  74. * @aspace: address space pointer
  75. * @csc_cfg: Decoded user configuration for csc
  76. * @csc_usr_ptr: Points to csc_cfg if valid user config available
  77. * @csc_ptr: Points to sde_csc_cfg structure to use for current
  78. * @mplane_list: List of multirect planes of the same pipe
  79. * @catalog: Points to sde catalog structure
  80. * @revalidate: force revalidation of all the plane properties
  81. * @xin_halt_forced_clk: whether or not clocks were forced on for xin halt
  82. * @blob_rot_caps: Pointer to rotator capability blob
  83. */
  84. struct sde_plane {
  85. struct drm_plane base;
  86. struct mutex lock;
  87. enum sde_sspp pipe;
  88. uint32_t features; /* capabilities from catalog */
  89. uint32_t perf_features; /* perf capabilities from catalog */
  90. uint32_t nformats;
  91. uint32_t formats[64];
  92. struct sde_hw_pipe *pipe_hw;
  93. struct sde_hw_pipe_cfg pipe_cfg;
  94. struct sde_hw_sharp_cfg sharp_cfg;
  95. struct sde_hw_pipe_qos_cfg pipe_qos_cfg;
  96. uint32_t color_fill;
  97. bool is_error;
  98. bool is_rt_pipe;
  99. bool is_virtual;
  100. struct list_head mplane_list;
  101. struct sde_mdss_cfg *catalog;
  102. bool revalidate;
  103. bool xin_halt_forced_clk;
  104. struct sde_csc_cfg csc_cfg;
  105. struct sde_csc_cfg *csc_usr_ptr;
  106. struct sde_csc_cfg *csc_ptr;
  107. const struct sde_sspp_sub_blks *pipe_sblk;
  108. char pipe_name[SDE_NAME_SIZE];
  109. struct msm_property_info property_info;
  110. struct msm_property_data property_data[PLANE_PROP_COUNT];
  111. struct drm_property_blob *blob_info;
  112. struct drm_property_blob *blob_rot_caps;
  113. /* debugfs related stuff */
  114. struct dentry *debugfs_root;
  115. bool debugfs_default_scale;
  116. };
  117. #define to_sde_plane(x) container_of(x, struct sde_plane, base)
  118. static int plane_prop_array[PLANE_PROP_COUNT] = {SDE_PLANE_DIRTY_ALL};
  119. static struct sde_kms *_sde_plane_get_kms(struct drm_plane *plane)
  120. {
  121. struct msm_drm_private *priv;
  122. if (!plane || !plane->dev)
  123. return NULL;
  124. priv = plane->dev->dev_private;
  125. if (!priv)
  126. return NULL;
  127. return to_sde_kms(priv->kms);
  128. }
  129. static struct sde_hw_ctl *_sde_plane_get_hw_ctl(const struct drm_plane *plane)
  130. {
  131. struct drm_plane_state *pstate = NULL;
  132. struct drm_crtc *drm_crtc = NULL;
  133. struct sde_crtc *sde_crtc = NULL;
  134. struct sde_crtc_mixer *mixer = NULL;
  135. struct sde_hw_ctl *ctl = NULL;
  136. if (!plane) {
  137. DRM_ERROR("Invalid plane %pK\n", plane);
  138. return NULL;
  139. }
  140. pstate = plane->state;
  141. if (!pstate) {
  142. DRM_ERROR("Invalid plane state %pK\n", pstate);
  143. return NULL;
  144. }
  145. drm_crtc = pstate->crtc;
  146. if (!drm_crtc) {
  147. DRM_ERROR("Invalid drm_crtc %pK\n", drm_crtc);
  148. return NULL;
  149. }
  150. sde_crtc = to_sde_crtc(drm_crtc);
  151. if (!sde_crtc) {
  152. DRM_ERROR("invalid sde_crtc %pK\n", sde_crtc);
  153. return NULL;
  154. }
  155. /* it will always return the first mixer and single CTL */
  156. mixer = sde_crtc->mixers;
  157. if (!mixer) {
  158. DRM_ERROR("invalid mixer %pK\n", mixer);
  159. return NULL;
  160. }
  161. ctl = mixer->hw_ctl;
  162. if (!mixer) {
  163. DRM_ERROR("invalid ctl %pK\n", ctl);
  164. return NULL;
  165. }
  166. return ctl;
  167. }
  168. static bool sde_plane_enabled(const struct drm_plane_state *state)
  169. {
  170. return state && state->fb && state->crtc;
  171. }
  172. bool sde_plane_is_sec_ui_allowed(struct drm_plane *plane)
  173. {
  174. struct sde_plane *psde;
  175. if (!plane)
  176. return false;
  177. psde = to_sde_plane(plane);
  178. return !(psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI));
  179. }
  180. void sde_plane_setup_src_split_order(struct drm_plane *plane,
  181. enum sde_sspp_multirect_index rect_mode, bool enable)
  182. {
  183. struct sde_plane *psde;
  184. if (!plane)
  185. return;
  186. psde = to_sde_plane(plane);
  187. if (psde->pipe_hw->ops.set_src_split_order)
  188. psde->pipe_hw->ops.set_src_split_order(psde->pipe_hw,
  189. rect_mode, enable);
  190. }
  191. void sde_plane_set_sid(struct drm_plane *plane, u32 vm)
  192. {
  193. struct sde_plane *psde;
  194. struct sde_kms *sde_kms;
  195. struct msm_drm_private *priv;
  196. if (!plane || !plane->dev) {
  197. SDE_ERROR("invalid plane %d\n");
  198. return;
  199. }
  200. priv = plane->dev->dev_private;
  201. if (!priv || !priv->kms) {
  202. SDE_ERROR("invalid KMS reference\n");
  203. return;
  204. }
  205. sde_kms = to_sde_kms(priv->kms);
  206. psde = to_sde_plane(plane);
  207. sde_hw_set_sspp_sid(sde_kms->hw_sid, psde->pipe, vm);
  208. }
  209. /**
  210. * _sde_plane_set_qos_lut - set danger, safe and creq LUT of the given plane
  211. * @plane: Pointer to drm plane
  212. * @crtc: Pointer to drm crtc to find refresh rate on mode
  213. * @fb: Pointer to framebuffer associated with the given plane
  214. */
  215. static void _sde_plane_set_qos_lut(struct drm_plane *plane,
  216. struct drm_crtc *crtc,
  217. struct drm_framebuffer *fb)
  218. {
  219. struct sde_plane *psde;
  220. const struct sde_format *fmt = NULL;
  221. u32 frame_rate, qos_count, fps_index = 0, lut_index, index;
  222. struct sde_perf_cfg *perf;
  223. struct sde_plane_state *pstate;
  224. if (!plane || !fb) {
  225. SDE_ERROR("invalid arguments\n");
  226. return;
  227. }
  228. psde = to_sde_plane(plane);
  229. pstate = to_sde_plane_state(plane->state);
  230. if (!psde->pipe_hw || !psde->pipe_sblk || !psde->catalog) {
  231. SDE_ERROR("invalid arguments\n");
  232. return;
  233. } else if (!psde->pipe_hw->ops.setup_qos_lut) {
  234. return;
  235. }
  236. frame_rate = crtc->mode.vrefresh;
  237. perf = &psde->catalog->perf;
  238. qos_count = perf->qos_refresh_count;
  239. while (qos_count && perf->qos_refresh_rate) {
  240. if (frame_rate >= perf->qos_refresh_rate[qos_count - 1]) {
  241. fps_index = qos_count - 1;
  242. break;
  243. }
  244. qos_count--;
  245. }
  246. if (!psde->is_rt_pipe) {
  247. lut_index = SDE_QOS_LUT_USAGE_NRT;
  248. } else {
  249. fmt = sde_get_sde_format_ext(
  250. fb->format->format,
  251. fb->modifier);
  252. if (fmt && SDE_FORMAT_IS_LINEAR(fmt) &&
  253. pstate->scaler3_cfg.enable)
  254. lut_index = SDE_QOS_LUT_USAGE_LINEAR_QSEED;
  255. else if (fmt && SDE_FORMAT_IS_LINEAR(fmt))
  256. lut_index = SDE_QOS_LUT_USAGE_LINEAR;
  257. else if (pstate->scaler3_cfg.enable)
  258. lut_index = SDE_QOS_LUT_USAGE_MACROTILE_QSEED;
  259. else
  260. lut_index = SDE_QOS_LUT_USAGE_MACROTILE;
  261. }
  262. index = (fps_index * SDE_QOS_LUT_USAGE_MAX) + lut_index;
  263. psde->pipe_qos_cfg.danger_lut = perf->danger_lut[index];
  264. psde->pipe_qos_cfg.safe_lut = perf->safe_lut[index];
  265. psde->pipe_qos_cfg.creq_lut = perf->creq_lut[index];
  266. trace_sde_perf_set_qos_luts(psde->pipe - SSPP_VIG0,
  267. (fmt) ? fmt->base.pixel_format : 0,
  268. (fmt) ? fmt->fetch_mode : 0,
  269. psde->pipe_qos_cfg.danger_lut,
  270. psde->pipe_qos_cfg.safe_lut,
  271. psde->pipe_qos_cfg.creq_lut);
  272. SDE_DEBUG(
  273. "plane%u: pnum:%d fmt:%4.4s fps:%d mode:%d luts[0x%x,0x%x 0x%llx]\n",
  274. plane->base.id,
  275. psde->pipe - SSPP_VIG0,
  276. fmt ? (char *)&fmt->base.pixel_format : NULL, frame_rate,
  277. fmt ? fmt->fetch_mode : -1,
  278. psde->pipe_qos_cfg.danger_lut,
  279. psde->pipe_qos_cfg.safe_lut,
  280. psde->pipe_qos_cfg.creq_lut);
  281. psde->pipe_hw->ops.setup_qos_lut(psde->pipe_hw, &psde->pipe_qos_cfg);
  282. }
  283. /**
  284. * _sde_plane_set_qos_ctrl - set QoS control of the given plane
  285. * @plane: Pointer to drm plane
  286. * @enable: true to enable QoS control
  287. * @flags: QoS control mode (enum sde_plane_qos)
  288. */
  289. static void _sde_plane_set_qos_ctrl(struct drm_plane *plane,
  290. bool enable, u32 flags)
  291. {
  292. struct sde_plane *psde;
  293. if (!plane) {
  294. SDE_ERROR("invalid arguments\n");
  295. return;
  296. }
  297. psde = to_sde_plane(plane);
  298. if (!psde->pipe_hw || !psde->pipe_sblk) {
  299. SDE_ERROR("invalid arguments\n");
  300. return;
  301. } else if (!psde->pipe_hw->ops.setup_qos_ctrl) {
  302. return;
  303. }
  304. if (flags & SDE_PLANE_QOS_VBLANK_CTRL) {
  305. psde->pipe_qos_cfg.creq_vblank = psde->pipe_sblk->creq_vblank;
  306. psde->pipe_qos_cfg.danger_vblank =
  307. psde->pipe_sblk->danger_vblank;
  308. psde->pipe_qos_cfg.vblank_en = enable;
  309. }
  310. if (flags & SDE_PLANE_QOS_VBLANK_AMORTIZE) {
  311. /* this feature overrules previous VBLANK_CTRL */
  312. psde->pipe_qos_cfg.vblank_en = false;
  313. psde->pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */
  314. }
  315. if (flags & SDE_PLANE_QOS_PANIC_CTRL)
  316. psde->pipe_qos_cfg.danger_safe_en = enable;
  317. if (!psde->is_rt_pipe) {
  318. psde->pipe_qos_cfg.vblank_en = false;
  319. psde->pipe_qos_cfg.danger_safe_en = false;
  320. }
  321. SDE_DEBUG("plane%u: pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n",
  322. plane->base.id,
  323. psde->pipe - SSPP_VIG0,
  324. psde->pipe_qos_cfg.danger_safe_en,
  325. psde->pipe_qos_cfg.vblank_en,
  326. psde->pipe_qos_cfg.creq_vblank,
  327. psde->pipe_qos_cfg.danger_vblank,
  328. psde->is_rt_pipe);
  329. psde->pipe_hw->ops.setup_qos_ctrl(psde->pipe_hw,
  330. &psde->pipe_qos_cfg);
  331. }
  332. void sde_plane_set_revalidate(struct drm_plane *plane, bool enable)
  333. {
  334. struct sde_plane *psde;
  335. if (!plane)
  336. return;
  337. psde = to_sde_plane(plane);
  338. psde->revalidate = enable;
  339. }
  340. int sde_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
  341. {
  342. struct sde_plane *psde;
  343. int rc;
  344. if (!plane) {
  345. SDE_ERROR("invalid arguments\n");
  346. return -EINVAL;
  347. }
  348. psde = to_sde_plane(plane);
  349. if (!psde->is_rt_pipe)
  350. goto end;
  351. rc = pm_runtime_get_sync(plane->dev->dev);
  352. if (rc < 0) {
  353. SDE_ERROR("failed to enable power resource %d\n", rc);
  354. SDE_EVT32(rc, SDE_EVTLOG_ERROR);
  355. return rc;
  356. }
  357. _sde_plane_set_qos_ctrl(plane, enable, SDE_PLANE_QOS_PANIC_CTRL);
  358. pm_runtime_put_sync(plane->dev->dev);
  359. end:
  360. return 0;
  361. }
  362. /**
  363. * _sde_plane_set_ot_limit - set OT limit for the given plane
  364. * @plane: Pointer to drm plane
  365. * @crtc: Pointer to drm crtc
  366. */
  367. static void _sde_plane_set_ot_limit(struct drm_plane *plane,
  368. struct drm_crtc *crtc)
  369. {
  370. struct sde_plane *psde;
  371. struct sde_vbif_set_ot_params ot_params;
  372. struct msm_drm_private *priv;
  373. struct sde_kms *sde_kms;
  374. if (!plane || !plane->dev || !crtc) {
  375. SDE_ERROR("invalid arguments plane %d crtc %d\n",
  376. !plane, !crtc);
  377. return;
  378. }
  379. priv = plane->dev->dev_private;
  380. if (!priv || !priv->kms) {
  381. SDE_ERROR("invalid KMS reference\n");
  382. return;
  383. }
  384. sde_kms = to_sde_kms(priv->kms);
  385. psde = to_sde_plane(plane);
  386. if (!psde->pipe_hw) {
  387. SDE_ERROR("invalid pipe reference\n");
  388. return;
  389. }
  390. memset(&ot_params, 0, sizeof(ot_params));
  391. ot_params.xin_id = psde->pipe_hw->cap->xin_id;
  392. ot_params.num = psde->pipe_hw->idx - SSPP_NONE;
  393. ot_params.width = psde->pipe_cfg.src_rect.w;
  394. ot_params.height = psde->pipe_cfg.src_rect.h;
  395. ot_params.is_wfd = !psde->is_rt_pipe;
  396. ot_params.frame_rate = crtc->mode.vrefresh;
  397. ot_params.vbif_idx = VBIF_RT;
  398. ot_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  399. ot_params.rd = true;
  400. sde_vbif_set_ot_limit(sde_kms, &ot_params);
  401. }
  402. /**
  403. * _sde_plane_set_vbif_qos - set vbif QoS for the given plane
  404. * @plane: Pointer to drm plane
  405. */
  406. static void _sde_plane_set_qos_remap(struct drm_plane *plane)
  407. {
  408. struct sde_plane *psde;
  409. struct sde_vbif_set_qos_params qos_params;
  410. struct msm_drm_private *priv;
  411. struct sde_kms *sde_kms;
  412. if (!plane || !plane->dev) {
  413. SDE_ERROR("invalid arguments\n");
  414. return;
  415. }
  416. priv = plane->dev->dev_private;
  417. if (!priv || !priv->kms) {
  418. SDE_ERROR("invalid KMS reference\n");
  419. return;
  420. }
  421. sde_kms = to_sde_kms(priv->kms);
  422. psde = to_sde_plane(plane);
  423. if (!psde->pipe_hw) {
  424. SDE_ERROR("invalid pipe reference\n");
  425. return;
  426. }
  427. memset(&qos_params, 0, sizeof(qos_params));
  428. qos_params.vbif_idx = VBIF_RT;
  429. qos_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  430. qos_params.xin_id = psde->pipe_hw->cap->xin_id;
  431. qos_params.num = psde->pipe_hw->idx - SSPP_VIG0;
  432. qos_params.client_type = psde->is_rt_pipe ?
  433. VBIF_RT_CLIENT : VBIF_NRT_CLIENT;
  434. SDE_DEBUG("plane%d pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n",
  435. plane->base.id, qos_params.num,
  436. qos_params.vbif_idx,
  437. qos_params.xin_id, qos_params.client_type,
  438. qos_params.clk_ctrl);
  439. sde_vbif_set_qos_remap(sde_kms, &qos_params);
  440. }
  441. /**
  442. * _sde_plane_set_ts_prefill - set prefill with traffic shaper
  443. * @plane: Pointer to drm plane
  444. * @pstate: Pointer to sde plane state
  445. */
  446. static void _sde_plane_set_ts_prefill(struct drm_plane *plane,
  447. struct sde_plane_state *pstate)
  448. {
  449. struct sde_plane *psde;
  450. struct sde_hw_pipe_ts_cfg cfg;
  451. struct msm_drm_private *priv;
  452. struct sde_kms *sde_kms;
  453. if (!plane || !plane->dev) {
  454. SDE_ERROR("invalid arguments");
  455. return;
  456. }
  457. priv = plane->dev->dev_private;
  458. if (!priv || !priv->kms) {
  459. SDE_ERROR("invalid KMS reference\n");
  460. return;
  461. }
  462. sde_kms = to_sde_kms(priv->kms);
  463. psde = to_sde_plane(plane);
  464. if (!psde->pipe_hw) {
  465. SDE_ERROR("invalid pipe reference\n");
  466. return;
  467. }
  468. if (!psde->pipe_hw || !psde->pipe_hw->ops.setup_ts_prefill)
  469. return;
  470. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_VBLANK_AMORTIZE);
  471. memset(&cfg, 0, sizeof(cfg));
  472. cfg.size = sde_plane_get_property(pstate,
  473. PLANE_PROP_PREFILL_SIZE);
  474. cfg.time = sde_plane_get_property(pstate,
  475. PLANE_PROP_PREFILL_TIME);
  476. SDE_DEBUG("plane%d size:%llu time:%llu\n",
  477. plane->base.id, cfg.size, cfg.time);
  478. SDE_EVT32_VERBOSE(DRMID(plane), cfg.size, cfg.time);
  479. psde->pipe_hw->ops.setup_ts_prefill(psde->pipe_hw, &cfg,
  480. pstate->multirect_index);
  481. }
  482. /* helper to update a state's input fence pointer from the property */
  483. static void _sde_plane_set_input_fence(struct sde_plane *psde,
  484. struct sde_plane_state *pstate, uint64_t fd)
  485. {
  486. if (!psde || !pstate) {
  487. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  488. !psde, !pstate);
  489. return;
  490. }
  491. /* clear previous reference */
  492. if (pstate->input_fence)
  493. sde_sync_put(pstate->input_fence);
  494. /* get fence pointer for later */
  495. if (fd == 0)
  496. pstate->input_fence = NULL;
  497. else
  498. pstate->input_fence = sde_sync_get(fd);
  499. SDE_DEBUG_PLANE(psde, "0x%llX\n", fd);
  500. }
  501. int sde_plane_wait_input_fence(struct drm_plane *plane, uint32_t wait_ms)
  502. {
  503. struct sde_plane *psde;
  504. struct sde_plane_state *pstate;
  505. uint32_t prefix;
  506. void *input_fence;
  507. int ret = -EINVAL;
  508. signed long rc;
  509. if (!plane) {
  510. SDE_ERROR("invalid plane\n");
  511. } else if (!plane->state) {
  512. SDE_ERROR_PLANE(to_sde_plane(plane), "invalid state\n");
  513. } else {
  514. psde = to_sde_plane(plane);
  515. pstate = to_sde_plane_state(plane->state);
  516. input_fence = pstate->input_fence;
  517. if (input_fence) {
  518. prefix = sde_sync_get_name_prefix(input_fence);
  519. rc = sde_sync_wait(input_fence, wait_ms);
  520. switch (rc) {
  521. case 0:
  522. SDE_ERROR_PLANE(psde, "%ums timeout on %08X fd %d\n",
  523. wait_ms, prefix, sde_plane_get_property(pstate,
  524. PLANE_PROP_INPUT_FENCE));
  525. psde->is_error = true;
  526. sde_kms_timeline_status(plane->dev);
  527. ret = -ETIMEDOUT;
  528. break;
  529. case -ERESTARTSYS:
  530. SDE_ERROR_PLANE(psde,
  531. "%ums wait interrupted on %08X\n",
  532. wait_ms, prefix);
  533. psde->is_error = true;
  534. ret = -ERESTARTSYS;
  535. break;
  536. case -EINVAL:
  537. SDE_ERROR_PLANE(psde,
  538. "invalid fence param for %08X\n",
  539. prefix);
  540. psde->is_error = true;
  541. ret = -EINVAL;
  542. break;
  543. default:
  544. SDE_DEBUG_PLANE(psde, "signaled\n");
  545. ret = 0;
  546. break;
  547. }
  548. SDE_EVT32_VERBOSE(DRMID(plane), -ret, prefix);
  549. } else {
  550. ret = 0;
  551. }
  552. }
  553. return ret;
  554. }
  555. /**
  556. * _sde_plane_get_aspace: gets the address space based on the
  557. * fb_translation mode property
  558. */
  559. static int _sde_plane_get_aspace(
  560. struct sde_plane *psde,
  561. struct sde_plane_state *pstate,
  562. struct msm_gem_address_space **aspace)
  563. {
  564. struct sde_kms *kms;
  565. int mode;
  566. if (!psde || !pstate || !aspace) {
  567. SDE_ERROR("invalid parameters\n");
  568. return -EINVAL;
  569. }
  570. kms = _sde_plane_get_kms(&psde->base);
  571. if (!kms) {
  572. SDE_ERROR("invalid kms\n");
  573. return -EINVAL;
  574. }
  575. mode = sde_plane_get_property(pstate,
  576. PLANE_PROP_FB_TRANSLATION_MODE);
  577. switch (mode) {
  578. case SDE_DRM_FB_NON_SEC:
  579. *aspace = kms->aspace[MSM_SMMU_DOMAIN_UNSECURE];
  580. if (!aspace)
  581. return -EINVAL;
  582. break;
  583. case SDE_DRM_FB_SEC:
  584. *aspace = kms->aspace[MSM_SMMU_DOMAIN_SECURE];
  585. if (!aspace)
  586. return -EINVAL;
  587. break;
  588. case SDE_DRM_FB_NON_SEC_DIR_TRANS:
  589. case SDE_DRM_FB_SEC_DIR_TRANS:
  590. *aspace = NULL;
  591. break;
  592. default:
  593. SDE_ERROR("invalid fb_translation mode:%d\n", mode);
  594. return -EFAULT;
  595. }
  596. return 0;
  597. }
  598. static inline void _sde_plane_set_scanout(struct drm_plane *plane,
  599. struct sde_plane_state *pstate,
  600. struct sde_hw_pipe_cfg *pipe_cfg,
  601. struct drm_framebuffer *fb)
  602. {
  603. struct sde_plane *psde;
  604. struct msm_gem_address_space *aspace = NULL;
  605. int ret, mode;
  606. bool secure = false;
  607. if (!plane || !pstate || !pipe_cfg || !fb) {
  608. SDE_ERROR(
  609. "invalid arg(s), plane %d state %d cfg %d fb %d\n",
  610. !plane, !pstate, !pipe_cfg, !fb);
  611. return;
  612. }
  613. psde = to_sde_plane(plane);
  614. if (!psde->pipe_hw) {
  615. SDE_ERROR_PLANE(psde, "invalid pipe_hw\n");
  616. return;
  617. }
  618. ret = _sde_plane_get_aspace(psde, pstate, &aspace);
  619. if (ret) {
  620. SDE_ERROR_PLANE(psde, "Failed to get aspace %d\n", ret);
  621. return;
  622. }
  623. /*
  624. * framebuffer prepare is deferred for prepare_fb calls that
  625. * happen during the transition from secure to non-secure.
  626. * Handle the prepare at this point for such cases. This can be
  627. * expected for one or two frames during the transition.
  628. */
  629. if (aspace && pstate->defer_prepare_fb) {
  630. SDE_EVT32(DRMID(plane), psde->pipe, aspace->domain_attached);
  631. ret = msm_framebuffer_prepare(fb, pstate->aspace);
  632. if (ret) {
  633. SDE_ERROR_PLANE(psde,
  634. "failed to prepare framebuffer %d\n", ret);
  635. return;
  636. }
  637. pstate->defer_prepare_fb = false;
  638. }
  639. mode = sde_plane_get_property(pstate, PLANE_PROP_FB_TRANSLATION_MODE);
  640. if ((mode == SDE_DRM_FB_SEC) || (mode == SDE_DRM_FB_SEC_DIR_TRANS))
  641. secure = true;
  642. ret = sde_format_populate_layout(aspace, fb, &pipe_cfg->layout);
  643. if (ret == -EAGAIN)
  644. SDE_DEBUG_PLANE(psde, "not updating same src addrs\n");
  645. else if (ret) {
  646. SDE_ERROR_PLANE(psde, "failed to get format layout, %d\n", ret);
  647. /*
  648. * Force solid fill color on error. This is to prevent
  649. * smmu faults during secure session transition.
  650. */
  651. psde->is_error = true;
  652. } else if (psde->pipe_hw->ops.setup_sourceaddress) {
  653. SDE_EVT32_VERBOSE(psde->pipe_hw->idx,
  654. pipe_cfg->layout.width,
  655. pipe_cfg->layout.height,
  656. pipe_cfg->layout.plane_addr[0],
  657. pipe_cfg->layout.plane_size[0],
  658. pipe_cfg->layout.plane_addr[1],
  659. pipe_cfg->layout.plane_size[1],
  660. pipe_cfg->layout.plane_addr[2],
  661. pipe_cfg->layout.plane_size[2],
  662. pipe_cfg->layout.plane_addr[3],
  663. pipe_cfg->layout.plane_size[3],
  664. pstate->multirect_index,
  665. secure);
  666. psde->pipe_hw->ops.setup_sourceaddress(psde->pipe_hw, pipe_cfg,
  667. pstate->multirect_index);
  668. }
  669. }
  670. static int _sde_plane_setup_scaler3_lut(struct sde_plane *psde,
  671. struct sde_plane_state *pstate)
  672. {
  673. struct sde_hw_scaler3_cfg *cfg;
  674. int ret = 0;
  675. if (!psde || !pstate) {
  676. SDE_ERROR("invalid args\n");
  677. return -EINVAL;
  678. }
  679. cfg = &pstate->scaler3_cfg;
  680. cfg->dir_lut = msm_property_get_blob(
  681. &psde->property_info,
  682. &pstate->property_state, &cfg->dir_len,
  683. PLANE_PROP_SCALER_LUT_ED);
  684. cfg->cir_lut = msm_property_get_blob(
  685. &psde->property_info,
  686. &pstate->property_state, &cfg->cir_len,
  687. PLANE_PROP_SCALER_LUT_CIR);
  688. cfg->sep_lut = msm_property_get_blob(
  689. &psde->property_info,
  690. &pstate->property_state, &cfg->sep_len,
  691. PLANE_PROP_SCALER_LUT_SEP);
  692. if (!cfg->dir_lut || !cfg->cir_lut || !cfg->sep_lut)
  693. ret = -ENODATA;
  694. return ret;
  695. }
  696. static int _sde_plane_setup_scaler3lite_lut(struct sde_plane *psde,
  697. struct sde_plane_state *pstate)
  698. {
  699. struct sde_hw_scaler3_cfg *cfg;
  700. cfg = &pstate->scaler3_cfg;
  701. cfg->sep_lut = msm_property_get_blob(
  702. &psde->property_info,
  703. &pstate->property_state, &cfg->sep_len,
  704. PLANE_PROP_SCALER_LUT_SEP);
  705. return cfg->sep_lut ? 0 : -ENODATA;
  706. }
  707. static void _sde_plane_setup_scaler3(struct sde_plane *psde,
  708. struct sde_plane_state *pstate, const struct sde_format *fmt,
  709. uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v)
  710. {
  711. uint32_t decimated, i, src_w, src_h, dst_w, dst_h, src_h_pre_down;
  712. struct sde_hw_scaler3_cfg *scale_cfg;
  713. bool pre_down_supported = (psde->features & BIT(SDE_SSPP_PREDOWNSCALE));
  714. bool inline_rotation = (pstate->rotation & DRM_MODE_ROTATE_90);
  715. if (!fmt || !chroma_subsmpl_h || !chroma_subsmpl_v) {
  716. SDE_ERROR("fmt %d smp_h %d smp_v %d\n", !fmt,
  717. chroma_subsmpl_h, chroma_subsmpl_v);
  718. return;
  719. }
  720. scale_cfg = &pstate->scaler3_cfg;
  721. src_w = psde->pipe_cfg.src_rect.w;
  722. src_h = psde->pipe_cfg.src_rect.h;
  723. dst_w = psde->pipe_cfg.dst_rect.w;
  724. dst_h = psde->pipe_cfg.dst_rect.h;
  725. memset(scale_cfg, 0, sizeof(*scale_cfg));
  726. memset(&pstate->pixel_ext, 0, sizeof(struct sde_hw_pixel_ext));
  727. /*
  728. * For inline rotation cases, scaler config is post-rotation,
  729. * so swap the dimensions here. However, pixel extension will
  730. * need pre-rotation settings, this will be corrected below
  731. * when calculating pixel extension settings.
  732. */
  733. if (inline_rotation)
  734. swap(src_w, src_h);
  735. decimated = DECIMATED_DIMENSION(src_w,
  736. psde->pipe_cfg.horz_decimation);
  737. scale_cfg->phase_step_x[SDE_SSPP_COMP_0] =
  738. mult_frac((1 << PHASE_STEP_SHIFT), decimated, dst_w);
  739. decimated = DECIMATED_DIMENSION(src_h,
  740. psde->pipe_cfg.vert_decimation);
  741. scale_cfg->phase_step_y[SDE_SSPP_COMP_0] =
  742. mult_frac((1 << PHASE_STEP_SHIFT), decimated, dst_h);
  743. scale_cfg->phase_step_y[SDE_SSPP_COMP_1_2] =
  744. scale_cfg->phase_step_y[SDE_SSPP_COMP_0] / chroma_subsmpl_v;
  745. scale_cfg->phase_step_x[SDE_SSPP_COMP_1_2] =
  746. scale_cfg->phase_step_x[SDE_SSPP_COMP_0] / chroma_subsmpl_h;
  747. scale_cfg->phase_step_x[SDE_SSPP_COMP_2] =
  748. scale_cfg->phase_step_x[SDE_SSPP_COMP_1_2];
  749. scale_cfg->phase_step_y[SDE_SSPP_COMP_2] =
  750. scale_cfg->phase_step_y[SDE_SSPP_COMP_1_2];
  751. scale_cfg->phase_step_x[SDE_SSPP_COMP_3] =
  752. scale_cfg->phase_step_x[SDE_SSPP_COMP_0];
  753. scale_cfg->phase_step_y[SDE_SSPP_COMP_3] =
  754. scale_cfg->phase_step_y[SDE_SSPP_COMP_0];
  755. for (i = 0; i < SDE_MAX_PLANES; i++) {
  756. /*
  757. * For inline rotation cases with pre-downscaling enabled
  758. * set x pre-downscale value if required. Only x direction
  759. * is currently supported. Use src_h as values have been swapped
  760. * and x direction corresponds to height value.
  761. */
  762. src_h_pre_down = src_h;
  763. if (pre_down_supported && inline_rotation) {
  764. if (i == 0 && (src_h > mult_frac(dst_h, 11, 5)))
  765. src_h_pre_down = src_h / 2;
  766. }
  767. scale_cfg->src_width[i] = DECIMATED_DIMENSION(src_w,
  768. psde->pipe_cfg.horz_decimation);
  769. scale_cfg->src_height[i] = DECIMATED_DIMENSION(src_h_pre_down,
  770. psde->pipe_cfg.vert_decimation);
  771. if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2) {
  772. scale_cfg->src_width[i] /= chroma_subsmpl_h;
  773. scale_cfg->src_height[i] /= chroma_subsmpl_v;
  774. }
  775. scale_cfg->preload_x[i] = psde->pipe_sblk->scaler_blk.h_preload;
  776. scale_cfg->preload_y[i] = psde->pipe_sblk->scaler_blk.v_preload;
  777. /* For pixel extension we need the pre-rotated orientation */
  778. if (inline_rotation) {
  779. pstate->pixel_ext.num_ext_pxls_top[i] =
  780. scale_cfg->src_width[i];
  781. pstate->pixel_ext.num_ext_pxls_left[i] =
  782. scale_cfg->src_height[i];
  783. } else {
  784. pstate->pixel_ext.num_ext_pxls_top[i] =
  785. scale_cfg->src_height[i];
  786. pstate->pixel_ext.num_ext_pxls_left[i] =
  787. scale_cfg->src_width[i];
  788. }
  789. }
  790. if ((!(SDE_FORMAT_IS_YUV(fmt)) && (src_h == dst_h)
  791. && (src_w == dst_w) && !inline_rotation) ||
  792. pstate->multirect_mode)
  793. return;
  794. SDE_DEBUG_PLANE(psde,
  795. "setting bilinear: src:%dx%d dst:%dx%d chroma:%dx%d fmt:%x\n",
  796. src_w, src_h, dst_w, dst_h,
  797. chroma_subsmpl_v, chroma_subsmpl_h,
  798. fmt->base.pixel_format);
  799. scale_cfg->dst_width = dst_w;
  800. scale_cfg->dst_height = dst_h;
  801. scale_cfg->y_rgb_filter_cfg = SDE_SCALE_BIL;
  802. scale_cfg->uv_filter_cfg = SDE_SCALE_BIL;
  803. scale_cfg->alpha_filter_cfg = SDE_SCALE_ALPHA_BIL;
  804. scale_cfg->lut_flag = 0;
  805. scale_cfg->blend_cfg = 1;
  806. scale_cfg->enable = 1;
  807. scale_cfg->dyn_exp_disabled = SDE_QSEED_DEFAULT_DYN_EXP;
  808. }
  809. /**
  810. * _sde_plane_setup_scaler2 - determine default scaler phase steps/filter type
  811. * @psde: Pointer to SDE plane object
  812. * @src: Source size
  813. * @dst: Destination size
  814. * @phase_steps: Pointer to output array for phase steps
  815. * @filter: Pointer to output array for filter type
  816. * @fmt: Pointer to format definition
  817. * @chroma_subsampling: Subsampling amount for chroma channel
  818. *
  819. * Returns: 0 on success
  820. */
  821. static int _sde_plane_setup_scaler2(struct sde_plane *psde,
  822. uint32_t src, uint32_t dst, uint32_t *phase_steps,
  823. enum sde_hw_filter *filter, const struct sde_format *fmt,
  824. uint32_t chroma_subsampling)
  825. {
  826. if (!psde || !phase_steps || !filter || !fmt) {
  827. SDE_ERROR(
  828. "invalid arg(s), plane %d phase %d filter %d fmt %d\n",
  829. !psde, !phase_steps, !filter, !fmt);
  830. return -EINVAL;
  831. }
  832. /* calculate phase steps, leave init phase as zero */
  833. phase_steps[SDE_SSPP_COMP_0] =
  834. mult_frac(1 << PHASE_STEP_SHIFT, src, dst);
  835. phase_steps[SDE_SSPP_COMP_1_2] =
  836. phase_steps[SDE_SSPP_COMP_0] / chroma_subsampling;
  837. phase_steps[SDE_SSPP_COMP_2] = phase_steps[SDE_SSPP_COMP_1_2];
  838. phase_steps[SDE_SSPP_COMP_3] = phase_steps[SDE_SSPP_COMP_0];
  839. /* calculate scaler config, if necessary */
  840. if (SDE_FORMAT_IS_YUV(fmt) || src != dst) {
  841. filter[SDE_SSPP_COMP_3] =
  842. (src <= dst) ? SDE_SCALE_FILTER_BIL :
  843. SDE_SCALE_FILTER_PCMN;
  844. if (SDE_FORMAT_IS_YUV(fmt)) {
  845. filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_CA;
  846. filter[SDE_SSPP_COMP_1_2] = filter[SDE_SSPP_COMP_3];
  847. } else {
  848. filter[SDE_SSPP_COMP_0] = filter[SDE_SSPP_COMP_3];
  849. filter[SDE_SSPP_COMP_1_2] =
  850. SDE_SCALE_FILTER_NEAREST;
  851. }
  852. } else {
  853. /* disable scaler */
  854. filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_MAX;
  855. filter[SDE_SSPP_COMP_1_2] = SDE_SCALE_FILTER_MAX;
  856. filter[SDE_SSPP_COMP_3] = SDE_SCALE_FILTER_MAX;
  857. }
  858. return 0;
  859. }
  860. /**
  861. * _sde_plane_setup_pixel_ext - determine default pixel extension values
  862. * @psde: Pointer to SDE plane object
  863. * @src: Source size
  864. * @dst: Destination size
  865. * @decimated_src: Source size after decimation, if any
  866. * @phase_steps: Pointer to output array for phase steps
  867. * @out_src: Output array for pixel extension values
  868. * @out_edge1: Output array for pixel extension first edge
  869. * @out_edge2: Output array for pixel extension second edge
  870. * @filter: Pointer to array for filter type
  871. * @fmt: Pointer to format definition
  872. * @chroma_subsampling: Subsampling amount for chroma channel
  873. * @post_compare: Whether to chroma subsampled source size for comparisions
  874. */
  875. static void _sde_plane_setup_pixel_ext(struct sde_plane *psde,
  876. uint32_t src, uint32_t dst, uint32_t decimated_src,
  877. uint32_t *phase_steps, uint32_t *out_src, int *out_edge1,
  878. int *out_edge2, enum sde_hw_filter *filter,
  879. const struct sde_format *fmt, uint32_t chroma_subsampling,
  880. bool post_compare)
  881. {
  882. int64_t edge1, edge2, caf;
  883. uint32_t src_work;
  884. int i, tmp;
  885. if (psde && phase_steps && out_src && out_edge1 &&
  886. out_edge2 && filter && fmt) {
  887. /* handle CAF for YUV formats */
  888. if (SDE_FORMAT_IS_YUV(fmt) && *filter == SDE_SCALE_FILTER_CA)
  889. caf = PHASE_STEP_UNIT_SCALE;
  890. else
  891. caf = 0;
  892. for (i = 0; i < SDE_MAX_PLANES; i++) {
  893. src_work = decimated_src;
  894. if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2)
  895. src_work /= chroma_subsampling;
  896. if (post_compare)
  897. src = src_work;
  898. if (!SDE_FORMAT_IS_YUV(fmt) && (src == dst)) {
  899. /* unity */
  900. edge1 = 0;
  901. edge2 = 0;
  902. } else if (dst >= src) {
  903. /* upscale */
  904. edge1 = (1 << PHASE_RESIDUAL);
  905. edge1 -= caf;
  906. edge2 = (1 << PHASE_RESIDUAL);
  907. edge2 += (dst - 1) * *(phase_steps + i);
  908. edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
  909. edge2 += caf;
  910. edge2 = -(edge2);
  911. } else {
  912. /* downscale */
  913. edge1 = 0;
  914. edge2 = (dst - 1) * *(phase_steps + i);
  915. edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
  916. edge2 += *(phase_steps + i);
  917. edge2 = -(edge2);
  918. }
  919. /* only enable CAF for luma plane */
  920. caf = 0;
  921. /* populate output arrays */
  922. *(out_src + i) = src_work;
  923. /* edge updates taken from __pxl_extn_helper */
  924. if (edge1 >= 0) {
  925. tmp = (uint32_t)edge1;
  926. tmp >>= PHASE_STEP_SHIFT;
  927. *(out_edge1 + i) = -tmp;
  928. } else {
  929. tmp = (uint32_t)(-edge1);
  930. *(out_edge1 + i) =
  931. (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
  932. PHASE_STEP_SHIFT;
  933. }
  934. if (edge2 >= 0) {
  935. tmp = (uint32_t)edge2;
  936. tmp >>= PHASE_STEP_SHIFT;
  937. *(out_edge2 + i) = -tmp;
  938. } else {
  939. tmp = (uint32_t)(-edge2);
  940. *(out_edge2 + i) =
  941. (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
  942. PHASE_STEP_SHIFT;
  943. }
  944. }
  945. }
  946. }
  947. static inline void _sde_plane_setup_csc(struct sde_plane *psde)
  948. {
  949. static const struct sde_csc_cfg sde_csc_YUV2RGB_601L = {
  950. {
  951. /* S15.16 format */
  952. 0x00012A00, 0x00000000, 0x00019880,
  953. 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
  954. 0x00012A00, 0x00020480, 0x00000000,
  955. },
  956. /* signed bias */
  957. { 0xfff0, 0xff80, 0xff80,},
  958. { 0x0, 0x0, 0x0,},
  959. /* unsigned clamp */
  960. { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,},
  961. { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,},
  962. };
  963. static const struct sde_csc_cfg sde_csc10_YUV2RGB_601L = {
  964. {
  965. /* S15.16 format */
  966. 0x00012A00, 0x00000000, 0x00019880,
  967. 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
  968. 0x00012A00, 0x00020480, 0x00000000,
  969. },
  970. /* signed bias */
  971. { 0xffc0, 0xfe00, 0xfe00,},
  972. { 0x0, 0x0, 0x0,},
  973. /* unsigned clamp */
  974. { 0x40, 0x3ac, 0x40, 0x3c0, 0x40, 0x3c0,},
  975. { 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,},
  976. };
  977. if (!psde) {
  978. SDE_ERROR("invalid plane\n");
  979. return;
  980. }
  981. /* revert to kernel default if override not available */
  982. if (psde->csc_usr_ptr)
  983. psde->csc_ptr = psde->csc_usr_ptr;
  984. else if (BIT(SDE_SSPP_CSC_10BIT) & psde->features)
  985. psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc10_YUV2RGB_601L;
  986. else
  987. psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc_YUV2RGB_601L;
  988. SDE_DEBUG_PLANE(psde, "using 0x%X 0x%X 0x%X...\n",
  989. psde->csc_ptr->csc_mv[0],
  990. psde->csc_ptr->csc_mv[1],
  991. psde->csc_ptr->csc_mv[2]);
  992. }
  993. static void sde_color_process_plane_setup(struct drm_plane *plane)
  994. {
  995. struct sde_plane *psde;
  996. struct sde_plane_state *pstate;
  997. uint32_t hue, saturation, value, contrast;
  998. struct drm_msm_memcol *memcol = NULL;
  999. struct drm_msm_3d_gamut *vig_gamut = NULL;
  1000. struct drm_msm_igc_lut *igc = NULL;
  1001. struct drm_msm_pgc_lut *gc = NULL;
  1002. size_t memcol_sz = 0, size = 0;
  1003. struct sde_hw_cp_cfg hw_cfg = {};
  1004. struct sde_hw_ctl *ctl = _sde_plane_get_hw_ctl(plane);
  1005. psde = to_sde_plane(plane);
  1006. pstate = to_sde_plane_state(plane->state);
  1007. hue = (uint32_t) sde_plane_get_property(pstate, PLANE_PROP_HUE_ADJUST);
  1008. if (psde->pipe_hw->ops.setup_pa_hue)
  1009. psde->pipe_hw->ops.setup_pa_hue(psde->pipe_hw, &hue);
  1010. saturation = (uint32_t) sde_plane_get_property(pstate,
  1011. PLANE_PROP_SATURATION_ADJUST);
  1012. if (psde->pipe_hw->ops.setup_pa_sat)
  1013. psde->pipe_hw->ops.setup_pa_sat(psde->pipe_hw, &saturation);
  1014. value = (uint32_t) sde_plane_get_property(pstate,
  1015. PLANE_PROP_VALUE_ADJUST);
  1016. if (psde->pipe_hw->ops.setup_pa_val)
  1017. psde->pipe_hw->ops.setup_pa_val(psde->pipe_hw, &value);
  1018. contrast = (uint32_t) sde_plane_get_property(pstate,
  1019. PLANE_PROP_CONTRAST_ADJUST);
  1020. if (psde->pipe_hw->ops.setup_pa_cont)
  1021. psde->pipe_hw->ops.setup_pa_cont(psde->pipe_hw, &contrast);
  1022. if (psde->pipe_hw->ops.setup_pa_memcolor) {
  1023. /* Skin memory color setup */
  1024. memcol = msm_property_get_blob(&psde->property_info,
  1025. &pstate->property_state,
  1026. &memcol_sz,
  1027. PLANE_PROP_SKIN_COLOR);
  1028. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1029. MEMCOLOR_SKIN, memcol);
  1030. /* Sky memory color setup */
  1031. memcol = msm_property_get_blob(&psde->property_info,
  1032. &pstate->property_state,
  1033. &memcol_sz,
  1034. PLANE_PROP_SKY_COLOR);
  1035. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1036. MEMCOLOR_SKY, memcol);
  1037. /* Foliage memory color setup */
  1038. memcol = msm_property_get_blob(&psde->property_info,
  1039. &pstate->property_state,
  1040. &memcol_sz,
  1041. PLANE_PROP_FOLIAGE_COLOR);
  1042. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1043. MEMCOLOR_FOLIAGE, memcol);
  1044. }
  1045. if (pstate->dirty & SDE_PLANE_DIRTY_VIG_GAMUT &&
  1046. psde->pipe_hw->ops.setup_vig_gamut) {
  1047. vig_gamut = msm_property_get_blob(&psde->property_info,
  1048. &pstate->property_state,
  1049. &size,
  1050. PLANE_PROP_VIG_GAMUT);
  1051. hw_cfg.last_feature = 0;
  1052. hw_cfg.ctl = ctl;
  1053. hw_cfg.len = sizeof(struct drm_msm_3d_gamut);
  1054. hw_cfg.payload = vig_gamut;
  1055. psde->pipe_hw->ops.setup_vig_gamut(psde->pipe_hw, &hw_cfg);
  1056. }
  1057. if (pstate->dirty & SDE_PLANE_DIRTY_VIG_IGC &&
  1058. psde->pipe_hw->ops.setup_vig_igc) {
  1059. igc = msm_property_get_blob(&psde->property_info,
  1060. &pstate->property_state,
  1061. &size,
  1062. PLANE_PROP_VIG_IGC);
  1063. hw_cfg.last_feature = 0;
  1064. hw_cfg.ctl = ctl;
  1065. hw_cfg.len = sizeof(struct drm_msm_igc_lut);
  1066. hw_cfg.payload = igc;
  1067. psde->pipe_hw->ops.setup_vig_igc(psde->pipe_hw, &hw_cfg);
  1068. }
  1069. if (pstate->dirty & SDE_PLANE_DIRTY_DMA_IGC &&
  1070. psde->pipe_hw->ops.setup_dma_igc) {
  1071. igc = msm_property_get_blob(&psde->property_info,
  1072. &pstate->property_state,
  1073. &size,
  1074. PLANE_PROP_DMA_IGC);
  1075. hw_cfg.last_feature = 0;
  1076. hw_cfg.ctl = ctl;
  1077. hw_cfg.len = sizeof(struct drm_msm_igc_lut);
  1078. hw_cfg.payload = igc;
  1079. psde->pipe_hw->ops.setup_dma_igc(psde->pipe_hw, &hw_cfg,
  1080. pstate->multirect_index);
  1081. }
  1082. if (pstate->dirty & SDE_PLANE_DIRTY_DMA_GC &&
  1083. psde->pipe_hw->ops.setup_dma_gc) {
  1084. gc = msm_property_get_blob(&psde->property_info,
  1085. &pstate->property_state,
  1086. &size,
  1087. PLANE_PROP_DMA_GC);
  1088. hw_cfg.last_feature = 0;
  1089. hw_cfg.ctl = ctl;
  1090. hw_cfg.len = sizeof(struct drm_msm_pgc_lut);
  1091. hw_cfg.payload = gc;
  1092. psde->pipe_hw->ops.setup_dma_gc(psde->pipe_hw, &hw_cfg,
  1093. pstate->multirect_index);
  1094. }
  1095. }
  1096. static void _sde_plane_setup_scaler(struct sde_plane *psde,
  1097. struct sde_plane_state *pstate,
  1098. const struct sde_format *fmt, bool color_fill)
  1099. {
  1100. struct sde_hw_pixel_ext *pe;
  1101. uint32_t chroma_subsmpl_h, chroma_subsmpl_v;
  1102. const struct drm_format_info *info = NULL;
  1103. if (!psde || !fmt || !pstate) {
  1104. SDE_ERROR("invalid arg(s), plane %d fmt %d state %d\n",
  1105. !psde, !fmt, !pstate);
  1106. return;
  1107. }
  1108. info = drm_format_info(fmt->base.pixel_format);
  1109. pe = &pstate->pixel_ext;
  1110. psde->pipe_cfg.horz_decimation =
  1111. sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
  1112. psde->pipe_cfg.vert_decimation =
  1113. sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
  1114. /* don't chroma subsample if decimating */
  1115. chroma_subsmpl_h = psde->pipe_cfg.horz_decimation ? 1 : info->hsub;
  1116. chroma_subsmpl_v = psde->pipe_cfg.vert_decimation ? 1 : info->vsub;
  1117. /* update scaler */
  1118. if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3) ||
  1119. (psde->features & BIT(SDE_SSPP_SCALER_QSEED3LITE))) {
  1120. int rc = -EINVAL;
  1121. if (!color_fill && !psde->debugfs_default_scale)
  1122. rc = is_qseed3_rev_qseed3lite(psde->pipe_hw->catalog) ?
  1123. _sde_plane_setup_scaler3lite_lut(psde, pstate) :
  1124. _sde_plane_setup_scaler3_lut(psde, pstate);
  1125. if (rc || pstate->scaler_check_state !=
  1126. SDE_PLANE_SCLCHECK_SCALER_V2) {
  1127. SDE_EVT32_VERBOSE(DRMID(&psde->base), color_fill,
  1128. pstate->scaler_check_state,
  1129. psde->debugfs_default_scale, rc,
  1130. psde->pipe_cfg.src_rect.w,
  1131. psde->pipe_cfg.src_rect.h,
  1132. psde->pipe_cfg.dst_rect.w,
  1133. psde->pipe_cfg.dst_rect.h,
  1134. pstate->multirect_mode);
  1135. /* calculate default config for QSEED3 */
  1136. _sde_plane_setup_scaler3(psde, pstate, fmt,
  1137. chroma_subsmpl_h, chroma_subsmpl_v);
  1138. }
  1139. } else if (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V1 ||
  1140. color_fill || psde->debugfs_default_scale) {
  1141. uint32_t deci_dim, i;
  1142. /* calculate default configuration for QSEED2 */
  1143. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  1144. SDE_DEBUG_PLANE(psde, "default config\n");
  1145. deci_dim = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.w,
  1146. psde->pipe_cfg.horz_decimation);
  1147. _sde_plane_setup_scaler2(psde,
  1148. deci_dim,
  1149. psde->pipe_cfg.dst_rect.w,
  1150. pe->phase_step_x,
  1151. pe->horz_filter, fmt, chroma_subsmpl_h);
  1152. if (SDE_FORMAT_IS_YUV(fmt))
  1153. deci_dim &= ~0x1;
  1154. _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.w,
  1155. psde->pipe_cfg.dst_rect.w, deci_dim,
  1156. pe->phase_step_x,
  1157. pe->roi_w,
  1158. pe->num_ext_pxls_left,
  1159. pe->num_ext_pxls_right, pe->horz_filter, fmt,
  1160. chroma_subsmpl_h, 0);
  1161. deci_dim = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.h,
  1162. psde->pipe_cfg.vert_decimation);
  1163. _sde_plane_setup_scaler2(psde,
  1164. deci_dim,
  1165. psde->pipe_cfg.dst_rect.h,
  1166. pe->phase_step_y,
  1167. pe->vert_filter, fmt, chroma_subsmpl_v);
  1168. _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.h,
  1169. psde->pipe_cfg.dst_rect.h, deci_dim,
  1170. pe->phase_step_y,
  1171. pe->roi_h,
  1172. pe->num_ext_pxls_top,
  1173. pe->num_ext_pxls_btm, pe->vert_filter, fmt,
  1174. chroma_subsmpl_v, 1);
  1175. for (i = 0; i < SDE_MAX_PLANES; i++) {
  1176. if (pe->num_ext_pxls_left[i] >= 0)
  1177. pe->left_rpt[i] = pe->num_ext_pxls_left[i];
  1178. else
  1179. pe->left_ftch[i] = pe->num_ext_pxls_left[i];
  1180. if (pe->num_ext_pxls_right[i] >= 0)
  1181. pe->right_rpt[i] = pe->num_ext_pxls_right[i];
  1182. else
  1183. pe->right_ftch[i] = pe->num_ext_pxls_right[i];
  1184. if (pe->num_ext_pxls_top[i] >= 0)
  1185. pe->top_rpt[i] = pe->num_ext_pxls_top[i];
  1186. else
  1187. pe->top_ftch[i] = pe->num_ext_pxls_top[i];
  1188. if (pe->num_ext_pxls_btm[i] >= 0)
  1189. pe->btm_rpt[i] = pe->num_ext_pxls_btm[i];
  1190. else
  1191. pe->btm_ftch[i] = pe->num_ext_pxls_btm[i];
  1192. }
  1193. }
  1194. if (psde->pipe_hw->ops.setup_pre_downscale)
  1195. psde->pipe_hw->ops.setup_pre_downscale(psde->pipe_hw,
  1196. &pstate->pre_down);
  1197. }
  1198. /**
  1199. * _sde_plane_color_fill - enables color fill on plane
  1200. * @psde: Pointer to SDE plane object
  1201. * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red
  1202. * @alpha: 8-bit fill alpha value, 255 selects 100% alpha
  1203. * Returns: 0 on success
  1204. */
  1205. static int _sde_plane_color_fill(struct sde_plane *psde,
  1206. uint32_t color, uint32_t alpha)
  1207. {
  1208. const struct sde_format *fmt;
  1209. const struct drm_plane *plane;
  1210. struct sde_plane_state *pstate;
  1211. bool blend_enable = true;
  1212. if (!psde || !psde->base.state) {
  1213. SDE_ERROR("invalid plane\n");
  1214. return -EINVAL;
  1215. }
  1216. if (!psde->pipe_hw) {
  1217. SDE_ERROR_PLANE(psde, "invalid plane h/w pointer\n");
  1218. return -EINVAL;
  1219. }
  1220. plane = &psde->base;
  1221. pstate = to_sde_plane_state(plane->state);
  1222. SDE_DEBUG_PLANE(psde, "\n");
  1223. /*
  1224. * select fill format to match user property expectation,
  1225. * h/w only supports RGB variants
  1226. */
  1227. fmt = sde_get_sde_format(DRM_FORMAT_ABGR8888);
  1228. blend_enable = (SDE_DRM_BLEND_OP_OPAQUE !=
  1229. sde_plane_get_property(pstate, PLANE_PROP_BLEND_OP));
  1230. /* update sspp */
  1231. if (fmt && psde->pipe_hw->ops.setup_solidfill) {
  1232. psde->pipe_hw->ops.setup_solidfill(psde->pipe_hw,
  1233. (color & 0xFFFFFF) | ((alpha & 0xFF) << 24),
  1234. pstate->multirect_index);
  1235. /* override scaler/decimation if solid fill */
  1236. psde->pipe_cfg.src_rect.x = 0;
  1237. psde->pipe_cfg.src_rect.y = 0;
  1238. psde->pipe_cfg.src_rect.w = psde->pipe_cfg.dst_rect.w;
  1239. psde->pipe_cfg.src_rect.h = psde->pipe_cfg.dst_rect.h;
  1240. _sde_plane_setup_scaler(psde, pstate, fmt, true);
  1241. if (psde->pipe_hw->ops.setup_format)
  1242. psde->pipe_hw->ops.setup_format(psde->pipe_hw,
  1243. fmt, blend_enable,
  1244. SDE_SSPP_SOLID_FILL,
  1245. pstate->multirect_index);
  1246. if (psde->pipe_hw->ops.setup_rects)
  1247. psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
  1248. &psde->pipe_cfg,
  1249. pstate->multirect_index);
  1250. if (psde->pipe_hw->ops.setup_pe)
  1251. psde->pipe_hw->ops.setup_pe(psde->pipe_hw,
  1252. &pstate->pixel_ext);
  1253. if (psde->pipe_hw->ops.setup_scaler &&
  1254. pstate->multirect_index != SDE_SSPP_RECT_1) {
  1255. psde->pipe_hw->ctl = _sde_plane_get_hw_ctl(plane);
  1256. psde->pipe_hw->ops.setup_scaler(psde->pipe_hw,
  1257. &psde->pipe_cfg, &pstate->pixel_ext,
  1258. &pstate->scaler3_cfg);
  1259. }
  1260. }
  1261. return 0;
  1262. }
  1263. /**
  1264. * sde_plane_rot_atomic_check - verify rotator update of the given state
  1265. * @plane: Pointer to drm plane
  1266. * @state: Pointer to drm plane state to be validated
  1267. * return: 0 if success; error code otherwise
  1268. */
  1269. static int sde_plane_rot_atomic_check(struct drm_plane *plane,
  1270. struct drm_plane_state *state)
  1271. {
  1272. struct sde_plane *psde;
  1273. struct sde_plane_state *pstate, *old_pstate;
  1274. int ret = 0;
  1275. u32 rotation;
  1276. if (!plane || !state) {
  1277. SDE_ERROR("invalid plane/state\n");
  1278. return -EINVAL;
  1279. }
  1280. psde = to_sde_plane(plane);
  1281. pstate = to_sde_plane_state(state);
  1282. old_pstate = to_sde_plane_state(plane->state);
  1283. /* check inline rotation and simplify the transform */
  1284. rotation = drm_rotation_simplify(
  1285. state->rotation,
  1286. DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
  1287. DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y);
  1288. if ((rotation & DRM_MODE_ROTATE_180) ||
  1289. (rotation & DRM_MODE_ROTATE_270)) {
  1290. SDE_ERROR_PLANE(psde,
  1291. "invalid rotation transform must be simplified 0x%x\n",
  1292. rotation);
  1293. ret = -EINVAL;
  1294. goto exit;
  1295. }
  1296. if (rotation & DRM_MODE_ROTATE_90) {
  1297. struct msm_drm_private *priv = plane->dev->dev_private;
  1298. struct sde_kms *sde_kms;
  1299. const struct msm_format *msm_fmt;
  1300. const struct sde_format *fmt;
  1301. struct sde_rect src;
  1302. bool q16_data = true;
  1303. POPULATE_RECT(&src, state->src_x, state->src_y,
  1304. state->src_w, state->src_h, q16_data);
  1305. /*
  1306. * DRM framework expects rotation flag in counter-clockwise
  1307. * direction and the HW expects in clockwise direction.
  1308. * Flip the flags to match with HW.
  1309. */
  1310. rotation ^= (DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y);
  1311. if (!psde->pipe_sblk->in_rot_maxdwnscale_rt_num ||
  1312. !psde->pipe_sblk->in_rot_maxdwnscale_rt_denom ||
  1313. !psde->pipe_sblk->in_rot_maxdwnscale_nrt ||
  1314. !psde->pipe_sblk->in_rot_maxheight ||
  1315. !psde->pipe_sblk->in_rot_format_list ||
  1316. !(psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT))) {
  1317. SDE_ERROR_PLANE(psde,
  1318. "wrong config rt:%d/%d nrt:%d fmt:%d h:%d 0x%x\n",
  1319. !psde->pipe_sblk->in_rot_maxdwnscale_rt_num,
  1320. !psde->pipe_sblk->in_rot_maxdwnscale_rt_denom,
  1321. !psde->pipe_sblk->in_rot_maxdwnscale_nrt,
  1322. !psde->pipe_sblk->in_rot_format_list,
  1323. !psde->pipe_sblk->in_rot_maxheight,
  1324. psde->features);
  1325. ret = -EINVAL;
  1326. goto exit;
  1327. }
  1328. /* check for valid height */
  1329. if (src.h > psde->pipe_sblk->in_rot_maxheight) {
  1330. SDE_ERROR_PLANE(psde,
  1331. "invalid height for inline rot:%d max:%d\n",
  1332. src.h, psde->pipe_sblk->in_rot_maxheight);
  1333. ret = -EINVAL;
  1334. goto exit;
  1335. }
  1336. if (!sde_plane_enabled(state))
  1337. goto exit;
  1338. /* check for valid formats supported by inline rot */
  1339. sde_kms = to_sde_kms(priv->kms);
  1340. msm_fmt = msm_framebuffer_format(state->fb);
  1341. fmt = to_sde_format(msm_fmt);
  1342. ret = sde_format_validate_fmt(&sde_kms->base, fmt,
  1343. psde->pipe_sblk->in_rot_format_list);
  1344. }
  1345. exit:
  1346. pstate->rotation = rotation;
  1347. return ret;
  1348. }
  1349. static bool _sde_plane_halt_requests(struct drm_plane *plane,
  1350. uint32_t xin_id, bool halt_forced_clk, bool enable)
  1351. {
  1352. struct sde_plane *psde;
  1353. struct msm_drm_private *priv;
  1354. struct sde_vbif_set_xin_halt_params halt_params;
  1355. if (!plane || !plane->dev) {
  1356. SDE_ERROR("invalid arguments\n");
  1357. return false;
  1358. }
  1359. psde = to_sde_plane(plane);
  1360. if (!psde->pipe_hw || !psde->pipe_hw->cap) {
  1361. SDE_ERROR("invalid pipe reference\n");
  1362. return false;
  1363. }
  1364. priv = plane->dev->dev_private;
  1365. if (!priv || !priv->kms) {
  1366. SDE_ERROR("invalid KMS reference\n");
  1367. return false;
  1368. }
  1369. memset(&halt_params, 0, sizeof(halt_params));
  1370. halt_params.vbif_idx = VBIF_RT;
  1371. halt_params.xin_id = xin_id;
  1372. halt_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  1373. halt_params.forced_on = halt_forced_clk;
  1374. halt_params.enable = enable;
  1375. return sde_vbif_set_xin_halt(to_sde_kms(priv->kms), &halt_params);
  1376. }
  1377. void sde_plane_halt_requests(struct drm_plane *plane, bool enable)
  1378. {
  1379. struct sde_plane *psde;
  1380. if (!plane) {
  1381. SDE_ERROR("invalid plane\n");
  1382. return;
  1383. }
  1384. psde = to_sde_plane(plane);
  1385. if (!psde->pipe_hw || !psde->pipe_hw->cap) {
  1386. SDE_ERROR("invalid pipe reference\n");
  1387. return;
  1388. }
  1389. SDE_EVT32(DRMID(plane), psde->xin_halt_forced_clk, enable);
  1390. psde->xin_halt_forced_clk =
  1391. _sde_plane_halt_requests(plane, psde->pipe_hw->cap->xin_id,
  1392. psde->xin_halt_forced_clk, enable);
  1393. }
  1394. void sde_plane_secure_ctrl_xin_client(struct drm_plane *plane,
  1395. struct drm_crtc *crtc)
  1396. {
  1397. struct sde_plane *psde;
  1398. if (!plane || !crtc) {
  1399. SDE_ERROR("invalid plane/crtc\n");
  1400. return;
  1401. }
  1402. psde = to_sde_plane(plane);
  1403. if (psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI))
  1404. return;
  1405. /* do all VBIF programming for the sec-ui allowed SSPP */
  1406. _sde_plane_set_qos_remap(plane);
  1407. _sde_plane_set_ot_limit(plane, crtc);
  1408. }
  1409. /**
  1410. * sde_plane_rot_install_properties - install plane rotator properties
  1411. * @plane: Pointer to drm plane
  1412. * @catalog: Pointer to mdss configuration
  1413. * return: none
  1414. */
  1415. static void sde_plane_rot_install_properties(struct drm_plane *plane,
  1416. struct sde_mdss_cfg *catalog)
  1417. {
  1418. struct sde_plane *psde = to_sde_plane(plane);
  1419. unsigned long supported_rotations = DRM_MODE_ROTATE_0 |
  1420. DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y;
  1421. int ret = 0;
  1422. if (!plane || !psde) {
  1423. SDE_ERROR("invalid plane\n");
  1424. return;
  1425. } else if (!catalog) {
  1426. SDE_ERROR("invalid catalog\n");
  1427. return;
  1428. }
  1429. if (psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT))
  1430. supported_rotations |= DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
  1431. DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
  1432. ret = drm_plane_create_rotation_property(plane,
  1433. DRM_MODE_ROTATE_0, supported_rotations);
  1434. if (ret) {
  1435. DRM_ERROR("create rotation property failed: %d\n", ret);
  1436. return;
  1437. }
  1438. }
  1439. void sde_plane_clear_multirect(const struct drm_plane_state *drm_state)
  1440. {
  1441. struct sde_plane_state *pstate;
  1442. if (!drm_state)
  1443. return;
  1444. pstate = to_sde_plane_state(drm_state);
  1445. pstate->multirect_index = SDE_SSPP_RECT_SOLO;
  1446. pstate->multirect_mode = SDE_SSPP_MULTIRECT_NONE;
  1447. }
  1448. /**
  1449. * multi_rect validate API allows to validate only R0 and R1 RECT
  1450. * passing for each plane. Client of this API must not pass multiple
  1451. * plane which are not sharing same XIN client. Such calls will fail
  1452. * even though kernel client is passing valid multirect configuration.
  1453. */
  1454. int sde_plane_validate_multirect_v2(struct sde_multirect_plane_states *plane)
  1455. {
  1456. struct sde_plane_state *pstate[R_MAX];
  1457. const struct drm_plane_state *drm_state[R_MAX];
  1458. struct sde_rect src[R_MAX], dst[R_MAX];
  1459. struct sde_plane *sde_plane[R_MAX];
  1460. const struct sde_format *fmt[R_MAX];
  1461. int xin_id[R_MAX];
  1462. bool q16_data = true;
  1463. int i, j, buffer_lines, width_threshold[R_MAX];
  1464. unsigned int max_tile_height = 1;
  1465. bool parallel_fetch_qualified = true;
  1466. enum sde_sspp_multirect_mode mode = SDE_SSPP_MULTIRECT_NONE;
  1467. const struct msm_format *msm_fmt;
  1468. bool const_alpha_enable = true;
  1469. for (i = 0; i < R_MAX; i++) {
  1470. drm_state[i] = i ? plane->r1 : plane->r0;
  1471. if (!drm_state[i]) {
  1472. SDE_ERROR("drm plane state is NULL\n");
  1473. return -EINVAL;
  1474. }
  1475. pstate[i] = to_sde_plane_state(drm_state[i]);
  1476. sde_plane[i] = to_sde_plane(drm_state[i]->plane);
  1477. xin_id[i] = sde_plane[i]->pipe_hw->cap->xin_id;
  1478. for (j = 0; j < i; j++) {
  1479. if (xin_id[i] != xin_id[j]) {
  1480. SDE_ERROR_PLANE(sde_plane[i],
  1481. "invalid multirect validate call base:%d xin_id:%d curr:%d xin:%d\n",
  1482. j, xin_id[j], i, xin_id[i]);
  1483. return -EINVAL;
  1484. }
  1485. }
  1486. msm_fmt = msm_framebuffer_format(drm_state[i]->fb);
  1487. if (!msm_fmt) {
  1488. SDE_ERROR_PLANE(sde_plane[i], "null fb\n");
  1489. return -EINVAL;
  1490. }
  1491. fmt[i] = to_sde_format(msm_fmt);
  1492. if (SDE_FORMAT_IS_UBWC(fmt[i]) &&
  1493. (fmt[i]->tile_height > max_tile_height))
  1494. max_tile_height = fmt[i]->tile_height;
  1495. POPULATE_RECT(&src[i], drm_state[i]->src_x, drm_state[i]->src_y,
  1496. drm_state[i]->src_w, drm_state[i]->src_h, q16_data);
  1497. POPULATE_RECT(&dst[i], drm_state[i]->crtc_x,
  1498. drm_state[i]->crtc_y, drm_state[i]->crtc_w,
  1499. drm_state[i]->crtc_h, !q16_data);
  1500. if (src[i].w != dst[i].w || src[i].h != dst[i].h) {
  1501. SDE_ERROR_PLANE(sde_plane[i],
  1502. "scaling is not supported in multirect mode\n");
  1503. return -EINVAL;
  1504. }
  1505. if (pstate[i]->rotation & DRM_MODE_ROTATE_90) {
  1506. SDE_ERROR_PLANE(sde_plane[i],
  1507. "inline rotation is not supported in mulirect mode\n");
  1508. return -EINVAL;
  1509. }
  1510. if (SDE_FORMAT_IS_YUV(fmt[i])) {
  1511. SDE_ERROR_PLANE(sde_plane[i],
  1512. "Unsupported format for multirect mode\n");
  1513. return -EINVAL;
  1514. }
  1515. /**
  1516. * SSPP PD_MEM is split half - one for each RECT.
  1517. * Tiled formats need 5 lines of buffering while fetching
  1518. * whereas linear formats need only 2 lines.
  1519. * So we cannot support more than half of the supported SSPP
  1520. * width for tiled formats.
  1521. */
  1522. width_threshold[i] = sde_plane[i]->pipe_sblk->maxlinewidth;
  1523. if (SDE_FORMAT_IS_UBWC(fmt[i]))
  1524. width_threshold[i] /= 2;
  1525. if (parallel_fetch_qualified && src[i].w > width_threshold[i])
  1526. parallel_fetch_qualified = false;
  1527. if (sde_plane[i]->is_virtual)
  1528. mode = sde_plane_get_property(pstate[i],
  1529. PLANE_PROP_MULTIRECT_MODE);
  1530. if (pstate[i]->const_alpha_en != const_alpha_enable)
  1531. const_alpha_enable = false;
  1532. }
  1533. buffer_lines = 2 * max_tile_height;
  1534. /**
  1535. * fallback to driver mode selection logic if client is using
  1536. * multirect plane without setting property.
  1537. *
  1538. * validate multirect mode configuration based on rectangle
  1539. */
  1540. switch (mode) {
  1541. case SDE_SSPP_MULTIRECT_NONE:
  1542. if (parallel_fetch_qualified)
  1543. mode = SDE_SSPP_MULTIRECT_PARALLEL;
  1544. else if (TIME_MULTIPLEX_RECT(dst[R1], dst[R0], buffer_lines) ||
  1545. TIME_MULTIPLEX_RECT(dst[R0], dst[R1], buffer_lines))
  1546. mode = SDE_SSPP_MULTIRECT_TIME_MX;
  1547. else
  1548. SDE_ERROR(
  1549. "planes(%d - %d) multirect mode selection fail\n",
  1550. drm_state[R0]->plane->base.id,
  1551. drm_state[R1]->plane->base.id);
  1552. break;
  1553. case SDE_SSPP_MULTIRECT_PARALLEL:
  1554. if (!parallel_fetch_qualified) {
  1555. SDE_ERROR("R0 plane:%d width_threshold:%d src_w:%d\n",
  1556. drm_state[R0]->plane->base.id,
  1557. width_threshold[R0], src[R0].w);
  1558. SDE_ERROR("R1 plane:%d width_threshold:%d src_w:%d\n",
  1559. drm_state[R1]->plane->base.id,
  1560. width_threshold[R1], src[R1].w);
  1561. SDE_ERROR("parallel fetch not qualified\n");
  1562. mode = SDE_SSPP_MULTIRECT_NONE;
  1563. }
  1564. break;
  1565. case SDE_SSPP_MULTIRECT_TIME_MX:
  1566. if (!TIME_MULTIPLEX_RECT(dst[R1], dst[R0], buffer_lines) &&
  1567. !TIME_MULTIPLEX_RECT(dst[R0], dst[R1], buffer_lines)) {
  1568. SDE_ERROR(
  1569. "buffer_lines:%d R0 plane:%d dst_y:%d dst_h:%d\n",
  1570. buffer_lines, drm_state[R0]->plane->base.id,
  1571. dst[R0].y, dst[R0].h);
  1572. SDE_ERROR(
  1573. "buffer_lines:%d R1 plane:%d dst_y:%d dst_h:%d\n",
  1574. buffer_lines, drm_state[R1]->plane->base.id,
  1575. dst[R1].y, dst[R1].h);
  1576. SDE_ERROR("time multiplexed fetch not qualified\n");
  1577. mode = SDE_SSPP_MULTIRECT_NONE;
  1578. }
  1579. break;
  1580. default:
  1581. SDE_ERROR("bad mode:%d selection\n", mode);
  1582. mode = SDE_SSPP_MULTIRECT_NONE;
  1583. break;
  1584. }
  1585. for (i = 0; i < R_MAX; i++) {
  1586. pstate[i]->multirect_mode = mode;
  1587. pstate[i]->const_alpha_en = const_alpha_enable;
  1588. }
  1589. if (mode == SDE_SSPP_MULTIRECT_NONE)
  1590. return -EINVAL;
  1591. if (sde_plane[R0]->is_virtual) {
  1592. pstate[R0]->multirect_index = SDE_SSPP_RECT_1;
  1593. pstate[R1]->multirect_index = SDE_SSPP_RECT_0;
  1594. } else {
  1595. pstate[R0]->multirect_index = SDE_SSPP_RECT_0;
  1596. pstate[R1]->multirect_index = SDE_SSPP_RECT_1;
  1597. }
  1598. SDE_DEBUG_PLANE(sde_plane[R0], "R0: %d - %d\n",
  1599. pstate[R0]->multirect_mode, pstate[R0]->multirect_index);
  1600. SDE_DEBUG_PLANE(sde_plane[R1], "R1: %d - %d\n",
  1601. pstate[R1]->multirect_mode, pstate[R1]->multirect_index);
  1602. return 0;
  1603. }
  1604. /**
  1605. * sde_plane_ctl_flush - set/clear control flush bitmask for the given plane
  1606. * @plane: Pointer to drm plane structure
  1607. * @ctl: Pointer to hardware control driver
  1608. * @set: set if true else clear
  1609. */
  1610. void sde_plane_ctl_flush(struct drm_plane *plane, struct sde_hw_ctl *ctl,
  1611. bool set)
  1612. {
  1613. if (!plane || !ctl) {
  1614. SDE_ERROR("invalid parameters\n");
  1615. return;
  1616. }
  1617. if (!ctl->ops.update_bitmask_sspp) {
  1618. SDE_ERROR("invalid ops\n");
  1619. return;
  1620. }
  1621. ctl->ops.update_bitmask_sspp(ctl, sde_plane_pipe(plane), set);
  1622. }
  1623. static int sde_plane_prepare_fb(struct drm_plane *plane,
  1624. struct drm_plane_state *new_state)
  1625. {
  1626. struct drm_framebuffer *fb = new_state->fb;
  1627. struct sde_plane *psde = to_sde_plane(plane);
  1628. struct sde_plane_state *pstate = to_sde_plane_state(new_state);
  1629. struct sde_hw_fmt_layout layout;
  1630. struct msm_gem_address_space *aspace;
  1631. int ret;
  1632. if (!fb)
  1633. return 0;
  1634. SDE_DEBUG_PLANE(psde, "FB[%u]\n", fb->base.id);
  1635. ret = _sde_plane_get_aspace(psde, pstate, &aspace);
  1636. if (ret) {
  1637. SDE_ERROR_PLANE(psde, "Failed to get aspace\n");
  1638. return ret;
  1639. }
  1640. /* cache aspace */
  1641. pstate->aspace = aspace;
  1642. /*
  1643. * when transitioning from secure to non-secure,
  1644. * plane->prepare_fb happens before the commit. In such case,
  1645. * defer the prepare_fb and handled it late, during the commit
  1646. * after attaching the domains as part of the transition
  1647. */
  1648. pstate->defer_prepare_fb = (aspace && !aspace->domain_attached) ?
  1649. true : false;
  1650. if (pstate->defer_prepare_fb) {
  1651. SDE_EVT32(DRMID(plane), psde->pipe);
  1652. SDE_DEBUG_PLANE(psde,
  1653. "domain not attached, prepare_fb handled later\n");
  1654. return 0;
  1655. }
  1656. if (pstate->aspace && fb) {
  1657. ret = msm_framebuffer_prepare(fb,
  1658. pstate->aspace);
  1659. if (ret) {
  1660. SDE_ERROR("failed to prepare framebuffer\n");
  1661. return ret;
  1662. }
  1663. }
  1664. /* validate framebuffer layout before commit */
  1665. ret = sde_format_populate_layout(pstate->aspace,
  1666. fb, &layout);
  1667. if (ret) {
  1668. SDE_ERROR_PLANE(psde, "failed to get format layout, %d\n", ret);
  1669. return ret;
  1670. }
  1671. return 0;
  1672. }
  1673. static void sde_plane_cleanup_fb(struct drm_plane *plane,
  1674. struct drm_plane_state *old_state)
  1675. {
  1676. struct sde_plane *psde = to_sde_plane(plane);
  1677. struct sde_plane_state *old_pstate;
  1678. if (!old_state || !old_state->fb || !plane)
  1679. return;
  1680. old_pstate = to_sde_plane_state(old_state);
  1681. SDE_DEBUG_PLANE(psde, "FB[%u]\n", old_state->fb->base.id);
  1682. msm_framebuffer_cleanup(old_state->fb, old_pstate->aspace);
  1683. }
  1684. static void _sde_plane_sspp_atomic_check_mode_changed(struct sde_plane *psde,
  1685. struct drm_plane_state *state,
  1686. struct drm_plane_state *old_state)
  1687. {
  1688. struct sde_plane_state *pstate = to_sde_plane_state(state);
  1689. struct sde_plane_state *old_pstate = to_sde_plane_state(old_state);
  1690. struct drm_framebuffer *fb, *old_fb;
  1691. /* no need to check it again */
  1692. if (pstate->dirty == SDE_PLANE_DIRTY_ALL)
  1693. return;
  1694. if (!sde_plane_enabled(state) || !sde_plane_enabled(old_state)
  1695. || psde->is_error) {
  1696. SDE_DEBUG_PLANE(psde,
  1697. "enabling/disabling full modeset required\n");
  1698. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1699. } else if (to_sde_plane_state(old_state)->pending) {
  1700. SDE_DEBUG_PLANE(psde, "still pending\n");
  1701. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1702. } else if (pstate->multirect_index != old_pstate->multirect_index ||
  1703. pstate->multirect_mode != old_pstate->multirect_mode) {
  1704. SDE_DEBUG_PLANE(psde, "multirect config updated\n");
  1705. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1706. } else if (state->src_w != old_state->src_w ||
  1707. state->src_h != old_state->src_h ||
  1708. state->src_x != old_state->src_x ||
  1709. state->src_y != old_state->src_y) {
  1710. SDE_DEBUG_PLANE(psde, "src rect updated\n");
  1711. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1712. } else if (state->crtc_w != old_state->crtc_w ||
  1713. state->crtc_h != old_state->crtc_h ||
  1714. state->crtc_x != old_state->crtc_x ||
  1715. state->crtc_y != old_state->crtc_y) {
  1716. SDE_DEBUG_PLANE(psde, "crtc rect updated\n");
  1717. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1718. } else if (pstate->excl_rect.w != old_pstate->excl_rect.w ||
  1719. pstate->excl_rect.h != old_pstate->excl_rect.h ||
  1720. pstate->excl_rect.x != old_pstate->excl_rect.x ||
  1721. pstate->excl_rect.y != old_pstate->excl_rect.y) {
  1722. SDE_DEBUG_PLANE(psde, "excl_rect updated\n");
  1723. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1724. } else if (pstate->rotation != old_pstate->rotation) {
  1725. SDE_DEBUG_PLANE(psde, "rotation updated 0x%x->0x%x\n",
  1726. pstate->rotation, old_pstate->rotation);
  1727. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT;
  1728. }
  1729. fb = state->fb;
  1730. old_fb = old_state->fb;
  1731. if (!fb || !old_fb) {
  1732. SDE_DEBUG_PLANE(psde, "can't compare fb handles\n");
  1733. } else if ((fb->format->format != old_fb->format->format) ||
  1734. pstate->const_alpha_en != old_pstate->const_alpha_en) {
  1735. SDE_DEBUG_PLANE(psde, "format change\n");
  1736. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT | SDE_PLANE_DIRTY_RECTS;
  1737. } else {
  1738. uint64_t new_mod = fb->modifier;
  1739. uint64_t old_mod = old_fb->modifier;
  1740. uint32_t *new_pitches = fb->pitches;
  1741. uint32_t *old_pitches = old_fb->pitches;
  1742. uint32_t *new_offset = fb->offsets;
  1743. uint32_t *old_offset = old_fb->offsets;
  1744. int i;
  1745. if (new_mod != old_mod) {
  1746. SDE_DEBUG_PLANE(psde,
  1747. "format modifiers change new_mode:%llu old_mode:%llu\n",
  1748. new_mod, old_mod);
  1749. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
  1750. SDE_PLANE_DIRTY_RECTS;
  1751. }
  1752. for (i = 0; i < ARRAY_SIZE(fb->pitches); i++) {
  1753. if (new_pitches[i] != old_pitches[i]) {
  1754. SDE_DEBUG_PLANE(psde,
  1755. "pitches change plane:%d old_pitches:%u new_pitches:%u\n",
  1756. i, old_pitches[i], new_pitches[i]);
  1757. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1758. break;
  1759. }
  1760. }
  1761. for (i = 0; i < ARRAY_SIZE(fb->offsets); i++) {
  1762. if (new_offset[i] != old_offset[i]) {
  1763. SDE_DEBUG_PLANE(psde,
  1764. "offset change plane:%d old_offset:%u new_offset:%u\n",
  1765. i, old_offset[i], new_offset[i]);
  1766. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
  1767. SDE_PLANE_DIRTY_RECTS;
  1768. break;
  1769. }
  1770. }
  1771. }
  1772. }
  1773. int sde_plane_validate_src_addr(struct drm_plane *plane,
  1774. unsigned long base_addr, u32 size)
  1775. {
  1776. int ret = -EINVAL;
  1777. u32 addr;
  1778. struct sde_plane *psde = to_sde_plane(plane);
  1779. if (!psde || !base_addr || !size) {
  1780. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  1781. return ret;
  1782. }
  1783. if (psde->pipe_hw && psde->pipe_hw->ops.get_sourceaddress) {
  1784. addr = psde->pipe_hw->ops.get_sourceaddress(psde->pipe_hw,
  1785. is_sde_plane_virtual(plane));
  1786. if ((addr >= base_addr) && (addr < (base_addr + size)))
  1787. ret = 0;
  1788. }
  1789. return ret;
  1790. }
  1791. static inline bool _sde_plane_is_pre_downscale_enabled(
  1792. struct sde_hw_inline_pre_downscale_cfg *pre_down)
  1793. {
  1794. return pre_down->pre_downscale_x_0 || pre_down->pre_downscale_y_0;
  1795. }
  1796. static int _sde_plane_validate_scaler_v2(struct sde_plane *psde,
  1797. struct sde_plane_state *pstate,
  1798. const struct sde_format *fmt,
  1799. uint32_t img_w, uint32_t img_h,
  1800. uint32_t src_w, uint32_t src_h,
  1801. uint32_t deci_w, uint32_t deci_h)
  1802. {
  1803. struct sde_hw_inline_pre_downscale_cfg *pd_cfg;
  1804. bool pre_down_en;
  1805. int i;
  1806. if (!psde || !pstate || !fmt) {
  1807. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  1808. return -EINVAL;
  1809. }
  1810. if (psde->debugfs_default_scale ||
  1811. (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2 &&
  1812. pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2_CHECK))
  1813. return 0;
  1814. pd_cfg = &pstate->pre_down;
  1815. pre_down_en = _sde_plane_is_pre_downscale_enabled(pd_cfg);
  1816. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_INVALID;
  1817. for (i = 0; i < SDE_MAX_PLANES; i++) {
  1818. uint32_t hor_req_pixels, hor_fetch_pixels;
  1819. uint32_t vert_req_pixels, vert_fetch_pixels;
  1820. uint32_t src_w_tmp, src_h_tmp;
  1821. uint32_t scaler_w, scaler_h;
  1822. uint32_t pre_down_ratio_x = 1, pre_down_ratio_y = 1;
  1823. bool rot;
  1824. /* re-use color plane 1's config for plane 2 */
  1825. if (i == 2)
  1826. continue;
  1827. if (pre_down_en) {
  1828. if (i == 0 && pd_cfg->pre_downscale_x_0)
  1829. pre_down_ratio_x = pd_cfg->pre_downscale_x_0;
  1830. if (i == 0 && pd_cfg->pre_downscale_y_0)
  1831. pre_down_ratio_y = pd_cfg->pre_downscale_y_0;
  1832. if ((i == 1 || i == 2) && pd_cfg->pre_downscale_x_1)
  1833. pre_down_ratio_x = pd_cfg->pre_downscale_x_1;
  1834. if ((i == 1 || i == 2) && pd_cfg->pre_downscale_y_1)
  1835. pre_down_ratio_y = pd_cfg->pre_downscale_y_1;
  1836. SDE_DEBUG_PLANE(psde, "pre_down[%d]: x:%d, y:%d\n",
  1837. i, pre_down_ratio_x, pre_down_ratio_y);
  1838. }
  1839. src_w_tmp = src_w;
  1840. src_h_tmp = src_h;
  1841. /*
  1842. * For chroma plane, width is half for the following sub sampled
  1843. * formats. Except in case of decimation, where hardware avoids
  1844. * 1 line of decimation instead of downsampling.
  1845. */
  1846. if (i == 1) {
  1847. if (!deci_w &&
  1848. (fmt->chroma_sample == SDE_CHROMA_420 ||
  1849. fmt->chroma_sample == SDE_CHROMA_H2V1))
  1850. src_w_tmp >>= 1;
  1851. if (!deci_h &&
  1852. (fmt->chroma_sample == SDE_CHROMA_420 ||
  1853. fmt->chroma_sample == SDE_CHROMA_H1V2))
  1854. src_h_tmp >>= 1;
  1855. }
  1856. hor_req_pixels = pstate->pixel_ext.roi_w[i];
  1857. vert_req_pixels = pstate->pixel_ext.roi_h[i];
  1858. hor_fetch_pixels = DECIMATED_DIMENSION(src_w_tmp +
  1859. (int8_t)(pstate->pixel_ext.left_ftch[i] & 0xFF) +
  1860. (int8_t)(pstate->pixel_ext.right_ftch[i] & 0xFF),
  1861. deci_w);
  1862. vert_fetch_pixels = DECIMATED_DIMENSION(src_h_tmp +
  1863. (int8_t)(pstate->pixel_ext.top_ftch[i] & 0xFF) +
  1864. (int8_t)(pstate->pixel_ext.btm_ftch[i] & 0xFF),
  1865. deci_h);
  1866. if ((hor_req_pixels != hor_fetch_pixels) ||
  1867. (hor_fetch_pixels > img_w) ||
  1868. (vert_req_pixels != vert_fetch_pixels) ||
  1869. (vert_fetch_pixels > img_h)) {
  1870. SDE_ERROR_PLANE(psde,
  1871. "req %d/%d, fetch %d/%d, src %dx%d\n",
  1872. hor_req_pixels, vert_req_pixels,
  1873. hor_fetch_pixels, vert_fetch_pixels,
  1874. img_w, img_h);
  1875. return -EINVAL;
  1876. }
  1877. /*
  1878. * swap the scaler src width & height for inline-rotation 90
  1879. * comparison with Pixel-Extension, as PE is based on
  1880. * pre-rotation and QSEED is based on post-rotation
  1881. */
  1882. rot = pstate->rotation & DRM_MODE_ROTATE_90;
  1883. scaler_w = rot ? pstate->scaler3_cfg.src_height[i]
  1884. : pstate->scaler3_cfg.src_width[i];
  1885. scaler_h = rot ? pstate->scaler3_cfg.src_width[i]
  1886. : pstate->scaler3_cfg.src_height[i];
  1887. /*
  1888. * Alpha plane can only be scaled using bilinear or pixel
  1889. * repeat/drop, src_width and src_height are only specified
  1890. * for Y and UV plane
  1891. */
  1892. if (i != 3 && (hor_req_pixels / pre_down_ratio_x != scaler_w ||
  1893. vert_req_pixels / pre_down_ratio_y !=
  1894. scaler_h)) {
  1895. SDE_ERROR_PLANE(psde,
  1896. "roi[%d] roi:%dx%d scaler:%dx%d src:%dx%d rot:%d pd:%d/%d\n",
  1897. i, pstate->pixel_ext.roi_w[i],
  1898. pstate->pixel_ext.roi_h[i], scaler_w, scaler_h,
  1899. src_w, src_h, rot, pre_down_ratio_x, pre_down_ratio_y);
  1900. return -EINVAL;
  1901. }
  1902. /*
  1903. * SSPP fetch , unpack output and QSEED3 input lines need
  1904. * to match for Y plane
  1905. */
  1906. if (i == 0 &&
  1907. (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) &
  1908. BIT(SDE_DRM_DEINTERLACE)) &&
  1909. ((pstate->scaler3_cfg.src_height[i] != (src_h/2)) ||
  1910. (pstate->pixel_ext.roi_h[i] != (src_h/2)))) {
  1911. SDE_ERROR_PLANE(psde,
  1912. "de-interlace fail roi[%d] %d/%d, src %dx%d, src %dx%d\n",
  1913. i, pstate->pixel_ext.roi_w[i],
  1914. pstate->pixel_ext.roi_h[i],
  1915. pstate->scaler3_cfg.src_width[i],
  1916. pstate->scaler3_cfg.src_height[i],
  1917. src_w, src_h);
  1918. return -EINVAL;
  1919. }
  1920. }
  1921. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V2;
  1922. return 0;
  1923. }
  1924. static inline bool _sde_plane_has_pre_downscale(struct sde_plane *psde)
  1925. {
  1926. return (psde->features & BIT(SDE_SSPP_PREDOWNSCALE));
  1927. }
  1928. static int _sde_atomic_check_pre_downscale(struct sde_plane *psde,
  1929. struct sde_plane_state *pstate, struct sde_rect *dst,
  1930. u32 src_w, u32 src_h)
  1931. {
  1932. int ret = 0;
  1933. u32 min_ratio_numer, min_ratio_denom;
  1934. struct sde_hw_inline_pre_downscale_cfg *pd_cfg = &pstate->pre_down;
  1935. bool pd_x;
  1936. bool pd_y;
  1937. if (!_sde_plane_is_pre_downscale_enabled(pd_cfg))
  1938. return ret;
  1939. pd_x = pd_cfg->pre_downscale_x_0 > 1;
  1940. pd_y = pd_cfg->pre_downscale_y_0 > 1;
  1941. min_ratio_numer = psde->pipe_sblk->in_rot_maxdwnscale_rt_nopd_num;
  1942. min_ratio_denom = psde->pipe_sblk->in_rot_maxdwnscale_rt_nopd_denom;
  1943. if (pd_x && !_sde_plane_has_pre_downscale(psde)) {
  1944. SDE_ERROR_PLANE(psde,
  1945. "hw does not support pre-downscale X: 0x%x\n",
  1946. psde->features);
  1947. ret = -EINVAL;
  1948. } else if (pd_y && !(psde->features & BIT(SDE_SSPP_PREDOWNSCALE_Y))) {
  1949. SDE_ERROR_PLANE(psde,
  1950. "hw does not support pre-downscale Y: 0x%x\n",
  1951. psde->features);
  1952. ret = -EINVAL;
  1953. } else if (!min_ratio_numer || !min_ratio_denom) {
  1954. SDE_ERROR_PLANE(psde,
  1955. "min downscale ratio not set! %u / %u\n",
  1956. min_ratio_numer, min_ratio_denom);
  1957. ret = -EINVAL;
  1958. /* compare pre-rotated src w/h with post-rotated dst h/w resp. */
  1959. } else if (pd_x && (src_w < mult_frac(dst->h, min_ratio_numer,
  1960. min_ratio_denom))) {
  1961. SDE_ERROR_PLANE(psde,
  1962. "failed min downscale-x check %u->%u, %u/%u\n",
  1963. src_w, dst->h, min_ratio_numer, min_ratio_denom);
  1964. ret = -EINVAL;
  1965. } else if (pd_y && (src_h < mult_frac(dst->w, min_ratio_numer,
  1966. min_ratio_denom))) {
  1967. SDE_ERROR_PLANE(psde,
  1968. "failed min downscale-y check %u->%u, %u/%u\n",
  1969. src_h, dst->w, min_ratio_numer, min_ratio_denom);
  1970. ret = -EINVAL;
  1971. }
  1972. return ret;
  1973. }
  1974. static void _sde_plane_get_max_downscale_limits(struct sde_plane *psde,
  1975. struct sde_plane_state *pstate, bool rt_client, u32 dst_h,
  1976. u32 src_h, u32 *max_numer_w, u32 *max_denom_w,
  1977. u32 *max_numer_h, u32 *max_denom_h)
  1978. {
  1979. bool rotated, has_predown, default_scale;
  1980. const struct sde_sspp_sub_blks *sblk;
  1981. struct sde_hw_inline_pre_downscale_cfg *pd;
  1982. rotated = pstate->rotation & DRM_MODE_ROTATE_90;
  1983. sblk = psde->pipe_sblk;
  1984. *max_numer_w = sblk->maxdwnscale;
  1985. *max_denom_w = 1;
  1986. *max_numer_h = sblk->maxdwnscale;
  1987. *max_denom_h = 1;
  1988. has_predown = _sde_plane_has_pre_downscale(psde);
  1989. if (has_predown)
  1990. pd = &pstate->pre_down;
  1991. default_scale = psde->debugfs_default_scale ||
  1992. (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2 &&
  1993. pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2_CHECK);
  1994. /**
  1995. * Inline rotation has different max vertical downscaling limits since
  1996. * the source-width becomes the scaler's pre-downscaled source-height.
  1997. **/
  1998. if (rotated) {
  1999. if (rt_client && has_predown) {
  2000. if (default_scale)
  2001. pd->pre_downscale_x_0 = (src_h >
  2002. mult_frac(dst_h, 11, 5)) ? 2 : 0;
  2003. *max_numer_h = pd->pre_downscale_x_0 ?
  2004. sblk->in_rot_maxdwnscale_rt_num :
  2005. sblk->in_rot_maxdwnscale_rt_nopd_num;
  2006. *max_denom_h = pd->pre_downscale_x_0 ?
  2007. sblk->in_rot_maxdwnscale_rt_denom :
  2008. sblk->in_rot_maxdwnscale_rt_nopd_denom;
  2009. } else if (rt_client) {
  2010. *max_numer_h = sblk->in_rot_maxdwnscale_rt_num;
  2011. *max_denom_h = sblk->in_rot_maxdwnscale_rt_denom;
  2012. } else {
  2013. *max_numer_h = sblk->in_rot_maxdwnscale_nrt;
  2014. }
  2015. }
  2016. }
  2017. static int _sde_atomic_check_decimation_scaler(struct drm_plane_state *state,
  2018. struct sde_plane *psde, const struct sde_format *fmt,
  2019. struct sde_plane_state *pstate, struct sde_rect *src,
  2020. struct sde_rect *dst, u32 width, u32 height)
  2021. {
  2022. int ret = 0;
  2023. uint32_t deci_w, deci_h, src_deci_w, src_deci_h;
  2024. uint32_t scaler_src_w, scaler_src_h;
  2025. uint32_t max_downscale_num_w, max_downscale_denom_w;
  2026. uint32_t max_downscale_num_h, max_downscale_denom_h;
  2027. uint32_t max_upscale, max_linewidth;
  2028. bool inline_rotation, rt_client;
  2029. struct drm_crtc *crtc;
  2030. struct drm_crtc_state *new_cstate;
  2031. const struct sde_sspp_sub_blks *sblk;
  2032. if (!state || !state->state || !state->crtc) {
  2033. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  2034. return -EINVAL;
  2035. }
  2036. deci_w = sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
  2037. deci_h = sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
  2038. src_deci_w = DECIMATED_DIMENSION(src->w, deci_w);
  2039. src_deci_h = DECIMATED_DIMENSION(src->h, deci_h);
  2040. /* with inline rotator, the source of the scaler is post-rotated */
  2041. inline_rotation = pstate->rotation & DRM_MODE_ROTATE_90 ? true : false;
  2042. if (inline_rotation) {
  2043. scaler_src_w = src_deci_h;
  2044. scaler_src_h = src_deci_w;
  2045. } else {
  2046. scaler_src_w = src_deci_w;
  2047. scaler_src_h = src_deci_h;
  2048. }
  2049. sblk = psde->pipe_sblk;
  2050. max_upscale = sblk->maxupscale;
  2051. if (inline_rotation)
  2052. max_linewidth = sblk->in_rot_maxheight;
  2053. else if (scaler_src_w != state->crtc_w || scaler_src_h != state->crtc_h)
  2054. max_linewidth = sblk->scaling_linewidth;
  2055. else
  2056. max_linewidth = sblk->maxlinewidth;
  2057. crtc = state->crtc;
  2058. new_cstate = drm_atomic_get_new_crtc_state(state->state, crtc);
  2059. rt_client = sde_crtc_is_rt_client(crtc, new_cstate);
  2060. _sde_plane_get_max_downscale_limits(psde, pstate, rt_client, dst->h,
  2061. scaler_src_h, &max_downscale_num_w, &max_downscale_denom_w,
  2062. &max_downscale_num_h, &max_downscale_denom_h);
  2063. /* decimation validation */
  2064. if ((deci_w || deci_h)
  2065. && ((deci_w > sblk->maxhdeciexp)
  2066. || (deci_h > sblk->maxvdeciexp))) {
  2067. SDE_ERROR_PLANE(psde, "too much decimation requested\n");
  2068. ret = -EINVAL;
  2069. } else if ((deci_w || deci_h)
  2070. && (fmt->fetch_mode != SDE_FETCH_LINEAR)) {
  2071. SDE_ERROR_PLANE(psde, "decimation requires linear fetch\n");
  2072. ret = -EINVAL;
  2073. } else if (!(psde->features & SDE_SSPP_SCALER) &&
  2074. ((src->w != dst->w) || (src->h != dst->h))) {
  2075. SDE_ERROR_PLANE(psde,
  2076. "pipe doesn't support scaling %ux%u->%ux%u\n",
  2077. src->w, src->h, dst->w, dst->h);
  2078. ret = -EINVAL;
  2079. /* check scaler source width */
  2080. } else if (scaler_src_w > max_linewidth) {
  2081. SDE_ERROR_PLANE(psde,
  2082. "invalid src w:%u, scaler w:%u, line w:%u, rot: %d\n",
  2083. src->w, scaler_src_w, max_linewidth, inline_rotation);
  2084. ret = -E2BIG;
  2085. /* check max scaler capability */
  2086. } else if (((scaler_src_w * max_upscale) < dst->w) ||
  2087. ((scaler_src_h * max_upscale) < dst->h) ||
  2088. (mult_frac(dst->w, max_downscale_num_w, max_downscale_denom_w)
  2089. < scaler_src_w) ||
  2090. (mult_frac(dst->h, max_downscale_num_h, max_downscale_denom_h)
  2091. < scaler_src_h)) {
  2092. SDE_ERROR_PLANE(psde,
  2093. "too much scaling %ux%u->%ux%u rot:%d dwn:%d/%d %d/%d\n",
  2094. scaler_src_w, scaler_src_h, dst->w, dst->h,
  2095. inline_rotation, max_downscale_num_w,
  2096. max_downscale_denom_w, max_downscale_num_h,
  2097. max_downscale_denom_h);
  2098. ret = -E2BIG;
  2099. /* check inline pre-downscale support */
  2100. } else if (inline_rotation && _sde_atomic_check_pre_downscale(psde,
  2101. pstate, dst, src_deci_w, src_deci_h)) {
  2102. ret = -EINVAL;
  2103. /* QSEED validation */
  2104. } else if (_sde_plane_validate_scaler_v2(psde, pstate, fmt,
  2105. width, height, src->w, src->h,
  2106. deci_w, deci_h)) {
  2107. ret = -EINVAL;
  2108. }
  2109. return ret;
  2110. }
  2111. static int _sde_atomic_check_excl_rect(struct sde_plane *psde,
  2112. struct sde_plane_state *pstate, struct sde_rect *src,
  2113. const struct sde_format *fmt, int ret)
  2114. {
  2115. /* check excl rect configs */
  2116. if (!ret && pstate->excl_rect.w && pstate->excl_rect.h) {
  2117. struct sde_rect intersect;
  2118. /*
  2119. * Check exclusion rect against src rect.
  2120. * it must intersect with source rect.
  2121. */
  2122. sde_kms_rect_intersect(src, &pstate->excl_rect, &intersect);
  2123. if (intersect.w != pstate->excl_rect.w ||
  2124. intersect.h != pstate->excl_rect.h ||
  2125. SDE_FORMAT_IS_YUV(fmt)) {
  2126. SDE_ERROR_PLANE(psde,
  2127. "invalid excl_rect:{%d,%d,%d,%d} src:{%d,%d,%d,%d}, fmt: %4.4s\n",
  2128. pstate->excl_rect.x, pstate->excl_rect.y,
  2129. pstate->excl_rect.w, pstate->excl_rect.h,
  2130. src->x, src->y, src->w, src->h,
  2131. (char *)&fmt->base.pixel_format);
  2132. ret = -EINVAL;
  2133. }
  2134. SDE_DEBUG_PLANE(psde, "excl_rect: {%d,%d,%d,%d}\n",
  2135. pstate->excl_rect.x, pstate->excl_rect.y,
  2136. pstate->excl_rect.w, pstate->excl_rect.h);
  2137. }
  2138. return ret;
  2139. }
  2140. static int _sde_plane_validate_shared_crtc(struct sde_plane *psde,
  2141. struct drm_plane_state *state)
  2142. {
  2143. struct sde_kms *sde_kms;
  2144. struct sde_splash_display *splash_display;
  2145. int i, j;
  2146. sde_kms = _sde_plane_get_kms(&psde->base);
  2147. if (!sde_kms || !state->crtc)
  2148. return 0;
  2149. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  2150. splash_display = &sde_kms->splash_data.splash_display[i];
  2151. if (splash_display && splash_display->cont_splash_enabled &&
  2152. splash_display->encoder &&
  2153. state->crtc != splash_display->encoder->crtc) {
  2154. for (j = 0; j < MAX_DATA_PATH_PER_DSIPLAY; j++) {
  2155. if (splash_display->pipes[j].sspp ==
  2156. psde->pipe) {
  2157. SDE_ERROR_PLANE(psde,
  2158. "pipe:%d used in cont-splash on crtc:%d\n",
  2159. psde->pipe,
  2160. splash_display->encoder->crtc->base.id);
  2161. return -EINVAL;
  2162. }
  2163. }
  2164. }
  2165. }
  2166. return 0;
  2167. }
  2168. static int _sde_plane_sspp_atomic_check_helper(struct sde_plane *psde,
  2169. const struct sde_format *fmt,
  2170. struct sde_rect src, struct sde_rect dst,
  2171. u32 width, u32 height)
  2172. {
  2173. int ret = 0;
  2174. u32 min_src_size = SDE_FORMAT_IS_YUV(fmt) ? 2 : 1;
  2175. if (SDE_FORMAT_IS_YUV(fmt) &&
  2176. (!(psde->features & SDE_SSPP_SCALER) ||
  2177. !(psde->features & (BIT(SDE_SSPP_CSC)
  2178. | BIT(SDE_SSPP_CSC_10BIT))))) {
  2179. SDE_ERROR_PLANE(psde,
  2180. "plane doesn't have scaler/csc for yuv\n");
  2181. ret = -EINVAL;
  2182. /* check src bounds */
  2183. } else if (width > MAX_IMG_WIDTH || height > MAX_IMG_HEIGHT ||
  2184. src.w < min_src_size || src.h < min_src_size ||
  2185. CHECK_LAYER_BOUNDS(src.x, src.w, width) ||
  2186. CHECK_LAYER_BOUNDS(src.y, src.h, height)) {
  2187. SDE_ERROR_PLANE(psde, "invalid source %u, %u, %ux%u\n",
  2188. src.x, src.y, src.w, src.h);
  2189. ret = -E2BIG;
  2190. /* valid yuv image */
  2191. } else if (SDE_FORMAT_IS_YUV(fmt) && ((src.x & 0x1) || (src.y & 0x1) ||
  2192. (src.w & 0x1) || (src.h & 0x1))) {
  2193. SDE_ERROR_PLANE(psde, "invalid yuv source %u, %u, %ux%u\n",
  2194. src.x, src.y, src.w, src.h);
  2195. ret = -EINVAL;
  2196. /* min dst support */
  2197. } else if (dst.w < 0x1 || dst.h < 0x1) {
  2198. SDE_ERROR_PLANE(psde, "invalid dest rect %u, %u, %ux%u\n",
  2199. dst.x, dst.y, dst.w, dst.h);
  2200. ret = -EINVAL;
  2201. } else if (SDE_FORMAT_IS_UBWC(fmt) &&
  2202. !psde->catalog->ubwc_version) {
  2203. SDE_ERROR_PLANE(psde, "ubwc not supported\n");
  2204. ret = -EINVAL;
  2205. }
  2206. return ret;
  2207. }
  2208. static int sde_plane_sspp_atomic_check(struct drm_plane *plane,
  2209. struct drm_plane_state *state)
  2210. {
  2211. int ret = 0;
  2212. struct sde_plane *psde;
  2213. struct sde_plane_state *pstate;
  2214. const struct msm_format *msm_fmt;
  2215. const struct sde_format *fmt;
  2216. struct sde_rect src, dst;
  2217. bool q16_data = true;
  2218. struct drm_framebuffer *fb;
  2219. u32 width;
  2220. u32 height;
  2221. psde = to_sde_plane(plane);
  2222. pstate = to_sde_plane_state(state);
  2223. if (!psde->pipe_sblk) {
  2224. SDE_ERROR_PLANE(psde, "invalid catalog\n");
  2225. return -EINVAL;
  2226. }
  2227. /* src values are in Q16 fixed point, convert to integer */
  2228. POPULATE_RECT(&src, state->src_x, state->src_y,
  2229. state->src_w, state->src_h, q16_data);
  2230. POPULATE_RECT(&dst, state->crtc_x, state->crtc_y, state->crtc_w,
  2231. state->crtc_h, !q16_data);
  2232. SDE_DEBUG_PLANE(psde, "check %d -> %d\n",
  2233. sde_plane_enabled(plane->state), sde_plane_enabled(state));
  2234. if (!sde_plane_enabled(state))
  2235. goto modeset_update;
  2236. fb = state->fb;
  2237. width = fb ? state->fb->width : 0x0;
  2238. height = fb ? state->fb->height : 0x0;
  2239. SDE_DEBUG("plane%d sspp:%x/%dx%d/%4.4s/%llx\n",
  2240. plane->base.id,
  2241. pstate->rotation,
  2242. width, height,
  2243. fb ? (char *) &state->fb->format->format : 0x0,
  2244. fb ? state->fb->modifier : 0x0);
  2245. SDE_DEBUG("src:%dx%d %d,%d crtc:%dx%d+%d+%d\n",
  2246. state->src_w >> 16, state->src_h >> 16,
  2247. state->src_x >> 16, state->src_y >> 16,
  2248. state->crtc_w, state->crtc_h,
  2249. state->crtc_x, state->crtc_y);
  2250. msm_fmt = msm_framebuffer_format(fb);
  2251. fmt = to_sde_format(msm_fmt);
  2252. ret = _sde_plane_sspp_atomic_check_helper(psde, fmt, src, dst, width,
  2253. height);
  2254. if (ret)
  2255. return ret;
  2256. ret = _sde_atomic_check_decimation_scaler(state, psde, fmt, pstate,
  2257. &src, &dst, width, height);
  2258. if (ret)
  2259. return ret;
  2260. ret = _sde_atomic_check_excl_rect(psde, pstate,
  2261. &src, fmt, ret);
  2262. if (ret)
  2263. return ret;
  2264. ret = _sde_plane_validate_shared_crtc(psde, state);
  2265. if (ret)
  2266. return ret;
  2267. pstate->const_alpha_en = fmt->alpha_enable &&
  2268. (SDE_DRM_BLEND_OP_OPAQUE !=
  2269. sde_plane_get_property(pstate, PLANE_PROP_BLEND_OP)) &&
  2270. (pstate->stage != SDE_STAGE_0);
  2271. modeset_update:
  2272. if (!ret)
  2273. _sde_plane_sspp_atomic_check_mode_changed(psde,
  2274. state, plane->state);
  2275. return ret;
  2276. }
  2277. static int sde_plane_atomic_check(struct drm_plane *plane,
  2278. struct drm_plane_state *state)
  2279. {
  2280. int ret = 0;
  2281. struct sde_plane *psde;
  2282. struct sde_plane_state *pstate;
  2283. if (!plane || !state) {
  2284. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  2285. !plane, !state);
  2286. ret = -EINVAL;
  2287. goto exit;
  2288. }
  2289. psde = to_sde_plane(plane);
  2290. pstate = to_sde_plane_state(state);
  2291. SDE_DEBUG_PLANE(psde, "\n");
  2292. ret = sde_plane_rot_atomic_check(plane, state);
  2293. if (ret)
  2294. goto exit;
  2295. ret = sde_plane_sspp_atomic_check(plane, state);
  2296. exit:
  2297. return ret;
  2298. }
  2299. void sde_plane_flush(struct drm_plane *plane)
  2300. {
  2301. struct sde_plane *psde;
  2302. struct sde_plane_state *pstate;
  2303. if (!plane || !plane->state) {
  2304. SDE_ERROR("invalid plane\n");
  2305. return;
  2306. }
  2307. psde = to_sde_plane(plane);
  2308. pstate = to_sde_plane_state(plane->state);
  2309. /*
  2310. * These updates have to be done immediately before the plane flush
  2311. * timing, and may not be moved to the atomic_update/mode_set functions.
  2312. */
  2313. if (psde->is_error)
  2314. /* force white frame with 100% alpha pipe output on error */
  2315. _sde_plane_color_fill(psde, 0xFFFFFF, 0xFF);
  2316. else if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG)
  2317. /* force 100% alpha */
  2318. _sde_plane_color_fill(psde, psde->color_fill, 0xFF);
  2319. else if (psde->pipe_hw && psde->csc_ptr && psde->pipe_hw->ops.setup_csc)
  2320. psde->pipe_hw->ops.setup_csc(psde->pipe_hw, psde->csc_ptr);
  2321. /* flag h/w flush complete */
  2322. if (plane->state)
  2323. pstate->pending = false;
  2324. }
  2325. /**
  2326. * sde_plane_set_error: enable/disable error condition
  2327. * @plane: pointer to drm_plane structure
  2328. */
  2329. void sde_plane_set_error(struct drm_plane *plane, bool error)
  2330. {
  2331. struct sde_plane *psde;
  2332. if (!plane)
  2333. return;
  2334. psde = to_sde_plane(plane);
  2335. psde->is_error = error;
  2336. }
  2337. static void _sde_plane_sspp_setup_sys_cache(struct sde_plane *psde,
  2338. struct sde_plane_state *pstate, bool is_tp10)
  2339. {
  2340. struct sde_sc_cfg *sc_cfg = psde->catalog->sc_cfg;
  2341. if (!psde->pipe_hw->ops.setup_sys_cache ||
  2342. !(psde->perf_features & BIT(SDE_PERF_SSPP_SYS_CACHE)))
  2343. return;
  2344. SDE_DEBUG("features:0x%x rotation:0x%x\n",
  2345. psde->features, pstate->rotation);
  2346. pstate->sc_cfg.rd_en = false;
  2347. pstate->sc_cfg.rd_scid = 0x0;
  2348. pstate->sc_cfg.flags = SSPP_SYS_CACHE_EN_FLAG |
  2349. SSPP_SYS_CACHE_SCID;
  2350. pstate->sc_cfg.type = SDE_SYS_CACHE_NONE;
  2351. if (pstate->rotation & DRM_MODE_ROTATE_90) {
  2352. if (is_tp10 && sc_cfg[SDE_SYS_CACHE_ROT].has_sys_cache) {
  2353. pstate->sc_cfg.rd_en = true;
  2354. pstate->sc_cfg.rd_scid =
  2355. sc_cfg[SDE_SYS_CACHE_ROT].llcc_scid;
  2356. pstate->sc_cfg.flags = SSPP_SYS_CACHE_EN_FLAG |
  2357. SSPP_SYS_CACHE_SCID;
  2358. pstate->sc_cfg.type = SDE_SYS_CACHE_ROT;
  2359. }
  2360. } else if (pstate->static_cache_state == CACHE_STATE_FRAME_WRITE &&
  2361. sc_cfg[SDE_SYS_CACHE_DISP].has_sys_cache) {
  2362. pstate->sc_cfg.rd_en = true;
  2363. pstate->sc_cfg.rd_scid =
  2364. sc_cfg[SDE_SYS_CACHE_DISP].llcc_scid;
  2365. pstate->sc_cfg.rd_noallocate = false;
  2366. pstate->sc_cfg.flags = SSPP_SYS_CACHE_EN_FLAG |
  2367. SSPP_SYS_CACHE_SCID | SSPP_SYS_CACHE_NO_ALLOC;
  2368. pstate->sc_cfg.type = SDE_SYS_CACHE_DISP;
  2369. } else if (pstate->static_cache_state == CACHE_STATE_FRAME_READ &&
  2370. sc_cfg[SDE_SYS_CACHE_DISP].has_sys_cache) {
  2371. pstate->sc_cfg.rd_en = true;
  2372. pstate->sc_cfg.rd_scid =
  2373. sc_cfg[SDE_SYS_CACHE_DISP].llcc_scid;
  2374. pstate->sc_cfg.rd_noallocate = true;
  2375. pstate->sc_cfg.flags = SSPP_SYS_CACHE_EN_FLAG |
  2376. SSPP_SYS_CACHE_SCID | SSPP_SYS_CACHE_NO_ALLOC;
  2377. pstate->sc_cfg.type = SDE_SYS_CACHE_DISP;
  2378. }
  2379. SDE_EVT32(DRMID(&psde->base), pstate->sc_cfg.rd_scid,
  2380. pstate->sc_cfg.rd_en, pstate->sc_cfg.rd_noallocate);
  2381. psde->pipe_hw->ops.setup_sys_cache(
  2382. psde->pipe_hw, &pstate->sc_cfg);
  2383. }
  2384. void sde_plane_static_img_control(struct drm_plane *plane,
  2385. enum sde_crtc_cache_state state)
  2386. {
  2387. struct sde_plane *psde;
  2388. struct sde_plane_state *pstate;
  2389. if (!plane || !plane->state) {
  2390. SDE_ERROR("invalid plane\n");
  2391. return;
  2392. }
  2393. psde = to_sde_plane(plane);
  2394. pstate = to_sde_plane_state(plane->state);
  2395. pstate->static_cache_state = state;
  2396. if (state == CACHE_STATE_FRAME_WRITE || state == CACHE_STATE_FRAME_READ)
  2397. _sde_plane_sspp_setup_sys_cache(psde, pstate, false);
  2398. }
  2399. static void _sde_plane_map_prop_to_dirty_bits(void)
  2400. {
  2401. plane_prop_array[PLANE_PROP_SCALER_V1] =
  2402. plane_prop_array[PLANE_PROP_SCALER_V2] =
  2403. plane_prop_array[PLANE_PROP_SCALER_LUT_ED] =
  2404. plane_prop_array[PLANE_PROP_SCALER_LUT_CIR] =
  2405. plane_prop_array[PLANE_PROP_SCALER_LUT_SEP] =
  2406. plane_prop_array[PLANE_PROP_H_DECIMATE] =
  2407. plane_prop_array[PLANE_PROP_V_DECIMATE] =
  2408. plane_prop_array[PLANE_PROP_SRC_CONFIG] =
  2409. plane_prop_array[PLANE_PROP_ZPOS] =
  2410. plane_prop_array[PLANE_PROP_EXCL_RECT_V1] =
  2411. SDE_PLANE_DIRTY_RECTS;
  2412. plane_prop_array[PLANE_PROP_CSC_V1] =
  2413. plane_prop_array[PLANE_PROP_CSC_DMA_V1] =
  2414. plane_prop_array[PLANE_PROP_INVERSE_PMA] =
  2415. SDE_PLANE_DIRTY_FORMAT;
  2416. plane_prop_array[PLANE_PROP_MULTIRECT_MODE] =
  2417. plane_prop_array[PLANE_PROP_COLOR_FILL] =
  2418. SDE_PLANE_DIRTY_ALL;
  2419. /* no special action required */
  2420. plane_prop_array[PLANE_PROP_INFO] =
  2421. plane_prop_array[PLANE_PROP_ALPHA] =
  2422. plane_prop_array[PLANE_PROP_INPUT_FENCE] =
  2423. plane_prop_array[PLANE_PROP_BLEND_OP] = 0;
  2424. plane_prop_array[PLANE_PROP_FB_TRANSLATION_MODE] =
  2425. SDE_PLANE_DIRTY_FB_TRANSLATION_MODE;
  2426. plane_prop_array[PLANE_PROP_PREFILL_SIZE] =
  2427. plane_prop_array[PLANE_PROP_PREFILL_TIME] =
  2428. SDE_PLANE_DIRTY_PERF;
  2429. plane_prop_array[PLANE_PROP_VIG_GAMUT] = SDE_PLANE_DIRTY_VIG_GAMUT;
  2430. plane_prop_array[PLANE_PROP_VIG_IGC] = SDE_PLANE_DIRTY_VIG_IGC;
  2431. plane_prop_array[PLANE_PROP_DMA_IGC] = SDE_PLANE_DIRTY_DMA_IGC;
  2432. plane_prop_array[PLANE_PROP_DMA_GC] = SDE_PLANE_DIRTY_DMA_GC;
  2433. plane_prop_array[PLANE_PROP_SKIN_COLOR] =
  2434. plane_prop_array[PLANE_PROP_SKY_COLOR] =
  2435. plane_prop_array[PLANE_PROP_FOLIAGE_COLOR] =
  2436. plane_prop_array[PLANE_PROP_HUE_ADJUST] =
  2437. plane_prop_array[PLANE_PROP_SATURATION_ADJUST] =
  2438. plane_prop_array[PLANE_PROP_VALUE_ADJUST] =
  2439. plane_prop_array[PLANE_PROP_CONTRAST_ADJUST] =
  2440. SDE_PLANE_DIRTY_ALL;
  2441. }
  2442. static inline bool _sde_plane_allow_uidle(struct sde_plane *psde,
  2443. struct sde_rect *src, struct sde_rect *dst)
  2444. {
  2445. u32 max_downscale = psde->catalog->uidle_cfg.max_dwnscale;
  2446. u32 downscale = (src->h * 1000)/dst->h;
  2447. return (downscale > max_downscale) ? false : true;
  2448. }
  2449. static void _sde_plane_setup_uidle(struct drm_crtc *crtc,
  2450. struct sde_plane *psde, struct sde_plane_state *pstate,
  2451. struct sde_rect *src, struct sde_rect *dst)
  2452. {
  2453. struct sde_hw_pipe_uidle_cfg cfg;
  2454. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  2455. u32 line_time = sde_get_linetime(&crtc->mode,
  2456. sde_crtc->src_bpp, sde_crtc->target_bpp); /* nS */
  2457. u32 fal1_target_idle_time_ns =
  2458. psde->catalog->uidle_cfg.fal1_target_idle_time * 1000; /* nS */
  2459. u32 fal10_target_idle_time_ns =
  2460. psde->catalog->uidle_cfg.fal10_target_idle_time * 1000; /* nS */
  2461. u32 fal10_threshold =
  2462. psde->catalog->uidle_cfg.fal10_threshold; /* uS */
  2463. if (line_time && fal10_threshold && fal10_target_idle_time_ns &&
  2464. fal1_target_idle_time_ns) {
  2465. cfg.enable = _sde_plane_allow_uidle(psde, src, dst);
  2466. cfg.fal10_threshold = fal10_threshold;
  2467. cfg.fal10_exit_threshold = fal10_threshold + 2;
  2468. cfg.fal1_threshold = 1 +
  2469. (fal1_target_idle_time_ns*1000/line_time*2)/1000;
  2470. cfg.fal_allowed_threshold = fal10_threshold +
  2471. (fal10_target_idle_time_ns*1000/line_time*2)/1000;
  2472. } else {
  2473. SDE_ERROR("invalid settings, will disable UIDLE %d %d %d %d\n",
  2474. line_time, fal10_threshold, fal10_target_idle_time_ns,
  2475. fal1_target_idle_time_ns);
  2476. memset(&cfg, 0, sizeof(struct sde_hw_pipe_uidle_cfg));
  2477. }
  2478. SDE_DEBUG_PLANE(psde,
  2479. "tholds: fal10=%d fal10_exit=%d fal1=%d fal_allowed=%d\n",
  2480. cfg.fal10_threshold, cfg.fal10_exit_threshold,
  2481. cfg.fal1_threshold, cfg.fal_allowed_threshold);
  2482. SDE_DEBUG_PLANE(psde,
  2483. "times: line:%d fal1_idle:%d fal10_idle:%d dwnscale:%d\n",
  2484. line_time, fal1_target_idle_time_ns,
  2485. fal10_target_idle_time_ns,
  2486. psde->catalog->uidle_cfg.max_dwnscale);
  2487. SDE_EVT32_VERBOSE(cfg.enable,
  2488. cfg.fal10_threshold, cfg.fal10_exit_threshold,
  2489. cfg.fal1_threshold, cfg.fal_allowed_threshold,
  2490. psde->catalog->uidle_cfg.max_dwnscale);
  2491. psde->pipe_hw->ops.setup_uidle(
  2492. psde->pipe_hw, &cfg,
  2493. pstate->multirect_index);
  2494. }
  2495. static void _sde_plane_update_secure_session(struct sde_plane *psde,
  2496. struct sde_plane_state *pstate)
  2497. {
  2498. bool enable = false;
  2499. int mode = sde_plane_get_property(pstate,
  2500. PLANE_PROP_FB_TRANSLATION_MODE);
  2501. if ((mode == SDE_DRM_FB_SEC) ||
  2502. (mode == SDE_DRM_FB_SEC_DIR_TRANS))
  2503. enable = true;
  2504. /* update secure session flag */
  2505. psde->pipe_hw->ops.setup_secure_address(psde->pipe_hw,
  2506. pstate->multirect_index,
  2507. enable);
  2508. }
  2509. static void _sde_plane_update_roi_config(struct drm_plane *plane,
  2510. struct drm_crtc *crtc, struct drm_framebuffer *fb)
  2511. {
  2512. const struct sde_format *fmt;
  2513. const struct msm_format *msm_fmt;
  2514. struct sde_plane *psde;
  2515. struct drm_plane_state *state;
  2516. struct sde_plane_state *pstate;
  2517. struct sde_rect src, dst;
  2518. const struct sde_rect *crtc_roi;
  2519. bool q16_data = true;
  2520. int idx;
  2521. psde = to_sde_plane(plane);
  2522. state = plane->state;
  2523. pstate = to_sde_plane_state(state);
  2524. msm_fmt = msm_framebuffer_format(fb);
  2525. if (!msm_fmt) {
  2526. SDE_ERROR("crtc%d plane%d: null format\n",
  2527. DRMID(crtc), DRMID(plane));
  2528. return;
  2529. }
  2530. fmt = to_sde_format(msm_fmt);
  2531. POPULATE_RECT(&src, state->src_x, state->src_y,
  2532. state->src_w, state->src_h, q16_data);
  2533. POPULATE_RECT(&dst, state->crtc_x, state->crtc_y,
  2534. state->crtc_w, state->crtc_h, !q16_data);
  2535. SDE_DEBUG_PLANE(psde,
  2536. "FB[%u] %u,%u,%ux%u->crtc%u %d,%d,%ux%u, %4.4s ubwc %d\n",
  2537. fb->base.id, src.x, src.y, src.w, src.h,
  2538. crtc->base.id, dst.x, dst.y, dst.w, dst.h,
  2539. (char *)&fmt->base.pixel_format,
  2540. SDE_FORMAT_IS_UBWC(fmt));
  2541. if (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) &
  2542. BIT(SDE_DRM_DEINTERLACE)) {
  2543. SDE_DEBUG_PLANE(psde, "deinterlace\n");
  2544. for (idx = 0; idx < SDE_MAX_PLANES; ++idx)
  2545. psde->pipe_cfg.layout.plane_pitch[idx] <<= 1;
  2546. src.h /= 2;
  2547. src.y = DIV_ROUND_UP(src.y, 2);
  2548. src.y &= ~0x1;
  2549. }
  2550. /*
  2551. * adjust layer mixer position of the sspp in the presence
  2552. * of a partial update to the active lm origin
  2553. */
  2554. sde_crtc_get_crtc_roi(crtc->state, &crtc_roi);
  2555. dst.x -= crtc_roi->x;
  2556. dst.y -= crtc_roi->y;
  2557. /* check for UIDLE */
  2558. if (psde->pipe_hw->ops.setup_uidle)
  2559. _sde_plane_setup_uidle(crtc, psde, pstate, &src, &dst);
  2560. psde->pipe_cfg.src_rect = src;
  2561. psde->pipe_cfg.dst_rect = dst;
  2562. _sde_plane_setup_scaler(psde, pstate, fmt, false);
  2563. /* check for color fill */
  2564. psde->color_fill = (uint32_t)sde_plane_get_property(pstate,
  2565. PLANE_PROP_COLOR_FILL);
  2566. if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG) {
  2567. /* skip remaining processing on color fill */
  2568. pstate->dirty = 0x0;
  2569. } else if (psde->pipe_hw->ops.setup_rects) {
  2570. psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
  2571. &psde->pipe_cfg,
  2572. pstate->multirect_index);
  2573. }
  2574. if (psde->pipe_hw->ops.setup_pe &&
  2575. (pstate->multirect_index != SDE_SSPP_RECT_1))
  2576. psde->pipe_hw->ops.setup_pe(psde->pipe_hw,
  2577. &pstate->pixel_ext);
  2578. /**
  2579. * when programmed in multirect mode, scalar block will be
  2580. * bypassed. Still we need to update alpha and bitwidth
  2581. * ONLY for RECT0
  2582. */
  2583. if (psde->pipe_hw->ops.setup_scaler &&
  2584. pstate->multirect_index != SDE_SSPP_RECT_1) {
  2585. psde->pipe_hw->ctl = _sde_plane_get_hw_ctl(plane);
  2586. psde->pipe_hw->ops.setup_scaler(psde->pipe_hw,
  2587. &psde->pipe_cfg, &pstate->pixel_ext,
  2588. &pstate->scaler3_cfg);
  2589. }
  2590. /* update excl rect */
  2591. if (psde->pipe_hw->ops.setup_excl_rect)
  2592. psde->pipe_hw->ops.setup_excl_rect(psde->pipe_hw,
  2593. &pstate->excl_rect,
  2594. pstate->multirect_index);
  2595. if (psde->pipe_hw->ops.setup_multirect)
  2596. psde->pipe_hw->ops.setup_multirect(
  2597. psde->pipe_hw,
  2598. pstate->multirect_index,
  2599. pstate->multirect_mode);
  2600. }
  2601. static void _sde_plane_update_format_and_rects(struct sde_plane *psde,
  2602. struct sde_plane_state *pstate, const struct sde_format *fmt)
  2603. {
  2604. uint32_t src_flags = 0;
  2605. SDE_DEBUG_PLANE(psde, "rotation 0x%X\n", pstate->rotation);
  2606. if (pstate->rotation & DRM_MODE_REFLECT_X)
  2607. src_flags |= SDE_SSPP_FLIP_LR;
  2608. if (pstate->rotation & DRM_MODE_REFLECT_Y)
  2609. src_flags |= SDE_SSPP_FLIP_UD;
  2610. if (pstate->rotation & DRM_MODE_ROTATE_90)
  2611. src_flags |= SDE_SSPP_ROT_90;
  2612. /* update format */
  2613. psde->pipe_hw->ops.setup_format(psde->pipe_hw, fmt,
  2614. pstate->const_alpha_en, src_flags,
  2615. pstate->multirect_index);
  2616. if (psde->pipe_hw->ops.setup_cdp) {
  2617. struct sde_hw_pipe_cdp_cfg *cdp_cfg = &pstate->cdp_cfg;
  2618. memset(cdp_cfg, 0, sizeof(struct sde_hw_pipe_cdp_cfg));
  2619. cdp_cfg->enable = psde->catalog->perf.cdp_cfg
  2620. [SDE_PERF_CDP_USAGE_RT].rd_enable;
  2621. cdp_cfg->ubwc_meta_enable =
  2622. SDE_FORMAT_IS_UBWC(fmt);
  2623. cdp_cfg->tile_amortize_enable =
  2624. SDE_FORMAT_IS_UBWC(fmt) ||
  2625. SDE_FORMAT_IS_TILE(fmt);
  2626. cdp_cfg->preload_ahead = SDE_WB_CDP_PRELOAD_AHEAD_64;
  2627. psde->pipe_hw->ops.setup_cdp(psde->pipe_hw, cdp_cfg,
  2628. pstate->multirect_index);
  2629. }
  2630. _sde_plane_sspp_setup_sys_cache(psde, pstate,
  2631. sde_format_is_tp10_ubwc(fmt));
  2632. /* update csc */
  2633. if (SDE_FORMAT_IS_YUV(fmt))
  2634. _sde_plane_setup_csc(psde);
  2635. else
  2636. psde->csc_ptr = 0;
  2637. if (psde->pipe_hw->ops.setup_inverse_pma) {
  2638. uint32_t pma_mode = 0;
  2639. if (fmt->alpha_enable)
  2640. pma_mode = (uint32_t) sde_plane_get_property(
  2641. pstate, PLANE_PROP_INVERSE_PMA);
  2642. psde->pipe_hw->ops.setup_inverse_pma(psde->pipe_hw,
  2643. pstate->multirect_index, pma_mode);
  2644. }
  2645. if (psde->pipe_hw->ops.setup_dgm_csc)
  2646. psde->pipe_hw->ops.setup_dgm_csc(psde->pipe_hw,
  2647. pstate->multirect_index, psde->csc_usr_ptr);
  2648. }
  2649. static void _sde_plane_update_sharpening(struct sde_plane *psde)
  2650. {
  2651. psde->sharp_cfg.strength = SHARP_STRENGTH_DEFAULT;
  2652. psde->sharp_cfg.edge_thr = SHARP_EDGE_THR_DEFAULT;
  2653. psde->sharp_cfg.smooth_thr = SHARP_SMOOTH_THR_DEFAULT;
  2654. psde->sharp_cfg.noise_thr = SHARP_NOISE_THR_DEFAULT;
  2655. psde->pipe_hw->ops.setup_sharpening(psde->pipe_hw,
  2656. &psde->sharp_cfg);
  2657. }
  2658. static void _sde_plane_update_properties(struct drm_plane *plane,
  2659. struct drm_crtc *crtc, struct drm_framebuffer *fb)
  2660. {
  2661. uint32_t nplanes;
  2662. const struct msm_format *msm_fmt;
  2663. const struct sde_format *fmt;
  2664. struct sde_plane *psde;
  2665. struct drm_plane_state *state;
  2666. struct sde_plane_state *pstate;
  2667. psde = to_sde_plane(plane);
  2668. state = plane->state;
  2669. pstate = to_sde_plane_state(state);
  2670. if (!pstate) {
  2671. SDE_ERROR("invalid plane state for plane%d\n", DRMID(plane));
  2672. return;
  2673. }
  2674. msm_fmt = msm_framebuffer_format(fb);
  2675. if (!msm_fmt) {
  2676. SDE_ERROR("crtc%d plane%d: null format\n",
  2677. DRMID(crtc), DRMID(plane));
  2678. return;
  2679. }
  2680. fmt = to_sde_format(msm_fmt);
  2681. nplanes = fmt->num_planes;
  2682. /* update secure session flag */
  2683. if (pstate->dirty & SDE_PLANE_DIRTY_FB_TRANSLATION_MODE)
  2684. _sde_plane_update_secure_session(psde, pstate);
  2685. /* update roi config */
  2686. if (pstate->dirty & SDE_PLANE_DIRTY_RECTS)
  2687. _sde_plane_update_roi_config(plane, crtc, fb);
  2688. if ((pstate->dirty & SDE_PLANE_DIRTY_FORMAT ||
  2689. pstate->dirty & SDE_PLANE_DIRTY_RECTS) &&
  2690. psde->pipe_hw->ops.setup_format)
  2691. _sde_plane_update_format_and_rects(psde, pstate, fmt);
  2692. sde_color_process_plane_setup(plane);
  2693. /* update sharpening */
  2694. if ((pstate->dirty & SDE_PLANE_DIRTY_SHARPEN) &&
  2695. psde->pipe_hw->ops.setup_sharpening)
  2696. _sde_plane_update_sharpening(psde);
  2697. if (pstate->dirty & (SDE_PLANE_DIRTY_QOS | SDE_PLANE_DIRTY_RECTS |
  2698. SDE_PLANE_DIRTY_FORMAT))
  2699. _sde_plane_set_qos_lut(plane, crtc, fb);
  2700. if (plane->type != DRM_PLANE_TYPE_CURSOR) {
  2701. _sde_plane_set_qos_ctrl(plane, true, SDE_PLANE_QOS_PANIC_CTRL);
  2702. _sde_plane_set_ot_limit(plane, crtc);
  2703. if (pstate->dirty & SDE_PLANE_DIRTY_PERF)
  2704. _sde_plane_set_ts_prefill(plane, pstate);
  2705. }
  2706. if (pstate->dirty & SDE_PLANE_DIRTY_QOS)
  2707. _sde_plane_set_qos_remap(plane);
  2708. /* clear dirty */
  2709. pstate->dirty = 0x0;
  2710. }
  2711. static int sde_plane_sspp_atomic_update(struct drm_plane *plane,
  2712. struct drm_plane_state *old_state)
  2713. {
  2714. struct sde_plane *psde;
  2715. struct drm_plane_state *state;
  2716. struct sde_plane_state *pstate;
  2717. struct sde_plane_state *old_pstate;
  2718. struct drm_crtc *crtc;
  2719. struct drm_framebuffer *fb;
  2720. int idx;
  2721. int dirty_prop_flag;
  2722. bool is_rt;
  2723. if (!plane) {
  2724. SDE_ERROR("invalid plane\n");
  2725. return -EINVAL;
  2726. } else if (!plane->state) {
  2727. SDE_ERROR("invalid plane state\n");
  2728. return -EINVAL;
  2729. } else if (!old_state) {
  2730. SDE_ERROR("invalid old state\n");
  2731. return -EINVAL;
  2732. }
  2733. psde = to_sde_plane(plane);
  2734. state = plane->state;
  2735. pstate = to_sde_plane_state(state);
  2736. old_pstate = to_sde_plane_state(old_state);
  2737. crtc = state->crtc;
  2738. fb = state->fb;
  2739. if (!crtc || !fb) {
  2740. SDE_ERROR_PLANE(psde, "invalid crtc %d or fb %d\n",
  2741. !crtc, !fb);
  2742. return -EINVAL;
  2743. }
  2744. SDE_DEBUG(
  2745. "plane%d sspp:%dx%d/%4.4s/%llx/%dx%d+%d+%d/%x crtc:%dx%d+%d+%d\n",
  2746. plane->base.id,
  2747. state->fb->width, state->fb->height,
  2748. (char *) &state->fb->format->format,
  2749. state->fb->modifier,
  2750. state->src_w >> 16, state->src_h >> 16,
  2751. state->src_x >> 16, state->src_y >> 16,
  2752. pstate->rotation,
  2753. state->crtc_w, state->crtc_h,
  2754. state->crtc_x, state->crtc_y);
  2755. /* force reprogramming of all the parameters, if the flag is set */
  2756. if (psde->revalidate) {
  2757. SDE_DEBUG("plane:%d - reconfigure all the parameters\n",
  2758. plane->base.id);
  2759. pstate->dirty = SDE_PLANE_DIRTY_ALL | SDE_PLANE_DIRTY_CP;
  2760. psde->revalidate = false;
  2761. }
  2762. /* determine what needs to be refreshed */
  2763. mutex_lock(&psde->property_info.property_lock);
  2764. while ((idx = msm_property_pop_dirty(&psde->property_info,
  2765. &pstate->property_state)) >= 0) {
  2766. dirty_prop_flag = plane_prop_array[idx];
  2767. pstate->dirty |= dirty_prop_flag;
  2768. }
  2769. mutex_unlock(&psde->property_info.property_lock);
  2770. /**
  2771. * since plane_atomic_check is invoked before crtc_atomic_check
  2772. * in the commit sequence, all the parameters for updating the
  2773. * plane dirty flag will not be available during
  2774. * plane_atomic_check as some features params are updated
  2775. * in crtc_atomic_check (eg.:sDMA). So check for mode_change
  2776. * before sspp update.
  2777. */
  2778. _sde_plane_sspp_atomic_check_mode_changed(psde, state,
  2779. old_state);
  2780. /* re-program the output rects always if partial update roi changed */
  2781. if (sde_crtc_is_crtc_roi_dirty(crtc->state))
  2782. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  2783. if (pstate->dirty & SDE_PLANE_DIRTY_RECTS)
  2784. memset(&(psde->pipe_cfg), 0, sizeof(struct sde_hw_pipe_cfg));
  2785. _sde_plane_set_scanout(plane, pstate, &psde->pipe_cfg, fb);
  2786. is_rt = sde_crtc_is_rt_client(crtc, crtc->state);
  2787. if (is_rt != psde->is_rt_pipe) {
  2788. psde->is_rt_pipe = is_rt;
  2789. pstate->dirty |= SDE_PLANE_DIRTY_QOS;
  2790. }
  2791. /* early out if nothing dirty */
  2792. if (!pstate->dirty)
  2793. return 0;
  2794. pstate->pending = true;
  2795. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
  2796. _sde_plane_update_properties(plane, crtc, fb);
  2797. return 0;
  2798. }
  2799. static void _sde_plane_atomic_disable(struct drm_plane *plane,
  2800. struct drm_plane_state *old_state)
  2801. {
  2802. struct sde_plane *psde;
  2803. struct drm_plane_state *state;
  2804. struct sde_plane_state *pstate;
  2805. if (!plane) {
  2806. SDE_ERROR("invalid plane\n");
  2807. return;
  2808. } else if (!plane->state) {
  2809. SDE_ERROR("invalid plane state\n");
  2810. return;
  2811. } else if (!old_state) {
  2812. SDE_ERROR("invalid old state\n");
  2813. return;
  2814. }
  2815. psde = to_sde_plane(plane);
  2816. state = plane->state;
  2817. pstate = to_sde_plane_state(state);
  2818. SDE_EVT32(DRMID(plane), is_sde_plane_virtual(plane),
  2819. pstate->multirect_mode);
  2820. pstate->pending = true;
  2821. if (is_sde_plane_virtual(plane) &&
  2822. psde->pipe_hw && psde->pipe_hw->ops.setup_multirect)
  2823. psde->pipe_hw->ops.setup_multirect(psde->pipe_hw,
  2824. SDE_SSPP_RECT_SOLO, SDE_SSPP_MULTIRECT_NONE);
  2825. }
  2826. static void sde_plane_atomic_update(struct drm_plane *plane,
  2827. struct drm_plane_state *old_state)
  2828. {
  2829. struct sde_plane *psde;
  2830. struct drm_plane_state *state;
  2831. if (!plane) {
  2832. SDE_ERROR("invalid plane\n");
  2833. return;
  2834. } else if (!plane->state) {
  2835. SDE_ERROR("invalid plane state\n");
  2836. return;
  2837. }
  2838. psde = to_sde_plane(plane);
  2839. psde->is_error = false;
  2840. state = plane->state;
  2841. SDE_DEBUG_PLANE(psde, "\n");
  2842. if (!sde_plane_enabled(state)) {
  2843. _sde_plane_atomic_disable(plane, old_state);
  2844. } else {
  2845. int ret;
  2846. ret = sde_plane_sspp_atomic_update(plane, old_state);
  2847. /* atomic_check should have ensured that this doesn't fail */
  2848. WARN_ON(ret < 0);
  2849. }
  2850. }
  2851. void sde_plane_restore(struct drm_plane *plane)
  2852. {
  2853. struct sde_plane *psde;
  2854. if (!plane || !plane->state) {
  2855. SDE_ERROR("invalid plane\n");
  2856. return;
  2857. }
  2858. psde = to_sde_plane(plane);
  2859. /*
  2860. * Revalidate is only true here if idle PC occurred and
  2861. * there is no plane state update in current commit cycle.
  2862. */
  2863. if (!psde->revalidate)
  2864. return;
  2865. SDE_DEBUG_PLANE(psde, "\n");
  2866. /* last plane state is same as current state */
  2867. sde_plane_atomic_update(plane, plane->state);
  2868. }
  2869. bool sde_plane_is_cache_required(struct drm_plane *plane,
  2870. enum sde_sys_cache_type type)
  2871. {
  2872. struct sde_plane_state *pstate;
  2873. if (!plane || !plane->state) {
  2874. SDE_ERROR("invalid plane\n");
  2875. return false;
  2876. }
  2877. pstate = to_sde_plane_state(plane->state);
  2878. /* check if llcc is required for the plane */
  2879. if (pstate->sc_cfg.rd_en && (pstate->sc_cfg.type == type))
  2880. return true;
  2881. else
  2882. return false;
  2883. }
  2884. static void _sde_plane_install_master_only_properties(struct sde_plane *psde)
  2885. {
  2886. char feature_name[256];
  2887. if (psde->pipe_sblk->maxhdeciexp) {
  2888. msm_property_install_range(&psde->property_info,
  2889. "h_decimate", 0x0, 0,
  2890. psde->pipe_sblk->maxhdeciexp, 0,
  2891. PLANE_PROP_H_DECIMATE);
  2892. }
  2893. if (psde->pipe_sblk->maxvdeciexp) {
  2894. msm_property_install_range(&psde->property_info,
  2895. "v_decimate", 0x0, 0,
  2896. psde->pipe_sblk->maxvdeciexp, 0,
  2897. PLANE_PROP_V_DECIMATE);
  2898. }
  2899. if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) {
  2900. msm_property_install_range(
  2901. &psde->property_info, "scaler_v2",
  2902. 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V2);
  2903. msm_property_install_blob(&psde->property_info,
  2904. "lut_ed", 0, PLANE_PROP_SCALER_LUT_ED);
  2905. msm_property_install_blob(&psde->property_info,
  2906. "lut_cir", 0,
  2907. PLANE_PROP_SCALER_LUT_CIR);
  2908. msm_property_install_blob(&psde->property_info,
  2909. "lut_sep", 0,
  2910. PLANE_PROP_SCALER_LUT_SEP);
  2911. } else if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3LITE)) {
  2912. msm_property_install_range(
  2913. &psde->property_info, "scaler_v2",
  2914. 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V2);
  2915. msm_property_install_blob(&psde->property_info,
  2916. "lut_sep", 0,
  2917. PLANE_PROP_SCALER_LUT_SEP);
  2918. } else if (psde->features & SDE_SSPP_SCALER) {
  2919. msm_property_install_range(
  2920. &psde->property_info, "scaler_v1", 0x0,
  2921. 0, ~0, 0, PLANE_PROP_SCALER_V1);
  2922. }
  2923. if (psde->features & BIT(SDE_SSPP_CSC) ||
  2924. psde->features & BIT(SDE_SSPP_CSC_10BIT))
  2925. msm_property_install_volatile_range(
  2926. &psde->property_info, "csc_v1", 0x0,
  2927. 0, ~0, 0, PLANE_PROP_CSC_V1);
  2928. if (psde->features & BIT(SDE_SSPP_HSIC)) {
  2929. snprintf(feature_name, sizeof(feature_name), "%s%d",
  2930. "SDE_SSPP_HUE_V",
  2931. psde->pipe_sblk->hsic_blk.version >> 16);
  2932. msm_property_install_range(&psde->property_info,
  2933. feature_name, 0, 0, 0xFFFFFFFF, 0,
  2934. PLANE_PROP_HUE_ADJUST);
  2935. snprintf(feature_name, sizeof(feature_name), "%s%d",
  2936. "SDE_SSPP_SATURATION_V",
  2937. psde->pipe_sblk->hsic_blk.version >> 16);
  2938. msm_property_install_range(&psde->property_info,
  2939. feature_name, 0, 0, 0xFFFFFFFF, 0,
  2940. PLANE_PROP_SATURATION_ADJUST);
  2941. snprintf(feature_name, sizeof(feature_name), "%s%d",
  2942. "SDE_SSPP_VALUE_V",
  2943. psde->pipe_sblk->hsic_blk.version >> 16);
  2944. msm_property_install_range(&psde->property_info,
  2945. feature_name, 0, 0, 0xFFFFFFFF, 0,
  2946. PLANE_PROP_VALUE_ADJUST);
  2947. snprintf(feature_name, sizeof(feature_name), "%s%d",
  2948. "SDE_SSPP_CONTRAST_V",
  2949. psde->pipe_sblk->hsic_blk.version >> 16);
  2950. msm_property_install_range(&psde->property_info,
  2951. feature_name, 0, 0, 0xFFFFFFFF, 0,
  2952. PLANE_PROP_CONTRAST_ADJUST);
  2953. }
  2954. }
  2955. static void _sde_plane_install_colorproc_properties(struct sde_plane *psde,
  2956. struct sde_kms_info *info)
  2957. {
  2958. char feature_name[256];
  2959. bool is_master = !psde->is_virtual;
  2960. if ((is_master &&
  2961. (psde->features & BIT(SDE_SSPP_INVERSE_PMA))) ||
  2962. (psde->features & BIT(SDE_SSPP_DGM_INVERSE_PMA))) {
  2963. msm_property_install_range(&psde->property_info,
  2964. "inverse_pma", 0x0, 0, 1, 0, PLANE_PROP_INVERSE_PMA);
  2965. sde_kms_info_add_keyint(info, "inverse_pma", 1);
  2966. }
  2967. if (psde->features & BIT(SDE_SSPP_DGM_CSC)) {
  2968. msm_property_install_volatile_range(
  2969. &psde->property_info, "csc_dma_v1", 0x0,
  2970. 0, ~0, 0, PLANE_PROP_CSC_DMA_V1);
  2971. sde_kms_info_add_keyint(info, "csc_dma_v1", 1);
  2972. }
  2973. if (psde->features & BIT(SDE_SSPP_MEMCOLOR)) {
  2974. snprintf(feature_name, sizeof(feature_name), "%s%d",
  2975. "SDE_SSPP_SKIN_COLOR_V",
  2976. psde->pipe_sblk->memcolor_blk.version >> 16);
  2977. msm_property_install_blob(&psde->property_info, feature_name, 0,
  2978. PLANE_PROP_SKIN_COLOR);
  2979. snprintf(feature_name, sizeof(feature_name), "%s%d",
  2980. "SDE_SSPP_SKY_COLOR_V",
  2981. psde->pipe_sblk->memcolor_blk.version >> 16);
  2982. msm_property_install_blob(&psde->property_info, feature_name, 0,
  2983. PLANE_PROP_SKY_COLOR);
  2984. snprintf(feature_name, sizeof(feature_name), "%s%d",
  2985. "SDE_SSPP_FOLIAGE_COLOR_V",
  2986. psde->pipe_sblk->memcolor_blk.version >> 16);
  2987. msm_property_install_blob(&psde->property_info, feature_name, 0,
  2988. PLANE_PROP_FOLIAGE_COLOR);
  2989. }
  2990. if (psde->features & BIT(SDE_SSPP_VIG_GAMUT)) {
  2991. snprintf(feature_name, sizeof(feature_name), "%s%d",
  2992. "SDE_VIG_3D_LUT_GAMUT_V",
  2993. psde->pipe_sblk->gamut_blk.version >> 16);
  2994. msm_property_install_blob(&psde->property_info, feature_name, 0,
  2995. PLANE_PROP_VIG_GAMUT);
  2996. }
  2997. if (psde->features & BIT(SDE_SSPP_VIG_IGC)) {
  2998. snprintf(feature_name, sizeof(feature_name), "%s%d",
  2999. "SDE_VIG_1D_LUT_IGC_V",
  3000. psde->pipe_sblk->igc_blk[0].version >> 16);
  3001. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3002. PLANE_PROP_VIG_IGC);
  3003. }
  3004. if (psde->features & BIT(SDE_SSPP_DMA_IGC)) {
  3005. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3006. "SDE_DGM_1D_LUT_IGC_V",
  3007. psde->pipe_sblk->igc_blk[0].version >> 16);
  3008. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3009. PLANE_PROP_DMA_IGC);
  3010. }
  3011. if (psde->features & BIT(SDE_SSPP_DMA_GC)) {
  3012. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3013. "SDE_DGM_1D_LUT_GC_V",
  3014. psde->pipe_sblk->gc_blk[0].version >> 16);
  3015. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3016. PLANE_PROP_DMA_GC);
  3017. }
  3018. }
  3019. static void _sde_plane_setup_capabilities_blob(struct sde_plane *psde,
  3020. u32 master_plane_id, struct sde_kms_info *info,
  3021. struct sde_mdss_cfg *catalog)
  3022. {
  3023. bool is_master = !psde->is_virtual;
  3024. const struct sde_format_extended *format_list;
  3025. u32 index;
  3026. if (is_master) {
  3027. format_list = psde->pipe_sblk->format_list;
  3028. } else {
  3029. format_list = psde->pipe_sblk->virt_format_list;
  3030. sde_kms_info_add_keyint(info, "primary_smart_plane_id",
  3031. master_plane_id);
  3032. }
  3033. if (format_list) {
  3034. sde_kms_info_start(info, "pixel_formats");
  3035. while (format_list->fourcc_format) {
  3036. sde_kms_info_append_format(info,
  3037. format_list->fourcc_format,
  3038. format_list->modifier);
  3039. ++format_list;
  3040. }
  3041. sde_kms_info_stop(info);
  3042. }
  3043. if (psde->pipe_hw && catalog->qseed_hw_version)
  3044. sde_kms_info_add_keyint(info, "scaler_step_ver",
  3045. catalog->qseed_hw_version);
  3046. sde_kms_info_add_keyint(info, "max_linewidth",
  3047. psde->pipe_sblk->maxlinewidth);
  3048. sde_kms_info_add_keyint(info, "max_upscale",
  3049. psde->pipe_sblk->maxupscale);
  3050. sde_kms_info_add_keyint(info, "max_downscale",
  3051. psde->pipe_sblk->maxdwnscale);
  3052. sde_kms_info_add_keyint(info, "max_horizontal_deci",
  3053. psde->pipe_sblk->maxhdeciexp);
  3054. sde_kms_info_add_keyint(info, "max_vertical_deci",
  3055. psde->pipe_sblk->maxvdeciexp);
  3056. sde_kms_info_add_keyint(info, "max_per_pipe_bw",
  3057. psde->pipe_sblk->max_per_pipe_bw * 1000LL);
  3058. sde_kms_info_add_keyint(info, "max_per_pipe_bw_high",
  3059. psde->pipe_sblk->max_per_pipe_bw_high * 1000LL);
  3060. index = (master_plane_id == 0) ? 0 : 1;
  3061. if (catalog->has_demura &&
  3062. catalog->demura_supported[psde->pipe][index] != ~0x0) {
  3063. sde_kms_info_add_keyint(info, "demura_block", index);
  3064. sde_kms_info_add_keyint(info, "demura_pipe_id",
  3065. psde->pipe - SSPP_DMA0);
  3066. }
  3067. if (psde->features & BIT(SDE_SSPP_SEC_UI_ALLOWED))
  3068. sde_kms_info_add_keyint(info, "sec_ui_allowed", 1);
  3069. if (psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI))
  3070. sde_kms_info_add_keyint(info, "block_sec_ui", 1);
  3071. if (psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT)) {
  3072. const struct sde_format_extended *inline_rot_fmt_list;
  3073. sde_kms_info_add_keyint(info, "true_inline_rot_rev",
  3074. catalog->true_inline_rot_rev);
  3075. sde_kms_info_add_keyint(info,
  3076. "true_inline_dwnscale_rt",
  3077. (int) (psde->pipe_sblk->in_rot_maxdwnscale_rt_num /
  3078. psde->pipe_sblk->in_rot_maxdwnscale_rt_denom));
  3079. sde_kms_info_add_keyint(info,
  3080. "true_inline_dwnscale_rt_numerator",
  3081. psde->pipe_sblk->in_rot_maxdwnscale_rt_num);
  3082. sde_kms_info_add_keyint(info,
  3083. "true_inline_dwnscale_rt_denominator",
  3084. psde->pipe_sblk->in_rot_maxdwnscale_rt_denom);
  3085. sde_kms_info_add_keyint(info, "true_inline_dwnscale_nrt",
  3086. psde->pipe_sblk->in_rot_maxdwnscale_nrt);
  3087. sde_kms_info_add_keyint(info, "true_inline_max_height",
  3088. psde->pipe_sblk->in_rot_maxheight);
  3089. inline_rot_fmt_list = psde->pipe_sblk->in_rot_format_list;
  3090. if (inline_rot_fmt_list) {
  3091. sde_kms_info_start(info, "inline_rot_pixel_formats");
  3092. while (inline_rot_fmt_list->fourcc_format) {
  3093. sde_kms_info_append_format(info,
  3094. inline_rot_fmt_list->fourcc_format,
  3095. inline_rot_fmt_list->modifier);
  3096. ++inline_rot_fmt_list;
  3097. }
  3098. sde_kms_info_stop(info);
  3099. }
  3100. }
  3101. }
  3102. /* helper to install properties which are common to planes and crtcs */
  3103. static void _sde_plane_install_properties(struct drm_plane *plane,
  3104. struct sde_mdss_cfg *catalog, u32 master_plane_id)
  3105. {
  3106. static const struct drm_prop_enum_list e_blend_op[] = {
  3107. {SDE_DRM_BLEND_OP_NOT_DEFINED, "not_defined"},
  3108. {SDE_DRM_BLEND_OP_OPAQUE, "opaque"},
  3109. {SDE_DRM_BLEND_OP_PREMULTIPLIED, "premultiplied"},
  3110. {SDE_DRM_BLEND_OP_COVERAGE, "coverage"},
  3111. {SDE_DRM_BLEND_OP_SKIP, "skip_blending"},
  3112. };
  3113. static const struct drm_prop_enum_list e_src_config[] = {
  3114. {SDE_DRM_DEINTERLACE, "deinterlace"}
  3115. };
  3116. static const struct drm_prop_enum_list e_fb_translation_mode[] = {
  3117. {SDE_DRM_FB_NON_SEC, "non_sec"},
  3118. {SDE_DRM_FB_SEC, "sec"},
  3119. {SDE_DRM_FB_NON_SEC_DIR_TRANS, "non_sec_direct_translation"},
  3120. {SDE_DRM_FB_SEC_DIR_TRANS, "sec_direct_translation"},
  3121. };
  3122. static const struct drm_prop_enum_list e_multirect_mode[] = {
  3123. {SDE_SSPP_MULTIRECT_NONE, "none"},
  3124. {SDE_SSPP_MULTIRECT_PARALLEL, "parallel"},
  3125. {SDE_SSPP_MULTIRECT_TIME_MX, "serial"},
  3126. };
  3127. struct sde_kms_info *info;
  3128. struct sde_plane *psde = to_sde_plane(plane);
  3129. bool is_master;
  3130. int zpos_max = 255;
  3131. int zpos_def = 0;
  3132. if (!plane || !psde) {
  3133. SDE_ERROR("invalid plane\n");
  3134. return;
  3135. } else if (!psde->pipe_hw || !psde->pipe_sblk) {
  3136. SDE_ERROR("invalid plane, pipe_hw %d pipe_sblk %d\n",
  3137. !psde->pipe_hw, !psde->pipe_sblk);
  3138. return;
  3139. } else if (!catalog) {
  3140. SDE_ERROR("invalid catalog\n");
  3141. return;
  3142. }
  3143. psde->catalog = catalog;
  3144. is_master = !psde->is_virtual;
  3145. info = kzalloc(sizeof(struct sde_kms_info), GFP_KERNEL);
  3146. if (!info) {
  3147. SDE_ERROR("failed to allocate info memory\n");
  3148. return;
  3149. }
  3150. if (sde_is_custom_client()) {
  3151. if (catalog->mixer_count &&
  3152. catalog->mixer[0].sblk->maxblendstages) {
  3153. zpos_max = catalog->mixer[0].sblk->maxblendstages - 1;
  3154. if (catalog->has_base_layer &&
  3155. (zpos_max > SDE_STAGE_MAX - 1))
  3156. zpos_max = SDE_STAGE_MAX - 1;
  3157. else if (zpos_max > SDE_STAGE_MAX - SDE_STAGE_0 - 1)
  3158. zpos_max = SDE_STAGE_MAX - SDE_STAGE_0 - 1;
  3159. }
  3160. } else if (plane->type != DRM_PLANE_TYPE_PRIMARY) {
  3161. /* reserve zpos == 0 for primary planes */
  3162. zpos_def = drm_plane_index(plane) + 1;
  3163. }
  3164. msm_property_install_range(&psde->property_info, "zpos",
  3165. 0x0, 0, zpos_max, zpos_def, PLANE_PROP_ZPOS);
  3166. msm_property_install_range(&psde->property_info, "alpha",
  3167. 0x0, 0, 255, 255, PLANE_PROP_ALPHA);
  3168. /* linux default file descriptor range on each process */
  3169. msm_property_install_range(&psde->property_info, "input_fence",
  3170. 0x0, 0, INR_OPEN_MAX, 0, PLANE_PROP_INPUT_FENCE);
  3171. if (is_master)
  3172. _sde_plane_install_master_only_properties(psde);
  3173. else
  3174. msm_property_install_enum(&psde->property_info,
  3175. "multirect_mode", 0x0, 0, e_multirect_mode,
  3176. ARRAY_SIZE(e_multirect_mode),
  3177. PLANE_PROP_MULTIRECT_MODE);
  3178. if (psde->features & BIT(SDE_SSPP_EXCL_RECT))
  3179. msm_property_install_volatile_range(&psde->property_info,
  3180. "excl_rect_v1", 0x0, 0, ~0, 0, PLANE_PROP_EXCL_RECT_V1);
  3181. sde_plane_rot_install_properties(plane, catalog);
  3182. msm_property_install_enum(&psde->property_info, "blend_op", 0x0, 0,
  3183. e_blend_op, ARRAY_SIZE(e_blend_op), PLANE_PROP_BLEND_OP);
  3184. msm_property_install_enum(&psde->property_info, "src_config", 0x0, 1,
  3185. e_src_config, ARRAY_SIZE(e_src_config), PLANE_PROP_SRC_CONFIG);
  3186. if (psde->pipe_hw->ops.setup_solidfill)
  3187. msm_property_install_range(&psde->property_info, "color_fill",
  3188. 0, 0, 0xFFFFFFFF, 0, PLANE_PROP_COLOR_FILL);
  3189. msm_property_install_range(&psde->property_info, "prefill_size", 0x0,
  3190. 0, ~0, 0, PLANE_PROP_PREFILL_SIZE);
  3191. msm_property_install_range(&psde->property_info, "prefill_time", 0x0,
  3192. 0, ~0, 0, PLANE_PROP_PREFILL_TIME);
  3193. msm_property_install_blob(&psde->property_info, "capabilities",
  3194. DRM_MODE_PROP_IMMUTABLE, PLANE_PROP_INFO);
  3195. sde_kms_info_reset(info);
  3196. _sde_plane_setup_capabilities_blob(psde, master_plane_id, info,
  3197. catalog);
  3198. _sde_plane_install_colorproc_properties(psde, info);
  3199. msm_property_set_blob(&psde->property_info, &psde->blob_info,
  3200. info->data, SDE_KMS_INFO_DATALEN(info),
  3201. PLANE_PROP_INFO);
  3202. msm_property_install_enum(&psde->property_info, "fb_translation_mode",
  3203. 0x0, 0, e_fb_translation_mode,
  3204. ARRAY_SIZE(e_fb_translation_mode),
  3205. PLANE_PROP_FB_TRANSLATION_MODE);
  3206. kfree(info);
  3207. }
  3208. static inline void _sde_plane_set_csc_v1(struct sde_plane *psde,
  3209. void __user *usr_ptr)
  3210. {
  3211. struct sde_drm_csc_v1 csc_v1;
  3212. int i;
  3213. if (!psde) {
  3214. SDE_ERROR("invalid plane\n");
  3215. return;
  3216. }
  3217. psde->csc_usr_ptr = NULL;
  3218. if (!usr_ptr) {
  3219. SDE_DEBUG_PLANE(psde, "csc data removed\n");
  3220. return;
  3221. }
  3222. if (copy_from_user(&csc_v1, usr_ptr, sizeof(csc_v1))) {
  3223. SDE_ERROR_PLANE(psde, "failed to copy csc data\n");
  3224. return;
  3225. }
  3226. /* populate from user space */
  3227. for (i = 0; i < SDE_CSC_MATRIX_COEFF_SIZE; ++i)
  3228. psde->csc_cfg.csc_mv[i] = csc_v1.ctm_coeff[i] >> 16;
  3229. for (i = 0; i < SDE_CSC_BIAS_SIZE; ++i) {
  3230. psde->csc_cfg.csc_pre_bv[i] = csc_v1.pre_bias[i];
  3231. psde->csc_cfg.csc_post_bv[i] = csc_v1.post_bias[i];
  3232. }
  3233. for (i = 0; i < SDE_CSC_CLAMP_SIZE; ++i) {
  3234. psde->csc_cfg.csc_pre_lv[i] = csc_v1.pre_clamp[i];
  3235. psde->csc_cfg.csc_post_lv[i] = csc_v1.post_clamp[i];
  3236. }
  3237. psde->csc_usr_ptr = &psde->csc_cfg;
  3238. }
  3239. static inline void _sde_plane_set_scaler_v1(struct sde_plane *psde,
  3240. struct sde_plane_state *pstate, void __user *usr)
  3241. {
  3242. struct sde_drm_scaler_v1 scale_v1;
  3243. struct sde_hw_pixel_ext *pe;
  3244. int i;
  3245. if (!psde || !pstate) {
  3246. SDE_ERROR("invalid argument(s)\n");
  3247. return;
  3248. }
  3249. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_NONE;
  3250. if (!usr) {
  3251. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3252. return;
  3253. }
  3254. if (copy_from_user(&scale_v1, usr, sizeof(scale_v1))) {
  3255. SDE_ERROR_PLANE(psde, "failed to copy scale data\n");
  3256. return;
  3257. }
  3258. /* force property to be dirty, even if the pointer didn't change */
  3259. msm_property_set_dirty(&psde->property_info,
  3260. &pstate->property_state, PLANE_PROP_SCALER_V1);
  3261. /* populate from user space */
  3262. pe = &pstate->pixel_ext;
  3263. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  3264. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3265. pe->init_phase_x[i] = scale_v1.init_phase_x[i];
  3266. pe->phase_step_x[i] = scale_v1.phase_step_x[i];
  3267. pe->init_phase_y[i] = scale_v1.init_phase_y[i];
  3268. pe->phase_step_y[i] = scale_v1.phase_step_y[i];
  3269. pe->horz_filter[i] = scale_v1.horz_filter[i];
  3270. pe->vert_filter[i] = scale_v1.vert_filter[i];
  3271. }
  3272. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3273. pe->left_ftch[i] = scale_v1.pe.left_ftch[i];
  3274. pe->right_ftch[i] = scale_v1.pe.right_ftch[i];
  3275. pe->left_rpt[i] = scale_v1.pe.left_rpt[i];
  3276. pe->right_rpt[i] = scale_v1.pe.right_rpt[i];
  3277. pe->roi_w[i] = scale_v1.pe.num_ext_pxls_lr[i];
  3278. pe->top_ftch[i] = scale_v1.pe.top_ftch[i];
  3279. pe->btm_ftch[i] = scale_v1.pe.btm_ftch[i];
  3280. pe->top_rpt[i] = scale_v1.pe.top_rpt[i];
  3281. pe->btm_rpt[i] = scale_v1.pe.btm_rpt[i];
  3282. pe->roi_h[i] = scale_v1.pe.num_ext_pxls_tb[i];
  3283. }
  3284. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V1;
  3285. SDE_EVT32_VERBOSE(DRMID(&psde->base));
  3286. SDE_DEBUG_PLANE(psde, "user property data copied\n");
  3287. }
  3288. static void _sde_plane_clear_predownscale_settings(
  3289. struct sde_plane_state *pstate)
  3290. {
  3291. pstate->pre_down.pre_downscale_x_0 = 0;
  3292. pstate->pre_down.pre_downscale_x_1 = 0;
  3293. pstate->pre_down.pre_downscale_y_0 = 0;
  3294. pstate->pre_down.pre_downscale_y_1 = 0;
  3295. }
  3296. static inline void _sde_plane_set_scaler_v2(struct sde_plane *psde,
  3297. struct sde_plane_state *pstate, void __user *usr)
  3298. {
  3299. struct sde_drm_scaler_v2 scale_v2;
  3300. struct sde_hw_pixel_ext *pe;
  3301. int i;
  3302. struct sde_hw_scaler3_cfg *cfg;
  3303. struct sde_hw_inline_pre_downscale_cfg *pd_cfg;
  3304. if (!psde || !pstate) {
  3305. SDE_ERROR("invalid argument(s)\n");
  3306. return;
  3307. }
  3308. cfg = &pstate->scaler3_cfg;
  3309. pd_cfg = &pstate->pre_down;
  3310. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_NONE;
  3311. if (!usr) {
  3312. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3313. cfg->enable = 0;
  3314. _sde_plane_clear_predownscale_settings(pstate);
  3315. goto end;
  3316. }
  3317. if (copy_from_user(&scale_v2, usr, sizeof(scale_v2))) {
  3318. SDE_ERROR_PLANE(psde, "failed to copy scale data\n");
  3319. return;
  3320. }
  3321. /* detach/ignore user data if 'disabled' */
  3322. if (!scale_v2.enable) {
  3323. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3324. cfg->enable = 0;
  3325. _sde_plane_clear_predownscale_settings(pstate);
  3326. goto end;
  3327. }
  3328. /* populate from user space */
  3329. sde_set_scaler_v2(cfg, &scale_v2);
  3330. if (_sde_plane_has_pre_downscale(psde)) {
  3331. pd_cfg->pre_downscale_x_0 = scale_v2.pre_downscale_x_0;
  3332. pd_cfg->pre_downscale_x_1 = scale_v2.pre_downscale_x_1;
  3333. pd_cfg->pre_downscale_y_0 = scale_v2.pre_downscale_y_0;
  3334. pd_cfg->pre_downscale_y_1 = scale_v2.pre_downscale_y_1;
  3335. }
  3336. pe = &pstate->pixel_ext;
  3337. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  3338. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3339. pe->left_ftch[i] = scale_v2.pe.left_ftch[i];
  3340. pe->right_ftch[i] = scale_v2.pe.right_ftch[i];
  3341. pe->left_rpt[i] = scale_v2.pe.left_rpt[i];
  3342. pe->right_rpt[i] = scale_v2.pe.right_rpt[i];
  3343. pe->roi_w[i] = scale_v2.pe.num_ext_pxls_lr[i];
  3344. pe->top_ftch[i] = scale_v2.pe.top_ftch[i];
  3345. pe->btm_ftch[i] = scale_v2.pe.btm_ftch[i];
  3346. pe->top_rpt[i] = scale_v2.pe.top_rpt[i];
  3347. pe->btm_rpt[i] = scale_v2.pe.btm_rpt[i];
  3348. pe->roi_h[i] = scale_v2.pe.num_ext_pxls_tb[i];
  3349. }
  3350. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V2_CHECK;
  3351. end:
  3352. /* force property to be dirty, even if the pointer didn't change */
  3353. msm_property_set_dirty(&psde->property_info,
  3354. &pstate->property_state, PLANE_PROP_SCALER_V2);
  3355. SDE_EVT32_VERBOSE(DRMID(&psde->base), cfg->enable, cfg->de.enable,
  3356. cfg->src_width[0], cfg->src_height[0],
  3357. cfg->dst_width, cfg->dst_height);
  3358. SDE_DEBUG_PLANE(psde, "user property data copied\n");
  3359. }
  3360. static void _sde_plane_set_excl_rect_v1(struct sde_plane *psde,
  3361. struct sde_plane_state *pstate, void __user *usr_ptr)
  3362. {
  3363. struct drm_clip_rect excl_rect_v1;
  3364. if (!psde || !pstate) {
  3365. SDE_ERROR("invalid argument(s)\n");
  3366. return;
  3367. }
  3368. if (!usr_ptr) {
  3369. memset(&pstate->excl_rect, 0, sizeof(pstate->excl_rect));
  3370. SDE_DEBUG_PLANE(psde, "excl_rect data cleared\n");
  3371. return;
  3372. }
  3373. if (copy_from_user(&excl_rect_v1, usr_ptr, sizeof(excl_rect_v1))) {
  3374. SDE_ERROR_PLANE(psde, "failed to copy excl_rect data\n");
  3375. return;
  3376. }
  3377. /* populate from user space */
  3378. pstate->excl_rect.x = excl_rect_v1.x1;
  3379. pstate->excl_rect.y = excl_rect_v1.y1;
  3380. pstate->excl_rect.w = excl_rect_v1.x2 - excl_rect_v1.x1;
  3381. pstate->excl_rect.h = excl_rect_v1.y2 - excl_rect_v1.y1;
  3382. SDE_DEBUG_PLANE(psde, "excl_rect: {%d,%d,%d,%d}\n",
  3383. pstate->excl_rect.x, pstate->excl_rect.y,
  3384. pstate->excl_rect.w, pstate->excl_rect.h);
  3385. }
  3386. static int sde_plane_atomic_set_property(struct drm_plane *plane,
  3387. struct drm_plane_state *state, struct drm_property *property,
  3388. uint64_t val)
  3389. {
  3390. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3391. struct sde_plane_state *pstate;
  3392. int idx, ret = -EINVAL;
  3393. SDE_DEBUG_PLANE(psde, "\n");
  3394. if (!plane) {
  3395. SDE_ERROR("invalid plane\n");
  3396. } else if (!state) {
  3397. SDE_ERROR_PLANE(psde, "invalid state\n");
  3398. } else {
  3399. pstate = to_sde_plane_state(state);
  3400. ret = msm_property_atomic_set(&psde->property_info,
  3401. &pstate->property_state, property, val);
  3402. if (!ret) {
  3403. idx = msm_property_index(&psde->property_info,
  3404. property);
  3405. switch (idx) {
  3406. case PLANE_PROP_INPUT_FENCE:
  3407. _sde_plane_set_input_fence(psde, pstate, val);
  3408. break;
  3409. case PLANE_PROP_CSC_V1:
  3410. case PLANE_PROP_CSC_DMA_V1:
  3411. _sde_plane_set_csc_v1(psde, (void __user *)val);
  3412. break;
  3413. case PLANE_PROP_SCALER_V1:
  3414. _sde_plane_set_scaler_v1(psde, pstate,
  3415. (void *)(uintptr_t)val);
  3416. break;
  3417. case PLANE_PROP_SCALER_V2:
  3418. _sde_plane_set_scaler_v2(psde, pstate,
  3419. (void *)(uintptr_t)val);
  3420. break;
  3421. case PLANE_PROP_EXCL_RECT_V1:
  3422. _sde_plane_set_excl_rect_v1(psde, pstate,
  3423. (void *)(uintptr_t)val);
  3424. break;
  3425. default:
  3426. /* nothing to do */
  3427. break;
  3428. }
  3429. }
  3430. }
  3431. SDE_DEBUG_PLANE(psde, "%s[%d] <= 0x%llx ret=%d\n",
  3432. property->name, property->base.id, val, ret);
  3433. return ret;
  3434. }
  3435. static int sde_plane_atomic_get_property(struct drm_plane *plane,
  3436. const struct drm_plane_state *state,
  3437. struct drm_property *property, uint64_t *val)
  3438. {
  3439. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3440. struct sde_plane_state *pstate;
  3441. int ret = -EINVAL;
  3442. if (!plane) {
  3443. SDE_ERROR("invalid plane\n");
  3444. } else if (!state) {
  3445. SDE_ERROR("invalid state\n");
  3446. } else {
  3447. SDE_DEBUG_PLANE(psde, "\n");
  3448. pstate = to_sde_plane_state(state);
  3449. ret = msm_property_atomic_get(&psde->property_info,
  3450. &pstate->property_state, property, val);
  3451. }
  3452. return ret;
  3453. }
  3454. int sde_plane_helper_reset_custom_properties(struct drm_plane *plane,
  3455. struct drm_plane_state *plane_state)
  3456. {
  3457. struct sde_plane *psde;
  3458. struct sde_plane_state *pstate;
  3459. struct drm_property *drm_prop;
  3460. enum msm_mdp_plane_property prop_idx;
  3461. if (!plane || !plane_state) {
  3462. SDE_ERROR("invalid params\n");
  3463. return -EINVAL;
  3464. }
  3465. psde = to_sde_plane(plane);
  3466. pstate = to_sde_plane_state(plane_state);
  3467. for (prop_idx = 0; prop_idx < PLANE_PROP_COUNT; prop_idx++) {
  3468. uint64_t val = pstate->property_values[prop_idx].value;
  3469. uint64_t def;
  3470. int ret;
  3471. drm_prop = msm_property_index_to_drm_property(
  3472. &psde->property_info, prop_idx);
  3473. if (!drm_prop) {
  3474. /* not all props will be installed, based on caps */
  3475. SDE_DEBUG_PLANE(psde, "invalid property index %d\n",
  3476. prop_idx);
  3477. continue;
  3478. }
  3479. def = msm_property_get_default(&psde->property_info, prop_idx);
  3480. if (val == def)
  3481. continue;
  3482. SDE_DEBUG_PLANE(psde, "set prop %s idx %d from %llu to %llu\n",
  3483. drm_prop->name, prop_idx, val, def);
  3484. ret = sde_plane_atomic_set_property(plane, plane_state,
  3485. drm_prop, def);
  3486. if (ret) {
  3487. SDE_ERROR_PLANE(psde,
  3488. "set property failed, idx %d ret %d\n",
  3489. prop_idx, ret);
  3490. continue;
  3491. }
  3492. }
  3493. return 0;
  3494. }
  3495. static void sde_plane_destroy(struct drm_plane *plane)
  3496. {
  3497. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3498. SDE_DEBUG_PLANE(psde, "\n");
  3499. if (psde) {
  3500. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
  3501. if (psde->blob_info)
  3502. drm_property_blob_put(psde->blob_info);
  3503. msm_property_destroy(&psde->property_info);
  3504. mutex_destroy(&psde->lock);
  3505. /* this will destroy the states as well */
  3506. drm_plane_cleanup(plane);
  3507. if (psde->pipe_hw)
  3508. sde_hw_sspp_destroy(psde->pipe_hw);
  3509. kfree(psde);
  3510. }
  3511. }
  3512. void sde_plane_destroy_fb(struct drm_plane_state *state)
  3513. {
  3514. struct sde_plane_state *pstate;
  3515. if (!state) {
  3516. SDE_ERROR("invalid arg state %d\n", !state);
  3517. return;
  3518. }
  3519. pstate = to_sde_plane_state(state);
  3520. if (sde_plane_get_property(pstate, PLANE_PROP_FB_TRANSLATION_MODE) ==
  3521. SDE_DRM_FB_SEC) {
  3522. /* remove ref count for frame buffers */
  3523. if (state->fb) {
  3524. drm_framebuffer_put(state->fb);
  3525. state->fb = NULL;
  3526. }
  3527. }
  3528. }
  3529. static void sde_plane_destroy_state(struct drm_plane *plane,
  3530. struct drm_plane_state *state)
  3531. {
  3532. struct sde_plane *psde;
  3533. struct sde_plane_state *pstate;
  3534. if (!plane || !state) {
  3535. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  3536. !plane, !state);
  3537. return;
  3538. }
  3539. psde = to_sde_plane(plane);
  3540. pstate = to_sde_plane_state(state);
  3541. SDE_DEBUG_PLANE(psde, "\n");
  3542. /* remove ref count for frame buffers */
  3543. if (state->fb)
  3544. drm_framebuffer_put(state->fb);
  3545. /* remove ref count for fence */
  3546. if (pstate->input_fence)
  3547. sde_sync_put(pstate->input_fence);
  3548. /* destroy value helper */
  3549. msm_property_destroy_state(&psde->property_info, pstate,
  3550. &pstate->property_state);
  3551. }
  3552. static struct drm_plane_state *
  3553. sde_plane_duplicate_state(struct drm_plane *plane)
  3554. {
  3555. struct sde_plane *psde;
  3556. struct sde_plane_state *pstate;
  3557. struct sde_plane_state *old_state;
  3558. struct drm_property *drm_prop;
  3559. uint64_t input_fence_default;
  3560. if (!plane) {
  3561. SDE_ERROR("invalid plane\n");
  3562. return NULL;
  3563. } else if (!plane->state) {
  3564. SDE_ERROR("invalid plane state\n");
  3565. return NULL;
  3566. }
  3567. old_state = to_sde_plane_state(plane->state);
  3568. psde = to_sde_plane(plane);
  3569. pstate = msm_property_alloc_state(&psde->property_info);
  3570. if (!pstate) {
  3571. SDE_ERROR_PLANE(psde, "failed to allocate state\n");
  3572. return NULL;
  3573. }
  3574. SDE_DEBUG_PLANE(psde, "\n");
  3575. /* duplicate value helper */
  3576. msm_property_duplicate_state(&psde->property_info, old_state, pstate,
  3577. &pstate->property_state, pstate->property_values);
  3578. /* clear out any input fence */
  3579. pstate->input_fence = 0;
  3580. input_fence_default = msm_property_get_default(
  3581. &psde->property_info, PLANE_PROP_INPUT_FENCE);
  3582. drm_prop = msm_property_index_to_drm_property(
  3583. &psde->property_info, PLANE_PROP_INPUT_FENCE);
  3584. if (msm_property_atomic_set(&psde->property_info,
  3585. &pstate->property_state, drm_prop,
  3586. input_fence_default))
  3587. SDE_DEBUG_PLANE(psde,
  3588. "error clearing duplicated input fence\n");
  3589. pstate->dirty = 0x0;
  3590. pstate->pending = false;
  3591. __drm_atomic_helper_plane_duplicate_state(plane, &pstate->base);
  3592. /* reset layout offset */
  3593. if (pstate->layout_offset) {
  3594. if (pstate->layout_offset > 0)
  3595. pstate->base.crtc_x += pstate->layout_offset;
  3596. pstate->layout = SDE_LAYOUT_NONE;
  3597. pstate->layout_offset = 0;
  3598. }
  3599. return &pstate->base;
  3600. }
  3601. static void sde_plane_reset(struct drm_plane *plane)
  3602. {
  3603. struct sde_plane *psde;
  3604. struct sde_plane_state *pstate;
  3605. if (!plane) {
  3606. SDE_ERROR("invalid plane\n");
  3607. return;
  3608. }
  3609. psde = to_sde_plane(plane);
  3610. SDE_DEBUG_PLANE(psde, "\n");
  3611. if (plane->state && !sde_crtc_is_reset_required(plane->state->crtc)) {
  3612. SDE_DEBUG_PLANE(psde, "avoid reset for plane\n");
  3613. return;
  3614. }
  3615. /* remove previous state, if present */
  3616. if (plane->state) {
  3617. sde_plane_destroy_state(plane, plane->state);
  3618. plane->state = 0;
  3619. }
  3620. pstate = msm_property_alloc_state(&psde->property_info);
  3621. if (!pstate) {
  3622. SDE_ERROR_PLANE(psde, "failed to allocate state\n");
  3623. return;
  3624. }
  3625. /* reset value helper */
  3626. msm_property_reset_state(&psde->property_info, pstate,
  3627. &pstate->property_state,
  3628. pstate->property_values);
  3629. pstate->base.plane = plane;
  3630. plane->state = &pstate->base;
  3631. }
  3632. u32 sde_plane_get_ubwc_error(struct drm_plane *plane)
  3633. {
  3634. u32 ubwc_error = 0;
  3635. struct sde_plane *psde;
  3636. if (!plane) {
  3637. SDE_ERROR("invalid plane\n");
  3638. return 0;
  3639. }
  3640. psde = to_sde_plane(plane);
  3641. if (!psde->is_virtual && psde->pipe_hw->ops.get_ubwc_error)
  3642. ubwc_error = psde->pipe_hw->ops.get_ubwc_error(psde->pipe_hw);
  3643. return ubwc_error;
  3644. }
  3645. void sde_plane_clear_ubwc_error(struct drm_plane *plane)
  3646. {
  3647. struct sde_plane *psde;
  3648. if (!plane) {
  3649. SDE_ERROR("invalid plane\n");
  3650. return;
  3651. }
  3652. psde = to_sde_plane(plane);
  3653. if (psde->pipe_hw->ops.clear_ubwc_error)
  3654. psde->pipe_hw->ops.clear_ubwc_error(psde->pipe_hw);
  3655. }
  3656. #ifdef CONFIG_DEBUG_FS
  3657. static ssize_t _sde_plane_danger_read(struct file *file,
  3658. char __user *buff, size_t count, loff_t *ppos)
  3659. {
  3660. struct sde_kms *kms = file->private_data;
  3661. struct sde_mdss_cfg *cfg = kms->catalog;
  3662. int len = 0;
  3663. char buf[40] = {'\0'};
  3664. if (!cfg)
  3665. return -ENODEV;
  3666. if (*ppos)
  3667. return 0; /* the end */
  3668. len = snprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl);
  3669. if (len < 0 || len >= sizeof(buf))
  3670. return 0;
  3671. if ((count < sizeof(buf)) || copy_to_user(buff, buf, len))
  3672. return -EFAULT;
  3673. *ppos += len; /* increase offset */
  3674. return len;
  3675. }
  3676. static void _sde_plane_set_danger_state(struct sde_kms *kms, bool enable)
  3677. {
  3678. struct drm_plane *plane;
  3679. drm_for_each_plane(plane, kms->dev) {
  3680. if (plane->fb && plane->state) {
  3681. sde_plane_danger_signal_ctrl(plane, enable);
  3682. SDE_DEBUG("plane:%d img:%dx%d ",
  3683. plane->base.id, plane->fb->width,
  3684. plane->fb->height);
  3685. SDE_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n",
  3686. plane->state->src_x >> 16,
  3687. plane->state->src_y >> 16,
  3688. plane->state->src_w >> 16,
  3689. plane->state->src_h >> 16,
  3690. plane->state->crtc_x, plane->state->crtc_y,
  3691. plane->state->crtc_w, plane->state->crtc_h);
  3692. } else {
  3693. SDE_DEBUG("Inactive plane:%d\n", plane->base.id);
  3694. }
  3695. }
  3696. }
  3697. static ssize_t _sde_plane_danger_write(struct file *file,
  3698. const char __user *user_buf, size_t count, loff_t *ppos)
  3699. {
  3700. struct sde_kms *kms = file->private_data;
  3701. struct sde_mdss_cfg *cfg = kms->catalog;
  3702. int disable_panic;
  3703. char buf[10];
  3704. if (!cfg)
  3705. return -EFAULT;
  3706. if (count >= sizeof(buf))
  3707. return -EFAULT;
  3708. if (copy_from_user(buf, user_buf, count))
  3709. return -EFAULT;
  3710. buf[count] = 0; /* end of string */
  3711. if (kstrtoint(buf, 0, &disable_panic))
  3712. return -EFAULT;
  3713. if (disable_panic) {
  3714. /* Disable panic signal for all active pipes */
  3715. SDE_DEBUG("Disabling danger:\n");
  3716. _sde_plane_set_danger_state(kms, false);
  3717. kms->has_danger_ctrl = false;
  3718. } else {
  3719. /* Enable panic signal for all active pipes */
  3720. SDE_DEBUG("Enabling danger:\n");
  3721. kms->has_danger_ctrl = true;
  3722. _sde_plane_set_danger_state(kms, true);
  3723. }
  3724. return count;
  3725. }
  3726. static const struct file_operations sde_plane_danger_enable = {
  3727. .open = simple_open,
  3728. .read = _sde_plane_danger_read,
  3729. .write = _sde_plane_danger_write,
  3730. };
  3731. static int _sde_plane_init_debugfs(struct drm_plane *plane)
  3732. {
  3733. struct sde_plane *psde;
  3734. struct sde_kms *kms;
  3735. struct msm_drm_private *priv;
  3736. const struct sde_sspp_sub_blks *sblk = 0;
  3737. const struct sde_sspp_cfg *cfg = 0;
  3738. if (!plane || !plane->dev) {
  3739. SDE_ERROR("invalid arguments\n");
  3740. return -EINVAL;
  3741. }
  3742. priv = plane->dev->dev_private;
  3743. if (!priv || !priv->kms) {
  3744. SDE_ERROR("invalid KMS reference\n");
  3745. return -EINVAL;
  3746. }
  3747. kms = to_sde_kms(priv->kms);
  3748. psde = to_sde_plane(plane);
  3749. if (psde && psde->pipe_hw)
  3750. cfg = psde->pipe_hw->cap;
  3751. if (cfg)
  3752. sblk = cfg->sblk;
  3753. if (!sblk)
  3754. return 0;
  3755. /* create overall sub-directory for the pipe */
  3756. psde->debugfs_root =
  3757. debugfs_create_dir(psde->pipe_name,
  3758. plane->dev->primary->debugfs_root);
  3759. if (!psde->debugfs_root)
  3760. return -ENOMEM;
  3761. /* don't error check these */
  3762. debugfs_create_x32("features", 0400,
  3763. psde->debugfs_root, &psde->features);
  3764. if (cfg->features & BIT(SDE_SSPP_SCALER_QSEED3) ||
  3765. cfg->features & BIT(SDE_SSPP_SCALER_QSEED3LITE) ||
  3766. cfg->features & BIT(SDE_SSPP_SCALER_QSEED2))
  3767. debugfs_create_bool("default_scaling",
  3768. 0600,
  3769. psde->debugfs_root,
  3770. &psde->debugfs_default_scale);
  3771. if (cfg->features & BIT(SDE_SSPP_TRUE_INLINE_ROT)) {
  3772. debugfs_create_u32("in_rot_max_downscale_rt_num",
  3773. 0600,
  3774. psde->debugfs_root,
  3775. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_rt_num);
  3776. debugfs_create_u32("in_rot_max_downscale_rt_denom",
  3777. 0600,
  3778. psde->debugfs_root,
  3779. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_rt_denom);
  3780. debugfs_create_u32("in_rot_max_downscale_nrt",
  3781. 0600,
  3782. psde->debugfs_root,
  3783. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_nrt);
  3784. debugfs_create_u32("in_rot_max_height",
  3785. 0600,
  3786. psde->debugfs_root,
  3787. (u32 *) &psde->pipe_sblk->in_rot_maxheight);
  3788. }
  3789. debugfs_create_u32("xin_id",
  3790. 0400,
  3791. psde->debugfs_root,
  3792. (u32 *) &cfg->xin_id);
  3793. debugfs_create_x32("creq_vblank",
  3794. 0600,
  3795. psde->debugfs_root,
  3796. (u32 *) &sblk->creq_vblank);
  3797. debugfs_create_x32("danger_vblank",
  3798. 0600,
  3799. psde->debugfs_root,
  3800. (u32 *) &sblk->danger_vblank);
  3801. debugfs_create_file("disable_danger",
  3802. 0600,
  3803. psde->debugfs_root,
  3804. kms, &sde_plane_danger_enable);
  3805. return 0;
  3806. }
  3807. static void _sde_plane_destroy_debugfs(struct drm_plane *plane)
  3808. {
  3809. struct sde_plane *psde;
  3810. if (!plane)
  3811. return;
  3812. psde = to_sde_plane(plane);
  3813. debugfs_remove_recursive(psde->debugfs_root);
  3814. }
  3815. #else
  3816. static int _sde_plane_init_debugfs(struct drm_plane *plane)
  3817. {
  3818. return 0;
  3819. }
  3820. static void _sde_plane_destroy_debugfs(struct drm_plane *plane)
  3821. {
  3822. }
  3823. #endif
  3824. static int sde_plane_late_register(struct drm_plane *plane)
  3825. {
  3826. return _sde_plane_init_debugfs(plane);
  3827. }
  3828. static void sde_plane_early_unregister(struct drm_plane *plane)
  3829. {
  3830. _sde_plane_destroy_debugfs(plane);
  3831. }
  3832. static const struct drm_plane_funcs sde_plane_funcs = {
  3833. .update_plane = drm_atomic_helper_update_plane,
  3834. .disable_plane = drm_atomic_helper_disable_plane,
  3835. .destroy = sde_plane_destroy,
  3836. .atomic_set_property = sde_plane_atomic_set_property,
  3837. .atomic_get_property = sde_plane_atomic_get_property,
  3838. .reset = sde_plane_reset,
  3839. .atomic_duplicate_state = sde_plane_duplicate_state,
  3840. .atomic_destroy_state = sde_plane_destroy_state,
  3841. .late_register = sde_plane_late_register,
  3842. .early_unregister = sde_plane_early_unregister,
  3843. };
  3844. static const struct drm_plane_helper_funcs sde_plane_helper_funcs = {
  3845. .prepare_fb = sde_plane_prepare_fb,
  3846. .cleanup_fb = sde_plane_cleanup_fb,
  3847. .atomic_check = sde_plane_atomic_check,
  3848. .atomic_update = sde_plane_atomic_update,
  3849. };
  3850. enum sde_sspp sde_plane_pipe(struct drm_plane *plane)
  3851. {
  3852. return plane ? to_sde_plane(plane)->pipe : SSPP_NONE;
  3853. }
  3854. bool is_sde_plane_virtual(struct drm_plane *plane)
  3855. {
  3856. return plane ? to_sde_plane(plane)->is_virtual : false;
  3857. }
  3858. /* initialize plane */
  3859. struct drm_plane *sde_plane_init(struct drm_device *dev,
  3860. uint32_t pipe, bool primary_plane,
  3861. unsigned long possible_crtcs, u32 master_plane_id)
  3862. {
  3863. struct drm_plane *plane = NULL, *master_plane = NULL;
  3864. const struct sde_format_extended *format_list;
  3865. struct sde_plane *psde;
  3866. struct msm_drm_private *priv;
  3867. struct sde_kms *kms;
  3868. enum drm_plane_type type;
  3869. int ret = -EINVAL;
  3870. if (!dev) {
  3871. SDE_ERROR("[%u]device is NULL\n", pipe);
  3872. goto exit;
  3873. }
  3874. priv = dev->dev_private;
  3875. if (!priv) {
  3876. SDE_ERROR("[%u]private data is NULL\n", pipe);
  3877. goto exit;
  3878. }
  3879. if (!priv->kms) {
  3880. SDE_ERROR("[%u]invalid KMS reference\n", pipe);
  3881. goto exit;
  3882. }
  3883. kms = to_sde_kms(priv->kms);
  3884. if (!kms->catalog) {
  3885. SDE_ERROR("[%u]invalid catalog reference\n", pipe);
  3886. goto exit;
  3887. }
  3888. /* create and zero local structure */
  3889. psde = kzalloc(sizeof(*psde), GFP_KERNEL);
  3890. if (!psde) {
  3891. SDE_ERROR("[%u]failed to allocate local plane struct\n", pipe);
  3892. ret = -ENOMEM;
  3893. goto exit;
  3894. }
  3895. /* cache local stuff for later */
  3896. plane = &psde->base;
  3897. psde->pipe = pipe;
  3898. psde->is_virtual = (master_plane_id != 0);
  3899. INIT_LIST_HEAD(&psde->mplane_list);
  3900. master_plane = drm_plane_find(dev, NULL, master_plane_id);
  3901. if (master_plane) {
  3902. struct sde_plane *mpsde = to_sde_plane(master_plane);
  3903. list_add_tail(&psde->mplane_list, &mpsde->mplane_list);
  3904. }
  3905. /* initialize underlying h/w driver */
  3906. psde->pipe_hw = sde_hw_sspp_init(pipe, kms->mmio, kms->catalog,
  3907. psde->is_virtual);
  3908. if (IS_ERR(psde->pipe_hw)) {
  3909. SDE_ERROR("[%u]SSPP init failed\n", pipe);
  3910. ret = PTR_ERR(psde->pipe_hw);
  3911. goto clean_plane;
  3912. } else if (!psde->pipe_hw->cap || !psde->pipe_hw->cap->sblk) {
  3913. SDE_ERROR("[%u]SSPP init returned invalid cfg\n", pipe);
  3914. goto clean_sspp;
  3915. }
  3916. /* cache features mask for later */
  3917. psde->features = psde->pipe_hw->cap->features;
  3918. psde->perf_features = psde->pipe_hw->cap->perf_features;
  3919. psde->pipe_sblk = psde->pipe_hw->cap->sblk;
  3920. if (!psde->pipe_sblk) {
  3921. SDE_ERROR("[%u]invalid sblk\n", pipe);
  3922. goto clean_sspp;
  3923. }
  3924. if (psde->is_virtual)
  3925. format_list = psde->pipe_sblk->virt_format_list;
  3926. else
  3927. format_list = psde->pipe_sblk->format_list;
  3928. psde->nformats = sde_populate_formats(format_list,
  3929. psde->formats,
  3930. 0,
  3931. ARRAY_SIZE(psde->formats));
  3932. if (!psde->nformats) {
  3933. SDE_ERROR("[%u]no valid formats for plane\n", pipe);
  3934. goto clean_sspp;
  3935. }
  3936. if (psde->features & BIT(SDE_SSPP_CURSOR))
  3937. type = DRM_PLANE_TYPE_CURSOR;
  3938. else if (primary_plane)
  3939. type = DRM_PLANE_TYPE_PRIMARY;
  3940. else
  3941. type = DRM_PLANE_TYPE_OVERLAY;
  3942. ret = drm_universal_plane_init(dev, plane, 0xff, &sde_plane_funcs,
  3943. psde->formats, psde->nformats,
  3944. NULL, type, NULL);
  3945. if (ret)
  3946. goto clean_sspp;
  3947. /* Populate static array of plane property flags */
  3948. _sde_plane_map_prop_to_dirty_bits();
  3949. /* success! finalize initialization */
  3950. drm_plane_helper_add(plane, &sde_plane_helper_funcs);
  3951. msm_property_init(&psde->property_info, &plane->base, dev,
  3952. priv->plane_property, psde->property_data,
  3953. PLANE_PROP_COUNT, PLANE_PROP_BLOBCOUNT,
  3954. sizeof(struct sde_plane_state));
  3955. _sde_plane_install_properties(plane, kms->catalog, master_plane_id);
  3956. /* save user friendly pipe name for later */
  3957. snprintf(psde->pipe_name, SDE_NAME_SIZE, "plane%u", plane->base.id);
  3958. mutex_init(&psde->lock);
  3959. SDE_DEBUG("%s created for pipe:%u id:%u master:%u\n", psde->pipe_name,
  3960. pipe, plane->base.id, master_plane_id);
  3961. return plane;
  3962. clean_sspp:
  3963. if (psde && psde->pipe_hw)
  3964. sde_hw_sspp_destroy(psde->pipe_hw);
  3965. clean_plane:
  3966. kfree(psde);
  3967. exit:
  3968. return ERR_PTR(ret);
  3969. }