d4846129c1
Add qcn9224 v2 HW headers and move v1 headers to qca9224/v1 dir. Change-Id: Ieba3f50dd1160e8fe3017eb8656f993456ca410a CRs-Fixed: 3247610
185 řádky
8.7 KiB
C
185 řádky
8.7 KiB
C
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/* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _TX_FES_STATUS_START_H_
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#define _TX_FES_STATUS_START_H_
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#if !defined(__ASSEMBLER__)
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#endif
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#define NUM_OF_DWORDS_TX_FES_STATUS_START 4
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#define NUM_OF_QWORDS_TX_FES_STATUS_START 2
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struct tx_fes_status_start {
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#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
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uint32_t schedule_id : 32;
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uint32_t reserved_1a : 8,
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transmit_start_reason : 3,
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disabled_user_bitmap_36_32 : 5,
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schedule_cmd_ring_id : 5,
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fes_control_mode : 2,
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schedule_try : 4,
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medium_prot_type : 3,
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reserved_1b : 2;
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uint32_t optimal_bw_try_count : 4,
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number_of_users : 7,
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coex_nack_count : 5,
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cca_ed0 : 16;
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uint32_t disabled_user_bitmap_31_0 : 32;
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#else
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uint32_t schedule_id : 32;
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uint32_t reserved_1b : 2,
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medium_prot_type : 3,
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schedule_try : 4,
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fes_control_mode : 2,
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schedule_cmd_ring_id : 5,
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disabled_user_bitmap_36_32 : 5,
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transmit_start_reason : 3,
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reserved_1a : 8;
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uint32_t cca_ed0 : 16,
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coex_nack_count : 5,
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number_of_users : 7,
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optimal_bw_try_count : 4;
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uint32_t disabled_user_bitmap_31_0 : 32;
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#endif
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};
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#define TX_FES_STATUS_START_SCHEDULE_ID_OFFSET 0x0000000000000000
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#define TX_FES_STATUS_START_SCHEDULE_ID_LSB 0
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#define TX_FES_STATUS_START_SCHEDULE_ID_MSB 31
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#define TX_FES_STATUS_START_SCHEDULE_ID_MASK 0x00000000ffffffff
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#define TX_FES_STATUS_START_RESERVED_1A_OFFSET 0x0000000000000000
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#define TX_FES_STATUS_START_RESERVED_1A_LSB 32
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#define TX_FES_STATUS_START_RESERVED_1A_MSB 39
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#define TX_FES_STATUS_START_RESERVED_1A_MASK 0x000000ff00000000
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#define TX_FES_STATUS_START_TRANSMIT_START_REASON_OFFSET 0x0000000000000000
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#define TX_FES_STATUS_START_TRANSMIT_START_REASON_LSB 40
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#define TX_FES_STATUS_START_TRANSMIT_START_REASON_MSB 42
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#define TX_FES_STATUS_START_TRANSMIT_START_REASON_MASK 0x0000070000000000
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#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_OFFSET 0x0000000000000000
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#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_LSB 43
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#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_MSB 47
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#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_MASK 0x0000f80000000000
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#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_OFFSET 0x0000000000000000
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#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_LSB 48
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#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_MSB 52
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#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_MASK 0x001f000000000000
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#define TX_FES_STATUS_START_FES_CONTROL_MODE_OFFSET 0x0000000000000000
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#define TX_FES_STATUS_START_FES_CONTROL_MODE_LSB 53
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#define TX_FES_STATUS_START_FES_CONTROL_MODE_MSB 54
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#define TX_FES_STATUS_START_FES_CONTROL_MODE_MASK 0x0060000000000000
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#define TX_FES_STATUS_START_SCHEDULE_TRY_OFFSET 0x0000000000000000
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#define TX_FES_STATUS_START_SCHEDULE_TRY_LSB 55
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#define TX_FES_STATUS_START_SCHEDULE_TRY_MSB 58
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#define TX_FES_STATUS_START_SCHEDULE_TRY_MASK 0x0780000000000000
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#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_OFFSET 0x0000000000000000
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#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_LSB 59
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#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_MSB 61
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#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_MASK 0x3800000000000000
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#define TX_FES_STATUS_START_RESERVED_1B_OFFSET 0x0000000000000000
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#define TX_FES_STATUS_START_RESERVED_1B_LSB 62
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#define TX_FES_STATUS_START_RESERVED_1B_MSB 63
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#define TX_FES_STATUS_START_RESERVED_1B_MASK 0xc000000000000000
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#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_OFFSET 0x0000000000000008
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#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_LSB 0
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#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_MSB 3
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#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_MASK 0x000000000000000f
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#define TX_FES_STATUS_START_NUMBER_OF_USERS_OFFSET 0x0000000000000008
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#define TX_FES_STATUS_START_NUMBER_OF_USERS_LSB 4
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#define TX_FES_STATUS_START_NUMBER_OF_USERS_MSB 10
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#define TX_FES_STATUS_START_NUMBER_OF_USERS_MASK 0x00000000000007f0
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#define TX_FES_STATUS_START_COEX_NACK_COUNT_OFFSET 0x0000000000000008
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#define TX_FES_STATUS_START_COEX_NACK_COUNT_LSB 11
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#define TX_FES_STATUS_START_COEX_NACK_COUNT_MSB 15
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#define TX_FES_STATUS_START_COEX_NACK_COUNT_MASK 0x000000000000f800
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#define TX_FES_STATUS_START_CCA_ED0_OFFSET 0x0000000000000008
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#define TX_FES_STATUS_START_CCA_ED0_LSB 16
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#define TX_FES_STATUS_START_CCA_ED0_MSB 31
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#define TX_FES_STATUS_START_CCA_ED0_MASK 0x00000000ffff0000
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#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_OFFSET 0x0000000000000008
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#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_LSB 32
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#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_MSB 63
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#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_MASK 0xffffffff00000000
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#endif
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