c3fae0027c
Added qcn6432 target header files based on E3R47 under qcn6432 to make fw-api project compatible to host. Change-Id: I3bdf6298281323f4f0fe75aed04db93cd698ee1f CRs-Fixed: 3463782
102 خطوط
3.7 KiB
C
102 خطوط
3.7 KiB
C
/*
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _PHYRX_HE_SIG_B1_MU_H_
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#define _PHYRX_HE_SIG_B1_MU_H_
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#if !defined(__ASSEMBLER__)
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#endif
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#include "he_sig_b1_mu_info.h"
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#define NUM_OF_DWORDS_PHYRX_HE_SIG_B1_MU 2
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#define NUM_OF_QWORDS_PHYRX_HE_SIG_B1_MU 1
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struct phyrx_he_sig_b1_mu {
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#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
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struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details;
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uint32_t tlv64_padding : 32; // [31:0]
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#else
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struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details;
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uint32_t tlv64_padding : 32; // [31:0]
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#endif
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};
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/* Description PHYRX_HE_SIG_B1_MU_INFO_DETAILS
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See detailed description of the STRUCT
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*/
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/* Description RU_ALLOCATION
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RU allocation for the user(s) following this common portion
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of the SIG
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For details, refer to RU_TYPE description
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<legal all>
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*/
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#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 0x0000000000000000
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#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB 0
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#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB 7
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#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK 0x00000000000000ff
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/* Description RESERVED_0
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<legal 0>
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*/
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#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
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#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB 8
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#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB 30
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#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK 0x000000007fffff00
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/* Description RX_INTEGRITY_CHECK_PASSED
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TX side: Set to 0
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RX side: Set to 1 if PHY determines the CRC check of the
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codeblock containing the HE-SIG-B common info has passed,
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else set to 0
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<legal all>
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*/
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#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
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#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
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#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
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#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
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/* Description TLV64_PADDING
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Automatic DWORD padding inserted while converting TLV32
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to TLV64 for 64 bit ARCH
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<legal 0>
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*/
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#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_OFFSET 0x0000000000000000
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#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_LSB 32
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#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_MSB 63
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#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_MASK 0xffffffff00000000
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#endif // PHYRX_HE_SIG_B1_MU
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