android_kernel_samsung_sm8650-modules/hw/qcn6122/reo_reg_seq_hwioreg.h

/*
 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#ifndef __REO_REG_SEQ_REG_H__
#define __REO_REG_SEQ_REG_H__

#include "seq_hwio.h"
#include "reo_reg_seq_hwiobase.h"
#ifdef SCALE_INCLUDES
	#include "HALhwio.h"
#else
	#include "msmhwio.h"
#endif


///////////////////////////////////////////////////////////////////////////////////////////////
// Register Data for Block REO_REG
///////////////////////////////////////////////////////////////////////////////////////////////

//// Register REO_R0_GENERAL_ENABLE ////

#define HWIO_REO_R0_GENERAL_ENABLE_ADDR(x)                           (x+0x00000000)
#define HWIO_REO_R0_GENERAL_ENABLE_PHYS(x)                           (x+0x00000000)
#define HWIO_REO_R0_GENERAL_ENABLE_RMSK                              0xfbffff7f
#define HWIO_REO_R0_GENERAL_ENABLE_SHFT                                       0
#define HWIO_REO_R0_GENERAL_ENABLE_IN(x)                             \
	in_dword_masked ( HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), HWIO_REO_R0_GENERAL_ENABLE_RMSK)
#define HWIO_REO_R0_GENERAL_ENABLE_INM(x, mask)                      \
	in_dword_masked ( HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), mask) 
#define HWIO_REO_R0_GENERAL_ENABLE_OUT(x, val)                       \
	out_dword( HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), val)
#define HWIO_REO_R0_GENERAL_ENABLE_OUTM(x, mask, val)                \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), mask, val, HWIO_REO_R0_GENERAL_ENABLE_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_GENERAL_ENABLE_SW2REO1_RING_ENABLE_BMSK          0x80000000
#define HWIO_REO_R0_GENERAL_ENABLE_SW2REO1_RING_ENABLE_SHFT                0x1f

#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW6_RING_ENABLE_BMSK          0x40000000
#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW6_RING_ENABLE_SHFT                0x1e

#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW5_RING_ENABLE_BMSK          0x20000000
#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW5_RING_ENABLE_SHFT                0x1d

#define HWIO_REO_R0_GENERAL_ENABLE_INVALIDATE_CACHE_FOR_ZERO_VLD_BMSK 0x10000000
#define HWIO_REO_R0_GENERAL_ENABLE_INVALIDATE_CACHE_FOR_ZERO_VLD_SHFT       0x1c

#define HWIO_REO_R0_GENERAL_ENABLE_STRUCT_SWAP_DELINK_BMSK           0x08000000
#define HWIO_REO_R0_GENERAL_ENABLE_STRUCT_SWAP_DELINK_SHFT                 0x1b

#define HWIO_REO_R0_GENERAL_ENABLE_SOFT_REORDER_DEST_RING_BMSK       0x03800000
#define HWIO_REO_R0_GENERAL_ENABLE_SOFT_REORDER_DEST_RING_SHFT             0x17

#define HWIO_REO_R0_GENERAL_ENABLE_SW2REO_RING_ENABLE_BMSK           0x00400000
#define HWIO_REO_R0_GENERAL_ENABLE_SW2REO_RING_ENABLE_SHFT                 0x16

#define HWIO_REO_R0_GENERAL_ENABLE_REO_CMD_RING_ENABLE_BMSK          0x00200000
#define HWIO_REO_R0_GENERAL_ENABLE_REO_CMD_RING_ENABLE_SHFT                0x15

#define HWIO_REO_R0_GENERAL_ENABLE_REO_STATUS_RING_ENABLE_BMSK       0x00100000
#define HWIO_REO_R0_GENERAL_ENABLE_REO_STATUS_RING_ENABLE_SHFT             0x14

#define HWIO_REO_R0_GENERAL_ENABLE_REO_RELEASE_RING_ENABLE_BMSK      0x00080000
#define HWIO_REO_R0_GENERAL_ENABLE_REO_RELEASE_RING_ENABLE_SHFT            0x13

#define HWIO_REO_R0_GENERAL_ENABLE_REO2TCL_RING_ENABLE_BMSK          0x00040000
#define HWIO_REO_R0_GENERAL_ENABLE_REO2TCL_RING_ENABLE_SHFT                0x12

#define HWIO_REO_R0_GENERAL_ENABLE_REO2FW_RING_ENABLE_BMSK           0x00020000
#define HWIO_REO_R0_GENERAL_ENABLE_REO2FW_RING_ENABLE_SHFT                 0x11

#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW4_RING_ENABLE_BMSK          0x00010000
#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW4_RING_ENABLE_SHFT                0x10

#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW3_RING_ENABLE_BMSK          0x00008000
#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW3_RING_ENABLE_SHFT                 0xf

#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW2_RING_ENABLE_BMSK          0x00004000
#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW2_RING_ENABLE_SHFT                 0xe

#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW1_RING_ENABLE_BMSK          0x00002000
#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW1_RING_ENABLE_SHFT                 0xd

#define HWIO_REO_R0_GENERAL_ENABLE_WBM2REO_LINK_RING_ENABLE_BMSK     0x00001000
#define HWIO_REO_R0_GENERAL_ENABLE_WBM2REO_LINK_RING_ENABLE_SHFT            0xc

#define HWIO_REO_R0_GENERAL_ENABLE_RXDMA2REO_RING_ENABLE_BMSK        0x00000e00
#define HWIO_REO_R0_GENERAL_ENABLE_RXDMA2REO_RING_ENABLE_SHFT               0x9

#define HWIO_REO_R0_GENERAL_ENABLE_GLOBAL_PN_CHK_BMSK                0x00000100
#define HWIO_REO_R0_GENERAL_ENABLE_GLOBAL_PN_CHK_SHFT                       0x8

#define HWIO_REO_R0_GENERAL_ENABLE_BAR_DEST_RING_BMSK                0x00000070
#define HWIO_REO_R0_GENERAL_ENABLE_BAR_DEST_RING_SHFT                       0x4

#define HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK           0x00000008
#define HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_SHFT                  0x3

#define HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK            0x00000004
#define HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_SHFT                   0x2

#define HWIO_REO_R0_GENERAL_ENABLE_REO_HWREORDER_DISABLE_BMSK        0x00000002
#define HWIO_REO_R0_GENERAL_ENABLE_REO_HWREORDER_DISABLE_SHFT               0x1

#define HWIO_REO_R0_GENERAL_ENABLE_REO_ENABLE_BMSK                   0x00000001
#define HWIO_REO_R0_GENERAL_ENABLE_REO_ENABLE_SHFT                          0x0

//// Register REO_R0_DESTINATION_RING_CTRL_IX_0 ////

#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x)               (x+0x00000004)
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_PHYS(x)               (x+0x00000004)
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_RMSK                  0x77777777
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_SHFT                           0
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_IN(x)                 \
	in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_RMSK)
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_INM(x, mask)          \
	in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), mask) 
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_OUT(x, val)           \
	out_dword( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), val)
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_OUTM(x, mask, val)    \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_7_BMSK 0x70000000
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_7_SHFT       0x1c

#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_6_BMSK 0x07000000
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_6_SHFT       0x18

#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_5_BMSK 0x00700000
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_5_SHFT       0x14

#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_4_BMSK 0x00070000
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_4_SHFT       0x10

#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_3_BMSK 0x00007000
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_3_SHFT        0xc

#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_2_BMSK 0x00000700
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_2_SHFT        0x8

#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_1_BMSK 0x00000070
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_1_SHFT        0x4

#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_0_BMSK 0x00000007
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_0_SHFT        0x0

//// Register REO_R0_DESTINATION_RING_CTRL_IX_1 ////

#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x)               (x+0x00000008)
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_PHYS(x)               (x+0x00000008)
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_RMSK                  0x77777777
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_SHFT                           0
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_IN(x)                 \
	in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_RMSK)
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_INM(x, mask)          \
	in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), mask) 
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_OUT(x, val)           \
	out_dword( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), val)
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_OUTM(x, mask, val)    \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_15_BMSK 0x70000000
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_15_SHFT       0x1c

#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_14_BMSK 0x07000000
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_14_SHFT       0x18

#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_13_BMSK 0x00700000
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_13_SHFT       0x14

#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_12_BMSK 0x00070000
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_12_SHFT       0x10

#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_11_BMSK 0x00007000
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_11_SHFT        0xc

#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_10_BMSK 0x00000700
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_10_SHFT        0x8

#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_9_BMSK 0x00000070
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_9_SHFT        0x4

#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_8_BMSK 0x00000007
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_8_SHFT        0x0

//// Register REO_R0_DESTINATION_RING_CTRL_IX_2 ////

#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x)               (x+0x0000000c)
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_PHYS(x)               (x+0x0000000c)
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_RMSK                  0x77777777
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_SHFT                           0
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_IN(x)                 \
	in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_RMSK)
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_INM(x, mask)          \
	in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), mask) 
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_OUT(x, val)           \
	out_dword( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), val)
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_OUTM(x, mask, val)    \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_23_BMSK 0x70000000
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_23_SHFT       0x1c

#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_22_BMSK 0x07000000
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_22_SHFT       0x18

#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_21_BMSK 0x00700000
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_21_SHFT       0x14

#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_20_BMSK 0x00070000
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_20_SHFT       0x10

#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_19_BMSK 0x00007000
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_19_SHFT        0xc

#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_18_BMSK 0x00000700
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_18_SHFT        0x8

#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_17_BMSK 0x00000070
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_17_SHFT        0x4

#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_16_BMSK 0x00000007
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_16_SHFT        0x0

//// Register REO_R0_DESTINATION_RING_CTRL_IX_3 ////

#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x)               (x+0x00000010)
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_PHYS(x)               (x+0x00000010)
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_RMSK                  0x77777777
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_SHFT                           0
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_IN(x)                 \
	in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_RMSK)
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_INM(x, mask)          \
	in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), mask) 
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_OUT(x, val)           \
	out_dword( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), val)
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_OUTM(x, mask, val)    \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_31_BMSK 0x70000000
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_31_SHFT       0x1c

#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_30_BMSK 0x07000000
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_30_SHFT       0x18

#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_29_BMSK 0x00700000
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_29_SHFT       0x14

#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_28_BMSK 0x00070000
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_28_SHFT       0x10

#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_27_BMSK 0x00007000
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_27_SHFT        0xc

#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_26_BMSK 0x00000700
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_26_SHFT        0x8

#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_25_BMSK 0x00000070
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_25_SHFT        0x4

#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_24_BMSK 0x00000007
#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_24_SHFT        0x0

//// Register REO_R0_DESTINATION_RING_ALT_CTRL_IX_0 ////

#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x)           (x+0x00000014)
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_PHYS(x)           (x+0x00000014)
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_RMSK              0x77777777
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_SHFT                       0
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_IN(x)             \
	in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_RMSK)
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_INM(x, mask)      \
	in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), mask) 
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_OUT(x, val)       \
	out_dword( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), val)
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_7_BMSK 0x70000000
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_7_SHFT       0x1c

#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_6_BMSK 0x07000000
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_6_SHFT       0x18

#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_5_BMSK 0x00700000
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_5_SHFT       0x14

#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_4_BMSK 0x00070000
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_4_SHFT       0x10

#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_3_BMSK 0x00007000
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_3_SHFT        0xc

#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_2_BMSK 0x00000700
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_2_SHFT        0x8

#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_1_BMSK 0x00000070
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_1_SHFT        0x4

#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_0_BMSK 0x00000007
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_0_SHFT        0x0

//// Register REO_R0_DESTINATION_RING_ALT_CTRL_IX_1 ////

#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x)           (x+0x00000018)
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_PHYS(x)           (x+0x00000018)
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_RMSK              0x77777777
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_SHFT                       0
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_IN(x)             \
	in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_RMSK)
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_INM(x, mask)      \
	in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), mask) 
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_OUT(x, val)       \
	out_dword( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), val)
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_15_BMSK 0x70000000
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_15_SHFT       0x1c

#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_14_BMSK 0x07000000
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_14_SHFT       0x18

#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_13_BMSK 0x00700000
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_13_SHFT       0x14

#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_12_BMSK 0x00070000
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_12_SHFT       0x10

#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_11_BMSK 0x00007000
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_11_SHFT        0xc

#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_10_BMSK 0x00000700
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_10_SHFT        0x8

#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_9_BMSK 0x00000070
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_9_SHFT        0x4

#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_8_BMSK 0x00000007
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_8_SHFT        0x0

//// Register REO_R0_DESTINATION_RING_ALT_CTRL_IX_2 ////

#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x)           (x+0x0000001c)
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_PHYS(x)           (x+0x0000001c)
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_RMSK              0x77777777
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_SHFT                       0
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_IN(x)             \
	in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_RMSK)
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_INM(x, mask)      \
	in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), mask) 
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_OUT(x, val)       \
	out_dword( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), val)
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_23_BMSK 0x70000000
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_23_SHFT       0x1c

#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_22_BMSK 0x07000000
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_22_SHFT       0x18

#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_21_BMSK 0x00700000
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_21_SHFT       0x14

#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_20_BMSK 0x00070000
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_20_SHFT       0x10

#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_19_BMSK 0x00007000
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_19_SHFT        0xc

#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_18_BMSK 0x00000700
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_18_SHFT        0x8

#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_17_BMSK 0x00000070
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_17_SHFT        0x4

#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_16_BMSK 0x00000007
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_16_SHFT        0x0

//// Register REO_R0_DESTINATION_RING_ALT_CTRL_IX_3 ////

#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x)           (x+0x00000020)
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_PHYS(x)           (x+0x00000020)
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_RMSK              0x77777777
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_SHFT                       0
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_IN(x)             \
	in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_RMSK)
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_INM(x, mask)      \
	in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), mask) 
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_OUT(x, val)       \
	out_dword( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), val)
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_31_BMSK 0x70000000
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_31_SHFT       0x1c

#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_30_BMSK 0x07000000
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_30_SHFT       0x18

#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_29_BMSK 0x00700000
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_29_SHFT       0x14

#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_28_BMSK 0x00070000
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_28_SHFT       0x10

#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_27_BMSK 0x00007000
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_27_SHFT        0xc

#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_26_BMSK 0x00000700
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_26_SHFT        0x8

#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_25_BMSK 0x00000070
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_25_SHFT        0x4

#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_24_BMSK 0x00000007
#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_24_SHFT        0x0

//// Register REO_R0_TIMESTAMP ////

#define HWIO_REO_R0_TIMESTAMP_ADDR(x)                                (x+0x00000024)
#define HWIO_REO_R0_TIMESTAMP_PHYS(x)                                (x+0x00000024)
#define HWIO_REO_R0_TIMESTAMP_RMSK                                   0xffffffff
#define HWIO_REO_R0_TIMESTAMP_SHFT                                            0
#define HWIO_REO_R0_TIMESTAMP_IN(x)                                  \
	in_dword_masked ( HWIO_REO_R0_TIMESTAMP_ADDR(x), HWIO_REO_R0_TIMESTAMP_RMSK)
#define HWIO_REO_R0_TIMESTAMP_INM(x, mask)                           \
	in_dword_masked ( HWIO_REO_R0_TIMESTAMP_ADDR(x), mask) 
#define HWIO_REO_R0_TIMESTAMP_OUT(x, val)                            \
	out_dword( HWIO_REO_R0_TIMESTAMP_ADDR(x), val)
#define HWIO_REO_R0_TIMESTAMP_OUTM(x, mask, val)                     \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_TIMESTAMP_ADDR(x), mask, val, HWIO_REO_R0_TIMESTAMP_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_TIMESTAMP_TIMESTAMP_BMSK                         0xffffffff
#define HWIO_REO_R0_TIMESTAMP_TIMESTAMP_SHFT                                0x0

//// Register REO_R0_ERROR_DESTINATION_MAPPING_IX_0 ////

#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x)           (x+0x00000028)
#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_PHYS(x)           (x+0x00000028)
#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_RMSK              0x77777777
#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_SHFT                       0
#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_IN(x)             \
	in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_RMSK)
#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_INM(x, mask)      \
	in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), mask) 
#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_OUT(x, val)       \
	out_dword( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), val)
#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), mask, val, HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_BMSK 0x70000000
#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_SHFT       0x1c

#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_BMSK 0x07000000
#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_SHFT       0x18

#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_BMSK 0x00700000
#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_SHFT       0x14

#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_BMSK 0x00070000
#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_SHFT       0x10

#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_BMSK 0x00007000
#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_SHFT        0xc

#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_BMSK 0x00000700
#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_SHFT        0x8

#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_BMSK 0x00000070
#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_SHFT        0x4

#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_BMSK 0x00000007
#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_SHFT        0x0

//// Register REO_R0_ERROR_DESTINATION_MAPPING_IX_1 ////

#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x)           (x+0x0000002c)
#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_PHYS(x)           (x+0x0000002c)
#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_RMSK              0x77777777
#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_SHFT                       0
#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_IN(x)             \
	in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_RMSK)
#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_INM(x, mask)      \
	in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), mask) 
#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_OUT(x, val)       \
	out_dword( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), val)
#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), mask, val, HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_OTHER_BMSK 0x70000000
#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_OTHER_SHFT       0x1c

#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_14_BMSK 0x07000000
#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_14_SHFT       0x18

#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_13_BMSK 0x00700000
#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_13_SHFT       0x14

#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_12_BMSK 0x00070000
#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_12_SHFT       0x10

#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_11_BMSK 0x00007000
#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_11_SHFT        0xc

#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_10_BMSK 0x00000700
#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_10_SHFT        0x8

#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_9_BMSK 0x00000070
#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_9_SHFT        0x4

#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_8_BMSK 0x00000007
#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_8_SHFT        0x0

//// Register REO_R0_IDLE_REQ_CTRL ////

#define HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x)                            (x+0x00000030)
#define HWIO_REO_R0_IDLE_REQ_CTRL_PHYS(x)                            (x+0x00000030)
#define HWIO_REO_R0_IDLE_REQ_CTRL_RMSK                               0x00000003
#define HWIO_REO_R0_IDLE_REQ_CTRL_SHFT                                        0
#define HWIO_REO_R0_IDLE_REQ_CTRL_IN(x)                              \
	in_dword_masked ( HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), HWIO_REO_R0_IDLE_REQ_CTRL_RMSK)
#define HWIO_REO_R0_IDLE_REQ_CTRL_INM(x, mask)                       \
	in_dword_masked ( HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), mask) 
#define HWIO_REO_R0_IDLE_REQ_CTRL_OUT(x, val)                        \
	out_dword( HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), val)
#define HWIO_REO_R0_IDLE_REQ_CTRL_OUTM(x, mask, val)                 \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), mask, val, HWIO_REO_R0_IDLE_REQ_CTRL_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_CACHE_BMSK          0x00000002
#define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_CACHE_SHFT                 0x1

#define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_AGE_LIST_BMSK       0x00000001
#define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_AGE_LIST_SHFT              0x0

//// Register REO_R0_RXDMA2REO0_RING_BASE_LSB ////

#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x)                 (x+0x00000034)
#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_PHYS(x)                 (x+0x00000034)
#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RMSK                    0xffffffff
#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_SHFT                             0
#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_IN(x)                   \
	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RMSK)
#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_INM(x, mask)            \
	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), mask) 
#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_OUT(x, val)             \
	out_dword( HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), val)
#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_OUTM(x, mask, val)      \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT        0x0

//// Register REO_R0_RXDMA2REO0_RING_BASE_MSB ////

#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x)                 (x+0x00000038)
#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_PHYS(x)                 (x+0x00000038)
#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RMSK                    0x00ffffff
#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_SHFT                             0
#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_IN(x)                   \
	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RMSK)
#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_INM(x, mask)            \
	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), mask) 
#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_OUT(x, val)             \
	out_dword( HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), val)
#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_OUTM(x, mask, val)      \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_SIZE_BMSK          0x00ffff00
#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_SIZE_SHFT                 0x8

#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT        0x0

//// Register REO_R0_RXDMA2REO0_RING_ID ////

#define HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x)                       (x+0x0000003c)
#define HWIO_REO_R0_RXDMA2REO0_RING_ID_PHYS(x)                       (x+0x0000003c)
#define HWIO_REO_R0_RXDMA2REO0_RING_ID_RMSK                          0x000000ff
#define HWIO_REO_R0_RXDMA2REO0_RING_ID_SHFT                                   0
#define HWIO_REO_R0_RXDMA2REO0_RING_ID_IN(x)                         \
	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_ID_RMSK)
#define HWIO_REO_R0_RXDMA2REO0_RING_ID_INM(x, mask)                  \
	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), mask) 
#define HWIO_REO_R0_RXDMA2REO0_RING_ID_OUT(x, val)                   \
	out_dword( HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), val)
#define HWIO_REO_R0_RXDMA2REO0_RING_ID_OUTM(x, mask, val)            \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_ID_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_RXDMA2REO0_RING_ID_ENTRY_SIZE_BMSK               0x000000ff
#define HWIO_REO_R0_RXDMA2REO0_RING_ID_ENTRY_SIZE_SHFT                      0x0

//// Register REO_R0_RXDMA2REO0_RING_STATUS ////

#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x)                   (x+0x00000040)
#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_PHYS(x)                   (x+0x00000040)
#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_RMSK                      0xffffffff
#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_SHFT                               0
#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_IN(x)                     \
	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_STATUS_RMSK)
#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_INM(x, mask)              \
	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), mask) 
#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_OUT(x, val)               \
	out_dword( HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), val)
#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_OUTM(x, mask, val)        \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_STATUS_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_AVAIL_WORDS_BMSK      0xffff0000
#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_AVAIL_WORDS_SHFT            0x10

#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_VALID_WORDS_BMSK      0x0000ffff
#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_VALID_WORDS_SHFT             0x0

//// Register REO_R0_RXDMA2REO0_RING_MISC ////

#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x)                     (x+0x00000044)
#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_PHYS(x)                     (x+0x00000044)
#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_RMSK                        0x003fffff
#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SHFT                                 0
#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_IN(x)                       \
	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_MISC_RMSK)
#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_INM(x, mask)                \
	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), mask) 
#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_OUT(x, val)                 \
	out_dword( HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), val)
#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_OUTM(x, mask, val)          \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_MISC_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SPARE_CONTROL_BMSK          0x003fc000
#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SPARE_CONTROL_SHFT                 0xe

#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_SM_STATE2_BMSK         0x00003000
#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_SM_STATE2_SHFT                0xc

#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_SM_STATE1_BMSK         0x00000f00
#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_SM_STATE1_SHFT                0x8

#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_IS_IDLE_BMSK           0x00000080
#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_IS_IDLE_SHFT                  0x7

#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_ENABLE_BMSK            0x00000040
#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_ENABLE_SHFT                   0x6

#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_DATA_TLV_SWAP_BIT_BMSK      0x00000020
#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_DATA_TLV_SWAP_BIT_SHFT             0x5

#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_HOST_FW_SWAP_BIT_BMSK       0x00000010
#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_HOST_FW_SWAP_BIT_SHFT              0x4

#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_MSI_SWAP_BIT_BMSK           0x00000008
#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_MSI_SWAP_BIT_SHFT                  0x3

#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SECURITY_BIT_BMSK           0x00000004
#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SECURITY_BIT_SHFT                  0x2

#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_LOOPCNT_DISABLE_BMSK        0x00000002
#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_LOOPCNT_DISABLE_SHFT               0x1

#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_RING_ID_DISABLE_BMSK        0x00000001
#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_RING_ID_DISABLE_SHFT               0x0

//// Register REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB ////

#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x)              (x+0x00000050)
#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_PHYS(x)              (x+0x00000050)
#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_RMSK                 0xffffffff
#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_SHFT                          0
#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_IN(x)                \
	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_RMSK)
#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_INM(x, mask)         \
	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), mask) 
#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_OUT(x, val)          \
	out_dword( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), val)
#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_OUTM(x, mask, val)   \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT        0x0

//// Register REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB ////

#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x)              (x+0x00000054)
#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_PHYS(x)              (x+0x00000054)
#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_RMSK                 0x000000ff
#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_SHFT                          0
#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_IN(x)                \
	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_RMSK)
#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_INM(x, mask)         \
	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), mask) 
#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_OUT(x, val)          \
	out_dword( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), val)
#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_OUTM(x, mask, val)   \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT        0x0

//// Register REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0 ////

#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)   (x+0x00000064)
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_PHYS(x)   (x+0x00000064)
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_RMSK      0xffffffff
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_SHFT               0
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_IN(x)     \
	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_RMSK)
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \
	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \
	out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10

#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT        0xf

#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT        0x0

//// Register REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1 ////

#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)   (x+0x00000068)
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_PHYS(x)   (x+0x00000068)
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_RMSK      0x0000ffff
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_SHFT               0
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_IN(x)     \
	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_RMSK)
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \
	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \
	out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT        0x0

//// Register REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS ////

#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x)      (x+0x0000006c)
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_PHYS(x)      (x+0x0000006c)
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_RMSK         0xffffffff
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_SHFT                  0
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_IN(x)        \
	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_RMSK)
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_INM(x, mask) \
	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_OUT(x, val)  \
	out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), val)
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10

#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT        0xf

#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0

//// Register REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER ////

#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)   (x+0x00000070)
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_PHYS(x)   (x+0x00000070)
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RMSK      0x000003ff
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_SHFT               0
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_IN(x)     \
	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RMSK)
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \
	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \
	out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT        0x0

//// Register REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER ////

#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)  (x+0x00000074)
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_PHYS(x)  (x+0x00000074)
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_RMSK     0x00000007
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_SHFT              0
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_IN(x)    \
	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_RMSK)
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \
	out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT        0x0

//// Register REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS ////

#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000078)
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000078)
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_RMSK    0x00ffffff
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_SHFT             0
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_IN(x)   \
	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_RMSK)
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
	out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT       0x10

#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff
#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT        0x0

//// Register REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB ////

#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x)            (x+0x0000007c)
#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_PHYS(x)            (x+0x0000007c)
#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_RMSK               0xffffffff
#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_SHFT                        0
#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_IN(x)              \
	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_RMSK)
#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_INM(x, mask)       \
	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), mask) 
#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_OUT(x, val)        \
	out_dword( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), val)
#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR_BMSK          0xffffffff
#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR_SHFT                 0x0

//// Register REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB ////

#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x)            (x+0x00000080)
#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_PHYS(x)            (x+0x00000080)
#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_RMSK               0x000001ff
#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_SHFT                        0
#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_IN(x)              \
	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_RMSK)
#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_INM(x, mask)       \
	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), mask) 
#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_OUT(x, val)        \
	out_dword( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), val)
#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK   0x00000100
#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT          0x8

#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR_BMSK          0x000000ff
#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR_SHFT                 0x0

//// Register REO_R0_RXDMA2REO0_RING_MSI1_DATA ////

#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x)                (x+0x00000084)
#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_PHYS(x)                (x+0x00000084)
#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_RMSK                   0xffffffff
#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_SHFT                            0
#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_IN(x)                  \
	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_RMSK)
#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_INM(x, mask)           \
	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), mask) 
#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_OUT(x, val)            \
	out_dword( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), val)
#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_OUTM(x, mask, val)     \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_VALUE_BMSK             0xffffffff
#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_VALUE_SHFT                    0x0

//// Register REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET ////

#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x)          (x+0x00000088)
#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_PHYS(x)          (x+0x00000088)
#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_RMSK             0x0000ffff
#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_SHFT                      0
#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_IN(x)            \
	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_RMSK)
#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_INM(x, mask)     \
	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_OUT(x, val)      \
	out_dword( HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), val)
#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0

//// Register REO_R0_WBM2REO_LINK_RING_BASE_LSB ////

#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x)               (x+0x0000008c)
#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_PHYS(x)               (x+0x0000008c)
#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RMSK                  0xffffffff
#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_SHFT                           0
#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_IN(x)                 \
	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RMSK)
#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_INM(x, mask)          \
	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), mask) 
#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_OUT(x, val)           \
	out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), val)
#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_OUTM(x, mask, val)    \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT        0x0

//// Register REO_R0_WBM2REO_LINK_RING_BASE_MSB ////

#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x)               (x+0x00000090)
#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_PHYS(x)               (x+0x00000090)
#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RMSK                  0x00ffffff
#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_SHFT                           0
#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_IN(x)                 \
	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RMSK)
#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_INM(x, mask)          \
	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), mask) 
#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_OUT(x, val)           \
	out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), val)
#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_OUTM(x, mask, val)    \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_SIZE_BMSK        0x00ffff00
#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_SIZE_SHFT               0x8

#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT        0x0

//// Register REO_R0_WBM2REO_LINK_RING_ID ////

#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x)                     (x+0x00000094)
#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_PHYS(x)                     (x+0x00000094)
#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_RMSK                        0x000000ff
#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_SHFT                                 0
#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_IN(x)                       \
	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_ID_RMSK)
#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_INM(x, mask)                \
	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), mask) 
#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_OUT(x, val)                 \
	out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), val)
#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_OUTM(x, mask, val)          \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_ID_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_ENTRY_SIZE_BMSK             0x000000ff
#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_ENTRY_SIZE_SHFT                    0x0

//// Register REO_R0_WBM2REO_LINK_RING_STATUS ////

#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x)                 (x+0x00000098)
#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_PHYS(x)                 (x+0x00000098)
#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_RMSK                    0xffffffff
#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_SHFT                             0
#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_IN(x)                   \
	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_RMSK)
#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_INM(x, mask)            \
	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), mask) 
#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_OUT(x, val)             \
	out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), val)
#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_OUTM(x, mask, val)      \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK    0xffff0000
#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT          0x10

#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK    0x0000ffff
#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT           0x0

//// Register REO_R0_WBM2REO_LINK_RING_MISC ////

#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x)                   (x+0x0000009c)
#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_PHYS(x)                   (x+0x0000009c)
#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RMSK                      0x003fffff
#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SHFT                               0
#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_IN(x)                     \
	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RMSK)
#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_INM(x, mask)              \
	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), mask) 
#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_OUT(x, val)               \
	out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), val)
#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_OUTM(x, mask, val)        \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_MISC_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SPARE_CONTROL_BMSK        0x003fc000
#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SPARE_CONTROL_SHFT               0xe

#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE2_BMSK       0x00003000
#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE2_SHFT              0xc

#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE1_BMSK       0x00000f00
#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE1_SHFT              0x8

#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_IS_IDLE_BMSK         0x00000080
#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_IS_IDLE_SHFT                0x7

#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_ENABLE_BMSK          0x00000040
#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_ENABLE_SHFT                 0x6

#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK    0x00000020
#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT           0x5

#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK     0x00000010
#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT            0x4

#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_MSI_SWAP_BIT_BMSK         0x00000008
#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_MSI_SWAP_BIT_SHFT                0x3

#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SECURITY_BIT_BMSK         0x00000004
#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SECURITY_BIT_SHFT                0x2

#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK      0x00000002
#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT             0x1

#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RING_ID_DISABLE_BMSK      0x00000001
#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RING_ID_DISABLE_SHFT             0x0

//// Register REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB ////

#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x)            (x+0x000000a8)
#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_PHYS(x)            (x+0x000000a8)
#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_RMSK               0xffffffff
#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_SHFT                        0
#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_IN(x)              \
	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_RMSK)
#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_INM(x, mask)       \
	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), mask) 
#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_OUT(x, val)        \
	out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), val)
#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT        0x0

//// Register REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB ////

#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x)            (x+0x000000ac)
#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_PHYS(x)            (x+0x000000ac)
#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_RMSK               0x000000ff
#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_SHFT                        0
#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_IN(x)              \
	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_RMSK)
#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_INM(x, mask)       \
	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), mask) 
#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_OUT(x, val)        \
	out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), val)
#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT        0x0

//// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0 ////

#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000000bc)
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000000bc)
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_RMSK    0xffffffff
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_SHFT             0
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_IN(x)   \
	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_RMSK)
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \
	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \
	out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10

#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT        0xf

#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT        0x0

//// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1 ////

#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000000c0)
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000000c0)
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_RMSK    0x0000ffff
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_SHFT             0
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_IN(x)   \
	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_RMSK)
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \
	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \
	out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT        0x0

//// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS ////

#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x)    (x+0x000000c4)
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_PHYS(x)    (x+0x000000c4)
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_RMSK       0xffffffff
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_SHFT                0
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_IN(x)      \
	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_RMSK)
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_INM(x, mask) \
	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_OUT(x, val) \
	out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), val)
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10

#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT        0xf

#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0

//// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER ////

#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000000c8)
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000000c8)
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK    0x000003ff
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_SHFT             0
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x)   \
	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK)
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \
	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \
	out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT        0x0

//// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER ////

#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000000cc)
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000000cc)
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_RMSK   0x00000007
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_SHFT            0
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_IN(x)  \
	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_RMSK)
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \
	out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT        0x0

//// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS ////

#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000000d0)
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000000d0)
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_RMSK  0x00ffffff
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_SHFT           0
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_RMSK)
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
	out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT       0x10

#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff
#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT        0x0

//// Register REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB ////

#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR(x)          (x+0x000000d4)
#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_PHYS(x)          (x+0x000000d4)
#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_RMSK             0xffffffff
#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_SHFT                      0
#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_IN(x)            \
	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_RMSK)
#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_INM(x, mask)     \
	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask) 
#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_OUT(x, val)      \
	out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR(x), val)
#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR_BMSK        0xffffffff
#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR_SHFT               0x0

//// Register REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB ////

#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR(x)          (x+0x000000d8)
#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_PHYS(x)          (x+0x000000d8)
#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_RMSK             0x000001ff
#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_SHFT                      0
#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_IN(x)            \
	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_RMSK)
#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_INM(x, mask)     \
	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask) 
#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_OUT(x, val)      \
	out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR(x), val)
#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT        0x8

#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR_BMSK        0x000000ff
#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR_SHFT               0x0

//// Register REO_R0_WBM2REO_LINK_RING_MSI1_DATA ////

#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_ADDR(x)              (x+0x000000dc)
#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_PHYS(x)              (x+0x000000dc)
#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_RMSK                 0xffffffff
#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_SHFT                          0
#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_IN(x)                \
	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_RMSK)
#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_INM(x, mask)         \
	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_ADDR(x), mask) 
#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_OUT(x, val)          \
	out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_ADDR(x), val)
#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_OUTM(x, mask, val)   \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_VALUE_BMSK           0xffffffff
#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_VALUE_SHFT                  0x0

//// Register REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET ////

#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x)        (x+0x000000e0)
#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_PHYS(x)        (x+0x000000e0)
#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_RMSK           0x0000ffff
#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_SHFT                    0
#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_IN(x)          \
	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_RMSK)
#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask)   \
	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val)    \
	out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val)
#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0

//// Register REO_R0_REO_CMD_RING_BASE_LSB ////

#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x)                    (x+0x000000e4)
#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_PHYS(x)                    (x+0x000000e4)
#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RMSK                       0xffffffff
#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_SHFT                                0
#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_IN(x)                      \
	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RMSK)
#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_INM(x, mask)               \
	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_OUT(x, val)                \
	out_dword( HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), val)
#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_OUTM(x, mask, val)         \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_BASE_LSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK    0xffffffff
#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT           0x0

//// Register REO_R0_REO_CMD_RING_BASE_MSB ////

#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x)                    (x+0x000000e8)
#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_PHYS(x)                    (x+0x000000e8)
#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RMSK                       0x00ffffff
#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_SHFT                                0
#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_IN(x)                      \
	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RMSK)
#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_INM(x, mask)               \
	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_OUT(x, val)                \
	out_dword( HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), val)
#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_OUTM(x, mask, val)         \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_BASE_MSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK             0x00ffff00
#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT                    0x8

#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK    0x000000ff
#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT           0x0

//// Register REO_R0_REO_CMD_RING_ID ////

#define HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x)                          (x+0x000000ec)
#define HWIO_REO_R0_REO_CMD_RING_ID_PHYS(x)                          (x+0x000000ec)
#define HWIO_REO_R0_REO_CMD_RING_ID_RMSK                             0x000000ff
#define HWIO_REO_R0_REO_CMD_RING_ID_SHFT                                      0
#define HWIO_REO_R0_REO_CMD_RING_ID_IN(x)                            \
	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), HWIO_REO_R0_REO_CMD_RING_ID_RMSK)
#define HWIO_REO_R0_REO_CMD_RING_ID_INM(x, mask)                     \
	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), mask) 
#define HWIO_REO_R0_REO_CMD_RING_ID_OUT(x, val)                      \
	out_dword( HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), val)
#define HWIO_REO_R0_REO_CMD_RING_ID_OUTM(x, mask, val)               \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_ID_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO_CMD_RING_ID_ENTRY_SIZE_BMSK                  0x000000ff
#define HWIO_REO_R0_REO_CMD_RING_ID_ENTRY_SIZE_SHFT                         0x0

//// Register REO_R0_REO_CMD_RING_STATUS ////

#define HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x)                      (x+0x000000f0)
#define HWIO_REO_R0_REO_CMD_RING_STATUS_PHYS(x)                      (x+0x000000f0)
#define HWIO_REO_R0_REO_CMD_RING_STATUS_RMSK                         0xffffffff
#define HWIO_REO_R0_REO_CMD_RING_STATUS_SHFT                                  0
#define HWIO_REO_R0_REO_CMD_RING_STATUS_IN(x)                        \
	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), HWIO_REO_R0_REO_CMD_RING_STATUS_RMSK)
#define HWIO_REO_R0_REO_CMD_RING_STATUS_INM(x, mask)                 \
	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), mask) 
#define HWIO_REO_R0_REO_CMD_RING_STATUS_OUT(x, val)                  \
	out_dword( HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), val)
#define HWIO_REO_R0_REO_CMD_RING_STATUS_OUTM(x, mask, val)           \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_STATUS_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_AVAIL_WORDS_BMSK         0xffff0000
#define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_AVAIL_WORDS_SHFT               0x10

#define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_VALID_WORDS_BMSK         0x0000ffff
#define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_VALID_WORDS_SHFT                0x0

//// Register REO_R0_REO_CMD_RING_MISC ////

#define HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x)                        (x+0x000000f4)
#define HWIO_REO_R0_REO_CMD_RING_MISC_PHYS(x)                        (x+0x000000f4)
#define HWIO_REO_R0_REO_CMD_RING_MISC_RMSK                           0x003fffff
#define HWIO_REO_R0_REO_CMD_RING_MISC_SHFT                                    0
#define HWIO_REO_R0_REO_CMD_RING_MISC_IN(x)                          \
	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), HWIO_REO_R0_REO_CMD_RING_MISC_RMSK)
#define HWIO_REO_R0_REO_CMD_RING_MISC_INM(x, mask)                   \
	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), mask) 
#define HWIO_REO_R0_REO_CMD_RING_MISC_OUT(x, val)                    \
	out_dword( HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), val)
#define HWIO_REO_R0_REO_CMD_RING_MISC_OUTM(x, mask, val)             \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_MISC_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO_CMD_RING_MISC_SPARE_CONTROL_BMSK             0x003fc000
#define HWIO_REO_R0_REO_CMD_RING_MISC_SPARE_CONTROL_SHFT                    0xe

#define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_SM_STATE2_BMSK            0x00003000
#define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_SM_STATE2_SHFT                   0xc

#define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_SM_STATE1_BMSK            0x00000f00
#define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_SM_STATE1_SHFT                   0x8

#define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_IS_IDLE_BMSK              0x00000080
#define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_IS_IDLE_SHFT                     0x7

#define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_ENABLE_BMSK               0x00000040
#define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_ENABLE_SHFT                      0x6

#define HWIO_REO_R0_REO_CMD_RING_MISC_DATA_TLV_SWAP_BIT_BMSK         0x00000020
#define HWIO_REO_R0_REO_CMD_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                0x5

#define HWIO_REO_R0_REO_CMD_RING_MISC_HOST_FW_SWAP_BIT_BMSK          0x00000010
#define HWIO_REO_R0_REO_CMD_RING_MISC_HOST_FW_SWAP_BIT_SHFT                 0x4

#define HWIO_REO_R0_REO_CMD_RING_MISC_MSI_SWAP_BIT_BMSK              0x00000008
#define HWIO_REO_R0_REO_CMD_RING_MISC_MSI_SWAP_BIT_SHFT                     0x3

#define HWIO_REO_R0_REO_CMD_RING_MISC_SECURITY_BIT_BMSK              0x00000004
#define HWIO_REO_R0_REO_CMD_RING_MISC_SECURITY_BIT_SHFT                     0x2

#define HWIO_REO_R0_REO_CMD_RING_MISC_LOOPCNT_DISABLE_BMSK           0x00000002
#define HWIO_REO_R0_REO_CMD_RING_MISC_LOOPCNT_DISABLE_SHFT                  0x1

#define HWIO_REO_R0_REO_CMD_RING_MISC_RING_ID_DISABLE_BMSK           0x00000001
#define HWIO_REO_R0_REO_CMD_RING_MISC_RING_ID_DISABLE_SHFT                  0x0

//// Register REO_R0_REO_CMD_RING_TP_ADDR_LSB ////

#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x)                 (x+0x00000100)
#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_PHYS(x)                 (x+0x00000100)
#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_RMSK                    0xffffffff
#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_SHFT                             0
#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_IN(x)                   \
	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_RMSK)
#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_INM(x, mask)            \
	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_OUT(x, val)             \
	out_dword( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), val)
#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_OUTM(x, mask, val)      \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT        0x0

//// Register REO_R0_REO_CMD_RING_TP_ADDR_MSB ////

#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x)                 (x+0x00000104)
#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_PHYS(x)                 (x+0x00000104)
#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_RMSK                    0x000000ff
#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_SHFT                             0
#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_IN(x)                   \
	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_RMSK)
#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_INM(x, mask)            \
	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_OUT(x, val)             \
	out_dword( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), val)
#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_OUTM(x, mask, val)      \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT        0x0

//// Register REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0 ////

#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)      (x+0x00000114)
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_PHYS(x)      (x+0x00000114)
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_RMSK         0xffffffff
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_SHFT                  0
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x)        \
	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_RMSK)
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \
	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val)  \
	out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10

#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT        0xf

#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT        0x0

//// Register REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1 ////

#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)      (x+0x00000118)
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_PHYS(x)      (x+0x00000118)
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_RMSK         0x0000ffff
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_SHFT                  0
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x)        \
	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_RMSK)
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \
	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val)  \
	out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT        0x0

//// Register REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS ////

#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x)         (x+0x0000011c)
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_PHYS(x)         (x+0x0000011c)
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_RMSK            0xffffffff
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_SHFT                     0
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_IN(x)           \
	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_RMSK)
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_INM(x, mask)    \
	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_OUT(x, val)     \
	out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), val)
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10

#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT        0xf

#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0

//// Register REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER ////

#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)      (x+0x00000120)
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_PHYS(x)      (x+0x00000120)
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK         0x000003ff
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_SHFT                  0
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x)        \
	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK)
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \
	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val)  \
	out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT        0x0

//// Register REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER ////

#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)     (x+0x00000124)
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_PHYS(x)     (x+0x00000124)
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_RMSK        0x00000007
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_SHFT                 0
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x)       \
	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_RMSK)
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \
	out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK   0x00000007
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT          0x0

//// Register REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS ////

#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)    (x+0x00000128)
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_PHYS(x)    (x+0x00000128)
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_RMSK       0x00ffffff
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_SHFT                0
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_IN(x)      \
	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_RMSK)
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
	out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT       0x10

#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff
#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT        0x0

//// Register REO_R0_REO_CMD_RING_MSI1_BASE_LSB ////

#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x)               (x+0x0000012c)
#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_PHYS(x)               (x+0x0000012c)
#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_RMSK                  0xffffffff
#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_SHFT                           0
#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_IN(x)                 \
	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_RMSK)
#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_INM(x, mask)          \
	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_OUT(x, val)           \
	out_dword( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), val)
#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_OUTM(x, mask, val)    \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR_BMSK             0xffffffff
#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR_SHFT                    0x0

//// Register REO_R0_REO_CMD_RING_MSI1_BASE_MSB ////

#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x)               (x+0x00000130)
#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_PHYS(x)               (x+0x00000130)
#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_RMSK                  0x000001ff
#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_SHFT                           0
#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_IN(x)                 \
	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_RMSK)
#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_INM(x, mask)          \
	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_OUT(x, val)           \
	out_dword( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), val)
#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_OUTM(x, mask, val)    \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK      0x00000100
#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT             0x8

#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR_BMSK             0x000000ff
#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR_SHFT                    0x0

//// Register REO_R0_REO_CMD_RING_MSI1_DATA ////

#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x)                   (x+0x00000134)
#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_PHYS(x)                   (x+0x00000134)
#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_RMSK                      0xffffffff
#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_SHFT                               0
#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_IN(x)                     \
	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_RMSK)
#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_INM(x, mask)              \
	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), mask) 
#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_OUT(x, val)               \
	out_dword( HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), val)
#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_OUTM(x, mask, val)        \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_VALUE_BMSK                0xffffffff
#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_VALUE_SHFT                       0x0

//// Register REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET ////

#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x)             (x+0x00000138)
#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_PHYS(x)             (x+0x00000138)
#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_RMSK                0x0000ffff
#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_SHFT                         0
#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_IN(x)               \
	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_RMSK)
#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_INM(x, mask)        \
	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_OUT(x, val)         \
	out_dword( HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), val)
#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val)  \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0

//// Register REO_R0_SW2REO_RING_BASE_LSB ////

#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x)                     (x+0x0000013c)
#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_PHYS(x)                     (x+0x0000013c)
#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_RMSK                        0xffffffff
#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_SHFT                                 0
#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_IN(x)                       \
	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_BASE_LSB_RMSK)
#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_INM(x, mask)                \
	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), mask) 
#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_OUT(x, val)                 \
	out_dword( HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), val)
#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_OUTM(x, mask, val)          \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_BASE_LSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK     0xffffffff
#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT            0x0

//// Register REO_R0_SW2REO_RING_BASE_MSB ////

#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x)                     (x+0x00000140)
#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_PHYS(x)                     (x+0x00000140)
#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RMSK                        0x00ffffff
#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_SHFT                                 0
#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_IN(x)                       \
	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_BASE_MSB_RMSK)
#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_INM(x, mask)                \
	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), mask) 
#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_OUT(x, val)                 \
	out_dword( HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), val)
#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_OUTM(x, mask, val)          \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_BASE_MSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK              0x00ffff00
#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT                     0x8

#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK     0x000000ff
#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT            0x0

//// Register REO_R0_SW2REO_RING_ID ////

#define HWIO_REO_R0_SW2REO_RING_ID_ADDR(x)                           (x+0x00000144)
#define HWIO_REO_R0_SW2REO_RING_ID_PHYS(x)                           (x+0x00000144)
#define HWIO_REO_R0_SW2REO_RING_ID_RMSK                              0x000000ff
#define HWIO_REO_R0_SW2REO_RING_ID_SHFT                                       0
#define HWIO_REO_R0_SW2REO_RING_ID_IN(x)                             \
	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), HWIO_REO_R0_SW2REO_RING_ID_RMSK)
#define HWIO_REO_R0_SW2REO_RING_ID_INM(x, mask)                      \
	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), mask) 
#define HWIO_REO_R0_SW2REO_RING_ID_OUT(x, val)                       \
	out_dword( HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), val)
#define HWIO_REO_R0_SW2REO_RING_ID_OUTM(x, mask, val)                \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_ID_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_SW2REO_RING_ID_ENTRY_SIZE_BMSK                   0x000000ff
#define HWIO_REO_R0_SW2REO_RING_ID_ENTRY_SIZE_SHFT                          0x0

//// Register REO_R0_SW2REO_RING_STATUS ////

#define HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x)                       (x+0x00000148)
#define HWIO_REO_R0_SW2REO_RING_STATUS_PHYS(x)                       (x+0x00000148)
#define HWIO_REO_R0_SW2REO_RING_STATUS_RMSK                          0xffffffff
#define HWIO_REO_R0_SW2REO_RING_STATUS_SHFT                                   0
#define HWIO_REO_R0_SW2REO_RING_STATUS_IN(x)                         \
	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), HWIO_REO_R0_SW2REO_RING_STATUS_RMSK)
#define HWIO_REO_R0_SW2REO_RING_STATUS_INM(x, mask)                  \
	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), mask) 
#define HWIO_REO_R0_SW2REO_RING_STATUS_OUT(x, val)                   \
	out_dword( HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), val)
#define HWIO_REO_R0_SW2REO_RING_STATUS_OUTM(x, mask, val)            \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_STATUS_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_AVAIL_WORDS_BMSK          0xffff0000
#define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_AVAIL_WORDS_SHFT                0x10

#define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_VALID_WORDS_BMSK          0x0000ffff
#define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_VALID_WORDS_SHFT                 0x0

//// Register REO_R0_SW2REO_RING_MISC ////

#define HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x)                         (x+0x0000014c)
#define HWIO_REO_R0_SW2REO_RING_MISC_PHYS(x)                         (x+0x0000014c)
#define HWIO_REO_R0_SW2REO_RING_MISC_RMSK                            0x003fffff
#define HWIO_REO_R0_SW2REO_RING_MISC_SHFT                                     0
#define HWIO_REO_R0_SW2REO_RING_MISC_IN(x)                           \
	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), HWIO_REO_R0_SW2REO_RING_MISC_RMSK)
#define HWIO_REO_R0_SW2REO_RING_MISC_INM(x, mask)                    \
	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), mask) 
#define HWIO_REO_R0_SW2REO_RING_MISC_OUT(x, val)                     \
	out_dword( HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), val)
#define HWIO_REO_R0_SW2REO_RING_MISC_OUTM(x, mask, val)              \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_MISC_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_SW2REO_RING_MISC_SPARE_CONTROL_BMSK              0x003fc000
#define HWIO_REO_R0_SW2REO_RING_MISC_SPARE_CONTROL_SHFT                     0xe

#define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_SM_STATE2_BMSK             0x00003000
#define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_SM_STATE2_SHFT                    0xc

#define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_SM_STATE1_BMSK             0x00000f00
#define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_SM_STATE1_SHFT                    0x8

#define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_IS_IDLE_BMSK               0x00000080
#define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_IS_IDLE_SHFT                      0x7

#define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_ENABLE_BMSK                0x00000040
#define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_ENABLE_SHFT                       0x6

#define HWIO_REO_R0_SW2REO_RING_MISC_DATA_TLV_SWAP_BIT_BMSK          0x00000020
#define HWIO_REO_R0_SW2REO_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                 0x5

#define HWIO_REO_R0_SW2REO_RING_MISC_HOST_FW_SWAP_BIT_BMSK           0x00000010
#define HWIO_REO_R0_SW2REO_RING_MISC_HOST_FW_SWAP_BIT_SHFT                  0x4

#define HWIO_REO_R0_SW2REO_RING_MISC_MSI_SWAP_BIT_BMSK               0x00000008
#define HWIO_REO_R0_SW2REO_RING_MISC_MSI_SWAP_BIT_SHFT                      0x3

#define HWIO_REO_R0_SW2REO_RING_MISC_SECURITY_BIT_BMSK               0x00000004
#define HWIO_REO_R0_SW2REO_RING_MISC_SECURITY_BIT_SHFT                      0x2

#define HWIO_REO_R0_SW2REO_RING_MISC_LOOPCNT_DISABLE_BMSK            0x00000002
#define HWIO_REO_R0_SW2REO_RING_MISC_LOOPCNT_DISABLE_SHFT                   0x1

#define HWIO_REO_R0_SW2REO_RING_MISC_RING_ID_DISABLE_BMSK            0x00000001
#define HWIO_REO_R0_SW2REO_RING_MISC_RING_ID_DISABLE_SHFT                   0x0

//// Register REO_R0_SW2REO_RING_TP_ADDR_LSB ////

#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x)                  (x+0x00000158)
#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_PHYS(x)                  (x+0x00000158)
#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_RMSK                     0xffffffff
#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_SHFT                              0
#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_IN(x)                    \
	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_RMSK)
#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_INM(x, mask)             \
	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), mask) 
#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_OUT(x, val)              \
	out_dword( HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), val)
#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_OUTM(x, mask, val)       \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT        0x0

//// Register REO_R0_SW2REO_RING_TP_ADDR_MSB ////

#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x)                  (x+0x0000015c)
#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_PHYS(x)                  (x+0x0000015c)
#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_RMSK                     0x000000ff
#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_SHFT                              0
#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_IN(x)                    \
	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_RMSK)
#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_INM(x, mask)             \
	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), mask) 
#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_OUT(x, val)              \
	out_dword( HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), val)
#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_OUTM(x, mask, val)       \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT        0x0

//// Register REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0 ////

#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)       (x+0x0000016c)
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_PHYS(x)       (x+0x0000016c)
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_RMSK          0xffffffff
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_SHFT                   0
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_IN(x)         \
	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_RMSK)
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask)  \
	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val)   \
	out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10

#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT        0xf

#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT        0x0

//// Register REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1 ////

#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)       (x+0x00000170)
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_PHYS(x)       (x+0x00000170)
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_RMSK          0x0000ffff
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_SHFT                   0
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_IN(x)         \
	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_RMSK)
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask)  \
	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val)   \
	out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT        0x0

//// Register REO_R0_SW2REO_RING_CONSUMER_INT_STATUS ////

#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x)          (x+0x00000174)
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_PHYS(x)          (x+0x00000174)
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_RMSK             0xffffffff
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_SHFT                      0
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_IN(x)            \
	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_RMSK)
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_INM(x, mask)     \
	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_OUT(x, val)      \
	out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), val)
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10

#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT        0xf

#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0

//// Register REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER ////

#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)       (x+0x00000178)
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_PHYS(x)       (x+0x00000178)
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RMSK          0x000003ff
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_SHFT                   0
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_IN(x)         \
	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RMSK)
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask)  \
	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val)   \
	out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT        0x0

//// Register REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER ////

#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)      (x+0x0000017c)
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_PHYS(x)      (x+0x0000017c)
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_RMSK         0x00000007
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_SHFT                  0
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_IN(x)        \
	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_RMSK)
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val)  \
	out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK    0x00000007
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT           0x0

//// Register REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS ////

#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)     (x+0x00000180)
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_PHYS(x)     (x+0x00000180)
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_RMSK        0x00ffffff
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_SHFT                 0
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_IN(x)       \
	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_RMSK)
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
	out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT       0x10

#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff
#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT        0x0

//// Register REO_R0_SW2REO_RING_MSI1_BASE_LSB ////

#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x)                (x+0x00000184)
#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_PHYS(x)                (x+0x00000184)
#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_RMSK                   0xffffffff
#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_SHFT                            0
#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_IN(x)                  \
	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_RMSK)
#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_INM(x, mask)           \
	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), mask) 
#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_OUT(x, val)            \
	out_dword( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), val)
#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_OUTM(x, mask, val)     \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR_BMSK              0xffffffff
#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR_SHFT                     0x0

//// Register REO_R0_SW2REO_RING_MSI1_BASE_MSB ////

#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x)                (x+0x00000188)
#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_PHYS(x)                (x+0x00000188)
#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_RMSK                   0x000001ff
#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_SHFT                            0
#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_IN(x)                  \
	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_RMSK)
#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_INM(x, mask)           \
	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), mask) 
#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_OUT(x, val)            \
	out_dword( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), val)
#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_OUTM(x, mask, val)     \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK       0x00000100
#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT              0x8

#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR_BMSK              0x000000ff
#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR_SHFT                     0x0

//// Register REO_R0_SW2REO_RING_MSI1_DATA ////

#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x)                    (x+0x0000018c)
#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_PHYS(x)                    (x+0x0000018c)
#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_RMSK                       0xffffffff
#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_SHFT                                0
#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_IN(x)                      \
	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_SW2REO_RING_MSI1_DATA_RMSK)
#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_INM(x, mask)               \
	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), mask) 
#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_OUT(x, val)                \
	out_dword( HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), val)
#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_OUTM(x, mask, val)         \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_MSI1_DATA_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_VALUE_BMSK                 0xffffffff
#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_VALUE_SHFT                        0x0

//// Register REO_R0_SW2REO_RING_HP_TP_SW_OFFSET ////

#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x)              (x+0x00000190)
#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_PHYS(x)              (x+0x00000190)
#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_RMSK                 0x0000ffff
#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_SHFT                          0
#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_IN(x)                \
	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_RMSK)
#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_INM(x, mask)         \
	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_OUT(x, val)          \
	out_dword( HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), val)
#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val)   \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0

//// Register REO_R0_SW2REO1_RING_BASE_LSB ////

#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(x)                    (x+0x00000194)
#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_PHYS(x)                    (x+0x00000194)
#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_RMSK                       0xffffffff
#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_SHFT                                0
#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_IN(x)                      \
	in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_SW2REO1_RING_BASE_LSB_RMSK)
#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_INM(x, mask)               \
	in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(x), mask) 
#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_OUT(x, val)                \
	out_dword( HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(x), val)
#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_OUTM(x, mask, val)         \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_BASE_LSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK    0xffffffff
#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT           0x0

//// Register REO_R0_SW2REO1_RING_BASE_MSB ////

#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ADDR(x)                    (x+0x00000198)
#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_PHYS(x)                    (x+0x00000198)
#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RMSK                       0x00ffffff
#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_SHFT                                0
#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_IN(x)                      \
	in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RMSK)
#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_INM(x, mask)               \
	in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ADDR(x), mask) 
#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_OUT(x, val)                \
	out_dword( HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ADDR(x), val)
#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_OUTM(x, mask, val)         \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_BASE_MSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RING_SIZE_BMSK             0x00ffff00
#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RING_SIZE_SHFT                    0x8

#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK    0x000000ff
#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT           0x0

//// Register REO_R0_SW2REO1_RING_ID ////

#define HWIO_REO_R0_SW2REO1_RING_ID_ADDR(x)                          (x+0x0000019c)
#define HWIO_REO_R0_SW2REO1_RING_ID_PHYS(x)                          (x+0x0000019c)
#define HWIO_REO_R0_SW2REO1_RING_ID_RMSK                             0x000000ff
#define HWIO_REO_R0_SW2REO1_RING_ID_SHFT                                      0
#define HWIO_REO_R0_SW2REO1_RING_ID_IN(x)                            \
	in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_ID_ADDR(x), HWIO_REO_R0_SW2REO1_RING_ID_RMSK)
#define HWIO_REO_R0_SW2REO1_RING_ID_INM(x, mask)                     \
	in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_ID_ADDR(x), mask) 
#define HWIO_REO_R0_SW2REO1_RING_ID_OUT(x, val)                      \
	out_dword( HWIO_REO_R0_SW2REO1_RING_ID_ADDR(x), val)
#define HWIO_REO_R0_SW2REO1_RING_ID_OUTM(x, mask, val)               \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_ID_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_SW2REO1_RING_ID_ENTRY_SIZE_BMSK                  0x000000ff
#define HWIO_REO_R0_SW2REO1_RING_ID_ENTRY_SIZE_SHFT                         0x0

//// Register REO_R0_SW2REO1_RING_STATUS ////

#define HWIO_REO_R0_SW2REO1_RING_STATUS_ADDR(x)                      (x+0x000001a0)
#define HWIO_REO_R0_SW2REO1_RING_STATUS_PHYS(x)                      (x+0x000001a0)
#define HWIO_REO_R0_SW2REO1_RING_STATUS_RMSK                         0xffffffff
#define HWIO_REO_R0_SW2REO1_RING_STATUS_SHFT                                  0
#define HWIO_REO_R0_SW2REO1_RING_STATUS_IN(x)                        \
	in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_STATUS_ADDR(x), HWIO_REO_R0_SW2REO1_RING_STATUS_RMSK)
#define HWIO_REO_R0_SW2REO1_RING_STATUS_INM(x, mask)                 \
	in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_STATUS_ADDR(x), mask) 
#define HWIO_REO_R0_SW2REO1_RING_STATUS_OUT(x, val)                  \
	out_dword( HWIO_REO_R0_SW2REO1_RING_STATUS_ADDR(x), val)
#define HWIO_REO_R0_SW2REO1_RING_STATUS_OUTM(x, mask, val)           \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_STATUS_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_SW2REO1_RING_STATUS_NUM_AVAIL_WORDS_BMSK         0xffff0000
#define HWIO_REO_R0_SW2REO1_RING_STATUS_NUM_AVAIL_WORDS_SHFT               0x10

#define HWIO_REO_R0_SW2REO1_RING_STATUS_NUM_VALID_WORDS_BMSK         0x0000ffff
#define HWIO_REO_R0_SW2REO1_RING_STATUS_NUM_VALID_WORDS_SHFT                0x0

//// Register REO_R0_SW2REO1_RING_MISC ////

#define HWIO_REO_R0_SW2REO1_RING_MISC_ADDR(x)                        (x+0x000001a4)
#define HWIO_REO_R0_SW2REO1_RING_MISC_PHYS(x)                        (x+0x000001a4)
#define HWIO_REO_R0_SW2REO1_RING_MISC_RMSK                           0x003fffff
#define HWIO_REO_R0_SW2REO1_RING_MISC_SHFT                                    0
#define HWIO_REO_R0_SW2REO1_RING_MISC_IN(x)                          \
	in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MISC_ADDR(x), HWIO_REO_R0_SW2REO1_RING_MISC_RMSK)
#define HWIO_REO_R0_SW2REO1_RING_MISC_INM(x, mask)                   \
	in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MISC_ADDR(x), mask) 
#define HWIO_REO_R0_SW2REO1_RING_MISC_OUT(x, val)                    \
	out_dword( HWIO_REO_R0_SW2REO1_RING_MISC_ADDR(x), val)
#define HWIO_REO_R0_SW2REO1_RING_MISC_OUTM(x, mask, val)             \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_MISC_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_SW2REO1_RING_MISC_SPARE_CONTROL_BMSK             0x003fc000
#define HWIO_REO_R0_SW2REO1_RING_MISC_SPARE_CONTROL_SHFT                    0xe

#define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_SM_STATE2_BMSK            0x00003000
#define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_SM_STATE2_SHFT                   0xc

#define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_SM_STATE1_BMSK            0x00000f00
#define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_SM_STATE1_SHFT                   0x8

#define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_IS_IDLE_BMSK              0x00000080
#define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_IS_IDLE_SHFT                     0x7

#define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_ENABLE_BMSK               0x00000040
#define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_ENABLE_SHFT                      0x6

#define HWIO_REO_R0_SW2REO1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK         0x00000020
#define HWIO_REO_R0_SW2REO1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                0x5

#define HWIO_REO_R0_SW2REO1_RING_MISC_HOST_FW_SWAP_BIT_BMSK          0x00000010
#define HWIO_REO_R0_SW2REO1_RING_MISC_HOST_FW_SWAP_BIT_SHFT                 0x4

#define HWIO_REO_R0_SW2REO1_RING_MISC_MSI_SWAP_BIT_BMSK              0x00000008
#define HWIO_REO_R0_SW2REO1_RING_MISC_MSI_SWAP_BIT_SHFT                     0x3

#define HWIO_REO_R0_SW2REO1_RING_MISC_SECURITY_BIT_BMSK              0x00000004
#define HWIO_REO_R0_SW2REO1_RING_MISC_SECURITY_BIT_SHFT                     0x2

#define HWIO_REO_R0_SW2REO1_RING_MISC_LOOPCNT_DISABLE_BMSK           0x00000002
#define HWIO_REO_R0_SW2REO1_RING_MISC_LOOPCNT_DISABLE_SHFT                  0x1

#define HWIO_REO_R0_SW2REO1_RING_MISC_RING_ID_DISABLE_BMSK           0x00000001
#define HWIO_REO_R0_SW2REO1_RING_MISC_RING_ID_DISABLE_SHFT                  0x0

//// Register REO_R0_SW2REO1_RING_TP_ADDR_LSB ////

#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ADDR(x)                 (x+0x000001b0)
#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_PHYS(x)                 (x+0x000001b0)
#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_RMSK                    0xffffffff
#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_SHFT                             0
#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_IN(x)                   \
	in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_RMSK)
#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_INM(x, mask)            \
	in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ADDR(x), mask) 
#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_OUT(x, val)             \
	out_dword( HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ADDR(x), val)
#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_OUTM(x, mask, val)      \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT        0x0

//// Register REO_R0_SW2REO1_RING_TP_ADDR_MSB ////

#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ADDR(x)                 (x+0x000001b4)
#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_PHYS(x)                 (x+0x000001b4)
#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_RMSK                    0x000000ff
#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_SHFT                             0
#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_IN(x)                   \
	in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_RMSK)
#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_INM(x, mask)            \
	in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ADDR(x), mask) 
#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_OUT(x, val)             \
	out_dword( HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ADDR(x), val)
#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_OUTM(x, mask, val)      \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT        0x0

//// Register REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0 ////

#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)      (x+0x000001c4)
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x)      (x+0x000001c4)
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_RMSK         0xffffffff
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_SHFT                  0
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_IN(x)        \
	in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_RMSK)
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \
	in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val)  \
	out_dword( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10

#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT        0xf

#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT        0x0

//// Register REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1 ////

#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)      (x+0x000001c8)
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x)      (x+0x000001c8)
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_RMSK         0x0000ffff
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_SHFT                  0
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_IN(x)        \
	in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_RMSK)
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \
	in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val)  \
	out_dword( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT        0x0

//// Register REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS ////

#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x)         (x+0x000001cc)
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_PHYS(x)         (x+0x000001cc)
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_RMSK            0xffffffff
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_SHFT                     0
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_IN(x)           \
	in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_RMSK)
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_INM(x, mask)    \
	in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_OUT(x, val)     \
	out_dword( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), val)
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10

#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT        0xf

#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0

//// Register REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER ////

#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)      (x+0x000001d0)
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x)      (x+0x000001d0)
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_RMSK         0x000003ff
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_SHFT                  0
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_IN(x)        \
	in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_RMSK)
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \
	in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val)  \
	out_dword( HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT        0x0

//// Register REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER ////

#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)     (x+0x000001d4)
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x)     (x+0x000001d4)
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_RMSK        0x00000007
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_SHFT                 0
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_IN(x)       \
	in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_RMSK)
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
	in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \
	out_dword( HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK   0x00000007
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT          0x0

//// Register REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS ////

#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)    (x+0x000001d8)
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x)    (x+0x000001d8)
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_RMSK       0x00ffffff
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_SHFT                0
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_IN(x)      \
	in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_RMSK)
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
	in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
	out_dword( HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT       0x10

#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff
#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT        0x0

//// Register REO_R0_SW2REO1_RING_MSI1_BASE_LSB ////

#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR(x)               (x+0x000001dc)
#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_PHYS(x)               (x+0x000001dc)
#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_RMSK                  0xffffffff
#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_SHFT                           0
#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_IN(x)                 \
	in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_RMSK)
#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_INM(x, mask)          \
	in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR(x), mask) 
#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_OUT(x, val)           \
	out_dword( HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR(x), val)
#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_OUTM(x, mask, val)    \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR_BMSK             0xffffffff
#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR_SHFT                    0x0

//// Register REO_R0_SW2REO1_RING_MSI1_BASE_MSB ////

#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR(x)               (x+0x000001e0)
#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_PHYS(x)               (x+0x000001e0)
#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_RMSK                  0x000001ff
#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_SHFT                           0
#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_IN(x)                 \
	in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_RMSK)
#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_INM(x, mask)          \
	in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR(x), mask) 
#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_OUT(x, val)           \
	out_dword( HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR(x), val)
#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_OUTM(x, mask, val)    \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK      0x00000100
#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT             0x8

#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR_BMSK             0x000000ff
#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR_SHFT                    0x0

//// Register REO_R0_SW2REO1_RING_MSI1_DATA ////

#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ADDR(x)                   (x+0x000001e4)
#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_PHYS(x)                   (x+0x000001e4)
#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_RMSK                      0xffffffff
#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_SHFT                               0
#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_IN(x)                     \
	in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_RMSK)
#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_INM(x, mask)              \
	in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ADDR(x), mask) 
#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_OUT(x, val)               \
	out_dword( HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ADDR(x), val)
#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_OUTM(x, mask, val)        \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_VALUE_BMSK                0xffffffff
#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_VALUE_SHFT                       0x0

//// Register REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET ////

#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x)             (x+0x000001e8)
#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_PHYS(x)             (x+0x000001e8)
#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_RMSK                0x0000ffff
#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_SHFT                         0
#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_IN(x)               \
	in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_RMSK)
#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_INM(x, mask)        \
	in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_OUT(x, val)         \
	out_dword( HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), val)
#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val)  \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0

//// Register REO_R0_REO2SW1_RING_BASE_LSB ////

#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x)                    (x+0x000001ec)
#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_PHYS(x)                    (x+0x000001ec)
#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RMSK                       0xffffffff
#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_SHFT                                0
#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_IN(x)                      \
	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RMSK)
#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_INM(x, mask)               \
	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_OUT(x, val)                \
	out_dword( HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), val)
#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_OUTM(x, mask, val)         \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_BASE_LSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK    0xffffffff
#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT           0x0

//// Register REO_R0_REO2SW1_RING_BASE_MSB ////

#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x)                    (x+0x000001f0)
#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_PHYS(x)                    (x+0x000001f0)
#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RMSK                       0x0fffffff
#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_SHFT                                0
#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_IN(x)                      \
	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RMSK)
#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_INM(x, mask)               \
	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_OUT(x, val)                \
	out_dword( HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), val)
#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_OUTM(x, mask, val)         \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_BASE_MSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK             0x0fffff00
#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT                    0x8

#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK    0x000000ff
#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT           0x0

//// Register REO_R0_REO2SW1_RING_ID ////

#define HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x)                          (x+0x000001f4)
#define HWIO_REO_R0_REO2SW1_RING_ID_PHYS(x)                          (x+0x000001f4)
#define HWIO_REO_R0_REO2SW1_RING_ID_RMSK                             0x0000ffff
#define HWIO_REO_R0_REO2SW1_RING_ID_SHFT                                      0
#define HWIO_REO_R0_REO2SW1_RING_ID_IN(x)                            \
	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW1_RING_ID_RMSK)
#define HWIO_REO_R0_REO2SW1_RING_ID_INM(x, mask)                     \
	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW1_RING_ID_OUT(x, val)                      \
	out_dword( HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), val)
#define HWIO_REO_R0_REO2SW1_RING_ID_OUTM(x, mask, val)               \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_ID_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW1_RING_ID_RING_ID_BMSK                     0x0000ff00
#define HWIO_REO_R0_REO2SW1_RING_ID_RING_ID_SHFT                            0x8

#define HWIO_REO_R0_REO2SW1_RING_ID_ENTRY_SIZE_BMSK                  0x000000ff
#define HWIO_REO_R0_REO2SW1_RING_ID_ENTRY_SIZE_SHFT                         0x0

//// Register REO_R0_REO2SW1_RING_STATUS ////

#define HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x)                      (x+0x000001f8)
#define HWIO_REO_R0_REO2SW1_RING_STATUS_PHYS(x)                      (x+0x000001f8)
#define HWIO_REO_R0_REO2SW1_RING_STATUS_RMSK                         0xffffffff
#define HWIO_REO_R0_REO2SW1_RING_STATUS_SHFT                                  0
#define HWIO_REO_R0_REO2SW1_RING_STATUS_IN(x)                        \
	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW1_RING_STATUS_RMSK)
#define HWIO_REO_R0_REO2SW1_RING_STATUS_INM(x, mask)                 \
	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW1_RING_STATUS_OUT(x, val)                  \
	out_dword( HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), val)
#define HWIO_REO_R0_REO2SW1_RING_STATUS_OUTM(x, mask, val)           \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_STATUS_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_AVAIL_WORDS_BMSK         0xffff0000
#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_AVAIL_WORDS_SHFT               0x10

#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_VALID_WORDS_BMSK         0x0000ffff
#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_VALID_WORDS_SHFT                0x0

//// Register REO_R0_REO2SW1_RING_MISC ////

#define HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x)                        (x+0x000001fc)
#define HWIO_REO_R0_REO2SW1_RING_MISC_PHYS(x)                        (x+0x000001fc)
#define HWIO_REO_R0_REO2SW1_RING_MISC_RMSK                           0x03ffffff
#define HWIO_REO_R0_REO2SW1_RING_MISC_SHFT                                    0
#define HWIO_REO_R0_REO2SW1_RING_MISC_IN(x)                          \
	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW1_RING_MISC_RMSK)
#define HWIO_REO_R0_REO2SW1_RING_MISC_INM(x, mask)                   \
	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW1_RING_MISC_OUT(x, val)                    \
	out_dword( HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), val)
#define HWIO_REO_R0_REO2SW1_RING_MISC_OUTM(x, mask, val)             \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_MISC_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW1_RING_MISC_LOOP_CNT_BMSK                  0x03c00000
#define HWIO_REO_R0_REO2SW1_RING_MISC_LOOP_CNT_SHFT                        0x16

#define HWIO_REO_R0_REO2SW1_RING_MISC_SPARE_CONTROL_BMSK             0x003fc000
#define HWIO_REO_R0_REO2SW1_RING_MISC_SPARE_CONTROL_SHFT                    0xe

#define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_SM_STATE2_BMSK            0x00003000
#define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_SM_STATE2_SHFT                   0xc

#define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_SM_STATE1_BMSK            0x00000f00
#define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_SM_STATE1_SHFT                   0x8

#define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_IS_IDLE_BMSK              0x00000080
#define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_IS_IDLE_SHFT                     0x7

#define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_ENABLE_BMSK               0x00000040
#define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_ENABLE_SHFT                      0x6

#define HWIO_REO_R0_REO2SW1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK         0x00000020
#define HWIO_REO_R0_REO2SW1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                0x5

#define HWIO_REO_R0_REO2SW1_RING_MISC_HOST_FW_SWAP_BIT_BMSK          0x00000010
#define HWIO_REO_R0_REO2SW1_RING_MISC_HOST_FW_SWAP_BIT_SHFT                 0x4

#define HWIO_REO_R0_REO2SW1_RING_MISC_MSI_SWAP_BIT_BMSK              0x00000008
#define HWIO_REO_R0_REO2SW1_RING_MISC_MSI_SWAP_BIT_SHFT                     0x3

#define HWIO_REO_R0_REO2SW1_RING_MISC_SECURITY_BIT_BMSK              0x00000004
#define HWIO_REO_R0_REO2SW1_RING_MISC_SECURITY_BIT_SHFT                     0x2

#define HWIO_REO_R0_REO2SW1_RING_MISC_LOOPCNT_DISABLE_BMSK           0x00000002
#define HWIO_REO_R0_REO2SW1_RING_MISC_LOOPCNT_DISABLE_SHFT                  0x1

#define HWIO_REO_R0_REO2SW1_RING_MISC_RING_ID_DISABLE_BMSK           0x00000001
#define HWIO_REO_R0_REO2SW1_RING_MISC_RING_ID_DISABLE_SHFT                  0x0

//// Register REO_R0_REO2SW1_RING_HP_ADDR_LSB ////

#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x)                 (x+0x00000200)
#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_PHYS(x)                 (x+0x00000200)
#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_RMSK                    0xffffffff
#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_SHFT                             0
#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_IN(x)                   \
	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_RMSK)
#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_INM(x, mask)            \
	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_OUT(x, val)             \
	out_dword( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), val)
#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_OUTM(x, mask, val)      \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT        0x0

//// Register REO_R0_REO2SW1_RING_HP_ADDR_MSB ////

#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x)                 (x+0x00000204)
#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_PHYS(x)                 (x+0x00000204)
#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_RMSK                    0x000000ff
#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_SHFT                             0
#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_IN(x)                   \
	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_RMSK)
#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_INM(x, mask)            \
	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_OUT(x, val)             \
	out_dword( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), val)
#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_OUTM(x, mask, val)      \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT        0x0

//// Register REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP ////

#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x)          (x+0x00000210)
#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_PHYS(x)          (x+0x00000210)
#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_RMSK             0xffffffff
#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_SHFT                      0
#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_IN(x)            \
	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_RMSK)
#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INM(x, mask)     \
	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_OUT(x, val)      \
	out_dword( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), val)
#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10

#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT        0xf

#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT        0x0

//// Register REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS ////

#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x)         (x+0x00000214)
#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_PHYS(x)         (x+0x00000214)
#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_RMSK            0xffffffff
#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_SHFT                     0
#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_IN(x)           \
	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_RMSK)
#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_INM(x, mask)    \
	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_OUT(x, val)     \
	out_dword( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), val)
#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10

#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT        0xf

#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0

//// Register REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER ////

#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x)       (x+0x00000218)
#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_PHYS(x)       (x+0x00000218)
#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RMSK          0x000003ff
#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_SHFT                   0
#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_IN(x)         \
	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RMSK)
#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_INM(x, mask)  \
	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_OUT(x, val)   \
	out_dword( HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff
#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT        0x0

//// Register REO_R0_REO2SW1_RING_MSI1_BASE_LSB ////

#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x)               (x+0x00000234)
#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_PHYS(x)               (x+0x00000234)
#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_RMSK                  0xffffffff
#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_SHFT                           0
#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_IN(x)                 \
	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_RMSK)
#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_INM(x, mask)          \
	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_OUT(x, val)           \
	out_dword( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), val)
#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_OUTM(x, mask, val)    \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR_BMSK             0xffffffff
#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR_SHFT                    0x0

//// Register REO_R0_REO2SW1_RING_MSI1_BASE_MSB ////

#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x)               (x+0x00000238)
#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_PHYS(x)               (x+0x00000238)
#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_RMSK                  0x000001ff
#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_SHFT                           0
#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_IN(x)                 \
	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_RMSK)
#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_INM(x, mask)          \
	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_OUT(x, val)           \
	out_dword( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), val)
#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_OUTM(x, mask, val)    \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK      0x00000100
#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT             0x8

#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR_BMSK             0x000000ff
#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR_SHFT                    0x0

//// Register REO_R0_REO2SW1_RING_MSI1_DATA ////

#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x)                   (x+0x0000023c)
#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_PHYS(x)                   (x+0x0000023c)
#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_RMSK                      0xffffffff
#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_SHFT                               0
#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_IN(x)                     \
	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_RMSK)
#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_INM(x, mask)              \
	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_OUT(x, val)               \
	out_dword( HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), val)
#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_OUTM(x, mask, val)        \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_VALUE_BMSK                0xffffffff
#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_VALUE_SHFT                       0x0

//// Register REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET ////

#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x)             (x+0x00000240)
#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_PHYS(x)             (x+0x00000240)
#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_RMSK                0x0000ffff
#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_SHFT                         0
#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_IN(x)               \
	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_RMSK)
#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_INM(x, mask)        \
	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_OUT(x, val)         \
	out_dword( HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), val)
#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val)  \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0

//// Register REO_R0_REO2SW2_RING_BASE_LSB ////

#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x)                    (x+0x00000244)
#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_PHYS(x)                    (x+0x00000244)
#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RMSK                       0xffffffff
#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_SHFT                                0
#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_IN(x)                      \
	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RMSK)
#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_INM(x, mask)               \
	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_OUT(x, val)                \
	out_dword( HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), val)
#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_OUTM(x, mask, val)         \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_BASE_LSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK    0xffffffff
#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT           0x0

//// Register REO_R0_REO2SW2_RING_BASE_MSB ////

#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x)                    (x+0x00000248)
#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_PHYS(x)                    (x+0x00000248)
#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RMSK                       0x0fffffff
#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_SHFT                                0
#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_IN(x)                      \
	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RMSK)
#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_INM(x, mask)               \
	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_OUT(x, val)                \
	out_dword( HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), val)
#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_OUTM(x, mask, val)         \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_BASE_MSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_SIZE_BMSK             0x0fffff00
#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_SIZE_SHFT                    0x8

#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK    0x000000ff
#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT           0x0

//// Register REO_R0_REO2SW2_RING_ID ////

#define HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x)                          (x+0x0000024c)
#define HWIO_REO_R0_REO2SW2_RING_ID_PHYS(x)                          (x+0x0000024c)
#define HWIO_REO_R0_REO2SW2_RING_ID_RMSK                             0x0000ffff
#define HWIO_REO_R0_REO2SW2_RING_ID_SHFT                                      0
#define HWIO_REO_R0_REO2SW2_RING_ID_IN(x)                            \
	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW2_RING_ID_RMSK)
#define HWIO_REO_R0_REO2SW2_RING_ID_INM(x, mask)                     \
	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW2_RING_ID_OUT(x, val)                      \
	out_dword( HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), val)
#define HWIO_REO_R0_REO2SW2_RING_ID_OUTM(x, mask, val)               \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_ID_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW2_RING_ID_RING_ID_BMSK                     0x0000ff00
#define HWIO_REO_R0_REO2SW2_RING_ID_RING_ID_SHFT                            0x8

#define HWIO_REO_R0_REO2SW2_RING_ID_ENTRY_SIZE_BMSK                  0x000000ff
#define HWIO_REO_R0_REO2SW2_RING_ID_ENTRY_SIZE_SHFT                         0x0

//// Register REO_R0_REO2SW2_RING_STATUS ////

#define HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x)                      (x+0x00000250)
#define HWIO_REO_R0_REO2SW2_RING_STATUS_PHYS(x)                      (x+0x00000250)
#define HWIO_REO_R0_REO2SW2_RING_STATUS_RMSK                         0xffffffff
#define HWIO_REO_R0_REO2SW2_RING_STATUS_SHFT                                  0
#define HWIO_REO_R0_REO2SW2_RING_STATUS_IN(x)                        \
	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW2_RING_STATUS_RMSK)
#define HWIO_REO_R0_REO2SW2_RING_STATUS_INM(x, mask)                 \
	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW2_RING_STATUS_OUT(x, val)                  \
	out_dword( HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), val)
#define HWIO_REO_R0_REO2SW2_RING_STATUS_OUTM(x, mask, val)           \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_STATUS_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_AVAIL_WORDS_BMSK         0xffff0000
#define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_AVAIL_WORDS_SHFT               0x10

#define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_VALID_WORDS_BMSK         0x0000ffff
#define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_VALID_WORDS_SHFT                0x0

//// Register REO_R0_REO2SW2_RING_MISC ////

#define HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x)                        (x+0x00000254)
#define HWIO_REO_R0_REO2SW2_RING_MISC_PHYS(x)                        (x+0x00000254)
#define HWIO_REO_R0_REO2SW2_RING_MISC_RMSK                           0x03ffffff
#define HWIO_REO_R0_REO2SW2_RING_MISC_SHFT                                    0
#define HWIO_REO_R0_REO2SW2_RING_MISC_IN(x)                          \
	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW2_RING_MISC_RMSK)
#define HWIO_REO_R0_REO2SW2_RING_MISC_INM(x, mask)                   \
	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW2_RING_MISC_OUT(x, val)                    \
	out_dword( HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), val)
#define HWIO_REO_R0_REO2SW2_RING_MISC_OUTM(x, mask, val)             \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_MISC_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW2_RING_MISC_LOOP_CNT_BMSK                  0x03c00000
#define HWIO_REO_R0_REO2SW2_RING_MISC_LOOP_CNT_SHFT                        0x16

#define HWIO_REO_R0_REO2SW2_RING_MISC_SPARE_CONTROL_BMSK             0x003fc000
#define HWIO_REO_R0_REO2SW2_RING_MISC_SPARE_CONTROL_SHFT                    0xe

#define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_SM_STATE2_BMSK            0x00003000
#define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_SM_STATE2_SHFT                   0xc

#define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_SM_STATE1_BMSK            0x00000f00
#define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_SM_STATE1_SHFT                   0x8

#define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_IS_IDLE_BMSK              0x00000080
#define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_IS_IDLE_SHFT                     0x7

#define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_ENABLE_BMSK               0x00000040
#define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_ENABLE_SHFT                      0x6

#define HWIO_REO_R0_REO2SW2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK         0x00000020
#define HWIO_REO_R0_REO2SW2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                0x5

#define HWIO_REO_R0_REO2SW2_RING_MISC_HOST_FW_SWAP_BIT_BMSK          0x00000010
#define HWIO_REO_R0_REO2SW2_RING_MISC_HOST_FW_SWAP_BIT_SHFT                 0x4

#define HWIO_REO_R0_REO2SW2_RING_MISC_MSI_SWAP_BIT_BMSK              0x00000008
#define HWIO_REO_R0_REO2SW2_RING_MISC_MSI_SWAP_BIT_SHFT                     0x3

#define HWIO_REO_R0_REO2SW2_RING_MISC_SECURITY_BIT_BMSK              0x00000004
#define HWIO_REO_R0_REO2SW2_RING_MISC_SECURITY_BIT_SHFT                     0x2

#define HWIO_REO_R0_REO2SW2_RING_MISC_LOOPCNT_DISABLE_BMSK           0x00000002
#define HWIO_REO_R0_REO2SW2_RING_MISC_LOOPCNT_DISABLE_SHFT                  0x1

#define HWIO_REO_R0_REO2SW2_RING_MISC_RING_ID_DISABLE_BMSK           0x00000001
#define HWIO_REO_R0_REO2SW2_RING_MISC_RING_ID_DISABLE_SHFT                  0x0

//// Register REO_R0_REO2SW2_RING_HP_ADDR_LSB ////

#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x)                 (x+0x00000258)
#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_PHYS(x)                 (x+0x00000258)
#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_RMSK                    0xffffffff
#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_SHFT                             0
#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_IN(x)                   \
	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_RMSK)
#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_INM(x, mask)            \
	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_OUT(x, val)             \
	out_dword( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), val)
#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_OUTM(x, mask, val)      \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT        0x0

//// Register REO_R0_REO2SW2_RING_HP_ADDR_MSB ////

#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x)                 (x+0x0000025c)
#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_PHYS(x)                 (x+0x0000025c)
#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_RMSK                    0x000000ff
#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_SHFT                             0
#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_IN(x)                   \
	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_RMSK)
#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_INM(x, mask)            \
	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_OUT(x, val)             \
	out_dword( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), val)
#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_OUTM(x, mask, val)      \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT        0x0

//// Register REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP ////

#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x)          (x+0x00000268)
#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_PHYS(x)          (x+0x00000268)
#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_RMSK             0xffffffff
#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_SHFT                      0
#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_IN(x)            \
	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_RMSK)
#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_INM(x, mask)     \
	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_OUT(x, val)      \
	out_dword( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), val)
#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10

#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT        0xf

#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT        0x0

//// Register REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS ////

#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x)         (x+0x0000026c)
#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_PHYS(x)         (x+0x0000026c)
#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_RMSK            0xffffffff
#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_SHFT                     0
#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_IN(x)           \
	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_RMSK)
#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_INM(x, mask)    \
	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_OUT(x, val)     \
	out_dword( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), val)
#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10

#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT        0xf

#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0

//// Register REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER ////

#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x)       (x+0x00000270)
#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_PHYS(x)       (x+0x00000270)
#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RMSK          0x000003ff
#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_SHFT                   0
#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_IN(x)         \
	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RMSK)
#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_INM(x, mask)  \
	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_OUT(x, val)   \
	out_dword( HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff
#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT        0x0

//// Register REO_R0_REO2SW2_RING_MSI1_BASE_LSB ////

#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x)               (x+0x0000028c)
#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_PHYS(x)               (x+0x0000028c)
#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_RMSK                  0xffffffff
#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_SHFT                           0
#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_IN(x)                 \
	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_RMSK)
#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_INM(x, mask)          \
	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_OUT(x, val)           \
	out_dword( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), val)
#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_OUTM(x, mask, val)    \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR_BMSK             0xffffffff
#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR_SHFT                    0x0

//// Register REO_R0_REO2SW2_RING_MSI1_BASE_MSB ////

#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x)               (x+0x00000290)
#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_PHYS(x)               (x+0x00000290)
#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_RMSK                  0x000001ff
#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_SHFT                           0
#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_IN(x)                 \
	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_RMSK)
#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_INM(x, mask)          \
	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_OUT(x, val)           \
	out_dword( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), val)
#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_OUTM(x, mask, val)    \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK      0x00000100
#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT             0x8

#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR_BMSK             0x000000ff
#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR_SHFT                    0x0

//// Register REO_R0_REO2SW2_RING_MSI1_DATA ////

#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x)                   (x+0x00000294)
#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_PHYS(x)                   (x+0x00000294)
#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_RMSK                      0xffffffff
#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_SHFT                               0
#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_IN(x)                     \
	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_RMSK)
#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_INM(x, mask)              \
	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_OUT(x, val)               \
	out_dword( HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), val)
#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_OUTM(x, mask, val)        \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_VALUE_BMSK                0xffffffff
#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_VALUE_SHFT                       0x0

//// Register REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET ////

#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x)             (x+0x00000298)
#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_PHYS(x)             (x+0x00000298)
#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_RMSK                0x0000ffff
#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_SHFT                         0
#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_IN(x)               \
	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_RMSK)
#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_INM(x, mask)        \
	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_OUT(x, val)         \
	out_dword( HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), val)
#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val)  \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0

//// Register REO_R0_REO2SW3_RING_BASE_LSB ////

#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x)                    (x+0x0000029c)
#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_PHYS(x)                    (x+0x0000029c)
#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RMSK                       0xffffffff
#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_SHFT                                0
#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_IN(x)                      \
	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RMSK)
#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_INM(x, mask)               \
	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_OUT(x, val)                \
	out_dword( HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), val)
#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_OUTM(x, mask, val)         \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_BASE_LSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK    0xffffffff
#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT           0x0

//// Register REO_R0_REO2SW3_RING_BASE_MSB ////

#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x)                    (x+0x000002a0)
#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_PHYS(x)                    (x+0x000002a0)
#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RMSK                       0x0fffffff
#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_SHFT                                0
#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_IN(x)                      \
	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RMSK)
#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_INM(x, mask)               \
	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_OUT(x, val)                \
	out_dword( HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), val)
#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_OUTM(x, mask, val)         \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_BASE_MSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_SIZE_BMSK             0x0fffff00
#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_SIZE_SHFT                    0x8

#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK    0x000000ff
#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT           0x0

//// Register REO_R0_REO2SW3_RING_ID ////

#define HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x)                          (x+0x000002a4)
#define HWIO_REO_R0_REO2SW3_RING_ID_PHYS(x)                          (x+0x000002a4)
#define HWIO_REO_R0_REO2SW3_RING_ID_RMSK                             0x0000ffff
#define HWIO_REO_R0_REO2SW3_RING_ID_SHFT                                      0
#define HWIO_REO_R0_REO2SW3_RING_ID_IN(x)                            \
	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW3_RING_ID_RMSK)
#define HWIO_REO_R0_REO2SW3_RING_ID_INM(x, mask)                     \
	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW3_RING_ID_OUT(x, val)                      \
	out_dword( HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), val)
#define HWIO_REO_R0_REO2SW3_RING_ID_OUTM(x, mask, val)               \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_ID_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW3_RING_ID_RING_ID_BMSK                     0x0000ff00
#define HWIO_REO_R0_REO2SW3_RING_ID_RING_ID_SHFT                            0x8

#define HWIO_REO_R0_REO2SW3_RING_ID_ENTRY_SIZE_BMSK                  0x000000ff
#define HWIO_REO_R0_REO2SW3_RING_ID_ENTRY_SIZE_SHFT                         0x0

//// Register REO_R0_REO2SW3_RING_STATUS ////

#define HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x)                      (x+0x000002a8)
#define HWIO_REO_R0_REO2SW3_RING_STATUS_PHYS(x)                      (x+0x000002a8)
#define HWIO_REO_R0_REO2SW3_RING_STATUS_RMSK                         0xffffffff
#define HWIO_REO_R0_REO2SW3_RING_STATUS_SHFT                                  0
#define HWIO_REO_R0_REO2SW3_RING_STATUS_IN(x)                        \
	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW3_RING_STATUS_RMSK)
#define HWIO_REO_R0_REO2SW3_RING_STATUS_INM(x, mask)                 \
	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW3_RING_STATUS_OUT(x, val)                  \
	out_dword( HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), val)
#define HWIO_REO_R0_REO2SW3_RING_STATUS_OUTM(x, mask, val)           \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_STATUS_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_AVAIL_WORDS_BMSK         0xffff0000
#define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_AVAIL_WORDS_SHFT               0x10

#define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_VALID_WORDS_BMSK         0x0000ffff
#define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_VALID_WORDS_SHFT                0x0

//// Register REO_R0_REO2SW3_RING_MISC ////

#define HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x)                        (x+0x000002ac)
#define HWIO_REO_R0_REO2SW3_RING_MISC_PHYS(x)                        (x+0x000002ac)
#define HWIO_REO_R0_REO2SW3_RING_MISC_RMSK                           0x03ffffff
#define HWIO_REO_R0_REO2SW3_RING_MISC_SHFT                                    0
#define HWIO_REO_R0_REO2SW3_RING_MISC_IN(x)                          \
	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW3_RING_MISC_RMSK)
#define HWIO_REO_R0_REO2SW3_RING_MISC_INM(x, mask)                   \
	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW3_RING_MISC_OUT(x, val)                    \
	out_dword( HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), val)
#define HWIO_REO_R0_REO2SW3_RING_MISC_OUTM(x, mask, val)             \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_MISC_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW3_RING_MISC_LOOP_CNT_BMSK                  0x03c00000
#define HWIO_REO_R0_REO2SW3_RING_MISC_LOOP_CNT_SHFT                        0x16

#define HWIO_REO_R0_REO2SW3_RING_MISC_SPARE_CONTROL_BMSK             0x003fc000
#define HWIO_REO_R0_REO2SW3_RING_MISC_SPARE_CONTROL_SHFT                    0xe

#define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_SM_STATE2_BMSK            0x00003000
#define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_SM_STATE2_SHFT                   0xc

#define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_SM_STATE1_BMSK            0x00000f00
#define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_SM_STATE1_SHFT                   0x8

#define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_IS_IDLE_BMSK              0x00000080
#define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_IS_IDLE_SHFT                     0x7

#define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_ENABLE_BMSK               0x00000040
#define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_ENABLE_SHFT                      0x6

#define HWIO_REO_R0_REO2SW3_RING_MISC_DATA_TLV_SWAP_BIT_BMSK         0x00000020
#define HWIO_REO_R0_REO2SW3_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                0x5

#define HWIO_REO_R0_REO2SW3_RING_MISC_HOST_FW_SWAP_BIT_BMSK          0x00000010
#define HWIO_REO_R0_REO2SW3_RING_MISC_HOST_FW_SWAP_BIT_SHFT                 0x4

#define HWIO_REO_R0_REO2SW3_RING_MISC_MSI_SWAP_BIT_BMSK              0x00000008
#define HWIO_REO_R0_REO2SW3_RING_MISC_MSI_SWAP_BIT_SHFT                     0x3

#define HWIO_REO_R0_REO2SW3_RING_MISC_SECURITY_BIT_BMSK              0x00000004
#define HWIO_REO_R0_REO2SW3_RING_MISC_SECURITY_BIT_SHFT                     0x2

#define HWIO_REO_R0_REO2SW3_RING_MISC_LOOPCNT_DISABLE_BMSK           0x00000002
#define HWIO_REO_R0_REO2SW3_RING_MISC_LOOPCNT_DISABLE_SHFT                  0x1

#define HWIO_REO_R0_REO2SW3_RING_MISC_RING_ID_DISABLE_BMSK           0x00000001
#define HWIO_REO_R0_REO2SW3_RING_MISC_RING_ID_DISABLE_SHFT                  0x0

//// Register REO_R0_REO2SW3_RING_HP_ADDR_LSB ////

#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x)                 (x+0x000002b0)
#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_PHYS(x)                 (x+0x000002b0)
#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_RMSK                    0xffffffff
#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_SHFT                             0
#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_IN(x)                   \
	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_RMSK)
#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_INM(x, mask)            \
	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_OUT(x, val)             \
	out_dword( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), val)
#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_OUTM(x, mask, val)      \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT        0x0

//// Register REO_R0_REO2SW3_RING_HP_ADDR_MSB ////

#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x)                 (x+0x000002b4)
#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_PHYS(x)                 (x+0x000002b4)
#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_RMSK                    0x000000ff
#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_SHFT                             0
#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_IN(x)                   \
	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_RMSK)
#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_INM(x, mask)            \
	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_OUT(x, val)             \
	out_dword( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), val)
#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_OUTM(x, mask, val)      \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT        0x0

//// Register REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP ////

#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x)          (x+0x000002c0)
#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_PHYS(x)          (x+0x000002c0)
#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_RMSK             0xffffffff
#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_SHFT                      0
#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_IN(x)            \
	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_RMSK)
#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_INM(x, mask)     \
	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_OUT(x, val)      \
	out_dword( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), val)
#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10

#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT        0xf

#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT        0x0

//// Register REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS ////

#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x)         (x+0x000002c4)
#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_PHYS(x)         (x+0x000002c4)
#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_RMSK            0xffffffff
#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_SHFT                     0
#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_IN(x)           \
	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_RMSK)
#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_INM(x, mask)    \
	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_OUT(x, val)     \
	out_dword( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), val)
#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10

#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT        0xf

#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0

//// Register REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER ////

#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x)       (x+0x000002c8)
#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_PHYS(x)       (x+0x000002c8)
#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RMSK          0x000003ff
#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_SHFT                   0
#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_IN(x)         \
	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RMSK)
#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_INM(x, mask)  \
	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_OUT(x, val)   \
	out_dword( HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff
#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT        0x0

//// Register REO_R0_REO2SW3_RING_MSI1_BASE_LSB ////

#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x)               (x+0x000002e4)
#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_PHYS(x)               (x+0x000002e4)
#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_RMSK                  0xffffffff
#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_SHFT                           0
#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_IN(x)                 \
	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_RMSK)
#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_INM(x, mask)          \
	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_OUT(x, val)           \
	out_dword( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), val)
#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_OUTM(x, mask, val)    \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR_BMSK             0xffffffff
#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR_SHFT                    0x0

//// Register REO_R0_REO2SW3_RING_MSI1_BASE_MSB ////

#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x)               (x+0x000002e8)
#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_PHYS(x)               (x+0x000002e8)
#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_RMSK                  0x000001ff
#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_SHFT                           0
#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_IN(x)                 \
	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_RMSK)
#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_INM(x, mask)          \
	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_OUT(x, val)           \
	out_dword( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), val)
#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_OUTM(x, mask, val)    \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK      0x00000100
#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT             0x8

#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR_BMSK             0x000000ff
#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR_SHFT                    0x0

//// Register REO_R0_REO2SW3_RING_MSI1_DATA ////

#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x)                   (x+0x000002ec)
#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_PHYS(x)                   (x+0x000002ec)
#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_RMSK                      0xffffffff
#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_SHFT                               0
#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_IN(x)                     \
	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_RMSK)
#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_INM(x, mask)              \
	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_OUT(x, val)               \
	out_dword( HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), val)
#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_OUTM(x, mask, val)        \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_VALUE_BMSK                0xffffffff
#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_VALUE_SHFT                       0x0

//// Register REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET ////

#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x)             (x+0x000002f0)
#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_PHYS(x)             (x+0x000002f0)
#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_RMSK                0x0000ffff
#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_SHFT                         0
#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_IN(x)               \
	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_RMSK)
#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_INM(x, mask)        \
	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_OUT(x, val)         \
	out_dword( HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), val)
#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val)  \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0

//// Register REO_R0_REO2SW4_RING_BASE_LSB ////

#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x)                    (x+0x000002f4)
#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_PHYS(x)                    (x+0x000002f4)
#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RMSK                       0xffffffff
#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_SHFT                                0
#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_IN(x)                      \
	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RMSK)
#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_INM(x, mask)               \
	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_OUT(x, val)                \
	out_dword( HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), val)
#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_OUTM(x, mask, val)         \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_BASE_LSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK    0xffffffff
#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT           0x0

//// Register REO_R0_REO2SW4_RING_BASE_MSB ////

#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x)                    (x+0x000002f8)
#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_PHYS(x)                    (x+0x000002f8)
#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RMSK                       0x0fffffff
#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_SHFT                                0
#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_IN(x)                      \
	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RMSK)
#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_INM(x, mask)               \
	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_OUT(x, val)                \
	out_dword( HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), val)
#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_OUTM(x, mask, val)         \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_BASE_MSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_SIZE_BMSK             0x0fffff00
#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_SIZE_SHFT                    0x8

#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK    0x000000ff
#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT           0x0

//// Register REO_R0_REO2SW4_RING_ID ////

#define HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x)                          (x+0x000002fc)
#define HWIO_REO_R0_REO2SW4_RING_ID_PHYS(x)                          (x+0x000002fc)
#define HWIO_REO_R0_REO2SW4_RING_ID_RMSK                             0x0000ffff
#define HWIO_REO_R0_REO2SW4_RING_ID_SHFT                                      0
#define HWIO_REO_R0_REO2SW4_RING_ID_IN(x)                            \
	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW4_RING_ID_RMSK)
#define HWIO_REO_R0_REO2SW4_RING_ID_INM(x, mask)                     \
	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW4_RING_ID_OUT(x, val)                      \
	out_dword( HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), val)
#define HWIO_REO_R0_REO2SW4_RING_ID_OUTM(x, mask, val)               \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_ID_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW4_RING_ID_RING_ID_BMSK                     0x0000ff00
#define HWIO_REO_R0_REO2SW4_RING_ID_RING_ID_SHFT                            0x8

#define HWIO_REO_R0_REO2SW4_RING_ID_ENTRY_SIZE_BMSK                  0x000000ff
#define HWIO_REO_R0_REO2SW4_RING_ID_ENTRY_SIZE_SHFT                         0x0

//// Register REO_R0_REO2SW4_RING_STATUS ////

#define HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x)                      (x+0x00000300)
#define HWIO_REO_R0_REO2SW4_RING_STATUS_PHYS(x)                      (x+0x00000300)
#define HWIO_REO_R0_REO2SW4_RING_STATUS_RMSK                         0xffffffff
#define HWIO_REO_R0_REO2SW4_RING_STATUS_SHFT                                  0
#define HWIO_REO_R0_REO2SW4_RING_STATUS_IN(x)                        \
	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW4_RING_STATUS_RMSK)
#define HWIO_REO_R0_REO2SW4_RING_STATUS_INM(x, mask)                 \
	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW4_RING_STATUS_OUT(x, val)                  \
	out_dword( HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), val)
#define HWIO_REO_R0_REO2SW4_RING_STATUS_OUTM(x, mask, val)           \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_STATUS_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_AVAIL_WORDS_BMSK         0xffff0000
#define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_AVAIL_WORDS_SHFT               0x10

#define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_VALID_WORDS_BMSK         0x0000ffff
#define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_VALID_WORDS_SHFT                0x0

//// Register REO_R0_REO2SW4_RING_MISC ////

#define HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x)                        (x+0x00000304)
#define HWIO_REO_R0_REO2SW4_RING_MISC_PHYS(x)                        (x+0x00000304)
#define HWIO_REO_R0_REO2SW4_RING_MISC_RMSK                           0x03ffffff
#define HWIO_REO_R0_REO2SW4_RING_MISC_SHFT                                    0
#define HWIO_REO_R0_REO2SW4_RING_MISC_IN(x)                          \
	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW4_RING_MISC_RMSK)
#define HWIO_REO_R0_REO2SW4_RING_MISC_INM(x, mask)                   \
	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW4_RING_MISC_OUT(x, val)                    \
	out_dword( HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), val)
#define HWIO_REO_R0_REO2SW4_RING_MISC_OUTM(x, mask, val)             \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_MISC_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW4_RING_MISC_LOOP_CNT_BMSK                  0x03c00000
#define HWIO_REO_R0_REO2SW4_RING_MISC_LOOP_CNT_SHFT                        0x16

#define HWIO_REO_R0_REO2SW4_RING_MISC_SPARE_CONTROL_BMSK             0x003fc000
#define HWIO_REO_R0_REO2SW4_RING_MISC_SPARE_CONTROL_SHFT                    0xe

#define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_SM_STATE2_BMSK            0x00003000
#define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_SM_STATE2_SHFT                   0xc

#define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_SM_STATE1_BMSK            0x00000f00
#define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_SM_STATE1_SHFT                   0x8

#define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_IS_IDLE_BMSK              0x00000080
#define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_IS_IDLE_SHFT                     0x7

#define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_ENABLE_BMSK               0x00000040
#define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_ENABLE_SHFT                      0x6

#define HWIO_REO_R0_REO2SW4_RING_MISC_DATA_TLV_SWAP_BIT_BMSK         0x00000020
#define HWIO_REO_R0_REO2SW4_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                0x5

#define HWIO_REO_R0_REO2SW4_RING_MISC_HOST_FW_SWAP_BIT_BMSK          0x00000010
#define HWIO_REO_R0_REO2SW4_RING_MISC_HOST_FW_SWAP_BIT_SHFT                 0x4

#define HWIO_REO_R0_REO2SW4_RING_MISC_MSI_SWAP_BIT_BMSK              0x00000008
#define HWIO_REO_R0_REO2SW4_RING_MISC_MSI_SWAP_BIT_SHFT                     0x3

#define HWIO_REO_R0_REO2SW4_RING_MISC_SECURITY_BIT_BMSK              0x00000004
#define HWIO_REO_R0_REO2SW4_RING_MISC_SECURITY_BIT_SHFT                     0x2

#define HWIO_REO_R0_REO2SW4_RING_MISC_LOOPCNT_DISABLE_BMSK           0x00000002
#define HWIO_REO_R0_REO2SW4_RING_MISC_LOOPCNT_DISABLE_SHFT                  0x1

#define HWIO_REO_R0_REO2SW4_RING_MISC_RING_ID_DISABLE_BMSK           0x00000001
#define HWIO_REO_R0_REO2SW4_RING_MISC_RING_ID_DISABLE_SHFT                  0x0

//// Register REO_R0_REO2SW4_RING_HP_ADDR_LSB ////

#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x)                 (x+0x00000308)
#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_PHYS(x)                 (x+0x00000308)
#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_RMSK                    0xffffffff
#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_SHFT                             0
#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_IN(x)                   \
	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_RMSK)
#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_INM(x, mask)            \
	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_OUT(x, val)             \
	out_dword( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), val)
#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_OUTM(x, mask, val)      \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT        0x0

//// Register REO_R0_REO2SW4_RING_HP_ADDR_MSB ////

#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x)                 (x+0x0000030c)
#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_PHYS(x)                 (x+0x0000030c)
#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_RMSK                    0x000000ff
#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_SHFT                             0
#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_IN(x)                   \
	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_RMSK)
#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_INM(x, mask)            \
	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_OUT(x, val)             \
	out_dword( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), val)
#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_OUTM(x, mask, val)      \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT        0x0

//// Register REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP ////

#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x)          (x+0x00000318)
#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_PHYS(x)          (x+0x00000318)
#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_RMSK             0xffffffff
#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_SHFT                      0
#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_IN(x)            \
	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_RMSK)
#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_INM(x, mask)     \
	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_OUT(x, val)      \
	out_dword( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), val)
#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10

#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT        0xf

#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT        0x0

//// Register REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS ////

#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x)         (x+0x0000031c)
#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_PHYS(x)         (x+0x0000031c)
#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_RMSK            0xffffffff
#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_SHFT                     0
#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_IN(x)           \
	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_RMSK)
#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_INM(x, mask)    \
	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_OUT(x, val)     \
	out_dword( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), val)
#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10

#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT        0xf

#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0

//// Register REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER ////

#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x)       (x+0x00000320)
#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_PHYS(x)       (x+0x00000320)
#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RMSK          0x000003ff
#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_SHFT                   0
#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_IN(x)         \
	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RMSK)
#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_INM(x, mask)  \
	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_OUT(x, val)   \
	out_dword( HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff
#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT        0x0

//// Register REO_R0_REO2SW4_RING_MSI1_BASE_LSB ////

#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x)               (x+0x0000033c)
#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_PHYS(x)               (x+0x0000033c)
#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_RMSK                  0xffffffff
#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_SHFT                           0
#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_IN(x)                 \
	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_RMSK)
#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_INM(x, mask)          \
	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_OUT(x, val)           \
	out_dword( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), val)
#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_OUTM(x, mask, val)    \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR_BMSK             0xffffffff
#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR_SHFT                    0x0

//// Register REO_R0_REO2SW4_RING_MSI1_BASE_MSB ////

#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x)               (x+0x00000340)
#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_PHYS(x)               (x+0x00000340)
#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_RMSK                  0x000001ff
#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_SHFT                           0
#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_IN(x)                 \
	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_RMSK)
#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_INM(x, mask)          \
	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_OUT(x, val)           \
	out_dword( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), val)
#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_OUTM(x, mask, val)    \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK      0x00000100
#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT             0x8

#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR_BMSK             0x000000ff
#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR_SHFT                    0x0

//// Register REO_R0_REO2SW4_RING_MSI1_DATA ////

#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x)                   (x+0x00000344)
#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_PHYS(x)                   (x+0x00000344)
#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_RMSK                      0xffffffff
#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_SHFT                               0
#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_IN(x)                     \
	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_RMSK)
#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_INM(x, mask)              \
	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_OUT(x, val)               \
	out_dword( HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), val)
#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_OUTM(x, mask, val)        \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_VALUE_BMSK                0xffffffff
#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_VALUE_SHFT                       0x0

//// Register REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET ////

#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x)             (x+0x00000348)
#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_PHYS(x)             (x+0x00000348)
#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_RMSK                0x0000ffff
#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_SHFT                         0
#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_IN(x)               \
	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_RMSK)
#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_INM(x, mask)        \
	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_OUT(x, val)         \
	out_dword( HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), val)
#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val)  \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0

//// Register REO_R0_REO2TCL_RING_BASE_LSB ////

#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x)                    (x+0x000003fc)
#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_PHYS(x)                    (x+0x000003fc)
#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_RMSK                       0xffffffff
#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_SHFT                                0
#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_IN(x)                      \
	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_BASE_LSB_RMSK)
#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_INM(x, mask)               \
	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_OUT(x, val)                \
	out_dword( HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), val)
#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_OUTM(x, mask, val)         \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_BASE_LSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK    0xffffffff
#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT           0x0

//// Register REO_R0_REO2TCL_RING_BASE_MSB ////

#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x)                    (x+0x00000400)
#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_PHYS(x)                    (x+0x00000400)
#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RMSK                       0x0fffffff
#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_SHFT                                0
#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_IN(x)                      \
	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RMSK)
#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_INM(x, mask)               \
	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_OUT(x, val)                \
	out_dword( HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), val)
#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_OUTM(x, mask, val)         \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_BASE_MSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK             0x0fffff00
#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT                    0x8

#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK    0x000000ff
#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT           0x0

//// Register REO_R0_REO2TCL_RING_ID ////

#define HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x)                          (x+0x00000404)
#define HWIO_REO_R0_REO2TCL_RING_ID_PHYS(x)                          (x+0x00000404)
#define HWIO_REO_R0_REO2TCL_RING_ID_RMSK                             0x0000ffff
#define HWIO_REO_R0_REO2TCL_RING_ID_SHFT                                      0
#define HWIO_REO_R0_REO2TCL_RING_ID_IN(x)                            \
	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), HWIO_REO_R0_REO2TCL_RING_ID_RMSK)
#define HWIO_REO_R0_REO2TCL_RING_ID_INM(x, mask)                     \
	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), mask) 
#define HWIO_REO_R0_REO2TCL_RING_ID_OUT(x, val)                      \
	out_dword( HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), val)
#define HWIO_REO_R0_REO2TCL_RING_ID_OUTM(x, mask, val)               \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_ID_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2TCL_RING_ID_RING_ID_BMSK                     0x0000ff00
#define HWIO_REO_R0_REO2TCL_RING_ID_RING_ID_SHFT                            0x8

#define HWIO_REO_R0_REO2TCL_RING_ID_ENTRY_SIZE_BMSK                  0x000000ff
#define HWIO_REO_R0_REO2TCL_RING_ID_ENTRY_SIZE_SHFT                         0x0

//// Register REO_R0_REO2TCL_RING_STATUS ////

#define HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x)                      (x+0x00000408)
#define HWIO_REO_R0_REO2TCL_RING_STATUS_PHYS(x)                      (x+0x00000408)
#define HWIO_REO_R0_REO2TCL_RING_STATUS_RMSK                         0xffffffff
#define HWIO_REO_R0_REO2TCL_RING_STATUS_SHFT                                  0
#define HWIO_REO_R0_REO2TCL_RING_STATUS_IN(x)                        \
	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2TCL_RING_STATUS_RMSK)
#define HWIO_REO_R0_REO2TCL_RING_STATUS_INM(x, mask)                 \
	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), mask) 
#define HWIO_REO_R0_REO2TCL_RING_STATUS_OUT(x, val)                  \
	out_dword( HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), val)
#define HWIO_REO_R0_REO2TCL_RING_STATUS_OUTM(x, mask, val)           \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_STATUS_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2TCL_RING_STATUS_NUM_AVAIL_WORDS_BMSK         0xffff0000
#define HWIO_REO_R0_REO2TCL_RING_STATUS_NUM_AVAIL_WORDS_SHFT               0x10

#define HWIO_REO_R0_REO2TCL_RING_STATUS_NUM_VALID_WORDS_BMSK         0x0000ffff
#define HWIO_REO_R0_REO2TCL_RING_STATUS_NUM_VALID_WORDS_SHFT                0x0

//// Register REO_R0_REO2TCL_RING_MISC ////

#define HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x)                        (x+0x0000040c)
#define HWIO_REO_R0_REO2TCL_RING_MISC_PHYS(x)                        (x+0x0000040c)
#define HWIO_REO_R0_REO2TCL_RING_MISC_RMSK                           0x03ffffff
#define HWIO_REO_R0_REO2TCL_RING_MISC_SHFT                                    0
#define HWIO_REO_R0_REO2TCL_RING_MISC_IN(x)                          \
	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), HWIO_REO_R0_REO2TCL_RING_MISC_RMSK)
#define HWIO_REO_R0_REO2TCL_RING_MISC_INM(x, mask)                   \
	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), mask) 
#define HWIO_REO_R0_REO2TCL_RING_MISC_OUT(x, val)                    \
	out_dword( HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), val)
#define HWIO_REO_R0_REO2TCL_RING_MISC_OUTM(x, mask, val)             \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_MISC_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2TCL_RING_MISC_LOOP_CNT_BMSK                  0x03c00000
#define HWIO_REO_R0_REO2TCL_RING_MISC_LOOP_CNT_SHFT                        0x16

#define HWIO_REO_R0_REO2TCL_RING_MISC_SPARE_CONTROL_BMSK             0x003fc000
#define HWIO_REO_R0_REO2TCL_RING_MISC_SPARE_CONTROL_SHFT                    0xe

#define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_SM_STATE2_BMSK            0x00003000
#define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_SM_STATE2_SHFT                   0xc

#define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_SM_STATE1_BMSK            0x00000f00
#define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_SM_STATE1_SHFT                   0x8

#define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_IS_IDLE_BMSK              0x00000080
#define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_IS_IDLE_SHFT                     0x7

#define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_ENABLE_BMSK               0x00000040
#define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_ENABLE_SHFT                      0x6

#define HWIO_REO_R0_REO2TCL_RING_MISC_DATA_TLV_SWAP_BIT_BMSK         0x00000020
#define HWIO_REO_R0_REO2TCL_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                0x5

#define HWIO_REO_R0_REO2TCL_RING_MISC_HOST_FW_SWAP_BIT_BMSK          0x00000010
#define HWIO_REO_R0_REO2TCL_RING_MISC_HOST_FW_SWAP_BIT_SHFT                 0x4

#define HWIO_REO_R0_REO2TCL_RING_MISC_MSI_SWAP_BIT_BMSK              0x00000008
#define HWIO_REO_R0_REO2TCL_RING_MISC_MSI_SWAP_BIT_SHFT                     0x3

#define HWIO_REO_R0_REO2TCL_RING_MISC_SECURITY_BIT_BMSK              0x00000004
#define HWIO_REO_R0_REO2TCL_RING_MISC_SECURITY_BIT_SHFT                     0x2

#define HWIO_REO_R0_REO2TCL_RING_MISC_LOOPCNT_DISABLE_BMSK           0x00000002
#define HWIO_REO_R0_REO2TCL_RING_MISC_LOOPCNT_DISABLE_SHFT                  0x1

#define HWIO_REO_R0_REO2TCL_RING_MISC_RING_ID_DISABLE_BMSK           0x00000001
#define HWIO_REO_R0_REO2TCL_RING_MISC_RING_ID_DISABLE_SHFT                  0x0

//// Register REO_R0_REO2TCL_RING_HP_ADDR_LSB ////

#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x)                 (x+0x00000410)
#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_PHYS(x)                 (x+0x00000410)
#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_RMSK                    0xffffffff
#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_SHFT                             0
#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_IN(x)                   \
	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_RMSK)
#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_INM(x, mask)            \
	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_OUT(x, val)             \
	out_dword( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), val)
#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_OUTM(x, mask, val)      \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT        0x0

//// Register REO_R0_REO2TCL_RING_HP_ADDR_MSB ////

#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x)                 (x+0x00000414)
#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_PHYS(x)                 (x+0x00000414)
#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_RMSK                    0x000000ff
#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_SHFT                             0
#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_IN(x)                   \
	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_RMSK)
#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_INM(x, mask)            \
	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_OUT(x, val)             \
	out_dword( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), val)
#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_OUTM(x, mask, val)      \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT        0x0

//// Register REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP ////

#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x)          (x+0x00000420)
#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_PHYS(x)          (x+0x00000420)
#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_RMSK             0xffffffff
#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_SHFT                      0
#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_IN(x)            \
	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_RMSK)
#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_INM(x, mask)     \
	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 
#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_OUT(x, val)      \
	out_dword( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), val)
#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10

#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT        0xf

#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT        0x0

//// Register REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS ////

#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x)         (x+0x00000424)
#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_PHYS(x)         (x+0x00000424)
#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_RMSK            0xffffffff
#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_SHFT                     0
#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_IN(x)           \
	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_RMSK)
#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_INM(x, mask)    \
	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 
#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_OUT(x, val)     \
	out_dword( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), val)
#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10

#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT        0xf

#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0

//// Register REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER ////

#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x)       (x+0x00000428)
#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_PHYS(x)       (x+0x00000428)
#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RMSK          0x000003ff
#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_SHFT                   0
#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_IN(x)         \
	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RMSK)
#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_INM(x, mask)  \
	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 
#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_OUT(x, val)   \
	out_dword( HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff
#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT        0x0

//// Register REO_R0_REO2TCL_RING_MSI1_BASE_LSB ////

#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x)               (x+0x00000444)
#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_PHYS(x)               (x+0x00000444)
#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_RMSK                  0xffffffff
#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_SHFT                           0
#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_IN(x)                 \
	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_RMSK)
#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_INM(x, mask)          \
	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_OUT(x, val)           \
	out_dword( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), val)
#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_OUTM(x, mask, val)    \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR_BMSK             0xffffffff
#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR_SHFT                    0x0

//// Register REO_R0_REO2TCL_RING_MSI1_BASE_MSB ////

#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x)               (x+0x00000448)
#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_PHYS(x)               (x+0x00000448)
#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_RMSK                  0x000001ff
#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_SHFT                           0
#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_IN(x)                 \
	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_RMSK)
#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_INM(x, mask)          \
	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_OUT(x, val)           \
	out_dword( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), val)
#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_OUTM(x, mask, val)    \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK      0x00000100
#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT             0x8

#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR_BMSK             0x000000ff
#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR_SHFT                    0x0

//// Register REO_R0_REO2TCL_RING_MSI1_DATA ////

#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x)                   (x+0x0000044c)
#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_PHYS(x)                   (x+0x0000044c)
#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_RMSK                      0xffffffff
#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_SHFT                               0
#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_IN(x)                     \
	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_RMSK)
#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_INM(x, mask)              \
	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), mask) 
#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_OUT(x, val)               \
	out_dword( HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), val)
#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_OUTM(x, mask, val)        \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_VALUE_BMSK                0xffffffff
#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_VALUE_SHFT                       0x0

//// Register REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET ////

#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x)             (x+0x00000450)
#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_PHYS(x)             (x+0x00000450)
#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_RMSK                0x0000ffff
#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_SHFT                         0
#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_IN(x)               \
	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_RMSK)
#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_INM(x, mask)        \
	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_OUT(x, val)         \
	out_dword( HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), val)
#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val)  \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0

//// Register REO_R0_REO2FW_RING_BASE_LSB ////

#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x)                     (x+0x00000454)
#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_PHYS(x)                     (x+0x00000454)
#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_RMSK                        0xffffffff
#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_SHFT                                 0
#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_IN(x)                       \
	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_BASE_LSB_RMSK)
#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_INM(x, mask)                \
	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_OUT(x, val)                 \
	out_dword( HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), val)
#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_OUTM(x, mask, val)          \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_BASE_LSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK     0xffffffff
#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT            0x0

//// Register REO_R0_REO2FW_RING_BASE_MSB ////

#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x)                     (x+0x00000458)
#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_PHYS(x)                     (x+0x00000458)
#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RMSK                        0x0fffffff
#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_SHFT                                 0
#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_IN(x)                       \
	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_BASE_MSB_RMSK)
#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_INM(x, mask)                \
	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_OUT(x, val)                 \
	out_dword( HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), val)
#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_OUTM(x, mask, val)          \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_BASE_MSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_SIZE_BMSK              0x0fffff00
#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_SIZE_SHFT                     0x8

#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK     0x000000ff
#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT            0x0

//// Register REO_R0_REO2FW_RING_ID ////

#define HWIO_REO_R0_REO2FW_RING_ID_ADDR(x)                           (x+0x0000045c)
#define HWIO_REO_R0_REO2FW_RING_ID_PHYS(x)                           (x+0x0000045c)
#define HWIO_REO_R0_REO2FW_RING_ID_RMSK                              0x0000ffff
#define HWIO_REO_R0_REO2FW_RING_ID_SHFT                                       0
#define HWIO_REO_R0_REO2FW_RING_ID_IN(x)                             \
	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), HWIO_REO_R0_REO2FW_RING_ID_RMSK)
#define HWIO_REO_R0_REO2FW_RING_ID_INM(x, mask)                      \
	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), mask) 
#define HWIO_REO_R0_REO2FW_RING_ID_OUT(x, val)                       \
	out_dword( HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), val)
#define HWIO_REO_R0_REO2FW_RING_ID_OUTM(x, mask, val)                \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_ID_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2FW_RING_ID_RING_ID_BMSK                      0x0000ff00
#define HWIO_REO_R0_REO2FW_RING_ID_RING_ID_SHFT                             0x8

#define HWIO_REO_R0_REO2FW_RING_ID_ENTRY_SIZE_BMSK                   0x000000ff
#define HWIO_REO_R0_REO2FW_RING_ID_ENTRY_SIZE_SHFT                          0x0

//// Register REO_R0_REO2FW_RING_STATUS ////

#define HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x)                       (x+0x00000460)
#define HWIO_REO_R0_REO2FW_RING_STATUS_PHYS(x)                       (x+0x00000460)
#define HWIO_REO_R0_REO2FW_RING_STATUS_RMSK                          0xffffffff
#define HWIO_REO_R0_REO2FW_RING_STATUS_SHFT                                   0
#define HWIO_REO_R0_REO2FW_RING_STATUS_IN(x)                         \
	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2FW_RING_STATUS_RMSK)
#define HWIO_REO_R0_REO2FW_RING_STATUS_INM(x, mask)                  \
	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), mask) 
#define HWIO_REO_R0_REO2FW_RING_STATUS_OUT(x, val)                   \
	out_dword( HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), val)
#define HWIO_REO_R0_REO2FW_RING_STATUS_OUTM(x, mask, val)            \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_STATUS_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_AVAIL_WORDS_BMSK          0xffff0000
#define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_AVAIL_WORDS_SHFT                0x10

#define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_VALID_WORDS_BMSK          0x0000ffff
#define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_VALID_WORDS_SHFT                 0x0

//// Register REO_R0_REO2FW_RING_MISC ////

#define HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x)                         (x+0x00000464)
#define HWIO_REO_R0_REO2FW_RING_MISC_PHYS(x)                         (x+0x00000464)
#define HWIO_REO_R0_REO2FW_RING_MISC_RMSK                            0x03ffffff
#define HWIO_REO_R0_REO2FW_RING_MISC_SHFT                                     0
#define HWIO_REO_R0_REO2FW_RING_MISC_IN(x)                           \
	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), HWIO_REO_R0_REO2FW_RING_MISC_RMSK)
#define HWIO_REO_R0_REO2FW_RING_MISC_INM(x, mask)                    \
	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), mask) 
#define HWIO_REO_R0_REO2FW_RING_MISC_OUT(x, val)                     \
	out_dword( HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), val)
#define HWIO_REO_R0_REO2FW_RING_MISC_OUTM(x, mask, val)              \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_MISC_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2FW_RING_MISC_LOOP_CNT_BMSK                   0x03c00000
#define HWIO_REO_R0_REO2FW_RING_MISC_LOOP_CNT_SHFT                         0x16

#define HWIO_REO_R0_REO2FW_RING_MISC_SPARE_CONTROL_BMSK              0x003fc000
#define HWIO_REO_R0_REO2FW_RING_MISC_SPARE_CONTROL_SHFT                     0xe

#define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_SM_STATE2_BMSK             0x00003000
#define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_SM_STATE2_SHFT                    0xc

#define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_SM_STATE1_BMSK             0x00000f00
#define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_SM_STATE1_SHFT                    0x8

#define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_IS_IDLE_BMSK               0x00000080
#define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_IS_IDLE_SHFT                      0x7

#define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_ENABLE_BMSK                0x00000040
#define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_ENABLE_SHFT                       0x6

#define HWIO_REO_R0_REO2FW_RING_MISC_DATA_TLV_SWAP_BIT_BMSK          0x00000020
#define HWIO_REO_R0_REO2FW_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                 0x5

#define HWIO_REO_R0_REO2FW_RING_MISC_HOST_FW_SWAP_BIT_BMSK           0x00000010
#define HWIO_REO_R0_REO2FW_RING_MISC_HOST_FW_SWAP_BIT_SHFT                  0x4

#define HWIO_REO_R0_REO2FW_RING_MISC_MSI_SWAP_BIT_BMSK               0x00000008
#define HWIO_REO_R0_REO2FW_RING_MISC_MSI_SWAP_BIT_SHFT                      0x3

#define HWIO_REO_R0_REO2FW_RING_MISC_SECURITY_BIT_BMSK               0x00000004
#define HWIO_REO_R0_REO2FW_RING_MISC_SECURITY_BIT_SHFT                      0x2

#define HWIO_REO_R0_REO2FW_RING_MISC_LOOPCNT_DISABLE_BMSK            0x00000002
#define HWIO_REO_R0_REO2FW_RING_MISC_LOOPCNT_DISABLE_SHFT                   0x1

#define HWIO_REO_R0_REO2FW_RING_MISC_RING_ID_DISABLE_BMSK            0x00000001
#define HWIO_REO_R0_REO2FW_RING_MISC_RING_ID_DISABLE_SHFT                   0x0

//// Register REO_R0_REO2FW_RING_HP_ADDR_LSB ////

#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x)                  (x+0x00000468)
#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_PHYS(x)                  (x+0x00000468)
#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_RMSK                     0xffffffff
#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_SHFT                              0
#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_IN(x)                    \
	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_RMSK)
#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_INM(x, mask)             \
	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_OUT(x, val)              \
	out_dword( HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), val)
#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_OUTM(x, mask, val)       \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT        0x0

//// Register REO_R0_REO2FW_RING_HP_ADDR_MSB ////

#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x)                  (x+0x0000046c)
#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_PHYS(x)                  (x+0x0000046c)
#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_RMSK                     0x000000ff
#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_SHFT                              0
#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_IN(x)                    \
	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_RMSK)
#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_INM(x, mask)             \
	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_OUT(x, val)              \
	out_dword( HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), val)
#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_OUTM(x, mask, val)       \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT        0x0

//// Register REO_R0_REO2FW_RING_PRODUCER_INT_SETUP ////

#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x)           (x+0x00000478)
#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_PHYS(x)           (x+0x00000478)
#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_RMSK              0xffffffff
#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_SHFT                       0
#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_IN(x)             \
	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_RMSK)
#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_INM(x, mask)      \
	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 
#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_OUT(x, val)       \
	out_dword( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), val)
#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10

#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT        0xf

#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT        0x0

//// Register REO_R0_REO2FW_RING_PRODUCER_INT_STATUS ////

#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x)          (x+0x0000047c)
#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_PHYS(x)          (x+0x0000047c)
#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_RMSK             0xffffffff
#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_SHFT                      0
#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_IN(x)            \
	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_RMSK)
#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_INM(x, mask)     \
	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 
#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_OUT(x, val)      \
	out_dword( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), val)
#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10

#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT        0xf

#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0

//// Register REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER ////

#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x)        (x+0x00000480)
#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_PHYS(x)        (x+0x00000480)
#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RMSK           0x000003ff
#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_SHFT                    0
#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_IN(x)          \
	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RMSK)
#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_INM(x, mask)   \
	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 
#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_OUT(x, val)    \
	out_dword( HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff
#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT        0x0

//// Register REO_R0_REO2FW_RING_MSI1_BASE_LSB ////

#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x)                (x+0x0000049c)
#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_PHYS(x)                (x+0x0000049c)
#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_RMSK                   0xffffffff
#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_SHFT                            0
#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_IN(x)                  \
	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_RMSK)
#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_INM(x, mask)           \
	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_OUT(x, val)            \
	out_dword( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), val)
#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_OUTM(x, mask, val)     \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR_BMSK              0xffffffff
#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR_SHFT                     0x0

//// Register REO_R0_REO2FW_RING_MSI1_BASE_MSB ////

#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x)                (x+0x000004a0)
#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_PHYS(x)                (x+0x000004a0)
#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_RMSK                   0x000001ff
#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_SHFT                            0
#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_IN(x)                  \
	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_RMSK)
#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_INM(x, mask)           \
	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_OUT(x, val)            \
	out_dword( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), val)
#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_OUTM(x, mask, val)     \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK       0x00000100
#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT              0x8

#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR_BMSK              0x000000ff
#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR_SHFT                     0x0

//// Register REO_R0_REO2FW_RING_MSI1_DATA ////

#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x)                    (x+0x000004a4)
#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_PHYS(x)                    (x+0x000004a4)
#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_RMSK                       0xffffffff
#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_SHFT                                0
#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_IN(x)                      \
	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2FW_RING_MSI1_DATA_RMSK)
#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_INM(x, mask)               \
	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), mask) 
#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_OUT(x, val)                \
	out_dword( HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), val)
#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_OUTM(x, mask, val)         \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_MSI1_DATA_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_VALUE_BMSK                 0xffffffff
#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_VALUE_SHFT                        0x0

//// Register REO_R0_REO2FW_RING_HP_TP_SW_OFFSET ////

#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x)              (x+0x000004a8)
#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_PHYS(x)              (x+0x000004a8)
#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_RMSK                 0x0000ffff
#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_SHFT                          0
#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_IN(x)                \
	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_RMSK)
#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_INM(x, mask)         \
	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_OUT(x, val)          \
	out_dword( HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), val)
#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val)   \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0

//// Register REO_R0_REO_RELEASE_RING_BASE_LSB ////

#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x)                (x+0x000004ac)
#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_PHYS(x)                (x+0x000004ac)
#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RMSK                   0xffffffff
#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_SHFT                            0
#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_IN(x)                  \
	in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RMSK)
#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_INM(x, mask)           \
	in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_OUT(x, val)            \
	out_dword( HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), val)
#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_OUTM(x, mask, val)     \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT        0x0

//// Register REO_R0_REO_RELEASE_RING_BASE_MSB ////

#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x)                (x+0x000004b0)
#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_PHYS(x)                (x+0x000004b0)
#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RMSK                   0x00ffffff
#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_SHFT                            0
#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_IN(x)                  \
	in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RMSK)
#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_INM(x, mask)           \
	in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_OUT(x, val)            \
	out_dword( HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), val)
#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_OUTM(x, mask, val)     \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK         0x00ffff00
#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT                0x8

#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT        0x0

//// Register REO_R0_REO_RELEASE_RING_ID ////

#define HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x)                      (x+0x000004b4)
#define HWIO_REO_R0_REO_RELEASE_RING_ID_PHYS(x)                      (x+0x000004b4)
#define HWIO_REO_R0_REO_RELEASE_RING_ID_RMSK                         0x0000ffff
#define HWIO_REO_R0_REO_RELEASE_RING_ID_SHFT                                  0
#define HWIO_REO_R0_REO_RELEASE_RING_ID_IN(x)                        \
	in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_ID_RMSK)
#define HWIO_REO_R0_REO_RELEASE_RING_ID_INM(x, mask)                 \
	in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), mask) 
#define HWIO_REO_R0_REO_RELEASE_RING_ID_OUT(x, val)                  \
	out_dword( HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), val)
#define HWIO_REO_R0_REO_RELEASE_RING_ID_OUTM(x, mask, val)           \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_ID_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO_RELEASE_RING_ID_RING_ID_BMSK                 0x0000ff00
#define HWIO_REO_R0_REO_RELEASE_RING_ID_RING_ID_SHFT                        0x8

#define HWIO_REO_R0_REO_RELEASE_RING_ID_ENTRY_SIZE_BMSK              0x000000ff
#define HWIO_REO_R0_REO_RELEASE_RING_ID_ENTRY_SIZE_SHFT                     0x0

//// Register REO_R0_REO_RELEASE_RING_STATUS ////

#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x)                  (x+0x000004b8)
#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_PHYS(x)                  (x+0x000004b8)
#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_RMSK                     0xffffffff
#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_SHFT                              0
#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_IN(x)                    \
	in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_STATUS_RMSK)
#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_INM(x, mask)             \
	in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), mask) 
#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_OUT(x, val)              \
	out_dword( HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), val)
#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_OUTM(x, mask, val)       \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_STATUS_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK     0xffff0000
#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT           0x10

#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK     0x0000ffff
#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT            0x0

//// Register REO_R0_REO_RELEASE_RING_MISC ////

#define HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x)                    (x+0x000004bc)
#define HWIO_REO_R0_REO_RELEASE_RING_MISC_PHYS(x)                    (x+0x000004bc)
#define HWIO_REO_R0_REO_RELEASE_RING_MISC_RMSK                       0x03ffffff
#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SHFT                                0
#define HWIO_REO_R0_REO_RELEASE_RING_MISC_IN(x)                      \
	in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_MISC_RMSK)
#define HWIO_REO_R0_REO_RELEASE_RING_MISC_INM(x, mask)               \
	in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), mask) 
#define HWIO_REO_R0_REO_RELEASE_RING_MISC_OUT(x, val)                \
	out_dword( HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), val)
#define HWIO_REO_R0_REO_RELEASE_RING_MISC_OUTM(x, mask, val)         \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_MISC_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO_RELEASE_RING_MISC_LOOP_CNT_BMSK              0x03c00000
#define HWIO_REO_R0_REO_RELEASE_RING_MISC_LOOP_CNT_SHFT                    0x16

#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SPARE_CONTROL_BMSK         0x003fc000
#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SPARE_CONTROL_SHFT                0xe

#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK        0x00003000
#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT               0xc

#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK        0x00000f00
#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT               0x8

#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK          0x00000080
#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT                 0x7

#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_ENABLE_BMSK           0x00000040
#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_ENABLE_SHFT                  0x6

#define HWIO_REO_R0_REO_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK     0x00000020
#define HWIO_REO_R0_REO_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT            0x5

#define HWIO_REO_R0_REO_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK      0x00000010
#define HWIO_REO_R0_REO_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT             0x4

#define HWIO_REO_R0_REO_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK          0x00000008
#define HWIO_REO_R0_REO_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT                 0x3

#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SECURITY_BIT_BMSK          0x00000004
#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SECURITY_BIT_SHFT                 0x2

#define HWIO_REO_R0_REO_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK       0x00000002
#define HWIO_REO_R0_REO_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT              0x1

#define HWIO_REO_R0_REO_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK       0x00000001
#define HWIO_REO_R0_REO_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT              0x0

//// Register REO_R0_REO_RELEASE_RING_HP_ADDR_LSB ////

#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x)             (x+0x000004c0)
#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_PHYS(x)             (x+0x000004c0)
#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_RMSK                0xffffffff
#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_SHFT                         0
#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_IN(x)               \
	in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_RMSK)
#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_INM(x, mask)        \
	in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_OUT(x, val)         \
	out_dword( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), val)
#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_OUTM(x, mask, val)  \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT        0x0

//// Register REO_R0_REO_RELEASE_RING_HP_ADDR_MSB ////

#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x)             (x+0x000004c4)
#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_PHYS(x)             (x+0x000004c4)
#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_RMSK                0x000000ff
#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_SHFT                         0
#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_IN(x)               \
	in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_RMSK)
#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_INM(x, mask)        \
	in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_OUT(x, val)         \
	out_dword( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), val)
#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_OUTM(x, mask, val)  \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT        0x0

//// Register REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP ////

#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)      (x+0x000004d0)
#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x)      (x+0x000004d0)
#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_RMSK         0xffffffff
#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_SHFT                  0
#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)        \
	in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_RMSK)
#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, mask) \
	in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 
#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, val)  \
	out_dword( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), val)
#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10

#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT        0xf

#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT        0x0

//// Register REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS ////

#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)     (x+0x000004d4)
#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x)     (x+0x000004d4)
#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_RMSK        0xffffffff
#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_SHFT                 0
#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)       \
	in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_RMSK)
#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, mask) \
	in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 
#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_OUT(x, val) \
	out_dword( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), val)
#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10

#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT        0xf

#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0

//// Register REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER ////

#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)   (x+0x000004d8)
#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x)   (x+0x000004d8)
#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK      0x000003ff
#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_SHFT               0
#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)     \
	in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK)
#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
	in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 
#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
	out_dword( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff
#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT        0x0

//// Register REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB ////

#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)           (x+0x000004f4)
#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_PHYS(x)           (x+0x000004f4)
#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_RMSK              0xffffffff
#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_SHFT                       0
#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_IN(x)             \
	in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_RMSK)
#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask)      \
	in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val)       \
	out_dword( HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val)
#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK         0xffffffff
#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT                0x0

//// Register REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB ////

#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)           (x+0x000004f8)
#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_PHYS(x)           (x+0x000004f8)
#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_RMSK              0x000001ff
#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_SHFT                       0
#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_IN(x)             \
	in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_RMSK)
#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask)      \
	in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val)       \
	out_dword( HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val)
#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK  0x00000100
#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT         0x8

#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK         0x000000ff
#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT                0x0

//// Register REO_R0_REO_RELEASE_RING_MSI1_DATA ////

#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_ADDR(x)               (x+0x000004fc)
#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_PHYS(x)               (x+0x000004fc)
#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_RMSK                  0xffffffff
#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_SHFT                           0
#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_IN(x)                 \
	in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_RMSK)
#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_INM(x, mask)          \
	in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_ADDR(x), mask) 
#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_OUT(x, val)           \
	out_dword( HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_ADDR(x), val)
#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val)    \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_VALUE_BMSK            0xffffffff
#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_VALUE_SHFT                   0x0

//// Register REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET ////

#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)         (x+0x00000500)
#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x)         (x+0x00000500)
#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_RMSK            0x0000ffff
#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_SHFT                     0
#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)           \
	in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_RMSK)
#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask)    \
	in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val)     \
	out_dword( HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val)
#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0

//// Register REO_R0_REO_STATUS_RING_BASE_LSB ////

#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x)                 (x+0x00000504)
#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_PHYS(x)                 (x+0x00000504)
#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RMSK                    0xffffffff
#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_SHFT                             0
#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_IN(x)                   \
	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RMSK)
#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_INM(x, mask)            \
	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_OUT(x, val)             \
	out_dword( HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), val)
#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_OUTM(x, mask, val)      \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT        0x0

//// Register REO_R0_REO_STATUS_RING_BASE_MSB ////

#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x)                 (x+0x00000508)
#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_PHYS(x)                 (x+0x00000508)
#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RMSK                    0x00ffffff
#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_SHFT                             0
#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_IN(x)                   \
	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RMSK)
#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_INM(x, mask)            \
	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_OUT(x, val)             \
	out_dword( HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), val)
#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_OUTM(x, mask, val)      \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK          0x00ffff00
#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT                 0x8

#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT        0x0

//// Register REO_R0_REO_STATUS_RING_ID ////

#define HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x)                       (x+0x0000050c)
#define HWIO_REO_R0_REO_STATUS_RING_ID_PHYS(x)                       (x+0x0000050c)
#define HWIO_REO_R0_REO_STATUS_RING_ID_RMSK                          0x0000ffff
#define HWIO_REO_R0_REO_STATUS_RING_ID_SHFT                                   0
#define HWIO_REO_R0_REO_STATUS_RING_ID_IN(x)                         \
	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_ID_RMSK)
#define HWIO_REO_R0_REO_STATUS_RING_ID_INM(x, mask)                  \
	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), mask) 
#define HWIO_REO_R0_REO_STATUS_RING_ID_OUT(x, val)                   \
	out_dword( HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), val)
#define HWIO_REO_R0_REO_STATUS_RING_ID_OUTM(x, mask, val)            \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_ID_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO_STATUS_RING_ID_RING_ID_BMSK                  0x0000ff00
#define HWIO_REO_R0_REO_STATUS_RING_ID_RING_ID_SHFT                         0x8

#define HWIO_REO_R0_REO_STATUS_RING_ID_ENTRY_SIZE_BMSK               0x000000ff
#define HWIO_REO_R0_REO_STATUS_RING_ID_ENTRY_SIZE_SHFT                      0x0

//// Register REO_R0_REO_STATUS_RING_STATUS ////

#define HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x)                   (x+0x00000510)
#define HWIO_REO_R0_REO_STATUS_RING_STATUS_PHYS(x)                   (x+0x00000510)
#define HWIO_REO_R0_REO_STATUS_RING_STATUS_RMSK                      0xffffffff
#define HWIO_REO_R0_REO_STATUS_RING_STATUS_SHFT                               0
#define HWIO_REO_R0_REO_STATUS_RING_STATUS_IN(x)                     \
	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_STATUS_RMSK)
#define HWIO_REO_R0_REO_STATUS_RING_STATUS_INM(x, mask)              \
	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), mask) 
#define HWIO_REO_R0_REO_STATUS_RING_STATUS_OUT(x, val)               \
	out_dword( HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), val)
#define HWIO_REO_R0_REO_STATUS_RING_STATUS_OUTM(x, mask, val)        \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_STATUS_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK      0xffff0000
#define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT            0x10

#define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK      0x0000ffff
#define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT             0x0

//// Register REO_R0_REO_STATUS_RING_MISC ////

#define HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x)                     (x+0x00000514)
#define HWIO_REO_R0_REO_STATUS_RING_MISC_PHYS(x)                     (x+0x00000514)
#define HWIO_REO_R0_REO_STATUS_RING_MISC_RMSK                        0x03ffffff
#define HWIO_REO_R0_REO_STATUS_RING_MISC_SHFT                                 0
#define HWIO_REO_R0_REO_STATUS_RING_MISC_IN(x)                       \
	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_MISC_RMSK)
#define HWIO_REO_R0_REO_STATUS_RING_MISC_INM(x, mask)                \
	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), mask) 
#define HWIO_REO_R0_REO_STATUS_RING_MISC_OUT(x, val)                 \
	out_dword( HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), val)
#define HWIO_REO_R0_REO_STATUS_RING_MISC_OUTM(x, mask, val)          \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_MISC_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO_STATUS_RING_MISC_LOOP_CNT_BMSK               0x03c00000
#define HWIO_REO_R0_REO_STATUS_RING_MISC_LOOP_CNT_SHFT                     0x16

#define HWIO_REO_R0_REO_STATUS_RING_MISC_SPARE_CONTROL_BMSK          0x003fc000
#define HWIO_REO_R0_REO_STATUS_RING_MISC_SPARE_CONTROL_SHFT                 0xe

#define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK         0x00003000
#define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT                0xc

#define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK         0x00000f00
#define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT                0x8

#define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK           0x00000080
#define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT                  0x7

#define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_ENABLE_BMSK            0x00000040
#define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_ENABLE_SHFT                   0x6

#define HWIO_REO_R0_REO_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK      0x00000020
#define HWIO_REO_R0_REO_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT             0x5

#define HWIO_REO_R0_REO_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK       0x00000010
#define HWIO_REO_R0_REO_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT              0x4

#define HWIO_REO_R0_REO_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK           0x00000008
#define HWIO_REO_R0_REO_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT                  0x3

#define HWIO_REO_R0_REO_STATUS_RING_MISC_SECURITY_BIT_BMSK           0x00000004
#define HWIO_REO_R0_REO_STATUS_RING_MISC_SECURITY_BIT_SHFT                  0x2

#define HWIO_REO_R0_REO_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK        0x00000002
#define HWIO_REO_R0_REO_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT               0x1

#define HWIO_REO_R0_REO_STATUS_RING_MISC_RING_ID_DISABLE_BMSK        0x00000001
#define HWIO_REO_R0_REO_STATUS_RING_MISC_RING_ID_DISABLE_SHFT               0x0

//// Register REO_R0_REO_STATUS_RING_HP_ADDR_LSB ////

#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x)              (x+0x00000518)
#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_PHYS(x)              (x+0x00000518)
#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_RMSK                 0xffffffff
#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_SHFT                          0
#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_IN(x)                \
	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_RMSK)
#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_INM(x, mask)         \
	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_OUT(x, val)          \
	out_dword( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), val)
#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_OUTM(x, mask, val)   \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT        0x0

//// Register REO_R0_REO_STATUS_RING_HP_ADDR_MSB ////

#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x)              (x+0x0000051c)
#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_PHYS(x)              (x+0x0000051c)
#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_RMSK                 0x000000ff
#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_SHFT                          0
#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_IN(x)                \
	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_RMSK)
#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_INM(x, mask)         \
	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_OUT(x, val)          \
	out_dword( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), val)
#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_OUTM(x, mask, val)   \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT        0x0

//// Register REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP ////

#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x)       (x+0x00000528)
#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x)       (x+0x00000528)
#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_RMSK          0xffffffff
#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_SHFT                   0
#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_IN(x)         \
	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_RMSK)
#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_INM(x, mask)  \
	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 
#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, val)   \
	out_dword( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), val)
#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10

#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT        0xf

#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT        0x0

//// Register REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS ////

#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x)      (x+0x0000052c)
#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x)      (x+0x0000052c)
#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_RMSK         0xffffffff
#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_SHFT                  0
#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_IN(x)        \
	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_RMSK)
#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_INM(x, mask) \
	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 
#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_OUT(x, val)  \
	out_dword( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), val)
#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10

#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT        0xf

#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0

//// Register REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER ////

#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x)    (x+0x00000530)
#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x)    (x+0x00000530)
#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK       0x000003ff
#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_SHFT                0
#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)      \
	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK)
#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 
#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
	out_dword( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff
#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT        0x0

//// Register REO_R0_REO_STATUS_RING_MSI1_BASE_LSB ////

#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x)            (x+0x0000054c)
#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_PHYS(x)            (x+0x0000054c)
#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_RMSK               0xffffffff
#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_SHFT                        0
#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_IN(x)              \
	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_RMSK)
#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_INM(x, mask)       \
	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_OUT(x, val)        \
	out_dword( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), val)
#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK          0xffffffff
#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT                 0x0

//// Register REO_R0_REO_STATUS_RING_MSI1_BASE_MSB ////

#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x)            (x+0x00000550)
#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_PHYS(x)            (x+0x00000550)
#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_RMSK               0x000001ff
#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_SHFT                        0
#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_IN(x)              \
	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_RMSK)
#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_INM(x, mask)       \
	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), mask) 
#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_OUT(x, val)        \
	out_dword( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), val)
#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK   0x00000100
#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT          0x8

#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK          0x000000ff
#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT                 0x0

//// Register REO_R0_REO_STATUS_RING_MSI1_DATA ////

#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x)                (x+0x00000554)
#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_PHYS(x)                (x+0x00000554)
#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_RMSK                   0xffffffff
#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_SHFT                            0
#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_IN(x)                  \
	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_RMSK)
#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_INM(x, mask)           \
	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), mask) 
#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_OUT(x, val)            \
	out_dword( HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), val)
#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_OUTM(x, mask, val)     \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_VALUE_BMSK             0xffffffff
#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_VALUE_SHFT                    0x0

//// Register REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET ////

#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x)          (x+0x00000558)
#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x)          (x+0x00000558)
#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_RMSK             0x0000ffff
#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_SHFT                      0
#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_IN(x)            \
	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_RMSK)
#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_INM(x, mask)     \
	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, val)      \
	out_dword( HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), val)
#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0

//// Register REO_R0_WATCHDOG_TIMEOUT ////

#define HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x)                         (x+0x0000055c)
#define HWIO_REO_R0_WATCHDOG_TIMEOUT_PHYS(x)                         (x+0x0000055c)
#define HWIO_REO_R0_WATCHDOG_TIMEOUT_RMSK                            0x00003fff
#define HWIO_REO_R0_WATCHDOG_TIMEOUT_SHFT                                     0
#define HWIO_REO_R0_WATCHDOG_TIMEOUT_IN(x)                           \
	in_dword_masked ( HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), HWIO_REO_R0_WATCHDOG_TIMEOUT_RMSK)
#define HWIO_REO_R0_WATCHDOG_TIMEOUT_INM(x, mask)                    \
	in_dword_masked ( HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), mask) 
#define HWIO_REO_R0_WATCHDOG_TIMEOUT_OUT(x, val)                     \
	out_dword( HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), val)
#define HWIO_REO_R0_WATCHDOG_TIMEOUT_OUTM(x, mask, val)              \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), mask, val, HWIO_REO_R0_WATCHDOG_TIMEOUT_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_WATCHDOG_TIMEOUT_RESOLUTION_UNITS_BMSK           0x00003000
#define HWIO_REO_R0_WATCHDOG_TIMEOUT_RESOLUTION_UNITS_SHFT                  0xc

#define HWIO_REO_R0_WATCHDOG_TIMEOUT_SRNG_TIMEOUT_BMSK               0x00000fff
#define HWIO_REO_R0_WATCHDOG_TIMEOUT_SRNG_TIMEOUT_SHFT                      0x0

//// Register REO_R0_INTERRUPT_DATA_CAPTURE_IX_0 ////

#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x)              (x+0x00000560)
#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_PHYS(x)              (x+0x00000560)
#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_RMSK                 0xffffffff
#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_SHFT                          0
#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_IN(x)                \
	in_dword_masked ( HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_RMSK)
#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_INM(x, mask)         \
	in_dword_masked ( HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), mask) 
#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_OUT(x, val)          \
	out_dword( HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), val)
#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_OUTM(x, mask, val)   \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), mask, val, HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ERROR_DATA_BMSK      0xffffffff
#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ERROR_DATA_SHFT             0x0

//// Register REO_R0_AGING_THRESHOLD_IX_0 ////

#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x)                     (x+0x00000564)
#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_PHYS(x)                     (x+0x00000564)
#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_RMSK                        0xffffffff
#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_SHFT                                 0
#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_IN(x)                       \
	in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), HWIO_REO_R0_AGING_THRESHOLD_IX_0_RMSK)
#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_INM(x, mask)                \
	in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), mask) 
#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_OUT(x, val)                 \
	out_dword( HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), val)
#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_OUTM(x, mask, val)          \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_THRESHOLD_IX_0_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_AGING_THRESHOLD_AC0_BMSK    0xffffffff
#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_AGING_THRESHOLD_AC0_SHFT           0x0

//// Register REO_R0_AGING_THRESHOLD_IX_1 ////

#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x)                     (x+0x00000568)
#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_PHYS(x)                     (x+0x00000568)
#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_RMSK                        0xffffffff
#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_SHFT                                 0
#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_IN(x)                       \
	in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), HWIO_REO_R0_AGING_THRESHOLD_IX_1_RMSK)
#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_INM(x, mask)                \
	in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), mask) 
#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_OUT(x, val)                 \
	out_dword( HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), val)
#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_OUTM(x, mask, val)          \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_THRESHOLD_IX_1_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_AGING_THRESHOLD_AC1_BMSK    0xffffffff
#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_AGING_THRESHOLD_AC1_SHFT           0x0

//// Register REO_R0_AGING_THRESHOLD_IX_2 ////

#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x)                     (x+0x0000056c)
#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_PHYS(x)                     (x+0x0000056c)
#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_RMSK                        0xffffffff
#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_SHFT                                 0
#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_IN(x)                       \
	in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), HWIO_REO_R0_AGING_THRESHOLD_IX_2_RMSK)
#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_INM(x, mask)                \
	in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), mask) 
#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_OUT(x, val)                 \
	out_dword( HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), val)
#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_OUTM(x, mask, val)          \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_THRESHOLD_IX_2_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_AGING_THRESHOLD_AC2_BMSK    0xffffffff
#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_AGING_THRESHOLD_AC2_SHFT           0x0

//// Register REO_R0_AGING_THRESHOLD_IX_3 ////

#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x)                     (x+0x00000570)
#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_PHYS(x)                     (x+0x00000570)
#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_RMSK                        0xffffffff
#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_SHFT                                 0
#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_IN(x)                       \
	in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), HWIO_REO_R0_AGING_THRESHOLD_IX_3_RMSK)
#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_INM(x, mask)                \
	in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), mask) 
#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_OUT(x, val)                 \
	out_dword( HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), val)
#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_OUTM(x, mask, val)          \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_THRESHOLD_IX_3_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_AGING_THRESHOLD_AC3_BMSK    0xffffffff
#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_AGING_THRESHOLD_AC3_SHFT           0x0

//// Register REO_R0_AGING_LINK_HEADPTR_LO_IX_0 ////

#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x)               (x+0x00000574)
#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_PHYS(x)               (x+0x00000574)
#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_RMSK                  0xffffffff
#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_SHFT                           0
#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_IN(x)                 \
	in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_RMSK)
#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_INM(x, mask)          \
	in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), mask) 
#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_OUT(x, val)           \
	out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), val)
#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_OUTM(x, mask, val)    \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff
#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_AGING_HEADPTR_LO_BITS_SHFT        0x0

//// Register REO_R0_AGING_LINK_HEADPTR_HI_IX_0 ////

#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x)               (x+0x00000578)
#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_PHYS(x)               (x+0x00000578)
#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_RMSK                  0x000000ff
#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_SHFT                           0
#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_IN(x)                 \
	in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_RMSK)
#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_INM(x, mask)          \
	in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), mask) 
#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_OUT(x, val)           \
	out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), val)
#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_OUTM(x, mask, val)    \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_AGING_HEADPTR_HI_BITS_BMSK 0x000000ff
#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_AGING_HEADPTR_HI_BITS_SHFT        0x0

//// Register REO_R0_AGING_LINK_TAILPTR_LO_IX_0 ////

#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x)               (x+0x0000057c)
#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_PHYS(x)               (x+0x0000057c)
#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_RMSK                  0xffffffff
#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_SHFT                           0
#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_IN(x)                 \
	in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_RMSK)
#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_INM(x, mask)          \
	in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), mask) 
#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_OUT(x, val)           \
	out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), val)
#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_OUTM(x, mask, val)    \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff
#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_AGING_TAILPTR_LO_BITS_SHFT        0x0

//// Register REO_R0_AGING_LINK_TAILPTR_HI_IX_0 ////

#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x)               (x+0x00000580)
#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_PHYS(x)               (x+0x00000580)
#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_RMSK                  0x000000ff
#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_SHFT                           0
#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_IN(x)                 \
	in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_RMSK)
#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_INM(x, mask)          \
	in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), mask) 
#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_OUT(x, val)           \
	out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), val)
#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_OUTM(x, mask, val)    \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_AGING_TAILPTR_HI_BITS_BMSK 0x000000ff
#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_AGING_TAILPTR_HI_BITS_SHFT        0x0

//// Register REO_R0_AGING_LINK_HEADPTR_LO_IX_1 ////

#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x)               (x+0x00000584)
#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_PHYS(x)               (x+0x00000584)
#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_RMSK                  0xffffffff
#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_SHFT                           0
#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_IN(x)                 \
	in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_RMSK)
#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_INM(x, mask)          \
	in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), mask) 
#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_OUT(x, val)           \
	out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), val)
#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_OUTM(x, mask, val)    \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff
#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_AGING_HEADPTR_LO_BITS_SHFT        0x0

//// Register REO_R0_AGING_LINK_HEADPTR_HI_IX_1 ////

#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x)               (x+0x00000588)
#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_PHYS(x)               (x+0x00000588)
#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_RMSK                  0x000000ff
#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_SHFT                           0
#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_IN(x)                 \
	in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_RMSK)
#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_INM(x, mask)          \
	in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), mask) 
#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_OUT(x, val)           \
	out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), val)
#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_OUTM(x, mask, val)    \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_AGING_HEADPTR_HI_BITS_BMSK 0x000000ff
#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_AGING_HEADPTR_HI_BITS_SHFT        0x0

//// Register REO_R0_AGING_LINK_TAILPTR_LO_IX_1 ////

#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x)               (x+0x0000058c)
#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_PHYS(x)               (x+0x0000058c)
#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_RMSK                  0xffffffff
#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_SHFT                           0
#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_IN(x)                 \
	in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_RMSK)
#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_INM(x, mask)          \
	in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), mask) 
#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_OUT(x, val)           \
	out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), val)
#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_OUTM(x, mask, val)    \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff
#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_AGING_TAILPTR_LO_BITS_SHFT        0x0

//// Register REO_R0_AGING_LINK_TAILPTR_HI_IX_1 ////

#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x)               (x+0x00000590)
#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_PHYS(x)               (x+0x00000590)
#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_RMSK                  0x000000ff
#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_SHFT                           0
#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_IN(x)                 \
	in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_RMSK)
#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_INM(x, mask)          \
	in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), mask) 
#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_OUT(x, val)           \
	out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), val)
#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_OUTM(x, mask, val)    \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_AGING_TAILPTR_HI_BITS_BMSK 0x000000ff
#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_AGING_TAILPTR_HI_BITS_SHFT        0x0

//// Register REO_R0_AGING_LINK_HEADPTR_LO_IX_2 ////

#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x)               (x+0x00000594)
#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_PHYS(x)               (x+0x00000594)
#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_RMSK                  0xffffffff
#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_SHFT                           0
#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_IN(x)                 \
	in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_RMSK)
#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_INM(x, mask)          \
	in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), mask) 
#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_OUT(x, val)           \
	out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), val)
#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_OUTM(x, mask, val)    \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff
#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_AGING_HEADPTR_LO_BITS_SHFT        0x0

//// Register REO_R0_AGING_LINK_HEADPTR_HI_IX_2 ////

#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x)               (x+0x00000598)
#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_PHYS(x)               (x+0x00000598)
#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_RMSK                  0x000000ff
#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_SHFT                           0
#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_IN(x)                 \
	in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_RMSK)
#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_INM(x, mask)          \
	in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), mask) 
#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_OUT(x, val)           \
	out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), val)
#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_OUTM(x, mask, val)    \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_AGING_HEADPTR_HI_BITS_BMSK 0x000000ff
#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_AGING_HEADPTR_HI_BITS_SHFT        0x0

//// Register REO_R0_AGING_LINK_TAILPTR_LO_IX_2 ////

#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x)               (x+0x0000059c)
#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_PHYS(x)               (x+0x0000059c)
#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_RMSK                  0xffffffff
#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_SHFT                           0
#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_IN(x)                 \
	in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_RMSK)
#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_INM(x, mask)          \
	in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), mask) 
#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_OUT(x, val)           \
	out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), val)
#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_OUTM(x, mask, val)    \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff
#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_AGING_TAILPTR_LO_BITS_SHFT        0x0

//// Register REO_R0_AGING_LINK_TAILPTR_HI_IX_2 ////

#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x)               (x+0x000005a0)
#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_PHYS(x)               (x+0x000005a0)
#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_RMSK                  0x000000ff
#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_SHFT                           0
#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_IN(x)                 \
	in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_RMSK)
#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_INM(x, mask)          \
	in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), mask) 
#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_OUT(x, val)           \
	out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), val)
#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_OUTM(x, mask, val)    \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_AGING_TAILPTR_HI_BITS_BMSK 0x000000ff
#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_AGING_TAILPTR_HI_BITS_SHFT        0x0

//// Register REO_R0_AGING_LINK_HEADPTR_LO_IX_3 ////

#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x)               (x+0x000005a4)
#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_PHYS(x)               (x+0x000005a4)
#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_RMSK                  0xffffffff
#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_SHFT                           0
#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_IN(x)                 \
	in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_RMSK)
#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_INM(x, mask)          \
	in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), mask) 
#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_OUT(x, val)           \
	out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), val)
#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_OUTM(x, mask, val)    \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff
#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_AGING_HEADPTR_LO_BITS_SHFT        0x0

//// Register REO_R0_AGING_LINK_HEADPTR_HI_IX_3 ////

#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x)               (x+0x000005a8)
#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_PHYS(x)               (x+0x000005a8)
#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_RMSK                  0x000000ff
#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_SHFT                           0
#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_IN(x)                 \
	in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_RMSK)
#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_INM(x, mask)          \
	in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), mask) 
#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_OUT(x, val)           \
	out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), val)
#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_OUTM(x, mask, val)    \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_AGING_HEADPTR_HI_BITS_BMSK 0x000000ff
#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_AGING_HEADPTR_HI_BITS_SHFT        0x0

//// Register REO_R0_AGING_LINK_TAILPTR_LO_IX_3 ////

#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x)               (x+0x000005ac)
#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_PHYS(x)               (x+0x000005ac)
#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_RMSK                  0xffffffff
#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_SHFT                           0
#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_IN(x)                 \
	in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_RMSK)
#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_INM(x, mask)          \
	in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), mask) 
#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_OUT(x, val)           \
	out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), val)
#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_OUTM(x, mask, val)    \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff
#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_AGING_TAILPTR_LO_BITS_SHFT        0x0

//// Register REO_R0_AGING_LINK_TAILPTR_HI_IX_3 ////

#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x)               (x+0x000005b0)
#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_PHYS(x)               (x+0x000005b0)
#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_RMSK                  0x000000ff
#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_SHFT                           0
#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_IN(x)                 \
	in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_RMSK)
#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_INM(x, mask)          \
	in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), mask) 
#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_OUT(x, val)           \
	out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), val)
#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_OUTM(x, mask, val)    \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_AGING_TAILPTR_HI_BITS_BMSK 0x000000ff
#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_AGING_TAILPTR_HI_BITS_SHFT        0x0

//// Register REO_R0_AGING_NUM_QUEUES_IX_0 ////

#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x)                    (x+0x000005b4)
#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_PHYS(x)                    (x+0x000005b4)
#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_RMSK                       0x0000ffff
#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_SHFT                                0
#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_IN(x)                      \
	in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_RMSK)
#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_INM(x, mask)               \
	in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), mask) 
#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_OUT(x, val)                \
	out_dword( HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), val)
#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_OUTM(x, mask, val)         \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_AGING_NUM_QUEUES_AC0_BMSK  0x0000ffff
#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_AGING_NUM_QUEUES_AC0_SHFT         0x0

//// Register REO_R0_AGING_NUM_QUEUES_IX_1 ////

#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x)                    (x+0x000005b8)
#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_PHYS(x)                    (x+0x000005b8)
#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_RMSK                       0x0000ffff
#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_SHFT                                0
#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_IN(x)                      \
	in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_RMSK)
#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_INM(x, mask)               \
	in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), mask) 
#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_OUT(x, val)                \
	out_dword( HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), val)
#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_OUTM(x, mask, val)         \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_AGING_NUM_QUEUES_AC1_BMSK  0x0000ffff
#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_AGING_NUM_QUEUES_AC1_SHFT         0x0

//// Register REO_R0_AGING_NUM_QUEUES_IX_2 ////

#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x)                    (x+0x000005bc)
#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_PHYS(x)                    (x+0x000005bc)
#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_RMSK                       0x0000ffff
#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_SHFT                                0
#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_IN(x)                      \
	in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_RMSK)
#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_INM(x, mask)               \
	in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), mask) 
#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_OUT(x, val)                \
	out_dword( HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), val)
#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_OUTM(x, mask, val)         \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_AGING_NUM_QUEUES_AC2_BMSK  0x0000ffff
#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_AGING_NUM_QUEUES_AC2_SHFT         0x0

//// Register REO_R0_AGING_NUM_QUEUES_IX_3 ////

#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x)                    (x+0x000005c0)
#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_PHYS(x)                    (x+0x000005c0)
#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_RMSK                       0x0000ffff
#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_SHFT                                0
#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_IN(x)                      \
	in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_RMSK)
#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_INM(x, mask)               \
	in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), mask) 
#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_OUT(x, val)                \
	out_dword( HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), val)
#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_OUTM(x, mask, val)         \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_AGING_NUM_QUEUES_AC3_BMSK  0x0000ffff
#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_AGING_NUM_QUEUES_AC3_SHFT         0x0

//// Register REO_R0_AGING_TIMESTAMP_IX_0 ////

#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x)                     (x+0x000005c4)
#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_PHYS(x)                     (x+0x000005c4)
#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_RMSK                        0xffffffff
#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_SHFT                                 0
#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_IN(x)                       \
	in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), HWIO_REO_R0_AGING_TIMESTAMP_IX_0_RMSK)
#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_INM(x, mask)                \
	in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), mask) 
#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_OUT(x, val)                 \
	out_dword( HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), val)
#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_OUTM(x, mask, val)          \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_TIMESTAMP_IX_0_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_AGING_TIMESTAMP_AC0_BMSK    0xffffffff
#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_AGING_TIMESTAMP_AC0_SHFT           0x0

//// Register REO_R0_AGING_TIMESTAMP_IX_1 ////

#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x)                     (x+0x000005c8)
#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_PHYS(x)                     (x+0x000005c8)
#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_RMSK                        0xffffffff
#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_SHFT                                 0
#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_IN(x)                       \
	in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), HWIO_REO_R0_AGING_TIMESTAMP_IX_1_RMSK)
#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_INM(x, mask)                \
	in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), mask) 
#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_OUT(x, val)                 \
	out_dword( HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), val)
#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_OUTM(x, mask, val)          \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_TIMESTAMP_IX_1_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_AGING_TIMESTAMP_AC1_BMSK    0xffffffff
#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_AGING_TIMESTAMP_AC1_SHFT           0x0

//// Register REO_R0_AGING_TIMESTAMP_IX_2 ////

#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x)                     (x+0x000005cc)
#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_PHYS(x)                     (x+0x000005cc)
#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_RMSK                        0xffffffff
#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_SHFT                                 0
#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_IN(x)                       \
	in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), HWIO_REO_R0_AGING_TIMESTAMP_IX_2_RMSK)
#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_INM(x, mask)                \
	in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), mask) 
#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_OUT(x, val)                 \
	out_dword( HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), val)
#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_OUTM(x, mask, val)          \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_TIMESTAMP_IX_2_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_AGING_TIMESTAMP_AC2_BMSK    0xffffffff
#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_AGING_TIMESTAMP_AC2_SHFT           0x0

//// Register REO_R0_AGING_TIMESTAMP_IX_3 ////

#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x)                     (x+0x000005d0)
#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_PHYS(x)                     (x+0x000005d0)
#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_RMSK                        0xffffffff
#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_SHFT                                 0
#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_IN(x)                       \
	in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), HWIO_REO_R0_AGING_TIMESTAMP_IX_3_RMSK)
#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_INM(x, mask)                \
	in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), mask) 
#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_OUT(x, val)                 \
	out_dword( HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), val)
#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_OUTM(x, mask, val)          \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_TIMESTAMP_IX_3_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_AGING_TIMESTAMP_AC3_BMSK    0xffffffff
#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_AGING_TIMESTAMP_AC3_SHFT           0x0

//// Register REO_R0_AGING_CONTROL ////

#define HWIO_REO_R0_AGING_CONTROL_ADDR(x)                            (x+0x000005d4)
#define HWIO_REO_R0_AGING_CONTROL_PHYS(x)                            (x+0x000005d4)
#define HWIO_REO_R0_AGING_CONTROL_RMSK                               0x0000001f
#define HWIO_REO_R0_AGING_CONTROL_SHFT                                        0
#define HWIO_REO_R0_AGING_CONTROL_IN(x)                              \
	in_dword_masked ( HWIO_REO_R0_AGING_CONTROL_ADDR(x), HWIO_REO_R0_AGING_CONTROL_RMSK)
#define HWIO_REO_R0_AGING_CONTROL_INM(x, mask)                       \
	in_dword_masked ( HWIO_REO_R0_AGING_CONTROL_ADDR(x), mask) 
#define HWIO_REO_R0_AGING_CONTROL_OUT(x, val)                        \
	out_dword( HWIO_REO_R0_AGING_CONTROL_ADDR(x), val)
#define HWIO_REO_R0_AGING_CONTROL_OUTM(x, mask, val)                 \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_AGING_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_AGING_CONTROL_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_AGING_CONTROL_PERMPDU_UPDATE_THRESHOLD_BMSK      0x0000001f
#define HWIO_REO_R0_AGING_CONTROL_PERMPDU_UPDATE_THRESHOLD_SHFT             0x0

//// Register REO_R0_MISC_CTL ////

#define HWIO_REO_R0_MISC_CTL_ADDR(x)                                 (x+0x000005d8)
#define HWIO_REO_R0_MISC_CTL_PHYS(x)                                 (x+0x000005d8)
#define HWIO_REO_R0_MISC_CTL_RMSK                                    0x000fffff
#define HWIO_REO_R0_MISC_CTL_SHFT                                             0
#define HWIO_REO_R0_MISC_CTL_IN(x)                                   \
	in_dword_masked ( HWIO_REO_R0_MISC_CTL_ADDR(x), HWIO_REO_R0_MISC_CTL_RMSK)
#define HWIO_REO_R0_MISC_CTL_INM(x, mask)                            \
	in_dword_masked ( HWIO_REO_R0_MISC_CTL_ADDR(x), mask) 
#define HWIO_REO_R0_MISC_CTL_OUT(x, val)                             \
	out_dword( HWIO_REO_R0_MISC_CTL_ADDR(x), val)
#define HWIO_REO_R0_MISC_CTL_OUTM(x, mask, val)                      \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_MISC_CTL_ADDR(x), mask, val, HWIO_REO_R0_MISC_CTL_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_BMSK                 0x000e0000
#define HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_SHFT                       0x11

#define HWIO_REO_R0_MISC_CTL_CACHE_FLUSH_Q_DESC_ONLY_BMSK            0x00010000
#define HWIO_REO_R0_MISC_CTL_CACHE_FLUSH_Q_DESC_ONLY_SHFT                  0x10

#define HWIO_REO_R0_MISC_CTL_MSI_ENABLE_CHK_BIT_BMSK                 0x00008000
#define HWIO_REO_R0_MISC_CTL_MSI_ENABLE_CHK_BIT_SHFT                        0xf

#define HWIO_REO_R0_MISC_CTL_SPARE_CONTROL_BMSK                      0x00007fff
#define HWIO_REO_R0_MISC_CTL_SPARE_CONTROL_SHFT                             0x0

//// Register REO_R0_HIGH_MEMORY_THRESHOLD ////

#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x)                    (x+0x000005dc)
#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_PHYS(x)                    (x+0x000005dc)
#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_RMSK                       0xffffffff
#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_SHFT                                0
#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_IN(x)                      \
	in_dword_masked ( HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_RMSK)
#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_INM(x, mask)               \
	in_dword_masked ( HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), mask) 
#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_OUT(x, val)                \
	out_dword( HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), val)
#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_OUTM(x, mask, val)         \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), mask, val, HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_HIGH_MEMORY_THRESHOLD_BMSK 0xffffffff
#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_HIGH_MEMORY_THRESHOLD_SHFT        0x0

//// Register REO_R0_AC_BUFFERS_USED_IX_0 ////

#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x)                     (x+0x000005e0)
#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_PHYS(x)                     (x+0x000005e0)
#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_RMSK                        0xffffffff
#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_SHFT                                 0
#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_IN(x)                       \
	in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), HWIO_REO_R0_AC_BUFFERS_USED_IX_0_RMSK)
#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_INM(x, mask)                \
	in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), mask) 
#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_OUT(x, val)                 \
	out_dword( HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), val)
#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_OUTM(x, mask, val)          \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AC_BUFFERS_USED_IX_0_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_BUFFERS_USED_BMSK           0xffffffff
#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_BUFFERS_USED_SHFT                  0x0

//// Register REO_R0_AC_BUFFERS_USED_IX_1 ////

#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x)                     (x+0x000005e4)
#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_PHYS(x)                     (x+0x000005e4)
#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_RMSK                        0xffffffff
#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_SHFT                                 0
#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_IN(x)                       \
	in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), HWIO_REO_R0_AC_BUFFERS_USED_IX_1_RMSK)
#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_INM(x, mask)                \
	in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), mask) 
#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_OUT(x, val)                 \
	out_dword( HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), val)
#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_OUTM(x, mask, val)          \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AC_BUFFERS_USED_IX_1_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_BUFFERS_USED_BMSK           0xffffffff
#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_BUFFERS_USED_SHFT                  0x0

//// Register REO_R0_AC_BUFFERS_USED_IX_2 ////

#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x)                     (x+0x000005e8)
#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_PHYS(x)                     (x+0x000005e8)
#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_RMSK                        0xffffffff
#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_SHFT                                 0
#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_IN(x)                       \
	in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), HWIO_REO_R0_AC_BUFFERS_USED_IX_2_RMSK)
#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_INM(x, mask)                \
	in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), mask) 
#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_OUT(x, val)                 \
	out_dword( HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), val)
#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_OUTM(x, mask, val)          \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AC_BUFFERS_USED_IX_2_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_BUFFERS_USED_BMSK           0xffffffff
#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_BUFFERS_USED_SHFT                  0x0

//// Register REO_R0_AC_BUFFERS_USED_IX_3 ////

#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x)                     (x+0x000005ec)
#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_PHYS(x)                     (x+0x000005ec)
#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_RMSK                        0xffffffff
#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_SHFT                                 0
#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_IN(x)                       \
	in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), HWIO_REO_R0_AC_BUFFERS_USED_IX_3_RMSK)
#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_INM(x, mask)                \
	in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), mask) 
#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_OUT(x, val)                 \
	out_dword( HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), val)
#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_OUTM(x, mask, val)          \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AC_BUFFERS_USED_IX_3_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_BUFFERS_USED_BMSK           0xffffffff
#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_BUFFERS_USED_SHFT                  0x0

//// Register REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0 ////

#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x)       (x+0x000005f0)
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_PHYS(x)       (x+0x000005f0)
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_RMSK          0x00ffffff
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_SHFT                   0
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_IN(x)         \
	in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_RMSK)
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_INM(x, mask)  \
	in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), mask) 
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_OUT(x, val)   \
	out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), val)
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_THRESHOLD_BMSK 0x00ffffff
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_THRESHOLD_SHFT        0x0

//// Register REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1 ////

#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x)       (x+0x000005f4)
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_PHYS(x)       (x+0x000005f4)
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_RMSK          0x00ffffff
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_SHFT                   0
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_IN(x)         \
	in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_RMSK)
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_INM(x, mask)  \
	in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), mask) 
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_OUT(x, val)   \
	out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), val)
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_THRESHOLD_BMSK 0x00ffffff
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_THRESHOLD_SHFT        0x0

//// Register REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2 ////

#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x)       (x+0x000005f8)
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_PHYS(x)       (x+0x000005f8)
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_RMSK          0x00ffffff
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_SHFT                   0
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_IN(x)         \
	in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_RMSK)
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_INM(x, mask)  \
	in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), mask) 
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_OUT(x, val)   \
	out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), val)
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_THRESHOLD_BMSK 0x00ffffff
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_THRESHOLD_SHFT        0x0

//// Register REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL ////

#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x)      (x+0x000005fc)
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_PHYS(x)      (x+0x000005fc)
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_RMSK         0x03ffffff
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_SHFT                  0
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_IN(x)        \
	in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_RMSK)
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_INM(x, mask) \
	in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), mask) 
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_OUT(x, val)  \
	out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), val)
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_THRESHOLD_BMSK 0x03ffffff
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_THRESHOLD_SHFT        0x0

//// Register REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0 ////

#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x)              (x+0x00000600)
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_PHYS(x)              (x+0x00000600)
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_RMSK                 0x00ffffff
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_SHFT                          0
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_IN(x)                \
	in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_RMSK)
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_INM(x, mask)         \
	in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), mask) 
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_OUT(x, val)          \
	out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), val)
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_OUTM(x, mask, val)   \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_COUNT_BMSK           0x00ffffff
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_COUNT_SHFT                  0x0

//// Register REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1 ////

#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x)              (x+0x00000604)
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_PHYS(x)              (x+0x00000604)
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_RMSK                 0x00ffffff
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_SHFT                          0
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_IN(x)                \
	in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_RMSK)
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_INM(x, mask)         \
	in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), mask) 
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_OUT(x, val)          \
	out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), val)
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_OUTM(x, mask, val)   \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_COUNT_BMSK           0x00ffffff
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_COUNT_SHFT                  0x0

//// Register REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2 ////

#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x)              (x+0x00000608)
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_PHYS(x)              (x+0x00000608)
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_RMSK                 0x00ffffff
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_SHFT                          0
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_IN(x)                \
	in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_RMSK)
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_INM(x, mask)         \
	in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), mask) 
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_OUT(x, val)          \
	out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), val)
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_OUTM(x, mask, val)   \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_COUNT_BMSK           0x00ffffff
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_COUNT_SHFT                  0x0

//// Register REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL ////

#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x)              (x+0x0000060c)
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_PHYS(x)              (x+0x0000060c)
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_RMSK                 0x00000001
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_SHFT                          0
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_IN(x)                \
	in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_RMSK)
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_INM(x, mask)         \
	in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), mask) 
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_OUT(x, val)          \
	out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), val)
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_OUTM(x, mask, val)   \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ENABLE_DESC_THRESH_TLV_BMSK 0x00000001
#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ENABLE_DESC_THRESH_TLV_SHFT        0x0

//// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0 ////

#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x)            (x+0x00000610)
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_PHYS(x)            (x+0x00000610)
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_RMSK               0xffffffff
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_SHFT                        0
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_IN(x)              \
	in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_RMSK)
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_INM(x, mask)       \
	in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), mask) 
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_OUT(x, val)        \
	out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), val)
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDRESS_LO_BITS_BMSK 0xffffffff
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDRESS_LO_BITS_SHFT        0x0

//// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0 ////

#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x)            (x+0x00000614)
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_PHYS(x)            (x+0x00000614)
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_RMSK               0x000000ff
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_SHFT                        0
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_IN(x)              \
	in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_RMSK)
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_INM(x, mask)       \
	in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), mask) 
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_OUT(x, val)        \
	out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), val)
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDRESS_HI_BITS_BMSK 0x000000ff
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDRESS_HI_BITS_SHFT        0x0

//// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1 ////

#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x)            (x+0x00000618)
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_PHYS(x)            (x+0x00000618)
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_RMSK               0xffffffff
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_SHFT                        0
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_IN(x)              \
	in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_RMSK)
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_INM(x, mask)       \
	in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), mask) 
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_OUT(x, val)        \
	out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), val)
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDRESS_LO_BITS_BMSK 0xffffffff
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDRESS_LO_BITS_SHFT        0x0

//// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1 ////

#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x)            (x+0x0000061c)
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_PHYS(x)            (x+0x0000061c)
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_RMSK               0x000000ff
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_SHFT                        0
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_IN(x)              \
	in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_RMSK)
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_INM(x, mask)       \
	in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), mask) 
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_OUT(x, val)        \
	out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), val)
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDRESS_HI_BITS_BMSK 0x000000ff
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDRESS_HI_BITS_SHFT        0x0

//// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2 ////

#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x)            (x+0x00000620)
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_PHYS(x)            (x+0x00000620)
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_RMSK               0xffffffff
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_SHFT                        0
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_IN(x)              \
	in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_RMSK)
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_INM(x, mask)       \
	in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), mask) 
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_OUT(x, val)        \
	out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), val)
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDRESS_LO_BITS_BMSK 0xffffffff
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDRESS_LO_BITS_SHFT        0x0

//// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2 ////

#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x)            (x+0x00000624)
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_PHYS(x)            (x+0x00000624)
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_RMSK               0x000000ff
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_SHFT                        0
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_IN(x)              \
	in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_RMSK)
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_INM(x, mask)       \
	in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), mask) 
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_OUT(x, val)        \
	out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), val)
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDRESS_HI_BITS_BMSK 0x000000ff
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDRESS_HI_BITS_SHFT        0x0

//// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3 ////

#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x)            (x+0x00000628)
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_PHYS(x)            (x+0x00000628)
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_RMSK               0xffffffff
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_SHFT                        0
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_IN(x)              \
	in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_RMSK)
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_INM(x, mask)       \
	in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), mask) 
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_OUT(x, val)        \
	out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), val)
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDRESS_LO_BITS_BMSK 0xffffffff
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDRESS_LO_BITS_SHFT        0x0

//// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3 ////

#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x)            (x+0x0000062c)
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_PHYS(x)            (x+0x0000062c)
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_RMSK               0x000000ff
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_SHFT                        0
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_IN(x)              \
	in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_RMSK)
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_INM(x, mask)       \
	in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), mask) 
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_OUT(x, val)        \
	out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), val)
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDRESS_HI_BITS_BMSK 0x000000ff
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDRESS_HI_BITS_SHFT        0x0

//// Register REO_R0_QUEUE_DESC_BLOCK_INFO ////

#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x)                    (x+0x00000630)
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_PHYS(x)                    (x+0x00000630)
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_RMSK                       0x0000001f
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_SHFT                                0
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_IN(x)                      \
	in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_RMSK)
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_INM(x, mask)               \
	in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), mask) 
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_OUT(x, val)                \
	out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), val)
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_OUTM(x, mask, val)         \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ENTIRE_CACHE_BLOCKED_BMSK  0x00000010
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ENTIRE_CACHE_BLOCKED_SHFT         0x4

#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDRESS_VALID_BMSK         0x0000000f
#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDRESS_VALID_SHFT                0x0

//// Register REO_R0_GXI_TESTBUS_LOWER ////

#define HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x)                        (x+0x00000654)
#define HWIO_REO_R0_GXI_TESTBUS_LOWER_PHYS(x)                        (x+0x00000654)
#define HWIO_REO_R0_GXI_TESTBUS_LOWER_RMSK                           0xffffffff
#define HWIO_REO_R0_GXI_TESTBUS_LOWER_SHFT                                    0
#define HWIO_REO_R0_GXI_TESTBUS_LOWER_IN(x)                          \
	in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), HWIO_REO_R0_GXI_TESTBUS_LOWER_RMSK)
#define HWIO_REO_R0_GXI_TESTBUS_LOWER_INM(x, mask)                   \
	in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), mask) 
#define HWIO_REO_R0_GXI_TESTBUS_LOWER_OUT(x, val)                    \
	out_dword( HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), val)
#define HWIO_REO_R0_GXI_TESTBUS_LOWER_OUTM(x, mask, val)             \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_REO_R0_GXI_TESTBUS_LOWER_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_GXI_TESTBUS_LOWER_VALUE_BMSK                     0xffffffff
#define HWIO_REO_R0_GXI_TESTBUS_LOWER_VALUE_SHFT                            0x0

//// Register REO_R0_GXI_TESTBUS_UPPER ////

#define HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x)                        (x+0x00000658)
#define HWIO_REO_R0_GXI_TESTBUS_UPPER_PHYS(x)                        (x+0x00000658)
#define HWIO_REO_R0_GXI_TESTBUS_UPPER_RMSK                           0x000000ff
#define HWIO_REO_R0_GXI_TESTBUS_UPPER_SHFT                                    0
#define HWIO_REO_R0_GXI_TESTBUS_UPPER_IN(x)                          \
	in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), HWIO_REO_R0_GXI_TESTBUS_UPPER_RMSK)
#define HWIO_REO_R0_GXI_TESTBUS_UPPER_INM(x, mask)                   \
	in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), mask) 
#define HWIO_REO_R0_GXI_TESTBUS_UPPER_OUT(x, val)                    \
	out_dword( HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), val)
#define HWIO_REO_R0_GXI_TESTBUS_UPPER_OUTM(x, mask, val)             \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), mask, val, HWIO_REO_R0_GXI_TESTBUS_UPPER_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_GXI_TESTBUS_UPPER_VALUE_BMSK                     0x000000ff
#define HWIO_REO_R0_GXI_TESTBUS_UPPER_VALUE_SHFT                            0x0

//// Register REO_R0_GXI_SM_STATES_IX_0 ////

#define HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x)                       (x+0x0000065c)
#define HWIO_REO_R0_GXI_SM_STATES_IX_0_PHYS(x)                       (x+0x0000065c)
#define HWIO_REO_R0_GXI_SM_STATES_IX_0_RMSK                          0x00000fff
#define HWIO_REO_R0_GXI_SM_STATES_IX_0_SHFT                                   0
#define HWIO_REO_R0_GXI_SM_STATES_IX_0_IN(x)                         \
	in_dword_masked ( HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), HWIO_REO_R0_GXI_SM_STATES_IX_0_RMSK)
#define HWIO_REO_R0_GXI_SM_STATES_IX_0_INM(x, mask)                  \
	in_dword_masked ( HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), mask) 
#define HWIO_REO_R0_GXI_SM_STATES_IX_0_OUT(x, val)                   \
	out_dword( HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), val)
#define HWIO_REO_R0_GXI_SM_STATES_IX_0_OUTM(x, mask, val)            \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GXI_SM_STATES_IX_0_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_BMSK         0x00000e00
#define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_SHFT                0x9

#define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_BMSK         0x000001f0
#define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_SHFT                0x4

#define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_BMSK         0x0000000f
#define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_SHFT                0x0

//// Register REO_R0_GXI_END_OF_TEST_CHECK ////

#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x)                    (x+0x00000660)
#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_PHYS(x)                    (x+0x00000660)
#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_RMSK                       0x00000001
#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_SHFT                                0
#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_IN(x)                      \
	in_dword_masked ( HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), HWIO_REO_R0_GXI_END_OF_TEST_CHECK_RMSK)
#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_INM(x, mask)               \
	in_dword_masked ( HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask) 
#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_OUT(x, val)                \
	out_dword( HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), val)
#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_OUTM(x, mask, val)         \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_REO_R0_GXI_END_OF_TEST_CHECK_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001
#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT        0x0

//// Register REO_R0_GXI_CLOCK_GATE_DISABLE ////

#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x)                   (x+0x00000664)
#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_PHYS(x)                   (x+0x00000664)
#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RMSK                      0x80000fff
#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_SHFT                               0
#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_IN(x)                     \
	in_dword_masked ( HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RMSK)
#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_INM(x, mask)              \
	in_dword_masked ( HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask) 
#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_OUT(x, val)               \
	out_dword( HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), val)
#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_OUTM(x, mask, val)        \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask, val, HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK    0x80000000
#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT          0x1f

#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_SPARE_BMSK                0x00000800
#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_SPARE_SHFT                       0xb

#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WDOG_CTR_BMSK             0x00000400
#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WDOG_CTR_SHFT                    0xa

#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RD_FIFO_BMSK              0x00000200
#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RD_FIFO_SHFT                     0x9

#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_FIFO_BMSK         0x00000100
#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_FIFO_SHFT                0x8

#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_BMSK         0x00000080
#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_SHFT                0x7

#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RD_AXI_MAS_BMSK           0x00000040
#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RD_AXI_MAS_SHFT                  0x6

#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_BMSK      0x00000020
#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_SHFT             0x5

#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_BMSK      0x00000010
#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_SHFT             0x4

#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_CMD_BMSK          0x00000008
#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_CMD_SHFT                 0x3

#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_CMD_BMSK          0x00000004
#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_CMD_SHFT                 0x2

#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RD_CMD_BMSK               0x00000002
#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RD_CMD_SHFT                      0x1

#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_CORE_BMSK                 0x00000001
#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_CORE_SHFT                        0x0

//// Register REO_R0_GXI_GXI_ERR_INTS ////

#define HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x)                         (x+0x00000668)
#define HWIO_REO_R0_GXI_GXI_ERR_INTS_PHYS(x)                         (x+0x00000668)
#define HWIO_REO_R0_GXI_GXI_ERR_INTS_RMSK                            0x01010101
#define HWIO_REO_R0_GXI_GXI_ERR_INTS_SHFT                                     0
#define HWIO_REO_R0_GXI_GXI_ERR_INTS_IN(x)                           \
	in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), HWIO_REO_R0_GXI_GXI_ERR_INTS_RMSK)
#define HWIO_REO_R0_GXI_GXI_ERR_INTS_INM(x, mask)                    \
	in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), mask) 
#define HWIO_REO_R0_GXI_GXI_ERR_INTS_OUT(x, val)                     \
	out_dword( HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), val)
#define HWIO_REO_R0_GXI_GXI_ERR_INTS_OUTM(x, mask, val)              \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_ERR_INTS_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_BMSK        0x01000000
#define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_SHFT              0x18

#define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_BMSK         0x00010000
#define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_SHFT               0x10

#define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_BMSK         0x00000100
#define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_SHFT                0x8

#define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_BMSK          0x00000001
#define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_SHFT                 0x0

//// Register REO_R0_GXI_GXI_ERR_STATS ////

#define HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x)                        (x+0x0000066c)
#define HWIO_REO_R0_GXI_GXI_ERR_STATS_PHYS(x)                        (x+0x0000066c)
#define HWIO_REO_R0_GXI_GXI_ERR_STATS_RMSK                           0x003f3f3f
#define HWIO_REO_R0_GXI_GXI_ERR_STATS_SHFT                                    0
#define HWIO_REO_R0_GXI_GXI_ERR_STATS_IN(x)                          \
	in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), HWIO_REO_R0_GXI_GXI_ERR_STATS_RMSK)
#define HWIO_REO_R0_GXI_GXI_ERR_STATS_INM(x, mask)                   \
	in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), mask) 
#define HWIO_REO_R0_GXI_GXI_ERR_STATS_OUT(x, val)                    \
	out_dword( HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), val)
#define HWIO_REO_R0_GXI_GXI_ERR_STATS_OUTM(x, mask, val)             \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_ERR_STATS_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_BMSK      0x003f0000
#define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_SHFT            0x10

#define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_BMSK           0x00003f00
#define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_SHFT                  0x8

#define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_BMSK           0x0000003f
#define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_SHFT                  0x0

//// Register REO_R0_GXI_GXI_DEFAULT_CONTROL ////

#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x)                  (x+0x00000670)
#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_PHYS(x)                  (x+0x00000670)
#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_RMSK                     0xffff3f3f
#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_SHFT                              0
#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_IN(x)                    \
	in_dword_masked ( HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_RMSK)
#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_INM(x, mask)             \
	in_dword_masked ( HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask) 
#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_OUT(x, val)              \
	out_dword( HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), val)
#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_OUTM(x, mask, val)       \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_BMSK 0xff000000
#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_SHFT       0x18

#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000
#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_SHFT       0x10

#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_BMSK 0x00003f00
#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_SHFT        0x8

#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_BMSK 0x0000003f
#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_SHFT        0x0

//// Register REO_R0_GXI_GXI_REDUCED_CONTROL ////

#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x)                  (x+0x00000674)
#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_PHYS(x)                  (x+0x00000674)
#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_RMSK                     0xffff3f3f
#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_SHFT                              0
#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_IN(x)                    \
	in_dword_masked ( HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_RMSK)
#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_INM(x, mask)             \
	in_dword_masked ( HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask) 
#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_OUT(x, val)              \
	out_dword( HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), val)
#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_OUTM(x, mask, val)       \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_BMSK 0xff000000
#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_SHFT       0x18

#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000
#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_SHFT       0x10

#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_BMSK 0x00003f00
#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_SHFT        0x8

#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_BMSK 0x0000003f
#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_SHFT        0x0

//// Register REO_R0_GXI_GXI_MISC_CONTROL ////

#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x)                     (x+0x00000678)
#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_PHYS(x)                     (x+0x00000678)
#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_RMSK                        0x0fffffff
#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_SHFT                                 0
#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_IN(x)                       \
	in_dword_masked ( HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), HWIO_REO_R0_GXI_GXI_MISC_CONTROL_RMSK)
#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_INM(x, mask)                \
	in_dword_masked ( HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask) 
#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_OUT(x, val)                 \
	out_dword( HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), val)
#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_OUTM(x, mask, val)          \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_MISC_CONTROL_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_BMSK   0x08000000
#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_SHFT         0x1b

#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_BMSK   0x04000000
#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_SHFT         0x1a

#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_BMSK  0x02000000
#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_SHFT        0x19

#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_BMSK 0x01000000
#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_SHFT       0x18

#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_BMSK 0x00800000
#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_SHFT       0x17

#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_BMSK   0x00700000
#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_SHFT         0x14

#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_BMSK    0x000e0000
#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_SHFT          0x11

#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_BMSK 0x0001fe00
#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_SHFT        0x9

#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_BMSK 0x000001fe
#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_SHFT        0x1

#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_BMSK        0x00000001
#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_SHFT               0x0

//// Register REO_R0_GXI_GXI_WDOG_CONTROL ////

#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x)                     (x+0x0000067c)
#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_PHYS(x)                     (x+0x0000067c)
#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_RMSK                        0xffff0001
#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_SHFT                                 0
#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_IN(x)                       \
	in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_RMSK)
#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_INM(x, mask)                \
	in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask) 
#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_OUT(x, val)                 \
	out_dword( HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), val)
#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_OUTM(x, mask, val)          \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_BMSK         0xffff0000
#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_SHFT               0x10

#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_BMSK       0x00000001
#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_SHFT              0x0

//// Register REO_R0_GXI_GXI_WDOG_STATUS ////

#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x)                      (x+0x00000680)
#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_PHYS(x)                      (x+0x00000680)
#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_RMSK                         0x0000ffff
#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_SHFT                                  0
#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_IN(x)                        \
	in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), HWIO_REO_R0_GXI_GXI_WDOG_STATUS_RMSK)
#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_INM(x, mask)                 \
	in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask) 
#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_OUT(x, val)                  \
	out_dword( HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), val)
#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_OUTM(x, mask, val)           \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_WDOG_STATUS_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_BMSK         0x0000ffff
#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_SHFT                0x0

//// Register REO_R0_GXI_GXI_IDLE_COUNTERS ////

#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x)                    (x+0x00000684)
#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_PHYS(x)                    (x+0x00000684)
#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_RMSK                       0xffffffff
#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_SHFT                                0
#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_IN(x)                      \
	in_dword_masked ( HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_RMSK)
#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_INM(x, mask)               \
	in_dword_masked ( HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask) 
#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_OUT(x, val)                \
	out_dword( HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), val)
#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_OUTM(x, mask, val)         \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_BMSK     0xffff0000
#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_SHFT           0x10

#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_BMSK    0x0000ffff
#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_SHFT           0x0

//// Register REO_R0_GXI_GXI_RD_LATENCY_CTRL ////

#define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x)                  (x+0x00000688)
#define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_PHYS(x)                  (x+0x00000688)
#define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_RMSK                     0x000fffff
#define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_SHFT                              0
#define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_IN(x)                    \
	in_dword_masked ( HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_RMSK)
#define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_INM(x, mask)             \
	in_dword_masked ( HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), mask) 
#define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_OUT(x, val)              \
	out_dword( HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), val)
#define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_OUTM(x, mask, val)       \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK   0x000e0000
#define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT         0x11

#define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_BMSK      0x00010000
#define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_SHFT            0x10

#define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK     0x0000ffff
#define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT            0x0

//// Register REO_R0_GXI_GXI_WR_LATENCY_CTRL ////

#define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x)                  (x+0x0000068c)
#define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_PHYS(x)                  (x+0x0000068c)
#define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_RMSK                     0x000fffff
#define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_SHFT                              0
#define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_IN(x)                    \
	in_dword_masked ( HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_RMSK)
#define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_INM(x, mask)             \
	in_dword_masked ( HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), mask) 
#define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_OUT(x, val)              \
	out_dword( HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), val)
#define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_OUTM(x, mask, val)       \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK   0x000e0000
#define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT         0x11

#define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_BMSK      0x00010000
#define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_SHFT            0x10

#define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK     0x0000ffff
#define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT            0x0

//// Register REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0 ////

#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x)        (x+0x00000690)
#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_PHYS(x)        (x+0x00000690)
#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_RMSK           0xffffffff
#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_SHFT                    0
#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_IN(x)          \
	in_dword_masked ( HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_RMSK)
#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_INM(x, mask)   \
	in_dword_masked ( HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), mask) 
#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_OUT(x, val)    \
	out_dword( HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), val)
#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_BMSK     0xffffffff
#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_SHFT            0x0

//// Register REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1 ////

#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x)        (x+0x00000694)
#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_PHYS(x)        (x+0x00000694)
#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_RMSK           0xffffffff
#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_SHFT                    0
#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_IN(x)          \
	in_dword_masked ( HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_RMSK)
#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_INM(x, mask)   \
	in_dword_masked ( HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), mask) 
#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_OUT(x, val)    \
	out_dword( HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), val)
#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_BMSK     0xffffffff
#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_SHFT            0x0

//// Register REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0 ////

#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x)        (x+0x00000698)
#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_PHYS(x)        (x+0x00000698)
#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_RMSK           0xffffffff
#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_SHFT                    0
#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_IN(x)          \
	in_dword_masked ( HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_RMSK)
#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_INM(x, mask)   \
	in_dword_masked ( HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), mask) 
#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_OUT(x, val)    \
	out_dword( HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), val)
#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_BMSK     0xffffffff
#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_SHFT            0x0

//// Register REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1 ////

#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x)        (x+0x0000069c)
#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_PHYS(x)        (x+0x0000069c)
#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_RMSK           0xffffffff
#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_SHFT                    0
#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_IN(x)          \
	in_dword_masked ( HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_RMSK)
#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_INM(x, mask)   \
	in_dword_masked ( HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), mask) 
#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_OUT(x, val)    \
	out_dword( HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), val)
#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_BMSK     0xffffffff
#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_SHFT            0x0

//// Register REO_R0_GXI_GXI_AXI_OUTSANDING_CTL ////

#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x)               (x+0x000006a0)
#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_PHYS(x)               (x+0x000006a0)
#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_RMSK                  0x00009f9f
#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_SHFT                           0
#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_IN(x)                 \
	in_dword_masked ( HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_RMSK)
#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_INM(x, mask)          \
	in_dword_masked ( HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), mask) 
#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_OUT(x, val)           \
	out_dword( HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), val)
#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_OUTM(x, mask, val)    \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_EN_BMSK        0x00008000
#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_EN_SHFT               0xf

#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_CNT_BMSK       0x00001f00
#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_CNT_SHFT              0x8

#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_EN_BMSK        0x00000080
#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_EN_SHFT               0x7

#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_CNT_BMSK       0x0000001f
#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_CNT_SHFT              0x0

//// Register REO_R0_CACHE_CTL_CONFIG ////

#define HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x)                         (x+0x000006a4)
#define HWIO_REO_R0_CACHE_CTL_CONFIG_PHYS(x)                         (x+0x000006a4)
#define HWIO_REO_R0_CACHE_CTL_CONFIG_RMSK                            0xffffffff
#define HWIO_REO_R0_CACHE_CTL_CONFIG_SHFT                                     0
#define HWIO_REO_R0_CACHE_CTL_CONFIG_IN(x)                           \
	in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), HWIO_REO_R0_CACHE_CTL_CONFIG_RMSK)
#define HWIO_REO_R0_CACHE_CTL_CONFIG_INM(x, mask)                    \
	in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), mask) 
#define HWIO_REO_R0_CACHE_CTL_CONFIG_OUT(x, val)                     \
	out_dword( HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), val)
#define HWIO_REO_R0_CACHE_CTL_CONFIG_OUTM(x, mask, val)              \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), mask, val, HWIO_REO_R0_CACHE_CTL_CONFIG_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_CACHE_CTL_CONFIG_DESC_TYPE_SWAP_BMSK             0xff000000
#define HWIO_REO_R0_CACHE_CTL_CONFIG_DESC_TYPE_SWAP_SHFT                   0x18

#define HWIO_REO_R0_CACHE_CTL_CONFIG_ENABLE_LEGACY_SWAP_BMSK         0x00800000
#define HWIO_REO_R0_CACHE_CTL_CONFIG_ENABLE_LEGACY_SWAP_SHFT               0x17

#define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_STRUCT_SWAP_BMSK          0x00400000
#define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_STRUCT_SWAP_SHFT                0x16

#define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_STRUCT_SWAP_BMSK           0x00200000
#define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_STRUCT_SWAP_SHFT                 0x15

#define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_SECURITY_BMSK             0x00100000
#define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_SECURITY_SHFT                   0x14

#define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_SECURITY_BMSK              0x00080000
#define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_SECURITY_SHFT                    0x13

#define HWIO_REO_R0_CACHE_CTL_CONFIG_BG_FLUSH_POST_WRITE_BMSK        0x00040000
#define HWIO_REO_R0_CACHE_CTL_CONFIG_BG_FLUSH_POST_WRITE_SHFT              0x12

#define HWIO_REO_R0_CACHE_CTL_CONFIG_CLIENT_FLUSH_POST_WRITE_BMSK    0x00020000
#define HWIO_REO_R0_CACHE_CTL_CONFIG_CLIENT_FLUSH_POST_WRITE_SHFT          0x11

#define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_EMPTY_THRESHOLD_BMSK      0x0001fe00
#define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_EMPTY_THRESHOLD_SHFT             0x9

#define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_LINE_USE_NUM_BMSK         0x000001ff
#define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_LINE_USE_NUM_SHFT                0x0

//// Register REO_R0_CACHE_CTL_CONTROL ////

#define HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x)                        (x+0x000006a8)
#define HWIO_REO_R0_CACHE_CTL_CONTROL_PHYS(x)                        (x+0x000006a8)
#define HWIO_REO_R0_CACHE_CTL_CONTROL_RMSK                           0x00000003
#define HWIO_REO_R0_CACHE_CTL_CONTROL_SHFT                                    0
#define HWIO_REO_R0_CACHE_CTL_CONTROL_IN(x)                          \
	in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), HWIO_REO_R0_CACHE_CTL_CONTROL_RMSK)
#define HWIO_REO_R0_CACHE_CTL_CONTROL_INM(x, mask)                   \
	in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), mask) 
#define HWIO_REO_R0_CACHE_CTL_CONTROL_OUT(x, val)                    \
	out_dword( HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), val)
#define HWIO_REO_R0_CACHE_CTL_CONTROL_OUTM(x, mask, val)             \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_CACHE_CTL_CONTROL_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_CACHE_CTL_CONTROL_WRITE_POSTED_FOR_NON_POSTED_LINE_FLUSH_BMSK 0x00000002
#define HWIO_REO_R0_CACHE_CTL_CONTROL_WRITE_POSTED_FOR_NON_POSTED_LINE_FLUSH_SHFT        0x1

#define HWIO_REO_R0_CACHE_CTL_CONTROL_CACHE_RESET_BMSK               0x00000001
#define HWIO_REO_R0_CACHE_CTL_CONTROL_CACHE_RESET_SHFT                      0x0

//// Register REO_R0_CACHE_CTL_CONFIG_SET ////

#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ADDR(x)                     (x+0x000006ac)
#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_PHYS(x)                     (x+0x000006ac)
#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_RMSK                        0x01ffffff
#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_SHFT                                 0
#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_IN(x)                       \
	in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ADDR(x), HWIO_REO_R0_CACHE_CTL_CONFIG_SET_RMSK)
#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_INM(x, mask)                \
	in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ADDR(x), mask) 
#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_OUT(x, val)                 \
	out_dword( HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ADDR(x), val)
#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_OUTM(x, mask, val)          \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ADDR(x), mask, val, HWIO_REO_R0_CACHE_CTL_CONFIG_SET_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_CONFIG_SET_BMSK             0x01ffffff
#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_CONFIG_SET_SHFT                    0x0

//// Register REO_R0_CACHE_CTL_SET_SIZE ////

#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_ADDR(x)                       (x+0x000006b0)
#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_PHYS(x)                       (x+0x000006b0)
#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_RMSK                          0x000001ff
#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_SHFT                                   0
#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_IN(x)                         \
	in_dword_masked ( HWIO_REO_R0_CACHE_CTL_SET_SIZE_ADDR(x), HWIO_REO_R0_CACHE_CTL_SET_SIZE_RMSK)
#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_INM(x, mask)                  \
	in_dword_masked ( HWIO_REO_R0_CACHE_CTL_SET_SIZE_ADDR(x), mask) 
#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_OUT(x, val)                   \
	out_dword( HWIO_REO_R0_CACHE_CTL_SET_SIZE_ADDR(x), val)
#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_OUTM(x, mask, val)            \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_SET_SIZE_ADDR(x), mask, val, HWIO_REO_R0_CACHE_CTL_SET_SIZE_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_SET1_SIZE_BMSK                0x000001ff
#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_SET1_SIZE_SHFT                       0x0

//// Register REO_R0_CLK_GATE_CTRL ////

#define HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x)                            (x+0x000006b4)
#define HWIO_REO_R0_CLK_GATE_CTRL_PHYS(x)                            (x+0x000006b4)
#define HWIO_REO_R0_CLK_GATE_CTRL_RMSK                               0x0007ffff
#define HWIO_REO_R0_CLK_GATE_CTRL_SHFT                                        0
#define HWIO_REO_R0_CLK_GATE_CTRL_IN(x)                              \
	in_dword_masked ( HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), HWIO_REO_R0_CLK_GATE_CTRL_RMSK)
#define HWIO_REO_R0_CLK_GATE_CTRL_INM(x, mask)                       \
	in_dword_masked ( HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), mask) 
#define HWIO_REO_R0_CLK_GATE_CTRL_OUT(x, val)                        \
	out_dword( HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), val)
#define HWIO_REO_R0_CLK_GATE_CTRL_OUTM(x, mask, val)                 \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), mask, val, HWIO_REO_R0_CLK_GATE_CTRL_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_7_BMSK                     0x00040000
#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_7_SHFT                           0x12

#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_6_BMSK                     0x00020000
#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_6_SHFT                           0x11

#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_5_BMSK                     0x00010000
#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_5_SHFT                           0x10

#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_4_BMSK                     0x00008000
#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_4_SHFT                            0xf

#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_3_BMSK                     0x00004000
#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_3_SHFT                            0xe

#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_2_BMSK                     0x00002000
#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_2_SHFT                            0xd

#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SRNG_P_BMSK    0x00001000
#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SRNG_P_SHFT           0xc

#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SRNG_C_BMSK    0x00000800
#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SRNG_C_SHFT           0xb

#define HWIO_REO_R0_CLK_GATE_CTRL_CLOCK_ENS_EXTEND_BMSK              0x00000400
#define HWIO_REO_R0_CLK_GATE_CTRL_CLOCK_ENS_EXTEND_SHFT                     0xa

#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_BMSK           0x000003ff
#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SHFT                  0x0

//// Register REO_R0_EVENTMASK_IX_0 ////

#define HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x)                           (x+0x000006b8)
#define HWIO_REO_R0_EVENTMASK_IX_0_PHYS(x)                           (x+0x000006b8)
#define HWIO_REO_R0_EVENTMASK_IX_0_RMSK                              0xffffffff
#define HWIO_REO_R0_EVENTMASK_IX_0_SHFT                                       0
#define HWIO_REO_R0_EVENTMASK_IX_0_IN(x)                             \
	in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), HWIO_REO_R0_EVENTMASK_IX_0_RMSK)
#define HWIO_REO_R0_EVENTMASK_IX_0_INM(x, mask)                      \
	in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), mask) 
#define HWIO_REO_R0_EVENTMASK_IX_0_OUT(x, val)                       \
	out_dword( HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), val)
#define HWIO_REO_R0_EVENTMASK_IX_0_OUTM(x, mask, val)                \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), mask, val, HWIO_REO_R0_EVENTMASK_IX_0_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_EVENTMASK_IX_0_MASK_BMSK                         0xffffffff
#define HWIO_REO_R0_EVENTMASK_IX_0_MASK_SHFT                                0x0

//// Register REO_R0_EVENTMASK_IX_1 ////

#define HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x)                           (x+0x000006bc)
#define HWIO_REO_R0_EVENTMASK_IX_1_PHYS(x)                           (x+0x000006bc)
#define HWIO_REO_R0_EVENTMASK_IX_1_RMSK                              0xffffffff
#define HWIO_REO_R0_EVENTMASK_IX_1_SHFT                                       0
#define HWIO_REO_R0_EVENTMASK_IX_1_IN(x)                             \
	in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), HWIO_REO_R0_EVENTMASK_IX_1_RMSK)
#define HWIO_REO_R0_EVENTMASK_IX_1_INM(x, mask)                      \
	in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), mask) 
#define HWIO_REO_R0_EVENTMASK_IX_1_OUT(x, val)                       \
	out_dword( HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), val)
#define HWIO_REO_R0_EVENTMASK_IX_1_OUTM(x, mask, val)                \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), mask, val, HWIO_REO_R0_EVENTMASK_IX_1_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_EVENTMASK_IX_1_MASK_BMSK                         0xffffffff
#define HWIO_REO_R0_EVENTMASK_IX_1_MASK_SHFT                                0x0

//// Register REO_R0_EVENTMASK_IX_2 ////

#define HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x)                           (x+0x000006c0)
#define HWIO_REO_R0_EVENTMASK_IX_2_PHYS(x)                           (x+0x000006c0)
#define HWIO_REO_R0_EVENTMASK_IX_2_RMSK                              0xffffffff
#define HWIO_REO_R0_EVENTMASK_IX_2_SHFT                                       0
#define HWIO_REO_R0_EVENTMASK_IX_2_IN(x)                             \
	in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), HWIO_REO_R0_EVENTMASK_IX_2_RMSK)
#define HWIO_REO_R0_EVENTMASK_IX_2_INM(x, mask)                      \
	in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), mask) 
#define HWIO_REO_R0_EVENTMASK_IX_2_OUT(x, val)                       \
	out_dword( HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), val)
#define HWIO_REO_R0_EVENTMASK_IX_2_OUTM(x, mask, val)                \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), mask, val, HWIO_REO_R0_EVENTMASK_IX_2_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_EVENTMASK_IX_2_MASK_BMSK                         0xffffffff
#define HWIO_REO_R0_EVENTMASK_IX_2_MASK_SHFT                                0x0

//// Register REO_R0_EVENTMASK_IX_3 ////

#define HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x)                           (x+0x000006c4)
#define HWIO_REO_R0_EVENTMASK_IX_3_PHYS(x)                           (x+0x000006c4)
#define HWIO_REO_R0_EVENTMASK_IX_3_RMSK                              0xffffffff
#define HWIO_REO_R0_EVENTMASK_IX_3_SHFT                                       0
#define HWIO_REO_R0_EVENTMASK_IX_3_IN(x)                             \
	in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), HWIO_REO_R0_EVENTMASK_IX_3_RMSK)
#define HWIO_REO_R0_EVENTMASK_IX_3_INM(x, mask)                      \
	in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), mask) 
#define HWIO_REO_R0_EVENTMASK_IX_3_OUT(x, val)                       \
	out_dword( HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), val)
#define HWIO_REO_R0_EVENTMASK_IX_3_OUTM(x, mask, val)                \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), mask, val, HWIO_REO_R0_EVENTMASK_IX_3_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R0_EVENTMASK_IX_3_MASK_BMSK                         0xffffffff
#define HWIO_REO_R0_EVENTMASK_IX_3_MASK_SHFT                                0x0

//// Register REO_R1_MISC_DEBUG_CTRL ////

#define HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x)                          (x+0x00002000)
#define HWIO_REO_R1_MISC_DEBUG_CTRL_PHYS(x)                          (x+0x00002000)
#define HWIO_REO_R1_MISC_DEBUG_CTRL_RMSK                             0xffffffff
#define HWIO_REO_R1_MISC_DEBUG_CTRL_SHFT                                      0
#define HWIO_REO_R1_MISC_DEBUG_CTRL_IN(x)                            \
	in_dword_masked ( HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), HWIO_REO_R1_MISC_DEBUG_CTRL_RMSK)
#define HWIO_REO_R1_MISC_DEBUG_CTRL_INM(x, mask)                     \
	in_dword_masked ( HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), mask) 
#define HWIO_REO_R1_MISC_DEBUG_CTRL_OUT(x, val)                      \
	out_dword( HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), val)
#define HWIO_REO_R1_MISC_DEBUG_CTRL_OUTM(x, mask, val)               \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), mask, val, HWIO_REO_R1_MISC_DEBUG_CTRL_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R1_MISC_DEBUG_CTRL_DISABLE_SW_EXCEPTION_BMSK        0x80000000
#define HWIO_REO_R1_MISC_DEBUG_CTRL_DISABLE_SW_EXCEPTION_SHFT              0x1f

#define HWIO_REO_R1_MISC_DEBUG_CTRL_IDLE_REQ_BMSK                    0x40000000
#define HWIO_REO_R1_MISC_DEBUG_CTRL_IDLE_REQ_SHFT                          0x1e

#define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_RESUME_THRESH_BMSK      0x3ff00000
#define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_RESUME_THRESH_SHFT            0x14

#define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_STOP_THRESH_BMSK        0x000ffc00
#define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_STOP_THRESH_SHFT               0xa

#define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_START_THRESH_BMSK       0x000003ff
#define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_START_THRESH_SHFT              0x0

//// Register REO_R1_MISC_PERF_DEBUG_CTRL ////

#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x)                     (x+0x00002004)
#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_PHYS(x)                     (x+0x00002004)
#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RMSK                        0x00ffffff
#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_SHFT                                 0
#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_IN(x)                       \
	in_dword_masked ( HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RMSK)
#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_INM(x, mask)                \
	in_dword_masked ( HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), mask) 
#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_OUT(x, val)                 \
	out_dword( HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), val)
#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_OUTM(x, mask, val)          \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), mask, val, HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RELEASE_RING_ACCUM_DELAY_BMSK 0x00fff000
#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RELEASE_RING_ACCUM_DELAY_SHFT        0xc

#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_PROD_RING_ACCUM_DELAY_BMSK  0x00000fff
#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_PROD_RING_ACCUM_DELAY_SHFT         0x0

//// Register REO_R1_CACHE_CTL_DEBUG_CONTROL ////

#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x)                  (x+0x00002008)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_PHYS(x)                  (x+0x00002008)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_RMSK                     0x00000fff
#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_SHFT                              0
#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_IN(x)                    \
	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_RMSK)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_INM(x, mask)             \
	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), mask) 
#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_OUT(x, val)              \
	out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), val)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_OUTM(x, mask, val)       \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_ACK_BMSK  0x00000800
#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_ACK_SHFT         0xb

#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_BMSK      0x00000400
#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_SHFT             0xa

#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_UPDATE_BMSK    0x00000200
#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_UPDATE_SHFT           0x9

#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_SEL_BMSK       0x000001ff
#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_SEL_SHFT              0x0

//// Register REO_R1_CACHE_CTL_DEBUG_HIT_COUNT ////

#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x)                (x+0x0000200c)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_PHYS(x)                (x+0x0000200c)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_RMSK                   0xffffffff
#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_SHFT                            0
#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_IN(x)                  \
	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_RMSK)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_INM(x, mask)           \
	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), mask) 
#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_OUT(x, val)            \
	out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), val)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_OUTM(x, mask, val)     \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_CACHE_HIT_COUNT_BMSK   0xffffffff
#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_CACHE_HIT_COUNT_SHFT          0x0

//// Register REO_R1_CACHE_CTL_DEBUG_MISS_COUNT ////

#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x)               (x+0x00002010)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_PHYS(x)               (x+0x00002010)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_RMSK                  0x00ffffff
#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_SHFT                           0
#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_IN(x)                 \
	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_RMSK)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_INM(x, mask)          \
	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), mask) 
#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_OUT(x, val)           \
	out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), val)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_OUTM(x, mask, val)    \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_CACHE_MISS_COUNT_BMSK 0x00ffffff
#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_CACHE_MISS_COUNT_SHFT        0x0

//// Register REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW ////

#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x)            (x+0x00002014)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_PHYS(x)            (x+0x00002014)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_RMSK               0xffffffff
#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_SHFT                        0
#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_IN(x)              \
	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_RMSK)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_INM(x, mask)       \
	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), mask) 
#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OUT(x, val)        \
	out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), val)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OVERWRITE_BMSK     0xffffffff
#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OVERWRITE_SHFT            0x0

//// Register REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH ////

#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x)           (x+0x00002018)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_PHYS(x)           (x+0x00002018)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_RMSK              0xffffffff
#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_SHFT                       0
#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_IN(x)             \
	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_RMSK)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_INM(x, mask)      \
	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), mask) 
#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OUT(x, val)       \
	out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), val)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OVERWRITE_BMSK    0xffffffff
#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OVERWRITE_SHFT           0x0

//// Register REO_R1_CACHE_CTL_DEBUG_STM ////

#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x)                      (x+0x0000201c)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_PHYS(x)                      (x+0x0000201c)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_RMSK                         0x01ffffff
#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_SHFT                                  0
#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_IN(x)                        \
	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_STM_RMSK)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_INM(x, mask)                 \
	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), mask) 
#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_OUT(x, val)                  \
	out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), val)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_OUTM(x, mask, val)           \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_STM_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_STATE_BMSK                   0x01ffffff
#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_STATE_SHFT                          0x0

//// Register REO_R1_CACHE_CTL_DEBUG_LINK_LIST ////

#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x)                (x+0x00002020)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_PHYS(x)                (x+0x00002020)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_RMSK                   0x0007ffff
#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_SHFT                            0
#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_IN(x)                  \
	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_RMSK)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_INM(x, mask)           \
	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), mask) 
#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_OUT(x, val)            \
	out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), val)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_OUTM(x, mask, val)     \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_MRU_FLAG_BMSK          0x0007fc00
#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_MRU_FLAG_SHFT                 0xa

#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_LRU_FLAG_BMSK          0x000003ff
#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_LRU_FLAG_SHFT                 0x0

//// Register REO_R1_CACHE_CTL_DEBUG_LINK_LIST1 ////

#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_ADDR(x)               (x+0x00002024)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_PHYS(x)               (x+0x00002024)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_RMSK                  0x0007ffff
#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_SHFT                           0
#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_IN(x)                 \
	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_RMSK)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_INM(x, mask)          \
	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_ADDR(x), mask) 
#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_OUT(x, val)           \
	out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_ADDR(x), val)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_OUTM(x, mask, val)    \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_HEAD_FLAG_BMSK        0x0007fc00
#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_HEAD_FLAG_SHFT               0xa

#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_TAIL_FLAG_BMSK        0x000003ff
#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_TAIL_FLAG_SHFT               0x0

//// Register REO_R1_CACHE_CTL_DEBUG_LINK_LIST2 ////

#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_ADDR(x)               (x+0x00002028)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_PHYS(x)               (x+0x00002028)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_RMSK                  0x0007ffff
#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_SHFT                           0
#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_IN(x)                 \
	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_RMSK)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_INM(x, mask)          \
	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_ADDR(x), mask) 
#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_OUT(x, val)           \
	out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_ADDR(x), val)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_OUTM(x, mask, val)    \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_MRU_FLAG_SET2_BMSK    0x0007fc00
#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_MRU_FLAG_SET2_SHFT           0xa

#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_LRU_FLAG_SET2_BMSK    0x000003ff
#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_LRU_FLAG_SET2_SHFT           0x0

//// Register REO_R1_CACHE_CTL_DEBUG_LINK_LIST3 ////

#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_ADDR(x)               (x+0x0000202c)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_PHYS(x)               (x+0x0000202c)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_RMSK                  0x0007ffff
#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_SHFT                           0
#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_IN(x)                 \
	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_RMSK)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_INM(x, mask)          \
	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_ADDR(x), mask) 
#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_OUT(x, val)           \
	out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_ADDR(x), val)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_OUTM(x, mask, val)    \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_HEAD_FLAG_SET2_BMSK   0x0007fc00
#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_HEAD_FLAG_SET2_SHFT          0xa

#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_TAIL_FLAG_SET2_BMSK   0x000003ff
#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_TAIL_FLAG_SET2_SHFT          0x0

//// Register REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW ////

#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_ADDR(x)          (x+0x00002030)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_PHYS(x)          (x+0x00002030)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_RMSK             0xffffffff
#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_SHFT                      0
#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_IN(x)            \
	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_RMSK)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_INM(x, mask)     \
	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_ADDR(x), mask) 
#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_OUT(x, val)      \
	out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_ADDR(x), val)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_VALUE_BMSK       0xffffffff
#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_VALUE_SHFT              0x0

//// Register REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH ////

#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_ADDR(x)         (x+0x00002034)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_PHYS(x)         (x+0x00002034)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_RMSK            0xffffffff
#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_SHFT                     0
#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_IN(x)           \
	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_RMSK)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_INM(x, mask)    \
	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_ADDR(x), mask) 
#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_OUT(x, val)     \
	out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_ADDR(x), val)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_VALUE_BMSK      0xffffffff
#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_VALUE_SHFT             0x0

//// Register REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER ////

#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ADDR(x)       (x+0x00002038)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_PHYS(x)       (x+0x00002038)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_RMSK          0x000fffff
#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SHFT                   0
#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_IN(x)         \
	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_RMSK)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_INM(x, mask)  \
	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ADDR(x), mask) 
#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_OUT(x, val)   \
	out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ADDR(x), val)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SET2_BMSK     0x000ffc00
#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SET2_SHFT            0xa

#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SET1_BMSK     0x000003ff
#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SET1_SHFT            0x0

//// Register REO_R1_CACHE_CTL_END_OF_TEST_CHECK ////

#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x)              (x+0x0000203c)
#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_PHYS(x)              (x+0x0000203c)
#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_RMSK                 0x00000001
#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_SHFT                          0
#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_IN(x)                \
	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_RMSK)
#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_INM(x, mask)         \
	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), mask) 
#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_OUT(x, val)          \
	out_dword( HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), val)
#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_OUTM(x, mask, val)   \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001
#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT        0x0

//// Register REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1 ////

#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ADDR(x)            (x+0x00002040)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_PHYS(x)            (x+0x00002040)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_RMSK               0x000007ff
#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_SHFT                        0
#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_IN(x)              \
	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_RMSK)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_INM(x, mask)       \
	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ADDR(x), mask) 
#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_OUT(x, val)        \
	out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ADDR(x), val)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_BACKUP_BMSK        0x000007f8
#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_BACKUP_SHFT               0x3

#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_WITHOUT_INVALIDATE_BMSK 0x00000004
#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_WITHOUT_INVALIDATE_SHFT        0x2

#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_ENTIRE_CACHE_BMSK 0x00000002
#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_ENTIRE_CACHE_SHFT        0x1

#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_REQ_BMSK     0x00000001
#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_REQ_SHFT            0x0

//// Register REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2 ////

#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ADDR(x)            (x+0x00002044)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_PHYS(x)            (x+0x00002044)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_RMSK               0xffffffff
#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_SHFT                        0
#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_IN(x)              \
	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_RMSK)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_INM(x, mask)       \
	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ADDR(x), mask) 
#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_OUT(x, val)        \
	out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ADDR(x), val)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_FLUSH_ADDR_31_0_BMSK 0xffffffff
#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_FLUSH_ADDR_31_0_SHFT        0x0

//// Register REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3 ////

#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ADDR(x)            (x+0x00002048)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_PHYS(x)            (x+0x00002048)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_RMSK               0x000000ff
#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_SHFT                        0
#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_IN(x)              \
	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_RMSK)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_INM(x, mask)       \
	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ADDR(x), mask) 
#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_OUT(x, val)        \
	out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ADDR(x), val)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_FLUSH_ADDR_39_32_BMSK 0x000000ff
#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_FLUSH_ADDR_39_32_SHFT        0x0

//// Register REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS ////

#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_ADDR(x)             (x+0x0000204c)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_PHYS(x)             (x+0x0000204c)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_RMSK                0x3fffffff
#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_SHFT                         0
#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_IN(x)               \
	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_RMSK)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_INM(x, mask)        \
	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_ADDR(x), mask) 
#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_OUT(x, val)         \
	out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_ADDR(x), val)
#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_OUTM(x, mask, val)  \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_BACKUP_BMSK         0x3fc00000
#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_BACKUP_SHFT               0x16

#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_COUNT_BMSK    0x003ff000
#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_COUNT_SHFT           0xc

#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_HW_IF_BUSY_BMSK 0x00000800
#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_HW_IF_BUSY_SHFT        0xb

#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_ERROR_BMSK 0x00000600
#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_ERROR_SHFT        0x9

#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_CLIENT_ID_BMSK 0x000001e0
#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_CLIENT_ID_SHFT        0x5

#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_DESC_TYPE_BMSK 0x0000001c
#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_DESC_TYPE_SHFT        0x2

#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_HIT_BMSK 0x00000002
#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_HIT_SHFT        0x1

#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_DONE_BMSK     0x00000001
#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_DONE_SHFT            0x0

//// Register REO_R1_END_OF_TEST_CHECK ////

#define HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x)                        (x+0x00002050)
#define HWIO_REO_R1_END_OF_TEST_CHECK_PHYS(x)                        (x+0x00002050)
#define HWIO_REO_R1_END_OF_TEST_CHECK_RMSK                           0x00000001
#define HWIO_REO_R1_END_OF_TEST_CHECK_SHFT                                    0
#define HWIO_REO_R1_END_OF_TEST_CHECK_IN(x)                          \
	in_dword_masked ( HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), HWIO_REO_R1_END_OF_TEST_CHECK_RMSK)
#define HWIO_REO_R1_END_OF_TEST_CHECK_INM(x, mask)                   \
	in_dword_masked ( HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), mask) 
#define HWIO_REO_R1_END_OF_TEST_CHECK_OUT(x, val)                    \
	out_dword( HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), val)
#define HWIO_REO_R1_END_OF_TEST_CHECK_OUTM(x, mask, val)             \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_REO_R1_END_OF_TEST_CHECK_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK    0x00000001
#define HWIO_REO_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT           0x0

//// Register REO_R1_SM_ALL_IDLE ////

#define HWIO_REO_R1_SM_ALL_IDLE_ADDR(x)                              (x+0x00002054)
#define HWIO_REO_R1_SM_ALL_IDLE_PHYS(x)                              (x+0x00002054)
#define HWIO_REO_R1_SM_ALL_IDLE_RMSK                                 0x00000007
#define HWIO_REO_R1_SM_ALL_IDLE_SHFT                                          0
#define HWIO_REO_R1_SM_ALL_IDLE_IN(x)                                \
	in_dword_masked ( HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), HWIO_REO_R1_SM_ALL_IDLE_RMSK)
#define HWIO_REO_R1_SM_ALL_IDLE_INM(x, mask)                         \
	in_dword_masked ( HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), mask) 
#define HWIO_REO_R1_SM_ALL_IDLE_OUT(x, val)                          \
	out_dword( HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), val)
#define HWIO_REO_R1_SM_ALL_IDLE_OUTM(x, mask, val)                   \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), mask, val, HWIO_REO_R1_SM_ALL_IDLE_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R1_SM_ALL_IDLE_REO_ENTRANCE_RINGS_NOT_EMPTY_BMSK    0x00000004
#define HWIO_REO_R1_SM_ALL_IDLE_REO_ENTRANCE_RINGS_NOT_EMPTY_SHFT           0x2

#define HWIO_REO_R1_SM_ALL_IDLE_REO_IN_IDLE_BMSK                     0x00000002
#define HWIO_REO_R1_SM_ALL_IDLE_REO_IN_IDLE_SHFT                            0x1

#define HWIO_REO_R1_SM_ALL_IDLE_ALL_STATES_IN_IDLE_BMSK              0x00000001
#define HWIO_REO_R1_SM_ALL_IDLE_ALL_STATES_IN_IDLE_SHFT                     0x0

//// Register REO_R1_TESTBUS_CTRL ////

#define HWIO_REO_R1_TESTBUS_CTRL_ADDR(x)                             (x+0x00002058)
#define HWIO_REO_R1_TESTBUS_CTRL_PHYS(x)                             (x+0x00002058)
#define HWIO_REO_R1_TESTBUS_CTRL_RMSK                                0x0000007f
#define HWIO_REO_R1_TESTBUS_CTRL_SHFT                                         0
#define HWIO_REO_R1_TESTBUS_CTRL_IN(x)                               \
	in_dword_masked ( HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), HWIO_REO_R1_TESTBUS_CTRL_RMSK)
#define HWIO_REO_R1_TESTBUS_CTRL_INM(x, mask)                        \
	in_dword_masked ( HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), mask) 
#define HWIO_REO_R1_TESTBUS_CTRL_OUT(x, val)                         \
	out_dword( HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), val)
#define HWIO_REO_R1_TESTBUS_CTRL_OUTM(x, mask, val)                  \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), mask, val, HWIO_REO_R1_TESTBUS_CTRL_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R1_TESTBUS_CTRL_TESTBUS_SELECT_BMSK                 0x0000007f
#define HWIO_REO_R1_TESTBUS_CTRL_TESTBUS_SELECT_SHFT                        0x0

//// Register REO_R1_TESTBUS_LOWER ////

#define HWIO_REO_R1_TESTBUS_LOWER_ADDR(x)                            (x+0x0000205c)
#define HWIO_REO_R1_TESTBUS_LOWER_PHYS(x)                            (x+0x0000205c)
#define HWIO_REO_R1_TESTBUS_LOWER_RMSK                               0xffffffff
#define HWIO_REO_R1_TESTBUS_LOWER_SHFT                                        0
#define HWIO_REO_R1_TESTBUS_LOWER_IN(x)                              \
	in_dword_masked ( HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), HWIO_REO_R1_TESTBUS_LOWER_RMSK)
#define HWIO_REO_R1_TESTBUS_LOWER_INM(x, mask)                       \
	in_dword_masked ( HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), mask) 
#define HWIO_REO_R1_TESTBUS_LOWER_OUT(x, val)                        \
	out_dword( HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), val)
#define HWIO_REO_R1_TESTBUS_LOWER_OUTM(x, mask, val)                 \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_REO_R1_TESTBUS_LOWER_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R1_TESTBUS_LOWER_VALUE_BMSK                         0xffffffff
#define HWIO_REO_R1_TESTBUS_LOWER_VALUE_SHFT                                0x0

//// Register REO_R1_TESTBUS_HIGHER ////

#define HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x)                           (x+0x00002060)
#define HWIO_REO_R1_TESTBUS_HIGHER_PHYS(x)                           (x+0x00002060)
#define HWIO_REO_R1_TESTBUS_HIGHER_RMSK                              0x000000ff
#define HWIO_REO_R1_TESTBUS_HIGHER_SHFT                                       0
#define HWIO_REO_R1_TESTBUS_HIGHER_IN(x)                             \
	in_dword_masked ( HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), HWIO_REO_R1_TESTBUS_HIGHER_RMSK)
#define HWIO_REO_R1_TESTBUS_HIGHER_INM(x, mask)                      \
	in_dword_masked ( HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), mask) 
#define HWIO_REO_R1_TESTBUS_HIGHER_OUT(x, val)                       \
	out_dword( HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), val)
#define HWIO_REO_R1_TESTBUS_HIGHER_OUTM(x, mask, val)                \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), mask, val, HWIO_REO_R1_TESTBUS_HIGHER_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R1_TESTBUS_HIGHER_VALUE_BMSK                        0x000000ff
#define HWIO_REO_R1_TESTBUS_HIGHER_VALUE_SHFT                               0x0

//// Register REO_R1_SM_STATES_IX_0 ////

#define HWIO_REO_R1_SM_STATES_IX_0_ADDR(x)                           (x+0x00002064)
#define HWIO_REO_R1_SM_STATES_IX_0_PHYS(x)                           (x+0x00002064)
#define HWIO_REO_R1_SM_STATES_IX_0_RMSK                              0xffffffff
#define HWIO_REO_R1_SM_STATES_IX_0_SHFT                                       0
#define HWIO_REO_R1_SM_STATES_IX_0_IN(x)                             \
	in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), HWIO_REO_R1_SM_STATES_IX_0_RMSK)
#define HWIO_REO_R1_SM_STATES_IX_0_INM(x, mask)                      \
	in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), mask) 
#define HWIO_REO_R1_SM_STATES_IX_0_OUT(x, val)                       \
	out_dword( HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), val)
#define HWIO_REO_R1_SM_STATES_IX_0_OUTM(x, mask, val)                \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_0_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R1_SM_STATES_IX_0_SM_STATE_BMSK                     0xffffffff
#define HWIO_REO_R1_SM_STATES_IX_0_SM_STATE_SHFT                            0x0

//// Register REO_R1_SM_STATES_IX_1 ////

#define HWIO_REO_R1_SM_STATES_IX_1_ADDR(x)                           (x+0x00002068)
#define HWIO_REO_R1_SM_STATES_IX_1_PHYS(x)                           (x+0x00002068)
#define HWIO_REO_R1_SM_STATES_IX_1_RMSK                              0xffffffff
#define HWIO_REO_R1_SM_STATES_IX_1_SHFT                                       0
#define HWIO_REO_R1_SM_STATES_IX_1_IN(x)                             \
	in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), HWIO_REO_R1_SM_STATES_IX_1_RMSK)
#define HWIO_REO_R1_SM_STATES_IX_1_INM(x, mask)                      \
	in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), mask) 
#define HWIO_REO_R1_SM_STATES_IX_1_OUT(x, val)                       \
	out_dword( HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), val)
#define HWIO_REO_R1_SM_STATES_IX_1_OUTM(x, mask, val)                \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_1_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R1_SM_STATES_IX_1_SM_STATE_BMSK                     0xffffffff
#define HWIO_REO_R1_SM_STATES_IX_1_SM_STATE_SHFT                            0x0

//// Register REO_R1_SM_STATES_IX_2 ////

#define HWIO_REO_R1_SM_STATES_IX_2_ADDR(x)                           (x+0x0000206c)
#define HWIO_REO_R1_SM_STATES_IX_2_PHYS(x)                           (x+0x0000206c)
#define HWIO_REO_R1_SM_STATES_IX_2_RMSK                              0xffffffff
#define HWIO_REO_R1_SM_STATES_IX_2_SHFT                                       0
#define HWIO_REO_R1_SM_STATES_IX_2_IN(x)                             \
	in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), HWIO_REO_R1_SM_STATES_IX_2_RMSK)
#define HWIO_REO_R1_SM_STATES_IX_2_INM(x, mask)                      \
	in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), mask) 
#define HWIO_REO_R1_SM_STATES_IX_2_OUT(x, val)                       \
	out_dword( HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), val)
#define HWIO_REO_R1_SM_STATES_IX_2_OUTM(x, mask, val)                \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_2_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R1_SM_STATES_IX_2_SM_STATE_BMSK                     0xffffffff
#define HWIO_REO_R1_SM_STATES_IX_2_SM_STATE_SHFT                            0x0

//// Register REO_R1_SM_STATES_IX_3 ////

#define HWIO_REO_R1_SM_STATES_IX_3_ADDR(x)                           (x+0x00002070)
#define HWIO_REO_R1_SM_STATES_IX_3_PHYS(x)                           (x+0x00002070)
#define HWIO_REO_R1_SM_STATES_IX_3_RMSK                              0xffffffff
#define HWIO_REO_R1_SM_STATES_IX_3_SHFT                                       0
#define HWIO_REO_R1_SM_STATES_IX_3_IN(x)                             \
	in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), HWIO_REO_R1_SM_STATES_IX_3_RMSK)
#define HWIO_REO_R1_SM_STATES_IX_3_INM(x, mask)                      \
	in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), mask) 
#define HWIO_REO_R1_SM_STATES_IX_3_OUT(x, val)                       \
	out_dword( HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), val)
#define HWIO_REO_R1_SM_STATES_IX_3_OUTM(x, mask, val)                \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_3_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R1_SM_STATES_IX_3_SM_STATE_BMSK                     0xffffffff
#define HWIO_REO_R1_SM_STATES_IX_3_SM_STATE_SHFT                            0x0

//// Register REO_R1_SM_STATES_IX_4 ////

#define HWIO_REO_R1_SM_STATES_IX_4_ADDR(x)                           (x+0x00002074)
#define HWIO_REO_R1_SM_STATES_IX_4_PHYS(x)                           (x+0x00002074)
#define HWIO_REO_R1_SM_STATES_IX_4_RMSK                              0xffffffff
#define HWIO_REO_R1_SM_STATES_IX_4_SHFT                                       0
#define HWIO_REO_R1_SM_STATES_IX_4_IN(x)                             \
	in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), HWIO_REO_R1_SM_STATES_IX_4_RMSK)
#define HWIO_REO_R1_SM_STATES_IX_4_INM(x, mask)                      \
	in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), mask) 
#define HWIO_REO_R1_SM_STATES_IX_4_OUT(x, val)                       \
	out_dword( HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), val)
#define HWIO_REO_R1_SM_STATES_IX_4_OUTM(x, mask, val)                \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_4_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R1_SM_STATES_IX_4_SM_STATE_BMSK                     0xffffffff
#define HWIO_REO_R1_SM_STATES_IX_4_SM_STATE_SHFT                            0x0

//// Register REO_R1_SM_STATES_IX_5 ////

#define HWIO_REO_R1_SM_STATES_IX_5_ADDR(x)                           (x+0x00002078)
#define HWIO_REO_R1_SM_STATES_IX_5_PHYS(x)                           (x+0x00002078)
#define HWIO_REO_R1_SM_STATES_IX_5_RMSK                              0xffffffff
#define HWIO_REO_R1_SM_STATES_IX_5_SHFT                                       0
#define HWIO_REO_R1_SM_STATES_IX_5_IN(x)                             \
	in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), HWIO_REO_R1_SM_STATES_IX_5_RMSK)
#define HWIO_REO_R1_SM_STATES_IX_5_INM(x, mask)                      \
	in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), mask) 
#define HWIO_REO_R1_SM_STATES_IX_5_OUT(x, val)                       \
	out_dword( HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), val)
#define HWIO_REO_R1_SM_STATES_IX_5_OUTM(x, mask, val)                \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_5_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R1_SM_STATES_IX_5_SM_STATE_BMSK                     0xffffffff
#define HWIO_REO_R1_SM_STATES_IX_5_SM_STATE_SHFT                            0x0

//// Register REO_R1_SM_STATES_IX_6 ////

#define HWIO_REO_R1_SM_STATES_IX_6_ADDR(x)                           (x+0x0000207c)
#define HWIO_REO_R1_SM_STATES_IX_6_PHYS(x)                           (x+0x0000207c)
#define HWIO_REO_R1_SM_STATES_IX_6_RMSK                              0xffffffff
#define HWIO_REO_R1_SM_STATES_IX_6_SHFT                                       0
#define HWIO_REO_R1_SM_STATES_IX_6_IN(x)                             \
	in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), HWIO_REO_R1_SM_STATES_IX_6_RMSK)
#define HWIO_REO_R1_SM_STATES_IX_6_INM(x, mask)                      \
	in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), mask) 
#define HWIO_REO_R1_SM_STATES_IX_6_OUT(x, val)                       \
	out_dword( HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), val)
#define HWIO_REO_R1_SM_STATES_IX_6_OUTM(x, mask, val)                \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_6_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R1_SM_STATES_IX_6_SM_STATE_BMSK                     0xffffffff
#define HWIO_REO_R1_SM_STATES_IX_6_SM_STATE_SHFT                            0x0

//// Register REO_R1_IDLE_STATES_IX_0 ////

#define HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x)                         (x+0x00002080)
#define HWIO_REO_R1_IDLE_STATES_IX_0_PHYS(x)                         (x+0x00002080)
#define HWIO_REO_R1_IDLE_STATES_IX_0_RMSK                            0xffffffff
#define HWIO_REO_R1_IDLE_STATES_IX_0_SHFT                                     0
#define HWIO_REO_R1_IDLE_STATES_IX_0_IN(x)                           \
	in_dword_masked ( HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), HWIO_REO_R1_IDLE_STATES_IX_0_RMSK)
#define HWIO_REO_R1_IDLE_STATES_IX_0_INM(x, mask)                    \
	in_dword_masked ( HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), mask) 
#define HWIO_REO_R1_IDLE_STATES_IX_0_OUT(x, val)                     \
	out_dword( HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), val)
#define HWIO_REO_R1_IDLE_STATES_IX_0_OUTM(x, mask, val)              \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), mask, val, HWIO_REO_R1_IDLE_STATES_IX_0_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R1_IDLE_STATES_IX_0_IDLE_STATE_BMSK                 0xffffffff
#define HWIO_REO_R1_IDLE_STATES_IX_0_IDLE_STATE_SHFT                        0x0

//// Register REO_R1_INVALID_APB_ACCESS ////

#define HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x)                       (x+0x00002084)
#define HWIO_REO_R1_INVALID_APB_ACCESS_PHYS(x)                       (x+0x00002084)
#define HWIO_REO_R1_INVALID_APB_ACCESS_RMSK                          0x0007ffff
#define HWIO_REO_R1_INVALID_APB_ACCESS_SHFT                                   0
#define HWIO_REO_R1_INVALID_APB_ACCESS_IN(x)                         \
	in_dword_masked ( HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), HWIO_REO_R1_INVALID_APB_ACCESS_RMSK)
#define HWIO_REO_R1_INVALID_APB_ACCESS_INM(x, mask)                  \
	in_dword_masked ( HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), mask) 
#define HWIO_REO_R1_INVALID_APB_ACCESS_OUT(x, val)                   \
	out_dword( HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), val)
#define HWIO_REO_R1_INVALID_APB_ACCESS_OUTM(x, mask, val)            \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), mask, val, HWIO_REO_R1_INVALID_APB_ACCESS_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_TYPE_BMSK                 0x00060000
#define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_TYPE_SHFT                       0x11

#define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_ADDR_BMSK                 0x0001ffff
#define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_ADDR_SHFT                        0x0

//// Register REO_R2_RXDMA2REO0_RING_HP ////

#define HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x)                       (x+0x00003000)
#define HWIO_REO_R2_RXDMA2REO0_RING_HP_PHYS(x)                       (x+0x00003000)
#define HWIO_REO_R2_RXDMA2REO0_RING_HP_RMSK                          0x0000ffff
#define HWIO_REO_R2_RXDMA2REO0_RING_HP_SHFT                                   0
#define HWIO_REO_R2_RXDMA2REO0_RING_HP_IN(x)                         \
	in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), HWIO_REO_R2_RXDMA2REO0_RING_HP_RMSK)
#define HWIO_REO_R2_RXDMA2REO0_RING_HP_INM(x, mask)                  \
	in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), mask) 
#define HWIO_REO_R2_RXDMA2REO0_RING_HP_OUT(x, val)                   \
	out_dword( HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), val)
#define HWIO_REO_R2_RXDMA2REO0_RING_HP_OUTM(x, mask, val)            \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO0_RING_HP_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R2_RXDMA2REO0_RING_HP_HEAD_PTR_BMSK                 0x0000ffff
#define HWIO_REO_R2_RXDMA2REO0_RING_HP_HEAD_PTR_SHFT                        0x0

//// Register REO_R2_RXDMA2REO0_RING_TP ////

#define HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x)                       (x+0x00003004)
#define HWIO_REO_R2_RXDMA2REO0_RING_TP_PHYS(x)                       (x+0x00003004)
#define HWIO_REO_R2_RXDMA2REO0_RING_TP_RMSK                          0x0000ffff
#define HWIO_REO_R2_RXDMA2REO0_RING_TP_SHFT                                   0
#define HWIO_REO_R2_RXDMA2REO0_RING_TP_IN(x)                         \
	in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), HWIO_REO_R2_RXDMA2REO0_RING_TP_RMSK)
#define HWIO_REO_R2_RXDMA2REO0_RING_TP_INM(x, mask)                  \
	in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), mask) 
#define HWIO_REO_R2_RXDMA2REO0_RING_TP_OUT(x, val)                   \
	out_dword( HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), val)
#define HWIO_REO_R2_RXDMA2REO0_RING_TP_OUTM(x, mask, val)            \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO0_RING_TP_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R2_RXDMA2REO0_RING_TP_TAIL_PTR_BMSK                 0x0000ffff
#define HWIO_REO_R2_RXDMA2REO0_RING_TP_TAIL_PTR_SHFT                        0x0

//// Register REO_R2_WBM2REO_LINK_RING_HP ////

#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x)                     (x+0x00003008)
#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_PHYS(x)                     (x+0x00003008)
#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_RMSK                        0x0000ffff
#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_SHFT                                 0
#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_IN(x)                       \
	in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), HWIO_REO_R2_WBM2REO_LINK_RING_HP_RMSK)
#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_INM(x, mask)                \
	in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), mask) 
#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_OUT(x, val)                 \
	out_dword( HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), val)
#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_OUTM(x, mask, val)          \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_WBM2REO_LINK_RING_HP_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_HEAD_PTR_BMSK               0x0000ffff
#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_HEAD_PTR_SHFT                      0x0

//// Register REO_R2_WBM2REO_LINK_RING_TP ////

#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x)                     (x+0x0000300c)
#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_PHYS(x)                     (x+0x0000300c)
#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_RMSK                        0x0000ffff
#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_SHFT                                 0
#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_IN(x)                       \
	in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), HWIO_REO_R2_WBM2REO_LINK_RING_TP_RMSK)
#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_INM(x, mask)                \
	in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), mask) 
#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_OUT(x, val)                 \
	out_dword( HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), val)
#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_OUTM(x, mask, val)          \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_WBM2REO_LINK_RING_TP_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_TAIL_PTR_BMSK               0x0000ffff
#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_TAIL_PTR_SHFT                      0x0

//// Register REO_R2_REO_CMD_RING_HP ////

#define HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x)                          (x+0x00003010)
#define HWIO_REO_R2_REO_CMD_RING_HP_PHYS(x)                          (x+0x00003010)
#define HWIO_REO_R2_REO_CMD_RING_HP_RMSK                             0x0000ffff
#define HWIO_REO_R2_REO_CMD_RING_HP_SHFT                                      0
#define HWIO_REO_R2_REO_CMD_RING_HP_IN(x)                            \
	in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), HWIO_REO_R2_REO_CMD_RING_HP_RMSK)
#define HWIO_REO_R2_REO_CMD_RING_HP_INM(x, mask)                     \
	in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), mask) 
#define HWIO_REO_R2_REO_CMD_RING_HP_OUT(x, val)                      \
	out_dword( HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), val)
#define HWIO_REO_R2_REO_CMD_RING_HP_OUTM(x, mask, val)               \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO_CMD_RING_HP_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R2_REO_CMD_RING_HP_HEAD_PTR_BMSK                    0x0000ffff
#define HWIO_REO_R2_REO_CMD_RING_HP_HEAD_PTR_SHFT                           0x0

//// Register REO_R2_REO_CMD_RING_TP ////

#define HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x)                          (x+0x00003014)
#define HWIO_REO_R2_REO_CMD_RING_TP_PHYS(x)                          (x+0x00003014)
#define HWIO_REO_R2_REO_CMD_RING_TP_RMSK                             0x0000ffff
#define HWIO_REO_R2_REO_CMD_RING_TP_SHFT                                      0
#define HWIO_REO_R2_REO_CMD_RING_TP_IN(x)                            \
	in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), HWIO_REO_R2_REO_CMD_RING_TP_RMSK)
#define HWIO_REO_R2_REO_CMD_RING_TP_INM(x, mask)                     \
	in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), mask) 
#define HWIO_REO_R2_REO_CMD_RING_TP_OUT(x, val)                      \
	out_dword( HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), val)
#define HWIO_REO_R2_REO_CMD_RING_TP_OUTM(x, mask, val)               \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO_CMD_RING_TP_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R2_REO_CMD_RING_TP_TAIL_PTR_BMSK                    0x0000ffff
#define HWIO_REO_R2_REO_CMD_RING_TP_TAIL_PTR_SHFT                           0x0

//// Register REO_R2_SW2REO_RING_HP ////

#define HWIO_REO_R2_SW2REO_RING_HP_ADDR(x)                           (x+0x00003018)
#define HWIO_REO_R2_SW2REO_RING_HP_PHYS(x)                           (x+0x00003018)
#define HWIO_REO_R2_SW2REO_RING_HP_RMSK                              0x0000ffff
#define HWIO_REO_R2_SW2REO_RING_HP_SHFT                                       0
#define HWIO_REO_R2_SW2REO_RING_HP_IN(x)                             \
	in_dword_masked ( HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), HWIO_REO_R2_SW2REO_RING_HP_RMSK)
#define HWIO_REO_R2_SW2REO_RING_HP_INM(x, mask)                      \
	in_dword_masked ( HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), mask) 
#define HWIO_REO_R2_SW2REO_RING_HP_OUT(x, val)                       \
	out_dword( HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), val)
#define HWIO_REO_R2_SW2REO_RING_HP_OUTM(x, mask, val)                \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_SW2REO_RING_HP_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R2_SW2REO_RING_HP_HEAD_PTR_BMSK                     0x0000ffff
#define HWIO_REO_R2_SW2REO_RING_HP_HEAD_PTR_SHFT                            0x0

//// Register REO_R2_SW2REO_RING_TP ////

#define HWIO_REO_R2_SW2REO_RING_TP_ADDR(x)                           (x+0x0000301c)
#define HWIO_REO_R2_SW2REO_RING_TP_PHYS(x)                           (x+0x0000301c)
#define HWIO_REO_R2_SW2REO_RING_TP_RMSK                              0x0000ffff
#define HWIO_REO_R2_SW2REO_RING_TP_SHFT                                       0
#define HWIO_REO_R2_SW2REO_RING_TP_IN(x)                             \
	in_dword_masked ( HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), HWIO_REO_R2_SW2REO_RING_TP_RMSK)
#define HWIO_REO_R2_SW2REO_RING_TP_INM(x, mask)                      \
	in_dword_masked ( HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), mask) 
#define HWIO_REO_R2_SW2REO_RING_TP_OUT(x, val)                       \
	out_dword( HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), val)
#define HWIO_REO_R2_SW2REO_RING_TP_OUTM(x, mask, val)                \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_SW2REO_RING_TP_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R2_SW2REO_RING_TP_TAIL_PTR_BMSK                     0x0000ffff
#define HWIO_REO_R2_SW2REO_RING_TP_TAIL_PTR_SHFT                            0x0

//// Register REO_R2_SW2REO1_RING_HP ////

#define HWIO_REO_R2_SW2REO1_RING_HP_ADDR(x)                          (x+0x00003020)
#define HWIO_REO_R2_SW2REO1_RING_HP_PHYS(x)                          (x+0x00003020)
#define HWIO_REO_R2_SW2REO1_RING_HP_RMSK                             0x0000ffff
#define HWIO_REO_R2_SW2REO1_RING_HP_SHFT                                      0
#define HWIO_REO_R2_SW2REO1_RING_HP_IN(x)                            \
	in_dword_masked ( HWIO_REO_R2_SW2REO1_RING_HP_ADDR(x), HWIO_REO_R2_SW2REO1_RING_HP_RMSK)
#define HWIO_REO_R2_SW2REO1_RING_HP_INM(x, mask)                     \
	in_dword_masked ( HWIO_REO_R2_SW2REO1_RING_HP_ADDR(x), mask) 
#define HWIO_REO_R2_SW2REO1_RING_HP_OUT(x, val)                      \
	out_dword( HWIO_REO_R2_SW2REO1_RING_HP_ADDR(x), val)
#define HWIO_REO_R2_SW2REO1_RING_HP_OUTM(x, mask, val)               \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R2_SW2REO1_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_SW2REO1_RING_HP_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R2_SW2REO1_RING_HP_HEAD_PTR_BMSK                    0x0000ffff
#define HWIO_REO_R2_SW2REO1_RING_HP_HEAD_PTR_SHFT                           0x0

//// Register REO_R2_SW2REO1_RING_TP ////

#define HWIO_REO_R2_SW2REO1_RING_TP_ADDR(x)                          (x+0x00003024)
#define HWIO_REO_R2_SW2REO1_RING_TP_PHYS(x)                          (x+0x00003024)
#define HWIO_REO_R2_SW2REO1_RING_TP_RMSK                             0x0000ffff
#define HWIO_REO_R2_SW2REO1_RING_TP_SHFT                                      0
#define HWIO_REO_R2_SW2REO1_RING_TP_IN(x)                            \
	in_dword_masked ( HWIO_REO_R2_SW2REO1_RING_TP_ADDR(x), HWIO_REO_R2_SW2REO1_RING_TP_RMSK)
#define HWIO_REO_R2_SW2REO1_RING_TP_INM(x, mask)                     \
	in_dword_masked ( HWIO_REO_R2_SW2REO1_RING_TP_ADDR(x), mask) 
#define HWIO_REO_R2_SW2REO1_RING_TP_OUT(x, val)                      \
	out_dword( HWIO_REO_R2_SW2REO1_RING_TP_ADDR(x), val)
#define HWIO_REO_R2_SW2REO1_RING_TP_OUTM(x, mask, val)               \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R2_SW2REO1_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_SW2REO1_RING_TP_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R2_SW2REO1_RING_TP_TAIL_PTR_BMSK                    0x0000ffff
#define HWIO_REO_R2_SW2REO1_RING_TP_TAIL_PTR_SHFT                           0x0

//// Register REO_R2_REO2SW1_RING_HP ////

#define HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x)                          (x+0x00003028)
#define HWIO_REO_R2_REO2SW1_RING_HP_PHYS(x)                          (x+0x00003028)
#define HWIO_REO_R2_REO2SW1_RING_HP_RMSK                             0x000fffff
#define HWIO_REO_R2_REO2SW1_RING_HP_SHFT                                      0
#define HWIO_REO_R2_REO2SW1_RING_HP_IN(x)                            \
	in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW1_RING_HP_RMSK)
#define HWIO_REO_R2_REO2SW1_RING_HP_INM(x, mask)                     \
	in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), mask) 
#define HWIO_REO_R2_REO2SW1_RING_HP_OUT(x, val)                      \
	out_dword( HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), val)
#define HWIO_REO_R2_REO2SW1_RING_HP_OUTM(x, mask, val)               \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW1_RING_HP_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R2_REO2SW1_RING_HP_HEAD_PTR_BMSK                    0x000fffff
#define HWIO_REO_R2_REO2SW1_RING_HP_HEAD_PTR_SHFT                           0x0

//// Register REO_R2_REO2SW1_RING_TP ////

#define HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x)                          (x+0x0000302c)
#define HWIO_REO_R2_REO2SW1_RING_TP_PHYS(x)                          (x+0x0000302c)
#define HWIO_REO_R2_REO2SW1_RING_TP_RMSK                             0x000fffff
#define HWIO_REO_R2_REO2SW1_RING_TP_SHFT                                      0
#define HWIO_REO_R2_REO2SW1_RING_TP_IN(x)                            \
	in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW1_RING_TP_RMSK)
#define HWIO_REO_R2_REO2SW1_RING_TP_INM(x, mask)                     \
	in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), mask) 
#define HWIO_REO_R2_REO2SW1_RING_TP_OUT(x, val)                      \
	out_dword( HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), val)
#define HWIO_REO_R2_REO2SW1_RING_TP_OUTM(x, mask, val)               \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW1_RING_TP_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R2_REO2SW1_RING_TP_TAIL_PTR_BMSK                    0x000fffff
#define HWIO_REO_R2_REO2SW1_RING_TP_TAIL_PTR_SHFT                           0x0

//// Register REO_R2_REO2SW2_RING_HP ////

#define HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x)                          (x+0x00003030)
#define HWIO_REO_R2_REO2SW2_RING_HP_PHYS(x)                          (x+0x00003030)
#define HWIO_REO_R2_REO2SW2_RING_HP_RMSK                             0x000fffff
#define HWIO_REO_R2_REO2SW2_RING_HP_SHFT                                      0
#define HWIO_REO_R2_REO2SW2_RING_HP_IN(x)                            \
	in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW2_RING_HP_RMSK)
#define HWIO_REO_R2_REO2SW2_RING_HP_INM(x, mask)                     \
	in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), mask) 
#define HWIO_REO_R2_REO2SW2_RING_HP_OUT(x, val)                      \
	out_dword( HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), val)
#define HWIO_REO_R2_REO2SW2_RING_HP_OUTM(x, mask, val)               \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW2_RING_HP_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R2_REO2SW2_RING_HP_HEAD_PTR_BMSK                    0x000fffff
#define HWIO_REO_R2_REO2SW2_RING_HP_HEAD_PTR_SHFT                           0x0

//// Register REO_R2_REO2SW2_RING_TP ////

#define HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x)                          (x+0x00003034)
#define HWIO_REO_R2_REO2SW2_RING_TP_PHYS(x)                          (x+0x00003034)
#define HWIO_REO_R2_REO2SW2_RING_TP_RMSK                             0x000fffff
#define HWIO_REO_R2_REO2SW2_RING_TP_SHFT                                      0
#define HWIO_REO_R2_REO2SW2_RING_TP_IN(x)                            \
	in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW2_RING_TP_RMSK)
#define HWIO_REO_R2_REO2SW2_RING_TP_INM(x, mask)                     \
	in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), mask) 
#define HWIO_REO_R2_REO2SW2_RING_TP_OUT(x, val)                      \
	out_dword( HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), val)
#define HWIO_REO_R2_REO2SW2_RING_TP_OUTM(x, mask, val)               \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW2_RING_TP_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R2_REO2SW2_RING_TP_TAIL_PTR_BMSK                    0x000fffff
#define HWIO_REO_R2_REO2SW2_RING_TP_TAIL_PTR_SHFT                           0x0

//// Register REO_R2_REO2SW3_RING_HP ////

#define HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x)                          (x+0x00003038)
#define HWIO_REO_R2_REO2SW3_RING_HP_PHYS(x)                          (x+0x00003038)
#define HWIO_REO_R2_REO2SW3_RING_HP_RMSK                             0x000fffff
#define HWIO_REO_R2_REO2SW3_RING_HP_SHFT                                      0
#define HWIO_REO_R2_REO2SW3_RING_HP_IN(x)                            \
	in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW3_RING_HP_RMSK)
#define HWIO_REO_R2_REO2SW3_RING_HP_INM(x, mask)                     \
	in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), mask) 
#define HWIO_REO_R2_REO2SW3_RING_HP_OUT(x, val)                      \
	out_dword( HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), val)
#define HWIO_REO_R2_REO2SW3_RING_HP_OUTM(x, mask, val)               \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW3_RING_HP_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R2_REO2SW3_RING_HP_HEAD_PTR_BMSK                    0x000fffff
#define HWIO_REO_R2_REO2SW3_RING_HP_HEAD_PTR_SHFT                           0x0

//// Register REO_R2_REO2SW3_RING_TP ////

#define HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x)                          (x+0x0000303c)
#define HWIO_REO_R2_REO2SW3_RING_TP_PHYS(x)                          (x+0x0000303c)
#define HWIO_REO_R2_REO2SW3_RING_TP_RMSK                             0x000fffff
#define HWIO_REO_R2_REO2SW3_RING_TP_SHFT                                      0
#define HWIO_REO_R2_REO2SW3_RING_TP_IN(x)                            \
	in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW3_RING_TP_RMSK)
#define HWIO_REO_R2_REO2SW3_RING_TP_INM(x, mask)                     \
	in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), mask) 
#define HWIO_REO_R2_REO2SW3_RING_TP_OUT(x, val)                      \
	out_dword( HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), val)
#define HWIO_REO_R2_REO2SW3_RING_TP_OUTM(x, mask, val)               \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW3_RING_TP_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R2_REO2SW3_RING_TP_TAIL_PTR_BMSK                    0x000fffff
#define HWIO_REO_R2_REO2SW3_RING_TP_TAIL_PTR_SHFT                           0x0

//// Register REO_R2_REO2SW4_RING_HP ////

#define HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x)                          (x+0x00003040)
#define HWIO_REO_R2_REO2SW4_RING_HP_PHYS(x)                          (x+0x00003040)
#define HWIO_REO_R2_REO2SW4_RING_HP_RMSK                             0x000fffff
#define HWIO_REO_R2_REO2SW4_RING_HP_SHFT                                      0
#define HWIO_REO_R2_REO2SW4_RING_HP_IN(x)                            \
	in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW4_RING_HP_RMSK)
#define HWIO_REO_R2_REO2SW4_RING_HP_INM(x, mask)                     \
	in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), mask) 
#define HWIO_REO_R2_REO2SW4_RING_HP_OUT(x, val)                      \
	out_dword( HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), val)
#define HWIO_REO_R2_REO2SW4_RING_HP_OUTM(x, mask, val)               \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW4_RING_HP_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R2_REO2SW4_RING_HP_HEAD_PTR_BMSK                    0x000fffff
#define HWIO_REO_R2_REO2SW4_RING_HP_HEAD_PTR_SHFT                           0x0

//// Register REO_R2_REO2SW4_RING_TP ////

#define HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x)                          (x+0x00003044)
#define HWIO_REO_R2_REO2SW4_RING_TP_PHYS(x)                          (x+0x00003044)
#define HWIO_REO_R2_REO2SW4_RING_TP_RMSK                             0x000fffff
#define HWIO_REO_R2_REO2SW4_RING_TP_SHFT                                      0
#define HWIO_REO_R2_REO2SW4_RING_TP_IN(x)                            \
	in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW4_RING_TP_RMSK)
#define HWIO_REO_R2_REO2SW4_RING_TP_INM(x, mask)                     \
	in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), mask) 
#define HWIO_REO_R2_REO2SW4_RING_TP_OUT(x, val)                      \
	out_dword( HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), val)
#define HWIO_REO_R2_REO2SW4_RING_TP_OUTM(x, mask, val)               \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW4_RING_TP_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R2_REO2SW4_RING_TP_TAIL_PTR_BMSK                    0x000fffff
#define HWIO_REO_R2_REO2SW4_RING_TP_TAIL_PTR_SHFT                           0x0

//// Register REO_R2_REO2TCL_RING_HP ////

#define HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x)                          (x+0x00003058)
#define HWIO_REO_R2_REO2TCL_RING_HP_PHYS(x)                          (x+0x00003058)
#define HWIO_REO_R2_REO2TCL_RING_HP_RMSK                             0x000fffff
#define HWIO_REO_R2_REO2TCL_RING_HP_SHFT                                      0
#define HWIO_REO_R2_REO2TCL_RING_HP_IN(x)                            \
	in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), HWIO_REO_R2_REO2TCL_RING_HP_RMSK)
#define HWIO_REO_R2_REO2TCL_RING_HP_INM(x, mask)                     \
	in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), mask) 
#define HWIO_REO_R2_REO2TCL_RING_HP_OUT(x, val)                      \
	out_dword( HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), val)
#define HWIO_REO_R2_REO2TCL_RING_HP_OUTM(x, mask, val)               \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2TCL_RING_HP_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R2_REO2TCL_RING_HP_HEAD_PTR_BMSK                    0x000fffff
#define HWIO_REO_R2_REO2TCL_RING_HP_HEAD_PTR_SHFT                           0x0

//// Register REO_R2_REO2TCL_RING_TP ////

#define HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x)                          (x+0x0000305c)
#define HWIO_REO_R2_REO2TCL_RING_TP_PHYS(x)                          (x+0x0000305c)
#define HWIO_REO_R2_REO2TCL_RING_TP_RMSK                             0x000fffff
#define HWIO_REO_R2_REO2TCL_RING_TP_SHFT                                      0
#define HWIO_REO_R2_REO2TCL_RING_TP_IN(x)                            \
	in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), HWIO_REO_R2_REO2TCL_RING_TP_RMSK)
#define HWIO_REO_R2_REO2TCL_RING_TP_INM(x, mask)                     \
	in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), mask) 
#define HWIO_REO_R2_REO2TCL_RING_TP_OUT(x, val)                      \
	out_dword( HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), val)
#define HWIO_REO_R2_REO2TCL_RING_TP_OUTM(x, mask, val)               \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2TCL_RING_TP_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R2_REO2TCL_RING_TP_TAIL_PTR_BMSK                    0x000fffff
#define HWIO_REO_R2_REO2TCL_RING_TP_TAIL_PTR_SHFT                           0x0

//// Register REO_R2_REO2FW_RING_HP ////

#define HWIO_REO_R2_REO2FW_RING_HP_ADDR(x)                           (x+0x00003060)
#define HWIO_REO_R2_REO2FW_RING_HP_PHYS(x)                           (x+0x00003060)
#define HWIO_REO_R2_REO2FW_RING_HP_RMSK                              0x000fffff
#define HWIO_REO_R2_REO2FW_RING_HP_SHFT                                       0
#define HWIO_REO_R2_REO2FW_RING_HP_IN(x)                             \
	in_dword_masked ( HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), HWIO_REO_R2_REO2FW_RING_HP_RMSK)
#define HWIO_REO_R2_REO2FW_RING_HP_INM(x, mask)                      \
	in_dword_masked ( HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), mask) 
#define HWIO_REO_R2_REO2FW_RING_HP_OUT(x, val)                       \
	out_dword( HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), val)
#define HWIO_REO_R2_REO2FW_RING_HP_OUTM(x, mask, val)                \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2FW_RING_HP_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R2_REO2FW_RING_HP_HEAD_PTR_BMSK                     0x000fffff
#define HWIO_REO_R2_REO2FW_RING_HP_HEAD_PTR_SHFT                            0x0

//// Register REO_R2_REO2FW_RING_TP ////

#define HWIO_REO_R2_REO2FW_RING_TP_ADDR(x)                           (x+0x00003064)
#define HWIO_REO_R2_REO2FW_RING_TP_PHYS(x)                           (x+0x00003064)
#define HWIO_REO_R2_REO2FW_RING_TP_RMSK                              0x000fffff
#define HWIO_REO_R2_REO2FW_RING_TP_SHFT                                       0
#define HWIO_REO_R2_REO2FW_RING_TP_IN(x)                             \
	in_dword_masked ( HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), HWIO_REO_R2_REO2FW_RING_TP_RMSK)
#define HWIO_REO_R2_REO2FW_RING_TP_INM(x, mask)                      \
	in_dword_masked ( HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), mask) 
#define HWIO_REO_R2_REO2FW_RING_TP_OUT(x, val)                       \
	out_dword( HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), val)
#define HWIO_REO_R2_REO2FW_RING_TP_OUTM(x, mask, val)                \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2FW_RING_TP_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R2_REO2FW_RING_TP_TAIL_PTR_BMSK                     0x000fffff
#define HWIO_REO_R2_REO2FW_RING_TP_TAIL_PTR_SHFT                            0x0

//// Register REO_R2_REO_RELEASE_RING_HP ////

#define HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x)                      (x+0x00003068)
#define HWIO_REO_R2_REO_RELEASE_RING_HP_PHYS(x)                      (x+0x00003068)
#define HWIO_REO_R2_REO_RELEASE_RING_HP_RMSK                         0x0000ffff
#define HWIO_REO_R2_REO_RELEASE_RING_HP_SHFT                                  0
#define HWIO_REO_R2_REO_RELEASE_RING_HP_IN(x)                        \
	in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), HWIO_REO_R2_REO_RELEASE_RING_HP_RMSK)
#define HWIO_REO_R2_REO_RELEASE_RING_HP_INM(x, mask)                 \
	in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), mask) 
#define HWIO_REO_R2_REO_RELEASE_RING_HP_OUT(x, val)                  \
	out_dword( HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), val)
#define HWIO_REO_R2_REO_RELEASE_RING_HP_OUTM(x, mask, val)           \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO_RELEASE_RING_HP_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R2_REO_RELEASE_RING_HP_HEAD_PTR_BMSK                0x0000ffff
#define HWIO_REO_R2_REO_RELEASE_RING_HP_HEAD_PTR_SHFT                       0x0

//// Register REO_R2_REO_RELEASE_RING_TP ////

#define HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x)                      (x+0x0000306c)
#define HWIO_REO_R2_REO_RELEASE_RING_TP_PHYS(x)                      (x+0x0000306c)
#define HWIO_REO_R2_REO_RELEASE_RING_TP_RMSK                         0x0000ffff
#define HWIO_REO_R2_REO_RELEASE_RING_TP_SHFT                                  0
#define HWIO_REO_R2_REO_RELEASE_RING_TP_IN(x)                        \
	in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), HWIO_REO_R2_REO_RELEASE_RING_TP_RMSK)
#define HWIO_REO_R2_REO_RELEASE_RING_TP_INM(x, mask)                 \
	in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), mask) 
#define HWIO_REO_R2_REO_RELEASE_RING_TP_OUT(x, val)                  \
	out_dword( HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), val)
#define HWIO_REO_R2_REO_RELEASE_RING_TP_OUTM(x, mask, val)           \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO_RELEASE_RING_TP_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R2_REO_RELEASE_RING_TP_TAIL_PTR_BMSK                0x0000ffff
#define HWIO_REO_R2_REO_RELEASE_RING_TP_TAIL_PTR_SHFT                       0x0

//// Register REO_R2_REO_STATUS_RING_HP ////

#define HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x)                       (x+0x00003070)
#define HWIO_REO_R2_REO_STATUS_RING_HP_PHYS(x)                       (x+0x00003070)
#define HWIO_REO_R2_REO_STATUS_RING_HP_RMSK                          0x0000ffff
#define HWIO_REO_R2_REO_STATUS_RING_HP_SHFT                                   0
#define HWIO_REO_R2_REO_STATUS_RING_HP_IN(x)                         \
	in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), HWIO_REO_R2_REO_STATUS_RING_HP_RMSK)
#define HWIO_REO_R2_REO_STATUS_RING_HP_INM(x, mask)                  \
	in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), mask) 
#define HWIO_REO_R2_REO_STATUS_RING_HP_OUT(x, val)                   \
	out_dword( HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), val)
#define HWIO_REO_R2_REO_STATUS_RING_HP_OUTM(x, mask, val)            \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO_STATUS_RING_HP_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R2_REO_STATUS_RING_HP_HEAD_PTR_BMSK                 0x0000ffff
#define HWIO_REO_R2_REO_STATUS_RING_HP_HEAD_PTR_SHFT                        0x0

//// Register REO_R2_REO_STATUS_RING_TP ////

#define HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x)                       (x+0x00003074)
#define HWIO_REO_R2_REO_STATUS_RING_TP_PHYS(x)                       (x+0x00003074)
#define HWIO_REO_R2_REO_STATUS_RING_TP_RMSK                          0x0000ffff
#define HWIO_REO_R2_REO_STATUS_RING_TP_SHFT                                   0
#define HWIO_REO_R2_REO_STATUS_RING_TP_IN(x)                         \
	in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), HWIO_REO_R2_REO_STATUS_RING_TP_RMSK)
#define HWIO_REO_R2_REO_STATUS_RING_TP_INM(x, mask)                  \
	in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), mask) 
#define HWIO_REO_R2_REO_STATUS_RING_TP_OUT(x, val)                   \
	out_dword( HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), val)
#define HWIO_REO_R2_REO_STATUS_RING_TP_OUTM(x, mask, val)            \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO_STATUS_RING_TP_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_REO_R2_REO_STATUS_RING_TP_TAIL_PTR_BMSK                 0x0000ffff
#define HWIO_REO_R2_REO_STATUS_RING_TP_TAIL_PTR_SHFT                        0x0


#endif