8f2ef48ebc
Bring in V2 HW header files for peach, also cleanup the header files 1. Remove comments; 2. Add appropriate copyright header; 3. Remove references to HW sensitive IP (structs, macros and etc). Change-Id: Iaa4db993ce08d04e5e571c740a4f30ff42890474 CRs-Fixed: 3691183
296 regels
21 KiB
C
296 regels
21 KiB
C
/*
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* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _TX_MPDU_START_H_
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#define _TX_MPDU_START_H_
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#define NUM_OF_DWORDS_TX_MPDU_START 9
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struct tx_mpdu_start {
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#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
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uint32_t mpdu_length : 14,
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frame_not_from_tqm : 1,
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vht_control_present : 1,
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mpdu_header_length : 8,
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retry_count : 7,
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wds : 1;
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uint32_t pn_31_0 : 32;
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uint32_t pn_47_32 : 16,
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mpdu_sequence_number : 12,
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raw_already_encrypted : 1,
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frame_type : 2,
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txdma_dropped_mpdu_warning : 1;
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uint32_t iv_byte_0 : 8,
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iv_byte_1 : 8,
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iv_byte_2 : 8,
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iv_byte_3 : 8;
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uint32_t iv_byte_4 : 8,
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iv_byte_5 : 8,
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iv_byte_6 : 8,
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iv_byte_7 : 8;
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uint32_t iv_byte_8 : 8,
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iv_byte_9 : 8,
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iv_byte_10 : 8,
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iv_byte_11 : 8;
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uint32_t iv_byte_12 : 8,
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iv_byte_13 : 8,
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iv_byte_14 : 8,
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iv_byte_15 : 8;
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uint32_t iv_byte_16 : 8,
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iv_byte_17 : 8,
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iv_len : 5,
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icv_len : 5,
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vht_control_offset : 6;
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uint32_t mpdu_type : 1,
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transmit_bw_restriction : 1,
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allowed_transmit_bw : 4,
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tx_notify_frame : 3,
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reserved_8a : 23;
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#else
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uint32_t wds : 1,
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retry_count : 7,
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mpdu_header_length : 8,
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vht_control_present : 1,
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frame_not_from_tqm : 1,
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mpdu_length : 14;
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uint32_t pn_31_0 : 32;
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uint32_t txdma_dropped_mpdu_warning : 1,
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frame_type : 2,
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raw_already_encrypted : 1,
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mpdu_sequence_number : 12,
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pn_47_32 : 16;
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uint32_t iv_byte_3 : 8,
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iv_byte_2 : 8,
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iv_byte_1 : 8,
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iv_byte_0 : 8;
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uint32_t iv_byte_7 : 8,
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iv_byte_6 : 8,
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iv_byte_5 : 8,
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iv_byte_4 : 8;
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uint32_t iv_byte_11 : 8,
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iv_byte_10 : 8,
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iv_byte_9 : 8,
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iv_byte_8 : 8;
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uint32_t iv_byte_15 : 8,
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iv_byte_14 : 8,
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iv_byte_13 : 8,
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iv_byte_12 : 8;
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uint32_t vht_control_offset : 6,
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icv_len : 5,
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iv_len : 5,
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iv_byte_17 : 8,
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iv_byte_16 : 8;
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uint32_t reserved_8a : 23,
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tx_notify_frame : 3,
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allowed_transmit_bw : 4,
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transmit_bw_restriction : 1,
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mpdu_type : 1;
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#endif
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};
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#define TX_MPDU_START_MPDU_LENGTH_OFFSET 0x00000000
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#define TX_MPDU_START_MPDU_LENGTH_LSB 0
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#define TX_MPDU_START_MPDU_LENGTH_MSB 13
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#define TX_MPDU_START_MPDU_LENGTH_MASK 0x00003fff
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#define TX_MPDU_START_FRAME_NOT_FROM_TQM_OFFSET 0x00000000
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#define TX_MPDU_START_FRAME_NOT_FROM_TQM_LSB 14
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#define TX_MPDU_START_FRAME_NOT_FROM_TQM_MSB 14
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#define TX_MPDU_START_FRAME_NOT_FROM_TQM_MASK 0x00004000
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#define TX_MPDU_START_VHT_CONTROL_PRESENT_OFFSET 0x00000000
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#define TX_MPDU_START_VHT_CONTROL_PRESENT_LSB 15
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#define TX_MPDU_START_VHT_CONTROL_PRESENT_MSB 15
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#define TX_MPDU_START_VHT_CONTROL_PRESENT_MASK 0x00008000
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#define TX_MPDU_START_MPDU_HEADER_LENGTH_OFFSET 0x00000000
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#define TX_MPDU_START_MPDU_HEADER_LENGTH_LSB 16
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#define TX_MPDU_START_MPDU_HEADER_LENGTH_MSB 23
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#define TX_MPDU_START_MPDU_HEADER_LENGTH_MASK 0x00ff0000
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#define TX_MPDU_START_RETRY_COUNT_OFFSET 0x00000000
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#define TX_MPDU_START_RETRY_COUNT_LSB 24
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#define TX_MPDU_START_RETRY_COUNT_MSB 30
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#define TX_MPDU_START_RETRY_COUNT_MASK 0x7f000000
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#define TX_MPDU_START_WDS_OFFSET 0x00000000
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#define TX_MPDU_START_WDS_LSB 31
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#define TX_MPDU_START_WDS_MSB 31
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#define TX_MPDU_START_WDS_MASK 0x80000000
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#define TX_MPDU_START_PN_31_0_OFFSET 0x00000004
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#define TX_MPDU_START_PN_31_0_LSB 0
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#define TX_MPDU_START_PN_31_0_MSB 31
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#define TX_MPDU_START_PN_31_0_MASK 0xffffffff
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#define TX_MPDU_START_PN_47_32_OFFSET 0x00000008
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#define TX_MPDU_START_PN_47_32_LSB 0
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#define TX_MPDU_START_PN_47_32_MSB 15
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#define TX_MPDU_START_PN_47_32_MASK 0x0000ffff
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#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008
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#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_LSB 16
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#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MSB 27
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#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MASK 0x0fff0000
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#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_OFFSET 0x00000008
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#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_LSB 28
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#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MSB 28
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#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MASK 0x10000000
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#define TX_MPDU_START_FRAME_TYPE_OFFSET 0x00000008
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#define TX_MPDU_START_FRAME_TYPE_LSB 29
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#define TX_MPDU_START_FRAME_TYPE_MSB 30
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#define TX_MPDU_START_FRAME_TYPE_MASK 0x60000000
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#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_OFFSET 0x00000008
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#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_LSB 31
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#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MSB 31
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#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MASK 0x80000000
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#define TX_MPDU_START_IV_BYTE_0_OFFSET 0x0000000c
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#define TX_MPDU_START_IV_BYTE_0_LSB 0
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#define TX_MPDU_START_IV_BYTE_0_MSB 7
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#define TX_MPDU_START_IV_BYTE_0_MASK 0x000000ff
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#define TX_MPDU_START_IV_BYTE_1_OFFSET 0x0000000c
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#define TX_MPDU_START_IV_BYTE_1_LSB 8
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#define TX_MPDU_START_IV_BYTE_1_MSB 15
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#define TX_MPDU_START_IV_BYTE_1_MASK 0x0000ff00
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#define TX_MPDU_START_IV_BYTE_2_OFFSET 0x0000000c
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#define TX_MPDU_START_IV_BYTE_2_LSB 16
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#define TX_MPDU_START_IV_BYTE_2_MSB 23
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#define TX_MPDU_START_IV_BYTE_2_MASK 0x00ff0000
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#define TX_MPDU_START_IV_BYTE_3_OFFSET 0x0000000c
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#define TX_MPDU_START_IV_BYTE_3_LSB 24
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#define TX_MPDU_START_IV_BYTE_3_MSB 31
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#define TX_MPDU_START_IV_BYTE_3_MASK 0xff000000
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#define TX_MPDU_START_IV_BYTE_4_OFFSET 0x00000010
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#define TX_MPDU_START_IV_BYTE_4_LSB 0
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#define TX_MPDU_START_IV_BYTE_4_MSB 7
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#define TX_MPDU_START_IV_BYTE_4_MASK 0x000000ff
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#define TX_MPDU_START_IV_BYTE_5_OFFSET 0x00000010
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#define TX_MPDU_START_IV_BYTE_5_LSB 8
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#define TX_MPDU_START_IV_BYTE_5_MSB 15
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#define TX_MPDU_START_IV_BYTE_5_MASK 0x0000ff00
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#define TX_MPDU_START_IV_BYTE_6_OFFSET 0x00000010
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#define TX_MPDU_START_IV_BYTE_6_LSB 16
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#define TX_MPDU_START_IV_BYTE_6_MSB 23
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#define TX_MPDU_START_IV_BYTE_6_MASK 0x00ff0000
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#define TX_MPDU_START_IV_BYTE_7_OFFSET 0x00000010
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#define TX_MPDU_START_IV_BYTE_7_LSB 24
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#define TX_MPDU_START_IV_BYTE_7_MSB 31
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#define TX_MPDU_START_IV_BYTE_7_MASK 0xff000000
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#define TX_MPDU_START_IV_BYTE_8_OFFSET 0x00000014
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#define TX_MPDU_START_IV_BYTE_8_LSB 0
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#define TX_MPDU_START_IV_BYTE_8_MSB 7
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#define TX_MPDU_START_IV_BYTE_8_MASK 0x000000ff
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#define TX_MPDU_START_IV_BYTE_9_OFFSET 0x00000014
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#define TX_MPDU_START_IV_BYTE_9_LSB 8
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#define TX_MPDU_START_IV_BYTE_9_MSB 15
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#define TX_MPDU_START_IV_BYTE_9_MASK 0x0000ff00
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#define TX_MPDU_START_IV_BYTE_10_OFFSET 0x00000014
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#define TX_MPDU_START_IV_BYTE_10_LSB 16
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#define TX_MPDU_START_IV_BYTE_10_MSB 23
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#define TX_MPDU_START_IV_BYTE_10_MASK 0x00ff0000
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#define TX_MPDU_START_IV_BYTE_11_OFFSET 0x00000014
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#define TX_MPDU_START_IV_BYTE_11_LSB 24
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#define TX_MPDU_START_IV_BYTE_11_MSB 31
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#define TX_MPDU_START_IV_BYTE_11_MASK 0xff000000
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#define TX_MPDU_START_IV_BYTE_12_OFFSET 0x00000018
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#define TX_MPDU_START_IV_BYTE_12_LSB 0
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#define TX_MPDU_START_IV_BYTE_12_MSB 7
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#define TX_MPDU_START_IV_BYTE_12_MASK 0x000000ff
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#define TX_MPDU_START_IV_BYTE_13_OFFSET 0x00000018
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#define TX_MPDU_START_IV_BYTE_13_LSB 8
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#define TX_MPDU_START_IV_BYTE_13_MSB 15
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#define TX_MPDU_START_IV_BYTE_13_MASK 0x0000ff00
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#define TX_MPDU_START_IV_BYTE_14_OFFSET 0x00000018
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#define TX_MPDU_START_IV_BYTE_14_LSB 16
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#define TX_MPDU_START_IV_BYTE_14_MSB 23
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#define TX_MPDU_START_IV_BYTE_14_MASK 0x00ff0000
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#define TX_MPDU_START_IV_BYTE_15_OFFSET 0x00000018
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#define TX_MPDU_START_IV_BYTE_15_LSB 24
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#define TX_MPDU_START_IV_BYTE_15_MSB 31
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#define TX_MPDU_START_IV_BYTE_15_MASK 0xff000000
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#define TX_MPDU_START_IV_BYTE_16_OFFSET 0x0000001c
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#define TX_MPDU_START_IV_BYTE_16_LSB 0
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#define TX_MPDU_START_IV_BYTE_16_MSB 7
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#define TX_MPDU_START_IV_BYTE_16_MASK 0x000000ff
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#define TX_MPDU_START_IV_BYTE_17_OFFSET 0x0000001c
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#define TX_MPDU_START_IV_BYTE_17_LSB 8
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#define TX_MPDU_START_IV_BYTE_17_MSB 15
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#define TX_MPDU_START_IV_BYTE_17_MASK 0x0000ff00
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#define TX_MPDU_START_IV_LEN_OFFSET 0x0000001c
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#define TX_MPDU_START_IV_LEN_LSB 16
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#define TX_MPDU_START_IV_LEN_MSB 20
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#define TX_MPDU_START_IV_LEN_MASK 0x001f0000
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#define TX_MPDU_START_ICV_LEN_OFFSET 0x0000001c
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#define TX_MPDU_START_ICV_LEN_LSB 21
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#define TX_MPDU_START_ICV_LEN_MSB 25
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#define TX_MPDU_START_ICV_LEN_MASK 0x03e00000
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#define TX_MPDU_START_VHT_CONTROL_OFFSET_OFFSET 0x0000001c
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#define TX_MPDU_START_VHT_CONTROL_OFFSET_LSB 26
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#define TX_MPDU_START_VHT_CONTROL_OFFSET_MSB 31
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#define TX_MPDU_START_VHT_CONTROL_OFFSET_MASK 0xfc000000
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#define TX_MPDU_START_MPDU_TYPE_OFFSET 0x00000020
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#define TX_MPDU_START_MPDU_TYPE_LSB 0
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#define TX_MPDU_START_MPDU_TYPE_MSB 0
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#define TX_MPDU_START_MPDU_TYPE_MASK 0x00000001
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#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_OFFSET 0x00000020
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#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_LSB 1
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#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MSB 1
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#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MASK 0x00000002
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#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_OFFSET 0x00000020
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#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_LSB 2
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#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MSB 5
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#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MASK 0x0000003c
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#define TX_MPDU_START_TX_NOTIFY_FRAME_OFFSET 0x00000020
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#define TX_MPDU_START_TX_NOTIFY_FRAME_LSB 6
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#define TX_MPDU_START_TX_NOTIFY_FRAME_MSB 8
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#define TX_MPDU_START_TX_NOTIFY_FRAME_MASK 0x000001c0
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#define TX_MPDU_START_RESERVED_8A_OFFSET 0x00000020
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#define TX_MPDU_START_RESERVED_8A_LSB 9
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#define TX_MPDU_START_RESERVED_8A_MSB 31
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#define TX_MPDU_START_RESERVED_8A_MASK 0xfffffe00
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#endif
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