8f2ef48ebc
Bring in V2 HW header files for peach, also cleanup the header files 1. Remove comments; 2. Add appropriate copyright header; 3. Remove references to HW sensitive IP (structs, macros and etc). Change-Id: Iaa4db993ce08d04e5e571c740a4f30ff42890474 CRs-Fixed: 3691183
512 rader
37 KiB
C
512 rader
37 KiB
C
/*
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* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _TX_FES_SETUP_H_
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#define _TX_FES_SETUP_H_
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#define NUM_OF_DWORDS_TX_FES_SETUP 10
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struct tx_fes_setup {
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#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
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uint32_t schedule_id : 32;
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uint32_t fes_in_11ax_trigger_response_config : 1,
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bo_based_tid_aggregation_limit : 4,
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__reserved_g_0005 : 1,
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expect_i2r_lmr : 1,
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transmit_start_reason : 3,
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use_alt_power_sr : 1,
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static_2_pwr_mode_status : 1,
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obss_srg_opport_transmit_status : 1,
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srp_based_transmit_status : 1,
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obss_pd_based_transmit_status : 1,
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puncture_from_all_allowed_modes : 1,
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schedule_cmd_ring_id : 5,
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fes_control_mode : 2,
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number_of_users : 6,
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mu_type : 1,
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ofdma_triggered_response : 1,
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response_to_response_cmd : 1;
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uint32_t schedule_try : 4,
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ndp_frame : 2,
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txbf : 1,
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allow_txop_exceed_in_1st_pkt : 1,
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ignore_bw_available : 1,
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ignore_tbtt : 1,
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static_bandwidth : 3,
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set_txop_duration_all_ones : 1,
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transmission_contains_mu_rts : 1,
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bw_restricted_frames_embedded : 1,
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ast_index : 16;
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uint32_t cv_id : 8,
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trigger_resp_txpdu_ppdu_boundary : 2,
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rxpcu_setup_complete_present : 1,
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rbo_must_have_data_user_limit : 4,
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mu_ndp : 1,
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bf_type : 2,
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cbf_nc_index_mask : 1,
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cbf_nc_index : 3,
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cbf_nr_index_mask : 1,
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cbf_nr_index : 3,
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secure___reserved_g_0005_ista : 1,
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ndpa : 1,
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wait_sifs : 2,
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cbf_feedback_type_mask : 1,
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cbf_feedback_type : 1;
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uint32_t cbf_sounding_token : 6,
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cbf_sounding_token_mask : 1,
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cbf_bw_mask : 1,
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cbf_bw : 3,
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use_static_bw : 1,
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coex_nack_count : 5,
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sch_tx_burst_ongoing : 1,
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gen_tqm_update_mpdu_count_tlv : 1,
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rts_tx_over___reserved_g_0016 : 1,
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reserved_4a : 3,
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optimal_bw_retry_count : 4,
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fes_continuation_ratio_threshold : 5;
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uint32_t transmit_cca_bitmap : 32;
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uint32_t tb___reserved_g_0005 : 1,
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__reserved_g_0005_trigger_subtype : 4,
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min_cts2self_count : 4,
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max_cts2self_count : 4,
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wifi_radar_enable : 1,
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reserved_6a : 1,
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wait_for_chksum_done : 1,
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reserved_6b : 15,
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enable_hw_qos_null : 1;
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uint32_t monitor_override_sta_31_0 : 32;
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uint32_t monitor_override_sta_36_32 : 5,
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enable_qos_null_switch_for_eosp : 1,
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reserved_8a : 26;
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uint32_t fw2sw_info : 32;
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#else
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uint32_t schedule_id : 32;
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uint32_t response_to_response_cmd : 1,
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ofdma_triggered_response : 1,
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mu_type : 1,
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number_of_users : 6,
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fes_control_mode : 2,
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schedule_cmd_ring_id : 5,
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puncture_from_all_allowed_modes : 1,
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obss_pd_based_transmit_status : 1,
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srp_based_transmit_status : 1,
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obss_srg_opport_transmit_status : 1,
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static_2_pwr_mode_status : 1,
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use_alt_power_sr : 1,
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transmit_start_reason : 3,
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expect_i2r_lmr : 1,
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__reserved_g_0005 : 1,
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bo_based_tid_aggregation_limit : 4,
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fes_in_11ax_trigger_response_config : 1;
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uint32_t ast_index : 16,
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bw_restricted_frames_embedded : 1,
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transmission_contains_mu_rts : 1,
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set_txop_duration_all_ones : 1,
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static_bandwidth : 3,
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ignore_tbtt : 1,
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ignore_bw_available : 1,
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allow_txop_exceed_in_1st_pkt : 1,
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txbf : 1,
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ndp_frame : 2,
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schedule_try : 4;
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uint32_t cbf_feedback_type : 1,
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cbf_feedback_type_mask : 1,
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wait_sifs : 2,
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ndpa : 1,
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secure___reserved_g_0005_ista : 1,
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cbf_nr_index : 3,
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cbf_nr_index_mask : 1,
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cbf_nc_index : 3,
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cbf_nc_index_mask : 1,
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bf_type : 2,
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mu_ndp : 1,
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rbo_must_have_data_user_limit : 4,
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rxpcu_setup_complete_present : 1,
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trigger_resp_txpdu_ppdu_boundary : 2,
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cv_id : 8;
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uint32_t fes_continuation_ratio_threshold : 5,
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optimal_bw_retry_count : 4,
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reserved_4a : 3,
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rts_tx_over___reserved_g_0016 : 1,
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gen_tqm_update_mpdu_count_tlv : 1,
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sch_tx_burst_ongoing : 1,
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coex_nack_count : 5,
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use_static_bw : 1,
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cbf_bw : 3,
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cbf_bw_mask : 1,
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cbf_sounding_token_mask : 1,
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cbf_sounding_token : 6;
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uint32_t transmit_cca_bitmap : 32;
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uint32_t enable_hw_qos_null : 1,
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reserved_6b : 15,
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wait_for_chksum_done : 1,
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reserved_6a : 1,
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wifi_radar_enable : 1,
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max_cts2self_count : 4,
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min_cts2self_count : 4,
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__reserved_g_0005_trigger_subtype : 4,
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tb___reserved_g_0005 : 1;
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uint32_t monitor_override_sta_31_0 : 32;
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uint32_t reserved_8a : 26,
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enable_qos_null_switch_for_eosp : 1,
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monitor_override_sta_36_32 : 5;
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uint32_t fw2sw_info : 32;
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#endif
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};
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#define TX_FES_SETUP_SCHEDULE_ID_OFFSET 0x00000000
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#define TX_FES_SETUP_SCHEDULE_ID_LSB 0
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#define TX_FES_SETUP_SCHEDULE_ID_MSB 31
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#define TX_FES_SETUP_SCHEDULE_ID_MASK 0xffffffff
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#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_OFFSET 0x00000004
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#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_LSB 0
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#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MSB 0
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#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MASK 0x00000001
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#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_OFFSET 0x00000004
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#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_LSB 1
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#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MSB 4
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#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MASK 0x0000001e
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#define TX_FES_SETUP_EXPECT_I2R_LMR_OFFSET 0x00000004
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#define TX_FES_SETUP_EXPECT_I2R_LMR_LSB 6
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#define TX_FES_SETUP_EXPECT_I2R_LMR_MSB 6
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#define TX_FES_SETUP_EXPECT_I2R_LMR_MASK 0x00000040
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#define TX_FES_SETUP_TRANSMIT_START_REASON_OFFSET 0x00000004
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#define TX_FES_SETUP_TRANSMIT_START_REASON_LSB 7
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#define TX_FES_SETUP_TRANSMIT_START_REASON_MSB 9
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#define TX_FES_SETUP_TRANSMIT_START_REASON_MASK 0x00000380
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#define TX_FES_SETUP_USE_ALT_POWER_SR_OFFSET 0x00000004
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#define TX_FES_SETUP_USE_ALT_POWER_SR_LSB 10
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#define TX_FES_SETUP_USE_ALT_POWER_SR_MSB 10
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#define TX_FES_SETUP_USE_ALT_POWER_SR_MASK 0x00000400
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#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_OFFSET 0x00000004
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#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_LSB 11
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#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MSB 11
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#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MASK 0x00000800
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#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_OFFSET 0x00000004
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#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_LSB 12
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#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MSB 12
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#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MASK 0x00001000
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#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_OFFSET 0x00000004
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#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_LSB 13
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#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MSB 13
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#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MASK 0x00002000
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#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_OFFSET 0x00000004
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#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_LSB 14
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#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MSB 14
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#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MASK 0x00004000
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#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_OFFSET 0x00000004
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#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_LSB 15
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#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MSB 15
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#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MASK 0x00008000
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#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_OFFSET 0x00000004
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#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_LSB 16
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#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MSB 20
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#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MASK 0x001f0000
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#define TX_FES_SETUP_FES_CONTROL_MODE_OFFSET 0x00000004
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#define TX_FES_SETUP_FES_CONTROL_MODE_LSB 21
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#define TX_FES_SETUP_FES_CONTROL_MODE_MSB 22
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#define TX_FES_SETUP_FES_CONTROL_MODE_MASK 0x00600000
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#define TX_FES_SETUP_NUMBER_OF_USERS_OFFSET 0x00000004
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#define TX_FES_SETUP_NUMBER_OF_USERS_LSB 23
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#define TX_FES_SETUP_NUMBER_OF_USERS_MSB 28
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#define TX_FES_SETUP_NUMBER_OF_USERS_MASK 0x1f800000
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#define TX_FES_SETUP_MU_TYPE_OFFSET 0x00000004
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#define TX_FES_SETUP_MU_TYPE_LSB 29
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#define TX_FES_SETUP_MU_TYPE_MSB 29
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#define TX_FES_SETUP_MU_TYPE_MASK 0x20000000
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#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_OFFSET 0x00000004
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#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_LSB 30
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#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MSB 30
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#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MASK 0x40000000
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#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_OFFSET 0x00000004
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#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_LSB 31
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#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MSB 31
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#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MASK 0x80000000
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#define TX_FES_SETUP_SCHEDULE_TRY_OFFSET 0x00000008
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#define TX_FES_SETUP_SCHEDULE_TRY_LSB 0
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#define TX_FES_SETUP_SCHEDULE_TRY_MSB 3
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#define TX_FES_SETUP_SCHEDULE_TRY_MASK 0x0000000f
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#define TX_FES_SETUP_NDP_FRAME_OFFSET 0x00000008
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#define TX_FES_SETUP_NDP_FRAME_LSB 4
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#define TX_FES_SETUP_NDP_FRAME_MSB 5
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#define TX_FES_SETUP_NDP_FRAME_MASK 0x00000030
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#define TX_FES_SETUP_TXBF_OFFSET 0x00000008
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#define TX_FES_SETUP_TXBF_LSB 6
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#define TX_FES_SETUP_TXBF_MSB 6
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#define TX_FES_SETUP_TXBF_MASK 0x00000040
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#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_OFFSET 0x00000008
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#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_LSB 7
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#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MSB 7
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#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MASK 0x00000080
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#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_OFFSET 0x00000008
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#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_LSB 8
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#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MSB 8
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#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MASK 0x00000100
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#define TX_FES_SETUP_IGNORE_TBTT_OFFSET 0x00000008
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#define TX_FES_SETUP_IGNORE_TBTT_LSB 9
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#define TX_FES_SETUP_IGNORE_TBTT_MSB 9
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#define TX_FES_SETUP_IGNORE_TBTT_MASK 0x00000200
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#define TX_FES_SETUP_STATIC_BANDWIDTH_OFFSET 0x00000008
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#define TX_FES_SETUP_STATIC_BANDWIDTH_LSB 10
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#define TX_FES_SETUP_STATIC_BANDWIDTH_MSB 12
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#define TX_FES_SETUP_STATIC_BANDWIDTH_MASK 0x00001c00
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#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_OFFSET 0x00000008
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#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_LSB 13
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#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MSB 13
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#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MASK 0x00002000
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#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_OFFSET 0x00000008
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#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_LSB 14
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#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MSB 14
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#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MASK 0x00004000
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#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_OFFSET 0x00000008
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#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_LSB 15
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#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MSB 15
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#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MASK 0x00008000
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#define TX_FES_SETUP_AST_INDEX_OFFSET 0x00000008
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#define TX_FES_SETUP_AST_INDEX_LSB 16
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#define TX_FES_SETUP_AST_INDEX_MSB 31
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#define TX_FES_SETUP_AST_INDEX_MASK 0xffff0000
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#define TX_FES_SETUP_CV_ID_OFFSET 0x0000000c
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#define TX_FES_SETUP_CV_ID_LSB 0
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#define TX_FES_SETUP_CV_ID_MSB 7
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#define TX_FES_SETUP_CV_ID_MASK 0x000000ff
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#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_OFFSET 0x0000000c
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#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_LSB 8
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#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MSB 9
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#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MASK 0x00000300
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#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_OFFSET 0x0000000c
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#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_LSB 10
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#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MSB 10
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#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MASK 0x00000400
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#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_OFFSET 0x0000000c
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#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_LSB 11
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#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MSB 14
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#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MASK 0x00007800
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#define TX_FES_SETUP_MU_NDP_OFFSET 0x0000000c
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#define TX_FES_SETUP_MU_NDP_LSB 15
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#define TX_FES_SETUP_MU_NDP_MSB 15
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#define TX_FES_SETUP_MU_NDP_MASK 0x00008000
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#define TX_FES_SETUP_BF_TYPE_OFFSET 0x0000000c
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#define TX_FES_SETUP_BF_TYPE_LSB 16
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#define TX_FES_SETUP_BF_TYPE_MSB 17
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#define TX_FES_SETUP_BF_TYPE_MASK 0x00030000
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#define TX_FES_SETUP_CBF_NC_INDEX_MASK_OFFSET 0x0000000c
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#define TX_FES_SETUP_CBF_NC_INDEX_MASK_LSB 18
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#define TX_FES_SETUP_CBF_NC_INDEX_MASK_MSB 18
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#define TX_FES_SETUP_CBF_NC_INDEX_MASK_MASK 0x00040000
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#define TX_FES_SETUP_CBF_NC_INDEX_OFFSET 0x0000000c
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#define TX_FES_SETUP_CBF_NC_INDEX_LSB 19
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#define TX_FES_SETUP_CBF_NC_INDEX_MSB 21
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#define TX_FES_SETUP_CBF_NC_INDEX_MASK 0x00380000
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#define TX_FES_SETUP_CBF_NR_INDEX_MASK_OFFSET 0x0000000c
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#define TX_FES_SETUP_CBF_NR_INDEX_MASK_LSB 22
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#define TX_FES_SETUP_CBF_NR_INDEX_MASK_MSB 22
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#define TX_FES_SETUP_CBF_NR_INDEX_MASK_MASK 0x00400000
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#define TX_FES_SETUP_CBF_NR_INDEX_OFFSET 0x0000000c
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#define TX_FES_SETUP_CBF_NR_INDEX_LSB 23
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#define TX_FES_SETUP_CBF_NR_INDEX_MSB 25
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#define TX_FES_SETUP_CBF_NR_INDEX_MASK 0x03800000
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#define TX_FES_SETUP_SECURE_RANGING_ISTA_OFFSET 0x0000000c
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#define TX_FES_SETUP_SECURE_RANGING_ISTA_LSB 26
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#define TX_FES_SETUP_SECURE_RANGING_ISTA_MSB 26
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#define TX_FES_SETUP_SECURE_RANGING_ISTA_MASK 0x04000000
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#define TX_FES_SETUP_NDPA_OFFSET 0x0000000c
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#define TX_FES_SETUP_NDPA_LSB 27
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#define TX_FES_SETUP_NDPA_MSB 27
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#define TX_FES_SETUP_NDPA_MASK 0x08000000
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#define TX_FES_SETUP_WAIT_SIFS_OFFSET 0x0000000c
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#define TX_FES_SETUP_WAIT_SIFS_LSB 28
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#define TX_FES_SETUP_WAIT_SIFS_MSB 29
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#define TX_FES_SETUP_WAIT_SIFS_MASK 0x30000000
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#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_OFFSET 0x0000000c
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#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_LSB 30
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#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MSB 30
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#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MASK 0x40000000
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#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_OFFSET 0x0000000c
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#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_LSB 31
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#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MSB 31
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#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK 0x80000000
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#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_OFFSET 0x00000010
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#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_LSB 0
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#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MSB 5
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#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK 0x0000003f
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#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_OFFSET 0x00000010
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#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_LSB 6
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#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MSB 6
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#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MASK 0x00000040
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#define TX_FES_SETUP_CBF_BW_MASK_OFFSET 0x00000010
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#define TX_FES_SETUP_CBF_BW_MASK_LSB 7
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#define TX_FES_SETUP_CBF_BW_MASK_MSB 7
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#define TX_FES_SETUP_CBF_BW_MASK_MASK 0x00000080
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#define TX_FES_SETUP_CBF_BW_OFFSET 0x00000010
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#define TX_FES_SETUP_CBF_BW_LSB 8
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#define TX_FES_SETUP_CBF_BW_MSB 10
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#define TX_FES_SETUP_CBF_BW_MASK 0x00000700
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#define TX_FES_SETUP_USE_STATIC_BW_OFFSET 0x00000010
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#define TX_FES_SETUP_USE_STATIC_BW_LSB 11
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#define TX_FES_SETUP_USE_STATIC_BW_MSB 11
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#define TX_FES_SETUP_USE_STATIC_BW_MASK 0x00000800
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#define TX_FES_SETUP_COEX_NACK_COUNT_OFFSET 0x00000010
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#define TX_FES_SETUP_COEX_NACK_COUNT_LSB 12
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#define TX_FES_SETUP_COEX_NACK_COUNT_MSB 16
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#define TX_FES_SETUP_COEX_NACK_COUNT_MASK 0x0001f000
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#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_OFFSET 0x00000010
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#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_LSB 17
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#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MSB 17
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#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MASK 0x00020000
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#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_OFFSET 0x00000010
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#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_LSB 18
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#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MSB 18
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#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MASK 0x00040000
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#define TX_FES_SETUP_RESERVED_4A_OFFSET 0x00000010
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#define TX_FES_SETUP_RESERVED_4A_LSB 20
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#define TX_FES_SETUP_RESERVED_4A_MSB 22
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#define TX_FES_SETUP_RESERVED_4A_MASK 0x00700000
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#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_OFFSET 0x00000010
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#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_LSB 23
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#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MSB 26
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#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MASK 0x07800000
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#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_OFFSET 0x00000010
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#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_LSB 27
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#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MSB 31
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#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MASK 0xf8000000
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#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_OFFSET 0x00000014
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#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_LSB 0
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#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MSB 31
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#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MASK 0xffffffff
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#define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_OFFSET 0x00000018
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#define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_LSB 1
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#define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_MSB 4
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#define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_MASK 0x0000001e
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#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_OFFSET 0x00000018
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#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_LSB 5
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#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MSB 8
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#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MASK 0x000001e0
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#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_OFFSET 0x00000018
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#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_LSB 9
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#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MSB 12
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#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MASK 0x00001e00
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#define TX_FES_SETUP_WIFI_RADAR_ENABLE_OFFSET 0x00000018
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#define TX_FES_SETUP_WIFI_RADAR_ENABLE_LSB 13
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#define TX_FES_SETUP_WIFI_RADAR_ENABLE_MSB 13
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#define TX_FES_SETUP_WIFI_RADAR_ENABLE_MASK 0x00002000
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#define TX_FES_SETUP_RESERVED_6A_OFFSET 0x00000018
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#define TX_FES_SETUP_RESERVED_6A_LSB 14
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#define TX_FES_SETUP_RESERVED_6A_MSB 14
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#define TX_FES_SETUP_RESERVED_6A_MASK 0x00004000
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#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_OFFSET 0x00000018
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#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_LSB 15
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#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_MSB 15
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#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_MASK 0x00008000
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#define TX_FES_SETUP_RESERVED_6B_OFFSET 0x00000018
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#define TX_FES_SETUP_RESERVED_6B_LSB 16
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#define TX_FES_SETUP_RESERVED_6B_MSB 30
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#define TX_FES_SETUP_RESERVED_6B_MASK 0x7fff0000
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#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_OFFSET 0x00000018
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#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_LSB 31
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#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_MSB 31
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#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_MASK 0x80000000
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#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_OFFSET 0x0000001c
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#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_LSB 0
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#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MSB 31
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#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MASK 0xffffffff
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#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_OFFSET 0x00000020
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#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_LSB 0
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#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MSB 4
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#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MASK 0x0000001f
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#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_OFFSET 0x00000020
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#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_LSB 5
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#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_MSB 5
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#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_MASK 0x00000020
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#define TX_FES_SETUP_RESERVED_8A_OFFSET 0x00000020
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#define TX_FES_SETUP_RESERVED_8A_LSB 6
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#define TX_FES_SETUP_RESERVED_8A_MSB 31
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#define TX_FES_SETUP_RESERVED_8A_MASK 0xffffffc0
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#define TX_FES_SETUP_FW2SW_INFO_OFFSET 0x00000024
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#define TX_FES_SETUP_FW2SW_INFO_LSB 0
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#define TX_FES_SETUP_FW2SW_INFO_MSB 31
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#define TX_FES_SETUP_FW2SW_INFO_MASK 0xffffffff
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#endif
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