2d29d9afc7
Add HW header files to bring-in support for Peach WIFI. Change-Id: I73ee0a2c4f22a90013b441ecd5e666d673d77ae0 CRs-Fixed: 3580269
290 lines
20 KiB
C
290 lines
20 KiB
C
/*
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _TX_PEER_ENTRY_H_
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#define _TX_PEER_ENTRY_H_
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#define NUM_OF_DWORDS_TX_PEER_ENTRY 18
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struct tx_peer_entry {
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#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
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uint32_t mac_addr_a_31_0 : 32;
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uint32_t mac_addr_a_47_32 : 16,
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mac_addr_b_15_0 : 16;
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uint32_t mac_addr_b_47_16 : 32;
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uint32_t use_ad_b : 1,
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strip_insert_vlan_inner : 1,
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strip_insert_vlan_outer : 1,
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vlan_llc_mode : 1,
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key_type : 4,
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a_msdu_wds_ad3_ad4 : 3,
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ignore_hard_filters : 1,
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ignore_soft_filters : 1,
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epd_output : 1,
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wds : 1,
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insert_or_strip : 1,
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sw_filter_id : 16;
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uint32_t temporal_key_31_0 : 32;
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uint32_t temporal_key_63_32 : 32;
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uint32_t temporal_key_95_64 : 32;
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uint32_t temporal_key_127_96 : 32;
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uint32_t temporal_key_159_128 : 32;
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uint32_t temporal_key_191_160 : 32;
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uint32_t temporal_key_223_192 : 32;
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uint32_t temporal_key_255_224 : 32;
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uint32_t sta_partial_aid : 11,
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transmit_vif : 4,
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block_this_user : 1,
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mesh_amsdu_mode : 2,
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use_qos_alt_mute_mask : 1,
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dl_ul_direction : 1,
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reserved_12 : 12;
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uint32_t insert_vlan_outer_tci : 16,
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insert_vlan_inner_tci : 16;
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uint32_t __reserved_g_0007 : 32;
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uint32_t __reserved_g_0008 : 16,
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__reserved_g_0009 : 16;
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uint32_t __reserved_g_0010 : 32;
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uint32_t multi_link_addr_crypto_enable : 1,
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reserved_17a : 15,
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sw_peer_id : 16;
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#else
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uint32_t mac_addr_a_31_0 : 32;
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uint32_t mac_addr_b_15_0 : 16,
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mac_addr_a_47_32 : 16;
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uint32_t mac_addr_b_47_16 : 32;
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uint32_t sw_filter_id : 16,
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insert_or_strip : 1,
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wds : 1,
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epd_output : 1,
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ignore_soft_filters : 1,
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ignore_hard_filters : 1,
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a_msdu_wds_ad3_ad4 : 3,
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key_type : 4,
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vlan_llc_mode : 1,
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strip_insert_vlan_outer : 1,
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strip_insert_vlan_inner : 1,
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use_ad_b : 1;
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uint32_t temporal_key_31_0 : 32;
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uint32_t temporal_key_63_32 : 32;
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uint32_t temporal_key_95_64 : 32;
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uint32_t temporal_key_127_96 : 32;
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uint32_t temporal_key_159_128 : 32;
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uint32_t temporal_key_191_160 : 32;
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uint32_t temporal_key_223_192 : 32;
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uint32_t temporal_key_255_224 : 32;
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uint32_t reserved_12 : 12,
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dl_ul_direction : 1,
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use_qos_alt_mute_mask : 1,
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mesh_amsdu_mode : 2,
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block_this_user : 1,
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transmit_vif : 4,
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sta_partial_aid : 11;
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uint32_t insert_vlan_inner_tci : 16,
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insert_vlan_outer_tci : 16;
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uint32_t __reserved_g_0007 : 32;
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uint32_t __reserved_g_0009 : 16,
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__reserved_g_0008 : 16;
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uint32_t __reserved_g_0010 : 32;
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uint32_t sw_peer_id : 16,
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reserved_17a : 15,
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multi_link_addr_crypto_enable : 1;
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#endif
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};
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#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_OFFSET 0x00000000
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#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_LSB 0
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#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MSB 31
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#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MASK 0xffffffff
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#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_OFFSET 0x00000004
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#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_LSB 0
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#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MSB 15
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#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MASK 0x0000ffff
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#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_OFFSET 0x00000004
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#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_LSB 16
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#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MSB 31
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#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MASK 0xffff0000
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#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_OFFSET 0x00000008
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#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_LSB 0
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#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MSB 31
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#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MASK 0xffffffff
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#define TX_PEER_ENTRY_USE_AD_B_OFFSET 0x0000000c
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#define TX_PEER_ENTRY_USE_AD_B_LSB 0
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#define TX_PEER_ENTRY_USE_AD_B_MSB 0
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#define TX_PEER_ENTRY_USE_AD_B_MASK 0x00000001
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#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_OFFSET 0x0000000c
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#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_LSB 1
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#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MSB 1
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#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MASK 0x00000002
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#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_OFFSET 0x0000000c
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#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_LSB 2
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#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MSB 2
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#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MASK 0x00000004
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#define TX_PEER_ENTRY_VLAN_LLC_MODE_OFFSET 0x0000000c
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#define TX_PEER_ENTRY_VLAN_LLC_MODE_LSB 3
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#define TX_PEER_ENTRY_VLAN_LLC_MODE_MSB 3
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#define TX_PEER_ENTRY_VLAN_LLC_MODE_MASK 0x00000008
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#define TX_PEER_ENTRY_KEY_TYPE_OFFSET 0x0000000c
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#define TX_PEER_ENTRY_KEY_TYPE_LSB 4
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#define TX_PEER_ENTRY_KEY_TYPE_MSB 7
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#define TX_PEER_ENTRY_KEY_TYPE_MASK 0x000000f0
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#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_OFFSET 0x0000000c
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#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_LSB 8
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#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MSB 10
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#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MASK 0x00000700
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#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_OFFSET 0x0000000c
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#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_LSB 11
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#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MSB 11
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#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MASK 0x00000800
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#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_OFFSET 0x0000000c
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#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_LSB 12
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#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MSB 12
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#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MASK 0x00001000
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#define TX_PEER_ENTRY_EPD_OUTPUT_OFFSET 0x0000000c
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#define TX_PEER_ENTRY_EPD_OUTPUT_LSB 13
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#define TX_PEER_ENTRY_EPD_OUTPUT_MSB 13
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#define TX_PEER_ENTRY_EPD_OUTPUT_MASK 0x00002000
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#define TX_PEER_ENTRY_WDS_OFFSET 0x0000000c
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#define TX_PEER_ENTRY_WDS_LSB 14
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#define TX_PEER_ENTRY_WDS_MSB 14
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#define TX_PEER_ENTRY_WDS_MASK 0x00004000
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#define TX_PEER_ENTRY_INSERT_OR_STRIP_OFFSET 0x0000000c
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#define TX_PEER_ENTRY_INSERT_OR_STRIP_LSB 15
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#define TX_PEER_ENTRY_INSERT_OR_STRIP_MSB 15
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#define TX_PEER_ENTRY_INSERT_OR_STRIP_MASK 0x00008000
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#define TX_PEER_ENTRY_SW_FILTER_ID_OFFSET 0x0000000c
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#define TX_PEER_ENTRY_SW_FILTER_ID_LSB 16
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#define TX_PEER_ENTRY_SW_FILTER_ID_MSB 31
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#define TX_PEER_ENTRY_SW_FILTER_ID_MASK 0xffff0000
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#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_OFFSET 0x00000010
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#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_LSB 0
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#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MSB 31
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#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MASK 0xffffffff
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#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_OFFSET 0x00000014
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#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_LSB 0
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#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MSB 31
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#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MASK 0xffffffff
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#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_OFFSET 0x00000018
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#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_LSB 0
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#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MSB 31
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#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MASK 0xffffffff
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#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_OFFSET 0x0000001c
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#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_LSB 0
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#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MSB 31
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#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MASK 0xffffffff
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#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_OFFSET 0x00000020
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#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_LSB 0
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#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MSB 31
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#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MASK 0xffffffff
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#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_OFFSET 0x00000024
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#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_LSB 0
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#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MSB 31
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#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MASK 0xffffffff
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#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_OFFSET 0x00000028
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#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_LSB 0
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#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MSB 31
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#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MASK 0xffffffff
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#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_OFFSET 0x0000002c
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#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_LSB 0
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#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MSB 31
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#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MASK 0xffffffff
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#define TX_PEER_ENTRY_STA_PARTIAL_AID_OFFSET 0x00000030
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#define TX_PEER_ENTRY_STA_PARTIAL_AID_LSB 0
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#define TX_PEER_ENTRY_STA_PARTIAL_AID_MSB 10
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#define TX_PEER_ENTRY_STA_PARTIAL_AID_MASK 0x000007ff
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#define TX_PEER_ENTRY_TRANSMIT_VIF_OFFSET 0x00000030
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#define TX_PEER_ENTRY_TRANSMIT_VIF_LSB 11
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#define TX_PEER_ENTRY_TRANSMIT_VIF_MSB 14
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#define TX_PEER_ENTRY_TRANSMIT_VIF_MASK 0x00007800
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#define TX_PEER_ENTRY_BLOCK_THIS_USER_OFFSET 0x00000030
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#define TX_PEER_ENTRY_BLOCK_THIS_USER_LSB 15
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#define TX_PEER_ENTRY_BLOCK_THIS_USER_MSB 15
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#define TX_PEER_ENTRY_BLOCK_THIS_USER_MASK 0x00008000
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#define TX_PEER_ENTRY_MESH_AMSDU_MODE_OFFSET 0x00000030
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#define TX_PEER_ENTRY_MESH_AMSDU_MODE_LSB 16
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#define TX_PEER_ENTRY_MESH_AMSDU_MODE_MSB 17
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#define TX_PEER_ENTRY_MESH_AMSDU_MODE_MASK 0x00030000
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#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_OFFSET 0x00000030
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#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_LSB 18
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#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MSB 18
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#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MASK 0x00040000
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#define TX_PEER_ENTRY_DL_UL_DIRECTION_OFFSET 0x00000030
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#define TX_PEER_ENTRY_DL_UL_DIRECTION_LSB 19
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#define TX_PEER_ENTRY_DL_UL_DIRECTION_MSB 19
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#define TX_PEER_ENTRY_DL_UL_DIRECTION_MASK 0x00080000
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#define TX_PEER_ENTRY_RESERVED_12_OFFSET 0x00000030
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#define TX_PEER_ENTRY_RESERVED_12_LSB 20
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#define TX_PEER_ENTRY_RESERVED_12_MSB 31
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#define TX_PEER_ENTRY_RESERVED_12_MASK 0xfff00000
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#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_OFFSET 0x00000034
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#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_LSB 0
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#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MSB 15
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#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MASK 0x0000ffff
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#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_OFFSET 0x00000034
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#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_LSB 16
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#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MSB 31
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#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MASK 0xffff0000
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#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_OFFSET 0x00000044
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#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_LSB 0
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#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MSB 0
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#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MASK 0x00000001
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#define TX_PEER_ENTRY_RESERVED_17A_OFFSET 0x00000044
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#define TX_PEER_ENTRY_RESERVED_17A_LSB 1
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#define TX_PEER_ENTRY_RESERVED_17A_MSB 15
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#define TX_PEER_ENTRY_RESERVED_17A_MASK 0x0000fffe
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#define TX_PEER_ENTRY_SW_PEER_ID_OFFSET 0x00000044
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#define TX_PEER_ENTRY_SW_PEER_ID_LSB 16
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#define TX_PEER_ENTRY_SW_PEER_ID_MSB 31
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#define TX_PEER_ENTRY_SW_PEER_ID_MASK 0xffff0000
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#endif
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