msm_vidc_internal.h 24 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2020-2021,, The Linux Foundation. All rights reserved.
  4. */
  5. #ifndef _MSM_VIDC_INTERNAL_H_
  6. #define _MSM_VIDC_INTERNAL_H_
  7. #include <linux/version.h>
  8. #include <linux/bits.h>
  9. #include <linux/workqueue.h>
  10. #include <media/v4l2-dev.h>
  11. #include <media/v4l2-device.h>
  12. #include <media/v4l2-ioctl.h>
  13. #include <media/v4l2-event.h>
  14. #include <media/v4l2-ctrls.h>
  15. #include <media/videobuf2-core.h>
  16. #include <media/videobuf2-v4l2.h>
  17. #define MAX_NAME_LENGTH 128
  18. #define VENUS_VERSION_LENGTH 128
  19. #define MAX_MATRIX_COEFFS 9
  20. #define MAX_BIAS_COEFFS 3
  21. #define MAX_LIMIT_COEFFS 6
  22. #define MAX_DEBUGFS_NAME 50
  23. #define DEFAULT_TIMEOUT 3
  24. #define DEFAULT_HEIGHT 240
  25. #define DEFAULT_WIDTH 320
  26. #define MAX_HEIGHT 4320
  27. #define MAX_WIDTH 8192
  28. #define MIN_SUPPORTED_WIDTH 32
  29. #define MIN_SUPPORTED_HEIGHT 32
  30. #define DEFAULT_FPS 30
  31. #define MAXIMUM_VP9_FPS 60
  32. #define SINGLE_INPUT_BUFFER 1
  33. #define SINGLE_OUTPUT_BUFFER 1
  34. #define MAX_NUM_INPUT_BUFFERS VIDEO_MAX_FRAME // same as VB2_MAX_FRAME
  35. #define MAX_NUM_OUTPUT_BUFFERS VIDEO_MAX_FRAME // same as VB2_MAX_FRAME
  36. #define MAX_SUPPORTED_INSTANCES 16
  37. #define MAX_BSE_VPP_DELAY 6
  38. #define DEFAULT_BSE_VPP_DELAY 2
  39. #define MAX_CAP_PARENTS 20
  40. #define MAX_CAP_CHILDREN 20
  41. #define DEFAULT_BITSTREM_ALIGNMENT 16
  42. #define H265_BITSTREM_ALIGNMENT 32
  43. #define DEFAULT_MAX_HOST_BUF_COUNT 64
  44. #define DEFAULT_MAX_HOST_BURST_BUF_COUNT 256
  45. #define BIT_DEPTH_8 (8 << 16 | 8)
  46. #define BIT_DEPTH_10 (10 << 16 | 10)
  47. #define CODED_FRAMES_PROGRESSIVE 0x0
  48. #define CODED_FRAMES_INTERLACE 0x1
  49. #define MAX_VP9D_INST_COUNT 6
  50. /* TODO: move below macros to waipio.c */
  51. #define MAX_ENH_LAYER_HB 3
  52. #define MAX_HEVC_ENH_LAYER_SLIDING_WINDOW 5
  53. #define MAX_AVC_ENH_LAYER_SLIDING_WINDOW 3
  54. #define MAX_AVC_ENH_LAYER_HYBRID_HP 5
  55. #define INVALID_DEFAULT_MARK_OR_USE_LTR -1
  56. #define MAX_SLICES_PER_FRAME 10
  57. #define MAX_SLICES_FRAME_RATE 60
  58. #define MAX_MB_SLICE_WIDTH 4096
  59. #define MAX_MB_SLICE_HEIGHT 2160
  60. #define MAX_BYTES_SLICE_WIDTH 1920
  61. #define MAX_BYTES_SLICE_HEIGHT 1088
  62. #define MIN_HEVC_SLICE_WIDTH 384
  63. #define MIN_AVC_SLICE_WIDTH 192
  64. #define MIN_SLICE_HEIGHT 128
  65. #define MAX_BITRATE_BOOST 25
  66. #define MAX_SUPPORTED_MIN_QUALITY 70
  67. #define MIN_CHROMA_QP_OFFSET -12
  68. #define MAX_CHROMA_QP_OFFSET 0
  69. #define DCVS_WINDOW 16
  70. #define ENC_FPS_WINDOW 3
  71. #define DEC_FPS_WINDOW 10
  72. /* Superframe can have maximum of 32 frames */
  73. #define VIDC_SUPERFRAME_MAX 32
  74. #define COLOR_RANGE_UNSPECIFIED (-1)
  75. #define V4L2_EVENT_VIDC_BASE 10
  76. #define INPUT_MPLANE V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE
  77. #define OUTPUT_MPLANE V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE
  78. #define INPUT_META_PLANE V4L2_BUF_TYPE_META_OUTPUT
  79. #define OUTPUT_META_PLANE V4L2_BUF_TYPE_META_CAPTURE
  80. #define VIDC_IFACEQ_MAX_PKT_SIZE 1024
  81. #define VIDC_IFACEQ_MED_PKT_SIZE 768
  82. #define VIDC_IFACEQ_MIN_PKT_SIZE 8
  83. #define VIDC_IFACEQ_VAR_SMALL_PKT_SIZE 100
  84. #define VIDC_IFACEQ_VAR_LARGE_PKT_SIZE 512
  85. #define VIDC_IFACEQ_VAR_HUGE_PKT_SIZE (1024*12)
  86. #define NUM_MBS_PER_SEC(__height, __width, __fps) \
  87. (NUM_MBS_PER_FRAME(__height, __width) * __fps)
  88. #define NUM_MBS_PER_FRAME(__height, __width) \
  89. ((ALIGN(__height, 16) / 16) * (ALIGN(__width, 16) / 16))
  90. #ifdef V4L2_CTRL_CLASS_CODEC
  91. #define IS_PRIV_CTRL(idx) ( \
  92. (V4L2_CTRL_ID2WHICH(idx) == V4L2_CTRL_CLASS_CODEC) && \
  93. V4L2_CTRL_DRIVER_PRIV(idx))
  94. #else
  95. #define IS_PRIV_CTRL(idx) ( \
  96. (V4L2_CTRL_ID2WHICH(idx) == V4L2_CTRL_CLASS_MPEG) && \
  97. V4L2_CTRL_DRIVER_PRIV(idx))
  98. #endif
  99. #define BUFFER_ALIGNMENT_SIZE(x) x
  100. #define NUM_MBS_720P (((1280 + 15) >> 4) * ((720 + 15) >> 4))
  101. #define NUM_MBS_4k (((4096 + 15) >> 4) * ((2304 + 15) >> 4))
  102. #define MB_SIZE_IN_PIXEL (16 * 16)
  103. #define DB_H264_DISABLE_SLICE_BOUNDARY \
  104. V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY
  105. #define DB_HEVC_DISABLE_SLICE_BOUNDARY \
  106. V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY
  107. /*
  108. * Convert Q16 number into Integer and Fractional part upto 2 places.
  109. * Ex : 105752 / 65536 = 1.61; 1.61 in Q16 = 105752;
  110. * Integer part = 105752 / 65536 = 1;
  111. * Reminder = 105752 * 0xFFFF = 40216; Last 16 bits.
  112. * Fractional part = 40216 * 100 / 65536 = 61;
  113. * Now convert to FP(1, 61, 100).
  114. */
  115. #define Q16_INT(q) ((q) >> 16)
  116. #define Q16_FRAC(q) ((((q) & 0xFFFF) * 100) >> 16)
  117. /* define timeout values */
  118. #define HW_RESPONSE_TIMEOUT_VALUE (1000)
  119. #define SW_PC_DELAY_VALUE (HW_RESPONSE_TIMEOUT_VALUE + 500)
  120. #define FW_UNLOAD_DELAY_VALUE (SW_PC_DELAY_VALUE + 1500)
  121. #define MAX_MAP_OUTPUT_COUNT 64
  122. #define MAX_DPB_COUNT 32
  123. /*
  124. * max dpb count in firmware = 16
  125. * each dpb: 4 words - <base_address, addr_offset, data_offset>
  126. * dpb list array size = 16 * 4
  127. * dpb payload size = 16 * 4 * 4
  128. */
  129. #define MAX_DPB_LIST_ARRAY_SIZE (16 * 4)
  130. #define MAX_DPB_LIST_PAYLOAD_SIZE (16 * 4 * 4)
  131. enum msm_vidc_domain_type {
  132. MSM_VIDC_ENCODER = BIT(0),
  133. MSM_VIDC_DECODER = BIT(1),
  134. };
  135. enum msm_vidc_codec_type {
  136. MSM_VIDC_H264 = BIT(0),
  137. MSM_VIDC_HEVC = BIT(1),
  138. MSM_VIDC_VP9 = BIT(2),
  139. MSM_VIDC_HEIC = BIT(3),
  140. MSM_VIDC_AV1 = BIT(4),
  141. };
  142. enum priority_level {
  143. MSM_VIDC_PRIORITY_HIGH = 0,
  144. MSM_VIDC_PRIORITY_LOW = 1,
  145. };
  146. enum msm_vidc_colorformat_type {
  147. MSM_VIDC_FMT_NONE = 0,
  148. MSM_VIDC_FMT_NV12C = BIT(0),
  149. MSM_VIDC_FMT_NV12 = BIT(1),
  150. MSM_VIDC_FMT_NV21 = BIT(2),
  151. MSM_VIDC_FMT_TP10C = BIT(3),
  152. MSM_VIDC_FMT_P010 = BIT(4),
  153. MSM_VIDC_FMT_RGBA8888C = BIT(5),
  154. MSM_VIDC_FMT_RGBA8888 = BIT(6),
  155. };
  156. enum msm_vidc_buffer_type {
  157. MSM_VIDC_BUF_INPUT = 1,
  158. MSM_VIDC_BUF_OUTPUT = 2,
  159. MSM_VIDC_BUF_INPUT_META = 3,
  160. MSM_VIDC_BUF_OUTPUT_META = 4,
  161. MSM_VIDC_BUF_READ_ONLY = 5,
  162. MSM_VIDC_BUF_QUEUE = 6,
  163. MSM_VIDC_BUF_BIN = 7,
  164. MSM_VIDC_BUF_ARP = 8,
  165. MSM_VIDC_BUF_COMV = 9,
  166. MSM_VIDC_BUF_NON_COMV = 10,
  167. MSM_VIDC_BUF_LINE = 11,
  168. MSM_VIDC_BUF_DPB = 12,
  169. MSM_VIDC_BUF_PERSIST = 13,
  170. MSM_VIDC_BUF_VPSS = 14,
  171. };
  172. /* always match with v4l2 flags V4L2_BUF_FLAG_* */
  173. enum msm_vidc_buffer_flags {
  174. MSM_VIDC_BUF_FLAG_KEYFRAME = 0x00000008,
  175. MSM_VIDC_BUF_FLAG_PFRAME = 0x00000010,
  176. MSM_VIDC_BUF_FLAG_BFRAME = 0x00000020,
  177. MSM_VIDC_BUF_FLAG_ERROR = 0x00000040,
  178. MSM_VIDC_BUF_FLAG_LAST = 0x00100000,
  179. MSM_VIDC_BUF_FLAG_CODECCONFIG = 0x01000000,
  180. MSM_VIDC_BUF_FLAG_SUBFRAME = 0x02000000,
  181. };
  182. enum msm_vidc_buffer_attributes {
  183. MSM_VIDC_ATTR_DEFERRED = BIT(0),
  184. MSM_VIDC_ATTR_READ_ONLY = BIT(1),
  185. MSM_VIDC_ATTR_PENDING_RELEASE = BIT(2),
  186. MSM_VIDC_ATTR_QUEUED = BIT(3),
  187. MSM_VIDC_ATTR_DEQUEUED = BIT(4),
  188. MSM_VIDC_ATTR_BUFFER_DONE = BIT(5),
  189. };
  190. enum msm_vidc_buffer_region {
  191. MSM_VIDC_REGION_NONE = 0,
  192. MSM_VIDC_NON_SECURE,
  193. MSM_VIDC_NON_SECURE_PIXEL,
  194. MSM_VIDC_SECURE_PIXEL,
  195. MSM_VIDC_SECURE_NONPIXEL,
  196. MSM_VIDC_SECURE_BITSTREAM,
  197. };
  198. enum msm_vidc_port_type {
  199. INPUT_PORT = 0,
  200. OUTPUT_PORT,
  201. INPUT_META_PORT,
  202. OUTPUT_META_PORT,
  203. PORT_NONE,
  204. MAX_PORT,
  205. };
  206. enum msm_vidc_stage_type {
  207. MSM_VIDC_STAGE_NONE = 0,
  208. MSM_VIDC_STAGE_1 = 1,
  209. MSM_VIDC_STAGE_2 = 2,
  210. };
  211. enum msm_vidc_pipe_type {
  212. MSM_VIDC_PIPE_NONE = 0,
  213. MSM_VIDC_PIPE_1 = 1,
  214. MSM_VIDC_PIPE_2 = 2,
  215. MSM_VIDC_PIPE_4 = 4,
  216. };
  217. enum msm_vidc_quality_mode {
  218. MSM_VIDC_MAX_QUALITY_MODE = 0x1,
  219. MSM_VIDC_POWER_SAVE_MODE = 0x2,
  220. };
  221. enum msm_vidc_color_primaries {
  222. MSM_VIDC_PRIMARIES_RESERVED = 0,
  223. MSM_VIDC_PRIMARIES_BT709 = 1,
  224. MSM_VIDC_PRIMARIES_UNSPECIFIED = 2,
  225. MSM_VIDC_PRIMARIES_BT470_SYSTEM_M = 4,
  226. MSM_VIDC_PRIMARIES_BT470_SYSTEM_BG = 5,
  227. MSM_VIDC_PRIMARIES_BT601_525 = 6,
  228. MSM_VIDC_PRIMARIES_SMPTE_ST240M = 7,
  229. MSM_VIDC_PRIMARIES_GENERIC_FILM = 8,
  230. MSM_VIDC_PRIMARIES_BT2020 = 9,
  231. MSM_VIDC_PRIMARIES_SMPTE_ST428_1 = 10,
  232. MSM_VIDC_PRIMARIES_SMPTE_RP431_2 = 11,
  233. MSM_VIDC_PRIMARIES_SMPTE_EG431_1 = 12,
  234. MSM_VIDC_PRIMARIES_SMPTE_EBU_TECH = 22,
  235. };
  236. enum msm_vidc_transfer_characteristics {
  237. MSM_VIDC_TRANSFER_RESERVED = 0,
  238. MSM_VIDC_TRANSFER_BT709 = 1,
  239. MSM_VIDC_TRANSFER_UNSPECIFIED = 2,
  240. MSM_VIDC_TRANSFER_BT470_SYSTEM_M = 4,
  241. MSM_VIDC_TRANSFER_BT470_SYSTEM_BG = 5,
  242. MSM_VIDC_TRANSFER_BT601_525_OR_625 = 6,
  243. MSM_VIDC_TRANSFER_SMPTE_ST240M = 7,
  244. MSM_VIDC_TRANSFER_LINEAR = 8,
  245. MSM_VIDC_TRANSFER_LOG_100_1 = 9,
  246. MSM_VIDC_TRANSFER_LOG_SQRT = 10,
  247. MSM_VIDC_TRANSFER_XVYCC = 11,
  248. MSM_VIDC_TRANSFER_BT1361_0 = 12,
  249. MSM_VIDC_TRANSFER_SRGB_SYCC = 13,
  250. MSM_VIDC_TRANSFER_BT2020_14 = 14,
  251. MSM_VIDC_TRANSFER_BT2020_15 = 15,
  252. MSM_VIDC_TRANSFER_SMPTE_ST2084_PQ = 16,
  253. MSM_VIDC_TRANSFER_SMPTE_ST428_1 = 17,
  254. MSM_VIDC_TRANSFER_BT2100_2_HLG = 18,
  255. };
  256. enum msm_vidc_matrix_coefficients {
  257. MSM_VIDC_MATRIX_COEFF_SRGB_SMPTE_ST428_1 = 0,
  258. MSM_VIDC_MATRIX_COEFF_BT709 = 1,
  259. MSM_VIDC_MATRIX_COEFF_UNSPECIFIED = 2,
  260. MSM_VIDC_MATRIX_COEFF_RESERVED = 3,
  261. MSM_VIDC_MATRIX_COEFF_FCC_TITLE_47 = 4,
  262. MSM_VIDC_MATRIX_COEFF_BT470_SYS_BG_OR_BT601_625 = 5,
  263. MSM_VIDC_MATRIX_COEFF_BT601_525_BT1358_525_OR_625 = 6,
  264. MSM_VIDC_MATRIX_COEFF_SMPTE_ST240 = 7,
  265. MSM_VIDC_MATRIX_COEFF_YCGCO = 8,
  266. MSM_VIDC_MATRIX_COEFF_BT2020_NON_CONSTANT = 9,
  267. MSM_VIDC_MATRIX_COEFF_BT2020_CONSTANT = 10,
  268. MSM_VIDC_MATRIX_COEFF_SMPTE_ST2085 = 11,
  269. MSM_VIDC_MATRIX_COEFF_SMPTE_CHROM_DERV_NON_CONSTANT = 12,
  270. MSM_VIDC_MATRIX_COEFF_SMPTE_CHROM_DERV_CONSTANT = 13,
  271. MSM_VIDC_MATRIX_COEFF_BT2100 = 14,
  272. };
  273. enum msm_vidc_ctrl_list_type {
  274. CHILD_LIST = BIT(0),
  275. FW_LIST = BIT(1),
  276. };
  277. enum msm_vidc_core_capability_type {
  278. CORE_CAP_NONE = 0,
  279. ENC_CODECS,
  280. DEC_CODECS,
  281. MAX_SESSION_COUNT,
  282. MAX_NUM_720P_SESSIONS,
  283. MAX_NUM_1080P_SESSIONS,
  284. MAX_NUM_4K_SESSIONS,
  285. MAX_NUM_8K_SESSIONS,
  286. MAX_SECURE_SESSION_COUNT,
  287. MAX_LOAD,
  288. MAX_RT_MBPF,
  289. MAX_MBPF,
  290. MAX_MBPS,
  291. MAX_IMAGE_MBPF,
  292. MAX_MBPF_HQ,
  293. MAX_MBPS_HQ,
  294. MAX_MBPF_B_FRAME,
  295. MAX_MBPS_B_FRAME,
  296. MAX_MBPS_ALL_INTRA,
  297. MAX_ENH_LAYER_COUNT,
  298. NUM_VPP_PIPE,
  299. SW_PC,
  300. SW_PC_DELAY,
  301. FW_UNLOAD,
  302. FW_UNLOAD_DELAY,
  303. HW_RESPONSE_TIMEOUT,
  304. PREFIX_BUF_COUNT_PIX,
  305. PREFIX_BUF_SIZE_PIX,
  306. PREFIX_BUF_COUNT_NON_PIX,
  307. PREFIX_BUF_SIZE_NON_PIX,
  308. PAGEFAULT_NON_FATAL,
  309. PAGETABLE_CACHING,
  310. DCVS,
  311. DECODE_BATCH,
  312. DECODE_BATCH_TIMEOUT,
  313. STATS_TIMEOUT_MS,
  314. AV_SYNC_WINDOW_SIZE,
  315. CLK_FREQ_THRESHOLD,
  316. NON_FATAL_FAULTS,
  317. ENC_AUTO_FRAMERATE,
  318. MMRM,
  319. CORE_CAP_MAX,
  320. };
  321. enum msm_vidc_inst_capability_type {
  322. INST_CAP_NONE = 0,
  323. FRAME_WIDTH,
  324. LOSSLESS_FRAME_WIDTH,
  325. SECURE_FRAME_WIDTH,
  326. FRAME_HEIGHT,
  327. LOSSLESS_FRAME_HEIGHT,
  328. SECURE_FRAME_HEIGHT,
  329. PIX_FMTS,
  330. MIN_BUFFERS_INPUT,
  331. MIN_BUFFERS_OUTPUT,
  332. MBPF,
  333. LOSSLESS_MBPF,
  334. BATCH_MBPF,
  335. BATCH_FPS,
  336. SECURE_MBPF,
  337. MBPS,
  338. POWER_SAVE_MBPS,
  339. FRAME_RATE,
  340. OPERATING_RATE,
  341. SCALE_FACTOR,
  342. MB_CYCLES_VSP,
  343. MB_CYCLES_VPP,
  344. MB_CYCLES_LP,
  345. MB_CYCLES_FW,
  346. MB_CYCLES_FW_VPP,
  347. SECURE_MODE,
  348. HFLIP,
  349. VFLIP,
  350. ROTATION,
  351. SUPER_FRAME,
  352. SLICE_INTERFACE,
  353. HEADER_MODE,
  354. PREPEND_SPSPPS_TO_IDR,
  355. META_SEQ_HDR_NAL,
  356. WITHOUT_STARTCODE,
  357. NAL_LENGTH_FIELD,
  358. REQUEST_I_FRAME,
  359. BIT_RATE,
  360. BITRATE_MODE,
  361. LOSSLESS,
  362. FRAME_SKIP_MODE,
  363. FRAME_RC_ENABLE,
  364. CONSTANT_QUALITY,
  365. GOP_SIZE,
  366. GOP_CLOSURE,
  367. B_FRAME,
  368. BLUR_TYPES,
  369. BLUR_RESOLUTION,
  370. CSC,
  371. CSC_CUSTOM_MATRIX,
  372. GRID,
  373. LOWLATENCY_MODE,
  374. LTR_COUNT,
  375. USE_LTR,
  376. MARK_LTR,
  377. BASELAYER_PRIORITY,
  378. IR_RANDOM,
  379. AU_DELIMITER,
  380. TIME_DELTA_BASED_RC,
  381. CONTENT_ADAPTIVE_CODING,
  382. BITRATE_BOOST,
  383. MIN_QUALITY,
  384. VBV_DELAY,
  385. PEAK_BITRATE,
  386. MIN_FRAME_QP,
  387. I_FRAME_MIN_QP,
  388. P_FRAME_MIN_QP,
  389. B_FRAME_MIN_QP,
  390. MAX_FRAME_QP,
  391. I_FRAME_MAX_QP,
  392. P_FRAME_MAX_QP,
  393. B_FRAME_MAX_QP,
  394. I_FRAME_QP,
  395. P_FRAME_QP,
  396. B_FRAME_QP,
  397. LAYER_TYPE,
  398. LAYER_ENABLE,
  399. ENH_LAYER_COUNT,
  400. L0_BR,
  401. L1_BR,
  402. L2_BR,
  403. L3_BR,
  404. L4_BR,
  405. L5_BR,
  406. ENTROPY_MODE,
  407. PROFILE,
  408. LEVEL,
  409. HEVC_TIER,
  410. AV1_TIER,
  411. LF_MODE,
  412. LF_ALPHA,
  413. LF_BETA,
  414. SLICE_MODE,
  415. SLICE_MAX_BYTES,
  416. SLICE_MAX_MB,
  417. MB_RC,
  418. TRANSFORM_8X8,
  419. CHROMA_QP_INDEX_OFFSET,
  420. DISPLAY_DELAY_ENABLE,
  421. DISPLAY_DELAY,
  422. CONCEAL_COLOR_8BIT,
  423. CONCEAL_COLOR_10BIT,
  424. STAGE,
  425. PIPE,
  426. POC,
  427. QUALITY_MODE,
  428. CODED_FRAMES,
  429. BIT_DEPTH,
  430. CODEC_CONFIG,
  431. BITSTREAM_SIZE_OVERWRITE,
  432. THUMBNAIL_MODE,
  433. DEFAULT_HEADER,
  434. RAP_FRAME,
  435. SEQ_CHANGE_AT_SYNC_FRAME,
  436. PRIORITY,
  437. ENC_IP_CR,
  438. DPB_LIST,
  439. FILM_GRAIN,
  440. SUPER_BLOCK,
  441. ALL_INTRA,
  442. META_BITSTREAM_RESOLUTION,
  443. META_CROP_OFFSETS,
  444. META_LTR_MARK_USE,
  445. META_DPB_MISR,
  446. META_OPB_MISR,
  447. META_INTERLACE,
  448. META_TIMESTAMP,
  449. META_CONCEALED_MB_CNT,
  450. META_HIST_INFO,
  451. META_SEI_MASTERING_DISP,
  452. META_SEI_CLL,
  453. META_HDR10PLUS,
  454. META_EVA_STATS,
  455. META_BUF_TAG,
  456. META_DPB_TAG_LIST,
  457. META_OUTPUT_BUF_TAG,
  458. META_SUBFRAME_OUTPUT,
  459. META_ENC_QP_METADATA,
  460. META_ROI_INFO,
  461. META_DEC_QP_METADATA,
  462. COMPLEXITY,
  463. META_MAX_NUM_REORDER_FRAMES,
  464. INST_CAP_MAX,
  465. };
  466. enum msm_vidc_inst_capability_flags {
  467. CAP_FLAG_NONE = 0,
  468. CAP_FLAG_ROOT = BIT(0),
  469. CAP_FLAG_DYNAMIC_ALLOWED = BIT(1),
  470. CAP_FLAG_MENU = BIT(2),
  471. CAP_FLAG_INPUT_PORT = BIT(3),
  472. CAP_FLAG_OUTPUT_PORT = BIT(4),
  473. CAP_FLAG_CLIENT_SET = BIT(5),
  474. };
  475. struct msm_vidc_inst_cap {
  476. enum msm_vidc_inst_capability_type cap;
  477. s32 min;
  478. s32 max;
  479. u32 step_or_mask;
  480. s32 value;
  481. u32 v4l2_id;
  482. u32 hfi_id;
  483. enum msm_vidc_inst_capability_flags flags;
  484. enum msm_vidc_inst_capability_type parents[MAX_CAP_PARENTS];
  485. enum msm_vidc_inst_capability_type children[MAX_CAP_CHILDREN];
  486. int (*adjust)(void *inst,
  487. struct v4l2_ctrl *ctrl);
  488. int (*set)(void *inst,
  489. enum msm_vidc_inst_capability_type cap_id);
  490. };
  491. struct msm_vidc_inst_capability {
  492. enum msm_vidc_domain_type domain;
  493. enum msm_vidc_codec_type codec;
  494. struct msm_vidc_inst_cap cap[INST_CAP_MAX+1];
  495. };
  496. struct msm_vidc_core_capability {
  497. enum msm_vidc_core_capability_type type;
  498. u32 value;
  499. };
  500. struct msm_vidc_inst_cap_entry {
  501. /* list of struct msm_vidc_inst_cap_entry */
  502. struct list_head list;
  503. enum msm_vidc_inst_capability_type cap_id;
  504. };
  505. struct debug_buf_count {
  506. u64 etb;
  507. u64 ftb;
  508. u64 fbd;
  509. u64 ebd;
  510. };
  511. struct msm_vidc_statistics {
  512. struct debug_buf_count count;
  513. u64 data_size;
  514. u64 time_ms;
  515. };
  516. enum efuse_purpose {
  517. SKU_VERSION = 0,
  518. };
  519. enum sku_version {
  520. SKU_VERSION_0 = 0,
  521. SKU_VERSION_1,
  522. SKU_VERSION_2,
  523. };
  524. enum msm_vidc_ssr_trigger_type {
  525. SSR_ERR_FATAL = 1,
  526. SSR_SW_DIV_BY_ZERO,
  527. SSR_HW_WDOG_IRQ,
  528. };
  529. enum msm_vidc_cache_op {
  530. MSM_VIDC_CACHE_CLEAN,
  531. MSM_VIDC_CACHE_INVALIDATE,
  532. MSM_VIDC_CACHE_CLEAN_INVALIDATE,
  533. };
  534. enum msm_vidc_dcvs_flags {
  535. MSM_VIDC_DCVS_INCR = BIT(0),
  536. MSM_VIDC_DCVS_DECR = BIT(1),
  537. };
  538. enum msm_vidc_clock_properties {
  539. CLOCK_PROP_HAS_SCALING = BIT(0),
  540. CLOCK_PROP_HAS_MEM_RETENTION = BIT(1),
  541. };
  542. enum profiling_points {
  543. FRAME_PROCESSING = 0,
  544. MAX_PROFILING_POINTS,
  545. };
  546. enum signal_session_response {
  547. SIGNAL_CMD_STOP_INPUT = 0,
  548. SIGNAL_CMD_STOP_OUTPUT,
  549. SIGNAL_CMD_CLOSE,
  550. MAX_SIGNAL,
  551. };
  552. #define HFI_MASK_QHDR_TX_TYPE 0xFF000000
  553. #define HFI_MASK_QHDR_RX_TYPE 0x00FF0000
  554. #define HFI_MASK_QHDR_PRI_TYPE 0x0000FF00
  555. #define HFI_MASK_QHDR_Q_ID_TYPE 0x000000FF
  556. #define HFI_Q_ID_HOST_TO_CTRL_CMD_Q 0x00
  557. #define HFI_Q_ID_CTRL_TO_HOST_MSG_Q 0x01
  558. #define HFI_Q_ID_CTRL_TO_HOST_DEBUG_Q 0x02
  559. #define HFI_MASK_QHDR_STATUS 0x000000FF
  560. #define VIDC_IFACEQ_NUMQ 3
  561. #define VIDC_IFACEQ_CMDQ_IDX 0
  562. #define VIDC_IFACEQ_MSGQ_IDX 1
  563. #define VIDC_IFACEQ_DBGQ_IDX 2
  564. #define VIDC_IFACEQ_MAX_BUF_COUNT 50
  565. #define VIDC_IFACE_MAX_PARALLEL_CLNTS 16
  566. #define VIDC_IFACEQ_DFLT_QHDR 0x01010000
  567. struct hfi_queue_table_header {
  568. u32 qtbl_version;
  569. u32 qtbl_size;
  570. u32 qtbl_qhdr0_offset;
  571. u32 qtbl_qhdr_size;
  572. u32 qtbl_num_q;
  573. u32 qtbl_num_active_q;
  574. void *device_addr;
  575. char name[256];
  576. };
  577. struct hfi_queue_header {
  578. u32 qhdr_status;
  579. u32 qhdr_start_addr;
  580. u32 qhdr_type;
  581. u32 qhdr_q_size;
  582. u32 qhdr_pkt_size;
  583. u32 qhdr_pkt_drop_cnt;
  584. u32 qhdr_rx_wm;
  585. u32 qhdr_tx_wm;
  586. u32 qhdr_rx_req;
  587. u32 qhdr_tx_req;
  588. u32 qhdr_rx_irq_status;
  589. u32 qhdr_tx_irq_status;
  590. u32 qhdr_read_idx;
  591. u32 qhdr_write_idx;
  592. };
  593. #define VIDC_IFACEQ_TABLE_SIZE (sizeof(struct hfi_queue_table_header) \
  594. + sizeof(struct hfi_queue_header) * VIDC_IFACEQ_NUMQ)
  595. #define VIDC_IFACEQ_QUEUE_SIZE (VIDC_IFACEQ_MAX_PKT_SIZE * \
  596. VIDC_IFACEQ_MAX_BUF_COUNT * VIDC_IFACE_MAX_PARALLEL_CLNTS)
  597. #define VIDC_IFACEQ_GET_QHDR_START_ADDR(ptr, i) \
  598. (void *)((ptr + sizeof(struct hfi_queue_table_header)) + \
  599. (i * sizeof(struct hfi_queue_header)))
  600. #define QDSS_SIZE 4096
  601. #define SFR_SIZE 4096
  602. #define QUEUE_SIZE (VIDC_IFACEQ_TABLE_SIZE + \
  603. (VIDC_IFACEQ_QUEUE_SIZE * VIDC_IFACEQ_NUMQ))
  604. #define ALIGNED_QDSS_SIZE ALIGN(QDSS_SIZE, SZ_4K)
  605. #define ALIGNED_SFR_SIZE ALIGN(SFR_SIZE, SZ_4K)
  606. #define ALIGNED_QUEUE_SIZE ALIGN(QUEUE_SIZE, SZ_4K)
  607. #define SHARED_QSIZE ALIGN(ALIGNED_SFR_SIZE + ALIGNED_QUEUE_SIZE + \
  608. ALIGNED_QDSS_SIZE, SZ_1M)
  609. #define TOTAL_QSIZE (SHARED_QSIZE - ALIGNED_SFR_SIZE - ALIGNED_QDSS_SIZE)
  610. struct profile_data {
  611. u64 start;
  612. u64 stop;
  613. u64 cumulative;
  614. char name[64];
  615. u32 sampling;
  616. u64 average;
  617. };
  618. struct msm_vidc_debug {
  619. struct profile_data pdata[MAX_PROFILING_POINTS];
  620. u32 profile;
  621. u32 samples;
  622. };
  623. struct msm_vidc_input_cr_data {
  624. struct list_head list;
  625. u32 index;
  626. u32 input_cr;
  627. };
  628. struct msm_vidc_session_idle {
  629. bool idle;
  630. u64 last_activity_time_ns;
  631. };
  632. struct msm_vidc_color_info {
  633. u32 colorspace;
  634. u32 ycbcr_enc;
  635. u32 xfer_func;
  636. u32 quantization;
  637. };
  638. struct msm_vidc_rectangle {
  639. u32 left;
  640. u32 top;
  641. u32 width;
  642. u32 height;
  643. };
  644. struct msm_vidc_subscription_params {
  645. u32 bitstream_resolution;
  646. u32 crop_offsets[2];
  647. u32 bit_depth;
  648. u32 coded_frames;
  649. u32 fw_min_count;
  650. u32 pic_order_cnt;
  651. u32 color_info;
  652. u32 profile;
  653. u32 level;
  654. u32 tier;
  655. u32 av1_film_grain_present;
  656. u32 av1_super_block_enabled;
  657. };
  658. struct msm_vidc_hfi_frame_info {
  659. u32 picture_type;
  660. u32 no_output;
  661. u32 cr;
  662. u32 cf;
  663. u32 data_corrupt;
  664. u32 overflow;
  665. };
  666. struct msm_vidc_decode_vpp_delay {
  667. bool enable;
  668. u32 size;
  669. };
  670. struct msm_vidc_decode_batch {
  671. bool enable;
  672. u32 size;
  673. struct delayed_work work;
  674. };
  675. enum msm_vidc_power_mode {
  676. VIDC_POWER_NORMAL = 0,
  677. VIDC_POWER_LOW,
  678. VIDC_POWER_TURBO,
  679. };
  680. struct vidc_bus_vote_data {
  681. enum msm_vidc_domain_type domain;
  682. enum msm_vidc_codec_type codec;
  683. enum msm_vidc_power_mode power_mode;
  684. u32 color_formats[2];
  685. int num_formats; /* 1 = DPB-OPB unified; 2 = split */
  686. int input_height, input_width, bitrate;
  687. int output_height, output_width;
  688. int rotation;
  689. int compression_ratio;
  690. int complexity_factor;
  691. int input_cr;
  692. u32 lcu_size;
  693. u32 fps;
  694. u32 work_mode;
  695. bool use_sys_cache;
  696. bool b_frames_enabled;
  697. u64 calc_bw_ddr;
  698. u64 calc_bw_llcc;
  699. u32 num_vpp_pipes;
  700. };
  701. struct msm_vidc_power {
  702. enum msm_vidc_power_mode power_mode;
  703. u32 buffer_counter;
  704. u32 min_threshold;
  705. u32 nom_threshold;
  706. u32 max_threshold;
  707. bool dcvs_mode;
  708. u32 dcvs_window;
  709. u64 min_freq;
  710. u64 curr_freq;
  711. u32 ddr_bw;
  712. u32 sys_cache_bw;
  713. u32 dcvs_flags;
  714. u32 fw_cr;
  715. u32 fw_cf;
  716. };
  717. struct msm_vidc_alloc {
  718. struct list_head list;
  719. enum msm_vidc_buffer_type type;
  720. enum msm_vidc_buffer_region region;
  721. u32 size;
  722. u8 secure:1;
  723. u8 map_kernel:1;
  724. struct dma_buf *dmabuf;
  725. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5,15,0))
  726. struct dma_buf_map dmabuf_map;
  727. #endif
  728. void *kvaddr;
  729. };
  730. struct msm_vidc_allocations {
  731. struct list_head list; // list of "struct msm_vidc_alloc"
  732. };
  733. struct msm_vidc_map {
  734. struct list_head list;
  735. enum msm_vidc_buffer_type type;
  736. enum msm_vidc_buffer_region region;
  737. struct dma_buf *dmabuf;
  738. u32 refcount;
  739. u64 device_addr;
  740. struct sg_table *table;
  741. struct dma_buf_attachment *attach;
  742. u32 skip_delayed_unmap:1;
  743. };
  744. struct msm_vidc_mappings {
  745. struct list_head list; // list of "struct msm_vidc_map"
  746. };
  747. struct msm_vidc_buffer {
  748. struct list_head list;
  749. enum msm_vidc_buffer_type type;
  750. u32 index;
  751. int fd;
  752. u32 buffer_size;
  753. u32 data_offset;
  754. u32 data_size;
  755. u64 device_addr;
  756. void *dmabuf;
  757. u32 flags;
  758. u64 timestamp;
  759. enum msm_vidc_buffer_attributes attr;
  760. };
  761. struct msm_vidc_buffers {
  762. struct list_head list; // list of "struct msm_vidc_buffer"
  763. u32 min_count;
  764. u32 extra_count;
  765. u32 actual_count;
  766. u32 size;
  767. bool reuse;
  768. };
  769. struct msm_vidc_sort {
  770. struct list_head list;
  771. u64 val;
  772. };
  773. struct msm_vidc_timestamp {
  774. struct msm_vidc_sort sort;
  775. u64 rank;
  776. };
  777. struct msm_vidc_timestamps {
  778. struct list_head list;
  779. u32 count;
  780. u64 rank;
  781. };
  782. enum msm_vidc_allow {
  783. MSM_VIDC_DISALLOW = 0,
  784. MSM_VIDC_ALLOW,
  785. MSM_VIDC_DEFER,
  786. MSM_VIDC_DISCARD,
  787. MSM_VIDC_IGNORE,
  788. };
  789. enum response_work_type {
  790. RESP_WORK_INPUT_PSC = 1,
  791. RESP_WORK_OUTPUT_PSC,
  792. RESP_WORK_LAST_FLAG,
  793. };
  794. struct response_work {
  795. struct list_head list;
  796. enum response_work_type type;
  797. void *data;
  798. u32 data_size;
  799. };
  800. struct msm_vidc_ssr {
  801. bool trigger;
  802. enum msm_vidc_ssr_trigger_type ssr_type;
  803. u32 sub_client_id;
  804. u32 test_addr;
  805. };
  806. struct msm_vidc_sfr {
  807. u32 bufSize;
  808. u8 rg_data[1];
  809. };
  810. #define call_mem_op(c, op, ...) \
  811. (((c) && (c)->mem_ops && (c)->mem_ops->op) ? \
  812. ((c)->mem_ops->op(__VA_ARGS__)) : 0)
  813. struct msm_vidc_memory_ops {
  814. int (*allocate)(void *inst, struct msm_vidc_buffer *mbuf);
  815. int (*dma_map)(void *inst, struct msm_vidc_buffer *mbuf);
  816. int (*dma_unmap)(void *inst, struct msm_vidc_buffer *mbuf);
  817. int (*free)(void *inst, struct msm_vidc_buffer *mbuf);
  818. int (*cache_op)(void *inst, struct msm_vidc_buffer *mbuf,
  819. enum msm_vidc_cache_op cache_op);
  820. };
  821. #endif // _MSM_VIDC_INTERNAL_H_