dp_tx.c 161 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "htt.h"
  20. #include "dp_htt.h"
  21. #include "hal_hw_headers.h"
  22. #include "dp_tx.h"
  23. #include "dp_tx_desc.h"
  24. #include "dp_peer.h"
  25. #include "dp_types.h"
  26. #include "hal_tx.h"
  27. #include "qdf_mem.h"
  28. #include "qdf_nbuf.h"
  29. #include "qdf_net_types.h"
  30. #include "qdf_module.h"
  31. #include <wlan_cfg.h>
  32. #include "dp_ipa.h"
  33. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  34. #include "if_meta_hdr.h"
  35. #endif
  36. #include "enet.h"
  37. #include "dp_internal.h"
  38. #ifdef ATH_SUPPORT_IQUE
  39. #include "dp_txrx_me.h"
  40. #endif
  41. #include "dp_hist.h"
  42. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  43. #include <wlan_dp_swlm.h>
  44. #endif
  45. #ifdef WIFI_MONITOR_SUPPORT
  46. #include <dp_mon.h>
  47. #endif
  48. #ifdef FEATURE_WDS
  49. #include "dp_txrx_wds.h"
  50. #endif
  51. #include "cdp_txrx_cmn_reg.h"
  52. #ifdef CONFIG_SAWF
  53. #include <dp_sawf.h>
  54. #endif
  55. /* Flag to skip CCE classify when mesh or tid override enabled */
  56. #define DP_TX_SKIP_CCE_CLASSIFY \
  57. (DP_TXRX_HLOS_TID_OVERRIDE_ENABLED | DP_TX_MESH_ENABLED)
  58. /* TODO Add support in TSO */
  59. #define DP_DESC_NUM_FRAG(x) 0
  60. /* disable TQM_BYPASS */
  61. #define TQM_BYPASS_WAR 0
  62. /* invalid peer id for reinject*/
  63. #define DP_INVALID_PEER 0XFFFE
  64. #define DP_RETRY_COUNT 7
  65. #ifdef QCA_DP_TX_FW_METADATA_V2
  66. #define DP_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)\
  67. HTT_TX_TCL_METADATA_V2_PDEV_ID_SET(_var, _val)
  68. #define DP_TX_TCL_METADATA_VALID_HTT_SET(_var, _val) \
  69. HTT_TX_TCL_METADATA_V2_VALID_HTT_SET(_var, _val)
  70. #define DP_TX_TCL_METADATA_TYPE_SET(_var, _val) \
  71. HTT_TX_TCL_METADATA_TYPE_V2_SET(_var, _val)
  72. #define DP_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val) \
  73. HTT_TX_TCL_METADATA_V2_HOST_INSPECTED_SET(_var, _val)
  74. #define DP_TX_TCL_METADATA_PEER_ID_SET(_var, _val) \
  75. HTT_TX_TCL_METADATA_V2_PEER_ID_SET(_var, _val)
  76. #define DP_TX_TCL_METADATA_VDEV_ID_SET(_var, _val) \
  77. HTT_TX_TCL_METADATA_V2_VDEV_ID_SET(_var, _val)
  78. #define DP_TCL_METADATA_TYPE_PEER_BASED \
  79. HTT_TCL_METADATA_V2_TYPE_PEER_BASED
  80. #define DP_TCL_METADATA_TYPE_VDEV_BASED \
  81. HTT_TCL_METADATA_V2_TYPE_VDEV_BASED
  82. #else
  83. #define DP_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)\
  84. HTT_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)
  85. #define DP_TX_TCL_METADATA_VALID_HTT_SET(_var, _val) \
  86. HTT_TX_TCL_METADATA_VALID_HTT_SET(_var, _val)
  87. #define DP_TX_TCL_METADATA_TYPE_SET(_var, _val) \
  88. HTT_TX_TCL_METADATA_TYPE_SET(_var, _val)
  89. #define DP_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val) \
  90. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val)
  91. #define DP_TX_TCL_METADATA_PEER_ID_SET(_var, _val) \
  92. HTT_TX_TCL_METADATA_PEER_ID_SET(_var, _val)
  93. #define DP_TX_TCL_METADATA_VDEV_ID_SET(_var, _val) \
  94. HTT_TX_TCL_METADATA_VDEV_ID_SET(_var, _val)
  95. #define DP_TCL_METADATA_TYPE_PEER_BASED \
  96. HTT_TCL_METADATA_TYPE_PEER_BASED
  97. #define DP_TCL_METADATA_TYPE_VDEV_BASED \
  98. HTT_TCL_METADATA_TYPE_VDEV_BASED
  99. #endif
  100. /*mapping between hal encrypt type and cdp_sec_type*/
  101. uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  102. HAL_TX_ENCRYPT_TYPE_WEP_128,
  103. HAL_TX_ENCRYPT_TYPE_WEP_104,
  104. HAL_TX_ENCRYPT_TYPE_WEP_40,
  105. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  106. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  107. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  108. HAL_TX_ENCRYPT_TYPE_WAPI,
  109. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  110. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  111. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  112. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  113. qdf_export_symbol(sec_type_map);
  114. #ifdef WLAN_FEATURE_DP_TX_DESC_HISTORY
  115. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  116. {
  117. enum dp_tx_event_type type;
  118. if (flags & DP_TX_DESC_FLAG_FLUSH)
  119. type = DP_TX_DESC_FLUSH;
  120. else if (flags & DP_TX_DESC_FLAG_TX_COMP_ERR)
  121. type = DP_TX_COMP_UNMAP_ERR;
  122. else if (flags & DP_TX_DESC_FLAG_COMPLETED_TX)
  123. type = DP_TX_COMP_UNMAP;
  124. else
  125. type = DP_TX_DESC_UNMAP;
  126. return type;
  127. }
  128. static inline void
  129. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  130. qdf_nbuf_t skb, uint32_t sw_cookie,
  131. enum dp_tx_event_type type)
  132. {
  133. struct dp_tx_desc_event *entry;
  134. uint32_t idx;
  135. if (qdf_unlikely(!soc->tx_tcl_history || !soc->tx_comp_history))
  136. return;
  137. switch (type) {
  138. case DP_TX_COMP_UNMAP:
  139. case DP_TX_COMP_UNMAP_ERR:
  140. case DP_TX_COMP_MSDU_EXT:
  141. idx = dp_history_get_next_index(&soc->tx_comp_history->index,
  142. DP_TX_COMP_HISTORY_SIZE);
  143. entry = &soc->tx_comp_history->entry[idx];
  144. break;
  145. case DP_TX_DESC_MAP:
  146. case DP_TX_DESC_UNMAP:
  147. case DP_TX_DESC_COOKIE:
  148. case DP_TX_DESC_FLUSH:
  149. idx = dp_history_get_next_index(&soc->tx_tcl_history->index,
  150. DP_TX_TCL_HISTORY_SIZE);
  151. entry = &soc->tx_tcl_history->entry[idx];
  152. break;
  153. default:
  154. dp_info_rl("Invalid dp_tx_event_type: %d", type);
  155. return;
  156. }
  157. entry->skb = skb;
  158. entry->paddr = paddr;
  159. entry->sw_cookie = sw_cookie;
  160. entry->type = type;
  161. entry->ts = qdf_get_log_timestamp();
  162. }
  163. static inline void
  164. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  165. struct qdf_tso_seg_elem_t *tso_seg,
  166. qdf_nbuf_t skb, uint32_t sw_cookie,
  167. enum dp_tx_event_type type)
  168. {
  169. int i;
  170. for (i = 1; i < tso_seg->seg.num_frags; i++) {
  171. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[i].paddr,
  172. skb, sw_cookie, type);
  173. }
  174. if (!tso_seg->next)
  175. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[0].paddr,
  176. skb, 0xFFFFFFFF, type);
  177. }
  178. static inline void
  179. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  180. qdf_nbuf_t skb, uint32_t sw_cookie,
  181. enum dp_tx_event_type type)
  182. {
  183. struct qdf_tso_seg_elem_t *curr_seg = tso_info.tso_seg_list;
  184. uint32_t num_segs = tso_info.num_segs;
  185. while (num_segs) {
  186. dp_tx_tso_seg_history_add(soc, curr_seg, skb, sw_cookie, type);
  187. curr_seg = curr_seg->next;
  188. num_segs--;
  189. }
  190. }
  191. #else
  192. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  193. {
  194. return DP_TX_DESC_INVAL_EVT;
  195. }
  196. static inline void
  197. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  198. qdf_nbuf_t skb, uint32_t sw_cookie,
  199. enum dp_tx_event_type type)
  200. {
  201. }
  202. static inline void
  203. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  204. struct qdf_tso_seg_elem_t *tso_seg,
  205. qdf_nbuf_t skb, uint32_t sw_cookie,
  206. enum dp_tx_event_type type)
  207. {
  208. }
  209. static inline void
  210. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  211. qdf_nbuf_t skb, uint32_t sw_cookie,
  212. enum dp_tx_event_type type)
  213. {
  214. }
  215. #endif /* WLAN_FEATURE_DP_TX_DESC_HISTORY */
  216. static int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc);
  217. /**
  218. * dp_is_tput_high() - Check if throughput is high
  219. *
  220. * @soc - core txrx main context
  221. *
  222. * The current function is based of the RTPM tput policy variable where RTPM is
  223. * avoided based on throughput.
  224. */
  225. static inline int dp_is_tput_high(struct dp_soc *soc)
  226. {
  227. return dp_get_rtpm_tput_policy_requirement(soc);
  228. }
  229. #if defined(FEATURE_TSO)
  230. /**
  231. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  232. *
  233. * @soc - core txrx main context
  234. * @seg_desc - tso segment descriptor
  235. * @num_seg_desc - tso number segment descriptor
  236. */
  237. static void dp_tx_tso_unmap_segment(
  238. struct dp_soc *soc,
  239. struct qdf_tso_seg_elem_t *seg_desc,
  240. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  241. {
  242. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  243. if (qdf_unlikely(!seg_desc)) {
  244. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  245. __func__, __LINE__);
  246. qdf_assert(0);
  247. } else if (qdf_unlikely(!num_seg_desc)) {
  248. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  249. __func__, __LINE__);
  250. qdf_assert(0);
  251. } else {
  252. bool is_last_seg;
  253. /* no tso segment left to do dma unmap */
  254. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  255. return;
  256. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  257. true : false;
  258. qdf_nbuf_unmap_tso_segment(soc->osdev,
  259. seg_desc, is_last_seg);
  260. num_seg_desc->num_seg.tso_cmn_num_seg--;
  261. }
  262. }
  263. /**
  264. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  265. * back to the freelist
  266. *
  267. * @soc - soc device handle
  268. * @tx_desc - Tx software descriptor
  269. */
  270. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  271. struct dp_tx_desc_s *tx_desc)
  272. {
  273. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  274. if (qdf_unlikely(!tx_desc->msdu_ext_desc->tso_desc)) {
  275. dp_tx_err("SO desc is NULL!");
  276. qdf_assert(0);
  277. } else if (qdf_unlikely(!tx_desc->msdu_ext_desc->tso_num_desc)) {
  278. dp_tx_err("TSO num desc is NULL!");
  279. qdf_assert(0);
  280. } else {
  281. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  282. (struct qdf_tso_num_seg_elem_t *)tx_desc->
  283. msdu_ext_desc->tso_num_desc;
  284. /* Add the tso num segment into the free list */
  285. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  286. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  287. tx_desc->msdu_ext_desc->
  288. tso_num_desc);
  289. tx_desc->msdu_ext_desc->tso_num_desc = NULL;
  290. DP_STATS_INC(tx_desc->pdev, tso_stats.tso_comp, 1);
  291. }
  292. /* Add the tso segment into the free list*/
  293. dp_tx_tso_desc_free(soc,
  294. tx_desc->pool_id, tx_desc->msdu_ext_desc->
  295. tso_desc);
  296. tx_desc->msdu_ext_desc->tso_desc = NULL;
  297. }
  298. }
  299. #else
  300. static void dp_tx_tso_unmap_segment(
  301. struct dp_soc *soc,
  302. struct qdf_tso_seg_elem_t *seg_desc,
  303. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  304. {
  305. }
  306. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  307. struct dp_tx_desc_s *tx_desc)
  308. {
  309. }
  310. #endif
  311. /**
  312. * dp_tx_desc_release() - Release Tx Descriptor
  313. * @tx_desc : Tx Descriptor
  314. * @desc_pool_id: Descriptor Pool ID
  315. *
  316. * Deallocate all resources attached to Tx descriptor and free the Tx
  317. * descriptor.
  318. *
  319. * Return:
  320. */
  321. void
  322. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  323. {
  324. struct dp_pdev *pdev = tx_desc->pdev;
  325. struct dp_soc *soc;
  326. uint8_t comp_status = 0;
  327. qdf_assert(pdev);
  328. soc = pdev->soc;
  329. dp_tx_outstanding_dec(pdev);
  330. if (tx_desc->msdu_ext_desc) {
  331. if (tx_desc->frm_type == dp_tx_frm_tso)
  332. dp_tx_tso_desc_release(soc, tx_desc);
  333. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  334. dp_tx_me_free_buf(tx_desc->pdev,
  335. tx_desc->msdu_ext_desc->me_buffer);
  336. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  337. }
  338. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  339. qdf_atomic_dec(&soc->num_tx_exception);
  340. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  341. tx_desc->buffer_src)
  342. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  343. soc->hal_soc);
  344. else
  345. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  346. dp_tx_debug("Tx Completion Release desc %d status %d outstanding %d",
  347. tx_desc->id, comp_status,
  348. qdf_atomic_read(&pdev->num_tx_outstanding));
  349. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  350. return;
  351. }
  352. /**
  353. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  354. * @vdev: DP vdev Handle
  355. * @nbuf: skb
  356. * @msdu_info: msdu_info required to create HTT metadata
  357. *
  358. * Prepares and fills HTT metadata in the frame pre-header for special frames
  359. * that should be transmitted using varying transmit parameters.
  360. * There are 2 VDEV modes that currently needs this special metadata -
  361. * 1) Mesh Mode
  362. * 2) DSRC Mode
  363. *
  364. * Return: HTT metadata size
  365. *
  366. */
  367. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  368. struct dp_tx_msdu_info_s *msdu_info)
  369. {
  370. uint32_t *meta_data = msdu_info->meta_data;
  371. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  372. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  373. uint8_t htt_desc_size;
  374. /* Size rounded of multiple of 8 bytes */
  375. uint8_t htt_desc_size_aligned;
  376. uint8_t *hdr = NULL;
  377. /*
  378. * Metadata - HTT MSDU Extension header
  379. */
  380. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  381. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  382. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  383. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  384. meta_data[0]) ||
  385. msdu_info->exception_fw) {
  386. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  387. htt_desc_size_aligned)) {
  388. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  389. htt_desc_size_aligned);
  390. if (!nbuf) {
  391. /*
  392. * qdf_nbuf_realloc_headroom won't do skb_clone
  393. * as skb_realloc_headroom does. so, no free is
  394. * needed here.
  395. */
  396. DP_STATS_INC(vdev,
  397. tx_i.dropped.headroom_insufficient,
  398. 1);
  399. qdf_print(" %s[%d] skb_realloc_headroom failed",
  400. __func__, __LINE__);
  401. return 0;
  402. }
  403. }
  404. /* Fill and add HTT metaheader */
  405. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  406. if (!hdr) {
  407. dp_tx_err("Error in filling HTT metadata");
  408. return 0;
  409. }
  410. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  411. } else if (vdev->opmode == wlan_op_mode_ocb) {
  412. /* Todo - Add support for DSRC */
  413. }
  414. return htt_desc_size_aligned;
  415. }
  416. /**
  417. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  418. * @tso_seg: TSO segment to process
  419. * @ext_desc: Pointer to MSDU extension descriptor
  420. *
  421. * Return: void
  422. */
  423. #if defined(FEATURE_TSO)
  424. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  425. void *ext_desc)
  426. {
  427. uint8_t num_frag;
  428. uint32_t tso_flags;
  429. /*
  430. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  431. * tcp_flag_mask
  432. *
  433. * Checksum enable flags are set in TCL descriptor and not in Extension
  434. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  435. */
  436. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  437. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  438. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  439. tso_seg->tso_flags.ip_len);
  440. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  441. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  442. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  443. uint32_t lo = 0;
  444. uint32_t hi = 0;
  445. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  446. (tso_seg->tso_frags[num_frag].length));
  447. qdf_dmaaddr_to_32s(
  448. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  449. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  450. tso_seg->tso_frags[num_frag].length);
  451. }
  452. return;
  453. }
  454. #else
  455. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  456. void *ext_desc)
  457. {
  458. return;
  459. }
  460. #endif
  461. #if defined(FEATURE_TSO)
  462. /**
  463. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  464. * allocated and free them
  465. *
  466. * @soc: soc handle
  467. * @free_seg: list of tso segments
  468. * @msdu_info: msdu descriptor
  469. *
  470. * Return - void
  471. */
  472. static void dp_tx_free_tso_seg_list(
  473. struct dp_soc *soc,
  474. struct qdf_tso_seg_elem_t *free_seg,
  475. struct dp_tx_msdu_info_s *msdu_info)
  476. {
  477. struct qdf_tso_seg_elem_t *next_seg;
  478. while (free_seg) {
  479. next_seg = free_seg->next;
  480. dp_tx_tso_desc_free(soc,
  481. msdu_info->tx_queue.desc_pool_id,
  482. free_seg);
  483. free_seg = next_seg;
  484. }
  485. }
  486. /**
  487. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  488. * allocated and free them
  489. *
  490. * @soc: soc handle
  491. * @free_num_seg: list of tso number segments
  492. * @msdu_info: msdu descriptor
  493. * Return - void
  494. */
  495. static void dp_tx_free_tso_num_seg_list(
  496. struct dp_soc *soc,
  497. struct qdf_tso_num_seg_elem_t *free_num_seg,
  498. struct dp_tx_msdu_info_s *msdu_info)
  499. {
  500. struct qdf_tso_num_seg_elem_t *next_num_seg;
  501. while (free_num_seg) {
  502. next_num_seg = free_num_seg->next;
  503. dp_tso_num_seg_free(soc,
  504. msdu_info->tx_queue.desc_pool_id,
  505. free_num_seg);
  506. free_num_seg = next_num_seg;
  507. }
  508. }
  509. /**
  510. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  511. * do dma unmap for each segment
  512. *
  513. * @soc: soc handle
  514. * @free_seg: list of tso segments
  515. * @num_seg_desc: tso number segment descriptor
  516. *
  517. * Return - void
  518. */
  519. static void dp_tx_unmap_tso_seg_list(
  520. struct dp_soc *soc,
  521. struct qdf_tso_seg_elem_t *free_seg,
  522. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  523. {
  524. struct qdf_tso_seg_elem_t *next_seg;
  525. if (qdf_unlikely(!num_seg_desc)) {
  526. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  527. return;
  528. }
  529. while (free_seg) {
  530. next_seg = free_seg->next;
  531. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  532. free_seg = next_seg;
  533. }
  534. }
  535. #ifdef FEATURE_TSO_STATS
  536. /**
  537. * dp_tso_get_stats_idx: Retrieve the tso packet id
  538. * @pdev - pdev handle
  539. *
  540. * Return: id
  541. */
  542. static uint32_t dp_tso_get_stats_idx(struct dp_pdev *pdev)
  543. {
  544. uint32_t stats_idx;
  545. stats_idx = (((uint32_t)qdf_atomic_inc_return(&pdev->tso_idx))
  546. % CDP_MAX_TSO_PACKETS);
  547. return stats_idx;
  548. }
  549. #else
  550. static int dp_tso_get_stats_idx(struct dp_pdev *pdev)
  551. {
  552. return 0;
  553. }
  554. #endif /* FEATURE_TSO_STATS */
  555. /**
  556. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  557. * free the tso segments descriptor and
  558. * tso num segments descriptor
  559. *
  560. * @soc: soc handle
  561. * @msdu_info: msdu descriptor
  562. * @tso_seg_unmap: flag to show if dma unmap is necessary
  563. *
  564. * Return - void
  565. */
  566. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  567. struct dp_tx_msdu_info_s *msdu_info,
  568. bool tso_seg_unmap)
  569. {
  570. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  571. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  572. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  573. tso_info->tso_num_seg_list;
  574. /* do dma unmap for each segment */
  575. if (tso_seg_unmap)
  576. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  577. /* free all tso number segment descriptor though looks only have 1 */
  578. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  579. /* free all tso segment descriptor */
  580. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  581. }
  582. /**
  583. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  584. * @vdev: virtual device handle
  585. * @msdu: network buffer
  586. * @msdu_info: meta data associated with the msdu
  587. *
  588. * Return: QDF_STATUS_SUCCESS success
  589. */
  590. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  591. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  592. {
  593. struct qdf_tso_seg_elem_t *tso_seg;
  594. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  595. struct dp_soc *soc = vdev->pdev->soc;
  596. struct dp_pdev *pdev = vdev->pdev;
  597. struct qdf_tso_info_t *tso_info;
  598. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  599. tso_info = &msdu_info->u.tso_info;
  600. tso_info->curr_seg = NULL;
  601. tso_info->tso_seg_list = NULL;
  602. tso_info->num_segs = num_seg;
  603. msdu_info->frm_type = dp_tx_frm_tso;
  604. tso_info->tso_num_seg_list = NULL;
  605. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  606. while (num_seg) {
  607. tso_seg = dp_tx_tso_desc_alloc(
  608. soc, msdu_info->tx_queue.desc_pool_id);
  609. if (tso_seg) {
  610. tso_seg->next = tso_info->tso_seg_list;
  611. tso_info->tso_seg_list = tso_seg;
  612. num_seg--;
  613. } else {
  614. dp_err_rl("Failed to alloc tso seg desc");
  615. DP_STATS_INC_PKT(vdev->pdev,
  616. tso_stats.tso_no_mem_dropped, 1,
  617. qdf_nbuf_len(msdu));
  618. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  619. return QDF_STATUS_E_NOMEM;
  620. }
  621. }
  622. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  623. tso_num_seg = dp_tso_num_seg_alloc(soc,
  624. msdu_info->tx_queue.desc_pool_id);
  625. if (tso_num_seg) {
  626. tso_num_seg->next = tso_info->tso_num_seg_list;
  627. tso_info->tso_num_seg_list = tso_num_seg;
  628. } else {
  629. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  630. __func__);
  631. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  632. return QDF_STATUS_E_NOMEM;
  633. }
  634. msdu_info->num_seg =
  635. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  636. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  637. msdu_info->num_seg);
  638. if (!(msdu_info->num_seg)) {
  639. /*
  640. * Free allocated TSO seg desc and number seg desc,
  641. * do unmap for segments if dma map has done.
  642. */
  643. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  644. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  645. return QDF_STATUS_E_INVAL;
  646. }
  647. dp_tx_tso_history_add(soc, msdu_info->u.tso_info,
  648. msdu, 0, DP_TX_DESC_MAP);
  649. tso_info->curr_seg = tso_info->tso_seg_list;
  650. tso_info->msdu_stats_idx = dp_tso_get_stats_idx(pdev);
  651. dp_tso_packet_update(pdev, tso_info->msdu_stats_idx,
  652. msdu, msdu_info->num_seg);
  653. dp_tso_segment_stats_update(pdev, tso_info->tso_seg_list,
  654. tso_info->msdu_stats_idx);
  655. dp_stats_tso_segment_histogram_update(pdev, msdu_info->num_seg);
  656. return QDF_STATUS_SUCCESS;
  657. }
  658. #else
  659. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  660. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  661. {
  662. return QDF_STATUS_E_NOMEM;
  663. }
  664. #endif
  665. QDF_COMPILE_TIME_ASSERT(dp_tx_htt_metadata_len_check,
  666. (DP_TX_MSDU_INFO_META_DATA_DWORDS * 4 >=
  667. sizeof(struct htt_tx_msdu_desc_ext2_t)));
  668. /**
  669. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  670. * @vdev: DP Vdev handle
  671. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  672. * @desc_pool_id: Descriptor Pool ID
  673. *
  674. * Return:
  675. */
  676. static
  677. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  678. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  679. {
  680. uint8_t i;
  681. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  682. struct dp_tx_seg_info_s *seg_info;
  683. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  684. struct dp_soc *soc = vdev->pdev->soc;
  685. /* Allocate an extension descriptor */
  686. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  687. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  688. if (!msdu_ext_desc) {
  689. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  690. return NULL;
  691. }
  692. if (msdu_info->exception_fw &&
  693. qdf_unlikely(vdev->mesh_vdev)) {
  694. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  695. &msdu_info->meta_data[0],
  696. sizeof(struct htt_tx_msdu_desc_ext2_t));
  697. qdf_atomic_inc(&soc->num_tx_exception);
  698. msdu_ext_desc->flags |= DP_TX_EXT_DESC_FLAG_METADATA_VALID;
  699. }
  700. switch (msdu_info->frm_type) {
  701. case dp_tx_frm_sg:
  702. case dp_tx_frm_me:
  703. case dp_tx_frm_raw:
  704. seg_info = msdu_info->u.sg_info.curr_seg;
  705. /* Update the buffer pointers in MSDU Extension Descriptor */
  706. for (i = 0; i < seg_info->frag_cnt; i++) {
  707. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  708. seg_info->frags[i].paddr_lo,
  709. seg_info->frags[i].paddr_hi,
  710. seg_info->frags[i].len);
  711. }
  712. break;
  713. case dp_tx_frm_tso:
  714. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  715. &cached_ext_desc[0]);
  716. break;
  717. default:
  718. break;
  719. }
  720. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  721. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  722. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  723. msdu_ext_desc->vaddr);
  724. return msdu_ext_desc;
  725. }
  726. /**
  727. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  728. *
  729. * @skb: skb to be traced
  730. * @msdu_id: msdu_id of the packet
  731. * @vdev_id: vdev_id of the packet
  732. *
  733. * Return: None
  734. */
  735. #ifdef DP_DISABLE_TX_PKT_TRACE
  736. static void dp_tx_trace_pkt(struct dp_soc *soc,
  737. qdf_nbuf_t skb, uint16_t msdu_id,
  738. uint8_t vdev_id)
  739. {
  740. }
  741. #else
  742. static void dp_tx_trace_pkt(struct dp_soc *soc,
  743. qdf_nbuf_t skb, uint16_t msdu_id,
  744. uint8_t vdev_id)
  745. {
  746. if (dp_is_tput_high(soc))
  747. return;
  748. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  749. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  750. DPTRACE(qdf_dp_trace_ptr(skb,
  751. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  752. QDF_TRACE_DEFAULT_PDEV_ID,
  753. qdf_nbuf_data_addr(skb),
  754. sizeof(qdf_nbuf_data(skb)),
  755. msdu_id, vdev_id, 0));
  756. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  757. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  758. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  759. msdu_id, QDF_TX));
  760. }
  761. #endif
  762. #ifdef WLAN_DP_FEATURE_MARK_ICMP_REQ_TO_FW
  763. /**
  764. * dp_tx_is_nbuf_marked_exception() - Check if the packet has been marked as
  765. * exception by the upper layer (OS_IF)
  766. * @soc: DP soc handle
  767. * @nbuf: packet to be transmitted
  768. *
  769. * Returns: 1 if the packet is marked as exception,
  770. * 0, if the packet is not marked as exception.
  771. */
  772. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  773. qdf_nbuf_t nbuf)
  774. {
  775. return QDF_NBUF_CB_TX_PACKET_TO_FW(nbuf);
  776. }
  777. #else
  778. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  779. qdf_nbuf_t nbuf)
  780. {
  781. return 0;
  782. }
  783. #endif
  784. #ifdef DP_TRAFFIC_END_INDICATION
  785. /**
  786. * dp_tx_get_traffic_end_indication_pkt() - Allocate and prepare packet to send
  787. * as indication to fw to inform that
  788. * data stream has ended
  789. * @vdev: DP vdev handle
  790. * @nbuf: original buffer from network stack
  791. *
  792. * Return: NULL on failure,
  793. * nbuf on success
  794. */
  795. static inline qdf_nbuf_t
  796. dp_tx_get_traffic_end_indication_pkt(struct dp_vdev *vdev,
  797. qdf_nbuf_t nbuf)
  798. {
  799. /* Packet length should be enough to copy upto L3 header */
  800. uint8_t end_nbuf_len = 64;
  801. uint8_t htt_desc_size_aligned;
  802. uint8_t htt_desc_size;
  803. qdf_nbuf_t end_nbuf;
  804. if (qdf_unlikely(QDF_NBUF_CB_GET_PACKET_TYPE(nbuf) ==
  805. QDF_NBUF_CB_PACKET_TYPE_END_INDICATION)) {
  806. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  807. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  808. end_nbuf = qdf_nbuf_queue_remove(&vdev->end_ind_pkt_q);
  809. if (!end_nbuf) {
  810. end_nbuf = qdf_nbuf_alloc(NULL,
  811. (htt_desc_size_aligned +
  812. end_nbuf_len),
  813. htt_desc_size_aligned,
  814. 8, false);
  815. if (!end_nbuf) {
  816. dp_err("Packet allocation failed");
  817. goto out;
  818. }
  819. } else {
  820. qdf_nbuf_reset(end_nbuf, htt_desc_size_aligned, 8);
  821. }
  822. qdf_mem_copy(qdf_nbuf_data(end_nbuf), qdf_nbuf_data(nbuf),
  823. end_nbuf_len);
  824. qdf_nbuf_set_pktlen(end_nbuf, end_nbuf_len);
  825. return end_nbuf;
  826. }
  827. out:
  828. return NULL;
  829. }
  830. /**
  831. * dp_tx_send_traffic_end_indication_pkt() - Send indication packet to FW
  832. * via exception path.
  833. * @vdev: DP vdev handle
  834. * @end_nbuf: skb to send as indication
  835. * @msdu_info: msdu_info of original nbuf
  836. * @peer_id: peer id
  837. *
  838. * Return: None
  839. */
  840. static inline void
  841. dp_tx_send_traffic_end_indication_pkt(struct dp_vdev *vdev,
  842. qdf_nbuf_t end_nbuf,
  843. struct dp_tx_msdu_info_s *msdu_info,
  844. uint16_t peer_id)
  845. {
  846. struct dp_tx_msdu_info_s e_msdu_info = {0};
  847. qdf_nbuf_t nbuf;
  848. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  849. (struct htt_tx_msdu_desc_ext2_t *)(e_msdu_info.meta_data);
  850. e_msdu_info.tx_queue = msdu_info->tx_queue;
  851. e_msdu_info.tid = msdu_info->tid;
  852. e_msdu_info.exception_fw = 1;
  853. desc_ext->host_tx_desc_pool = 1;
  854. desc_ext->traffic_end_indication = 1;
  855. nbuf = dp_tx_send_msdu_single(vdev, end_nbuf, &e_msdu_info,
  856. peer_id, NULL);
  857. if (nbuf) {
  858. dp_err("Traffic end indication packet tx failed");
  859. qdf_nbuf_free(nbuf);
  860. }
  861. }
  862. /**
  863. * dp_tx_traffic_end_indication_set_desc_flag() - Set tx descriptor flag to
  864. * mark it trafic end indication
  865. * packet.
  866. * @tx_desc: Tx descriptor pointer
  867. * @msdu_info: msdu_info structure pointer
  868. *
  869. * Return: None
  870. */
  871. static inline void
  872. dp_tx_traffic_end_indication_set_desc_flag(struct dp_tx_desc_s *tx_desc,
  873. struct dp_tx_msdu_info_s *msdu_info)
  874. {
  875. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  876. (struct htt_tx_msdu_desc_ext2_t *)(msdu_info->meta_data);
  877. if (qdf_unlikely(desc_ext->traffic_end_indication))
  878. tx_desc->flags |= DP_TX_DESC_FLAG_TRAFFIC_END_IND;
  879. }
  880. /**
  881. * dp_tx_traffic_end_indication_enq_ind_pkt() - Enqueue the packet instead of
  882. * freeing which are associated
  883. * with traffic end indication
  884. * flagged descriptor.
  885. * @soc: dp soc handle
  886. * @desc: Tx descriptor pointer
  887. * @nbuf: buffer pointer
  888. *
  889. * Return: True if packet gets enqueued else false
  890. */
  891. static bool
  892. dp_tx_traffic_end_indication_enq_ind_pkt(struct dp_soc *soc,
  893. struct dp_tx_desc_s *desc,
  894. qdf_nbuf_t nbuf)
  895. {
  896. struct dp_vdev *vdev = NULL;
  897. if (qdf_unlikely((desc->flags &
  898. DP_TX_DESC_FLAG_TRAFFIC_END_IND) != 0)) {
  899. vdev = dp_vdev_get_ref_by_id(soc, desc->vdev_id,
  900. DP_MOD_ID_TX_COMP);
  901. if (vdev) {
  902. qdf_nbuf_queue_add(&vdev->end_ind_pkt_q, nbuf);
  903. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_COMP);
  904. return true;
  905. }
  906. }
  907. return false;
  908. }
  909. /**
  910. * dp_tx_traffic_end_indication_is_enabled() - get the feature
  911. * enable/disable status
  912. * @vdev: dp vdev handle
  913. *
  914. * Return: True if feature is enable else false
  915. */
  916. static inline bool
  917. dp_tx_traffic_end_indication_is_enabled(struct dp_vdev *vdev)
  918. {
  919. return qdf_unlikely(vdev->traffic_end_ind_en);
  920. }
  921. static inline qdf_nbuf_t
  922. dp_tx_send_msdu_single_wrapper(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  923. struct dp_tx_msdu_info_s *msdu_info,
  924. uint16_t peer_id, qdf_nbuf_t end_nbuf)
  925. {
  926. if (dp_tx_traffic_end_indication_is_enabled(vdev))
  927. end_nbuf = dp_tx_get_traffic_end_indication_pkt(vdev, nbuf);
  928. nbuf = dp_tx_send_msdu_single(vdev, nbuf, msdu_info, peer_id, NULL);
  929. if (qdf_unlikely(end_nbuf))
  930. dp_tx_send_traffic_end_indication_pkt(vdev, end_nbuf,
  931. msdu_info, peer_id);
  932. return nbuf;
  933. }
  934. #else
  935. static inline qdf_nbuf_t
  936. dp_tx_get_traffic_end_indication_pkt(struct dp_vdev *vdev,
  937. qdf_nbuf_t nbuf)
  938. {
  939. return NULL;
  940. }
  941. static inline void
  942. dp_tx_send_traffic_end_indication_pkt(struct dp_vdev *vdev,
  943. qdf_nbuf_t end_nbuf,
  944. struct dp_tx_msdu_info_s *msdu_info,
  945. uint16_t peer_id)
  946. {}
  947. static inline void
  948. dp_tx_traffic_end_indication_set_desc_flag(struct dp_tx_desc_s *tx_desc,
  949. struct dp_tx_msdu_info_s *msdu_info)
  950. {}
  951. static inline bool
  952. dp_tx_traffic_end_indication_enq_ind_pkt(struct dp_soc *soc,
  953. struct dp_tx_desc_s *desc,
  954. qdf_nbuf_t nbuf)
  955. {
  956. return false;
  957. }
  958. static inline bool
  959. dp_tx_traffic_end_indication_is_enabled(struct dp_vdev *vdev)
  960. {
  961. return false;
  962. }
  963. static inline qdf_nbuf_t
  964. dp_tx_send_msdu_single_wrapper(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  965. struct dp_tx_msdu_info_s *msdu_info,
  966. uint16_t peer_id, qdf_nbuf_t end_nbuf)
  967. {
  968. return dp_tx_send_msdu_single(vdev, nbuf, msdu_info, peer_id, NULL);
  969. }
  970. #endif
  971. /**
  972. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  973. * @vdev: DP vdev handle
  974. * @nbuf: skb
  975. * @desc_pool_id: Descriptor pool ID
  976. * @meta_data: Metadata to the fw
  977. * @tx_exc_metadata: Handle that holds exception path metadata
  978. * Allocate and prepare Tx descriptor with msdu information.
  979. *
  980. * Return: Pointer to Tx Descriptor on success,
  981. * NULL on failure
  982. */
  983. static
  984. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  985. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  986. struct dp_tx_msdu_info_s *msdu_info,
  987. struct cdp_tx_exception_metadata *tx_exc_metadata)
  988. {
  989. uint8_t align_pad;
  990. uint8_t is_exception = 0;
  991. uint8_t htt_hdr_size;
  992. struct dp_tx_desc_s *tx_desc;
  993. struct dp_pdev *pdev = vdev->pdev;
  994. struct dp_soc *soc = pdev->soc;
  995. if (dp_tx_limit_check(vdev))
  996. return NULL;
  997. /* Allocate software Tx descriptor */
  998. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  999. if (qdf_unlikely(!tx_desc)) {
  1000. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  1001. DP_STATS_INC(vdev, tx_i.dropped.desc_na_exc_alloc_fail.num, 1);
  1002. return NULL;
  1003. }
  1004. dp_tx_outstanding_inc(pdev);
  1005. /* Initialize the SW tx descriptor */
  1006. tx_desc->nbuf = nbuf;
  1007. tx_desc->frm_type = dp_tx_frm_std;
  1008. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  1009. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  1010. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  1011. tx_desc->vdev_id = vdev->vdev_id;
  1012. tx_desc->pdev = pdev;
  1013. tx_desc->msdu_ext_desc = NULL;
  1014. tx_desc->pkt_offset = 0;
  1015. tx_desc->length = qdf_nbuf_headlen(nbuf);
  1016. tx_desc->shinfo_addr = skb_end_pointer(nbuf);
  1017. dp_tx_trace_pkt(soc, nbuf, tx_desc->id, vdev->vdev_id);
  1018. if (qdf_unlikely(vdev->multipass_en)) {
  1019. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  1020. goto failure;
  1021. }
  1022. /* Packets marked by upper layer (OS-IF) to be sent to FW */
  1023. if (dp_tx_is_nbuf_marked_exception(soc, nbuf))
  1024. is_exception = 1;
  1025. /*
  1026. * For special modes (vdev_type == ocb or mesh), data frames should be
  1027. * transmitted using varying transmit parameters (tx spec) which include
  1028. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  1029. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  1030. * These frames are sent as exception packets to firmware.
  1031. *
  1032. * HW requirement is that metadata should always point to a
  1033. * 8-byte aligned address. So we add alignment pad to start of buffer.
  1034. * HTT Metadata should be ensured to be multiple of 8-bytes,
  1035. * to get 8-byte aligned start address along with align_pad added
  1036. *
  1037. * |-----------------------------|
  1038. * | |
  1039. * |-----------------------------| <-----Buffer Pointer Address given
  1040. * | | ^ in HW descriptor (aligned)
  1041. * | HTT Metadata | |
  1042. * | | |
  1043. * | | | Packet Offset given in descriptor
  1044. * | | |
  1045. * |-----------------------------| |
  1046. * | Alignment Pad | v
  1047. * |-----------------------------| <----- Actual buffer start address
  1048. * | SKB Data | (Unaligned)
  1049. * | |
  1050. * | |
  1051. * | |
  1052. * | |
  1053. * | |
  1054. * |-----------------------------|
  1055. */
  1056. if (qdf_unlikely((msdu_info->exception_fw)) ||
  1057. (vdev->opmode == wlan_op_mode_ocb) ||
  1058. (tx_exc_metadata &&
  1059. tx_exc_metadata->is_tx_sniffer)) {
  1060. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  1061. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  1062. DP_STATS_INC(vdev,
  1063. tx_i.dropped.headroom_insufficient, 1);
  1064. goto failure;
  1065. }
  1066. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  1067. dp_tx_err("qdf_nbuf_push_head failed");
  1068. goto failure;
  1069. }
  1070. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  1071. msdu_info);
  1072. if (htt_hdr_size == 0)
  1073. goto failure;
  1074. tx_desc->length = qdf_nbuf_headlen(nbuf);
  1075. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  1076. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1077. dp_tx_traffic_end_indication_set_desc_flag(tx_desc,
  1078. msdu_info);
  1079. is_exception = 1;
  1080. tx_desc->length -= tx_desc->pkt_offset;
  1081. }
  1082. #if !TQM_BYPASS_WAR
  1083. if (is_exception || tx_exc_metadata)
  1084. #endif
  1085. {
  1086. /* Temporary WAR due to TQM VP issues */
  1087. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1088. qdf_atomic_inc(&soc->num_tx_exception);
  1089. }
  1090. return tx_desc;
  1091. failure:
  1092. dp_tx_desc_release(tx_desc, desc_pool_id);
  1093. return NULL;
  1094. }
  1095. /**
  1096. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  1097. * @vdev: DP vdev handle
  1098. * @nbuf: skb
  1099. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  1100. * @desc_pool_id : Descriptor Pool ID
  1101. *
  1102. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  1103. * information. For frames wth fragments, allocate and prepare
  1104. * an MSDU extension descriptor
  1105. *
  1106. * Return: Pointer to Tx Descriptor on success,
  1107. * NULL on failure
  1108. */
  1109. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  1110. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  1111. uint8_t desc_pool_id)
  1112. {
  1113. struct dp_tx_desc_s *tx_desc;
  1114. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  1115. struct dp_pdev *pdev = vdev->pdev;
  1116. struct dp_soc *soc = pdev->soc;
  1117. if (dp_tx_limit_check(vdev))
  1118. return NULL;
  1119. /* Allocate software Tx descriptor */
  1120. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  1121. if (!tx_desc) {
  1122. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  1123. return NULL;
  1124. }
  1125. dp_tx_tso_seg_history_add(soc, msdu_info->u.tso_info.curr_seg,
  1126. nbuf, tx_desc->id, DP_TX_DESC_COOKIE);
  1127. dp_tx_outstanding_inc(pdev);
  1128. /* Initialize the SW tx descriptor */
  1129. tx_desc->nbuf = nbuf;
  1130. tx_desc->frm_type = msdu_info->frm_type;
  1131. tx_desc->tx_encap_type = vdev->tx_encap_type;
  1132. tx_desc->vdev_id = vdev->vdev_id;
  1133. tx_desc->pdev = pdev;
  1134. tx_desc->pkt_offset = 0;
  1135. dp_tx_trace_pkt(soc, nbuf, tx_desc->id, vdev->vdev_id);
  1136. /* Handle scattered frames - TSO/SG/ME */
  1137. /* Allocate and prepare an extension descriptor for scattered frames */
  1138. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  1139. if (!msdu_ext_desc) {
  1140. dp_tx_info("Tx Extension Descriptor Alloc Fail");
  1141. goto failure;
  1142. }
  1143. #if TQM_BYPASS_WAR
  1144. /* Temporary WAR due to TQM VP issues */
  1145. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1146. qdf_atomic_inc(&soc->num_tx_exception);
  1147. #endif
  1148. if (qdf_unlikely(msdu_info->exception_fw))
  1149. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1150. tx_desc->msdu_ext_desc = msdu_ext_desc;
  1151. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  1152. msdu_ext_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  1153. msdu_ext_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  1154. tx_desc->dma_addr = msdu_ext_desc->paddr;
  1155. if (msdu_ext_desc->flags & DP_TX_EXT_DESC_FLAG_METADATA_VALID)
  1156. tx_desc->length = HAL_TX_EXT_DESC_WITH_META_DATA;
  1157. else
  1158. tx_desc->length = HAL_TX_EXTENSION_DESC_LEN_BYTES;
  1159. return tx_desc;
  1160. failure:
  1161. dp_tx_desc_release(tx_desc, desc_pool_id);
  1162. return NULL;
  1163. }
  1164. /**
  1165. * dp_tx_prepare_raw() - Prepare RAW packet TX
  1166. * @vdev: DP vdev handle
  1167. * @nbuf: buffer pointer
  1168. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1169. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  1170. * descriptor
  1171. *
  1172. * Return:
  1173. */
  1174. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1175. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1176. {
  1177. qdf_nbuf_t curr_nbuf = NULL;
  1178. uint16_t total_len = 0;
  1179. qdf_dma_addr_t paddr;
  1180. int32_t i;
  1181. int32_t mapped_buf_num = 0;
  1182. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  1183. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1184. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  1185. /* Continue only if frames are of DATA type */
  1186. if (!DP_FRAME_IS_DATA(qos_wh)) {
  1187. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  1188. dp_tx_debug("Pkt. recd is of not data type");
  1189. goto error;
  1190. }
  1191. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  1192. if (vdev->raw_mode_war &&
  1193. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  1194. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  1195. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  1196. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  1197. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  1198. /*
  1199. * Number of nbuf's must not exceed the size of the frags
  1200. * array in seg_info.
  1201. */
  1202. if (i >= DP_TX_MAX_NUM_FRAGS) {
  1203. dp_err_rl("nbuf cnt exceeds the max number of segs");
  1204. DP_STATS_INC(vdev, tx_i.raw.num_frags_overflow_err, 1);
  1205. goto error;
  1206. }
  1207. if (QDF_STATUS_SUCCESS !=
  1208. qdf_nbuf_map_nbytes_single(vdev->osdev,
  1209. curr_nbuf,
  1210. QDF_DMA_TO_DEVICE,
  1211. curr_nbuf->len)) {
  1212. dp_tx_err("%s dma map error ", __func__);
  1213. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  1214. goto error;
  1215. }
  1216. /* Update the count of mapped nbuf's */
  1217. mapped_buf_num++;
  1218. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  1219. seg_info->frags[i].paddr_lo = paddr;
  1220. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  1221. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  1222. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  1223. total_len += qdf_nbuf_len(curr_nbuf);
  1224. }
  1225. seg_info->frag_cnt = i;
  1226. seg_info->total_len = total_len;
  1227. seg_info->next = NULL;
  1228. sg_info->curr_seg = seg_info;
  1229. msdu_info->frm_type = dp_tx_frm_raw;
  1230. msdu_info->num_seg = 1;
  1231. return nbuf;
  1232. error:
  1233. i = 0;
  1234. while (nbuf) {
  1235. curr_nbuf = nbuf;
  1236. if (i < mapped_buf_num) {
  1237. qdf_nbuf_unmap_nbytes_single(vdev->osdev, curr_nbuf,
  1238. QDF_DMA_TO_DEVICE,
  1239. curr_nbuf->len);
  1240. i++;
  1241. }
  1242. nbuf = qdf_nbuf_next(nbuf);
  1243. qdf_nbuf_free(curr_nbuf);
  1244. }
  1245. return NULL;
  1246. }
  1247. /**
  1248. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  1249. * @soc: DP soc handle
  1250. * @nbuf: Buffer pointer
  1251. *
  1252. * unmap the chain of nbufs that belong to this RAW frame.
  1253. *
  1254. * Return: None
  1255. */
  1256. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  1257. qdf_nbuf_t nbuf)
  1258. {
  1259. qdf_nbuf_t cur_nbuf = nbuf;
  1260. do {
  1261. qdf_nbuf_unmap_nbytes_single(soc->osdev, cur_nbuf,
  1262. QDF_DMA_TO_DEVICE,
  1263. cur_nbuf->len);
  1264. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  1265. } while (cur_nbuf);
  1266. }
  1267. #ifdef VDEV_PEER_PROTOCOL_COUNT
  1268. void dp_vdev_peer_stats_update_protocol_cnt_tx(struct dp_vdev *vdev_hdl,
  1269. qdf_nbuf_t nbuf)
  1270. {
  1271. qdf_nbuf_t nbuf_local;
  1272. struct dp_vdev *vdev_local = vdev_hdl;
  1273. do {
  1274. if (qdf_likely(!((vdev_local)->peer_protocol_count_track)))
  1275. break;
  1276. nbuf_local = nbuf;
  1277. if (qdf_unlikely(((vdev_local)->tx_encap_type) ==
  1278. htt_cmn_pkt_type_raw))
  1279. break;
  1280. else if (qdf_unlikely(qdf_nbuf_is_nonlinear((nbuf_local))))
  1281. break;
  1282. else if (qdf_nbuf_is_tso((nbuf_local)))
  1283. break;
  1284. dp_vdev_peer_stats_update_protocol_cnt((vdev_local),
  1285. (nbuf_local),
  1286. NULL, 1, 0);
  1287. } while (0);
  1288. }
  1289. #endif
  1290. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  1291. /**
  1292. * dp_tx_update_stats() - Update soc level tx stats
  1293. * @soc: DP soc handle
  1294. * @tx_desc: TX descriptor reference
  1295. * @ring_id: TCL ring id
  1296. *
  1297. * Returns: none
  1298. */
  1299. void dp_tx_update_stats(struct dp_soc *soc,
  1300. struct dp_tx_desc_s *tx_desc,
  1301. uint8_t ring_id)
  1302. {
  1303. uint32_t stats_len = 0;
  1304. if (tx_desc->frm_type == dp_tx_frm_tso)
  1305. stats_len = tx_desc->msdu_ext_desc->tso_desc->seg.total_len;
  1306. else
  1307. stats_len = qdf_nbuf_len(tx_desc->nbuf);
  1308. DP_STATS_INC_PKT(soc, tx.egress[ring_id], 1, stats_len);
  1309. }
  1310. int
  1311. dp_tx_attempt_coalescing(struct dp_soc *soc, struct dp_vdev *vdev,
  1312. struct dp_tx_desc_s *tx_desc,
  1313. uint8_t tid,
  1314. struct dp_tx_msdu_info_s *msdu_info,
  1315. uint8_t ring_id)
  1316. {
  1317. struct dp_swlm *swlm = &soc->swlm;
  1318. union swlm_data swlm_query_data;
  1319. struct dp_swlm_tcl_data tcl_data;
  1320. QDF_STATUS status;
  1321. int ret;
  1322. if (!swlm->is_enabled)
  1323. return msdu_info->skip_hp_update;
  1324. tcl_data.nbuf = tx_desc->nbuf;
  1325. tcl_data.tid = tid;
  1326. tcl_data.ring_id = ring_id;
  1327. if (tx_desc->frm_type == dp_tx_frm_tso) {
  1328. tcl_data.pkt_len =
  1329. tx_desc->msdu_ext_desc->tso_desc->seg.total_len;
  1330. } else {
  1331. tcl_data.pkt_len = qdf_nbuf_len(tx_desc->nbuf);
  1332. }
  1333. tcl_data.num_ll_connections = vdev->num_latency_critical_conn;
  1334. swlm_query_data.tcl_data = &tcl_data;
  1335. status = dp_swlm_tcl_pre_check(soc, &tcl_data);
  1336. if (QDF_IS_STATUS_ERROR(status)) {
  1337. dp_swlm_tcl_reset_session_data(soc, ring_id);
  1338. DP_STATS_INC(swlm, tcl[ring_id].coalesce_fail, 1);
  1339. return 0;
  1340. }
  1341. ret = dp_swlm_query_policy(soc, TCL_DATA, swlm_query_data);
  1342. if (ret) {
  1343. DP_STATS_INC(swlm, tcl[ring_id].coalesce_success, 1);
  1344. } else {
  1345. DP_STATS_INC(swlm, tcl[ring_id].coalesce_fail, 1);
  1346. }
  1347. return ret;
  1348. }
  1349. void
  1350. dp_tx_ring_access_end(struct dp_soc *soc, hal_ring_handle_t hal_ring_hdl,
  1351. int coalesce)
  1352. {
  1353. if (coalesce)
  1354. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1355. else
  1356. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1357. }
  1358. static inline void
  1359. dp_tx_is_hp_update_required(uint32_t i, struct dp_tx_msdu_info_s *msdu_info)
  1360. {
  1361. if (((i + 1) < msdu_info->num_seg))
  1362. msdu_info->skip_hp_update = 1;
  1363. else
  1364. msdu_info->skip_hp_update = 0;
  1365. }
  1366. static inline void
  1367. dp_flush_tcp_hp(struct dp_soc *soc, uint8_t ring_id)
  1368. {
  1369. hal_ring_handle_t hal_ring_hdl =
  1370. dp_tx_get_hal_ring_hdl(soc, ring_id);
  1371. if (dp_tx_hal_ring_access_start(soc, hal_ring_hdl)) {
  1372. dp_err("Fillmore: SRNG access start failed");
  1373. return;
  1374. }
  1375. dp_tx_ring_access_end_wrapper(soc, hal_ring_hdl, 0);
  1376. }
  1377. static inline void
  1378. dp_tx_check_and_flush_hp(struct dp_soc *soc,
  1379. QDF_STATUS status,
  1380. struct dp_tx_msdu_info_s *msdu_info)
  1381. {
  1382. if (QDF_IS_STATUS_ERROR(status) && !msdu_info->skip_hp_update) {
  1383. dp_flush_tcp_hp(soc,
  1384. (msdu_info->tx_queue.ring_id & DP_TX_QUEUE_MASK));
  1385. }
  1386. }
  1387. #else
  1388. static inline void
  1389. dp_tx_is_hp_update_required(uint32_t i, struct dp_tx_msdu_info_s *msdu_info)
  1390. {
  1391. }
  1392. static inline void
  1393. dp_tx_check_and_flush_hp(struct dp_soc *soc,
  1394. QDF_STATUS status,
  1395. struct dp_tx_msdu_info_s *msdu_info)
  1396. {
  1397. }
  1398. #endif
  1399. #ifdef FEATURE_RUNTIME_PM
  1400. static inline int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc)
  1401. {
  1402. int ret;
  1403. ret = qdf_atomic_read(&soc->rtpm_high_tput_flag) &&
  1404. (hif_rtpm_get_state() <= HIF_RTPM_STATE_ON);
  1405. return ret;
  1406. }
  1407. /**
  1408. * dp_tx_ring_access_end_wrapper() - Wrapper for ring access end
  1409. * @soc: Datapath soc handle
  1410. * @hal_ring_hdl: HAL ring handle
  1411. * @coalesce: Coalesce the current write or not
  1412. *
  1413. * Wrapper for HAL ring access end for data transmission for
  1414. * FEATURE_RUNTIME_PM
  1415. *
  1416. * Returns: none
  1417. */
  1418. void
  1419. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1420. hal_ring_handle_t hal_ring_hdl,
  1421. int coalesce)
  1422. {
  1423. int ret;
  1424. /*
  1425. * Avoid runtime get and put APIs under high throughput scenarios.
  1426. */
  1427. if (dp_get_rtpm_tput_policy_requirement(soc)) {
  1428. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1429. return;
  1430. }
  1431. ret = hif_rtpm_get(HIF_RTPM_GET_ASYNC, HIF_RTPM_ID_DP);
  1432. if (QDF_IS_STATUS_SUCCESS(ret)) {
  1433. if (hif_system_pm_state_check(soc->hif_handle)) {
  1434. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1435. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1436. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1437. } else {
  1438. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1439. }
  1440. hif_rtpm_put(HIF_RTPM_PUT_ASYNC, HIF_RTPM_ID_DP);
  1441. } else {
  1442. dp_runtime_get(soc);
  1443. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1444. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1445. qdf_atomic_inc(&soc->tx_pending_rtpm);
  1446. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1447. dp_runtime_put(soc);
  1448. }
  1449. }
  1450. #else
  1451. #ifdef DP_POWER_SAVE
  1452. void
  1453. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1454. hal_ring_handle_t hal_ring_hdl,
  1455. int coalesce)
  1456. {
  1457. if (hif_system_pm_state_check(soc->hif_handle)) {
  1458. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1459. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1460. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1461. } else {
  1462. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1463. }
  1464. }
  1465. #endif
  1466. static inline int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc)
  1467. {
  1468. return 0;
  1469. }
  1470. #endif
  1471. /**
  1472. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1473. * @vdev: DP vdev handle
  1474. * @nbuf: skb
  1475. *
  1476. * Extract the DSCP or PCP information from frame and map into TID value.
  1477. *
  1478. * Return: void
  1479. */
  1480. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1481. struct dp_tx_msdu_info_s *msdu_info)
  1482. {
  1483. uint8_t tos = 0, dscp_tid_override = 0;
  1484. uint8_t *hdr_ptr, *L3datap;
  1485. uint8_t is_mcast = 0;
  1486. qdf_ether_header_t *eh = NULL;
  1487. qdf_ethervlan_header_t *evh = NULL;
  1488. uint16_t ether_type;
  1489. qdf_llc_t *llcHdr;
  1490. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1491. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1492. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1493. eh = (qdf_ether_header_t *)nbuf->data;
  1494. hdr_ptr = (uint8_t *)(eh->ether_dhost);
  1495. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1496. } else {
  1497. qdf_dot3_qosframe_t *qos_wh =
  1498. (qdf_dot3_qosframe_t *) nbuf->data;
  1499. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1500. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1501. return;
  1502. }
  1503. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1504. ether_type = eh->ether_type;
  1505. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1506. /*
  1507. * Check if packet is dot3 or eth2 type.
  1508. */
  1509. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1510. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1511. sizeof(*llcHdr));
  1512. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1513. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1514. sizeof(*llcHdr);
  1515. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1516. + sizeof(*llcHdr) +
  1517. sizeof(qdf_net_vlanhdr_t));
  1518. } else {
  1519. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1520. sizeof(*llcHdr);
  1521. }
  1522. } else {
  1523. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1524. evh = (qdf_ethervlan_header_t *) eh;
  1525. ether_type = evh->ether_type;
  1526. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1527. }
  1528. }
  1529. /*
  1530. * Find priority from IP TOS DSCP field
  1531. */
  1532. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1533. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1534. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1535. /* Only for unicast frames */
  1536. if (!is_mcast) {
  1537. /* send it on VO queue */
  1538. msdu_info->tid = DP_VO_TID;
  1539. }
  1540. } else {
  1541. /*
  1542. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1543. * from TOS byte.
  1544. */
  1545. tos = ip->ip_tos;
  1546. dscp_tid_override = 1;
  1547. }
  1548. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1549. /* TODO
  1550. * use flowlabel
  1551. *igmpmld cases to be handled in phase 2
  1552. */
  1553. unsigned long ver_pri_flowlabel;
  1554. unsigned long pri;
  1555. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1556. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1557. DP_IPV6_PRIORITY_SHIFT;
  1558. tos = pri;
  1559. dscp_tid_override = 1;
  1560. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1561. msdu_info->tid = DP_VO_TID;
  1562. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1563. /* Only for unicast frames */
  1564. if (!is_mcast) {
  1565. /* send ucast arp on VO queue */
  1566. msdu_info->tid = DP_VO_TID;
  1567. }
  1568. }
  1569. /*
  1570. * Assign all MCAST packets to BE
  1571. */
  1572. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1573. if (is_mcast) {
  1574. tos = 0;
  1575. dscp_tid_override = 1;
  1576. }
  1577. }
  1578. if (dscp_tid_override == 1) {
  1579. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1580. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1581. }
  1582. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1583. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1584. return;
  1585. }
  1586. /**
  1587. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1588. * @vdev: DP vdev handle
  1589. * @nbuf: skb
  1590. *
  1591. * Software based TID classification is required when more than 2 DSCP-TID
  1592. * mapping tables are needed.
  1593. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1594. *
  1595. * Return: void
  1596. */
  1597. static inline void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1598. struct dp_tx_msdu_info_s *msdu_info)
  1599. {
  1600. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1601. /*
  1602. * skip_sw_tid_classification flag will set in below cases-
  1603. * 1. vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map
  1604. * 2. hlos_tid_override enabled for vdev
  1605. * 3. mesh mode enabled for vdev
  1606. */
  1607. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1608. /* Update tid in msdu_info from skb priority */
  1609. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1610. & DP_TXRX_HLOS_TID_OVERRIDE_ENABLED)) {
  1611. uint32_t tid = qdf_nbuf_get_priority(nbuf);
  1612. if (tid == DP_TX_INVALID_QOS_TAG)
  1613. return;
  1614. msdu_info->tid = tid;
  1615. return;
  1616. }
  1617. return;
  1618. }
  1619. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1620. }
  1621. #ifdef FEATURE_WLAN_TDLS
  1622. /**
  1623. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1624. * @soc: datapath SOC
  1625. * @vdev: datapath vdev
  1626. * @tx_desc: TX descriptor
  1627. *
  1628. * Return: None
  1629. */
  1630. static void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1631. struct dp_vdev *vdev,
  1632. struct dp_tx_desc_s *tx_desc)
  1633. {
  1634. if (vdev) {
  1635. if (vdev->is_tdls_frame) {
  1636. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1637. vdev->is_tdls_frame = false;
  1638. }
  1639. }
  1640. }
  1641. static uint8_t dp_htt_tx_comp_get_status(struct dp_soc *soc, char *htt_desc)
  1642. {
  1643. uint8_t tx_status = HTT_TX_FW2WBM_TX_STATUS_MAX;
  1644. switch (soc->arch_id) {
  1645. case CDP_ARCH_TYPE_LI:
  1646. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  1647. break;
  1648. case CDP_ARCH_TYPE_BE:
  1649. tx_status = HTT_TX_WBM_COMPLETION_V3_TX_STATUS_GET(htt_desc[0]);
  1650. break;
  1651. default:
  1652. dp_err("Incorrect CDP_ARCH %d", soc->arch_id);
  1653. QDF_BUG(0);
  1654. }
  1655. return tx_status;
  1656. }
  1657. /**
  1658. * dp_non_std_htt_tx_comp_free_buff() - Free the non std tx packet buffer
  1659. * @soc: dp_soc handle
  1660. * @tx_desc: TX descriptor
  1661. * @vdev: datapath vdev handle
  1662. *
  1663. * Return: None
  1664. */
  1665. static void dp_non_std_htt_tx_comp_free_buff(struct dp_soc *soc,
  1666. struct dp_tx_desc_s *tx_desc)
  1667. {
  1668. uint8_t tx_status = 0;
  1669. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  1670. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1671. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1672. DP_MOD_ID_TDLS);
  1673. if (qdf_unlikely(!vdev)) {
  1674. dp_err_rl("vdev is null!");
  1675. goto error;
  1676. }
  1677. hal_tx_comp_get_htt_desc(&tx_desc->comp, htt_tx_status);
  1678. tx_status = dp_htt_tx_comp_get_status(soc, htt_tx_status);
  1679. dp_debug("vdev_id: %d tx_status: %d", tx_desc->vdev_id, tx_status);
  1680. if (vdev->tx_non_std_data_callback.func) {
  1681. qdf_nbuf_set_next(nbuf, NULL);
  1682. vdev->tx_non_std_data_callback.func(
  1683. vdev->tx_non_std_data_callback.ctxt,
  1684. nbuf, tx_status);
  1685. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1686. return;
  1687. } else {
  1688. dp_err_rl("callback func is null");
  1689. }
  1690. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1691. error:
  1692. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1693. qdf_nbuf_free(nbuf);
  1694. }
  1695. /**
  1696. * dp_tx_msdu_single_map() - do nbuf map
  1697. * @vdev: DP vdev handle
  1698. * @tx_desc: DP TX descriptor pointer
  1699. * @nbuf: skb pointer
  1700. *
  1701. * For TDLS frame, use qdf_nbuf_map_single() to align with the unmap
  1702. * operation done in other component.
  1703. *
  1704. * Return: QDF_STATUS
  1705. */
  1706. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1707. struct dp_tx_desc_s *tx_desc,
  1708. qdf_nbuf_t nbuf)
  1709. {
  1710. if (qdf_likely(!(tx_desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)))
  1711. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1712. nbuf,
  1713. QDF_DMA_TO_DEVICE,
  1714. nbuf->len);
  1715. else
  1716. return qdf_nbuf_map_single(vdev->osdev, nbuf,
  1717. QDF_DMA_TO_DEVICE);
  1718. }
  1719. #else
  1720. static inline void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1721. struct dp_vdev *vdev,
  1722. struct dp_tx_desc_s *tx_desc)
  1723. {
  1724. }
  1725. static inline void dp_non_std_htt_tx_comp_free_buff(struct dp_soc *soc,
  1726. struct dp_tx_desc_s *tx_desc)
  1727. {
  1728. }
  1729. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1730. struct dp_tx_desc_s *tx_desc,
  1731. qdf_nbuf_t nbuf)
  1732. {
  1733. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1734. nbuf,
  1735. QDF_DMA_TO_DEVICE,
  1736. nbuf->len);
  1737. }
  1738. #endif
  1739. static inline
  1740. qdf_dma_addr_t dp_tx_nbuf_map_regular(struct dp_vdev *vdev,
  1741. struct dp_tx_desc_s *tx_desc,
  1742. qdf_nbuf_t nbuf)
  1743. {
  1744. QDF_STATUS ret = QDF_STATUS_E_FAILURE;
  1745. ret = dp_tx_msdu_single_map(vdev, tx_desc, nbuf);
  1746. if (qdf_unlikely(QDF_IS_STATUS_ERROR(ret)))
  1747. return 0;
  1748. return qdf_nbuf_mapped_paddr_get(nbuf);
  1749. }
  1750. static inline
  1751. void dp_tx_nbuf_unmap_regular(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1752. {
  1753. qdf_nbuf_unmap_nbytes_single_paddr(soc->osdev,
  1754. desc->nbuf,
  1755. desc->dma_addr,
  1756. QDF_DMA_TO_DEVICE,
  1757. desc->length);
  1758. }
  1759. #if defined(QCA_DP_TX_NBUF_NO_MAP_UNMAP) && !defined(BUILD_X86)
  1760. static inline
  1761. qdf_dma_addr_t dp_tx_nbuf_map(struct dp_vdev *vdev,
  1762. struct dp_tx_desc_s *tx_desc,
  1763. qdf_nbuf_t nbuf)
  1764. {
  1765. if (qdf_likely(tx_desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  1766. qdf_nbuf_dma_clean_range((void *)nbuf->data,
  1767. (void *)(nbuf->data + nbuf->len));
  1768. return (qdf_dma_addr_t)qdf_mem_virt_to_phys(nbuf->data);
  1769. } else {
  1770. return dp_tx_nbuf_map_regular(vdev, tx_desc, nbuf);
  1771. }
  1772. }
  1773. static inline
  1774. void dp_tx_nbuf_unmap(struct dp_soc *soc,
  1775. struct dp_tx_desc_s *desc)
  1776. {
  1777. if (qdf_unlikely(!(desc->flags & DP_TX_DESC_FLAG_SIMPLE)))
  1778. return dp_tx_nbuf_unmap_regular(soc, desc);
  1779. }
  1780. #else
  1781. static inline
  1782. qdf_dma_addr_t dp_tx_nbuf_map(struct dp_vdev *vdev,
  1783. struct dp_tx_desc_s *tx_desc,
  1784. qdf_nbuf_t nbuf)
  1785. {
  1786. return dp_tx_nbuf_map_regular(vdev, tx_desc, nbuf);
  1787. }
  1788. static inline
  1789. void dp_tx_nbuf_unmap(struct dp_soc *soc,
  1790. struct dp_tx_desc_s *desc)
  1791. {
  1792. return dp_tx_nbuf_unmap_regular(soc, desc);
  1793. }
  1794. #endif
  1795. #if defined(WLAN_TX_PKT_CAPTURE_ENH) || defined(FEATURE_PERPKT_INFO)
  1796. static inline
  1797. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1798. {
  1799. dp_tx_nbuf_unmap(soc, desc);
  1800. desc->flags |= DP_TX_DESC_FLAG_UNMAP_DONE;
  1801. }
  1802. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1803. {
  1804. if (qdf_likely(!(desc->flags & DP_TX_DESC_FLAG_UNMAP_DONE)))
  1805. dp_tx_nbuf_unmap(soc, desc);
  1806. }
  1807. #else
  1808. static inline
  1809. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1810. {
  1811. }
  1812. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1813. {
  1814. dp_tx_nbuf_unmap(soc, desc);
  1815. }
  1816. #endif
  1817. #ifdef MESH_MODE_SUPPORT
  1818. /**
  1819. * dp_tx_update_mesh_flags() - Update descriptor flags for mesh VAP
  1820. * @soc: datapath SOC
  1821. * @vdev: datapath vdev
  1822. * @tx_desc: TX descriptor
  1823. *
  1824. * Return: None
  1825. */
  1826. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1827. struct dp_vdev *vdev,
  1828. struct dp_tx_desc_s *tx_desc)
  1829. {
  1830. if (qdf_unlikely(vdev->mesh_vdev))
  1831. tx_desc->flags |= DP_TX_DESC_FLAG_MESH_MODE;
  1832. }
  1833. /**
  1834. * dp_mesh_tx_comp_free_buff() - Free the mesh tx packet buffer
  1835. * @soc: dp_soc handle
  1836. * @tx_desc: TX descriptor
  1837. * @vdev: datapath vdev handle
  1838. *
  1839. * Return: None
  1840. */
  1841. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1842. struct dp_tx_desc_s *tx_desc)
  1843. {
  1844. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1845. struct dp_vdev *vdev = NULL;
  1846. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  1847. qdf_nbuf_free(nbuf);
  1848. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  1849. } else {
  1850. vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1851. DP_MOD_ID_MESH);
  1852. if (vdev && vdev->osif_tx_free_ext)
  1853. vdev->osif_tx_free_ext((nbuf));
  1854. else
  1855. qdf_nbuf_free(nbuf);
  1856. if (vdev)
  1857. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  1858. }
  1859. }
  1860. #else
  1861. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1862. struct dp_vdev *vdev,
  1863. struct dp_tx_desc_s *tx_desc)
  1864. {
  1865. }
  1866. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1867. struct dp_tx_desc_s *tx_desc)
  1868. {
  1869. }
  1870. #endif
  1871. /**
  1872. * dp_tx_frame_is_drop() - checks if the packet is loopback
  1873. * @vdev: DP vdev handle
  1874. * @nbuf: skb
  1875. *
  1876. * Return: 1 if frame needs to be dropped else 0
  1877. */
  1878. int dp_tx_frame_is_drop(struct dp_vdev *vdev, uint8_t *srcmac, uint8_t *dstmac)
  1879. {
  1880. struct dp_pdev *pdev = NULL;
  1881. struct dp_ast_entry *src_ast_entry = NULL;
  1882. struct dp_ast_entry *dst_ast_entry = NULL;
  1883. struct dp_soc *soc = NULL;
  1884. qdf_assert(vdev);
  1885. pdev = vdev->pdev;
  1886. qdf_assert(pdev);
  1887. soc = pdev->soc;
  1888. dst_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1889. (soc, dstmac, vdev->pdev->pdev_id);
  1890. src_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1891. (soc, srcmac, vdev->pdev->pdev_id);
  1892. if (dst_ast_entry && src_ast_entry) {
  1893. if (dst_ast_entry->peer_id ==
  1894. src_ast_entry->peer_id)
  1895. return 1;
  1896. }
  1897. return 0;
  1898. }
  1899. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  1900. defined(WLAN_MCAST_MLO)
  1901. /* MLO peer id for reinject*/
  1902. #define DP_MLO_MCAST_REINJECT_PEER_ID 0XFFFD
  1903. /* MLO vdev id inc offset */
  1904. #define DP_MLO_VDEV_ID_OFFSET 0x80
  1905. static inline void
  1906. dp_tx_bypass_reinjection(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  1907. {
  1908. if (!(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)) {
  1909. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1910. qdf_atomic_inc(&soc->num_tx_exception);
  1911. }
  1912. }
  1913. static inline void
  1914. dp_tx_update_mcast_param(uint16_t peer_id,
  1915. uint16_t *htt_tcl_metadata,
  1916. struct dp_vdev *vdev,
  1917. struct dp_tx_msdu_info_s *msdu_info)
  1918. {
  1919. if (peer_id == DP_MLO_MCAST_REINJECT_PEER_ID) {
  1920. *htt_tcl_metadata = 0;
  1921. DP_TX_TCL_METADATA_TYPE_SET(
  1922. *htt_tcl_metadata,
  1923. HTT_TCL_METADATA_V2_TYPE_GLOBAL_SEQ_BASED);
  1924. HTT_TX_TCL_METADATA_GLBL_SEQ_NO_SET(*htt_tcl_metadata,
  1925. msdu_info->gsn);
  1926. msdu_info->vdev_id = vdev->vdev_id + DP_MLO_VDEV_ID_OFFSET;
  1927. if (qdf_unlikely(vdev->nawds_enabled))
  1928. HTT_TX_TCL_METADATA_GLBL_SEQ_HOST_INSPECTED_SET(
  1929. *htt_tcl_metadata, 1);
  1930. } else {
  1931. msdu_info->vdev_id = vdev->vdev_id;
  1932. }
  1933. }
  1934. #else
  1935. static inline void
  1936. dp_tx_bypass_reinjection(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  1937. {
  1938. }
  1939. static inline void
  1940. dp_tx_update_mcast_param(uint16_t peer_id,
  1941. uint16_t *htt_tcl_metadata,
  1942. struct dp_vdev *vdev,
  1943. struct dp_tx_msdu_info_s *msdu_info)
  1944. {
  1945. }
  1946. #endif
  1947. /**
  1948. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1949. * @vdev: DP vdev handle
  1950. * @nbuf: skb
  1951. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1952. * @meta_data: Metadata to the fw
  1953. * @tx_q: Tx queue to be used for this Tx frame
  1954. * @peer_id: peer_id of the peer in case of NAWDS frames
  1955. * @tx_exc_metadata: Handle that holds exception path metadata
  1956. *
  1957. * Return: NULL on success,
  1958. * nbuf when it fails to send
  1959. */
  1960. qdf_nbuf_t
  1961. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1962. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1963. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1964. {
  1965. struct dp_pdev *pdev = vdev->pdev;
  1966. struct dp_soc *soc = pdev->soc;
  1967. struct dp_tx_desc_s *tx_desc;
  1968. QDF_STATUS status;
  1969. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1970. uint16_t htt_tcl_metadata = 0;
  1971. enum cdp_tx_sw_drop drop_code = TX_MAX_DROP;
  1972. uint8_t tid = msdu_info->tid;
  1973. struct cdp_tid_tx_stats *tid_stats = NULL;
  1974. qdf_dma_addr_t paddr;
  1975. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1976. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1977. msdu_info, tx_exc_metadata);
  1978. if (!tx_desc) {
  1979. dp_err_rl("Tx_desc prepare Fail vdev %pK queue %d",
  1980. vdev, tx_q->desc_pool_id);
  1981. drop_code = TX_DESC_ERR;
  1982. goto fail_return;
  1983. }
  1984. dp_tx_update_tdls_flags(soc, vdev, tx_desc);
  1985. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1986. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1987. DP_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1988. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1989. DP_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1990. DP_TCL_METADATA_TYPE_PEER_BASED);
  1991. DP_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1992. peer_id);
  1993. dp_tx_bypass_reinjection(soc, tx_desc);
  1994. } else
  1995. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1996. if (msdu_info->exception_fw)
  1997. DP_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1998. dp_tx_desc_update_fast_comp_flag(soc, tx_desc,
  1999. !pdev->enhanced_stats_en);
  2000. dp_tx_update_mesh_flags(soc, vdev, tx_desc);
  2001. paddr = dp_tx_nbuf_map(vdev, tx_desc, nbuf);
  2002. if (!paddr) {
  2003. /* Handle failure */
  2004. dp_err("qdf_nbuf_map failed");
  2005. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  2006. drop_code = TX_DMA_MAP_ERR;
  2007. goto release_desc;
  2008. }
  2009. tx_desc->dma_addr = paddr;
  2010. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  2011. tx_desc->id, DP_TX_DESC_MAP);
  2012. dp_tx_update_mcast_param(peer_id, &htt_tcl_metadata, vdev, msdu_info);
  2013. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  2014. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  2015. htt_tcl_metadata,
  2016. tx_exc_metadata, msdu_info);
  2017. if (status != QDF_STATUS_SUCCESS) {
  2018. dp_tx_err_rl("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  2019. tx_desc, tx_q->ring_id);
  2020. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  2021. tx_desc->id, DP_TX_DESC_UNMAP);
  2022. dp_tx_nbuf_unmap(soc, tx_desc);
  2023. drop_code = TX_HW_ENQUEUE;
  2024. goto release_desc;
  2025. }
  2026. return NULL;
  2027. release_desc:
  2028. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2029. fail_return:
  2030. dp_tx_get_tid(vdev, nbuf, msdu_info);
  2031. tid_stats = &pdev->stats.tid_stats.
  2032. tid_tx_stats[tx_q->ring_id][tid];
  2033. tid_stats->swdrop_cnt[drop_code]++;
  2034. return nbuf;
  2035. }
  2036. /**
  2037. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2038. * @soc: Soc handle
  2039. * @desc: software Tx descriptor to be processed
  2040. *
  2041. * Return: none
  2042. */
  2043. void dp_tx_comp_free_buf(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  2044. {
  2045. qdf_nbuf_t nbuf = desc->nbuf;
  2046. enum dp_tx_event_type type = dp_tx_get_event_type(desc->flags);
  2047. /* nbuf already freed in vdev detach path */
  2048. if (!nbuf)
  2049. return;
  2050. /* If it is TDLS mgmt, don't unmap or free the frame */
  2051. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  2052. return dp_non_std_htt_tx_comp_free_buff(soc, desc);
  2053. /* 0 : MSDU buffer, 1 : MLE */
  2054. if (desc->msdu_ext_desc) {
  2055. /* TSO free */
  2056. if (hal_tx_ext_desc_get_tso_enable(
  2057. desc->msdu_ext_desc->vaddr)) {
  2058. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  2059. desc->id, DP_TX_COMP_MSDU_EXT);
  2060. dp_tx_tso_seg_history_add(soc,
  2061. desc->msdu_ext_desc->tso_desc,
  2062. desc->nbuf, desc->id, type);
  2063. /* unmap eash TSO seg before free the nbuf */
  2064. dp_tx_tso_unmap_segment(soc,
  2065. desc->msdu_ext_desc->tso_desc,
  2066. desc->msdu_ext_desc->
  2067. tso_num_desc);
  2068. qdf_nbuf_free(nbuf);
  2069. return;
  2070. }
  2071. if (qdf_unlikely(desc->frm_type == dp_tx_frm_sg)) {
  2072. void *msdu_ext_desc = desc->msdu_ext_desc->vaddr;
  2073. qdf_dma_addr_t iova;
  2074. uint32_t frag_len;
  2075. uint32_t i;
  2076. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf,
  2077. QDF_DMA_TO_DEVICE,
  2078. qdf_nbuf_headlen(nbuf));
  2079. for (i = 1; i < DP_TX_MAX_NUM_FRAGS; i++) {
  2080. hal_tx_ext_desc_get_frag_info(msdu_ext_desc, i,
  2081. &iova,
  2082. &frag_len);
  2083. if (!iova || !frag_len)
  2084. break;
  2085. qdf_mem_unmap_page(soc->osdev, iova, frag_len,
  2086. QDF_DMA_TO_DEVICE);
  2087. }
  2088. qdf_nbuf_free(nbuf);
  2089. return;
  2090. }
  2091. }
  2092. /* If it's ME frame, dont unmap the cloned nbuf's */
  2093. if ((desc->flags & DP_TX_DESC_FLAG_ME) && qdf_nbuf_is_cloned(nbuf))
  2094. goto nbuf_free;
  2095. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf, desc->id, type);
  2096. dp_tx_unmap(soc, desc);
  2097. if (desc->flags & DP_TX_DESC_FLAG_MESH_MODE)
  2098. return dp_mesh_tx_comp_free_buff(soc, desc);
  2099. if (dp_tx_traffic_end_indication_enq_ind_pkt(soc, desc, nbuf))
  2100. return;
  2101. nbuf_free:
  2102. qdf_nbuf_free(nbuf);
  2103. }
  2104. /**
  2105. * dp_tx_sg_unmap_buf() - Unmap scatter gather fragments
  2106. * @soc: DP soc handle
  2107. * @nbuf: skb
  2108. * @msdu_info: MSDU info
  2109. *
  2110. * Return: None
  2111. */
  2112. static inline void
  2113. dp_tx_sg_unmap_buf(struct dp_soc *soc, qdf_nbuf_t nbuf,
  2114. struct dp_tx_msdu_info_s *msdu_info)
  2115. {
  2116. uint32_t cur_idx;
  2117. struct dp_tx_seg_info_s *seg = msdu_info->u.sg_info.curr_seg;
  2118. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE,
  2119. qdf_nbuf_headlen(nbuf));
  2120. for (cur_idx = 1; cur_idx < seg->frag_cnt; cur_idx++)
  2121. qdf_mem_unmap_page(soc->osdev, (qdf_dma_addr_t)
  2122. (seg->frags[cur_idx].paddr_lo | ((uint64_t)
  2123. seg->frags[cur_idx].paddr_hi) << 32),
  2124. seg->frags[cur_idx].len,
  2125. QDF_DMA_TO_DEVICE);
  2126. }
  2127. /**
  2128. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  2129. * @vdev: DP vdev handle
  2130. * @nbuf: skb
  2131. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  2132. *
  2133. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  2134. *
  2135. * Return: NULL on success,
  2136. * nbuf when it fails to send
  2137. */
  2138. #if QDF_LOCK_STATS
  2139. noinline
  2140. #else
  2141. #endif
  2142. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2143. struct dp_tx_msdu_info_s *msdu_info)
  2144. {
  2145. uint32_t i;
  2146. struct dp_pdev *pdev = vdev->pdev;
  2147. struct dp_soc *soc = pdev->soc;
  2148. struct dp_tx_desc_s *tx_desc;
  2149. bool is_cce_classified = false;
  2150. QDF_STATUS status;
  2151. uint16_t htt_tcl_metadata = 0;
  2152. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  2153. struct cdp_tid_tx_stats *tid_stats = NULL;
  2154. uint8_t prep_desc_fail = 0, hw_enq_fail = 0;
  2155. if (msdu_info->frm_type == dp_tx_frm_me)
  2156. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2157. i = 0;
  2158. /* Print statement to track i and num_seg */
  2159. /*
  2160. * For each segment (maps to 1 MSDU) , prepare software and hardware
  2161. * descriptors using information in msdu_info
  2162. */
  2163. while (i < msdu_info->num_seg) {
  2164. /*
  2165. * Setup Tx descriptor for an MSDU, and MSDU extension
  2166. * descriptor
  2167. */
  2168. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  2169. tx_q->desc_pool_id);
  2170. if (!tx_desc) {
  2171. if (msdu_info->frm_type == dp_tx_frm_me) {
  2172. prep_desc_fail++;
  2173. dp_tx_me_free_buf(pdev,
  2174. (void *)(msdu_info->u.sg_info
  2175. .curr_seg->frags[0].vaddr));
  2176. if (prep_desc_fail == msdu_info->num_seg) {
  2177. /*
  2178. * Unmap is needed only if descriptor
  2179. * preparation failed for all segments.
  2180. */
  2181. qdf_nbuf_unmap(soc->osdev,
  2182. msdu_info->u.sg_info.
  2183. curr_seg->nbuf,
  2184. QDF_DMA_TO_DEVICE);
  2185. }
  2186. /*
  2187. * Free the nbuf for the current segment
  2188. * and make it point to the next in the list.
  2189. * For me, there are as many segments as there
  2190. * are no of clients.
  2191. */
  2192. qdf_nbuf_free(msdu_info->u.sg_info
  2193. .curr_seg->nbuf);
  2194. if (msdu_info->u.sg_info.curr_seg->next) {
  2195. msdu_info->u.sg_info.curr_seg =
  2196. msdu_info->u.sg_info
  2197. .curr_seg->next;
  2198. nbuf = msdu_info->u.sg_info
  2199. .curr_seg->nbuf;
  2200. }
  2201. i++;
  2202. continue;
  2203. }
  2204. if (msdu_info->frm_type == dp_tx_frm_tso) {
  2205. dp_tx_tso_seg_history_add(
  2206. soc,
  2207. msdu_info->u.tso_info.curr_seg,
  2208. nbuf, 0, DP_TX_DESC_UNMAP);
  2209. dp_tx_tso_unmap_segment(soc,
  2210. msdu_info->u.tso_info.
  2211. curr_seg,
  2212. msdu_info->u.tso_info.
  2213. tso_num_seg_list);
  2214. if (msdu_info->u.tso_info.curr_seg->next) {
  2215. msdu_info->u.tso_info.curr_seg =
  2216. msdu_info->u.tso_info.curr_seg->next;
  2217. i++;
  2218. continue;
  2219. }
  2220. }
  2221. if (msdu_info->frm_type == dp_tx_frm_sg)
  2222. dp_tx_sg_unmap_buf(soc, nbuf, msdu_info);
  2223. goto done;
  2224. }
  2225. if (msdu_info->frm_type == dp_tx_frm_me) {
  2226. tx_desc->msdu_ext_desc->me_buffer =
  2227. (struct dp_tx_me_buf_t *)msdu_info->
  2228. u.sg_info.curr_seg->frags[0].vaddr;
  2229. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  2230. }
  2231. if (is_cce_classified)
  2232. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  2233. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2234. if (msdu_info->exception_fw) {
  2235. DP_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  2236. }
  2237. dp_tx_is_hp_update_required(i, msdu_info);
  2238. /*
  2239. * For frames with multiple segments (TSO, ME), jump to next
  2240. * segment.
  2241. */
  2242. if (msdu_info->frm_type == dp_tx_frm_tso) {
  2243. if (msdu_info->u.tso_info.curr_seg->next) {
  2244. msdu_info->u.tso_info.curr_seg =
  2245. msdu_info->u.tso_info.curr_seg->next;
  2246. /*
  2247. * If this is a jumbo nbuf, then increment the
  2248. * number of nbuf users for each additional
  2249. * segment of the msdu. This will ensure that
  2250. * the skb is freed only after receiving tx
  2251. * completion for all segments of an nbuf
  2252. */
  2253. qdf_nbuf_inc_users(nbuf);
  2254. /* Check with MCL if this is needed */
  2255. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf;
  2256. */
  2257. }
  2258. }
  2259. dp_tx_update_mcast_param(DP_INVALID_PEER,
  2260. &htt_tcl_metadata,
  2261. vdev,
  2262. msdu_info);
  2263. /*
  2264. * Enqueue the Tx MSDU descriptor to HW for transmit
  2265. */
  2266. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  2267. htt_tcl_metadata,
  2268. NULL, msdu_info);
  2269. dp_tx_check_and_flush_hp(soc, status, msdu_info);
  2270. if (status != QDF_STATUS_SUCCESS) {
  2271. dp_info_rl("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  2272. tx_desc, tx_q->ring_id);
  2273. dp_tx_get_tid(vdev, nbuf, msdu_info);
  2274. tid_stats = &pdev->stats.tid_stats.
  2275. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  2276. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  2277. if (msdu_info->frm_type == dp_tx_frm_me) {
  2278. hw_enq_fail++;
  2279. if (hw_enq_fail == msdu_info->num_seg) {
  2280. /*
  2281. * Unmap is needed only if enqueue
  2282. * failed for all segments.
  2283. */
  2284. qdf_nbuf_unmap(soc->osdev,
  2285. msdu_info->u.sg_info.
  2286. curr_seg->nbuf,
  2287. QDF_DMA_TO_DEVICE);
  2288. }
  2289. /*
  2290. * Free the nbuf for the current segment
  2291. * and make it point to the next in the list.
  2292. * For me, there are as many segments as there
  2293. * are no of clients.
  2294. */
  2295. qdf_nbuf_free(msdu_info->u.sg_info
  2296. .curr_seg->nbuf);
  2297. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2298. if (msdu_info->u.sg_info.curr_seg->next) {
  2299. msdu_info->u.sg_info.curr_seg =
  2300. msdu_info->u.sg_info
  2301. .curr_seg->next;
  2302. nbuf = msdu_info->u.sg_info
  2303. .curr_seg->nbuf;
  2304. } else
  2305. break;
  2306. i++;
  2307. continue;
  2308. }
  2309. /*
  2310. * For TSO frames, the nbuf users increment done for
  2311. * the current segment has to be reverted, since the
  2312. * hw enqueue for this segment failed
  2313. */
  2314. if (msdu_info->frm_type == dp_tx_frm_tso &&
  2315. msdu_info->u.tso_info.curr_seg) {
  2316. /*
  2317. * unmap and free current,
  2318. * retransmit remaining segments
  2319. */
  2320. dp_tx_comp_free_buf(soc, tx_desc);
  2321. i++;
  2322. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2323. continue;
  2324. }
  2325. if (msdu_info->frm_type == dp_tx_frm_sg)
  2326. dp_tx_sg_unmap_buf(soc, nbuf, msdu_info);
  2327. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2328. goto done;
  2329. }
  2330. /*
  2331. * TODO
  2332. * if tso_info structure can be modified to have curr_seg
  2333. * as first element, following 2 blocks of code (for TSO and SG)
  2334. * can be combined into 1
  2335. */
  2336. /*
  2337. * For Multicast-Unicast converted packets,
  2338. * each converted frame (for a client) is represented as
  2339. * 1 segment
  2340. */
  2341. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  2342. (msdu_info->frm_type == dp_tx_frm_me)) {
  2343. if (msdu_info->u.sg_info.curr_seg->next) {
  2344. msdu_info->u.sg_info.curr_seg =
  2345. msdu_info->u.sg_info.curr_seg->next;
  2346. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2347. } else
  2348. break;
  2349. }
  2350. i++;
  2351. }
  2352. nbuf = NULL;
  2353. done:
  2354. return nbuf;
  2355. }
  2356. /**
  2357. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  2358. * for SG frames
  2359. * @vdev: DP vdev handle
  2360. * @nbuf: skb
  2361. * @seg_info: Pointer to Segment info Descriptor to be prepared
  2362. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2363. *
  2364. * Return: NULL on success,
  2365. * nbuf when it fails to send
  2366. */
  2367. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2368. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  2369. {
  2370. uint32_t cur_frag, nr_frags, i;
  2371. qdf_dma_addr_t paddr;
  2372. struct dp_tx_sg_info_s *sg_info;
  2373. sg_info = &msdu_info->u.sg_info;
  2374. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  2375. if (QDF_STATUS_SUCCESS !=
  2376. qdf_nbuf_map_nbytes_single(vdev->osdev, nbuf,
  2377. QDF_DMA_TO_DEVICE,
  2378. qdf_nbuf_headlen(nbuf))) {
  2379. dp_tx_err("dma map error");
  2380. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2381. qdf_nbuf_free(nbuf);
  2382. return NULL;
  2383. }
  2384. paddr = qdf_nbuf_mapped_paddr_get(nbuf);
  2385. seg_info->frags[0].paddr_lo = paddr;
  2386. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  2387. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  2388. seg_info->frags[0].vaddr = (void *) nbuf;
  2389. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  2390. if (QDF_STATUS_SUCCESS != qdf_nbuf_frag_map(vdev->osdev,
  2391. nbuf, 0,
  2392. QDF_DMA_TO_DEVICE,
  2393. cur_frag)) {
  2394. dp_tx_err("frag dma map error");
  2395. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2396. goto map_err;
  2397. }
  2398. paddr = qdf_nbuf_get_tx_frag_paddr(nbuf);
  2399. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  2400. seg_info->frags[cur_frag + 1].paddr_hi =
  2401. ((uint64_t) paddr) >> 32;
  2402. seg_info->frags[cur_frag + 1].len =
  2403. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  2404. }
  2405. seg_info->frag_cnt = (cur_frag + 1);
  2406. seg_info->total_len = qdf_nbuf_len(nbuf);
  2407. seg_info->next = NULL;
  2408. sg_info->curr_seg = seg_info;
  2409. msdu_info->frm_type = dp_tx_frm_sg;
  2410. msdu_info->num_seg = 1;
  2411. return nbuf;
  2412. map_err:
  2413. /* restore paddr into nbuf before calling unmap */
  2414. qdf_nbuf_mapped_paddr_set(nbuf,
  2415. (qdf_dma_addr_t)(seg_info->frags[0].paddr_lo |
  2416. ((uint64_t)
  2417. seg_info->frags[0].paddr_hi) << 32));
  2418. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  2419. QDF_DMA_TO_DEVICE,
  2420. seg_info->frags[0].len);
  2421. for (i = 1; i <= cur_frag; i++) {
  2422. qdf_mem_unmap_page(vdev->osdev, (qdf_dma_addr_t)
  2423. (seg_info->frags[i].paddr_lo | ((uint64_t)
  2424. seg_info->frags[i].paddr_hi) << 32),
  2425. seg_info->frags[i].len,
  2426. QDF_DMA_TO_DEVICE);
  2427. }
  2428. qdf_nbuf_free(nbuf);
  2429. return NULL;
  2430. }
  2431. /**
  2432. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  2433. * @vdev: DP vdev handle
  2434. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2435. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  2436. *
  2437. * Return: NULL on failure,
  2438. * nbuf when extracted successfully
  2439. */
  2440. static
  2441. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  2442. struct dp_tx_msdu_info_s *msdu_info,
  2443. uint16_t ppdu_cookie)
  2444. {
  2445. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2446. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2447. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2448. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  2449. (msdu_info->meta_data[5], 1);
  2450. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  2451. (msdu_info->meta_data[5], 1);
  2452. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  2453. (msdu_info->meta_data[6], ppdu_cookie);
  2454. msdu_info->exception_fw = 1;
  2455. msdu_info->is_tx_sniffer = 1;
  2456. }
  2457. #ifdef MESH_MODE_SUPPORT
  2458. /**
  2459. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  2460. and prepare msdu_info for mesh frames.
  2461. * @vdev: DP vdev handle
  2462. * @nbuf: skb
  2463. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2464. *
  2465. * Return: NULL on failure,
  2466. * nbuf when extracted successfully
  2467. */
  2468. static
  2469. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2470. struct dp_tx_msdu_info_s *msdu_info)
  2471. {
  2472. struct meta_hdr_s *mhdr;
  2473. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2474. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2475. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2476. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  2477. msdu_info->exception_fw = 0;
  2478. goto remove_meta_hdr;
  2479. }
  2480. msdu_info->exception_fw = 1;
  2481. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2482. meta_data->host_tx_desc_pool = 1;
  2483. meta_data->update_peer_cache = 1;
  2484. meta_data->learning_frame = 1;
  2485. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  2486. meta_data->power = mhdr->power;
  2487. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  2488. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  2489. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  2490. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  2491. meta_data->dyn_bw = 1;
  2492. meta_data->valid_pwr = 1;
  2493. meta_data->valid_mcs_mask = 1;
  2494. meta_data->valid_nss_mask = 1;
  2495. meta_data->valid_preamble_type = 1;
  2496. meta_data->valid_retries = 1;
  2497. meta_data->valid_bw_info = 1;
  2498. }
  2499. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  2500. meta_data->encrypt_type = 0;
  2501. meta_data->valid_encrypt_type = 1;
  2502. meta_data->learning_frame = 0;
  2503. }
  2504. meta_data->valid_key_flags = 1;
  2505. meta_data->key_flags = (mhdr->keyix & 0x3);
  2506. remove_meta_hdr:
  2507. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2508. dp_tx_err("qdf_nbuf_pull_head failed");
  2509. qdf_nbuf_free(nbuf);
  2510. return NULL;
  2511. }
  2512. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  2513. dp_tx_info("Meta hdr %0x %0x %0x %0x %0x %0x"
  2514. " tid %d to_fw %d",
  2515. msdu_info->meta_data[0],
  2516. msdu_info->meta_data[1],
  2517. msdu_info->meta_data[2],
  2518. msdu_info->meta_data[3],
  2519. msdu_info->meta_data[4],
  2520. msdu_info->meta_data[5],
  2521. msdu_info->tid, msdu_info->exception_fw);
  2522. return nbuf;
  2523. }
  2524. #else
  2525. static
  2526. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2527. struct dp_tx_msdu_info_s *msdu_info)
  2528. {
  2529. return nbuf;
  2530. }
  2531. #endif
  2532. /**
  2533. * dp_check_exc_metadata() - Checks if parameters are valid
  2534. * @tx_exc - holds all exception path parameters
  2535. *
  2536. * Returns true when all the parameters are valid else false
  2537. *
  2538. */
  2539. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  2540. {
  2541. bool invalid_tid = (tx_exc->tid >= DP_MAX_TIDS && tx_exc->tid !=
  2542. HTT_INVALID_TID);
  2543. bool invalid_encap_type =
  2544. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  2545. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  2546. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  2547. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  2548. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  2549. tx_exc->ppdu_cookie == 0);
  2550. if (tx_exc->is_intrabss_fwd)
  2551. return true;
  2552. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  2553. invalid_cookie) {
  2554. return false;
  2555. }
  2556. return true;
  2557. }
  2558. #ifdef ATH_SUPPORT_IQUE
  2559. /**
  2560. * dp_tx_mcast_enhance() - Multicast enhancement on TX
  2561. * @vdev: vdev handle
  2562. * @nbuf: skb
  2563. *
  2564. * Return: true on success,
  2565. * false on failure
  2566. */
  2567. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2568. {
  2569. qdf_ether_header_t *eh;
  2570. /* Mcast to Ucast Conversion*/
  2571. if (qdf_likely(!vdev->mcast_enhancement_en))
  2572. return true;
  2573. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2574. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2575. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2576. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  2577. qdf_nbuf_set_next(nbuf, NULL);
  2578. DP_STATS_INC_PKT(vdev, tx_i.mcast_en.mcast_pkt, 1,
  2579. qdf_nbuf_len(nbuf));
  2580. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  2581. QDF_STATUS_SUCCESS) {
  2582. return false;
  2583. }
  2584. if (qdf_unlikely(vdev->igmp_mcast_enhanc_en > 0)) {
  2585. if (dp_tx_prepare_send_igmp_me(vdev, nbuf) ==
  2586. QDF_STATUS_SUCCESS) {
  2587. return false;
  2588. }
  2589. }
  2590. }
  2591. return true;
  2592. }
  2593. #else
  2594. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2595. {
  2596. return true;
  2597. }
  2598. #endif
  2599. /**
  2600. * dp_tx_per_pkt_vdev_id_check() - vdev id check for frame
  2601. * @nbuf: qdf_nbuf_t
  2602. * @vdev: struct dp_vdev *
  2603. *
  2604. * Allow packet for processing only if it is for peer client which is
  2605. * connected with same vap. Drop packet if client is connected to
  2606. * different vap.
  2607. *
  2608. * Return: QDF_STATUS
  2609. */
  2610. static inline QDF_STATUS
  2611. dp_tx_per_pkt_vdev_id_check(qdf_nbuf_t nbuf, struct dp_vdev *vdev)
  2612. {
  2613. struct dp_ast_entry *dst_ast_entry = NULL;
  2614. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2615. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) ||
  2616. DP_FRAME_IS_BROADCAST((eh)->ether_dhost))
  2617. return QDF_STATUS_SUCCESS;
  2618. qdf_spin_lock_bh(&vdev->pdev->soc->ast_lock);
  2619. dst_ast_entry = dp_peer_ast_hash_find_by_vdevid(vdev->pdev->soc,
  2620. eh->ether_dhost,
  2621. vdev->vdev_id);
  2622. /* If there is no ast entry, return failure */
  2623. if (qdf_unlikely(!dst_ast_entry)) {
  2624. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2625. return QDF_STATUS_E_FAILURE;
  2626. }
  2627. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2628. return QDF_STATUS_SUCCESS;
  2629. }
  2630. /**
  2631. * dp_tx_nawds_handler() - NAWDS handler
  2632. *
  2633. * @soc: DP soc handle
  2634. * @vdev_id: id of DP vdev handle
  2635. * @msdu_info: msdu_info required to create HTT metadata
  2636. * @nbuf: skb
  2637. *
  2638. * This API transfers the multicast frames with the peer id
  2639. * on NAWDS enabled peer.
  2640. * Return: none
  2641. */
  2642. static inline
  2643. void dp_tx_nawds_handler(struct dp_soc *soc, struct dp_vdev *vdev,
  2644. struct dp_tx_msdu_info_s *msdu_info,
  2645. qdf_nbuf_t nbuf, uint16_t sa_peer_id)
  2646. {
  2647. struct dp_peer *peer = NULL;
  2648. qdf_nbuf_t nbuf_clone = NULL;
  2649. uint16_t peer_id = DP_INVALID_PEER;
  2650. struct dp_txrx_peer *txrx_peer;
  2651. /* This check avoids pkt forwarding which is entered
  2652. * in the ast table but still doesn't have valid peerid.
  2653. */
  2654. if (sa_peer_id == HTT_INVALID_PEER)
  2655. return;
  2656. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2657. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2658. txrx_peer = dp_get_txrx_peer(peer);
  2659. if (!txrx_peer)
  2660. continue;
  2661. if (!txrx_peer->bss_peer && txrx_peer->nawds_enabled) {
  2662. peer_id = peer->peer_id;
  2663. if (!dp_peer_is_primary_link_peer(peer))
  2664. continue;
  2665. /* Multicast packets needs to be
  2666. * dropped in case of intra bss forwarding
  2667. */
  2668. if (sa_peer_id == txrx_peer->peer_id) {
  2669. dp_tx_debug("multicast packet");
  2670. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  2671. tx.nawds_mcast_drop,
  2672. 1);
  2673. continue;
  2674. }
  2675. nbuf_clone = qdf_nbuf_clone(nbuf);
  2676. if (!nbuf_clone) {
  2677. QDF_TRACE(QDF_MODULE_ID_DP,
  2678. QDF_TRACE_LEVEL_ERROR,
  2679. FL("nbuf clone failed"));
  2680. break;
  2681. }
  2682. nbuf_clone = dp_tx_send_msdu_single(vdev, nbuf_clone,
  2683. msdu_info, peer_id,
  2684. NULL);
  2685. if (nbuf_clone) {
  2686. dp_tx_debug("pkt send failed");
  2687. qdf_nbuf_free(nbuf_clone);
  2688. } else {
  2689. if (peer_id != DP_INVALID_PEER)
  2690. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  2691. tx.nawds_mcast,
  2692. 1, qdf_nbuf_len(nbuf));
  2693. }
  2694. }
  2695. }
  2696. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2697. }
  2698. /**
  2699. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  2700. * @soc: DP soc handle
  2701. * @vdev_id: id of DP vdev handle
  2702. * @nbuf: skb
  2703. * @tx_exc_metadata: Handle that holds exception path meta data
  2704. *
  2705. * Entry point for Core Tx layer (DP_TX) invoked from
  2706. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2707. *
  2708. * Return: NULL on success,
  2709. * nbuf when it fails to send
  2710. */
  2711. qdf_nbuf_t
  2712. dp_tx_send_exception(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2713. qdf_nbuf_t nbuf,
  2714. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2715. {
  2716. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2717. qdf_ether_header_t *eh = NULL;
  2718. struct dp_tx_msdu_info_s msdu_info;
  2719. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2720. DP_MOD_ID_TX_EXCEPTION);
  2721. if (qdf_unlikely(!vdev))
  2722. goto fail;
  2723. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2724. if (!tx_exc_metadata)
  2725. goto fail;
  2726. msdu_info.tid = tx_exc_metadata->tid;
  2727. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2728. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2729. QDF_MAC_ADDR_REF(nbuf->data));
  2730. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2731. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  2732. dp_tx_err("Invalid parameters in exception path");
  2733. goto fail;
  2734. }
  2735. /* Basic sanity checks for unsupported packets */
  2736. /* MESH mode */
  2737. if (qdf_unlikely(vdev->mesh_vdev)) {
  2738. dp_tx_err("Mesh mode is not supported in exception path");
  2739. goto fail;
  2740. }
  2741. /*
  2742. * Classify the frame and call corresponding
  2743. * "prepare" function which extracts the segment (TSO)
  2744. * and fragmentation information (for TSO , SG, ME, or Raw)
  2745. * into MSDU_INFO structure which is later used to fill
  2746. * SW and HW descriptors.
  2747. */
  2748. if (qdf_nbuf_is_tso(nbuf)) {
  2749. dp_verbose_debug("TSO frame %pK", vdev);
  2750. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2751. qdf_nbuf_len(nbuf));
  2752. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2753. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2754. qdf_nbuf_len(nbuf));
  2755. goto fail;
  2756. }
  2757. goto send_multiple;
  2758. }
  2759. /* SG */
  2760. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2761. struct dp_tx_seg_info_s seg_info = {0};
  2762. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2763. if (!nbuf)
  2764. goto fail;
  2765. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2766. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2767. qdf_nbuf_len(nbuf));
  2768. goto send_multiple;
  2769. }
  2770. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  2771. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  2772. qdf_nbuf_len(nbuf));
  2773. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  2774. tx_exc_metadata->ppdu_cookie);
  2775. }
  2776. /*
  2777. * Get HW Queue to use for this frame.
  2778. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2779. * dedicated for data and 1 for command.
  2780. * "queue_id" maps to one hardware ring.
  2781. * With each ring, we also associate a unique Tx descriptor pool
  2782. * to minimize lock contention for these resources.
  2783. */
  2784. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2785. if (qdf_likely(tx_exc_metadata->is_intrabss_fwd)) {
  2786. if (qdf_unlikely(vdev->nawds_enabled)) {
  2787. /*
  2788. * This is a multicast packet
  2789. */
  2790. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf,
  2791. tx_exc_metadata->peer_id);
  2792. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2793. 1, qdf_nbuf_len(nbuf));
  2794. }
  2795. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2796. DP_INVALID_PEER, NULL);
  2797. } else {
  2798. /*
  2799. * Check exception descriptors
  2800. */
  2801. if (dp_tx_exception_limit_check(vdev))
  2802. goto fail;
  2803. /* Single linear frame */
  2804. /*
  2805. * If nbuf is a simple linear frame, use send_single function to
  2806. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2807. * SRNG. There is no need to setup a MSDU extension descriptor.
  2808. */
  2809. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2810. tx_exc_metadata->peer_id,
  2811. tx_exc_metadata);
  2812. }
  2813. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2814. return nbuf;
  2815. send_multiple:
  2816. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2817. fail:
  2818. if (vdev)
  2819. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2820. dp_verbose_debug("pkt send failed");
  2821. return nbuf;
  2822. }
  2823. /**
  2824. * dp_tx_send_exception_vdev_id_check() - Transmit a frame on a given VAP
  2825. * in exception path in special case to avoid regular exception path chk.
  2826. * @soc: DP soc handle
  2827. * @vdev_id: id of DP vdev handle
  2828. * @nbuf: skb
  2829. * @tx_exc_metadata: Handle that holds exception path meta data
  2830. *
  2831. * Entry point for Core Tx layer (DP_TX) invoked from
  2832. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2833. *
  2834. * Return: NULL on success,
  2835. * nbuf when it fails to send
  2836. */
  2837. qdf_nbuf_t
  2838. dp_tx_send_exception_vdev_id_check(struct cdp_soc_t *soc_hdl,
  2839. uint8_t vdev_id, qdf_nbuf_t nbuf,
  2840. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2841. {
  2842. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2843. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2844. DP_MOD_ID_TX_EXCEPTION);
  2845. if (qdf_unlikely(!vdev))
  2846. goto fail;
  2847. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  2848. == QDF_STATUS_E_FAILURE)) {
  2849. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  2850. goto fail;
  2851. }
  2852. /* Unref count as it will agin be taken inside dp_tx_exception */
  2853. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2854. return dp_tx_send_exception(soc_hdl, vdev_id, nbuf, tx_exc_metadata);
  2855. fail:
  2856. if (vdev)
  2857. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2858. dp_verbose_debug("pkt send failed");
  2859. return nbuf;
  2860. }
  2861. /**
  2862. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  2863. * @soc: DP soc handle
  2864. * @vdev_id: DP vdev handle
  2865. * @nbuf: skb
  2866. *
  2867. * Entry point for Core Tx layer (DP_TX) invoked from
  2868. * hard_start_xmit in OSIF/HDD
  2869. *
  2870. * Return: NULL on success,
  2871. * nbuf when it fails to send
  2872. */
  2873. #ifdef MESH_MODE_SUPPORT
  2874. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2875. qdf_nbuf_t nbuf)
  2876. {
  2877. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2878. struct meta_hdr_s *mhdr;
  2879. qdf_nbuf_t nbuf_mesh = NULL;
  2880. qdf_nbuf_t nbuf_clone = NULL;
  2881. struct dp_vdev *vdev;
  2882. uint8_t no_enc_frame = 0;
  2883. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  2884. if (!nbuf_mesh) {
  2885. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2886. "qdf_nbuf_unshare failed");
  2887. return nbuf;
  2888. }
  2889. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_MESH);
  2890. if (!vdev) {
  2891. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2892. "vdev is NULL for vdev_id %d", vdev_id);
  2893. return nbuf;
  2894. }
  2895. nbuf = nbuf_mesh;
  2896. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2897. if ((vdev->sec_type != cdp_sec_type_none) &&
  2898. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  2899. no_enc_frame = 1;
  2900. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  2901. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  2902. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  2903. !no_enc_frame) {
  2904. nbuf_clone = qdf_nbuf_clone(nbuf);
  2905. if (!nbuf_clone) {
  2906. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2907. "qdf_nbuf_clone failed");
  2908. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2909. return nbuf;
  2910. }
  2911. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  2912. }
  2913. if (nbuf_clone) {
  2914. if (!dp_tx_send(soc_hdl, vdev_id, nbuf_clone)) {
  2915. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2916. } else {
  2917. qdf_nbuf_free(nbuf_clone);
  2918. }
  2919. }
  2920. if (no_enc_frame)
  2921. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  2922. else
  2923. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  2924. nbuf = dp_tx_send(soc_hdl, vdev_id, nbuf);
  2925. if ((!nbuf) && no_enc_frame) {
  2926. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2927. }
  2928. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2929. return nbuf;
  2930. }
  2931. #else
  2932. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc, uint8_t vdev_id,
  2933. qdf_nbuf_t nbuf)
  2934. {
  2935. return dp_tx_send(soc, vdev_id, nbuf);
  2936. }
  2937. #endif
  2938. #ifdef QCA_DP_TX_NBUF_AND_NBUF_DATA_PREFETCH
  2939. static inline
  2940. void dp_tx_prefetch_nbuf_data(qdf_nbuf_t nbuf)
  2941. {
  2942. if (nbuf) {
  2943. qdf_prefetch(&nbuf->len);
  2944. qdf_prefetch(&nbuf->data);
  2945. }
  2946. }
  2947. #else
  2948. static inline
  2949. void dp_tx_prefetch_nbuf_data(qdf_nbuf_t nbuf)
  2950. {
  2951. }
  2952. #endif
  2953. #ifdef DP_UMAC_HW_RESET_SUPPORT
  2954. /*
  2955. * dp_tx_drop() - Drop the frame on a given VAP
  2956. * @soc: DP soc handle
  2957. * @vdev_id: id of DP vdev handle
  2958. * @nbuf: skb
  2959. *
  2960. * Drop all the incoming packets
  2961. *
  2962. * Return: nbuf
  2963. *
  2964. */
  2965. qdf_nbuf_t dp_tx_drop(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2966. qdf_nbuf_t nbuf)
  2967. {
  2968. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2969. struct dp_vdev *vdev = NULL;
  2970. vdev = soc->vdev_id_map[vdev_id];
  2971. if (qdf_unlikely(!vdev))
  2972. return nbuf;
  2973. DP_STATS_INC(vdev, tx_i.dropped.drop_ingress, 1);
  2974. return nbuf;
  2975. }
  2976. /*
  2977. * dp_tx_exc_drop() - Drop the frame on a given VAP
  2978. * @soc: DP soc handle
  2979. * @vdev_id: id of DP vdev handle
  2980. * @nbuf: skb
  2981. * @tx_exc_metadata: Handle that holds exception path meta data
  2982. *
  2983. * Drop all the incoming packets
  2984. *
  2985. * Return: nbuf
  2986. *
  2987. */
  2988. qdf_nbuf_t dp_tx_exc_drop(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2989. qdf_nbuf_t nbuf,
  2990. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2991. {
  2992. return dp_tx_drop(soc_hdl, vdev_id, nbuf);
  2993. }
  2994. #endif
  2995. /*
  2996. * dp_tx_send() - Transmit a frame on a given VAP
  2997. * @soc: DP soc handle
  2998. * @vdev_id: id of DP vdev handle
  2999. * @nbuf: skb
  3000. *
  3001. * Entry point for Core Tx layer (DP_TX) invoked from
  3002. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  3003. * cases
  3004. *
  3005. * Return: NULL on success,
  3006. * nbuf when it fails to send
  3007. */
  3008. qdf_nbuf_t dp_tx_send(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3009. qdf_nbuf_t nbuf)
  3010. {
  3011. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3012. uint16_t peer_id = HTT_INVALID_PEER;
  3013. /*
  3014. * doing a memzero is causing additional function call overhead
  3015. * so doing static stack clearing
  3016. */
  3017. struct dp_tx_msdu_info_s msdu_info = {0};
  3018. struct dp_vdev *vdev = NULL;
  3019. qdf_nbuf_t end_nbuf = NULL;
  3020. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  3021. return nbuf;
  3022. /*
  3023. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  3024. * this in per packet path.
  3025. *
  3026. * As in this path vdev memory is already protected with netdev
  3027. * tx lock
  3028. */
  3029. vdev = soc->vdev_id_map[vdev_id];
  3030. if (qdf_unlikely(!vdev))
  3031. return nbuf;
  3032. /*
  3033. * Set Default Host TID value to invalid TID
  3034. * (TID override disabled)
  3035. */
  3036. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  3037. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_headlen(nbuf));
  3038. if (qdf_unlikely(vdev->mesh_vdev)) {
  3039. qdf_nbuf_t nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  3040. &msdu_info);
  3041. if (!nbuf_mesh) {
  3042. dp_verbose_debug("Extracting mesh metadata failed");
  3043. return nbuf;
  3044. }
  3045. nbuf = nbuf_mesh;
  3046. }
  3047. /*
  3048. * Get HW Queue to use for this frame.
  3049. * TCL supports upto 4 DMA rings, out of which 3 rings are
  3050. * dedicated for data and 1 for command.
  3051. * "queue_id" maps to one hardware ring.
  3052. * With each ring, we also associate a unique Tx descriptor pool
  3053. * to minimize lock contention for these resources.
  3054. */
  3055. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  3056. DP_STATS_INC(vdev, tx_i.rcvd_per_core[msdu_info.tx_queue.desc_pool_id],
  3057. 1);
  3058. /*
  3059. * TCL H/W supports 2 DSCP-TID mapping tables.
  3060. * Table 1 - Default DSCP-TID mapping table
  3061. * Table 2 - 1 DSCP-TID override table
  3062. *
  3063. * If we need a different DSCP-TID mapping for this vap,
  3064. * call tid_classify to extract DSCP/ToS from frame and
  3065. * map to a TID and store in msdu_info. This is later used
  3066. * to fill in TCL Input descriptor (per-packet TID override).
  3067. */
  3068. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  3069. /*
  3070. * Classify the frame and call corresponding
  3071. * "prepare" function which extracts the segment (TSO)
  3072. * and fragmentation information (for TSO , SG, ME, or Raw)
  3073. * into MSDU_INFO structure which is later used to fill
  3074. * SW and HW descriptors.
  3075. */
  3076. if (qdf_nbuf_is_tso(nbuf)) {
  3077. dp_verbose_debug("TSO frame %pK", vdev);
  3078. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  3079. qdf_nbuf_len(nbuf));
  3080. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  3081. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  3082. qdf_nbuf_len(nbuf));
  3083. return nbuf;
  3084. }
  3085. goto send_multiple;
  3086. }
  3087. /* SG */
  3088. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  3089. if (qdf_nbuf_get_nr_frags(nbuf) > DP_TX_MAX_NUM_FRAGS - 1) {
  3090. if (qdf_unlikely(qdf_nbuf_linearize(nbuf)))
  3091. return nbuf;
  3092. } else {
  3093. struct dp_tx_seg_info_s seg_info = {0};
  3094. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info,
  3095. &msdu_info);
  3096. if (!nbuf)
  3097. return NULL;
  3098. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  3099. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  3100. qdf_nbuf_len(nbuf));
  3101. goto send_multiple;
  3102. }
  3103. }
  3104. if (qdf_unlikely(!dp_tx_mcast_enhance(vdev, nbuf)))
  3105. return NULL;
  3106. /* RAW */
  3107. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  3108. struct dp_tx_seg_info_s seg_info = {0};
  3109. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  3110. if (!nbuf)
  3111. return NULL;
  3112. dp_verbose_debug("Raw frame %pK", vdev);
  3113. goto send_multiple;
  3114. }
  3115. if (qdf_unlikely(vdev->nawds_enabled)) {
  3116. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  3117. qdf_nbuf_data(nbuf);
  3118. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  3119. uint16_t sa_peer_id = DP_INVALID_PEER;
  3120. if (!soc->ast_offload_support) {
  3121. struct dp_ast_entry *ast_entry = NULL;
  3122. qdf_spin_lock_bh(&soc->ast_lock);
  3123. ast_entry = dp_peer_ast_hash_find_by_pdevid
  3124. (soc,
  3125. (uint8_t *)(eh->ether_shost),
  3126. vdev->pdev->pdev_id);
  3127. if (ast_entry)
  3128. sa_peer_id = ast_entry->peer_id;
  3129. qdf_spin_unlock_bh(&soc->ast_lock);
  3130. }
  3131. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf,
  3132. sa_peer_id);
  3133. }
  3134. peer_id = DP_INVALID_PEER;
  3135. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  3136. 1, qdf_nbuf_len(nbuf));
  3137. }
  3138. /* Single linear frame */
  3139. /*
  3140. * If nbuf is a simple linear frame, use send_single function to
  3141. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  3142. * SRNG. There is no need to setup a MSDU extension descriptor.
  3143. */
  3144. dp_tx_prefetch_nbuf_data(nbuf);
  3145. nbuf = dp_tx_send_msdu_single_wrapper(vdev, nbuf, &msdu_info,
  3146. peer_id, end_nbuf);
  3147. return nbuf;
  3148. send_multiple:
  3149. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  3150. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  3151. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  3152. return nbuf;
  3153. }
  3154. /**
  3155. * dp_tx_send_vdev_id_check() - Transmit a frame on a given VAP in special
  3156. * case to vaoid check in perpkt path.
  3157. * @soc: DP soc handle
  3158. * @vdev_id: id of DP vdev handle
  3159. * @nbuf: skb
  3160. *
  3161. * Entry point for Core Tx layer (DP_TX) invoked from
  3162. * hard_start_xmit in OSIF/HDD to transmit packet through dp_tx_send
  3163. * with special condition to avoid per pkt check in dp_tx_send
  3164. *
  3165. * Return: NULL on success,
  3166. * nbuf when it fails to send
  3167. */
  3168. qdf_nbuf_t dp_tx_send_vdev_id_check(struct cdp_soc_t *soc_hdl,
  3169. uint8_t vdev_id, qdf_nbuf_t nbuf)
  3170. {
  3171. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3172. struct dp_vdev *vdev = NULL;
  3173. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  3174. return nbuf;
  3175. /*
  3176. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  3177. * this in per packet path.
  3178. *
  3179. * As in this path vdev memory is already protected with netdev
  3180. * tx lock
  3181. */
  3182. vdev = soc->vdev_id_map[vdev_id];
  3183. if (qdf_unlikely(!vdev))
  3184. return nbuf;
  3185. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  3186. == QDF_STATUS_E_FAILURE)) {
  3187. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  3188. return nbuf;
  3189. }
  3190. return dp_tx_send(soc_hdl, vdev_id, nbuf);
  3191. }
  3192. #ifdef UMAC_SUPPORT_PROXY_ARP
  3193. /**
  3194. * dp_tx_proxy_arp() - Tx proxy arp handler
  3195. * @vdev: datapath vdev handle
  3196. * @buf: sk buffer
  3197. *
  3198. * Return: status
  3199. */
  3200. static inline
  3201. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  3202. {
  3203. if (vdev->osif_proxy_arp)
  3204. return vdev->osif_proxy_arp(vdev->osif_vdev, nbuf);
  3205. /*
  3206. * when UMAC_SUPPORT_PROXY_ARP is defined, we expect
  3207. * osif_proxy_arp has a valid function pointer assigned
  3208. * to it
  3209. */
  3210. dp_tx_err("valid function pointer for osif_proxy_arp is expected!!\n");
  3211. return QDF_STATUS_NOT_INITIALIZED;
  3212. }
  3213. #else
  3214. /**
  3215. * dp_tx_proxy_arp() - Tx proxy arp handler
  3216. * @vdev: datapath vdev handle
  3217. * @buf: sk buffer
  3218. *
  3219. * This function always return 0 when UMAC_SUPPORT_PROXY_ARP
  3220. * is not defined.
  3221. *
  3222. * Return: status
  3223. */
  3224. static inline
  3225. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  3226. {
  3227. return QDF_STATUS_SUCCESS;
  3228. }
  3229. #endif
  3230. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP)
  3231. #ifdef WLAN_MCAST_MLO
  3232. static bool
  3233. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3234. struct dp_tx_desc_s *tx_desc,
  3235. qdf_nbuf_t nbuf,
  3236. uint8_t reinject_reason)
  3237. {
  3238. if (reinject_reason == HTT_TX_FW2WBM_REINJECT_REASON_MLO_MCAST) {
  3239. if (soc->arch_ops.dp_tx_mcast_handler)
  3240. soc->arch_ops.dp_tx_mcast_handler(soc, vdev, nbuf);
  3241. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3242. return true;
  3243. }
  3244. return false;
  3245. }
  3246. #else /* WLAN_MCAST_MLO */
  3247. static inline bool
  3248. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3249. struct dp_tx_desc_s *tx_desc,
  3250. qdf_nbuf_t nbuf,
  3251. uint8_t reinject_reason)
  3252. {
  3253. return false;
  3254. }
  3255. #endif /* WLAN_MCAST_MLO */
  3256. #else
  3257. static inline bool
  3258. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3259. struct dp_tx_desc_s *tx_desc,
  3260. qdf_nbuf_t nbuf,
  3261. uint8_t reinject_reason)
  3262. {
  3263. return false;
  3264. }
  3265. #endif
  3266. /**
  3267. * dp_tx_reinject_handler() - Tx Reinject Handler
  3268. * @soc: datapath soc handle
  3269. * @vdev: datapath vdev handle
  3270. * @tx_desc: software descriptor head pointer
  3271. * @status : Tx completion status from HTT descriptor
  3272. * @reinject_reason : reinject reason from HTT descriptor
  3273. *
  3274. * This function reinjects frames back to Target.
  3275. * Todo - Host queue needs to be added
  3276. *
  3277. * Return: none
  3278. */
  3279. void dp_tx_reinject_handler(struct dp_soc *soc,
  3280. struct dp_vdev *vdev,
  3281. struct dp_tx_desc_s *tx_desc,
  3282. uint8_t *status,
  3283. uint8_t reinject_reason)
  3284. {
  3285. struct dp_peer *peer = NULL;
  3286. uint32_t peer_id = HTT_INVALID_PEER;
  3287. qdf_nbuf_t nbuf = tx_desc->nbuf;
  3288. qdf_nbuf_t nbuf_copy = NULL;
  3289. struct dp_tx_msdu_info_s msdu_info;
  3290. #ifdef WDS_VENDOR_EXTENSION
  3291. int is_mcast = 0, is_ucast = 0;
  3292. int num_peers_3addr = 0;
  3293. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  3294. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  3295. #endif
  3296. struct dp_txrx_peer *txrx_peer;
  3297. qdf_assert(vdev);
  3298. dp_tx_debug("Tx reinject path");
  3299. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  3300. qdf_nbuf_len(tx_desc->nbuf));
  3301. if (dp_tx_reinject_mlo_hdl(soc, vdev, tx_desc, nbuf, reinject_reason))
  3302. return;
  3303. #ifdef WDS_VENDOR_EXTENSION
  3304. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  3305. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  3306. } else {
  3307. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  3308. }
  3309. is_ucast = !is_mcast;
  3310. qdf_spin_lock_bh(&vdev->peer_list_lock);
  3311. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3312. txrx_peer = dp_get_txrx_peer(peer);
  3313. if (!txrx_peer || txrx_peer->bss_peer)
  3314. continue;
  3315. /* Detect wds peers that use 3-addr framing for mcast.
  3316. * if there are any, the bss_peer is used to send the
  3317. * the mcast frame using 3-addr format. all wds enabled
  3318. * peers that use 4-addr framing for mcast frames will
  3319. * be duplicated and sent as 4-addr frames below.
  3320. */
  3321. if (!txrx_peer->wds_enabled ||
  3322. !txrx_peer->wds_ecm.wds_tx_mcast_4addr) {
  3323. num_peers_3addr = 1;
  3324. break;
  3325. }
  3326. }
  3327. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  3328. #endif
  3329. if (qdf_unlikely(vdev->mesh_vdev)) {
  3330. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  3331. } else {
  3332. qdf_spin_lock_bh(&vdev->peer_list_lock);
  3333. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3334. txrx_peer = dp_get_txrx_peer(peer);
  3335. if (!txrx_peer)
  3336. continue;
  3337. if ((txrx_peer->peer_id != HTT_INVALID_PEER) &&
  3338. #ifdef WDS_VENDOR_EXTENSION
  3339. /*
  3340. * . if 3-addr STA, then send on BSS Peer
  3341. * . if Peer WDS enabled and accept 4-addr mcast,
  3342. * send mcast on that peer only
  3343. * . if Peer WDS enabled and accept 4-addr ucast,
  3344. * send ucast on that peer only
  3345. */
  3346. ((txrx_peer->bss_peer && num_peers_3addr && is_mcast) ||
  3347. (txrx_peer->wds_enabled &&
  3348. ((is_mcast && txrx_peer->wds_ecm.wds_tx_mcast_4addr) ||
  3349. (is_ucast &&
  3350. txrx_peer->wds_ecm.wds_tx_ucast_4addr))))) {
  3351. #else
  3352. (txrx_peer->bss_peer &&
  3353. (dp_tx_proxy_arp(vdev, nbuf) == QDF_STATUS_SUCCESS))) {
  3354. #endif
  3355. peer_id = DP_INVALID_PEER;
  3356. nbuf_copy = qdf_nbuf_copy(nbuf);
  3357. if (!nbuf_copy) {
  3358. dp_tx_debug("nbuf copy failed");
  3359. break;
  3360. }
  3361. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  3362. dp_tx_get_queue(vdev, nbuf,
  3363. &msdu_info.tx_queue);
  3364. nbuf_copy = dp_tx_send_msdu_single(vdev,
  3365. nbuf_copy,
  3366. &msdu_info,
  3367. peer_id,
  3368. NULL);
  3369. if (nbuf_copy) {
  3370. dp_tx_debug("pkt send failed");
  3371. qdf_nbuf_free(nbuf_copy);
  3372. }
  3373. }
  3374. }
  3375. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  3376. }
  3377. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf, QDF_DMA_TO_DEVICE,
  3378. nbuf->len);
  3379. qdf_nbuf_free(nbuf);
  3380. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3381. }
  3382. /**
  3383. * dp_tx_inspect_handler() - Tx Inspect Handler
  3384. * @soc: datapath soc handle
  3385. * @vdev: datapath vdev handle
  3386. * @tx_desc: software descriptor head pointer
  3387. * @status : Tx completion status from HTT descriptor
  3388. *
  3389. * Handles Tx frames sent back to Host for inspection
  3390. * (ProxyARP)
  3391. *
  3392. * Return: none
  3393. */
  3394. void dp_tx_inspect_handler(struct dp_soc *soc,
  3395. struct dp_vdev *vdev,
  3396. struct dp_tx_desc_s *tx_desc,
  3397. uint8_t *status)
  3398. {
  3399. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3400. "%s Tx inspect path",
  3401. __func__);
  3402. DP_STATS_INC_PKT(vdev, tx_i.inspect_pkts, 1,
  3403. qdf_nbuf_len(tx_desc->nbuf));
  3404. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  3405. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3406. }
  3407. #ifdef MESH_MODE_SUPPORT
  3408. /**
  3409. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  3410. * in mesh meta header
  3411. * @tx_desc: software descriptor head pointer
  3412. * @ts: pointer to tx completion stats
  3413. * Return: none
  3414. */
  3415. static
  3416. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3417. struct hal_tx_completion_status *ts)
  3418. {
  3419. qdf_nbuf_t netbuf = tx_desc->nbuf;
  3420. if (!tx_desc->msdu_ext_desc) {
  3421. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  3422. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3423. "netbuf %pK offset %d",
  3424. netbuf, tx_desc->pkt_offset);
  3425. return;
  3426. }
  3427. }
  3428. }
  3429. #else
  3430. static
  3431. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3432. struct hal_tx_completion_status *ts)
  3433. {
  3434. }
  3435. #endif
  3436. #ifdef CONFIG_SAWF
  3437. static void dp_tx_update_peer_sawf_stats(struct dp_soc *soc,
  3438. struct dp_vdev *vdev,
  3439. struct dp_txrx_peer *txrx_peer,
  3440. struct dp_tx_desc_s *tx_desc,
  3441. struct hal_tx_completion_status *ts,
  3442. uint8_t tid)
  3443. {
  3444. dp_sawf_tx_compl_update_peer_stats(soc, vdev, txrx_peer, tx_desc,
  3445. ts, tid);
  3446. }
  3447. #else
  3448. static void dp_tx_update_peer_sawf_stats(struct dp_soc *soc,
  3449. struct dp_vdev *vdev,
  3450. struct dp_txrx_peer *txrx_peer,
  3451. struct dp_tx_desc_s *tx_desc,
  3452. struct hal_tx_completion_status *ts,
  3453. uint8_t tid)
  3454. {
  3455. }
  3456. #endif
  3457. #ifdef QCA_PEER_EXT_STATS
  3458. /*
  3459. * dp_tx_compute_tid_delay() - Compute per TID delay
  3460. * @stats: Per TID delay stats
  3461. * @tx_desc: Software Tx descriptor
  3462. *
  3463. * Compute the software enqueue and hw enqueue delays and
  3464. * update the respective histograms
  3465. *
  3466. * Return: void
  3467. */
  3468. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  3469. struct dp_tx_desc_s *tx_desc)
  3470. {
  3471. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  3472. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3473. uint32_t sw_enqueue_delay, fwhw_transmit_delay;
  3474. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3475. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3476. timestamp_hw_enqueue = qdf_ktime_to_ms(tx_desc->timestamp);
  3477. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3478. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3479. timestamp_hw_enqueue);
  3480. /*
  3481. * Update the Tx software enqueue delay and HW enque-Completion delay.
  3482. */
  3483. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  3484. dp_hist_update_stats(&tx_delay->hwtx_delay, fwhw_transmit_delay);
  3485. }
  3486. /*
  3487. * dp_tx_update_peer_delay_stats() - Update the peer delay stats
  3488. * @txrx_peer: DP peer context
  3489. * @tx_desc: Tx software descriptor
  3490. * @tid: Transmission ID
  3491. * @ring_id: Rx CPU context ID/CPU_ID
  3492. *
  3493. * Update the peer extended stats. These are enhanced other
  3494. * delay stats per msdu level.
  3495. *
  3496. * Return: void
  3497. */
  3498. static void dp_tx_update_peer_delay_stats(struct dp_txrx_peer *txrx_peer,
  3499. struct dp_tx_desc_s *tx_desc,
  3500. uint8_t tid, uint8_t ring_id)
  3501. {
  3502. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  3503. struct dp_soc *soc = NULL;
  3504. struct dp_peer_delay_stats *delay_stats = NULL;
  3505. soc = pdev->soc;
  3506. if (qdf_likely(!wlan_cfg_is_peer_ext_stats_enabled(soc->wlan_cfg_ctx)))
  3507. return;
  3508. delay_stats = txrx_peer->delay_stats;
  3509. qdf_assert(delay_stats);
  3510. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  3511. /*
  3512. * For non-TID packets use the TID 9
  3513. */
  3514. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3515. tid = CDP_MAX_DATA_TIDS - 1;
  3516. dp_tx_compute_tid_delay(&delay_stats->delay_tid_stats[tid][ring_id],
  3517. tx_desc);
  3518. }
  3519. #else
  3520. static inline void dp_tx_update_peer_delay_stats(struct dp_txrx_peer *txrx_peer,
  3521. struct dp_tx_desc_s *tx_desc,
  3522. uint8_t tid, uint8_t ring_id)
  3523. {
  3524. }
  3525. #endif
  3526. #ifdef HW_TX_DELAY_STATS_ENABLE
  3527. /**
  3528. * dp_update_tx_delay_stats() - update the delay stats
  3529. * @vdev: vdev handle
  3530. * @delay: delay in ms or us based on the flag delay_in_us
  3531. * @tid: tid value
  3532. * @mode: type of tx delay mode
  3533. * @ring id: ring number
  3534. * @delay_in_us: flag to indicate whether the delay is in ms or us
  3535. *
  3536. * Return: none
  3537. */
  3538. static inline
  3539. void dp_update_tx_delay_stats(struct dp_vdev *vdev, uint32_t delay, uint8_t tid,
  3540. uint8_t mode, uint8_t ring_id, bool delay_in_us)
  3541. {
  3542. struct cdp_tid_tx_stats *tstats =
  3543. &vdev->stats.tid_tx_stats[ring_id][tid];
  3544. dp_update_delay_stats(tstats, NULL, delay, tid, mode, ring_id,
  3545. delay_in_us);
  3546. }
  3547. #else
  3548. static inline
  3549. void dp_update_tx_delay_stats(struct dp_vdev *vdev, uint32_t delay, uint8_t tid,
  3550. uint8_t mode, uint8_t ring_id, bool delay_in_us)
  3551. {
  3552. struct cdp_tid_tx_stats *tstats =
  3553. &vdev->pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3554. dp_update_delay_stats(tstats, NULL, delay, tid, mode, ring_id,
  3555. delay_in_us);
  3556. }
  3557. #endif
  3558. /**
  3559. * dp_tx_compute_delay() - Compute and fill in all timestamps
  3560. * to pass in correct fields
  3561. *
  3562. * @vdev: pdev handle
  3563. * @tx_desc: tx descriptor
  3564. * @tid: tid value
  3565. * @ring_id: TCL or WBM ring number for transmit path
  3566. * Return: none
  3567. */
  3568. void dp_tx_compute_delay(struct dp_vdev *vdev, struct dp_tx_desc_s *tx_desc,
  3569. uint8_t tid, uint8_t ring_id)
  3570. {
  3571. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3572. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  3573. uint32_t fwhw_transmit_delay_us;
  3574. if (qdf_likely(!vdev->pdev->delay_stats_flag) &&
  3575. qdf_likely(!dp_is_vdev_tx_delay_stats_enabled(vdev)))
  3576. return;
  3577. if (dp_is_vdev_tx_delay_stats_enabled(vdev)) {
  3578. fwhw_transmit_delay_us =
  3579. qdf_ktime_to_us(qdf_ktime_real_get()) -
  3580. qdf_ktime_to_us(tx_desc->timestamp);
  3581. /*
  3582. * Delay between packet enqueued to HW and Tx completion in us
  3583. */
  3584. dp_update_tx_delay_stats(vdev, fwhw_transmit_delay_us, tid,
  3585. CDP_DELAY_STATS_FW_HW_TRANSMIT,
  3586. ring_id, true);
  3587. /*
  3588. * For MCL, only enqueue to completion delay is required
  3589. * so return if the vdev flag is enabled.
  3590. */
  3591. return;
  3592. }
  3593. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3594. timestamp_hw_enqueue = qdf_ktime_to_ms(tx_desc->timestamp);
  3595. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3596. timestamp_hw_enqueue);
  3597. /*
  3598. * Delay between packet enqueued to HW and Tx completion in ms
  3599. */
  3600. dp_update_tx_delay_stats(vdev, fwhw_transmit_delay, tid,
  3601. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id,
  3602. false);
  3603. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3604. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3605. interframe_delay = (uint32_t)(timestamp_ingress -
  3606. vdev->prev_tx_enq_tstamp);
  3607. /*
  3608. * Delay in software enqueue
  3609. */
  3610. dp_update_tx_delay_stats(vdev, sw_enqueue_delay, tid,
  3611. CDP_DELAY_STATS_SW_ENQ, ring_id,
  3612. false);
  3613. /*
  3614. * Update interframe delay stats calculated at hardstart receive point.
  3615. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  3616. * interframe delay will not be calculate correctly for 1st frame.
  3617. * On the other side, this will help in avoiding extra per packet check
  3618. * of !vdev->prev_tx_enq_tstamp.
  3619. */
  3620. dp_update_tx_delay_stats(vdev, interframe_delay, tid,
  3621. CDP_DELAY_STATS_TX_INTERFRAME, ring_id,
  3622. false);
  3623. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  3624. }
  3625. #ifdef DISABLE_DP_STATS
  3626. static
  3627. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf,
  3628. struct dp_txrx_peer *txrx_peer)
  3629. {
  3630. }
  3631. #else
  3632. static inline void
  3633. dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_txrx_peer *txrx_peer)
  3634. {
  3635. enum qdf_proto_subtype subtype = QDF_PROTO_INVALID;
  3636. DPTRACE(qdf_dp_track_noack_check(nbuf, &subtype));
  3637. if (subtype != QDF_PROTO_INVALID)
  3638. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.no_ack_count[subtype],
  3639. 1);
  3640. }
  3641. #endif
  3642. #ifndef QCA_ENHANCED_STATS_SUPPORT
  3643. /**
  3644. * dp_tx_update_peer_extd_stats()- Update Tx extended path stats for peer
  3645. *
  3646. * @ts: Tx compltion status
  3647. * @txrx_peer: datapath txrx_peer handle
  3648. *
  3649. * Return: void
  3650. */
  3651. static inline void
  3652. dp_tx_update_peer_extd_stats(struct hal_tx_completion_status *ts,
  3653. struct dp_txrx_peer *txrx_peer)
  3654. {
  3655. uint8_t mcs, pkt_type, dst_mcs_idx;
  3656. uint8_t retry_threshold = txrx_peer->mpdu_retry_threshold;
  3657. mcs = ts->mcs;
  3658. pkt_type = ts->pkt_type;
  3659. /* do HW to SW pkt type conversion */
  3660. pkt_type = (pkt_type >= HAL_DOT11_MAX ? DOT11_MAX :
  3661. hal_2_dp_pkt_type_map[pkt_type]);
  3662. dst_mcs_idx = dp_get_mcs_array_index_by_pkt_type_mcs(pkt_type, mcs);
  3663. if (MCS_INVALID_ARRAY_INDEX != dst_mcs_idx)
  3664. DP_PEER_EXTD_STATS_INC(txrx_peer,
  3665. tx.pkt_type[pkt_type].mcs_count[dst_mcs_idx],
  3666. 1);
  3667. DP_PEER_EXTD_STATS_INC(txrx_peer, tx.sgi_count[ts->sgi], 1);
  3668. DP_PEER_EXTD_STATS_INC(txrx_peer, tx.bw[ts->bw], 1);
  3669. DP_PEER_EXTD_STATS_UPD(txrx_peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  3670. DP_PEER_EXTD_STATS_INC(txrx_peer,
  3671. tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  3672. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.stbc, 1, ts->stbc);
  3673. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.ldpc, 1, ts->ldpc);
  3674. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.retries, 1, ts->transmit_cnt > 1);
  3675. if (ts->first_msdu) {
  3676. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.retries_mpdu, 1,
  3677. ts->transmit_cnt > 1);
  3678. if (!retry_threshold)
  3679. return;
  3680. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.mpdu_success_with_retries,
  3681. qdf_do_div(ts->transmit_cnt,
  3682. retry_threshold),
  3683. ts->transmit_cnt > retry_threshold);
  3684. }
  3685. }
  3686. #else
  3687. static inline void
  3688. dp_tx_update_peer_extd_stats(struct hal_tx_completion_status *ts,
  3689. struct dp_txrx_peer *txrx_peer)
  3690. {
  3691. }
  3692. #endif
  3693. /**
  3694. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  3695. * per wbm ring
  3696. *
  3697. * @tx_desc: software descriptor head pointer
  3698. * @ts: Tx completion status
  3699. * @peer: peer handle
  3700. * @ring_id: ring number
  3701. *
  3702. * Return: None
  3703. */
  3704. static inline void
  3705. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  3706. struct hal_tx_completion_status *ts,
  3707. struct dp_txrx_peer *txrx_peer, uint8_t ring_id)
  3708. {
  3709. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  3710. uint8_t tid = ts->tid;
  3711. uint32_t length;
  3712. struct cdp_tid_tx_stats *tid_stats;
  3713. if (!pdev)
  3714. return;
  3715. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3716. tid = CDP_MAX_DATA_TIDS - 1;
  3717. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3718. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  3719. dp_err_rl("Release source:%d is not from TQM", ts->release_src);
  3720. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.release_src_not_tqm, 1);
  3721. return;
  3722. }
  3723. length = qdf_nbuf_len(tx_desc->nbuf);
  3724. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  3725. if (qdf_unlikely(pdev->delay_stats_flag) ||
  3726. qdf_unlikely(dp_is_vdev_tx_delay_stats_enabled(txrx_peer->vdev)))
  3727. dp_tx_compute_delay(txrx_peer->vdev, tx_desc, tid, ring_id);
  3728. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  3729. tid_stats->tqm_status_cnt[ts->status]++;
  3730. }
  3731. if (qdf_likely(ts->status == HAL_TX_TQM_RR_FRAME_ACKED)) {
  3732. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.retry_count, 1,
  3733. ts->transmit_cnt > 1);
  3734. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.multiple_retry_count,
  3735. 1, ts->transmit_cnt > 2);
  3736. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.ofdma, 1, ts->ofdma);
  3737. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.amsdu_cnt, 1,
  3738. ts->msdu_part_of_amsdu);
  3739. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.non_amsdu_cnt, 1,
  3740. !ts->msdu_part_of_amsdu);
  3741. txrx_peer->stats.per_pkt_stats.tx.last_tx_ts =
  3742. qdf_system_ticks();
  3743. dp_tx_update_peer_extd_stats(ts, txrx_peer);
  3744. return;
  3745. }
  3746. /*
  3747. * tx_failed is ideally supposed to be updated from HTT ppdu
  3748. * completion stats. But in IPQ807X/IPQ6018 chipsets owing to
  3749. * hw limitation there are no completions for failed cases.
  3750. * Hence updating tx_failed from data path. Please note that
  3751. * if tx_failed is fixed to be from ppdu, then this has to be
  3752. * removed
  3753. */
  3754. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  3755. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.failed_retry_count, 1,
  3756. ts->transmit_cnt > DP_RETRY_COUNT);
  3757. dp_update_no_ack_stats(tx_desc->nbuf, txrx_peer);
  3758. if (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED) {
  3759. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.age_out, 1);
  3760. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_REM) {
  3761. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.dropped.fw_rem, 1,
  3762. length);
  3763. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX) {
  3764. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_rem_notx, 1);
  3765. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_TX) {
  3766. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_rem_tx, 1);
  3767. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON1) {
  3768. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason1, 1);
  3769. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON2) {
  3770. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason2, 1);
  3771. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON3) {
  3772. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason3, 1);
  3773. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_DISABLE_QUEUE) {
  3774. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  3775. tx.dropped.fw_rem_queue_disable, 1);
  3776. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_TILL_NONMATCHING) {
  3777. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  3778. tx.dropped.fw_rem_no_match, 1);
  3779. } else if (ts->status == HAL_TX_TQM_RR_DROP_THRESHOLD) {
  3780. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  3781. tx.dropped.drop_threshold, 1);
  3782. } else if (ts->status == HAL_TX_TQM_RR_LINK_DESC_UNAVAILABLE) {
  3783. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  3784. tx.dropped.drop_link_desc_na, 1);
  3785. } else if (ts->status == HAL_TX_TQM_RR_DROP_OR_INVALID_MSDU) {
  3786. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  3787. tx.dropped.invalid_drop, 1);
  3788. } else if (ts->status == HAL_TX_TQM_RR_MULTICAST_DROP) {
  3789. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  3790. tx.dropped.mcast_vdev_drop, 1);
  3791. } else {
  3792. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.invalid_rr, 1);
  3793. }
  3794. }
  3795. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3796. /**
  3797. * dp_tx_flow_pool_lock() - take flow pool lock
  3798. * @soc: core txrx main context
  3799. * @tx_desc: tx desc
  3800. *
  3801. * Return: None
  3802. */
  3803. static inline
  3804. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  3805. struct dp_tx_desc_s *tx_desc)
  3806. {
  3807. struct dp_tx_desc_pool_s *pool;
  3808. uint8_t desc_pool_id;
  3809. desc_pool_id = tx_desc->pool_id;
  3810. pool = &soc->tx_desc[desc_pool_id];
  3811. qdf_spin_lock_bh(&pool->flow_pool_lock);
  3812. }
  3813. /**
  3814. * dp_tx_flow_pool_unlock() - release flow pool lock
  3815. * @soc: core txrx main context
  3816. * @tx_desc: tx desc
  3817. *
  3818. * Return: None
  3819. */
  3820. static inline
  3821. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  3822. struct dp_tx_desc_s *tx_desc)
  3823. {
  3824. struct dp_tx_desc_pool_s *pool;
  3825. uint8_t desc_pool_id;
  3826. desc_pool_id = tx_desc->pool_id;
  3827. pool = &soc->tx_desc[desc_pool_id];
  3828. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  3829. }
  3830. #else
  3831. static inline
  3832. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3833. {
  3834. }
  3835. static inline
  3836. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3837. {
  3838. }
  3839. #endif
  3840. /**
  3841. * dp_tx_notify_completion() - Notify tx completion for this desc
  3842. * @soc: core txrx main context
  3843. * @vdev: datapath vdev handle
  3844. * @tx_desc: tx desc
  3845. * @netbuf: buffer
  3846. * @status: tx status
  3847. *
  3848. * Return: none
  3849. */
  3850. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  3851. struct dp_vdev *vdev,
  3852. struct dp_tx_desc_s *tx_desc,
  3853. qdf_nbuf_t netbuf,
  3854. uint8_t status)
  3855. {
  3856. void *osif_dev;
  3857. ol_txrx_completion_fp tx_compl_cbk = NULL;
  3858. uint16_t flag = BIT(QDF_TX_RX_STATUS_DOWNLOAD_SUCC);
  3859. qdf_assert(tx_desc);
  3860. if (!vdev ||
  3861. !vdev->osif_vdev) {
  3862. return;
  3863. }
  3864. osif_dev = vdev->osif_vdev;
  3865. tx_compl_cbk = vdev->tx_comp;
  3866. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3867. flag |= BIT(QDF_TX_RX_STATUS_OK);
  3868. if (tx_compl_cbk)
  3869. tx_compl_cbk(netbuf, osif_dev, flag);
  3870. }
  3871. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  3872. * @pdev: pdev handle
  3873. * @tid: tid value
  3874. * @txdesc_ts: timestamp from txdesc
  3875. * @ppdu_id: ppdu id
  3876. *
  3877. * Return: none
  3878. */
  3879. #ifdef FEATURE_PERPKT_INFO
  3880. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3881. struct dp_txrx_peer *txrx_peer,
  3882. uint8_t tid,
  3883. uint64_t txdesc_ts,
  3884. uint32_t ppdu_id)
  3885. {
  3886. uint64_t delta_ms;
  3887. struct cdp_tx_sojourn_stats *sojourn_stats;
  3888. struct dp_peer *primary_link_peer = NULL;
  3889. struct dp_soc *link_peer_soc = NULL;
  3890. if (qdf_unlikely(!pdev->enhanced_stats_en))
  3891. return;
  3892. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  3893. tid >= CDP_DATA_TID_MAX))
  3894. return;
  3895. if (qdf_unlikely(!pdev->sojourn_buf))
  3896. return;
  3897. primary_link_peer = dp_get_primary_link_peer_by_id(pdev->soc,
  3898. txrx_peer->peer_id,
  3899. DP_MOD_ID_TX_COMP);
  3900. if (qdf_unlikely(!primary_link_peer))
  3901. return;
  3902. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  3903. qdf_nbuf_data(pdev->sojourn_buf);
  3904. link_peer_soc = primary_link_peer->vdev->pdev->soc;
  3905. sojourn_stats->cookie = (void *)
  3906. dp_monitor_peer_get_peerstats_ctx(link_peer_soc,
  3907. primary_link_peer);
  3908. delta_ms = qdf_ktime_to_ms(qdf_ktime_real_get()) -
  3909. txdesc_ts;
  3910. qdf_ewma_tx_lag_add(&txrx_peer->stats.per_pkt_stats.tx.avg_sojourn_msdu[tid],
  3911. delta_ms);
  3912. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  3913. sojourn_stats->num_msdus[tid] = 1;
  3914. sojourn_stats->avg_sojourn_msdu[tid].internal =
  3915. txrx_peer->stats.per_pkt_stats.tx.avg_sojourn_msdu[tid].internal;
  3916. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  3917. pdev->sojourn_buf, HTT_INVALID_PEER,
  3918. WDI_NO_VAL, pdev->pdev_id);
  3919. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  3920. sojourn_stats->num_msdus[tid] = 0;
  3921. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  3922. dp_peer_unref_delete(primary_link_peer, DP_MOD_ID_TX_COMP);
  3923. }
  3924. #else
  3925. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3926. struct dp_txrx_peer *txrx_peer,
  3927. uint8_t tid,
  3928. uint64_t txdesc_ts,
  3929. uint32_t ppdu_id)
  3930. {
  3931. }
  3932. #endif
  3933. #ifdef WLAN_FEATURE_PKT_CAPTURE_V2
  3934. /**
  3935. * dp_send_completion_to_pkt_capture() - send tx completion to packet capture
  3936. * @soc: dp_soc handle
  3937. * @desc: Tx Descriptor
  3938. * @ts: HAL Tx completion descriptor contents
  3939. *
  3940. * This function is used to send tx completion to packet capture
  3941. */
  3942. void dp_send_completion_to_pkt_capture(struct dp_soc *soc,
  3943. struct dp_tx_desc_s *desc,
  3944. struct hal_tx_completion_status *ts)
  3945. {
  3946. dp_wdi_event_handler(WDI_EVENT_PKT_CAPTURE_TX_DATA, soc,
  3947. desc, ts->peer_id,
  3948. WDI_NO_VAL, desc->pdev->pdev_id);
  3949. }
  3950. #endif
  3951. /**
  3952. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  3953. * @soc: DP Soc handle
  3954. * @tx_desc: software Tx descriptor
  3955. * @ts : Tx completion status from HAL/HTT descriptor
  3956. *
  3957. * Return: none
  3958. */
  3959. void
  3960. dp_tx_comp_process_desc(struct dp_soc *soc,
  3961. struct dp_tx_desc_s *desc,
  3962. struct hal_tx_completion_status *ts,
  3963. struct dp_txrx_peer *txrx_peer)
  3964. {
  3965. uint64_t time_latency = 0;
  3966. uint16_t peer_id = DP_INVALID_PEER_ID;
  3967. /*
  3968. * m_copy/tx_capture modes are not supported for
  3969. * scatter gather packets
  3970. */
  3971. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  3972. time_latency = (qdf_ktime_to_ms(qdf_ktime_real_get()) -
  3973. qdf_ktime_to_ms(desc->timestamp));
  3974. }
  3975. dp_send_completion_to_pkt_capture(soc, desc, ts);
  3976. if (dp_tx_pkt_tracepoints_enabled())
  3977. qdf_trace_dp_packet(desc->nbuf, QDF_TX,
  3978. desc->msdu_ext_desc ?
  3979. desc->msdu_ext_desc->tso_desc : NULL,
  3980. qdf_ktime_to_ms(desc->timestamp));
  3981. if (!(desc->msdu_ext_desc)) {
  3982. dp_tx_enh_unmap(soc, desc);
  3983. if (txrx_peer)
  3984. peer_id = txrx_peer->peer_id;
  3985. if (QDF_STATUS_SUCCESS ==
  3986. dp_monitor_tx_add_to_comp_queue(soc, desc, ts, peer_id)) {
  3987. return;
  3988. }
  3989. if (QDF_STATUS_SUCCESS ==
  3990. dp_get_completion_indication_for_stack(soc,
  3991. desc->pdev,
  3992. txrx_peer, ts,
  3993. desc->nbuf,
  3994. time_latency)) {
  3995. dp_send_completion_to_stack(soc,
  3996. desc->pdev,
  3997. ts->peer_id,
  3998. ts->ppdu_id,
  3999. desc->nbuf);
  4000. return;
  4001. }
  4002. }
  4003. desc->flags |= DP_TX_DESC_FLAG_COMPLETED_TX;
  4004. dp_tx_comp_free_buf(soc, desc);
  4005. }
  4006. #ifdef DISABLE_DP_STATS
  4007. /**
  4008. * dp_tx_update_connectivity_stats() - update tx connectivity stats
  4009. * @soc: core txrx main context
  4010. * @tx_desc: tx desc
  4011. * @status: tx status
  4012. *
  4013. * Return: none
  4014. */
  4015. static inline
  4016. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  4017. struct dp_vdev *vdev,
  4018. struct dp_tx_desc_s *tx_desc,
  4019. uint8_t status)
  4020. {
  4021. }
  4022. #else
  4023. static inline
  4024. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  4025. struct dp_vdev *vdev,
  4026. struct dp_tx_desc_s *tx_desc,
  4027. uint8_t status)
  4028. {
  4029. void *osif_dev;
  4030. ol_txrx_stats_rx_fp stats_cbk;
  4031. uint8_t pkt_type;
  4032. qdf_assert(tx_desc);
  4033. if (!vdev ||
  4034. !vdev->osif_vdev ||
  4035. !vdev->stats_cb)
  4036. return;
  4037. osif_dev = vdev->osif_vdev;
  4038. stats_cbk = vdev->stats_cb;
  4039. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_HOST_FW_SENT, &pkt_type);
  4040. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  4041. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_ACK_CNT,
  4042. &pkt_type);
  4043. }
  4044. #endif
  4045. #if defined(WLAN_FEATURE_TSF_UPLINK_DELAY) || defined(WLAN_CONFIG_TX_DELAY)
  4046. QDF_STATUS
  4047. dp_tx_compute_hw_delay_us(struct hal_tx_completion_status *ts,
  4048. uint32_t delta_tsf,
  4049. uint32_t *delay_us)
  4050. {
  4051. uint32_t buffer_ts;
  4052. uint32_t delay;
  4053. if (!delay_us)
  4054. return QDF_STATUS_E_INVAL;
  4055. /* Tx_rate_stats_info_valid is 0 and tsf is invalid then */
  4056. if (!ts->valid)
  4057. return QDF_STATUS_E_INVAL;
  4058. /* buffer_timestamp is in units of 1024 us and is [31:13] of
  4059. * WBM_RELEASE_RING_4. After left shift 10 bits, it's
  4060. * valid up to 29 bits.
  4061. */
  4062. buffer_ts = ts->buffer_timestamp << 10;
  4063. delay = ts->tsf - buffer_ts - delta_tsf;
  4064. delay &= 0x1FFFFFFF; /* mask 29 BITS */
  4065. if (delay > 0x1000000) {
  4066. dp_info_rl("----------------------\n"
  4067. "Tx completion status:\n"
  4068. "----------------------\n"
  4069. "release_src = %d\n"
  4070. "ppdu_id = 0x%x\n"
  4071. "release_reason = %d\n"
  4072. "tsf = %u (0x%x)\n"
  4073. "buffer_timestamp = %u (0x%x)\n"
  4074. "delta_tsf = %u (0x%x)\n",
  4075. ts->release_src, ts->ppdu_id, ts->status,
  4076. ts->tsf, ts->tsf, ts->buffer_timestamp,
  4077. ts->buffer_timestamp, delta_tsf, delta_tsf);
  4078. return QDF_STATUS_E_FAILURE;
  4079. }
  4080. *delay_us = delay;
  4081. return QDF_STATUS_SUCCESS;
  4082. }
  4083. void dp_set_delta_tsf(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4084. uint32_t delta_tsf)
  4085. {
  4086. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4087. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4088. DP_MOD_ID_CDP);
  4089. if (!vdev) {
  4090. dp_err_rl("vdev %d does not exist", vdev_id);
  4091. return;
  4092. }
  4093. vdev->delta_tsf = delta_tsf;
  4094. dp_debug("vdev id %u delta_tsf %u", vdev_id, delta_tsf);
  4095. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4096. }
  4097. #endif
  4098. #ifdef WLAN_FEATURE_TSF_UPLINK_DELAY
  4099. QDF_STATUS dp_set_tsf_ul_delay_report(struct cdp_soc_t *soc_hdl,
  4100. uint8_t vdev_id, bool enable)
  4101. {
  4102. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4103. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4104. DP_MOD_ID_CDP);
  4105. if (!vdev) {
  4106. dp_err_rl("vdev %d does not exist", vdev_id);
  4107. return QDF_STATUS_E_FAILURE;
  4108. }
  4109. qdf_atomic_set(&vdev->ul_delay_report, enable);
  4110. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4111. return QDF_STATUS_SUCCESS;
  4112. }
  4113. QDF_STATUS dp_get_uplink_delay(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4114. uint32_t *val)
  4115. {
  4116. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4117. struct dp_vdev *vdev;
  4118. uint32_t delay_accum;
  4119. uint32_t pkts_accum;
  4120. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_CDP);
  4121. if (!vdev) {
  4122. dp_err_rl("vdev %d does not exist", vdev_id);
  4123. return QDF_STATUS_E_FAILURE;
  4124. }
  4125. if (!qdf_atomic_read(&vdev->ul_delay_report)) {
  4126. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4127. return QDF_STATUS_E_FAILURE;
  4128. }
  4129. /* Average uplink delay based on current accumulated values */
  4130. delay_accum = qdf_atomic_read(&vdev->ul_delay_accum);
  4131. pkts_accum = qdf_atomic_read(&vdev->ul_pkts_accum);
  4132. *val = delay_accum / pkts_accum;
  4133. dp_debug("uplink_delay %u delay_accum %u pkts_accum %u", *val,
  4134. delay_accum, pkts_accum);
  4135. /* Reset accumulated values to 0 */
  4136. qdf_atomic_set(&vdev->ul_delay_accum, 0);
  4137. qdf_atomic_set(&vdev->ul_pkts_accum, 0);
  4138. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4139. return QDF_STATUS_SUCCESS;
  4140. }
  4141. static void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  4142. struct hal_tx_completion_status *ts)
  4143. {
  4144. uint32_t ul_delay;
  4145. if (qdf_unlikely(!vdev)) {
  4146. dp_info_rl("vdev is null or delete in progrss");
  4147. return;
  4148. }
  4149. if (!qdf_atomic_read(&vdev->ul_delay_report))
  4150. return;
  4151. if (QDF_IS_STATUS_ERROR(dp_tx_compute_hw_delay_us(ts,
  4152. vdev->delta_tsf,
  4153. &ul_delay)))
  4154. return;
  4155. ul_delay /= 1000; /* in unit of ms */
  4156. qdf_atomic_add(ul_delay, &vdev->ul_delay_accum);
  4157. qdf_atomic_inc(&vdev->ul_pkts_accum);
  4158. }
  4159. #else /* !WLAN_FEATURE_TSF_UPLINK_DELAY */
  4160. static inline
  4161. void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  4162. struct hal_tx_completion_status *ts)
  4163. {
  4164. }
  4165. #endif /* WLAN_FEATURE_TSF_UPLINK_DELAY */
  4166. /**
  4167. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  4168. * @soc: DP soc handle
  4169. * @tx_desc: software descriptor head pointer
  4170. * @ts: Tx completion status
  4171. * @txrx_peer: txrx peer handle
  4172. * @ring_id: ring number
  4173. *
  4174. * Return: none
  4175. */
  4176. void dp_tx_comp_process_tx_status(struct dp_soc *soc,
  4177. struct dp_tx_desc_s *tx_desc,
  4178. struct hal_tx_completion_status *ts,
  4179. struct dp_txrx_peer *txrx_peer,
  4180. uint8_t ring_id)
  4181. {
  4182. uint32_t length;
  4183. qdf_ether_header_t *eh;
  4184. struct dp_vdev *vdev = NULL;
  4185. qdf_nbuf_t nbuf = tx_desc->nbuf;
  4186. enum qdf_dp_tx_rx_status dp_status;
  4187. if (!nbuf) {
  4188. dp_info_rl("invalid tx descriptor. nbuf NULL");
  4189. goto out;
  4190. }
  4191. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  4192. length = qdf_nbuf_len(nbuf);
  4193. dp_status = dp_tx_hw_to_qdf(ts->status);
  4194. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  4195. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  4196. QDF_TRACE_DEFAULT_PDEV_ID,
  4197. qdf_nbuf_data_addr(nbuf),
  4198. sizeof(qdf_nbuf_data(nbuf)),
  4199. tx_desc->id, ts->status, dp_status));
  4200. dp_tx_comp_debug("-------------------- \n"
  4201. "Tx Completion Stats: \n"
  4202. "-------------------- \n"
  4203. "ack_frame_rssi = %d \n"
  4204. "first_msdu = %d \n"
  4205. "last_msdu = %d \n"
  4206. "msdu_part_of_amsdu = %d \n"
  4207. "rate_stats valid = %d \n"
  4208. "bw = %d \n"
  4209. "pkt_type = %d \n"
  4210. "stbc = %d \n"
  4211. "ldpc = %d \n"
  4212. "sgi = %d \n"
  4213. "mcs = %d \n"
  4214. "ofdma = %d \n"
  4215. "tones_in_ru = %d \n"
  4216. "tsf = %d \n"
  4217. "ppdu_id = %d \n"
  4218. "transmit_cnt = %d \n"
  4219. "tid = %d \n"
  4220. "peer_id = %d\n"
  4221. "tx_status = %d\n",
  4222. ts->ack_frame_rssi, ts->first_msdu,
  4223. ts->last_msdu, ts->msdu_part_of_amsdu,
  4224. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  4225. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  4226. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  4227. ts->transmit_cnt, ts->tid, ts->peer_id,
  4228. ts->status);
  4229. /* Update SoC level stats */
  4230. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  4231. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  4232. if (!txrx_peer) {
  4233. dp_info_rl("peer is null or deletion in progress");
  4234. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  4235. goto out;
  4236. }
  4237. vdev = txrx_peer->vdev;
  4238. dp_tx_update_connectivity_stats(soc, vdev, tx_desc, ts->status);
  4239. dp_tx_update_uplink_delay(soc, vdev, ts);
  4240. /* check tx complete notification */
  4241. if (qdf_nbuf_tx_notify_comp_get(nbuf))
  4242. dp_tx_notify_completion(soc, vdev, tx_desc,
  4243. nbuf, ts->status);
  4244. /* Update per-packet stats for mesh mode */
  4245. if (qdf_unlikely(vdev->mesh_vdev) &&
  4246. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  4247. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  4248. /* Update peer level stats */
  4249. if (qdf_unlikely(txrx_peer->bss_peer &&
  4250. vdev->opmode == wlan_op_mode_ap)) {
  4251. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  4252. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.mcast, 1,
  4253. length);
  4254. if (txrx_peer->vdev->tx_encap_type ==
  4255. htt_cmn_pkt_type_ethernet &&
  4256. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  4257. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  4258. tx.bcast, 1,
  4259. length);
  4260. }
  4261. }
  4262. } else {
  4263. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.ucast, 1, length);
  4264. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED) {
  4265. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.tx_success,
  4266. 1, length);
  4267. if (qdf_unlikely(txrx_peer->in_twt)) {
  4268. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  4269. tx.tx_success_twt,
  4270. 1, length);
  4271. }
  4272. }
  4273. }
  4274. dp_tx_update_peer_stats(tx_desc, ts, txrx_peer, ring_id);
  4275. dp_tx_update_peer_delay_stats(txrx_peer, tx_desc, ts->tid, ring_id);
  4276. dp_tx_update_peer_sawf_stats(soc, vdev, txrx_peer, tx_desc,
  4277. ts, ts->tid);
  4278. dp_tx_send_pktlog(soc, vdev->pdev, tx_desc, nbuf, dp_status);
  4279. #ifdef QCA_SUPPORT_RDK_STATS
  4280. if (soc->peerstats_enabled)
  4281. dp_tx_sojourn_stats_process(vdev->pdev, txrx_peer, ts->tid,
  4282. qdf_ktime_to_ms(tx_desc->timestamp),
  4283. ts->ppdu_id);
  4284. #endif
  4285. out:
  4286. return;
  4287. }
  4288. #if defined(QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT) && \
  4289. defined(QCA_ENHANCED_STATS_SUPPORT)
  4290. /*
  4291. * dp_tx_update_peer_basic_stats(): Update peer basic stats
  4292. * @txrx_peer: Datapath txrx_peer handle
  4293. * @length: Length of the packet
  4294. * @tx_status: Tx status from TQM/FW
  4295. * @update: enhanced flag value present in dp_pdev
  4296. *
  4297. * Return: none
  4298. */
  4299. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4300. uint32_t length, uint8_t tx_status,
  4301. bool update)
  4302. {
  4303. if ((!txrx_peer->hw_txrx_stats_en) || update) {
  4304. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4305. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4306. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4307. }
  4308. }
  4309. #elif defined(QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT)
  4310. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4311. uint32_t length, uint8_t tx_status,
  4312. bool update)
  4313. {
  4314. if (!peer->hw_txrx_stats_en) {
  4315. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4316. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4317. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4318. }
  4319. }
  4320. #else
  4321. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4322. uint32_t length, uint8_t tx_status,
  4323. bool update)
  4324. {
  4325. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4326. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4327. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4328. }
  4329. #endif
  4330. /*
  4331. * dp_tx_prefetch_next_nbuf_data(): Prefetch nbuf and nbuf data
  4332. * @nbuf: skb buffer
  4333. *
  4334. * Return: none
  4335. */
  4336. #ifdef QCA_DP_RX_NBUF_AND_NBUF_DATA_PREFETCH
  4337. static inline
  4338. void dp_tx_prefetch_next_nbuf_data(struct dp_tx_desc_s *next)
  4339. {
  4340. qdf_nbuf_t nbuf = NULL;
  4341. if (next)
  4342. nbuf = next->nbuf;
  4343. if (nbuf) {
  4344. /* prefetch skb->next and first few bytes of skb->cb */
  4345. qdf_prefetch(next->shinfo_addr);
  4346. qdf_prefetch(nbuf);
  4347. /* prefetch skb fields present in different cachelines */
  4348. qdf_prefetch(&nbuf->len);
  4349. qdf_prefetch(&nbuf->users);
  4350. }
  4351. }
  4352. #else
  4353. static inline
  4354. void dp_tx_prefetch_next_nbuf_data(struct dp_tx_desc_s *next)
  4355. {
  4356. }
  4357. #endif
  4358. /**
  4359. * dp_tx_mcast_reinject_handler() - Tx reinjected multicast packets handler
  4360. * @soc: core txrx main context
  4361. * @desc: software descriptor
  4362. *
  4363. * Return: true when packet is reinjected
  4364. */
  4365. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  4366. defined(WLAN_MCAST_MLO)
  4367. static inline bool
  4368. dp_tx_mcast_reinject_handler(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  4369. {
  4370. struct dp_vdev *vdev = NULL;
  4371. if (desc->tx_status == HAL_TX_TQM_RR_MULTICAST_DROP) {
  4372. if (!soc->arch_ops.dp_tx_mcast_handler)
  4373. return false;
  4374. vdev = dp_vdev_get_ref_by_id(soc, desc->vdev_id,
  4375. DP_MOD_ID_REINJECT);
  4376. if (qdf_unlikely(!vdev)) {
  4377. dp_tx_comp_info_rl("Unable to get vdev ref %d",
  4378. desc->id);
  4379. return false;
  4380. }
  4381. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  4382. qdf_nbuf_len(desc->nbuf));
  4383. soc->arch_ops.dp_tx_mcast_handler(soc, vdev, desc->nbuf);
  4384. dp_tx_desc_release(desc, desc->pool_id);
  4385. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_REINJECT);
  4386. return true;
  4387. }
  4388. return false;
  4389. }
  4390. #else
  4391. static inline bool
  4392. dp_tx_mcast_reinject_handler(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  4393. {
  4394. return false;
  4395. }
  4396. #endif
  4397. /**
  4398. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  4399. * @soc: core txrx main context
  4400. * @comp_head: software descriptor head pointer
  4401. * @ring_id: ring number
  4402. *
  4403. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  4404. * and release the software descriptors after processing is complete
  4405. *
  4406. * Return: none
  4407. */
  4408. static void
  4409. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  4410. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  4411. {
  4412. struct dp_tx_desc_s *desc;
  4413. struct dp_tx_desc_s *next;
  4414. struct hal_tx_completion_status ts;
  4415. struct dp_txrx_peer *txrx_peer = NULL;
  4416. uint16_t peer_id = DP_INVALID_PEER;
  4417. dp_txrx_ref_handle txrx_ref_handle = NULL;
  4418. desc = comp_head;
  4419. while (desc) {
  4420. next = desc->next;
  4421. dp_tx_prefetch_next_nbuf_data(next);
  4422. if (peer_id != desc->peer_id) {
  4423. if (txrx_peer)
  4424. dp_txrx_peer_unref_delete(txrx_ref_handle,
  4425. DP_MOD_ID_TX_COMP);
  4426. peer_id = desc->peer_id;
  4427. txrx_peer =
  4428. dp_txrx_peer_get_ref_by_id(soc, peer_id,
  4429. &txrx_ref_handle,
  4430. DP_MOD_ID_TX_COMP);
  4431. }
  4432. if (dp_tx_mcast_reinject_handler(soc, desc)) {
  4433. desc = next;
  4434. continue;
  4435. }
  4436. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  4437. struct dp_pdev *pdev = desc->pdev;
  4438. if (qdf_likely(txrx_peer))
  4439. dp_tx_update_peer_basic_stats(txrx_peer,
  4440. desc->length,
  4441. desc->tx_status,
  4442. false);
  4443. qdf_assert(pdev);
  4444. dp_tx_outstanding_dec(pdev);
  4445. /*
  4446. * Calling a QDF WRAPPER here is creating signifcant
  4447. * performance impact so avoided the wrapper call here
  4448. */
  4449. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  4450. desc->id, DP_TX_COMP_UNMAP);
  4451. dp_tx_nbuf_unmap(soc, desc);
  4452. qdf_nbuf_free_simple(desc->nbuf);
  4453. dp_tx_desc_free(soc, desc, desc->pool_id);
  4454. desc = next;
  4455. continue;
  4456. }
  4457. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  4458. dp_tx_comp_process_tx_status(soc, desc, &ts, txrx_peer,
  4459. ring_id);
  4460. dp_tx_comp_process_desc(soc, desc, &ts, txrx_peer);
  4461. dp_tx_desc_release(desc, desc->pool_id);
  4462. desc = next;
  4463. }
  4464. if (txrx_peer)
  4465. dp_txrx_peer_unref_delete(txrx_ref_handle, DP_MOD_ID_TX_COMP);
  4466. }
  4467. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  4468. static inline
  4469. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  4470. int max_reap_limit)
  4471. {
  4472. bool limit_hit = false;
  4473. limit_hit =
  4474. (num_reaped >= max_reap_limit) ? true : false;
  4475. if (limit_hit)
  4476. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  4477. return limit_hit;
  4478. }
  4479. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  4480. {
  4481. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  4482. }
  4483. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  4484. {
  4485. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  4486. return cfg->tx_comp_loop_pkt_limit;
  4487. }
  4488. #else
  4489. static inline
  4490. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  4491. int max_reap_limit)
  4492. {
  4493. return false;
  4494. }
  4495. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  4496. {
  4497. return false;
  4498. }
  4499. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  4500. {
  4501. return 0;
  4502. }
  4503. #endif
  4504. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  4505. static inline int
  4506. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  4507. int *max_reap_limit)
  4508. {
  4509. return soc->arch_ops.dp_srng_test_and_update_nf_params(soc, dp_srng,
  4510. max_reap_limit);
  4511. }
  4512. #else
  4513. static inline int
  4514. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  4515. int *max_reap_limit)
  4516. {
  4517. return 0;
  4518. }
  4519. #endif
  4520. #ifdef DP_TX_TRACKING
  4521. void dp_tx_desc_check_corruption(struct dp_tx_desc_s *tx_desc)
  4522. {
  4523. if ((tx_desc->magic != DP_TX_MAGIC_PATTERN_INUSE) &&
  4524. (tx_desc->magic != DP_TX_MAGIC_PATTERN_FREE)) {
  4525. dp_err_rl("tx_desc %u is corrupted", tx_desc->id);
  4526. qdf_trigger_self_recovery(NULL, QDF_TX_DESC_LEAK);
  4527. }
  4528. }
  4529. #endif
  4530. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  4531. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  4532. uint32_t quota)
  4533. {
  4534. void *tx_comp_hal_desc;
  4535. void *last_prefetched_hw_desc = NULL;
  4536. struct dp_tx_desc_s *last_prefetched_sw_desc = NULL;
  4537. hal_soc_handle_t hal_soc;
  4538. uint8_t buffer_src;
  4539. struct dp_tx_desc_s *tx_desc = NULL;
  4540. struct dp_tx_desc_s *head_desc = NULL;
  4541. struct dp_tx_desc_s *tail_desc = NULL;
  4542. uint32_t num_processed = 0;
  4543. uint32_t count;
  4544. uint32_t num_avail_for_reap = 0;
  4545. bool force_break = false;
  4546. struct dp_srng *tx_comp_ring = &soc->tx_comp_ring[ring_id];
  4547. int max_reap_limit, ring_near_full;
  4548. DP_HIST_INIT();
  4549. more_data:
  4550. hal_soc = soc->hal_soc;
  4551. /* Re-initialize local variables to be re-used */
  4552. head_desc = NULL;
  4553. tail_desc = NULL;
  4554. count = 0;
  4555. max_reap_limit = dp_tx_comp_get_loop_pkt_limit(soc);
  4556. ring_near_full = dp_srng_test_and_update_nf_params(soc, tx_comp_ring,
  4557. &max_reap_limit);
  4558. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  4559. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  4560. return 0;
  4561. }
  4562. num_avail_for_reap = hal_srng_dst_num_valid(hal_soc, hal_ring_hdl, 0);
  4563. if (num_avail_for_reap >= quota)
  4564. num_avail_for_reap = quota;
  4565. dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap);
  4566. last_prefetched_hw_desc = dp_srng_dst_prefetch(hal_soc, hal_ring_hdl,
  4567. num_avail_for_reap);
  4568. /* Find head descriptor from completion ring */
  4569. while (qdf_likely(num_avail_for_reap--)) {
  4570. tx_comp_hal_desc = dp_srng_dst_get_next(soc, hal_ring_hdl);
  4571. if (qdf_unlikely(!tx_comp_hal_desc))
  4572. break;
  4573. buffer_src = hal_tx_comp_get_buffer_source(hal_soc,
  4574. tx_comp_hal_desc);
  4575. /* If this buffer was not released by TQM or FW, then it is not
  4576. * Tx completion indication, assert */
  4577. if (qdf_unlikely(buffer_src !=
  4578. HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  4579. (qdf_unlikely(buffer_src !=
  4580. HAL_TX_COMP_RELEASE_SOURCE_FW))) {
  4581. uint8_t wbm_internal_error;
  4582. dp_err_rl(
  4583. "Tx comp release_src != TQM | FW but from %d",
  4584. buffer_src);
  4585. hal_dump_comp_desc(tx_comp_hal_desc);
  4586. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  4587. /* When WBM sees NULL buffer_addr_info in any of
  4588. * ingress rings it sends an error indication,
  4589. * with wbm_internal_error=1, to a specific ring.
  4590. * The WBM2SW ring used to indicate these errors is
  4591. * fixed in HW, and that ring is being used as Tx
  4592. * completion ring. These errors are not related to
  4593. * Tx completions, and should just be ignored
  4594. */
  4595. wbm_internal_error = hal_get_wbm_internal_error(
  4596. hal_soc,
  4597. tx_comp_hal_desc);
  4598. if (wbm_internal_error) {
  4599. dp_err_rl("Tx comp wbm_internal_error!!");
  4600. DP_STATS_INC(soc, tx.wbm_internal_error[WBM_INT_ERROR_ALL], 1);
  4601. if (HAL_TX_COMP_RELEASE_SOURCE_REO ==
  4602. buffer_src)
  4603. dp_handle_wbm_internal_error(
  4604. soc,
  4605. tx_comp_hal_desc,
  4606. hal_tx_comp_get_buffer_type(
  4607. tx_comp_hal_desc));
  4608. } else {
  4609. dp_err_rl("Tx comp wbm_internal_error false");
  4610. DP_STATS_INC(soc, tx.non_wbm_internal_err, 1);
  4611. }
  4612. continue;
  4613. }
  4614. soc->arch_ops.tx_comp_get_params_from_hal_desc(soc,
  4615. tx_comp_hal_desc,
  4616. &tx_desc);
  4617. if (!tx_desc) {
  4618. dp_err("unable to retrieve tx_desc!");
  4619. QDF_BUG(0);
  4620. continue;
  4621. }
  4622. tx_desc->buffer_src = buffer_src;
  4623. /*
  4624. * If the release source is FW, process the HTT status
  4625. */
  4626. if (qdf_unlikely(buffer_src ==
  4627. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  4628. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  4629. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  4630. htt_tx_status);
  4631. /* Collect hw completion contents */
  4632. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  4633. &tx_desc->comp, 1);
  4634. soc->arch_ops.dp_tx_process_htt_completion(
  4635. soc,
  4636. tx_desc,
  4637. htt_tx_status,
  4638. ring_id);
  4639. } else {
  4640. tx_desc->tx_status =
  4641. hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  4642. tx_desc->buffer_src = buffer_src;
  4643. /*
  4644. * If the fast completion mode is enabled extended
  4645. * metadata from descriptor is not copied
  4646. */
  4647. if (qdf_likely(tx_desc->flags &
  4648. DP_TX_DESC_FLAG_SIMPLE))
  4649. goto add_to_pool;
  4650. /*
  4651. * If the descriptor is already freed in vdev_detach,
  4652. * continue to next descriptor
  4653. */
  4654. if (qdf_unlikely
  4655. ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) &&
  4656. !tx_desc->flags)) {
  4657. dp_tx_comp_info_rl("Descriptor freed in vdev_detach %d",
  4658. tx_desc->id);
  4659. DP_STATS_INC(soc, tx.tx_comp_exception, 1);
  4660. dp_tx_desc_check_corruption(tx_desc);
  4661. continue;
  4662. }
  4663. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  4664. dp_tx_comp_info_rl("pdev in down state %d",
  4665. tx_desc->id);
  4666. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  4667. dp_tx_comp_free_buf(soc, tx_desc);
  4668. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  4669. goto next_desc;
  4670. }
  4671. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  4672. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  4673. dp_tx_comp_alert("Txdesc invalid, flgs = %x,id = %d",
  4674. tx_desc->flags, tx_desc->id);
  4675. qdf_assert_always(0);
  4676. }
  4677. /* Collect hw completion contents */
  4678. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  4679. &tx_desc->comp, 1);
  4680. add_to_pool:
  4681. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  4682. /* First ring descriptor on the cycle */
  4683. if (!head_desc) {
  4684. head_desc = tx_desc;
  4685. tail_desc = tx_desc;
  4686. }
  4687. tail_desc->next = tx_desc;
  4688. tx_desc->next = NULL;
  4689. tail_desc = tx_desc;
  4690. }
  4691. next_desc:
  4692. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  4693. /*
  4694. * Processed packet count is more than given quota
  4695. * stop to processing
  4696. */
  4697. count++;
  4698. dp_tx_prefetch_hw_sw_nbuf_desc(soc, hal_soc,
  4699. num_avail_for_reap,
  4700. hal_ring_hdl,
  4701. &last_prefetched_hw_desc,
  4702. &last_prefetched_sw_desc);
  4703. if (dp_tx_comp_loop_pkt_limit_hit(soc, count, max_reap_limit))
  4704. break;
  4705. }
  4706. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  4707. /* Process the reaped descriptors */
  4708. if (head_desc)
  4709. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  4710. DP_STATS_INC(soc, tx.tx_comp[ring_id], count);
  4711. /*
  4712. * If we are processing in near-full condition, there are 3 scenario
  4713. * 1) Ring entries has reached critical state
  4714. * 2) Ring entries are still near high threshold
  4715. * 3) Ring entries are below the safe level
  4716. *
  4717. * One more loop will move te state to normal processing and yield
  4718. */
  4719. if (ring_near_full)
  4720. goto more_data;
  4721. if (dp_tx_comp_enable_eol_data_check(soc)) {
  4722. if (num_processed >= quota)
  4723. force_break = true;
  4724. if (!force_break &&
  4725. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  4726. hal_ring_hdl)) {
  4727. DP_STATS_INC(soc, tx.hp_oos2, 1);
  4728. if (!hif_exec_should_yield(soc->hif_handle,
  4729. int_ctx->dp_intr_id))
  4730. goto more_data;
  4731. }
  4732. }
  4733. DP_TX_HIST_STATS_PER_PDEV();
  4734. return num_processed;
  4735. }
  4736. #ifdef FEATURE_WLAN_TDLS
  4737. qdf_nbuf_t dp_tx_non_std(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4738. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  4739. {
  4740. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4741. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4742. DP_MOD_ID_TDLS);
  4743. if (!vdev) {
  4744. dp_err("vdev handle for id %d is NULL", vdev_id);
  4745. return NULL;
  4746. }
  4747. if (tx_spec & OL_TX_SPEC_NO_FREE)
  4748. vdev->is_tdls_frame = true;
  4749. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  4750. return dp_tx_send(soc_hdl, vdev_id, msdu_list);
  4751. }
  4752. #endif
  4753. /**
  4754. * dp_tx_vdev_attach() - attach vdev to dp tx
  4755. * @vdev: virtual device instance
  4756. *
  4757. * Return: QDF_STATUS_SUCCESS: success
  4758. * QDF_STATUS_E_RESOURCES: Error return
  4759. */
  4760. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  4761. {
  4762. int pdev_id;
  4763. /*
  4764. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  4765. */
  4766. DP_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  4767. DP_TCL_METADATA_TYPE_VDEV_BASED);
  4768. DP_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  4769. vdev->vdev_id);
  4770. pdev_id =
  4771. dp_get_target_pdev_id_for_host_pdev_id(vdev->pdev->soc,
  4772. vdev->pdev->pdev_id);
  4773. DP_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata, pdev_id);
  4774. /*
  4775. * Set HTT Extension Valid bit to 0 by default
  4776. */
  4777. DP_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  4778. dp_tx_vdev_update_search_flags(vdev);
  4779. return QDF_STATUS_SUCCESS;
  4780. }
  4781. #ifndef FEATURE_WDS
  4782. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  4783. {
  4784. return false;
  4785. }
  4786. #endif
  4787. /**
  4788. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  4789. * @vdev: virtual device instance
  4790. *
  4791. * Return: void
  4792. *
  4793. */
  4794. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  4795. {
  4796. struct dp_soc *soc = vdev->pdev->soc;
  4797. /*
  4798. * Enable both AddrY (SA based search) and AddrX (Da based search)
  4799. * for TDLS link
  4800. *
  4801. * Enable AddrY (SA based search) only for non-WDS STA and
  4802. * ProxySTA VAP (in HKv1) modes.
  4803. *
  4804. * In all other VAP modes, only DA based search should be
  4805. * enabled
  4806. */
  4807. if (vdev->opmode == wlan_op_mode_sta &&
  4808. vdev->tdls_link_connected)
  4809. vdev->hal_desc_addr_search_flags =
  4810. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  4811. else if ((vdev->opmode == wlan_op_mode_sta) &&
  4812. !dp_tx_da_search_override(vdev))
  4813. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  4814. else
  4815. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  4816. if (vdev->opmode == wlan_op_mode_sta && !vdev->tdls_link_connected)
  4817. vdev->search_type = soc->sta_mode_search_policy;
  4818. else
  4819. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  4820. }
  4821. static inline bool
  4822. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  4823. struct dp_vdev *vdev,
  4824. struct dp_tx_desc_s *tx_desc)
  4825. {
  4826. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  4827. return false;
  4828. /*
  4829. * if vdev is given, then only check whether desc
  4830. * vdev match. if vdev is NULL, then check whether
  4831. * desc pdev match.
  4832. */
  4833. return vdev ? (tx_desc->vdev_id == vdev->vdev_id) :
  4834. (tx_desc->pdev == pdev);
  4835. }
  4836. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4837. /**
  4838. * dp_tx_desc_flush() - release resources associated
  4839. * to TX Desc
  4840. *
  4841. * @dp_pdev: Handle to DP pdev structure
  4842. * @vdev: virtual device instance
  4843. * NULL: no specific Vdev is required and check all allcated TX desc
  4844. * on this pdev.
  4845. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  4846. *
  4847. * @force_free:
  4848. * true: flush the TX desc.
  4849. * false: only reset the Vdev in each allocated TX desc
  4850. * that associated to current Vdev.
  4851. *
  4852. * This function will go through the TX desc pool to flush
  4853. * the outstanding TX data or reset Vdev to NULL in associated TX
  4854. * Desc.
  4855. */
  4856. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  4857. bool force_free)
  4858. {
  4859. uint8_t i;
  4860. uint32_t j;
  4861. uint32_t num_desc, page_id, offset;
  4862. uint16_t num_desc_per_page;
  4863. struct dp_soc *soc = pdev->soc;
  4864. struct dp_tx_desc_s *tx_desc = NULL;
  4865. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  4866. if (!vdev && !force_free) {
  4867. dp_err("Reset TX desc vdev, Vdev param is required!");
  4868. return;
  4869. }
  4870. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  4871. tx_desc_pool = &soc->tx_desc[i];
  4872. if (!(tx_desc_pool->pool_size) ||
  4873. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  4874. !(tx_desc_pool->desc_pages.cacheable_pages))
  4875. continue;
  4876. /*
  4877. * Add flow pool lock protection in case pool is freed
  4878. * due to all tx_desc is recycled when handle TX completion.
  4879. * this is not necessary when do force flush as:
  4880. * a. double lock will happen if dp_tx_desc_release is
  4881. * also trying to acquire it.
  4882. * b. dp interrupt has been disabled before do force TX desc
  4883. * flush in dp_pdev_deinit().
  4884. */
  4885. if (!force_free)
  4886. qdf_spin_lock_bh(&tx_desc_pool->flow_pool_lock);
  4887. num_desc = tx_desc_pool->pool_size;
  4888. num_desc_per_page =
  4889. tx_desc_pool->desc_pages.num_element_per_page;
  4890. for (j = 0; j < num_desc; j++) {
  4891. page_id = j / num_desc_per_page;
  4892. offset = j % num_desc_per_page;
  4893. if (qdf_unlikely(!(tx_desc_pool->
  4894. desc_pages.cacheable_pages)))
  4895. break;
  4896. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  4897. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  4898. /*
  4899. * Free TX desc if force free is
  4900. * required, otherwise only reset vdev
  4901. * in this TX desc.
  4902. */
  4903. if (force_free) {
  4904. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  4905. dp_tx_comp_free_buf(soc, tx_desc);
  4906. dp_tx_desc_release(tx_desc, i);
  4907. } else {
  4908. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  4909. }
  4910. }
  4911. }
  4912. if (!force_free)
  4913. qdf_spin_unlock_bh(&tx_desc_pool->flow_pool_lock);
  4914. }
  4915. }
  4916. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  4917. /**
  4918. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  4919. *
  4920. * @soc: Handle to DP soc structure
  4921. * @tx_desc: pointer of one TX desc
  4922. * @desc_pool_id: TX Desc pool id
  4923. */
  4924. static inline void
  4925. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  4926. uint8_t desc_pool_id)
  4927. {
  4928. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  4929. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  4930. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  4931. }
  4932. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  4933. bool force_free)
  4934. {
  4935. uint8_t i, num_pool;
  4936. uint32_t j;
  4937. uint32_t num_desc, page_id, offset;
  4938. uint16_t num_desc_per_page;
  4939. struct dp_soc *soc = pdev->soc;
  4940. struct dp_tx_desc_s *tx_desc = NULL;
  4941. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  4942. if (!vdev && !force_free) {
  4943. dp_err("Reset TX desc vdev, Vdev param is required!");
  4944. return;
  4945. }
  4946. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4947. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4948. for (i = 0; i < num_pool; i++) {
  4949. tx_desc_pool = &soc->tx_desc[i];
  4950. if (!tx_desc_pool->desc_pages.cacheable_pages)
  4951. continue;
  4952. num_desc_per_page =
  4953. tx_desc_pool->desc_pages.num_element_per_page;
  4954. for (j = 0; j < num_desc; j++) {
  4955. page_id = j / num_desc_per_page;
  4956. offset = j % num_desc_per_page;
  4957. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  4958. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  4959. if (force_free) {
  4960. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  4961. dp_tx_comp_free_buf(soc, tx_desc);
  4962. dp_tx_desc_release(tx_desc, i);
  4963. } else {
  4964. dp_tx_desc_reset_vdev(soc, tx_desc,
  4965. i);
  4966. }
  4967. }
  4968. }
  4969. }
  4970. }
  4971. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  4972. /**
  4973. * dp_tx_vdev_detach() - detach vdev from dp tx
  4974. * @vdev: virtual device instance
  4975. *
  4976. * Return: QDF_STATUS_SUCCESS: success
  4977. * QDF_STATUS_E_RESOURCES: Error return
  4978. */
  4979. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  4980. {
  4981. struct dp_pdev *pdev = vdev->pdev;
  4982. /* Reset TX desc associated to this Vdev as NULL */
  4983. dp_tx_desc_flush(pdev, vdev, false);
  4984. return QDF_STATUS_SUCCESS;
  4985. }
  4986. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4987. /* Pools will be allocated dynamically */
  4988. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  4989. int num_desc)
  4990. {
  4991. uint8_t i;
  4992. for (i = 0; i < num_pool; i++) {
  4993. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  4994. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  4995. }
  4996. return QDF_STATUS_SUCCESS;
  4997. }
  4998. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  4999. uint32_t num_desc)
  5000. {
  5001. return QDF_STATUS_SUCCESS;
  5002. }
  5003. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  5004. {
  5005. }
  5006. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  5007. {
  5008. uint8_t i;
  5009. for (i = 0; i < num_pool; i++)
  5010. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  5011. }
  5012. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  5013. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  5014. uint32_t num_desc)
  5015. {
  5016. uint8_t i, count;
  5017. /* Allocate software Tx descriptor pools */
  5018. for (i = 0; i < num_pool; i++) {
  5019. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  5020. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  5021. FL("Tx Desc Pool alloc %d failed %pK"),
  5022. i, soc);
  5023. goto fail;
  5024. }
  5025. }
  5026. return QDF_STATUS_SUCCESS;
  5027. fail:
  5028. for (count = 0; count < i; count++)
  5029. dp_tx_desc_pool_free(soc, count);
  5030. return QDF_STATUS_E_NOMEM;
  5031. }
  5032. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  5033. uint32_t num_desc)
  5034. {
  5035. uint8_t i;
  5036. for (i = 0; i < num_pool; i++) {
  5037. if (dp_tx_desc_pool_init(soc, i, num_desc)) {
  5038. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  5039. FL("Tx Desc Pool init %d failed %pK"),
  5040. i, soc);
  5041. return QDF_STATUS_E_NOMEM;
  5042. }
  5043. }
  5044. return QDF_STATUS_SUCCESS;
  5045. }
  5046. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  5047. {
  5048. uint8_t i;
  5049. for (i = 0; i < num_pool; i++)
  5050. dp_tx_desc_pool_deinit(soc, i);
  5051. }
  5052. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  5053. {
  5054. uint8_t i;
  5055. for (i = 0; i < num_pool; i++)
  5056. dp_tx_desc_pool_free(soc, i);
  5057. }
  5058. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  5059. /**
  5060. * dp_tx_tso_cmn_desc_pool_deinit() - de-initialize TSO descriptors
  5061. * @soc: core txrx main context
  5062. * @num_pool: number of pools
  5063. *
  5064. */
  5065. void dp_tx_tso_cmn_desc_pool_deinit(struct dp_soc *soc, uint8_t num_pool)
  5066. {
  5067. dp_tx_tso_desc_pool_deinit(soc, num_pool);
  5068. dp_tx_tso_num_seg_pool_deinit(soc, num_pool);
  5069. }
  5070. /**
  5071. * dp_tx_tso_cmn_desc_pool_free() - free TSO descriptors
  5072. * @soc: core txrx main context
  5073. * @num_pool: number of pools
  5074. *
  5075. */
  5076. void dp_tx_tso_cmn_desc_pool_free(struct dp_soc *soc, uint8_t num_pool)
  5077. {
  5078. dp_tx_tso_desc_pool_free(soc, num_pool);
  5079. dp_tx_tso_num_seg_pool_free(soc, num_pool);
  5080. }
  5081. /**
  5082. * dp_soc_tx_desc_sw_pools_free() - free all TX descriptors
  5083. * @soc: core txrx main context
  5084. *
  5085. * This function frees all tx related descriptors as below
  5086. * 1. Regular TX descriptors (static pools)
  5087. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  5088. * 3. TSO descriptors
  5089. *
  5090. */
  5091. void dp_soc_tx_desc_sw_pools_free(struct dp_soc *soc)
  5092. {
  5093. uint8_t num_pool;
  5094. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5095. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  5096. dp_tx_ext_desc_pool_free(soc, num_pool);
  5097. dp_tx_delete_static_pools(soc, num_pool);
  5098. }
  5099. /**
  5100. * dp_soc_tx_desc_sw_pools_deinit() - de-initialize all TX descriptors
  5101. * @soc: core txrx main context
  5102. *
  5103. * This function de-initializes all tx related descriptors as below
  5104. * 1. Regular TX descriptors (static pools)
  5105. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  5106. * 3. TSO descriptors
  5107. *
  5108. */
  5109. void dp_soc_tx_desc_sw_pools_deinit(struct dp_soc *soc)
  5110. {
  5111. uint8_t num_pool;
  5112. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5113. dp_tx_flow_control_deinit(soc);
  5114. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  5115. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  5116. dp_tx_deinit_static_pools(soc, num_pool);
  5117. }
  5118. /**
  5119. * dp_tso_attach() - TSO attach handler
  5120. * @txrx_soc: Opaque Dp handle
  5121. *
  5122. * Reserve TSO descriptor buffers
  5123. *
  5124. * Return: QDF_STATUS_E_FAILURE on failure or
  5125. * QDF_STATUS_SUCCESS on success
  5126. */
  5127. QDF_STATUS dp_tx_tso_cmn_desc_pool_alloc(struct dp_soc *soc,
  5128. uint8_t num_pool,
  5129. uint32_t num_desc)
  5130. {
  5131. if (dp_tx_tso_desc_pool_alloc(soc, num_pool, num_desc)) {
  5132. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  5133. return QDF_STATUS_E_FAILURE;
  5134. }
  5135. if (dp_tx_tso_num_seg_pool_alloc(soc, num_pool, num_desc)) {
  5136. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  5137. num_pool, soc);
  5138. return QDF_STATUS_E_FAILURE;
  5139. }
  5140. return QDF_STATUS_SUCCESS;
  5141. }
  5142. /**
  5143. * dp_tx_tso_cmn_desc_pool_init() - TSO cmn desc pool init
  5144. * @soc: DP soc handle
  5145. * @num_pool: Number of pools
  5146. * @num_desc: Number of descriptors
  5147. *
  5148. * Initialize TSO descriptor pools
  5149. *
  5150. * Return: QDF_STATUS_E_FAILURE on failure or
  5151. * QDF_STATUS_SUCCESS on success
  5152. */
  5153. QDF_STATUS dp_tx_tso_cmn_desc_pool_init(struct dp_soc *soc,
  5154. uint8_t num_pool,
  5155. uint32_t num_desc)
  5156. {
  5157. if (dp_tx_tso_desc_pool_init(soc, num_pool, num_desc)) {
  5158. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  5159. return QDF_STATUS_E_FAILURE;
  5160. }
  5161. if (dp_tx_tso_num_seg_pool_init(soc, num_pool, num_desc)) {
  5162. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  5163. num_pool, soc);
  5164. return QDF_STATUS_E_FAILURE;
  5165. }
  5166. return QDF_STATUS_SUCCESS;
  5167. }
  5168. /**
  5169. * dp_soc_tx_desc_sw_pools_alloc() - Allocate tx descriptor pool memory
  5170. * @soc: core txrx main context
  5171. *
  5172. * This function allocates memory for following descriptor pools
  5173. * 1. regular sw tx descriptor pools (static pools)
  5174. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  5175. * 3. TSO descriptor pools
  5176. *
  5177. * Return: QDF_STATUS_SUCCESS: success
  5178. * QDF_STATUS_E_RESOURCES: Error return
  5179. */
  5180. QDF_STATUS dp_soc_tx_desc_sw_pools_alloc(struct dp_soc *soc)
  5181. {
  5182. uint8_t num_pool;
  5183. uint32_t num_desc;
  5184. uint32_t num_ext_desc;
  5185. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5186. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5187. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5188. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  5189. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  5190. __func__, num_pool, num_desc);
  5191. if ((num_pool > MAX_TXDESC_POOLS) ||
  5192. (num_desc > WLAN_CFG_NUM_TX_DESC_MAX))
  5193. goto fail1;
  5194. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  5195. goto fail1;
  5196. if (dp_tx_ext_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5197. goto fail2;
  5198. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  5199. return QDF_STATUS_SUCCESS;
  5200. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5201. goto fail3;
  5202. return QDF_STATUS_SUCCESS;
  5203. fail3:
  5204. dp_tx_ext_desc_pool_free(soc, num_pool);
  5205. fail2:
  5206. dp_tx_delete_static_pools(soc, num_pool);
  5207. fail1:
  5208. return QDF_STATUS_E_RESOURCES;
  5209. }
  5210. /**
  5211. * dp_soc_tx_desc_sw_pools_init() - Initialise TX descriptor pools
  5212. * @soc: core txrx main context
  5213. *
  5214. * This function initializes the following TX descriptor pools
  5215. * 1. regular sw tx descriptor pools (static pools)
  5216. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  5217. * 3. TSO descriptor pools
  5218. *
  5219. * Return: QDF_STATUS_SUCCESS: success
  5220. * QDF_STATUS_E_RESOURCES: Error return
  5221. */
  5222. QDF_STATUS dp_soc_tx_desc_sw_pools_init(struct dp_soc *soc)
  5223. {
  5224. uint8_t num_pool;
  5225. uint32_t num_desc;
  5226. uint32_t num_ext_desc;
  5227. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5228. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5229. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5230. if (dp_tx_init_static_pools(soc, num_pool, num_desc))
  5231. goto fail1;
  5232. if (dp_tx_ext_desc_pool_init(soc, num_pool, num_ext_desc))
  5233. goto fail2;
  5234. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  5235. return QDF_STATUS_SUCCESS;
  5236. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  5237. goto fail3;
  5238. dp_tx_flow_control_init(soc);
  5239. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  5240. return QDF_STATUS_SUCCESS;
  5241. fail3:
  5242. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  5243. fail2:
  5244. dp_tx_deinit_static_pools(soc, num_pool);
  5245. fail1:
  5246. return QDF_STATUS_E_RESOURCES;
  5247. }
  5248. /**
  5249. * dp_tso_soc_attach() - Allocate and initialize TSO descriptors
  5250. * @txrx_soc: dp soc handle
  5251. *
  5252. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  5253. * QDF_STATUS_E_FAILURE
  5254. */
  5255. QDF_STATUS dp_tso_soc_attach(struct cdp_soc_t *txrx_soc)
  5256. {
  5257. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  5258. uint8_t num_pool;
  5259. uint32_t num_desc;
  5260. uint32_t num_ext_desc;
  5261. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5262. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5263. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5264. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5265. return QDF_STATUS_E_FAILURE;
  5266. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  5267. return QDF_STATUS_E_FAILURE;
  5268. return QDF_STATUS_SUCCESS;
  5269. }
  5270. /**
  5271. * dp_tso_soc_detach() - de-initialize and free the TSO descriptors
  5272. * @txrx_soc: dp soc handle
  5273. *
  5274. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  5275. */
  5276. QDF_STATUS dp_tso_soc_detach(struct cdp_soc_t *txrx_soc)
  5277. {
  5278. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  5279. uint8_t num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5280. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  5281. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  5282. return QDF_STATUS_SUCCESS;
  5283. }
  5284. #ifdef CONFIG_DP_PKT_ADD_TIMESTAMP
  5285. void dp_pkt_add_timestamp(struct dp_vdev *vdev,
  5286. enum qdf_pkt_timestamp_index index, uint64_t time,
  5287. qdf_nbuf_t nbuf)
  5288. {
  5289. if (qdf_unlikely(qdf_is_dp_pkt_timestamp_enabled())) {
  5290. uint64_t tsf_time;
  5291. if (vdev->get_tsf_time) {
  5292. vdev->get_tsf_time(vdev->osif_vdev, time, &tsf_time);
  5293. qdf_add_dp_pkt_timestamp(nbuf, index, tsf_time);
  5294. }
  5295. }
  5296. }
  5297. void dp_pkt_get_timestamp(uint64_t *time)
  5298. {
  5299. if (qdf_unlikely(qdf_is_dp_pkt_timestamp_enabled()))
  5300. *time = qdf_get_log_timestamp();
  5301. }
  5302. #endif