dp_tx.c 97 KB

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  1. /*
  2. * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "dp_tx.h"
  20. #include "dp_tx_desc.h"
  21. #include "dp_peer.h"
  22. #include "dp_types.h"
  23. #include "hal_tx.h"
  24. #include "qdf_mem.h"
  25. #include "qdf_nbuf.h"
  26. #include "qdf_net_types.h"
  27. #include <wlan_cfg.h>
  28. #ifdef MESH_MODE_SUPPORT
  29. #include "if_meta_hdr.h"
  30. #endif
  31. #define DP_TX_QUEUE_MASK 0x3
  32. /* TODO Add support in TSO */
  33. #define DP_DESC_NUM_FRAG(x) 0
  34. /* disable TQM_BYPASS */
  35. #define TQM_BYPASS_WAR 0
  36. /* invalid peer id for reinject*/
  37. #define DP_INVALID_PEER 0XFFFE
  38. /*mapping between hal encrypt type and cdp_sec_type*/
  39. #define MAX_CDP_SEC_TYPE 12
  40. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  41. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  42. HAL_TX_ENCRYPT_TYPE_WEP_128,
  43. HAL_TX_ENCRYPT_TYPE_WEP_104,
  44. HAL_TX_ENCRYPT_TYPE_WEP_40,
  45. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  46. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  47. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  48. HAL_TX_ENCRYPT_TYPE_WAPI,
  49. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  50. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  51. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  52. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  53. /**
  54. * dp_tx_get_queue() - Returns Tx queue IDs to be used for this Tx frame
  55. * @vdev: DP Virtual device handle
  56. * @nbuf: Buffer pointer
  57. * @queue: queue ids container for nbuf
  58. *
  59. * TX packet queue has 2 instances, software descriptors id and dma ring id
  60. * Based on tx feature and hardware configuration queue id combination could be
  61. * different.
  62. * For example -
  63. * With XPS enabled,all TX descriptor pools and dma ring are assigned per cpu id
  64. * With no XPS,lock based resource protection, Descriptor pool ids are different
  65. * for each vdev, dma ring id will be same as single pdev id
  66. *
  67. * Return: None
  68. */
  69. #ifdef QCA_OL_TX_MULTIQ_SUPPORT
  70. static inline void dp_tx_get_queue(struct dp_vdev *vdev,
  71. qdf_nbuf_t nbuf, struct dp_tx_queue *queue)
  72. {
  73. uint16_t queue_offset = qdf_nbuf_get_queue_mapping(nbuf) & DP_TX_QUEUE_MASK;
  74. queue->desc_pool_id = queue_offset;
  75. queue->ring_id = vdev->pdev->soc->tx_ring_map[queue_offset];
  76. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  77. "%s, pool_id:%d ring_id: %d",
  78. __func__, queue->desc_pool_id, queue->ring_id);
  79. return;
  80. }
  81. #else /* QCA_OL_TX_MULTIQ_SUPPORT */
  82. static inline void dp_tx_get_queue(struct dp_vdev *vdev,
  83. qdf_nbuf_t nbuf, struct dp_tx_queue *queue)
  84. {
  85. /* get flow id */
  86. queue->desc_pool_id = DP_TX_GET_DESC_POOL_ID(vdev);
  87. queue->ring_id = DP_TX_GET_RING_ID(vdev);
  88. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  89. "%s, pool_id:%d ring_id: %d",
  90. __func__, queue->desc_pool_id, queue->ring_id);
  91. return;
  92. }
  93. #endif
  94. #if defined(FEATURE_TSO)
  95. /**
  96. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  97. *
  98. * @soc - core txrx main context
  99. * @tx_desc - Tx software descriptor
  100. */
  101. static void dp_tx_tso_unmap_segment(struct dp_soc *soc,
  102. struct dp_tx_desc_s *tx_desc)
  103. {
  104. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  105. if (qdf_unlikely(!tx_desc->tso_desc)) {
  106. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  107. "%s %d TSO desc is NULL!",
  108. __func__, __LINE__);
  109. qdf_assert(0);
  110. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  111. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  112. "%s %d TSO num desc is NULL!",
  113. __func__, __LINE__);
  114. qdf_assert(0);
  115. } else {
  116. bool is_last_seg;
  117. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  118. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  119. if (tso_num_desc->num_seg.tso_cmn_num_seg > 1)
  120. is_last_seg = false;
  121. else
  122. is_last_seg = true;
  123. tso_num_desc->num_seg.tso_cmn_num_seg--;
  124. qdf_nbuf_unmap_tso_segment(soc->osdev,
  125. tx_desc->tso_desc, is_last_seg);
  126. }
  127. }
  128. /**
  129. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  130. * back to the freelist
  131. *
  132. * @soc - soc device handle
  133. * @tx_desc - Tx software descriptor
  134. */
  135. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  136. struct dp_tx_desc_s *tx_desc)
  137. {
  138. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  139. if (qdf_unlikely(!tx_desc->tso_desc)) {
  140. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  141. "%s %d TSO desc is NULL!",
  142. __func__, __LINE__);
  143. qdf_assert(0);
  144. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  145. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  146. "%s %d TSO num desc is NULL!",
  147. __func__, __LINE__);
  148. qdf_assert(0);
  149. } else {
  150. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  151. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  152. /* Add the tso num segment into the free list */
  153. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  154. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  155. tx_desc->tso_num_desc);
  156. tx_desc->tso_num_desc = NULL;
  157. }
  158. /* Add the tso segment into the free list*/
  159. dp_tx_tso_desc_free(soc,
  160. tx_desc->pool_id, tx_desc->tso_desc);
  161. tx_desc->tso_desc = NULL;
  162. }
  163. }
  164. #else
  165. static void dp_tx_tso_unmap_segment(struct dp_soc *soc,
  166. struct dp_tx_desc_s *tx_desc)
  167. {
  168. }
  169. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  170. struct dp_tx_desc_s *tx_desc)
  171. {
  172. }
  173. #endif
  174. /**
  175. * dp_tx_desc_release() - Release Tx Descriptor
  176. * @tx_desc : Tx Descriptor
  177. * @desc_pool_id: Descriptor Pool ID
  178. *
  179. * Deallocate all resources attached to Tx descriptor and free the Tx
  180. * descriptor.
  181. *
  182. * Return:
  183. */
  184. static void
  185. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  186. {
  187. struct dp_pdev *pdev = tx_desc->pdev;
  188. struct dp_soc *soc;
  189. uint8_t comp_status = 0;
  190. qdf_assert(pdev);
  191. soc = pdev->soc;
  192. if (tx_desc->frm_type == dp_tx_frm_tso)
  193. dp_tx_tso_desc_release(soc, tx_desc);
  194. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  195. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  196. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  197. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  198. qdf_atomic_dec(&pdev->num_tx_outstanding);
  199. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  200. qdf_atomic_dec(&pdev->num_tx_exception);
  201. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  202. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  203. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp);
  204. else
  205. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  206. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  207. "Tx Completion Release desc %d status %d outstanding %d",
  208. tx_desc->id, comp_status,
  209. qdf_atomic_read(&pdev->num_tx_outstanding));
  210. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  211. return;
  212. }
  213. /**
  214. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  215. * @vdev: DP vdev Handle
  216. * @nbuf: skb
  217. *
  218. * Prepares and fills HTT metadata in the frame pre-header for special frames
  219. * that should be transmitted using varying transmit parameters.
  220. * There are 2 VDEV modes that currently needs this special metadata -
  221. * 1) Mesh Mode
  222. * 2) DSRC Mode
  223. *
  224. * Return: HTT metadata size
  225. *
  226. */
  227. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  228. uint32_t *meta_data)
  229. {
  230. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  231. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  232. uint8_t htt_desc_size;
  233. /* Size rounded of multiple of 8 bytes */
  234. uint8_t htt_desc_size_aligned;
  235. uint8_t *hdr = NULL;
  236. /*
  237. * Metadata - HTT MSDU Extension header
  238. */
  239. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  240. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  241. if (vdev->mesh_vdev) {
  242. /* Fill and add HTT metaheader */
  243. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  244. if (hdr == NULL) {
  245. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  246. "Error in filling HTT metadata\n");
  247. return 0;
  248. }
  249. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  250. } else if (vdev->opmode == wlan_op_mode_ocb) {
  251. /* Todo - Add support for DSRC */
  252. }
  253. return htt_desc_size_aligned;
  254. }
  255. /**
  256. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  257. * @tso_seg: TSO segment to process
  258. * @ext_desc: Pointer to MSDU extension descriptor
  259. *
  260. * Return: void
  261. */
  262. #if defined(FEATURE_TSO)
  263. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  264. void *ext_desc)
  265. {
  266. uint8_t num_frag;
  267. uint32_t tso_flags;
  268. /*
  269. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  270. * tcp_flag_mask
  271. *
  272. * Checksum enable flags are set in TCL descriptor and not in Extension
  273. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  274. */
  275. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  276. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  277. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  278. tso_seg->tso_flags.ip_len);
  279. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  280. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  281. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  282. uint32_t lo = 0;
  283. uint32_t hi = 0;
  284. qdf_dmaaddr_to_32s(
  285. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  286. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  287. tso_seg->tso_frags[num_frag].length);
  288. }
  289. return;
  290. }
  291. #else
  292. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  293. void *ext_desc)
  294. {
  295. return;
  296. }
  297. #endif
  298. #if defined(FEATURE_TSO)
  299. /**
  300. * dp_tx_free_tso_seg() - Loop through the tso segments
  301. * allocated and free them
  302. *
  303. * @soc: soc handle
  304. * @free_seg: list of tso segments
  305. * @msdu_info: msdu descriptor
  306. *
  307. * Return - void
  308. */
  309. static void dp_tx_free_tso_seg(struct dp_soc *soc,
  310. struct qdf_tso_seg_elem_t *free_seg,
  311. struct dp_tx_msdu_info_s *msdu_info)
  312. {
  313. struct qdf_tso_seg_elem_t *next_seg;
  314. while (free_seg) {
  315. next_seg = free_seg->next;
  316. dp_tx_tso_desc_free(soc,
  317. msdu_info->tx_queue.desc_pool_id,
  318. free_seg);
  319. free_seg = next_seg;
  320. }
  321. }
  322. /**
  323. * dp_tx_free_tso_num_seg() - Loop through the tso num segments
  324. * allocated and free them
  325. *
  326. * @soc: soc handle
  327. * @free_seg: list of tso segments
  328. * @msdu_info: msdu descriptor
  329. * Return - void
  330. */
  331. static void dp_tx_free_tso_num_seg(struct dp_soc *soc,
  332. struct qdf_tso_num_seg_elem_t *free_seg,
  333. struct dp_tx_msdu_info_s *msdu_info)
  334. {
  335. struct qdf_tso_num_seg_elem_t *next_seg;
  336. while (free_seg) {
  337. next_seg = free_seg->next;
  338. dp_tso_num_seg_free(soc,
  339. msdu_info->tx_queue.desc_pool_id,
  340. free_seg);
  341. free_seg = next_seg;
  342. }
  343. }
  344. /**
  345. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  346. * @vdev: virtual device handle
  347. * @msdu: network buffer
  348. * @msdu_info: meta data associated with the msdu
  349. *
  350. * Return: QDF_STATUS_SUCCESS success
  351. */
  352. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  353. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  354. {
  355. struct qdf_tso_seg_elem_t *tso_seg;
  356. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  357. struct dp_soc *soc = vdev->pdev->soc;
  358. struct qdf_tso_info_t *tso_info;
  359. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  360. tso_info = &msdu_info->u.tso_info;
  361. tso_info->curr_seg = NULL;
  362. tso_info->tso_seg_list = NULL;
  363. tso_info->num_segs = num_seg;
  364. msdu_info->frm_type = dp_tx_frm_tso;
  365. tso_info->tso_num_seg_list = NULL;
  366. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  367. while (num_seg) {
  368. tso_seg = dp_tx_tso_desc_alloc(
  369. soc, msdu_info->tx_queue.desc_pool_id);
  370. if (tso_seg) {
  371. tso_seg->next = tso_info->tso_seg_list;
  372. tso_info->tso_seg_list = tso_seg;
  373. num_seg--;
  374. } else {
  375. struct qdf_tso_seg_elem_t *free_seg =
  376. tso_info->tso_seg_list;
  377. dp_tx_free_tso_seg(soc, free_seg, msdu_info);
  378. return QDF_STATUS_E_NOMEM;
  379. }
  380. }
  381. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  382. tso_num_seg = dp_tso_num_seg_alloc(soc,
  383. msdu_info->tx_queue.desc_pool_id);
  384. if (tso_num_seg) {
  385. tso_num_seg->next = tso_info->tso_num_seg_list;
  386. tso_info->tso_num_seg_list = tso_num_seg;
  387. } else {
  388. /* Bug: free tso_num_seg and tso_seg */
  389. /* Free the already allocated num of segments */
  390. struct qdf_tso_seg_elem_t *free_seg =
  391. tso_info->tso_seg_list;
  392. TSO_DEBUG(" %s: Failed alloc - Number of segs for a TSO packet",
  393. __func__);
  394. dp_tx_free_tso_seg(soc, free_seg, msdu_info);
  395. return QDF_STATUS_E_NOMEM;
  396. }
  397. msdu_info->num_seg =
  398. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  399. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  400. msdu_info->num_seg);
  401. if (!(msdu_info->num_seg)) {
  402. dp_tx_free_tso_seg(soc, tso_info->tso_seg_list, msdu_info);
  403. dp_tx_free_tso_num_seg(soc, tso_info->tso_num_seg_list,
  404. msdu_info);
  405. return QDF_STATUS_E_INVAL;
  406. }
  407. tso_info->curr_seg = tso_info->tso_seg_list;
  408. return QDF_STATUS_SUCCESS;
  409. }
  410. #else
  411. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  412. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  413. {
  414. return QDF_STATUS_E_NOMEM;
  415. }
  416. #endif
  417. /**
  418. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  419. * @vdev: DP Vdev handle
  420. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  421. * @desc_pool_id: Descriptor Pool ID
  422. *
  423. * Return:
  424. */
  425. static
  426. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  427. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  428. {
  429. uint8_t i;
  430. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  431. struct dp_tx_seg_info_s *seg_info;
  432. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  433. struct dp_soc *soc = vdev->pdev->soc;
  434. /* Allocate an extension descriptor */
  435. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  436. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  437. if (!msdu_ext_desc) {
  438. DP_STATS_INC(vdev, tx_i.dropped.desc_na, 1);
  439. return NULL;
  440. }
  441. if (msdu_info->exception_fw &&
  442. qdf_unlikely(vdev->mesh_vdev)) {
  443. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  444. &msdu_info->meta_data[0],
  445. sizeof(struct htt_tx_msdu_desc_ext2_t));
  446. qdf_atomic_inc(&vdev->pdev->num_tx_exception);
  447. }
  448. switch (msdu_info->frm_type) {
  449. case dp_tx_frm_sg:
  450. case dp_tx_frm_me:
  451. case dp_tx_frm_raw:
  452. seg_info = msdu_info->u.sg_info.curr_seg;
  453. /* Update the buffer pointers in MSDU Extension Descriptor */
  454. for (i = 0; i < seg_info->frag_cnt; i++) {
  455. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  456. seg_info->frags[i].paddr_lo,
  457. seg_info->frags[i].paddr_hi,
  458. seg_info->frags[i].len);
  459. }
  460. break;
  461. case dp_tx_frm_tso:
  462. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  463. &cached_ext_desc[0]);
  464. break;
  465. default:
  466. break;
  467. }
  468. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  469. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  470. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  471. msdu_ext_desc->vaddr);
  472. return msdu_ext_desc;
  473. }
  474. /**
  475. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  476. * @vdev: DP vdev handle
  477. * @nbuf: skb
  478. * @desc_pool_id: Descriptor pool ID
  479. * @meta_data: Metadata to the fw
  480. * @tx_exc_metadata: Handle that holds exception path metadata
  481. * Allocate and prepare Tx descriptor with msdu information.
  482. *
  483. * Return: Pointer to Tx Descriptor on success,
  484. * NULL on failure
  485. */
  486. static
  487. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  488. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  489. struct dp_tx_msdu_info_s *msdu_info,
  490. struct cdp_tx_exception_metadata *tx_exc_metadata)
  491. {
  492. uint8_t align_pad;
  493. uint8_t is_exception = 0;
  494. uint8_t htt_hdr_size;
  495. struct ether_header *eh;
  496. struct dp_tx_desc_s *tx_desc;
  497. struct dp_pdev *pdev = vdev->pdev;
  498. struct dp_soc *soc = pdev->soc;
  499. /* Allocate software Tx descriptor */
  500. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  501. if (qdf_unlikely(!tx_desc)) {
  502. DP_STATS_INC(vdev, tx_i.dropped.desc_na, 1);
  503. return NULL;
  504. }
  505. /* Flow control/Congestion Control counters */
  506. qdf_atomic_inc(&pdev->num_tx_outstanding);
  507. /* Initialize the SW tx descriptor */
  508. tx_desc->nbuf = nbuf;
  509. tx_desc->frm_type = dp_tx_frm_std;
  510. tx_desc->tx_encap_type = (tx_exc_metadata ?
  511. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  512. tx_desc->vdev = vdev;
  513. tx_desc->pdev = pdev;
  514. tx_desc->msdu_ext_desc = NULL;
  515. tx_desc->pkt_offset = 0;
  516. /*
  517. * For special modes (vdev_type == ocb or mesh), data frames should be
  518. * transmitted using varying transmit parameters (tx spec) which include
  519. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  520. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  521. * These frames are sent as exception packets to firmware.
  522. *
  523. * HW requirement is that metadata should always point to a
  524. * 8-byte aligned address. So we add alignment pad to start of buffer.
  525. * HTT Metadata should be ensured to be multiple of 8-bytes,
  526. * to get 8-byte aligned start address along with align_pad added
  527. *
  528. * |-----------------------------|
  529. * | |
  530. * |-----------------------------| <-----Buffer Pointer Address given
  531. * | | ^ in HW descriptor (aligned)
  532. * | HTT Metadata | |
  533. * | | |
  534. * | | | Packet Offset given in descriptor
  535. * | | |
  536. * |-----------------------------| |
  537. * | Alignment Pad | v
  538. * |-----------------------------| <----- Actual buffer start address
  539. * | SKB Data | (Unaligned)
  540. * | |
  541. * | |
  542. * | |
  543. * | |
  544. * | |
  545. * |-----------------------------|
  546. */
  547. if (qdf_unlikely((msdu_info->exception_fw)) ||
  548. (vdev->opmode == wlan_op_mode_ocb)) {
  549. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  550. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  551. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  552. "qdf_nbuf_push_head failed\n");
  553. goto failure;
  554. }
  555. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  556. msdu_info->meta_data);
  557. if (htt_hdr_size == 0)
  558. goto failure;
  559. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  560. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  561. is_exception = 1;
  562. }
  563. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  564. qdf_nbuf_map(soc->osdev, nbuf,
  565. QDF_DMA_TO_DEVICE))) {
  566. /* Handle failure */
  567. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  568. "qdf_nbuf_map failed\n");
  569. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  570. goto failure;
  571. }
  572. if (qdf_unlikely(vdev->nawds_enabled)) {
  573. eh = (struct ether_header *) qdf_nbuf_data(nbuf);
  574. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  575. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  576. is_exception = 1;
  577. }
  578. }
  579. #if !TQM_BYPASS_WAR
  580. if (is_exception || tx_exc_metadata)
  581. #endif
  582. {
  583. /* Temporary WAR due to TQM VP issues */
  584. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  585. qdf_atomic_inc(&pdev->num_tx_exception);
  586. }
  587. return tx_desc;
  588. failure:
  589. dp_tx_desc_release(tx_desc, desc_pool_id);
  590. return NULL;
  591. }
  592. /**
  593. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  594. * @vdev: DP vdev handle
  595. * @nbuf: skb
  596. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  597. * @desc_pool_id : Descriptor Pool ID
  598. *
  599. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  600. * information. For frames wth fragments, allocate and prepare
  601. * an MSDU extension descriptor
  602. *
  603. * Return: Pointer to Tx Descriptor on success,
  604. * NULL on failure
  605. */
  606. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  607. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  608. uint8_t desc_pool_id)
  609. {
  610. struct dp_tx_desc_s *tx_desc;
  611. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  612. struct dp_pdev *pdev = vdev->pdev;
  613. struct dp_soc *soc = pdev->soc;
  614. /* Allocate software Tx descriptor */
  615. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  616. if (!tx_desc) {
  617. DP_STATS_INC(vdev, tx_i.dropped.desc_na, 1);
  618. return NULL;
  619. }
  620. /* Flow control/Congestion Control counters */
  621. qdf_atomic_inc(&pdev->num_tx_outstanding);
  622. /* Initialize the SW tx descriptor */
  623. tx_desc->nbuf = nbuf;
  624. tx_desc->frm_type = msdu_info->frm_type;
  625. tx_desc->tx_encap_type = vdev->tx_encap_type;
  626. tx_desc->vdev = vdev;
  627. tx_desc->pdev = pdev;
  628. tx_desc->pkt_offset = 0;
  629. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  630. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  631. /* Handle scattered frames - TSO/SG/ME */
  632. /* Allocate and prepare an extension descriptor for scattered frames */
  633. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  634. if (!msdu_ext_desc) {
  635. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  636. "%s Tx Extension Descriptor Alloc Fail\n",
  637. __func__);
  638. goto failure;
  639. }
  640. #if TQM_BYPASS_WAR
  641. /* Temporary WAR due to TQM VP issues */
  642. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  643. qdf_atomic_inc(&pdev->num_tx_exception);
  644. #endif
  645. if (qdf_unlikely(msdu_info->exception_fw))
  646. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  647. tx_desc->msdu_ext_desc = msdu_ext_desc;
  648. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  649. return tx_desc;
  650. failure:
  651. dp_tx_desc_release(tx_desc, desc_pool_id);
  652. return NULL;
  653. }
  654. /**
  655. * dp_tx_prepare_raw() - Prepare RAW packet TX
  656. * @vdev: DP vdev handle
  657. * @nbuf: buffer pointer
  658. * @seg_info: Pointer to Segment info Descriptor to be prepared
  659. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  660. * descriptor
  661. *
  662. * Return:
  663. */
  664. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  665. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  666. {
  667. qdf_nbuf_t curr_nbuf = NULL;
  668. uint16_t total_len = 0;
  669. qdf_dma_addr_t paddr;
  670. int32_t i;
  671. int32_t mapped_buf_num = 0;
  672. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  673. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  674. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  675. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  676. if (qos_wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS)
  677. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  678. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  679. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  680. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, curr_nbuf,
  681. QDF_DMA_TO_DEVICE)) {
  682. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  683. "%s dma map error \n", __func__);
  684. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  685. mapped_buf_num = i;
  686. goto error;
  687. }
  688. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  689. seg_info->frags[i].paddr_lo = paddr;
  690. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  691. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  692. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  693. total_len += qdf_nbuf_len(curr_nbuf);
  694. }
  695. seg_info->frag_cnt = i;
  696. seg_info->total_len = total_len;
  697. seg_info->next = NULL;
  698. sg_info->curr_seg = seg_info;
  699. msdu_info->frm_type = dp_tx_frm_raw;
  700. msdu_info->num_seg = 1;
  701. return nbuf;
  702. error:
  703. i = 0;
  704. while (nbuf) {
  705. curr_nbuf = nbuf;
  706. if (i < mapped_buf_num) {
  707. qdf_nbuf_unmap(vdev->osdev, curr_nbuf, QDF_DMA_TO_DEVICE);
  708. i++;
  709. }
  710. nbuf = qdf_nbuf_next(nbuf);
  711. qdf_nbuf_free(curr_nbuf);
  712. }
  713. return NULL;
  714. }
  715. /**
  716. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  717. * @soc: DP Soc Handle
  718. * @vdev: DP vdev handle
  719. * @tx_desc: Tx Descriptor Handle
  720. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  721. * @fw_metadata: Metadata to send to Target Firmware along with frame
  722. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  723. * @tx_exc_metadata: Handle that holds exception path meta data
  724. *
  725. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  726. * from software Tx descriptor
  727. *
  728. * Return:
  729. */
  730. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  731. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  732. uint16_t fw_metadata, uint8_t ring_id,
  733. struct cdp_tx_exception_metadata
  734. *tx_exc_metadata)
  735. {
  736. uint8_t type;
  737. uint16_t length;
  738. void *hal_tx_desc, *hal_tx_desc_cached;
  739. qdf_dma_addr_t dma_addr;
  740. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES];
  741. enum cdp_sec_type sec_type = (tx_exc_metadata ?
  742. tx_exc_metadata->sec_type : vdev->sec_type);
  743. /* Return Buffer Manager ID */
  744. uint8_t bm_id = ring_id;
  745. void *hal_srng = soc->tcl_data_ring[ring_id].hal_srng;
  746. hal_tx_desc_cached = (void *) cached_desc;
  747. qdf_mem_zero_outline(hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
  748. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  749. length = HAL_TX_EXT_DESC_WITH_META_DATA;
  750. type = HAL_TX_BUF_TYPE_EXT_DESC;
  751. dma_addr = tx_desc->msdu_ext_desc->paddr;
  752. } else {
  753. length = qdf_nbuf_len(tx_desc->nbuf) - tx_desc->pkt_offset;
  754. type = HAL_TX_BUF_TYPE_BUFFER;
  755. dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  756. }
  757. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  758. hal_tx_desc_set_buf_addr(hal_tx_desc_cached,
  759. dma_addr , bm_id, tx_desc->id, type);
  760. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id))
  761. return QDF_STATUS_E_RESOURCES;
  762. hal_tx_desc_set_buf_length(hal_tx_desc_cached, length);
  763. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  764. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  765. hal_tx_desc_set_lmac_id(hal_tx_desc_cached,
  766. HAL_TX_DESC_DEFAULT_LMAC_ID);
  767. hal_tx_desc_set_dscp_tid_table_id(hal_tx_desc_cached,
  768. vdev->dscp_tid_map_id);
  769. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  770. sec_type_map[sec_type]);
  771. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  772. "%s length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  773. __func__, length, type, (uint64_t)dma_addr,
  774. tx_desc->pkt_offset, tx_desc->id);
  775. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  776. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  777. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  778. vdev->hal_desc_addr_search_flags);
  779. /* verify checksum offload configuration*/
  780. if ((wlan_cfg_get_checksum_offload(soc->wlan_cfg_ctx)) &&
  781. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  782. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  783. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  784. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  785. }
  786. if (tid != HTT_TX_EXT_TID_INVALID)
  787. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  788. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  789. hal_tx_desc_set_mesh_en(hal_tx_desc_cached, 1);
  790. /* Sync cached descriptor with HW */
  791. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_srng);
  792. if (!hal_tx_desc) {
  793. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  794. "%s TCL ring full ring_id:%d\n", __func__, ring_id);
  795. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  796. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  797. return QDF_STATUS_E_RESOURCES;
  798. }
  799. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  800. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  801. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, length);
  802. /*
  803. * If one packet is enqueued in HW, PM usage count needs to be
  804. * incremented by one to prevent future runtime suspend. This
  805. * should be tied with the success of enqueuing. It will be
  806. * decremented after the packet has been sent.
  807. */
  808. hif_pm_runtime_get_noresume(soc->hif_handle);
  809. return QDF_STATUS_SUCCESS;
  810. }
  811. /**
  812. * dp_cce_classify() - Classify the frame based on CCE rules
  813. * @vdev: DP vdev handle
  814. * @nbuf: skb
  815. *
  816. * Classify frames based on CCE rules
  817. * Return: bool( true if classified,
  818. * else false)
  819. */
  820. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  821. {
  822. struct ether_header *eh = NULL;
  823. uint16_t ether_type;
  824. qdf_llc_t *llcHdr;
  825. qdf_nbuf_t nbuf_clone = NULL;
  826. qdf_dot3_qosframe_t *qos_wh = NULL;
  827. /* for mesh packets don't do any classification */
  828. if (qdf_unlikely(vdev->mesh_vdev))
  829. return false;
  830. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  831. eh = (struct ether_header *) qdf_nbuf_data(nbuf);
  832. ether_type = eh->ether_type;
  833. llcHdr = (qdf_llc_t *)(nbuf->data +
  834. sizeof(struct ether_header));
  835. } else {
  836. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  837. /* For encrypted packets don't do any classification */
  838. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  839. return false;
  840. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  841. if (qdf_unlikely(
  842. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  843. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  844. ether_type = *(uint16_t *)(nbuf->data
  845. + QDF_IEEE80211_4ADDR_HDR_LEN
  846. + sizeof(qdf_llc_t)
  847. - sizeof(ether_type));
  848. llcHdr = (qdf_llc_t *)(nbuf->data +
  849. QDF_IEEE80211_4ADDR_HDR_LEN);
  850. } else {
  851. ether_type = *(uint16_t *)(nbuf->data
  852. + QDF_IEEE80211_3ADDR_HDR_LEN
  853. + sizeof(qdf_llc_t)
  854. - sizeof(ether_type));
  855. llcHdr = (qdf_llc_t *)(nbuf->data +
  856. QDF_IEEE80211_3ADDR_HDR_LEN);
  857. }
  858. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  859. && (ether_type ==
  860. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  861. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  862. return true;
  863. }
  864. }
  865. return false;
  866. }
  867. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  868. ether_type = *(uint16_t *)(nbuf->data + 2*ETHER_ADDR_LEN +
  869. sizeof(*llcHdr));
  870. nbuf_clone = qdf_nbuf_clone(nbuf);
  871. if (qdf_unlikely(nbuf_clone)) {
  872. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  873. if (ether_type == htons(ETHERTYPE_8021Q)) {
  874. qdf_nbuf_pull_head(nbuf_clone,
  875. sizeof(qdf_net_vlanhdr_t));
  876. }
  877. }
  878. } else {
  879. if (ether_type == htons(ETHERTYPE_8021Q)) {
  880. nbuf_clone = qdf_nbuf_clone(nbuf);
  881. if (qdf_unlikely(nbuf_clone)) {
  882. qdf_nbuf_pull_head(nbuf_clone,
  883. sizeof(qdf_net_vlanhdr_t));
  884. }
  885. }
  886. }
  887. if (qdf_unlikely(nbuf_clone))
  888. nbuf = nbuf_clone;
  889. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  890. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  891. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  892. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  893. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  894. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  895. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  896. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  897. if (qdf_unlikely(nbuf_clone != NULL))
  898. qdf_nbuf_free(nbuf_clone);
  899. return true;
  900. }
  901. if (qdf_unlikely(nbuf_clone != NULL))
  902. qdf_nbuf_free(nbuf_clone);
  903. return false;
  904. }
  905. /**
  906. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  907. * @vdev: DP vdev handle
  908. * @nbuf: skb
  909. *
  910. * Extract the DSCP or PCP information from frame and map into TID value.
  911. * Software based TID classification is required when more than 2 DSCP-TID
  912. * mapping tables are needed.
  913. * Hardware supports 2 DSCP-TID mapping tables
  914. *
  915. * Return: void
  916. */
  917. static void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  918. struct dp_tx_msdu_info_s *msdu_info)
  919. {
  920. uint8_t tos = 0, dscp_tid_override = 0;
  921. uint8_t *hdr_ptr, *L3datap;
  922. uint8_t is_mcast = 0;
  923. struct ether_header *eh = NULL;
  924. qdf_ethervlan_header_t *evh = NULL;
  925. uint16_t ether_type;
  926. qdf_llc_t *llcHdr;
  927. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  928. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  929. if (vdev->dscp_tid_map_id <= 1)
  930. return;
  931. /* for mesh packets don't do any classification */
  932. if (qdf_unlikely(vdev->mesh_vdev))
  933. return;
  934. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  935. eh = (struct ether_header *) nbuf->data;
  936. hdr_ptr = eh->ether_dhost;
  937. L3datap = hdr_ptr + sizeof(struct ether_header);
  938. } else {
  939. qdf_dot3_qosframe_t *qos_wh =
  940. (qdf_dot3_qosframe_t *) nbuf->data;
  941. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  942. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  943. return;
  944. }
  945. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  946. ether_type = eh->ether_type;
  947. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(struct ether_header));
  948. /*
  949. * Check if packet is dot3 or eth2 type.
  950. */
  951. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  952. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN +
  953. sizeof(*llcHdr));
  954. if (ether_type == htons(ETHERTYPE_8021Q)) {
  955. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  956. sizeof(*llcHdr);
  957. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN
  958. + sizeof(*llcHdr) +
  959. sizeof(qdf_net_vlanhdr_t));
  960. } else {
  961. L3datap = hdr_ptr + sizeof(struct ether_header) +
  962. sizeof(*llcHdr);
  963. }
  964. } else {
  965. if (ether_type == htons(ETHERTYPE_8021Q)) {
  966. evh = (qdf_ethervlan_header_t *) eh;
  967. ether_type = evh->ether_type;
  968. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  969. }
  970. }
  971. /*
  972. * Find priority from IP TOS DSCP field
  973. */
  974. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  975. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  976. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  977. /* Only for unicast frames */
  978. if (!is_mcast) {
  979. /* send it on VO queue */
  980. msdu_info->tid = DP_VO_TID;
  981. }
  982. } else {
  983. /*
  984. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  985. * from TOS byte.
  986. */
  987. tos = ip->ip_tos;
  988. dscp_tid_override = 1;
  989. }
  990. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  991. /* TODO
  992. * use flowlabel
  993. *igmpmld cases to be handled in phase 2
  994. */
  995. unsigned long ver_pri_flowlabel;
  996. unsigned long pri;
  997. ver_pri_flowlabel = *(unsigned long *) L3datap;
  998. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  999. DP_IPV6_PRIORITY_SHIFT;
  1000. tos = pri;
  1001. dscp_tid_override = 1;
  1002. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1003. msdu_info->tid = DP_VO_TID;
  1004. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1005. /* Only for unicast frames */
  1006. if (!is_mcast) {
  1007. /* send ucast arp on VO queue */
  1008. msdu_info->tid = DP_VO_TID;
  1009. }
  1010. }
  1011. /*
  1012. * Assign all MCAST packets to BE
  1013. */
  1014. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1015. if (is_mcast) {
  1016. tos = 0;
  1017. dscp_tid_override = 1;
  1018. }
  1019. }
  1020. if (dscp_tid_override == 1) {
  1021. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1022. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1023. }
  1024. return;
  1025. }
  1026. #ifdef CONVERGED_TDLS_ENABLE
  1027. /**
  1028. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1029. * @tx_desc: TX descriptor
  1030. *
  1031. * Return: None
  1032. */
  1033. static void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1034. {
  1035. if (tx_desc->vdev) {
  1036. if (tx_desc->vdev->is_tdls_frame)
  1037. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1038. tx_desc->vdev->is_tdls_frame = false;
  1039. }
  1040. }
  1041. /**
  1042. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1043. * @tx_desc: TX descriptor
  1044. * @vdev: datapath vdev handle
  1045. *
  1046. * Return: None
  1047. */
  1048. static void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1049. struct dp_vdev *vdev)
  1050. {
  1051. struct hal_tx_completion_status ts = {0};
  1052. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1053. hal_tx_comp_get_status(&tx_desc->comp, &ts);
  1054. if (vdev->tx_non_std_data_callback.func) {
  1055. qdf_nbuf_set_next(tx_desc->nbuf, NULL);
  1056. vdev->tx_non_std_data_callback.func(
  1057. vdev->tx_non_std_data_callback.ctxt,
  1058. nbuf, ts.status);
  1059. return;
  1060. }
  1061. }
  1062. #endif
  1063. /**
  1064. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1065. * @vdev: DP vdev handle
  1066. * @nbuf: skb
  1067. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1068. * @meta_data: Metadata to the fw
  1069. * @tx_q: Tx queue to be used for this Tx frame
  1070. * @peer_id: peer_id of the peer in case of NAWDS frames
  1071. * @tx_exc_metadata: Handle that holds exception path metadata
  1072. *
  1073. * Return: NULL on success,
  1074. * nbuf when it fails to send
  1075. */
  1076. static qdf_nbuf_t dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1077. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1078. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1079. {
  1080. struct dp_pdev *pdev = vdev->pdev;
  1081. struct dp_soc *soc = pdev->soc;
  1082. struct dp_tx_desc_s *tx_desc;
  1083. QDF_STATUS status;
  1084. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1085. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1086. uint16_t htt_tcl_metadata = 0;
  1087. uint8_t tid = msdu_info->tid;
  1088. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1089. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1090. msdu_info, tx_exc_metadata);
  1091. if (!tx_desc) {
  1092. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1093. "%s Tx_desc prepare Fail vdev %pK queue %d\n",
  1094. __func__, vdev, tx_q->desc_pool_id);
  1095. return nbuf;
  1096. }
  1097. if (qdf_unlikely(soc->cce_disable)) {
  1098. if (dp_cce_classify(vdev, nbuf) == true) {
  1099. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1100. tid = DP_VO_TID;
  1101. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1102. }
  1103. }
  1104. dp_tx_update_tdls_flags(tx_desc);
  1105. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1106. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1107. "%s %d : HAL RING Access Failed -- %pK\n",
  1108. __func__, __LINE__, hal_srng);
  1109. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1110. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1111. goto fail_return;
  1112. }
  1113. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1114. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1115. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1116. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1117. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1118. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1119. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1120. peer_id);
  1121. } else
  1122. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1123. if (msdu_info->exception_fw) {
  1124. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1125. }
  1126. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1127. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  1128. htt_tcl_metadata, tx_q->ring_id, tx_exc_metadata);
  1129. if (status != QDF_STATUS_SUCCESS) {
  1130. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1131. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d\n",
  1132. __func__, tx_desc, tx_q->ring_id);
  1133. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1134. goto fail_return;
  1135. }
  1136. nbuf = NULL;
  1137. fail_return:
  1138. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1139. hal_srng_access_end(soc->hal_soc, hal_srng);
  1140. hif_pm_runtime_put(soc->hif_handle);
  1141. } else {
  1142. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1143. }
  1144. return nbuf;
  1145. }
  1146. /**
  1147. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1148. * @vdev: DP vdev handle
  1149. * @nbuf: skb
  1150. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1151. *
  1152. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1153. *
  1154. * Return: NULL on success,
  1155. * nbuf when it fails to send
  1156. */
  1157. #if QDF_LOCK_STATS
  1158. static noinline
  1159. #else
  1160. static
  1161. #endif
  1162. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1163. struct dp_tx_msdu_info_s *msdu_info)
  1164. {
  1165. uint8_t i;
  1166. struct dp_pdev *pdev = vdev->pdev;
  1167. struct dp_soc *soc = pdev->soc;
  1168. struct dp_tx_desc_s *tx_desc;
  1169. bool is_cce_classified = false;
  1170. QDF_STATUS status;
  1171. uint16_t htt_tcl_metadata = 0;
  1172. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1173. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1174. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1175. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1176. "%s %d : HAL RING Access Failed -- %pK\n",
  1177. __func__, __LINE__, hal_srng);
  1178. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1179. return nbuf;
  1180. }
  1181. if (qdf_unlikely(soc->cce_disable)) {
  1182. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1183. if (is_cce_classified) {
  1184. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1185. msdu_info->tid = DP_VO_TID;
  1186. }
  1187. }
  1188. if (msdu_info->frm_type == dp_tx_frm_me)
  1189. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1190. i = 0;
  1191. /* Print statement to track i and num_seg */
  1192. /*
  1193. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1194. * descriptors using information in msdu_info
  1195. */
  1196. while (i < msdu_info->num_seg) {
  1197. /*
  1198. * Setup Tx descriptor for an MSDU, and MSDU extension
  1199. * descriptor
  1200. */
  1201. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1202. tx_q->desc_pool_id);
  1203. if (!tx_desc) {
  1204. if (msdu_info->frm_type == dp_tx_frm_me) {
  1205. dp_tx_me_free_buf(pdev,
  1206. (void *)(msdu_info->u.sg_info
  1207. .curr_seg->frags[0].vaddr));
  1208. }
  1209. goto done;
  1210. }
  1211. if (msdu_info->frm_type == dp_tx_frm_me) {
  1212. tx_desc->me_buffer =
  1213. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1214. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1215. }
  1216. if (is_cce_classified)
  1217. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1218. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1219. if (msdu_info->exception_fw) {
  1220. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1221. }
  1222. /*
  1223. * Enqueue the Tx MSDU descriptor to HW for transmit
  1224. */
  1225. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  1226. htt_tcl_metadata, tx_q->ring_id, NULL);
  1227. if (status != QDF_STATUS_SUCCESS) {
  1228. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1229. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d\n",
  1230. __func__, tx_desc, tx_q->ring_id);
  1231. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  1232. dp_tx_me_free_buf(pdev, tx_desc->me_buffer);
  1233. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1234. goto done;
  1235. }
  1236. /*
  1237. * TODO
  1238. * if tso_info structure can be modified to have curr_seg
  1239. * as first element, following 2 blocks of code (for TSO and SG)
  1240. * can be combined into 1
  1241. */
  1242. /*
  1243. * For frames with multiple segments (TSO, ME), jump to next
  1244. * segment.
  1245. */
  1246. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1247. if (msdu_info->u.tso_info.curr_seg->next) {
  1248. msdu_info->u.tso_info.curr_seg =
  1249. msdu_info->u.tso_info.curr_seg->next;
  1250. /*
  1251. * If this is a jumbo nbuf, then increment the number of
  1252. * nbuf users for each additional segment of the msdu.
  1253. * This will ensure that the skb is freed only after
  1254. * receiving tx completion for all segments of an nbuf
  1255. */
  1256. qdf_nbuf_inc_users(nbuf);
  1257. /* Check with MCL if this is needed */
  1258. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1259. }
  1260. }
  1261. /*
  1262. * For Multicast-Unicast converted packets,
  1263. * each converted frame (for a client) is represented as
  1264. * 1 segment
  1265. */
  1266. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1267. (msdu_info->frm_type == dp_tx_frm_me)) {
  1268. if (msdu_info->u.sg_info.curr_seg->next) {
  1269. msdu_info->u.sg_info.curr_seg =
  1270. msdu_info->u.sg_info.curr_seg->next;
  1271. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1272. }
  1273. }
  1274. i++;
  1275. }
  1276. nbuf = NULL;
  1277. done:
  1278. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1279. hal_srng_access_end(soc->hal_soc, hal_srng);
  1280. hif_pm_runtime_put(soc->hif_handle);
  1281. } else {
  1282. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1283. }
  1284. return nbuf;
  1285. }
  1286. /**
  1287. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1288. * for SG frames
  1289. * @vdev: DP vdev handle
  1290. * @nbuf: skb
  1291. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1292. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1293. *
  1294. * Return: NULL on success,
  1295. * nbuf when it fails to send
  1296. */
  1297. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1298. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1299. {
  1300. uint32_t cur_frag, nr_frags;
  1301. qdf_dma_addr_t paddr;
  1302. struct dp_tx_sg_info_s *sg_info;
  1303. sg_info = &msdu_info->u.sg_info;
  1304. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1305. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, nbuf,
  1306. QDF_DMA_TO_DEVICE)) {
  1307. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1308. "dma map error\n");
  1309. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1310. qdf_nbuf_free(nbuf);
  1311. return NULL;
  1312. }
  1313. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1314. seg_info->frags[0].paddr_lo = paddr;
  1315. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  1316. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1317. seg_info->frags[0].vaddr = (void *) nbuf;
  1318. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1319. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1320. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1321. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1322. "frag dma map error\n");
  1323. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1324. qdf_nbuf_free(nbuf);
  1325. return NULL;
  1326. }
  1327. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1328. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1329. seg_info->frags[cur_frag + 1].paddr_hi =
  1330. ((uint64_t) paddr) >> 32;
  1331. seg_info->frags[cur_frag + 1].len =
  1332. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1333. }
  1334. seg_info->frag_cnt = (cur_frag + 1);
  1335. seg_info->total_len = qdf_nbuf_len(nbuf);
  1336. seg_info->next = NULL;
  1337. sg_info->curr_seg = seg_info;
  1338. msdu_info->frm_type = dp_tx_frm_sg;
  1339. msdu_info->num_seg = 1;
  1340. return nbuf;
  1341. }
  1342. #ifdef MESH_MODE_SUPPORT
  1343. /**
  1344. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1345. and prepare msdu_info for mesh frames.
  1346. * @vdev: DP vdev handle
  1347. * @nbuf: skb
  1348. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1349. *
  1350. * Return: NULL on failure,
  1351. * nbuf when extracted successfully
  1352. */
  1353. static
  1354. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1355. struct dp_tx_msdu_info_s *msdu_info)
  1356. {
  1357. struct meta_hdr_s *mhdr;
  1358. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1359. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1360. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1361. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  1362. msdu_info->exception_fw = 0;
  1363. goto remove_meta_hdr;
  1364. }
  1365. msdu_info->exception_fw = 1;
  1366. qdf_mem_set(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t), 0);
  1367. meta_data->host_tx_desc_pool = 1;
  1368. meta_data->update_peer_cache = 1;
  1369. meta_data->learning_frame = 1;
  1370. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1371. meta_data->power = mhdr->power;
  1372. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1373. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1374. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1375. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1376. meta_data->dyn_bw = 1;
  1377. meta_data->valid_pwr = 1;
  1378. meta_data->valid_mcs_mask = 1;
  1379. meta_data->valid_nss_mask = 1;
  1380. meta_data->valid_preamble_type = 1;
  1381. meta_data->valid_retries = 1;
  1382. meta_data->valid_bw_info = 1;
  1383. }
  1384. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1385. meta_data->encrypt_type = 0;
  1386. meta_data->valid_encrypt_type = 1;
  1387. meta_data->learning_frame = 0;
  1388. }
  1389. meta_data->valid_key_flags = 1;
  1390. meta_data->key_flags = (mhdr->keyix & 0x3);
  1391. remove_meta_hdr:
  1392. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1393. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1394. "qdf_nbuf_pull_head failed\n");
  1395. qdf_nbuf_free(nbuf);
  1396. return NULL;
  1397. }
  1398. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  1399. msdu_info->tid = HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST;
  1400. else
  1401. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1402. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1403. "%s , Meta hdr %0x %0x %0x %0x %0x %0x"
  1404. " tid %d to_fw %d\n",
  1405. __func__, msdu_info->meta_data[0],
  1406. msdu_info->meta_data[1],
  1407. msdu_info->meta_data[2],
  1408. msdu_info->meta_data[3],
  1409. msdu_info->meta_data[4],
  1410. msdu_info->meta_data[5],
  1411. msdu_info->tid, msdu_info->exception_fw);
  1412. return nbuf;
  1413. }
  1414. #else
  1415. static
  1416. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1417. struct dp_tx_msdu_info_s *msdu_info)
  1418. {
  1419. return nbuf;
  1420. }
  1421. #endif
  1422. #ifdef DP_FEATURE_NAWDS_TX
  1423. /**
  1424. * dp_tx_prepare_nawds(): Tramit NAWDS frames
  1425. * @vdev: dp_vdev handle
  1426. * @nbuf: skb
  1427. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1428. * @tx_q: Tx queue to be used for this Tx frame
  1429. * @meta_data: Meta date for mesh
  1430. * @peer_id: peer_id of the peer in case of NAWDS frames
  1431. *
  1432. * return: NULL on success nbuf on failure
  1433. */
  1434. static qdf_nbuf_t dp_tx_prepare_nawds(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1435. struct dp_tx_msdu_info_s *msdu_info)
  1436. {
  1437. struct dp_peer *peer = NULL;
  1438. struct dp_soc *soc = vdev->pdev->soc;
  1439. struct dp_ast_entry *ast_entry = NULL;
  1440. struct ether_header *eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1441. uint16_t peer_id = HTT_INVALID_PEER;
  1442. struct dp_peer *sa_peer = NULL;
  1443. qdf_nbuf_t nbuf_copy;
  1444. qdf_spin_lock_bh(&(soc->ast_lock));
  1445. ast_entry = dp_peer_ast_hash_find(soc, (uint8_t *)(eh->ether_shost));
  1446. if (ast_entry)
  1447. sa_peer = ast_entry->peer;
  1448. qdf_spin_unlock_bh(&(soc->ast_lock));
  1449. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1450. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1451. (peer->nawds_enabled)) {
  1452. if (sa_peer == peer) {
  1453. QDF_TRACE(QDF_MODULE_ID_DP,
  1454. QDF_TRACE_LEVEL_DEBUG,
  1455. " %s: broadcast multicast packet",
  1456. __func__);
  1457. DP_STATS_INC(peer, tx.nawds_mcast_drop, 1);
  1458. continue;
  1459. }
  1460. nbuf_copy = qdf_nbuf_copy(nbuf);
  1461. if (!nbuf_copy) {
  1462. QDF_TRACE(QDF_MODULE_ID_DP,
  1463. QDF_TRACE_LEVEL_ERROR,
  1464. "nbuf copy failed");
  1465. }
  1466. peer_id = peer->peer_ids[0];
  1467. nbuf_copy = dp_tx_send_msdu_single(vdev, nbuf_copy,
  1468. msdu_info, peer_id, NULL);
  1469. if (nbuf_copy != NULL) {
  1470. qdf_nbuf_free(nbuf_copy);
  1471. continue;
  1472. }
  1473. DP_STATS_INC_PKT(peer, tx.nawds_mcast,
  1474. 1, qdf_nbuf_len(nbuf));
  1475. }
  1476. }
  1477. if (peer_id == HTT_INVALID_PEER)
  1478. return nbuf;
  1479. return NULL;
  1480. }
  1481. #endif
  1482. /**
  1483. * dp_check_exc_metadata() - Checks if parameters are valid
  1484. * @tx_exc - holds all exception path parameters
  1485. *
  1486. * Returns true when all the parameters are valid else false
  1487. *
  1488. */
  1489. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  1490. {
  1491. if ((tx_exc->tid > DP_MAX_TIDS && tx_exc->tid != HTT_INVALID_TID) ||
  1492. tx_exc->tx_encap_type > htt_cmn_pkt_num_types ||
  1493. tx_exc->sec_type > cdp_num_sec_types) {
  1494. return false;
  1495. }
  1496. return true;
  1497. }
  1498. /**
  1499. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  1500. * @vap_dev: DP vdev handle
  1501. * @nbuf: skb
  1502. * @tx_exc_metadata: Handle that holds exception path meta data
  1503. *
  1504. * Entry point for Core Tx layer (DP_TX) invoked from
  1505. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  1506. *
  1507. * Return: NULL on success,
  1508. * nbuf when it fails to send
  1509. */
  1510. qdf_nbuf_t dp_tx_send_exception(void *vap_dev, qdf_nbuf_t nbuf,
  1511. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1512. {
  1513. struct ether_header *eh = NULL;
  1514. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1515. struct dp_tx_msdu_info_s msdu_info;
  1516. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1517. msdu_info.tid = tx_exc_metadata->tid;
  1518. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1519. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1520. "%s , skb %pM",
  1521. __func__, nbuf->data);
  1522. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1523. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  1524. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1525. "Invalid parameters in exception path");
  1526. goto fail;
  1527. }
  1528. /* Basic sanity checks for unsupported packets */
  1529. /* MESH mode */
  1530. if (qdf_unlikely(vdev->mesh_vdev)) {
  1531. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1532. "Mesh mode is not supported in exception path");
  1533. goto fail;
  1534. }
  1535. /* TSO or SG */
  1536. if (qdf_unlikely(qdf_nbuf_is_tso(nbuf)) ||
  1537. qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1538. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1539. "TSO and SG are not supported in exception path");
  1540. goto fail;
  1541. }
  1542. /* RAW */
  1543. if (qdf_unlikely(tx_exc_metadata->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1544. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1545. "Raw frame is not supported in exception path");
  1546. goto fail;
  1547. }
  1548. /* Mcast enhancement*/
  1549. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1550. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  1551. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1552. "Ignoring mcast_enhancement_en which is set and sending the mcast packet to the FW\n");
  1553. }
  1554. }
  1555. /*
  1556. * Get HW Queue to use for this frame.
  1557. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1558. * dedicated for data and 1 for command.
  1559. * "queue_id" maps to one hardware ring.
  1560. * With each ring, we also associate a unique Tx descriptor pool
  1561. * to minimize lock contention for these resources.
  1562. */
  1563. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1564. /* Reset the control block */
  1565. qdf_nbuf_reset_ctxt(nbuf);
  1566. /* Single linear frame */
  1567. /*
  1568. * If nbuf is a simple linear frame, use send_single function to
  1569. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1570. * SRNG. There is no need to setup a MSDU extension descriptor.
  1571. */
  1572. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  1573. tx_exc_metadata->peer_id, tx_exc_metadata);
  1574. return nbuf;
  1575. fail:
  1576. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1577. "pkt send failed");
  1578. return nbuf;
  1579. }
  1580. /**
  1581. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  1582. * @vap_dev: DP vdev handle
  1583. * @nbuf: skb
  1584. *
  1585. * Entry point for Core Tx layer (DP_TX) invoked from
  1586. * hard_start_xmit in OSIF/HDD
  1587. *
  1588. * Return: NULL on success,
  1589. * nbuf when it fails to send
  1590. */
  1591. #ifdef MESH_MODE_SUPPORT
  1592. qdf_nbuf_t dp_tx_send_mesh(void *vap_dev, qdf_nbuf_t nbuf)
  1593. {
  1594. struct meta_hdr_s *mhdr;
  1595. qdf_nbuf_t nbuf_mesh = NULL;
  1596. qdf_nbuf_t nbuf_clone = NULL;
  1597. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1598. uint8_t no_enc_frame = 0;
  1599. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  1600. if (nbuf_mesh == NULL) {
  1601. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1602. "qdf_nbuf_unshare failed\n");
  1603. return nbuf;
  1604. }
  1605. nbuf = nbuf_mesh;
  1606. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1607. if ((vdev->sec_type != cdp_sec_type_none) &&
  1608. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  1609. no_enc_frame = 1;
  1610. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  1611. !no_enc_frame) {
  1612. nbuf_clone = qdf_nbuf_clone(nbuf);
  1613. if (nbuf_clone == NULL) {
  1614. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1615. "qdf_nbuf_clone failed\n");
  1616. return nbuf;
  1617. }
  1618. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  1619. }
  1620. if (nbuf_clone) {
  1621. if (!dp_tx_send(vap_dev, nbuf_clone)) {
  1622. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1623. } else {
  1624. qdf_nbuf_free(nbuf_clone);
  1625. }
  1626. }
  1627. if (no_enc_frame)
  1628. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  1629. else
  1630. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  1631. nbuf = dp_tx_send(vap_dev, nbuf);
  1632. if ((nbuf == NULL) && no_enc_frame) {
  1633. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1634. }
  1635. return nbuf;
  1636. }
  1637. #else
  1638. qdf_nbuf_t dp_tx_send_mesh(void *vap_dev, qdf_nbuf_t nbuf)
  1639. {
  1640. return dp_tx_send(vap_dev, nbuf);
  1641. }
  1642. #endif
  1643. /**
  1644. * dp_tx_send() - Transmit a frame on a given VAP
  1645. * @vap_dev: DP vdev handle
  1646. * @nbuf: skb
  1647. *
  1648. * Entry point for Core Tx layer (DP_TX) invoked from
  1649. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  1650. * cases
  1651. *
  1652. * Return: NULL on success,
  1653. * nbuf when it fails to send
  1654. */
  1655. qdf_nbuf_t dp_tx_send(void *vap_dev, qdf_nbuf_t nbuf)
  1656. {
  1657. struct ether_header *eh = NULL;
  1658. struct dp_tx_msdu_info_s msdu_info;
  1659. struct dp_tx_seg_info_s seg_info;
  1660. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1661. uint16_t peer_id = HTT_INVALID_PEER;
  1662. qdf_nbuf_t nbuf_mesh = NULL;
  1663. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1664. qdf_mem_set(&seg_info, sizeof(seg_info), 0x0);
  1665. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1666. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1667. "%s , skb %pM",
  1668. __func__, nbuf->data);
  1669. /*
  1670. * Set Default Host TID value to invalid TID
  1671. * (TID override disabled)
  1672. */
  1673. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  1674. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1675. if (qdf_unlikely(vdev->mesh_vdev)) {
  1676. nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  1677. &msdu_info);
  1678. if (nbuf_mesh == NULL) {
  1679. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1680. "Extracting mesh metadata failed\n");
  1681. return nbuf;
  1682. }
  1683. nbuf = nbuf_mesh;
  1684. }
  1685. /*
  1686. * Get HW Queue to use for this frame.
  1687. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1688. * dedicated for data and 1 for command.
  1689. * "queue_id" maps to one hardware ring.
  1690. * With each ring, we also associate a unique Tx descriptor pool
  1691. * to minimize lock contention for these resources.
  1692. */
  1693. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1694. /*
  1695. * TCL H/W supports 2 DSCP-TID mapping tables.
  1696. * Table 1 - Default DSCP-TID mapping table
  1697. * Table 2 - 1 DSCP-TID override table
  1698. *
  1699. * If we need a different DSCP-TID mapping for this vap,
  1700. * call tid_classify to extract DSCP/ToS from frame and
  1701. * map to a TID and store in msdu_info. This is later used
  1702. * to fill in TCL Input descriptor (per-packet TID override).
  1703. */
  1704. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  1705. /* Reset the control block */
  1706. qdf_nbuf_reset_ctxt(nbuf);
  1707. /*
  1708. * Classify the frame and call corresponding
  1709. * "prepare" function which extracts the segment (TSO)
  1710. * and fragmentation information (for TSO , SG, ME, or Raw)
  1711. * into MSDU_INFO structure which is later used to fill
  1712. * SW and HW descriptors.
  1713. */
  1714. if (qdf_nbuf_is_tso(nbuf)) {
  1715. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1716. "%s TSO frame %pK\n", __func__, vdev);
  1717. DP_STATS_INC_PKT(vdev, tx_i.tso.tso_pkt, 1,
  1718. qdf_nbuf_len(nbuf));
  1719. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  1720. DP_STATS_INC(vdev, tx_i.tso.dropped_host, 1);
  1721. return nbuf;
  1722. }
  1723. goto send_multiple;
  1724. }
  1725. /* SG */
  1726. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1727. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  1728. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1729. "%s non-TSO SG frame %pK\n", __func__, vdev);
  1730. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  1731. qdf_nbuf_len(nbuf));
  1732. goto send_multiple;
  1733. }
  1734. #ifdef ATH_SUPPORT_IQUE
  1735. /* Mcast to Ucast Conversion*/
  1736. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1737. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1738. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  1739. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1740. "%s Mcast frm for ME %pK\n", __func__, vdev);
  1741. DP_STATS_INC_PKT(vdev,
  1742. tx_i.mcast_en.mcast_pkt, 1,
  1743. qdf_nbuf_len(nbuf));
  1744. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  1745. QDF_STATUS_SUCCESS) {
  1746. return NULL;
  1747. }
  1748. }
  1749. }
  1750. #endif
  1751. /* RAW */
  1752. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1753. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  1754. if (nbuf == NULL)
  1755. return NULL;
  1756. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1757. "%s Raw frame %pK\n", __func__, vdev);
  1758. goto send_multiple;
  1759. }
  1760. /* Single linear frame */
  1761. /*
  1762. * If nbuf is a simple linear frame, use send_single function to
  1763. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1764. * SRNG. There is no need to setup a MSDU extension descriptor.
  1765. */
  1766. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  1767. return nbuf;
  1768. send_multiple:
  1769. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  1770. return nbuf;
  1771. }
  1772. /**
  1773. * dp_tx_reinject_handler() - Tx Reinject Handler
  1774. * @tx_desc: software descriptor head pointer
  1775. * @status : Tx completion status from HTT descriptor
  1776. *
  1777. * This function reinjects frames back to Target.
  1778. * Todo - Host queue needs to be added
  1779. *
  1780. * Return: none
  1781. */
  1782. static
  1783. void dp_tx_reinject_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1784. {
  1785. struct dp_vdev *vdev;
  1786. struct dp_peer *peer = NULL;
  1787. uint32_t peer_id = HTT_INVALID_PEER;
  1788. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1789. qdf_nbuf_t nbuf_copy = NULL;
  1790. struct dp_tx_msdu_info_s msdu_info;
  1791. struct dp_peer *sa_peer = NULL;
  1792. struct dp_ast_entry *ast_entry = NULL;
  1793. struct dp_soc *soc = NULL;
  1794. struct ether_header *eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1795. #ifdef WDS_VENDOR_EXTENSION
  1796. int is_mcast = 0, is_ucast = 0;
  1797. int num_peers_3addr = 0;
  1798. struct ether_header *eth_hdr = (struct ether_header *)(qdf_nbuf_data(nbuf));
  1799. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  1800. #endif
  1801. vdev = tx_desc->vdev;
  1802. soc = vdev->pdev->soc;
  1803. qdf_assert(vdev);
  1804. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1805. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1806. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1807. "%s Tx reinject path\n", __func__);
  1808. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  1809. qdf_nbuf_len(tx_desc->nbuf));
  1810. qdf_spin_lock_bh(&(soc->ast_lock));
  1811. ast_entry = dp_peer_ast_hash_find(soc, (uint8_t *)(eh->ether_shost));
  1812. if (ast_entry)
  1813. sa_peer = ast_entry->peer;
  1814. qdf_spin_unlock_bh(&(soc->ast_lock));
  1815. #ifdef WDS_VENDOR_EXTENSION
  1816. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1817. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  1818. } else {
  1819. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  1820. }
  1821. is_ucast = !is_mcast;
  1822. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1823. if (peer->bss_peer)
  1824. continue;
  1825. /* Detect wds peers that use 3-addr framing for mcast.
  1826. * if there are any, the bss_peer is used to send the
  1827. * the mcast frame using 3-addr format. all wds enabled
  1828. * peers that use 4-addr framing for mcast frames will
  1829. * be duplicated and sent as 4-addr frames below.
  1830. */
  1831. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  1832. num_peers_3addr = 1;
  1833. break;
  1834. }
  1835. }
  1836. #endif
  1837. if (qdf_unlikely(vdev->mesh_vdev)) {
  1838. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  1839. } else {
  1840. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1841. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1842. #ifdef WDS_VENDOR_EXTENSION
  1843. /*
  1844. * . if 3-addr STA, then send on BSS Peer
  1845. * . if Peer WDS enabled and accept 4-addr mcast,
  1846. * send mcast on that peer only
  1847. * . if Peer WDS enabled and accept 4-addr ucast,
  1848. * send ucast on that peer only
  1849. */
  1850. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  1851. (peer->wds_enabled &&
  1852. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  1853. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  1854. #else
  1855. ((peer->bss_peer &&
  1856. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))) ||
  1857. peer->nawds_enabled)) {
  1858. #endif
  1859. peer_id = DP_INVALID_PEER;
  1860. if (peer->nawds_enabled) {
  1861. peer_id = peer->peer_ids[0];
  1862. if (sa_peer == peer) {
  1863. QDF_TRACE(
  1864. QDF_MODULE_ID_DP,
  1865. QDF_TRACE_LEVEL_DEBUG,
  1866. " %s: multicast packet",
  1867. __func__);
  1868. DP_STATS_INC(peer,
  1869. tx.nawds_mcast_drop, 1);
  1870. continue;
  1871. }
  1872. }
  1873. nbuf_copy = qdf_nbuf_copy(nbuf);
  1874. if (!nbuf_copy) {
  1875. QDF_TRACE(QDF_MODULE_ID_DP,
  1876. QDF_TRACE_LEVEL_DEBUG,
  1877. FL("nbuf copy failed"));
  1878. break;
  1879. }
  1880. nbuf_copy = dp_tx_send_msdu_single(vdev,
  1881. nbuf_copy,
  1882. &msdu_info,
  1883. peer_id,
  1884. NULL);
  1885. if (nbuf_copy) {
  1886. QDF_TRACE(QDF_MODULE_ID_DP,
  1887. QDF_TRACE_LEVEL_DEBUG,
  1888. FL("pkt send failed"));
  1889. qdf_nbuf_free(nbuf_copy);
  1890. } else {
  1891. if (peer_id != DP_INVALID_PEER)
  1892. DP_STATS_INC_PKT(peer,
  1893. tx.nawds_mcast,
  1894. 1, qdf_nbuf_len(nbuf));
  1895. }
  1896. }
  1897. }
  1898. }
  1899. if (vdev->nawds_enabled) {
  1900. peer_id = DP_INVALID_PEER;
  1901. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  1902. 1, qdf_nbuf_len(nbuf));
  1903. nbuf = dp_tx_send_msdu_single(vdev,
  1904. nbuf,
  1905. &msdu_info,
  1906. peer_id, NULL);
  1907. if (nbuf) {
  1908. QDF_TRACE(QDF_MODULE_ID_DP,
  1909. QDF_TRACE_LEVEL_DEBUG,
  1910. FL("pkt send failed"));
  1911. qdf_nbuf_free(nbuf);
  1912. }
  1913. } else
  1914. qdf_nbuf_free(nbuf);
  1915. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  1916. }
  1917. /**
  1918. * dp_tx_inspect_handler() - Tx Inspect Handler
  1919. * @tx_desc: software descriptor head pointer
  1920. * @status : Tx completion status from HTT descriptor
  1921. *
  1922. * Handles Tx frames sent back to Host for inspection
  1923. * (ProxyARP)
  1924. *
  1925. * Return: none
  1926. */
  1927. static void dp_tx_inspect_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1928. {
  1929. struct dp_soc *soc;
  1930. struct dp_pdev *pdev = tx_desc->pdev;
  1931. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1932. "%s Tx inspect path\n",
  1933. __func__);
  1934. qdf_assert(pdev);
  1935. soc = pdev->soc;
  1936. DP_STATS_INC_PKT(tx_desc->vdev, tx_i.inspect_pkts, 1,
  1937. qdf_nbuf_len(tx_desc->nbuf));
  1938. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  1939. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  1940. }
  1941. #ifdef FEATURE_PERPKT_INFO
  1942. /**
  1943. * dp_get_completion_indication_for_stack() - send completion to stack
  1944. * @soc : dp_soc handle
  1945. * @pdev: dp_pdev handle
  1946. * @peer_id: peer_id of the peer for which completion came
  1947. * @ppdu_id: ppdu_id
  1948. * @first_msdu: first msdu
  1949. * @last_msdu: last msdu
  1950. * @netbuf: Buffer pointer for free
  1951. *
  1952. * This function is used for indication whether buffer needs to be
  1953. * send to stack for free or not
  1954. */
  1955. QDF_STATUS
  1956. dp_get_completion_indication_for_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  1957. uint16_t peer_id, uint32_t ppdu_id, uint8_t first_msdu,
  1958. uint8_t last_msdu, qdf_nbuf_t netbuf)
  1959. {
  1960. struct tx_capture_hdr *ppdu_hdr;
  1961. struct dp_peer *peer = NULL;
  1962. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode))
  1963. return QDF_STATUS_E_NOSUPPORT;
  1964. peer = (peer_id == HTT_INVALID_PEER) ? NULL :
  1965. dp_peer_find_by_id(soc, peer_id);
  1966. if (!peer) {
  1967. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1968. FL("Peer Invalid"));
  1969. return QDF_STATUS_E_INVAL;
  1970. }
  1971. if (pdev->mcopy_mode) {
  1972. if ((pdev->m_copy_id.tx_ppdu_id == ppdu_id) &&
  1973. (pdev->m_copy_id.tx_peer_id == peer_id)) {
  1974. return QDF_STATUS_E_INVAL;
  1975. }
  1976. pdev->m_copy_id.tx_ppdu_id = ppdu_id;
  1977. pdev->m_copy_id.tx_peer_id = peer_id;
  1978. }
  1979. if (!qdf_nbuf_push_head(netbuf, sizeof(struct tx_capture_hdr))) {
  1980. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1981. FL("No headroom"));
  1982. return QDF_STATUS_E_NOMEM;
  1983. }
  1984. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  1985. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  1986. IEEE80211_ADDR_LEN);
  1987. ppdu_hdr->ppdu_id = ppdu_id;
  1988. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  1989. IEEE80211_ADDR_LEN);
  1990. ppdu_hdr->peer_id = peer_id;
  1991. ppdu_hdr->first_msdu = first_msdu;
  1992. ppdu_hdr->last_msdu = last_msdu;
  1993. return QDF_STATUS_SUCCESS;
  1994. }
  1995. /**
  1996. * dp_send_completion_to_stack() - send completion to stack
  1997. * @soc : dp_soc handle
  1998. * @pdev: dp_pdev handle
  1999. * @peer_id: peer_id of the peer for which completion came
  2000. * @ppdu_id: ppdu_id
  2001. * @netbuf: Buffer pointer for free
  2002. *
  2003. * This function is used to send completion to stack
  2004. * to free buffer
  2005. */
  2006. void dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2007. uint16_t peer_id, uint32_t ppdu_id,
  2008. qdf_nbuf_t netbuf)
  2009. {
  2010. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  2011. netbuf, peer_id,
  2012. WDI_NO_VAL, pdev->pdev_id);
  2013. }
  2014. #else
  2015. static QDF_STATUS
  2016. dp_get_completion_indication_for_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2017. uint16_t peer_id, uint32_t ppdu_id, uint8_t first_msdu,
  2018. uint8_t last_msdu, qdf_nbuf_t netbuf)
  2019. {
  2020. return QDF_STATUS_E_NOSUPPORT;
  2021. }
  2022. static void
  2023. dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2024. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  2025. {
  2026. }
  2027. #endif
  2028. /**
  2029. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2030. * @soc: Soc handle
  2031. * @desc: software Tx descriptor to be processed
  2032. *
  2033. * Return: none
  2034. */
  2035. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  2036. struct dp_tx_desc_s *desc)
  2037. {
  2038. struct dp_vdev *vdev = desc->vdev;
  2039. qdf_nbuf_t nbuf = desc->nbuf;
  2040. /* If it is TDLS mgmt, don't unmap or free the frame */
  2041. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  2042. return dp_non_std_tx_comp_free_buff(desc, vdev);
  2043. /* 0 : MSDU buffer, 1 : MLE */
  2044. if (desc->msdu_ext_desc) {
  2045. /* TSO free */
  2046. if (hal_tx_ext_desc_get_tso_enable(
  2047. desc->msdu_ext_desc->vaddr)) {
  2048. /* unmap eash TSO seg before free the nbuf */
  2049. dp_tx_tso_unmap_segment(soc, desc);
  2050. qdf_nbuf_free(nbuf);
  2051. return;
  2052. }
  2053. }
  2054. qdf_nbuf_unmap(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  2055. if (qdf_likely(!vdev->mesh_vdev))
  2056. qdf_nbuf_free(nbuf);
  2057. else {
  2058. if (desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  2059. qdf_nbuf_free(nbuf);
  2060. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  2061. } else
  2062. vdev->osif_tx_free_ext((nbuf));
  2063. }
  2064. }
  2065. /**
  2066. * dp_tx_mec_handler() - Tx MEC Notify Handler
  2067. * @vdev: pointer to dp dev handler
  2068. * @status : Tx completion status from HTT descriptor
  2069. *
  2070. * Handles MEC notify event sent from fw to Host
  2071. *
  2072. * Return: none
  2073. */
  2074. #ifdef FEATURE_WDS
  2075. void dp_tx_mec_handler(struct dp_vdev *vdev, uint8_t *status)
  2076. {
  2077. struct dp_soc *soc;
  2078. uint32_t flags = IEEE80211_NODE_F_WDS_HM;
  2079. struct dp_peer *peer;
  2080. uint8_t mac_addr[DP_MAC_ADDR_LEN], i;
  2081. if (!vdev->wds_enabled)
  2082. return;
  2083. soc = vdev->pdev->soc;
  2084. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2085. peer = TAILQ_FIRST(&vdev->peer_list);
  2086. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2087. if (!peer) {
  2088. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2089. FL("peer is NULL"));
  2090. return;
  2091. }
  2092. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2093. "%s Tx MEC Handler\n",
  2094. __func__);
  2095. for (i = 0; i < DP_MAC_ADDR_LEN; i++)
  2096. mac_addr[(DP_MAC_ADDR_LEN - 1) - i] =
  2097. status[(DP_MAC_ADDR_LEN - 2) + i];
  2098. if (qdf_mem_cmp(mac_addr, vdev->mac_addr.raw, DP_MAC_ADDR_LEN))
  2099. dp_peer_add_ast(soc,
  2100. peer,
  2101. mac_addr,
  2102. CDP_TXRX_AST_TYPE_MEC,
  2103. flags);
  2104. }
  2105. #endif
  2106. /**
  2107. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  2108. * @tx_desc: software descriptor head pointer
  2109. * @status : Tx completion status from HTT descriptor
  2110. *
  2111. * This function will process HTT Tx indication messages from Target
  2112. *
  2113. * Return: none
  2114. */
  2115. static
  2116. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2117. {
  2118. uint8_t tx_status;
  2119. struct dp_pdev *pdev;
  2120. struct dp_vdev *vdev;
  2121. struct dp_soc *soc;
  2122. uint32_t *htt_status_word = (uint32_t *) status;
  2123. qdf_assert(tx_desc->pdev);
  2124. pdev = tx_desc->pdev;
  2125. vdev = tx_desc->vdev;
  2126. soc = pdev->soc;
  2127. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_status_word[0]);
  2128. switch (tx_status) {
  2129. case HTT_TX_FW2WBM_TX_STATUS_OK:
  2130. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  2131. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  2132. {
  2133. dp_tx_comp_free_buf(soc, tx_desc);
  2134. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2135. break;
  2136. }
  2137. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  2138. {
  2139. dp_tx_reinject_handler(tx_desc, status);
  2140. break;
  2141. }
  2142. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  2143. {
  2144. dp_tx_inspect_handler(tx_desc, status);
  2145. break;
  2146. }
  2147. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  2148. {
  2149. dp_tx_mec_handler(vdev, status);
  2150. break;
  2151. }
  2152. default:
  2153. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2154. "%s Invalid HTT tx_status %d\n",
  2155. __func__, tx_status);
  2156. break;
  2157. }
  2158. }
  2159. #ifdef MESH_MODE_SUPPORT
  2160. /**
  2161. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2162. * in mesh meta header
  2163. * @tx_desc: software descriptor head pointer
  2164. * @ts: pointer to tx completion stats
  2165. * Return: none
  2166. */
  2167. static
  2168. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2169. struct hal_tx_completion_status *ts)
  2170. {
  2171. struct meta_hdr_s *mhdr;
  2172. qdf_nbuf_t netbuf = tx_desc->nbuf;
  2173. if (!tx_desc->msdu_ext_desc) {
  2174. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  2175. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2176. "netbuf %pK offset %d\n",
  2177. netbuf, tx_desc->pkt_offset);
  2178. return;
  2179. }
  2180. }
  2181. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2182. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2183. "netbuf %pK offset %d\n", netbuf,
  2184. sizeof(struct meta_hdr_s));
  2185. return;
  2186. }
  2187. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  2188. mhdr->rssi = ts->ack_frame_rssi;
  2189. mhdr->channel = tx_desc->pdev->operating_channel;
  2190. }
  2191. #else
  2192. static
  2193. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2194. struct hal_tx_completion_status *ts)
  2195. {
  2196. }
  2197. #endif
  2198. /**
  2199. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  2200. * @peer: Handle to DP peer
  2201. * @ts: pointer to HAL Tx completion stats
  2202. * @length: MSDU length
  2203. *
  2204. * Return: None
  2205. */
  2206. static void dp_tx_update_peer_stats(struct dp_peer *peer,
  2207. struct hal_tx_completion_status *ts, uint32_t length)
  2208. {
  2209. struct dp_pdev *pdev = peer->vdev->pdev;
  2210. struct dp_soc *soc = pdev->soc;
  2211. uint8_t mcs, pkt_type;
  2212. mcs = ts->mcs;
  2213. pkt_type = ts->pkt_type;
  2214. if (!ts->release_src == HAL_TX_COMP_RELEASE_SOURCE_TQM)
  2215. return;
  2216. if (peer->bss_peer) {
  2217. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  2218. } else {
  2219. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED) {
  2220. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  2221. }
  2222. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  2223. }
  2224. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  2225. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  2226. DP_STATS_INCC(peer, tx.dropped.fw_rem, 1,
  2227. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2228. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  2229. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  2230. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  2231. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  2232. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  2233. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  2234. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  2235. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  2236. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  2237. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  2238. if (!ts->status == HAL_TX_TQM_RR_FRAME_ACKED)
  2239. return;
  2240. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  2241. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  2242. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  2243. if (!(soc->process_tx_status))
  2244. return;
  2245. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2246. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  2247. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2248. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  2249. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2250. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2251. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2252. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2253. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2254. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2255. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2256. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2257. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2258. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2259. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2260. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2261. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2262. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2263. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2264. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2265. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  2266. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  2267. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  2268. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  2269. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  2270. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  2271. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  2272. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  2273. if (soc->cdp_soc.ol_ops->update_dp_stats) {
  2274. soc->cdp_soc.ol_ops->update_dp_stats(pdev->ctrl_pdev,
  2275. &peer->stats, ts->peer_id,
  2276. UPDATE_PEER_STATS);
  2277. }
  2278. }
  2279. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2280. /**
  2281. * dp_tx_flow_pool_lock() - take flow pool lock
  2282. * @soc: core txrx main context
  2283. * @tx_desc: tx desc
  2284. *
  2285. * Return: None
  2286. */
  2287. static inline
  2288. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  2289. struct dp_tx_desc_s *tx_desc)
  2290. {
  2291. struct dp_tx_desc_pool_s *pool;
  2292. uint8_t desc_pool_id;
  2293. desc_pool_id = tx_desc->pool_id;
  2294. pool = &soc->tx_desc[desc_pool_id];
  2295. qdf_spin_lock_bh(&pool->flow_pool_lock);
  2296. }
  2297. /**
  2298. * dp_tx_flow_pool_unlock() - release flow pool lock
  2299. * @soc: core txrx main context
  2300. * @tx_desc: tx desc
  2301. *
  2302. * Return: None
  2303. */
  2304. static inline
  2305. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  2306. struct dp_tx_desc_s *tx_desc)
  2307. {
  2308. struct dp_tx_desc_pool_s *pool;
  2309. uint8_t desc_pool_id;
  2310. desc_pool_id = tx_desc->pool_id;
  2311. pool = &soc->tx_desc[desc_pool_id];
  2312. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  2313. }
  2314. #else
  2315. static inline
  2316. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2317. {
  2318. }
  2319. static inline
  2320. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2321. {
  2322. }
  2323. #endif
  2324. /**
  2325. * dp_tx_notify_completion() - Notify tx completion for this desc
  2326. * @soc: core txrx main context
  2327. * @tx_desc: tx desc
  2328. * @netbuf: buffer
  2329. *
  2330. * Return: none
  2331. */
  2332. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  2333. struct dp_tx_desc_s *tx_desc,
  2334. qdf_nbuf_t netbuf)
  2335. {
  2336. void *osif_dev;
  2337. ol_txrx_completion_fp tx_compl_cbk = NULL;
  2338. qdf_assert(tx_desc);
  2339. dp_tx_flow_pool_lock(soc, tx_desc);
  2340. if (!tx_desc->vdev ||
  2341. !tx_desc->vdev->osif_vdev) {
  2342. dp_tx_flow_pool_unlock(soc, tx_desc);
  2343. return;
  2344. }
  2345. osif_dev = tx_desc->vdev->osif_vdev;
  2346. tx_compl_cbk = tx_desc->vdev->tx_comp;
  2347. dp_tx_flow_pool_unlock(soc, tx_desc);
  2348. if (tx_compl_cbk)
  2349. tx_compl_cbk(netbuf, osif_dev);
  2350. }
  2351. /**
  2352. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  2353. * @tx_desc: software descriptor head pointer
  2354. * @length: packet length
  2355. *
  2356. * Return: none
  2357. */
  2358. static inline void dp_tx_comp_process_tx_status(struct dp_tx_desc_s *tx_desc,
  2359. uint32_t length)
  2360. {
  2361. struct hal_tx_completion_status ts;
  2362. struct dp_soc *soc = NULL;
  2363. struct dp_vdev *vdev = tx_desc->vdev;
  2364. struct dp_peer *peer = NULL;
  2365. struct ether_header *eh =
  2366. (struct ether_header *)qdf_nbuf_data(tx_desc->nbuf);
  2367. hal_tx_comp_get_status(&tx_desc->comp, &ts);
  2368. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2369. "-------------------- \n"
  2370. "Tx Completion Stats: \n"
  2371. "-------------------- \n"
  2372. "ack_frame_rssi = %d \n"
  2373. "first_msdu = %d \n"
  2374. "last_msdu = %d \n"
  2375. "msdu_part_of_amsdu = %d \n"
  2376. "rate_stats valid = %d \n"
  2377. "bw = %d \n"
  2378. "pkt_type = %d \n"
  2379. "stbc = %d \n"
  2380. "ldpc = %d \n"
  2381. "sgi = %d \n"
  2382. "mcs = %d \n"
  2383. "ofdma = %d \n"
  2384. "tones_in_ru = %d \n"
  2385. "tsf = %d \n"
  2386. "ppdu_id = %d \n"
  2387. "transmit_cnt = %d \n"
  2388. "tid = %d \n"
  2389. "peer_id = %d \n",
  2390. ts.ack_frame_rssi, ts.first_msdu, ts.last_msdu,
  2391. ts.msdu_part_of_amsdu, ts.valid, ts.bw,
  2392. ts.pkt_type, ts.stbc, ts.ldpc, ts.sgi,
  2393. ts.mcs, ts.ofdma, ts.tones_in_ru, ts.tsf,
  2394. ts.ppdu_id, ts.transmit_cnt, ts.tid,
  2395. ts.peer_id);
  2396. if (!vdev) {
  2397. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2398. "invalid vdev");
  2399. goto out;
  2400. }
  2401. soc = vdev->pdev->soc;
  2402. /* Update SoC level stats */
  2403. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  2404. (ts.status == HAL_TX_TQM_RR_REM_CMD_REM));
  2405. /* Update per-packet stats */
  2406. if (qdf_unlikely(vdev->mesh_vdev) &&
  2407. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  2408. dp_tx_comp_fill_tx_completion_stats(tx_desc, &ts);
  2409. /* Update peer level stats */
  2410. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2411. if (!peer) {
  2412. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2413. "invalid peer");
  2414. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  2415. goto out;
  2416. }
  2417. if (qdf_likely(peer->vdev->tx_encap_type ==
  2418. htt_cmn_pkt_type_ethernet)) {
  2419. if (peer->bss_peer && IEEE80211_IS_BROADCAST(eh->ether_dhost))
  2420. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  2421. }
  2422. dp_tx_update_peer_stats(peer, &ts, length);
  2423. out:
  2424. return;
  2425. }
  2426. /**
  2427. * dp_tx_comp_process_desc() - Tx complete software descriptor handler
  2428. * @soc: core txrx main context
  2429. * @comp_head: software descriptor head pointer
  2430. *
  2431. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  2432. * and release the software descriptors after processing is complete
  2433. *
  2434. * Return: none
  2435. */
  2436. static void dp_tx_comp_process_desc(struct dp_soc *soc,
  2437. struct dp_tx_desc_s *comp_head)
  2438. {
  2439. struct dp_tx_desc_s *desc;
  2440. struct dp_tx_desc_s *next;
  2441. struct hal_tx_completion_status ts = {0};
  2442. uint32_t length;
  2443. struct dp_peer *peer;
  2444. DP_HIST_INIT();
  2445. desc = comp_head;
  2446. while (desc) {
  2447. hal_tx_comp_get_status(&desc->comp, &ts);
  2448. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2449. length = qdf_nbuf_len(desc->nbuf);
  2450. /* check tx completion notification */
  2451. if (QDF_NBUF_CB_TX_EXTRA_FRAG_FLAGS_NOTIFY_COMP(desc->nbuf))
  2452. dp_tx_notify_completion(soc, desc, desc->nbuf);
  2453. dp_tx_comp_process_tx_status(desc, length);
  2454. /*currently m_copy/tx_capture is not supported for scatter gather packets*/
  2455. if (!(desc->msdu_ext_desc) && (dp_get_completion_indication_for_stack(soc,
  2456. desc->pdev, ts.peer_id, ts.ppdu_id,
  2457. ts.first_msdu, ts.last_msdu,
  2458. desc->nbuf) == QDF_STATUS_SUCCESS)) {
  2459. qdf_nbuf_unmap(soc->osdev, desc->nbuf,
  2460. QDF_DMA_TO_DEVICE);
  2461. dp_send_completion_to_stack(soc, desc->pdev, ts.peer_id,
  2462. ts.ppdu_id, desc->nbuf);
  2463. } else {
  2464. dp_tx_comp_free_buf(soc, desc);
  2465. }
  2466. DP_HIST_PACKET_COUNT_INC(desc->pdev->pdev_id);
  2467. next = desc->next;
  2468. dp_tx_desc_release(desc, desc->pool_id);
  2469. desc = next;
  2470. }
  2471. DP_TX_HIST_STATS_PER_PDEV();
  2472. }
  2473. /**
  2474. * dp_tx_comp_handler() - Tx completion handler
  2475. * @soc: core txrx main context
  2476. * @ring_id: completion ring id
  2477. * @quota: No. of packets/descriptors that can be serviced in one loop
  2478. *
  2479. * This function will collect hardware release ring element contents and
  2480. * handle descriptor contents. Based on contents, free packet or handle error
  2481. * conditions
  2482. *
  2483. * Return: none
  2484. */
  2485. uint32_t dp_tx_comp_handler(struct dp_soc *soc, void *hal_srng, uint32_t quota)
  2486. {
  2487. void *tx_comp_hal_desc;
  2488. uint8_t buffer_src;
  2489. uint8_t pool_id;
  2490. uint32_t tx_desc_id;
  2491. struct dp_tx_desc_s *tx_desc = NULL;
  2492. struct dp_tx_desc_s *head_desc = NULL;
  2493. struct dp_tx_desc_s *tail_desc = NULL;
  2494. uint32_t num_processed;
  2495. uint32_t count;
  2496. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  2497. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2498. "%s %d : HAL RING Access Failed -- %pK\n",
  2499. __func__, __LINE__, hal_srng);
  2500. return 0;
  2501. }
  2502. num_processed = 0;
  2503. count = 0;
  2504. /* Find head descriptor from completion ring */
  2505. while (qdf_likely(tx_comp_hal_desc =
  2506. hal_srng_dst_get_next(soc->hal_soc, hal_srng))) {
  2507. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  2508. /* If this buffer was not released by TQM or FW, then it is not
  2509. * Tx completion indication, assert */
  2510. if ((buffer_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  2511. (buffer_src != HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2512. QDF_TRACE(QDF_MODULE_ID_DP,
  2513. QDF_TRACE_LEVEL_FATAL,
  2514. "Tx comp release_src != TQM | FW");
  2515. qdf_assert_always(0);
  2516. }
  2517. /* Get descriptor id */
  2518. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  2519. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  2520. DP_TX_DESC_ID_POOL_OS;
  2521. if (!dp_tx_is_desc_id_valid(soc, tx_desc_id))
  2522. continue;
  2523. /* Find Tx descriptor */
  2524. tx_desc = dp_tx_desc_find(soc, pool_id,
  2525. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  2526. DP_TX_DESC_ID_PAGE_OS,
  2527. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  2528. DP_TX_DESC_ID_OFFSET_OS);
  2529. /*
  2530. * If the release source is FW, process the HTT status
  2531. */
  2532. if (qdf_unlikely(buffer_src ==
  2533. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2534. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  2535. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  2536. htt_tx_status);
  2537. dp_tx_process_htt_completion(tx_desc,
  2538. htt_tx_status);
  2539. } else {
  2540. /* Pool id is not matching. Error */
  2541. if (tx_desc->pool_id != pool_id) {
  2542. QDF_TRACE(QDF_MODULE_ID_DP,
  2543. QDF_TRACE_LEVEL_FATAL,
  2544. "Tx Comp pool id %d not matched %d",
  2545. pool_id, tx_desc->pool_id);
  2546. qdf_assert_always(0);
  2547. }
  2548. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  2549. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  2550. QDF_TRACE(QDF_MODULE_ID_DP,
  2551. QDF_TRACE_LEVEL_FATAL,
  2552. "Txdesc invalid, flgs = %x,id = %d",
  2553. tx_desc->flags, tx_desc_id);
  2554. qdf_assert_always(0);
  2555. }
  2556. /* First ring descriptor on the cycle */
  2557. if (!head_desc) {
  2558. head_desc = tx_desc;
  2559. tail_desc = tx_desc;
  2560. }
  2561. tail_desc->next = tx_desc;
  2562. tx_desc->next = NULL;
  2563. tail_desc = tx_desc;
  2564. /* Collect hw completion contents */
  2565. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  2566. &tx_desc->comp, 1);
  2567. }
  2568. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  2569. /* Decrement PM usage count if the packet has been sent.*/
  2570. hif_pm_runtime_put(soc->hif_handle);
  2571. /*
  2572. * Processed packet count is more than given quota
  2573. * stop to processing
  2574. */
  2575. if ((num_processed >= quota))
  2576. break;
  2577. count++;
  2578. }
  2579. hal_srng_access_end(soc->hal_soc, hal_srng);
  2580. /* Process the reaped descriptors */
  2581. if (head_desc)
  2582. dp_tx_comp_process_desc(soc, head_desc);
  2583. return num_processed;
  2584. }
  2585. #ifdef CONVERGED_TDLS_ENABLE
  2586. /**
  2587. * dp_tx_non_std() - Allow the control-path SW to send data frames
  2588. *
  2589. * @data_vdev - which vdev should transmit the tx data frames
  2590. * @tx_spec - what non-standard handling to apply to the tx data frames
  2591. * @msdu_list - NULL-terminated list of tx MSDUs
  2592. *
  2593. * Return: NULL on success,
  2594. * nbuf when it fails to send
  2595. */
  2596. qdf_nbuf_t dp_tx_non_std(struct cdp_vdev *vdev_handle,
  2597. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  2598. {
  2599. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  2600. if (tx_spec & OL_TX_SPEC_NO_FREE)
  2601. vdev->is_tdls_frame = true;
  2602. return dp_tx_send(vdev_handle, msdu_list);
  2603. }
  2604. #endif
  2605. /**
  2606. * dp_tx_vdev_attach() - attach vdev to dp tx
  2607. * @vdev: virtual device instance
  2608. *
  2609. * Return: QDF_STATUS_SUCCESS: success
  2610. * QDF_STATUS_E_RESOURCES: Error return
  2611. */
  2612. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  2613. {
  2614. /*
  2615. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  2616. */
  2617. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  2618. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  2619. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  2620. vdev->vdev_id);
  2621. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata,
  2622. DP_SW2HW_MACID(vdev->pdev->pdev_id));
  2623. /*
  2624. * Set HTT Extension Valid bit to 0 by default
  2625. */
  2626. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  2627. dp_tx_vdev_update_search_flags(vdev);
  2628. return QDF_STATUS_SUCCESS;
  2629. }
  2630. /**
  2631. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  2632. * @vdev: virtual device instance
  2633. *
  2634. * Return: void
  2635. *
  2636. */
  2637. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  2638. {
  2639. /*
  2640. * Enable both AddrY (SA based search) and AddrX (Da based search)
  2641. * for TDLS link
  2642. *
  2643. * Enable AddrY (SA based search) only for non-WDS STA and
  2644. * ProxySTA VAP modes.
  2645. *
  2646. * In all other VAP modes, only DA based search should be
  2647. * enabled
  2648. */
  2649. if (vdev->opmode == wlan_op_mode_sta &&
  2650. vdev->tdls_link_connected)
  2651. vdev->hal_desc_addr_search_flags =
  2652. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  2653. else if ((vdev->opmode == wlan_op_mode_sta &&
  2654. (!vdev->wds_enabled || vdev->proxysta_vdev)))
  2655. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  2656. else
  2657. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  2658. }
  2659. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2660. static void dp_tx_desc_flush(struct dp_vdev *vdev)
  2661. {
  2662. }
  2663. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  2664. /* dp_tx_desc_flush() - release resources associated
  2665. * to tx_desc
  2666. * @vdev: virtual device instance
  2667. *
  2668. * This function will free all outstanding Tx buffers,
  2669. * including ME buffer for which either free during
  2670. * completion didn't happened or completion is not
  2671. * received.
  2672. */
  2673. static void dp_tx_desc_flush(struct dp_vdev *vdev)
  2674. {
  2675. uint8_t i, num_pool;
  2676. uint32_t j;
  2677. uint32_t num_desc;
  2678. struct dp_soc *soc = vdev->pdev->soc;
  2679. struct dp_tx_desc_s *tx_desc = NULL;
  2680. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  2681. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2682. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2683. for (i = 0; i < num_pool; i++) {
  2684. for (j = 0; j < num_desc; j++) {
  2685. tx_desc_pool = &((soc)->tx_desc[(i)]);
  2686. if (tx_desc_pool &&
  2687. tx_desc_pool->desc_pages.cacheable_pages) {
  2688. tx_desc = dp_tx_desc_find(soc, i,
  2689. (j & DP_TX_DESC_ID_PAGE_MASK) >>
  2690. DP_TX_DESC_ID_PAGE_OS,
  2691. (j & DP_TX_DESC_ID_OFFSET_MASK) >>
  2692. DP_TX_DESC_ID_OFFSET_OS);
  2693. if (tx_desc && (tx_desc->vdev == vdev) &&
  2694. (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)) {
  2695. dp_tx_comp_free_buf(soc, tx_desc);
  2696. dp_tx_desc_release(tx_desc, i);
  2697. }
  2698. }
  2699. }
  2700. }
  2701. }
  2702. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  2703. /**
  2704. * dp_tx_vdev_detach() - detach vdev from dp tx
  2705. * @vdev: virtual device instance
  2706. *
  2707. * Return: QDF_STATUS_SUCCESS: success
  2708. * QDF_STATUS_E_RESOURCES: Error return
  2709. */
  2710. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  2711. {
  2712. dp_tx_desc_flush(vdev);
  2713. return QDF_STATUS_SUCCESS;
  2714. }
  2715. /**
  2716. * dp_tx_pdev_attach() - attach pdev to dp tx
  2717. * @pdev: physical device instance
  2718. *
  2719. * Return: QDF_STATUS_SUCCESS: success
  2720. * QDF_STATUS_E_RESOURCES: Error return
  2721. */
  2722. QDF_STATUS dp_tx_pdev_attach(struct dp_pdev *pdev)
  2723. {
  2724. struct dp_soc *soc = pdev->soc;
  2725. /* Initialize Flow control counters */
  2726. qdf_atomic_init(&pdev->num_tx_exception);
  2727. qdf_atomic_init(&pdev->num_tx_outstanding);
  2728. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2729. /* Initialize descriptors in TCL Ring */
  2730. hal_tx_init_data_ring(soc->hal_soc,
  2731. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  2732. }
  2733. return QDF_STATUS_SUCCESS;
  2734. }
  2735. /**
  2736. * dp_tx_pdev_detach() - detach pdev from dp tx
  2737. * @pdev: physical device instance
  2738. *
  2739. * Return: QDF_STATUS_SUCCESS: success
  2740. * QDF_STATUS_E_RESOURCES: Error return
  2741. */
  2742. QDF_STATUS dp_tx_pdev_detach(struct dp_pdev *pdev)
  2743. {
  2744. dp_tx_me_exit(pdev);
  2745. return QDF_STATUS_SUCCESS;
  2746. }
  2747. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2748. /* Pools will be allocated dynamically */
  2749. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  2750. int num_desc)
  2751. {
  2752. uint8_t i;
  2753. for (i = 0; i < num_pool; i++) {
  2754. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  2755. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  2756. }
  2757. return 0;
  2758. }
  2759. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  2760. {
  2761. uint8_t i;
  2762. for (i = 0; i < num_pool; i++)
  2763. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  2764. }
  2765. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  2766. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  2767. int num_desc)
  2768. {
  2769. uint8_t i;
  2770. /* Allocate software Tx descriptor pools */
  2771. for (i = 0; i < num_pool; i++) {
  2772. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  2773. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2774. "%s Tx Desc Pool alloc %d failed %pK\n",
  2775. __func__, i, soc);
  2776. return ENOMEM;
  2777. }
  2778. }
  2779. return 0;
  2780. }
  2781. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  2782. {
  2783. uint8_t i;
  2784. for (i = 0; i < num_pool; i++) {
  2785. qdf_assert_always(!soc->tx_desc[i].num_allocated);
  2786. if (dp_tx_desc_pool_free(soc, i)) {
  2787. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2788. "%s Tx Desc Pool Free failed\n", __func__);
  2789. }
  2790. }
  2791. }
  2792. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  2793. /**
  2794. * dp_tx_soc_detach() - detach soc from dp tx
  2795. * @soc: core txrx main context
  2796. *
  2797. * This function will detach dp tx into main device context
  2798. * will free dp tx resource and initialize resources
  2799. *
  2800. * Return: QDF_STATUS_SUCCESS: success
  2801. * QDF_STATUS_E_RESOURCES: Error return
  2802. */
  2803. QDF_STATUS dp_tx_soc_detach(struct dp_soc *soc)
  2804. {
  2805. uint8_t num_pool;
  2806. uint16_t num_desc;
  2807. uint16_t num_ext_desc;
  2808. uint8_t i;
  2809. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2810. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2811. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  2812. dp_tx_flow_control_deinit(soc);
  2813. dp_tx_delete_static_pools(soc, num_pool);
  2814. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2815. "%s Tx Desc Pool Free num_pool = %d, descs = %d\n",
  2816. __func__, num_pool, num_desc);
  2817. for (i = 0; i < num_pool; i++) {
  2818. if (dp_tx_ext_desc_pool_free(soc, i)) {
  2819. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2820. "%s Tx Ext Desc Pool Free failed\n",
  2821. __func__);
  2822. return QDF_STATUS_E_RESOURCES;
  2823. }
  2824. }
  2825. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2826. "%s MSDU Ext Desc Pool %d Free descs = %d\n",
  2827. __func__, num_pool, num_ext_desc);
  2828. for (i = 0; i < num_pool; i++) {
  2829. dp_tx_tso_desc_pool_free(soc, i);
  2830. }
  2831. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2832. "%s TSO Desc Pool %d Free descs = %d\n",
  2833. __func__, num_pool, num_desc);
  2834. for (i = 0; i < num_pool; i++)
  2835. dp_tx_tso_num_seg_pool_free(soc, i);
  2836. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2837. "%s TSO Num of seg Desc Pool %d Free descs = %d\n",
  2838. __func__, num_pool, num_desc);
  2839. return QDF_STATUS_SUCCESS;
  2840. }
  2841. /**
  2842. * dp_tx_soc_attach() - attach soc to dp tx
  2843. * @soc: core txrx main context
  2844. *
  2845. * This function will attach dp tx into main device context
  2846. * will allocate dp tx resource and initialize resources
  2847. *
  2848. * Return: QDF_STATUS_SUCCESS: success
  2849. * QDF_STATUS_E_RESOURCES: Error return
  2850. */
  2851. QDF_STATUS dp_tx_soc_attach(struct dp_soc *soc)
  2852. {
  2853. uint8_t i;
  2854. uint8_t num_pool;
  2855. uint32_t num_desc;
  2856. uint32_t num_ext_desc;
  2857. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2858. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2859. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  2860. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  2861. goto fail;
  2862. dp_tx_flow_control_init(soc);
  2863. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2864. "%s Tx Desc Alloc num_pool = %d, descs = %d\n",
  2865. __func__, num_pool, num_desc);
  2866. /* Allocate extension tx descriptor pools */
  2867. for (i = 0; i < num_pool; i++) {
  2868. if (dp_tx_ext_desc_pool_alloc(soc, i, num_ext_desc)) {
  2869. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2870. "MSDU Ext Desc Pool alloc %d failed %pK\n",
  2871. i, soc);
  2872. goto fail;
  2873. }
  2874. }
  2875. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2876. "%s MSDU Ext Desc Alloc %d, descs = %d\n",
  2877. __func__, num_pool, num_ext_desc);
  2878. for (i = 0; i < num_pool; i++) {
  2879. if (dp_tx_tso_desc_pool_alloc(soc, i, num_desc)) {
  2880. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2881. "TSO Desc Pool alloc %d failed %pK\n",
  2882. i, soc);
  2883. goto fail;
  2884. }
  2885. }
  2886. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2887. "%s TSO Desc Alloc %d, descs = %d\n",
  2888. __func__, num_pool, num_desc);
  2889. for (i = 0; i < num_pool; i++) {
  2890. if (dp_tx_tso_num_seg_pool_alloc(soc, i, num_desc)) {
  2891. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2892. "TSO Num of seg Pool alloc %d failed %pK\n",
  2893. i, soc);
  2894. goto fail;
  2895. }
  2896. }
  2897. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2898. "%s TSO Num of seg pool Alloc %d, descs = %d\n",
  2899. __func__, num_pool, num_desc);
  2900. /* Initialize descriptors in TCL Rings */
  2901. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2902. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  2903. hal_tx_init_data_ring(soc->hal_soc,
  2904. soc->tcl_data_ring[i].hal_srng);
  2905. }
  2906. }
  2907. /*
  2908. * todo - Add a runtime config option to enable this.
  2909. */
  2910. /*
  2911. * Due to multiple issues on NPR EMU, enable it selectively
  2912. * only for NPR EMU, should be removed, once NPR platforms
  2913. * are stable.
  2914. */
  2915. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  2916. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2917. "%s HAL Tx init Success\n", __func__);
  2918. return QDF_STATUS_SUCCESS;
  2919. fail:
  2920. /* Detach will take care of freeing only allocated resources */
  2921. dp_tx_soc_detach(soc);
  2922. return QDF_STATUS_E_RESOURCES;
  2923. }
  2924. /*
  2925. * dp_tx_me_mem_free(): Function to free allocated memory in mcast enahncement
  2926. * pdev: pointer to DP PDEV structure
  2927. * seg_info_head: Pointer to the head of list
  2928. *
  2929. * return: void
  2930. */
  2931. static void dp_tx_me_mem_free(struct dp_pdev *pdev,
  2932. struct dp_tx_seg_info_s *seg_info_head)
  2933. {
  2934. struct dp_tx_me_buf_t *mc_uc_buf;
  2935. struct dp_tx_seg_info_s *seg_info_new = NULL;
  2936. qdf_nbuf_t nbuf = NULL;
  2937. uint64_t phy_addr;
  2938. while (seg_info_head) {
  2939. nbuf = seg_info_head->nbuf;
  2940. mc_uc_buf = (struct dp_tx_me_buf_t *)
  2941. seg_info_head->frags[0].vaddr;
  2942. phy_addr = seg_info_head->frags[0].paddr_hi;
  2943. phy_addr = (phy_addr << 32) | seg_info_head->frags[0].paddr_lo;
  2944. qdf_mem_unmap_nbytes_single(pdev->soc->osdev,
  2945. phy_addr,
  2946. QDF_DMA_TO_DEVICE , DP_MAC_ADDR_LEN);
  2947. dp_tx_me_free_buf(pdev, mc_uc_buf);
  2948. qdf_nbuf_free(nbuf);
  2949. seg_info_new = seg_info_head;
  2950. seg_info_head = seg_info_head->next;
  2951. qdf_mem_free(seg_info_new);
  2952. }
  2953. }
  2954. /**
  2955. * dp_tx_me_send_convert_ucast(): function to convert multicast to unicast
  2956. * @vdev: DP VDEV handle
  2957. * @nbuf: Multicast nbuf
  2958. * @newmac: Table of the clients to which packets have to be sent
  2959. * @new_mac_cnt: No of clients
  2960. *
  2961. * return: no of converted packets
  2962. */
  2963. uint16_t
  2964. dp_tx_me_send_convert_ucast(struct cdp_vdev *vdev_handle, qdf_nbuf_t nbuf,
  2965. uint8_t newmac[][DP_MAC_ADDR_LEN], uint8_t new_mac_cnt)
  2966. {
  2967. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  2968. struct dp_pdev *pdev = vdev->pdev;
  2969. struct ether_header *eh;
  2970. uint8_t *data;
  2971. uint16_t len;
  2972. /* reference to frame dst addr */
  2973. uint8_t *dstmac;
  2974. /* copy of original frame src addr */
  2975. uint8_t srcmac[DP_MAC_ADDR_LEN];
  2976. /* local index into newmac */
  2977. uint8_t new_mac_idx = 0;
  2978. struct dp_tx_me_buf_t *mc_uc_buf;
  2979. qdf_nbuf_t nbuf_clone;
  2980. struct dp_tx_msdu_info_s msdu_info;
  2981. struct dp_tx_seg_info_s *seg_info_head = NULL;
  2982. struct dp_tx_seg_info_s *seg_info_tail = NULL;
  2983. struct dp_tx_seg_info_s *seg_info_new;
  2984. struct dp_tx_frag_info_s data_frag;
  2985. qdf_dma_addr_t paddr_data;
  2986. qdf_dma_addr_t paddr_mcbuf = 0;
  2987. uint8_t empty_entry_mac[DP_MAC_ADDR_LEN] = {0};
  2988. QDF_STATUS status;
  2989. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  2990. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2991. eh = (struct ether_header *) nbuf;
  2992. qdf_mem_copy(srcmac, eh->ether_shost, DP_MAC_ADDR_LEN);
  2993. len = qdf_nbuf_len(nbuf);
  2994. data = qdf_nbuf_data(nbuf);
  2995. status = qdf_nbuf_map(vdev->osdev, nbuf,
  2996. QDF_DMA_TO_DEVICE);
  2997. if (status) {
  2998. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2999. "Mapping failure Error:%d", status);
  3000. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  3001. qdf_nbuf_free(nbuf);
  3002. return 1;
  3003. }
  3004. paddr_data = qdf_nbuf_get_frag_paddr(nbuf, 0) + IEEE80211_ADDR_LEN;
  3005. /*preparing data fragment*/
  3006. data_frag.vaddr = qdf_nbuf_data(nbuf) + IEEE80211_ADDR_LEN;
  3007. data_frag.paddr_lo = (uint32_t)paddr_data;
  3008. data_frag.paddr_hi = (((uint64_t) paddr_data) >> 32);
  3009. data_frag.len = len - DP_MAC_ADDR_LEN;
  3010. for (new_mac_idx = 0; new_mac_idx < new_mac_cnt; new_mac_idx++) {
  3011. dstmac = newmac[new_mac_idx];
  3012. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3013. "added mac addr (%pM)", dstmac);
  3014. /* Check for NULL Mac Address */
  3015. if (!qdf_mem_cmp(dstmac, empty_entry_mac, DP_MAC_ADDR_LEN))
  3016. continue;
  3017. /* frame to self mac. skip */
  3018. if (!qdf_mem_cmp(dstmac, srcmac, DP_MAC_ADDR_LEN))
  3019. continue;
  3020. /*
  3021. * TODO: optimize to avoid malloc in per-packet path
  3022. * For eg. seg_pool can be made part of vdev structure
  3023. */
  3024. seg_info_new = qdf_mem_malloc(sizeof(*seg_info_new));
  3025. if (!seg_info_new) {
  3026. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3027. "alloc failed");
  3028. DP_STATS_INC(vdev, tx_i.mcast_en.fail_seg_alloc, 1);
  3029. goto fail_seg_alloc;
  3030. }
  3031. mc_uc_buf = dp_tx_me_alloc_buf(pdev);
  3032. if (mc_uc_buf == NULL)
  3033. goto fail_buf_alloc;
  3034. /*
  3035. * TODO: Check if we need to clone the nbuf
  3036. * Or can we just use the reference for all cases
  3037. */
  3038. if (new_mac_idx < (new_mac_cnt - 1)) {
  3039. nbuf_clone = qdf_nbuf_clone((qdf_nbuf_t)nbuf);
  3040. if (nbuf_clone == NULL) {
  3041. DP_STATS_INC(vdev, tx_i.mcast_en.clone_fail, 1);
  3042. goto fail_clone;
  3043. }
  3044. } else {
  3045. /*
  3046. * Update the ref
  3047. * to account for frame sent without cloning
  3048. */
  3049. qdf_nbuf_ref(nbuf);
  3050. nbuf_clone = nbuf;
  3051. }
  3052. qdf_mem_copy(mc_uc_buf->data, dstmac, DP_MAC_ADDR_LEN);
  3053. status = qdf_mem_map_nbytes_single(vdev->osdev, mc_uc_buf->data,
  3054. QDF_DMA_TO_DEVICE, DP_MAC_ADDR_LEN,
  3055. &paddr_mcbuf);
  3056. if (status) {
  3057. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3058. "Mapping failure Error:%d", status);
  3059. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  3060. goto fail_map;
  3061. }
  3062. seg_info_new->frags[0].vaddr = (uint8_t *)mc_uc_buf;
  3063. seg_info_new->frags[0].paddr_lo = (uint32_t) paddr_mcbuf;
  3064. seg_info_new->frags[0].paddr_hi =
  3065. ((uint64_t) paddr_mcbuf >> 32);
  3066. seg_info_new->frags[0].len = DP_MAC_ADDR_LEN;
  3067. seg_info_new->frags[1] = data_frag;
  3068. seg_info_new->nbuf = nbuf_clone;
  3069. seg_info_new->frag_cnt = 2;
  3070. seg_info_new->total_len = len;
  3071. seg_info_new->next = NULL;
  3072. if (seg_info_head == NULL)
  3073. seg_info_head = seg_info_new;
  3074. else
  3075. seg_info_tail->next = seg_info_new;
  3076. seg_info_tail = seg_info_new;
  3077. }
  3078. if (!seg_info_head) {
  3079. goto free_return;
  3080. }
  3081. msdu_info.u.sg_info.curr_seg = seg_info_head;
  3082. msdu_info.num_seg = new_mac_cnt;
  3083. msdu_info.frm_type = dp_tx_frm_me;
  3084. DP_STATS_INC(vdev, tx_i.mcast_en.ucast, new_mac_cnt);
  3085. dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  3086. while (seg_info_head->next) {
  3087. seg_info_new = seg_info_head;
  3088. seg_info_head = seg_info_head->next;
  3089. qdf_mem_free(seg_info_new);
  3090. }
  3091. qdf_mem_free(seg_info_head);
  3092. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  3093. qdf_nbuf_free(nbuf);
  3094. return new_mac_cnt;
  3095. fail_map:
  3096. qdf_nbuf_free(nbuf_clone);
  3097. fail_clone:
  3098. dp_tx_me_free_buf(pdev, mc_uc_buf);
  3099. fail_buf_alloc:
  3100. qdf_mem_free(seg_info_new);
  3101. fail_seg_alloc:
  3102. dp_tx_me_mem_free(pdev, seg_info_head);
  3103. free_return:
  3104. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  3105. qdf_nbuf_free(nbuf);
  3106. return 1;
  3107. }