dp_tx.c 143 KB

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  1. /*
  2. * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "dp_htt.h"
  20. #include "hal_hw_headers.h"
  21. #include "dp_tx.h"
  22. #include "dp_tx_desc.h"
  23. #include "dp_peer.h"
  24. #include "dp_types.h"
  25. #include "hal_tx.h"
  26. #include "qdf_mem.h"
  27. #include "qdf_nbuf.h"
  28. #include "qdf_net_types.h"
  29. #include <wlan_cfg.h>
  30. #include "dp_ipa.h"
  31. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  32. #include "if_meta_hdr.h"
  33. #endif
  34. #include "enet.h"
  35. #include "dp_internal.h"
  36. #ifdef FEATURE_WDS
  37. #include "dp_txrx_wds.h"
  38. #endif
  39. #ifdef ATH_SUPPORT_IQUE
  40. #include "dp_txrx_me.h"
  41. #endif
  42. #include "dp_hist.h"
  43. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  44. #include <dp_swlm.h>
  45. #endif
  46. /* Flag to skip CCE classify when mesh or tid override enabled */
  47. #define DP_TX_SKIP_CCE_CLASSIFY \
  48. (DP_TXRX_HLOS_TID_OVERRIDE_ENABLED | DP_TX_MESH_ENABLED)
  49. /* TODO Add support in TSO */
  50. #define DP_DESC_NUM_FRAG(x) 0
  51. /* disable TQM_BYPASS */
  52. #define TQM_BYPASS_WAR 0
  53. /* invalid peer id for reinject*/
  54. #define DP_INVALID_PEER 0XFFFE
  55. /*mapping between hal encrypt type and cdp_sec_type*/
  56. #define MAX_CDP_SEC_TYPE 12
  57. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  58. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  59. HAL_TX_ENCRYPT_TYPE_WEP_128,
  60. HAL_TX_ENCRYPT_TYPE_WEP_104,
  61. HAL_TX_ENCRYPT_TYPE_WEP_40,
  62. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  63. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  64. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  65. HAL_TX_ENCRYPT_TYPE_WAPI,
  66. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  67. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  68. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  69. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  70. #ifdef CONFIG_WLAN_SYSFS_MEM_STATS
  71. /**
  72. * dp_update_tx_desc_stats - Update the increase or decrease in
  73. * outstanding tx desc count
  74. * values on pdev and soc
  75. * @vdev: DP pdev handle
  76. *
  77. * Return: void
  78. */
  79. static inline void
  80. dp_update_tx_desc_stats(struct dp_pdev *pdev)
  81. {
  82. int32_t tx_descs_cnt =
  83. qdf_atomic_read(&pdev->num_tx_outstanding);
  84. if (pdev->tx_descs_max < tx_descs_cnt)
  85. pdev->tx_descs_max = tx_descs_cnt;
  86. qdf_mem_tx_desc_cnt_update(pdev->num_tx_outstanding,
  87. pdev->tx_descs_max);
  88. }
  89. #else /* CONFIG_WLAN_SYSFS_MEM_STATS */
  90. static inline void
  91. dp_update_tx_desc_stats(struct dp_pdev *pdev)
  92. {
  93. }
  94. #endif /* CONFIG_WLAN_SYSFS_MEM_STATS */
  95. #ifdef QCA_TX_LIMIT_CHECK
  96. /**
  97. * dp_tx_limit_check - Check if allocated tx descriptors reached
  98. * soc max limit and pdev max limit
  99. * @vdev: DP vdev handle
  100. *
  101. * Return: true if allocated tx descriptors reached max configured value, else
  102. * false
  103. */
  104. static inline bool
  105. dp_tx_limit_check(struct dp_vdev *vdev)
  106. {
  107. struct dp_pdev *pdev = vdev->pdev;
  108. struct dp_soc *soc = pdev->soc;
  109. if (qdf_atomic_read(&soc->num_tx_outstanding) >=
  110. soc->num_tx_allowed) {
  111. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  112. "%s: queued packets are more than max tx, drop the frame",
  113. __func__);
  114. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  115. return true;
  116. }
  117. if (qdf_atomic_read(&pdev->num_tx_outstanding) >=
  118. pdev->num_tx_allowed) {
  119. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  120. "%s: queued packets are more than max tx, drop the frame",
  121. __func__);
  122. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  123. return true;
  124. }
  125. return false;
  126. }
  127. /**
  128. * dp_tx_exception_limit_check - Check if allocated tx exception descriptors
  129. * reached soc max limit
  130. * @vdev: DP vdev handle
  131. *
  132. * Return: true if allocated tx descriptors reached max configured value, else
  133. * false
  134. */
  135. static inline bool
  136. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  137. {
  138. struct dp_pdev *pdev = vdev->pdev;
  139. struct dp_soc *soc = pdev->soc;
  140. if (qdf_atomic_read(&soc->num_tx_exception) >=
  141. soc->num_msdu_exception_desc) {
  142. dp_info("exc packets are more than max drop the exc pkt");
  143. DP_STATS_INC(vdev, tx_i.dropped.exc_desc_na.num, 1);
  144. return true;
  145. }
  146. return false;
  147. }
  148. /**
  149. * dp_tx_outstanding_inc - Increment outstanding tx desc values on pdev and soc
  150. * @vdev: DP pdev handle
  151. *
  152. * Return: void
  153. */
  154. static inline void
  155. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  156. {
  157. struct dp_soc *soc = pdev->soc;
  158. qdf_atomic_inc(&pdev->num_tx_outstanding);
  159. qdf_atomic_inc(&soc->num_tx_outstanding);
  160. dp_update_tx_desc_stats(pdev);
  161. }
  162. /**
  163. * dp_tx_outstanding__dec - Decrement outstanding tx desc values on pdev and soc
  164. * @vdev: DP pdev handle
  165. *
  166. * Return: void
  167. */
  168. static inline void
  169. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  170. {
  171. struct dp_soc *soc = pdev->soc;
  172. qdf_atomic_dec(&pdev->num_tx_outstanding);
  173. qdf_atomic_dec(&soc->num_tx_outstanding);
  174. dp_update_tx_desc_stats(pdev);
  175. }
  176. #else //QCA_TX_LIMIT_CHECK
  177. static inline bool
  178. dp_tx_limit_check(struct dp_vdev *vdev)
  179. {
  180. return false;
  181. }
  182. static inline bool
  183. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  184. {
  185. return false;
  186. }
  187. static inline void
  188. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  189. {
  190. qdf_atomic_inc(&pdev->num_tx_outstanding);
  191. dp_update_tx_desc_stats(pdev);
  192. }
  193. static inline void
  194. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  195. {
  196. qdf_atomic_dec(&pdev->num_tx_outstanding);
  197. dp_update_tx_desc_stats(pdev);
  198. }
  199. #endif //QCA_TX_LIMIT_CHECK
  200. #if defined(FEATURE_TSO)
  201. /**
  202. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  203. *
  204. * @soc - core txrx main context
  205. * @seg_desc - tso segment descriptor
  206. * @num_seg_desc - tso number segment descriptor
  207. */
  208. static void dp_tx_tso_unmap_segment(
  209. struct dp_soc *soc,
  210. struct qdf_tso_seg_elem_t *seg_desc,
  211. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  212. {
  213. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  214. if (qdf_unlikely(!seg_desc)) {
  215. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  216. __func__, __LINE__);
  217. qdf_assert(0);
  218. } else if (qdf_unlikely(!num_seg_desc)) {
  219. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  220. __func__, __LINE__);
  221. qdf_assert(0);
  222. } else {
  223. bool is_last_seg;
  224. /* no tso segment left to do dma unmap */
  225. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  226. return;
  227. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  228. true : false;
  229. qdf_nbuf_unmap_tso_segment(soc->osdev,
  230. seg_desc, is_last_seg);
  231. num_seg_desc->num_seg.tso_cmn_num_seg--;
  232. }
  233. }
  234. /**
  235. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  236. * back to the freelist
  237. *
  238. * @soc - soc device handle
  239. * @tx_desc - Tx software descriptor
  240. */
  241. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  242. struct dp_tx_desc_s *tx_desc)
  243. {
  244. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  245. if (qdf_unlikely(!tx_desc->tso_desc)) {
  246. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  247. "%s %d TSO desc is NULL!",
  248. __func__, __LINE__);
  249. qdf_assert(0);
  250. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  251. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  252. "%s %d TSO num desc is NULL!",
  253. __func__, __LINE__);
  254. qdf_assert(0);
  255. } else {
  256. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  257. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  258. /* Add the tso num segment into the free list */
  259. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  260. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  261. tx_desc->tso_num_desc);
  262. tx_desc->tso_num_desc = NULL;
  263. DP_STATS_INC(tx_desc->pdev, tso_stats.tso_comp, 1);
  264. }
  265. /* Add the tso segment into the free list*/
  266. dp_tx_tso_desc_free(soc,
  267. tx_desc->pool_id, tx_desc->tso_desc);
  268. tx_desc->tso_desc = NULL;
  269. }
  270. }
  271. #else
  272. static void dp_tx_tso_unmap_segment(
  273. struct dp_soc *soc,
  274. struct qdf_tso_seg_elem_t *seg_desc,
  275. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  276. {
  277. }
  278. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  279. struct dp_tx_desc_s *tx_desc)
  280. {
  281. }
  282. #endif
  283. /**
  284. * dp_tx_desc_release() - Release Tx Descriptor
  285. * @tx_desc : Tx Descriptor
  286. * @desc_pool_id: Descriptor Pool ID
  287. *
  288. * Deallocate all resources attached to Tx descriptor and free the Tx
  289. * descriptor.
  290. *
  291. * Return:
  292. */
  293. static void
  294. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  295. {
  296. struct dp_pdev *pdev = tx_desc->pdev;
  297. struct dp_soc *soc;
  298. uint8_t comp_status = 0;
  299. qdf_assert(pdev);
  300. soc = pdev->soc;
  301. dp_tx_outstanding_dec(pdev);
  302. if (tx_desc->frm_type == dp_tx_frm_tso)
  303. dp_tx_tso_desc_release(soc, tx_desc);
  304. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  305. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  306. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  307. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  308. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  309. qdf_atomic_dec(&soc->num_tx_exception);
  310. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  311. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  312. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  313. soc->hal_soc);
  314. else
  315. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  316. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  317. "Tx Completion Release desc %d status %d outstanding %d",
  318. tx_desc->id, comp_status,
  319. qdf_atomic_read(&pdev->num_tx_outstanding));
  320. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  321. return;
  322. }
  323. /**
  324. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  325. * @vdev: DP vdev Handle
  326. * @nbuf: skb
  327. * @msdu_info: msdu_info required to create HTT metadata
  328. *
  329. * Prepares and fills HTT metadata in the frame pre-header for special frames
  330. * that should be transmitted using varying transmit parameters.
  331. * There are 2 VDEV modes that currently needs this special metadata -
  332. * 1) Mesh Mode
  333. * 2) DSRC Mode
  334. *
  335. * Return: HTT metadata size
  336. *
  337. */
  338. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  339. struct dp_tx_msdu_info_s *msdu_info)
  340. {
  341. uint32_t *meta_data = msdu_info->meta_data;
  342. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  343. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  344. uint8_t htt_desc_size;
  345. /* Size rounded of multiple of 8 bytes */
  346. uint8_t htt_desc_size_aligned;
  347. uint8_t *hdr = NULL;
  348. /*
  349. * Metadata - HTT MSDU Extension header
  350. */
  351. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  352. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  353. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  354. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  355. meta_data[0])) {
  356. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  357. htt_desc_size_aligned)) {
  358. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  359. htt_desc_size_aligned);
  360. if (!nbuf) {
  361. /*
  362. * qdf_nbuf_realloc_headroom won't do skb_clone
  363. * as skb_realloc_headroom does. so, no free is
  364. * needed here.
  365. */
  366. DP_STATS_INC(vdev,
  367. tx_i.dropped.headroom_insufficient,
  368. 1);
  369. qdf_print(" %s[%d] skb_realloc_headroom failed",
  370. __func__, __LINE__);
  371. return 0;
  372. }
  373. }
  374. /* Fill and add HTT metaheader */
  375. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  376. if (!hdr) {
  377. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  378. "Error in filling HTT metadata");
  379. return 0;
  380. }
  381. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  382. } else if (vdev->opmode == wlan_op_mode_ocb) {
  383. /* Todo - Add support for DSRC */
  384. }
  385. return htt_desc_size_aligned;
  386. }
  387. /**
  388. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  389. * @tso_seg: TSO segment to process
  390. * @ext_desc: Pointer to MSDU extension descriptor
  391. *
  392. * Return: void
  393. */
  394. #if defined(FEATURE_TSO)
  395. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  396. void *ext_desc)
  397. {
  398. uint8_t num_frag;
  399. uint32_t tso_flags;
  400. /*
  401. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  402. * tcp_flag_mask
  403. *
  404. * Checksum enable flags are set in TCL descriptor and not in Extension
  405. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  406. */
  407. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  408. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  409. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  410. tso_seg->tso_flags.ip_len);
  411. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  412. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  413. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  414. uint32_t lo = 0;
  415. uint32_t hi = 0;
  416. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  417. (tso_seg->tso_frags[num_frag].length));
  418. qdf_dmaaddr_to_32s(
  419. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  420. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  421. tso_seg->tso_frags[num_frag].length);
  422. }
  423. return;
  424. }
  425. #else
  426. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  427. void *ext_desc)
  428. {
  429. return;
  430. }
  431. #endif
  432. #if defined(FEATURE_TSO)
  433. /**
  434. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  435. * allocated and free them
  436. *
  437. * @soc: soc handle
  438. * @free_seg: list of tso segments
  439. * @msdu_info: msdu descriptor
  440. *
  441. * Return - void
  442. */
  443. static void dp_tx_free_tso_seg_list(
  444. struct dp_soc *soc,
  445. struct qdf_tso_seg_elem_t *free_seg,
  446. struct dp_tx_msdu_info_s *msdu_info)
  447. {
  448. struct qdf_tso_seg_elem_t *next_seg;
  449. while (free_seg) {
  450. next_seg = free_seg->next;
  451. dp_tx_tso_desc_free(soc,
  452. msdu_info->tx_queue.desc_pool_id,
  453. free_seg);
  454. free_seg = next_seg;
  455. }
  456. }
  457. /**
  458. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  459. * allocated and free them
  460. *
  461. * @soc: soc handle
  462. * @free_num_seg: list of tso number segments
  463. * @msdu_info: msdu descriptor
  464. * Return - void
  465. */
  466. static void dp_tx_free_tso_num_seg_list(
  467. struct dp_soc *soc,
  468. struct qdf_tso_num_seg_elem_t *free_num_seg,
  469. struct dp_tx_msdu_info_s *msdu_info)
  470. {
  471. struct qdf_tso_num_seg_elem_t *next_num_seg;
  472. while (free_num_seg) {
  473. next_num_seg = free_num_seg->next;
  474. dp_tso_num_seg_free(soc,
  475. msdu_info->tx_queue.desc_pool_id,
  476. free_num_seg);
  477. free_num_seg = next_num_seg;
  478. }
  479. }
  480. /**
  481. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  482. * do dma unmap for each segment
  483. *
  484. * @soc: soc handle
  485. * @free_seg: list of tso segments
  486. * @num_seg_desc: tso number segment descriptor
  487. *
  488. * Return - void
  489. */
  490. static void dp_tx_unmap_tso_seg_list(
  491. struct dp_soc *soc,
  492. struct qdf_tso_seg_elem_t *free_seg,
  493. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  494. {
  495. struct qdf_tso_seg_elem_t *next_seg;
  496. if (qdf_unlikely(!num_seg_desc)) {
  497. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  498. return;
  499. }
  500. while (free_seg) {
  501. next_seg = free_seg->next;
  502. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  503. free_seg = next_seg;
  504. }
  505. }
  506. #ifdef FEATURE_TSO_STATS
  507. /**
  508. * dp_tso_get_stats_idx: Retrieve the tso packet id
  509. * @pdev - pdev handle
  510. *
  511. * Return: id
  512. */
  513. static uint32_t dp_tso_get_stats_idx(struct dp_pdev *pdev)
  514. {
  515. uint32_t stats_idx;
  516. stats_idx = (((uint32_t)qdf_atomic_inc_return(&pdev->tso_idx))
  517. % CDP_MAX_TSO_PACKETS);
  518. return stats_idx;
  519. }
  520. #else
  521. static int dp_tso_get_stats_idx(struct dp_pdev *pdev)
  522. {
  523. return 0;
  524. }
  525. #endif /* FEATURE_TSO_STATS */
  526. /**
  527. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  528. * free the tso segments descriptor and
  529. * tso num segments descriptor
  530. *
  531. * @soc: soc handle
  532. * @msdu_info: msdu descriptor
  533. * @tso_seg_unmap: flag to show if dma unmap is necessary
  534. *
  535. * Return - void
  536. */
  537. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  538. struct dp_tx_msdu_info_s *msdu_info,
  539. bool tso_seg_unmap)
  540. {
  541. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  542. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  543. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  544. tso_info->tso_num_seg_list;
  545. /* do dma unmap for each segment */
  546. if (tso_seg_unmap)
  547. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  548. /* free all tso number segment descriptor though looks only have 1 */
  549. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  550. /* free all tso segment descriptor */
  551. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  552. }
  553. /**
  554. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  555. * @vdev: virtual device handle
  556. * @msdu: network buffer
  557. * @msdu_info: meta data associated with the msdu
  558. *
  559. * Return: QDF_STATUS_SUCCESS success
  560. */
  561. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  562. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  563. {
  564. struct qdf_tso_seg_elem_t *tso_seg;
  565. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  566. struct dp_soc *soc = vdev->pdev->soc;
  567. struct dp_pdev *pdev = vdev->pdev;
  568. struct qdf_tso_info_t *tso_info;
  569. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  570. tso_info = &msdu_info->u.tso_info;
  571. tso_info->curr_seg = NULL;
  572. tso_info->tso_seg_list = NULL;
  573. tso_info->num_segs = num_seg;
  574. msdu_info->frm_type = dp_tx_frm_tso;
  575. tso_info->tso_num_seg_list = NULL;
  576. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  577. while (num_seg) {
  578. tso_seg = dp_tx_tso_desc_alloc(
  579. soc, msdu_info->tx_queue.desc_pool_id);
  580. if (tso_seg) {
  581. tso_seg->next = tso_info->tso_seg_list;
  582. tso_info->tso_seg_list = tso_seg;
  583. num_seg--;
  584. } else {
  585. dp_err_rl("Failed to alloc tso seg desc");
  586. DP_STATS_INC_PKT(vdev->pdev,
  587. tso_stats.tso_no_mem_dropped, 1,
  588. qdf_nbuf_len(msdu));
  589. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  590. return QDF_STATUS_E_NOMEM;
  591. }
  592. }
  593. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  594. tso_num_seg = dp_tso_num_seg_alloc(soc,
  595. msdu_info->tx_queue.desc_pool_id);
  596. if (tso_num_seg) {
  597. tso_num_seg->next = tso_info->tso_num_seg_list;
  598. tso_info->tso_num_seg_list = tso_num_seg;
  599. } else {
  600. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  601. __func__);
  602. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  603. return QDF_STATUS_E_NOMEM;
  604. }
  605. msdu_info->num_seg =
  606. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  607. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  608. msdu_info->num_seg);
  609. if (!(msdu_info->num_seg)) {
  610. /*
  611. * Free allocated TSO seg desc and number seg desc,
  612. * do unmap for segments if dma map has done.
  613. */
  614. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  615. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  616. return QDF_STATUS_E_INVAL;
  617. }
  618. tso_info->curr_seg = tso_info->tso_seg_list;
  619. tso_info->msdu_stats_idx = dp_tso_get_stats_idx(pdev);
  620. dp_tso_packet_update(pdev, tso_info->msdu_stats_idx,
  621. msdu, msdu_info->num_seg);
  622. dp_tso_segment_stats_update(pdev, tso_info->tso_seg_list,
  623. tso_info->msdu_stats_idx);
  624. dp_stats_tso_segment_histogram_update(pdev, msdu_info->num_seg);
  625. return QDF_STATUS_SUCCESS;
  626. }
  627. #else
  628. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  629. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  630. {
  631. return QDF_STATUS_E_NOMEM;
  632. }
  633. #endif
  634. QDF_COMPILE_TIME_ASSERT(dp_tx_htt_metadata_len_check,
  635. (DP_TX_MSDU_INFO_META_DATA_DWORDS * 4 >=
  636. sizeof(struct htt_tx_msdu_desc_ext2_t)));
  637. /**
  638. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  639. * @vdev: DP Vdev handle
  640. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  641. * @desc_pool_id: Descriptor Pool ID
  642. *
  643. * Return:
  644. */
  645. static
  646. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  647. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  648. {
  649. uint8_t i;
  650. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  651. struct dp_tx_seg_info_s *seg_info;
  652. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  653. struct dp_soc *soc = vdev->pdev->soc;
  654. /* Allocate an extension descriptor */
  655. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  656. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  657. if (!msdu_ext_desc) {
  658. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  659. return NULL;
  660. }
  661. if (msdu_info->exception_fw &&
  662. qdf_unlikely(vdev->mesh_vdev)) {
  663. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  664. &msdu_info->meta_data[0],
  665. sizeof(struct htt_tx_msdu_desc_ext2_t));
  666. qdf_atomic_inc(&soc->num_tx_exception);
  667. msdu_ext_desc->flags |= DP_TX_EXT_DESC_FLAG_METADATA_VALID;
  668. }
  669. switch (msdu_info->frm_type) {
  670. case dp_tx_frm_sg:
  671. case dp_tx_frm_me:
  672. case dp_tx_frm_raw:
  673. seg_info = msdu_info->u.sg_info.curr_seg;
  674. /* Update the buffer pointers in MSDU Extension Descriptor */
  675. for (i = 0; i < seg_info->frag_cnt; i++) {
  676. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  677. seg_info->frags[i].paddr_lo,
  678. seg_info->frags[i].paddr_hi,
  679. seg_info->frags[i].len);
  680. }
  681. break;
  682. case dp_tx_frm_tso:
  683. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  684. &cached_ext_desc[0]);
  685. break;
  686. default:
  687. break;
  688. }
  689. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  690. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  691. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  692. msdu_ext_desc->vaddr);
  693. return msdu_ext_desc;
  694. }
  695. /**
  696. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  697. *
  698. * @skb: skb to be traced
  699. * @msdu_id: msdu_id of the packet
  700. * @vdev_id: vdev_id of the packet
  701. *
  702. * Return: None
  703. */
  704. #ifdef DP_DISABLE_TX_PKT_TRACE
  705. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  706. uint8_t vdev_id)
  707. {
  708. }
  709. #else
  710. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  711. uint8_t vdev_id)
  712. {
  713. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  714. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  715. DPTRACE(qdf_dp_trace_ptr(skb,
  716. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  717. QDF_TRACE_DEFAULT_PDEV_ID,
  718. qdf_nbuf_data_addr(skb),
  719. sizeof(qdf_nbuf_data(skb)),
  720. msdu_id, vdev_id, 0));
  721. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  722. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  723. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  724. msdu_id, QDF_TX));
  725. }
  726. #endif
  727. #ifdef WLAN_DP_FEATURE_MARK_ICMP_REQ_TO_FW
  728. /**
  729. * dp_tx_is_nbuf_marked_exception() - Check if the packet has been marked as
  730. * exception by the upper layer (OS_IF)
  731. * @soc: DP soc handle
  732. * @nbuf: packet to be transmitted
  733. *
  734. * Returns: 1 if the packet is marked as exception,
  735. * 0, if the packet is not marked as exception.
  736. */
  737. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  738. qdf_nbuf_t nbuf)
  739. {
  740. return QDF_NBUF_CB_TX_PACKET_TO_FW(nbuf);
  741. }
  742. #else
  743. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  744. qdf_nbuf_t nbuf)
  745. {
  746. return 0;
  747. }
  748. #endif
  749. /**
  750. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  751. * @vdev: DP vdev handle
  752. * @nbuf: skb
  753. * @desc_pool_id: Descriptor pool ID
  754. * @meta_data: Metadata to the fw
  755. * @tx_exc_metadata: Handle that holds exception path metadata
  756. * Allocate and prepare Tx descriptor with msdu information.
  757. *
  758. * Return: Pointer to Tx Descriptor on success,
  759. * NULL on failure
  760. */
  761. static
  762. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  763. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  764. struct dp_tx_msdu_info_s *msdu_info,
  765. struct cdp_tx_exception_metadata *tx_exc_metadata)
  766. {
  767. uint8_t align_pad;
  768. uint8_t is_exception = 0;
  769. uint8_t htt_hdr_size;
  770. struct dp_tx_desc_s *tx_desc;
  771. struct dp_pdev *pdev = vdev->pdev;
  772. struct dp_soc *soc = pdev->soc;
  773. if (dp_tx_limit_check(vdev))
  774. return NULL;
  775. /* Allocate software Tx descriptor */
  776. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  777. if (qdf_unlikely(!tx_desc)) {
  778. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  779. return NULL;
  780. }
  781. dp_tx_outstanding_inc(pdev);
  782. /* Initialize the SW tx descriptor */
  783. tx_desc->nbuf = nbuf;
  784. tx_desc->frm_type = dp_tx_frm_std;
  785. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  786. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  787. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  788. tx_desc->vdev_id = vdev->vdev_id;
  789. tx_desc->pdev = pdev;
  790. tx_desc->msdu_ext_desc = NULL;
  791. tx_desc->pkt_offset = 0;
  792. tx_desc->length = qdf_nbuf_headlen(nbuf);
  793. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  794. if (qdf_unlikely(vdev->multipass_en)) {
  795. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  796. goto failure;
  797. }
  798. /* Packets marked by upper layer (OS-IF) to be sent to FW */
  799. if (dp_tx_is_nbuf_marked_exception(soc, nbuf))
  800. is_exception = 1;
  801. /*
  802. * For special modes (vdev_type == ocb or mesh), data frames should be
  803. * transmitted using varying transmit parameters (tx spec) which include
  804. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  805. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  806. * These frames are sent as exception packets to firmware.
  807. *
  808. * HW requirement is that metadata should always point to a
  809. * 8-byte aligned address. So we add alignment pad to start of buffer.
  810. * HTT Metadata should be ensured to be multiple of 8-bytes,
  811. * to get 8-byte aligned start address along with align_pad added
  812. *
  813. * |-----------------------------|
  814. * | |
  815. * |-----------------------------| <-----Buffer Pointer Address given
  816. * | | ^ in HW descriptor (aligned)
  817. * | HTT Metadata | |
  818. * | | |
  819. * | | | Packet Offset given in descriptor
  820. * | | |
  821. * |-----------------------------| |
  822. * | Alignment Pad | v
  823. * |-----------------------------| <----- Actual buffer start address
  824. * | SKB Data | (Unaligned)
  825. * | |
  826. * | |
  827. * | |
  828. * | |
  829. * | |
  830. * |-----------------------------|
  831. */
  832. if (qdf_unlikely((msdu_info->exception_fw)) ||
  833. (vdev->opmode == wlan_op_mode_ocb) ||
  834. (tx_exc_metadata &&
  835. tx_exc_metadata->is_tx_sniffer)) {
  836. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  837. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  838. DP_STATS_INC(vdev,
  839. tx_i.dropped.headroom_insufficient, 1);
  840. goto failure;
  841. }
  842. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  843. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  844. "qdf_nbuf_push_head failed");
  845. goto failure;
  846. }
  847. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  848. msdu_info);
  849. if (htt_hdr_size == 0)
  850. goto failure;
  851. tx_desc->length = qdf_nbuf_headlen(nbuf);
  852. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  853. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  854. is_exception = 1;
  855. tx_desc->length -= tx_desc->pkt_offset;
  856. }
  857. #if !TQM_BYPASS_WAR
  858. if (is_exception || tx_exc_metadata)
  859. #endif
  860. {
  861. /* Temporary WAR due to TQM VP issues */
  862. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  863. qdf_atomic_inc(&soc->num_tx_exception);
  864. }
  865. return tx_desc;
  866. failure:
  867. dp_tx_desc_release(tx_desc, desc_pool_id);
  868. return NULL;
  869. }
  870. /**
  871. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  872. * @vdev: DP vdev handle
  873. * @nbuf: skb
  874. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  875. * @desc_pool_id : Descriptor Pool ID
  876. *
  877. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  878. * information. For frames wth fragments, allocate and prepare
  879. * an MSDU extension descriptor
  880. *
  881. * Return: Pointer to Tx Descriptor on success,
  882. * NULL on failure
  883. */
  884. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  885. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  886. uint8_t desc_pool_id)
  887. {
  888. struct dp_tx_desc_s *tx_desc;
  889. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  890. struct dp_pdev *pdev = vdev->pdev;
  891. struct dp_soc *soc = pdev->soc;
  892. if (dp_tx_limit_check(vdev))
  893. return NULL;
  894. /* Allocate software Tx descriptor */
  895. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  896. if (!tx_desc) {
  897. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  898. return NULL;
  899. }
  900. dp_tx_outstanding_inc(pdev);
  901. /* Initialize the SW tx descriptor */
  902. tx_desc->nbuf = nbuf;
  903. tx_desc->frm_type = msdu_info->frm_type;
  904. tx_desc->tx_encap_type = vdev->tx_encap_type;
  905. tx_desc->vdev_id = vdev->vdev_id;
  906. tx_desc->pdev = pdev;
  907. tx_desc->pkt_offset = 0;
  908. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  909. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  910. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  911. /* Handle scattered frames - TSO/SG/ME */
  912. /* Allocate and prepare an extension descriptor for scattered frames */
  913. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  914. if (!msdu_ext_desc) {
  915. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  916. "%s Tx Extension Descriptor Alloc Fail",
  917. __func__);
  918. goto failure;
  919. }
  920. #if TQM_BYPASS_WAR
  921. /* Temporary WAR due to TQM VP issues */
  922. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  923. qdf_atomic_inc(&soc->num_tx_exception);
  924. #endif
  925. if (qdf_unlikely(msdu_info->exception_fw))
  926. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  927. tx_desc->msdu_ext_desc = msdu_ext_desc;
  928. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  929. tx_desc->dma_addr = msdu_ext_desc->paddr;
  930. if (msdu_ext_desc->flags & DP_TX_EXT_DESC_FLAG_METADATA_VALID)
  931. tx_desc->length = HAL_TX_EXT_DESC_WITH_META_DATA;
  932. else
  933. tx_desc->length = HAL_TX_EXTENSION_DESC_LEN_BYTES;
  934. return tx_desc;
  935. failure:
  936. dp_tx_desc_release(tx_desc, desc_pool_id);
  937. return NULL;
  938. }
  939. /**
  940. * dp_tx_prepare_raw() - Prepare RAW packet TX
  941. * @vdev: DP vdev handle
  942. * @nbuf: buffer pointer
  943. * @seg_info: Pointer to Segment info Descriptor to be prepared
  944. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  945. * descriptor
  946. *
  947. * Return:
  948. */
  949. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  950. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  951. {
  952. qdf_nbuf_t curr_nbuf = NULL;
  953. uint16_t total_len = 0;
  954. qdf_dma_addr_t paddr;
  955. int32_t i;
  956. int32_t mapped_buf_num = 0;
  957. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  958. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  959. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  960. /* Continue only if frames are of DATA type */
  961. if (!DP_FRAME_IS_DATA(qos_wh)) {
  962. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  963. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  964. "Pkt. recd is of not data type");
  965. goto error;
  966. }
  967. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  968. if (vdev->raw_mode_war &&
  969. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  970. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  971. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  972. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  973. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  974. /*
  975. * Number of nbuf's must not exceed the size of the frags
  976. * array in seg_info.
  977. */
  978. if (i >= DP_TX_MAX_NUM_FRAGS) {
  979. dp_err_rl("nbuf cnt exceeds the max number of segs");
  980. DP_STATS_INC(vdev, tx_i.raw.num_frags_overflow_err, 1);
  981. goto error;
  982. }
  983. if (QDF_STATUS_SUCCESS !=
  984. qdf_nbuf_map_nbytes_single(vdev->osdev,
  985. curr_nbuf,
  986. QDF_DMA_TO_DEVICE,
  987. curr_nbuf->len)) {
  988. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  989. "%s dma map error ", __func__);
  990. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  991. goto error;
  992. }
  993. /* Update the count of mapped nbuf's */
  994. mapped_buf_num++;
  995. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  996. seg_info->frags[i].paddr_lo = paddr;
  997. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  998. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  999. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  1000. total_len += qdf_nbuf_len(curr_nbuf);
  1001. }
  1002. seg_info->frag_cnt = i;
  1003. seg_info->total_len = total_len;
  1004. seg_info->next = NULL;
  1005. sg_info->curr_seg = seg_info;
  1006. msdu_info->frm_type = dp_tx_frm_raw;
  1007. msdu_info->num_seg = 1;
  1008. return nbuf;
  1009. error:
  1010. i = 0;
  1011. while (nbuf) {
  1012. curr_nbuf = nbuf;
  1013. if (i < mapped_buf_num) {
  1014. qdf_nbuf_unmap_nbytes_single(vdev->osdev, curr_nbuf,
  1015. QDF_DMA_TO_DEVICE,
  1016. curr_nbuf->len);
  1017. i++;
  1018. }
  1019. nbuf = qdf_nbuf_next(nbuf);
  1020. qdf_nbuf_free(curr_nbuf);
  1021. }
  1022. return NULL;
  1023. }
  1024. /**
  1025. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  1026. * @soc: DP soc handle
  1027. * @nbuf: Buffer pointer
  1028. *
  1029. * unmap the chain of nbufs that belong to this RAW frame.
  1030. *
  1031. * Return: None
  1032. */
  1033. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  1034. qdf_nbuf_t nbuf)
  1035. {
  1036. qdf_nbuf_t cur_nbuf = nbuf;
  1037. do {
  1038. qdf_nbuf_unmap_nbytes_single(soc->osdev, cur_nbuf,
  1039. QDF_DMA_TO_DEVICE,
  1040. cur_nbuf->len);
  1041. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  1042. } while (cur_nbuf);
  1043. }
  1044. #ifdef VDEV_PEER_PROTOCOL_COUNT
  1045. #define dp_vdev_peer_stats_update_protocol_cnt_tx(vdev_hdl, nbuf) \
  1046. { \
  1047. qdf_nbuf_t nbuf_local; \
  1048. struct dp_vdev *vdev_local = vdev_hdl; \
  1049. do { \
  1050. if (qdf_likely(!((vdev_local)->peer_protocol_count_track))) \
  1051. break; \
  1052. nbuf_local = nbuf; \
  1053. if (qdf_unlikely(((vdev_local)->tx_encap_type) == \
  1054. htt_cmn_pkt_type_raw)) \
  1055. break; \
  1056. else if (qdf_unlikely(qdf_nbuf_is_nonlinear((nbuf_local)))) \
  1057. break; \
  1058. else if (qdf_nbuf_is_tso((nbuf_local))) \
  1059. break; \
  1060. dp_vdev_peer_stats_update_protocol_cnt((vdev_local), \
  1061. (nbuf_local), \
  1062. NULL, 1, 0); \
  1063. } while (0); \
  1064. }
  1065. #else
  1066. #define dp_vdev_peer_stats_update_protocol_cnt_tx(vdev_hdl, skb)
  1067. #endif
  1068. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  1069. /**
  1070. * dp_tx_update_stats() - Update soc level tx stats
  1071. * @soc: DP soc handle
  1072. * @nbuf: packet being transmitted
  1073. *
  1074. * Returns: none
  1075. */
  1076. static inline void dp_tx_update_stats(struct dp_soc *soc,
  1077. qdf_nbuf_t nbuf)
  1078. {
  1079. DP_STATS_INC_PKT(soc, tx.egress, 1, qdf_nbuf_len(nbuf));
  1080. }
  1081. /**
  1082. * dp_tx_attempt_coalescing() - Check and attempt TCL register write coalescing
  1083. * @soc: Datapath soc handle
  1084. * @tx_desc: tx packet descriptor
  1085. * @tid: TID for pkt transmission
  1086. *
  1087. * Returns: 1, if coalescing is to be done
  1088. * 0, if coalescing is not to be done
  1089. */
  1090. static inline int
  1091. dp_tx_attempt_coalescing(struct dp_soc *soc, struct dp_vdev *vdev,
  1092. struct dp_tx_desc_s *tx_desc,
  1093. uint8_t tid)
  1094. {
  1095. struct dp_swlm *swlm = &soc->swlm;
  1096. union swlm_data swlm_query_data;
  1097. struct dp_swlm_tcl_data tcl_data;
  1098. QDF_STATUS status;
  1099. int ret;
  1100. if (qdf_unlikely(!swlm->is_enabled))
  1101. return 0;
  1102. tcl_data.nbuf = tx_desc->nbuf;
  1103. tcl_data.tid = tid;
  1104. tcl_data.num_ll_connections = vdev->num_latency_critical_conn;
  1105. swlm_query_data.tcl_data = &tcl_data;
  1106. status = dp_swlm_tcl_pre_check(soc, &tcl_data);
  1107. if (QDF_IS_STATUS_ERROR(status)) {
  1108. dp_swlm_tcl_reset_session_data(soc);
  1109. DP_STATS_INC(swlm, tcl.coalesce_fail, 1);
  1110. return 0;
  1111. }
  1112. ret = dp_swlm_query_policy(soc, TCL_DATA, swlm_query_data);
  1113. if (ret) {
  1114. DP_STATS_INC(swlm, tcl.coalesce_success, 1);
  1115. } else {
  1116. DP_STATS_INC(swlm, tcl.coalesce_fail, 1);
  1117. }
  1118. return ret;
  1119. }
  1120. /**
  1121. * dp_tx_ring_access_end() - HAL ring access end for data transmission
  1122. * @soc: Datapath soc handle
  1123. * @hal_ring_hdl: HAL ring handle
  1124. * @coalesce: Coalesce the current write or not
  1125. *
  1126. * Returns: none
  1127. */
  1128. static inline void
  1129. dp_tx_ring_access_end(struct dp_soc *soc, hal_ring_handle_t hal_ring_hdl,
  1130. int coalesce)
  1131. {
  1132. if (coalesce)
  1133. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1134. else
  1135. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1136. }
  1137. #else
  1138. static inline void dp_tx_update_stats(struct dp_soc *soc,
  1139. qdf_nbuf_t nbuf)
  1140. {
  1141. }
  1142. static inline int
  1143. dp_tx_attempt_coalescing(struct dp_soc *soc, struct dp_vdev *vdev,
  1144. struct dp_tx_desc_s *tx_desc,
  1145. uint8_t tid)
  1146. {
  1147. return 0;
  1148. }
  1149. static inline void
  1150. dp_tx_ring_access_end(struct dp_soc *soc, hal_ring_handle_t hal_ring_hdl,
  1151. int coalesce)
  1152. {
  1153. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1154. }
  1155. #endif
  1156. /**
  1157. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  1158. * @soc: DP Soc Handle
  1159. * @vdev: DP vdev handle
  1160. * @tx_desc: Tx Descriptor Handle
  1161. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1162. * @fw_metadata: Metadata to send to Target Firmware along with frame
  1163. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  1164. * @tx_exc_metadata: Handle that holds exception path meta data
  1165. *
  1166. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  1167. * from software Tx descriptor
  1168. *
  1169. * Return: QDF_STATUS_SUCCESS: success
  1170. * QDF_STATUS_E_RESOURCES: Error return
  1171. */
  1172. static QDF_STATUS
  1173. dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  1174. struct dp_tx_desc_s *tx_desc, uint16_t fw_metadata,
  1175. struct cdp_tx_exception_metadata *tx_exc_metadata,
  1176. struct dp_tx_msdu_info_s *msdu_info)
  1177. {
  1178. void *hal_tx_desc;
  1179. uint32_t *hal_tx_desc_cached;
  1180. int coalesce = 0;
  1181. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1182. uint8_t ring_id = tx_q->ring_id & DP_TX_QUEUE_MASK;
  1183. uint8_t tid = msdu_info->tid;
  1184. /*
  1185. * Setting it initialization statically here to avoid
  1186. * a memset call jump with qdf_mem_set call
  1187. */
  1188. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES] = { 0 };
  1189. enum cdp_sec_type sec_type = ((tx_exc_metadata &&
  1190. tx_exc_metadata->sec_type != CDP_INVALID_SEC_TYPE) ?
  1191. tx_exc_metadata->sec_type : vdev->sec_type);
  1192. /* Return Buffer Manager ID */
  1193. uint8_t bm_id = dp_tx_get_rbm_id(soc, ring_id);
  1194. hal_ring_handle_t hal_ring_hdl = NULL;
  1195. QDF_STATUS status = QDF_STATUS_E_RESOURCES;
  1196. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id)) {
  1197. dp_err_rl("Invalid tx desc id:%d", tx_desc->id);
  1198. return QDF_STATUS_E_RESOURCES;
  1199. }
  1200. hal_tx_desc_cached = (void *) cached_desc;
  1201. hal_tx_desc_set_buf_addr(soc->hal_soc, hal_tx_desc_cached,
  1202. tx_desc->dma_addr, bm_id, tx_desc->id,
  1203. (tx_desc->flags & DP_TX_DESC_FLAG_FRAG));
  1204. hal_tx_desc_set_lmac_id(soc->hal_soc, hal_tx_desc_cached,
  1205. vdev->lmac_id);
  1206. hal_tx_desc_set_search_type(soc->hal_soc, hal_tx_desc_cached,
  1207. vdev->search_type);
  1208. hal_tx_desc_set_search_index(soc->hal_soc, hal_tx_desc_cached,
  1209. vdev->bss_ast_idx);
  1210. hal_tx_desc_set_dscp_tid_table_id(soc->hal_soc, hal_tx_desc_cached,
  1211. vdev->dscp_tid_map_id);
  1212. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  1213. sec_type_map[sec_type]);
  1214. hal_tx_desc_set_cache_set_num(soc->hal_soc, hal_tx_desc_cached,
  1215. (vdev->bss_ast_hash & 0xF));
  1216. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  1217. hal_tx_desc_set_buf_length(hal_tx_desc_cached, tx_desc->length);
  1218. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  1219. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  1220. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  1221. vdev->hal_desc_addr_search_flags);
  1222. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  1223. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  1224. /* verify checksum offload configuration*/
  1225. if (vdev->csum_enabled &&
  1226. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  1227. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  1228. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  1229. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  1230. }
  1231. if (tid != HTT_TX_EXT_TID_INVALID)
  1232. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  1233. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  1234. hal_tx_desc_set_mesh_en(soc->hal_soc, hal_tx_desc_cached, 1);
  1235. if (qdf_unlikely(vdev->pdev->delay_stats_flag) ||
  1236. qdf_unlikely(wlan_cfg_is_peer_ext_stats_enabled(
  1237. soc->wlan_cfg_ctx)))
  1238. tx_desc->timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  1239. dp_verbose_debug("length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  1240. tx_desc->length,
  1241. (tx_desc->flags & DP_TX_DESC_FLAG_FRAG),
  1242. (uint64_t)tx_desc->dma_addr, tx_desc->pkt_offset,
  1243. tx_desc->id);
  1244. hal_ring_hdl = dp_tx_get_hal_ring_hdl(soc, ring_id);
  1245. if (qdf_unlikely(dp_tx_hal_ring_access_start(soc, hal_ring_hdl))) {
  1246. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1247. "%s %d : HAL RING Access Failed -- %pK",
  1248. __func__, __LINE__, hal_ring_hdl);
  1249. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  1250. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  1251. return status;
  1252. }
  1253. /* Sync cached descriptor with HW */
  1254. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_ring_hdl);
  1255. if (qdf_unlikely(!hal_tx_desc)) {
  1256. dp_verbose_debug("TCL ring full ring_id:%d", ring_id);
  1257. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  1258. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  1259. goto ring_access_fail;
  1260. }
  1261. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  1262. dp_vdev_peer_stats_update_protocol_cnt_tx(vdev, tx_desc->nbuf);
  1263. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  1264. coalesce = dp_tx_attempt_coalescing(soc, vdev, tx_desc, tid);
  1265. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, tx_desc->length);
  1266. dp_tx_update_stats(soc, tx_desc->nbuf);
  1267. status = QDF_STATUS_SUCCESS;
  1268. ring_access_fail:
  1269. if (hif_pm_runtime_get(soc->hif_handle,
  1270. RTPM_ID_DW_TX_HW_ENQUEUE) == 0) {
  1271. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1272. hif_pm_runtime_put(soc->hif_handle,
  1273. RTPM_ID_DW_TX_HW_ENQUEUE);
  1274. } else {
  1275. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1276. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1277. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1278. }
  1279. return status;
  1280. }
  1281. /**
  1282. * dp_cce_classify() - Classify the frame based on CCE rules
  1283. * @vdev: DP vdev handle
  1284. * @nbuf: skb
  1285. *
  1286. * Classify frames based on CCE rules
  1287. * Return: bool( true if classified,
  1288. * else false)
  1289. */
  1290. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  1291. {
  1292. qdf_ether_header_t *eh = NULL;
  1293. uint16_t ether_type;
  1294. qdf_llc_t *llcHdr;
  1295. qdf_nbuf_t nbuf_clone = NULL;
  1296. qdf_dot3_qosframe_t *qos_wh = NULL;
  1297. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1298. /*
  1299. * In case of mesh packets or hlos tid override enabled,
  1300. * don't do any classification
  1301. */
  1302. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1303. & DP_TX_SKIP_CCE_CLASSIFY))
  1304. return false;
  1305. }
  1306. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1307. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1308. ether_type = eh->ether_type;
  1309. llcHdr = (qdf_llc_t *)(nbuf->data +
  1310. sizeof(qdf_ether_header_t));
  1311. } else {
  1312. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1313. /* For encrypted packets don't do any classification */
  1314. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  1315. return false;
  1316. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  1317. if (qdf_unlikely(
  1318. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  1319. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  1320. ether_type = *(uint16_t *)(nbuf->data
  1321. + QDF_IEEE80211_4ADDR_HDR_LEN
  1322. + sizeof(qdf_llc_t)
  1323. - sizeof(ether_type));
  1324. llcHdr = (qdf_llc_t *)(nbuf->data +
  1325. QDF_IEEE80211_4ADDR_HDR_LEN);
  1326. } else {
  1327. ether_type = *(uint16_t *)(nbuf->data
  1328. + QDF_IEEE80211_3ADDR_HDR_LEN
  1329. + sizeof(qdf_llc_t)
  1330. - sizeof(ether_type));
  1331. llcHdr = (qdf_llc_t *)(nbuf->data +
  1332. QDF_IEEE80211_3ADDR_HDR_LEN);
  1333. }
  1334. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  1335. && (ether_type ==
  1336. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  1337. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  1338. return true;
  1339. }
  1340. }
  1341. return false;
  1342. }
  1343. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  1344. ether_type = *(uint16_t *)(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1345. sizeof(*llcHdr));
  1346. nbuf_clone = qdf_nbuf_clone(nbuf);
  1347. if (qdf_unlikely(nbuf_clone)) {
  1348. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  1349. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1350. qdf_nbuf_pull_head(nbuf_clone,
  1351. sizeof(qdf_net_vlanhdr_t));
  1352. }
  1353. }
  1354. } else {
  1355. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1356. nbuf_clone = qdf_nbuf_clone(nbuf);
  1357. if (qdf_unlikely(nbuf_clone)) {
  1358. qdf_nbuf_pull_head(nbuf_clone,
  1359. sizeof(qdf_net_vlanhdr_t));
  1360. }
  1361. }
  1362. }
  1363. if (qdf_unlikely(nbuf_clone))
  1364. nbuf = nbuf_clone;
  1365. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  1366. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  1367. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  1368. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  1369. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  1370. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  1371. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  1372. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  1373. if (qdf_unlikely(nbuf_clone))
  1374. qdf_nbuf_free(nbuf_clone);
  1375. return true;
  1376. }
  1377. if (qdf_unlikely(nbuf_clone))
  1378. qdf_nbuf_free(nbuf_clone);
  1379. return false;
  1380. }
  1381. /**
  1382. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1383. * @vdev: DP vdev handle
  1384. * @nbuf: skb
  1385. *
  1386. * Extract the DSCP or PCP information from frame and map into TID value.
  1387. *
  1388. * Return: void
  1389. */
  1390. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1391. struct dp_tx_msdu_info_s *msdu_info)
  1392. {
  1393. uint8_t tos = 0, dscp_tid_override = 0;
  1394. uint8_t *hdr_ptr, *L3datap;
  1395. uint8_t is_mcast = 0;
  1396. qdf_ether_header_t *eh = NULL;
  1397. qdf_ethervlan_header_t *evh = NULL;
  1398. uint16_t ether_type;
  1399. qdf_llc_t *llcHdr;
  1400. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1401. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1402. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1403. eh = (qdf_ether_header_t *)nbuf->data;
  1404. hdr_ptr = (uint8_t *)(eh->ether_dhost);
  1405. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1406. } else {
  1407. qdf_dot3_qosframe_t *qos_wh =
  1408. (qdf_dot3_qosframe_t *) nbuf->data;
  1409. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1410. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1411. return;
  1412. }
  1413. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1414. ether_type = eh->ether_type;
  1415. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1416. /*
  1417. * Check if packet is dot3 or eth2 type.
  1418. */
  1419. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1420. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1421. sizeof(*llcHdr));
  1422. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1423. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1424. sizeof(*llcHdr);
  1425. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1426. + sizeof(*llcHdr) +
  1427. sizeof(qdf_net_vlanhdr_t));
  1428. } else {
  1429. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1430. sizeof(*llcHdr);
  1431. }
  1432. } else {
  1433. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1434. evh = (qdf_ethervlan_header_t *) eh;
  1435. ether_type = evh->ether_type;
  1436. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1437. }
  1438. }
  1439. /*
  1440. * Find priority from IP TOS DSCP field
  1441. */
  1442. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1443. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1444. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1445. /* Only for unicast frames */
  1446. if (!is_mcast) {
  1447. /* send it on VO queue */
  1448. msdu_info->tid = DP_VO_TID;
  1449. }
  1450. } else {
  1451. /*
  1452. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1453. * from TOS byte.
  1454. */
  1455. tos = ip->ip_tos;
  1456. dscp_tid_override = 1;
  1457. }
  1458. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1459. /* TODO
  1460. * use flowlabel
  1461. *igmpmld cases to be handled in phase 2
  1462. */
  1463. unsigned long ver_pri_flowlabel;
  1464. unsigned long pri;
  1465. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1466. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1467. DP_IPV6_PRIORITY_SHIFT;
  1468. tos = pri;
  1469. dscp_tid_override = 1;
  1470. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1471. msdu_info->tid = DP_VO_TID;
  1472. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1473. /* Only for unicast frames */
  1474. if (!is_mcast) {
  1475. /* send ucast arp on VO queue */
  1476. msdu_info->tid = DP_VO_TID;
  1477. }
  1478. }
  1479. /*
  1480. * Assign all MCAST packets to BE
  1481. */
  1482. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1483. if (is_mcast) {
  1484. tos = 0;
  1485. dscp_tid_override = 1;
  1486. }
  1487. }
  1488. if (dscp_tid_override == 1) {
  1489. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1490. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1491. }
  1492. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1493. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1494. return;
  1495. }
  1496. /**
  1497. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1498. * @vdev: DP vdev handle
  1499. * @nbuf: skb
  1500. *
  1501. * Software based TID classification is required when more than 2 DSCP-TID
  1502. * mapping tables are needed.
  1503. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1504. *
  1505. * Return: void
  1506. */
  1507. static inline void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1508. struct dp_tx_msdu_info_s *msdu_info)
  1509. {
  1510. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1511. /*
  1512. * skip_sw_tid_classification flag will set in below cases-
  1513. * 1. vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map
  1514. * 2. hlos_tid_override enabled for vdev
  1515. * 3. mesh mode enabled for vdev
  1516. */
  1517. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1518. /* Update tid in msdu_info from skb priority */
  1519. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1520. & DP_TXRX_HLOS_TID_OVERRIDE_ENABLED)) {
  1521. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1522. return;
  1523. }
  1524. return;
  1525. }
  1526. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1527. }
  1528. #ifdef FEATURE_WLAN_TDLS
  1529. /**
  1530. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1531. * @soc: datapath SOC
  1532. * @vdev: datapath vdev
  1533. * @tx_desc: TX descriptor
  1534. *
  1535. * Return: None
  1536. */
  1537. static void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1538. struct dp_vdev *vdev,
  1539. struct dp_tx_desc_s *tx_desc)
  1540. {
  1541. if (vdev) {
  1542. if (vdev->is_tdls_frame) {
  1543. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1544. vdev->is_tdls_frame = false;
  1545. }
  1546. }
  1547. }
  1548. /**
  1549. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1550. * @soc: dp_soc handle
  1551. * @tx_desc: TX descriptor
  1552. * @vdev: datapath vdev handle
  1553. *
  1554. * Return: None
  1555. */
  1556. static void dp_non_std_tx_comp_free_buff(struct dp_soc *soc,
  1557. struct dp_tx_desc_s *tx_desc)
  1558. {
  1559. struct hal_tx_completion_status ts = {0};
  1560. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1561. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1562. DP_MOD_ID_TDLS);
  1563. if (qdf_unlikely(!vdev)) {
  1564. dp_err_rl("vdev is null!");
  1565. goto error;
  1566. }
  1567. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  1568. if (vdev->tx_non_std_data_callback.func) {
  1569. qdf_nbuf_set_next(nbuf, NULL);
  1570. vdev->tx_non_std_data_callback.func(
  1571. vdev->tx_non_std_data_callback.ctxt,
  1572. nbuf, ts.status);
  1573. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1574. return;
  1575. } else {
  1576. dp_err_rl("callback func is null");
  1577. }
  1578. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1579. error:
  1580. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1581. qdf_nbuf_free(nbuf);
  1582. }
  1583. /**
  1584. * dp_tx_msdu_single_map() - do nbuf map
  1585. * @vdev: DP vdev handle
  1586. * @tx_desc: DP TX descriptor pointer
  1587. * @nbuf: skb pointer
  1588. *
  1589. * For TDLS frame, use qdf_nbuf_map_single() to align with the unmap
  1590. * operation done in other component.
  1591. *
  1592. * Return: QDF_STATUS
  1593. */
  1594. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1595. struct dp_tx_desc_s *tx_desc,
  1596. qdf_nbuf_t nbuf)
  1597. {
  1598. if (qdf_likely(!(tx_desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)))
  1599. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1600. nbuf,
  1601. QDF_DMA_TO_DEVICE,
  1602. nbuf->len);
  1603. else
  1604. return qdf_nbuf_map_single(vdev->osdev, nbuf,
  1605. QDF_DMA_TO_DEVICE);
  1606. }
  1607. #else
  1608. static inline void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1609. struct dp_vdev *vdev,
  1610. struct dp_tx_desc_s *tx_desc)
  1611. {
  1612. }
  1613. static inline void dp_non_std_tx_comp_free_buff(struct dp_soc *soc,
  1614. struct dp_tx_desc_s *tx_desc)
  1615. {
  1616. }
  1617. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1618. struct dp_tx_desc_s *tx_desc,
  1619. qdf_nbuf_t nbuf)
  1620. {
  1621. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1622. nbuf,
  1623. QDF_DMA_TO_DEVICE,
  1624. nbuf->len);
  1625. }
  1626. #endif
  1627. #ifdef MESH_MODE_SUPPORT
  1628. /**
  1629. * dp_tx_update_mesh_flags() - Update descriptor flags for mesh VAP
  1630. * @soc: datapath SOC
  1631. * @vdev: datapath vdev
  1632. * @tx_desc: TX descriptor
  1633. *
  1634. * Return: None
  1635. */
  1636. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1637. struct dp_vdev *vdev,
  1638. struct dp_tx_desc_s *tx_desc)
  1639. {
  1640. if (qdf_unlikely(vdev->mesh_vdev))
  1641. tx_desc->flags |= DP_TX_DESC_FLAG_MESH_MODE;
  1642. }
  1643. /**
  1644. * dp_mesh_tx_comp_free_buff() - Free the mesh tx packet buffer
  1645. * @soc: dp_soc handle
  1646. * @tx_desc: TX descriptor
  1647. * @vdev: datapath vdev handle
  1648. *
  1649. * Return: None
  1650. */
  1651. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1652. struct dp_tx_desc_s *tx_desc)
  1653. {
  1654. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1655. struct dp_vdev *vdev = NULL;
  1656. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  1657. qdf_nbuf_free(nbuf);
  1658. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  1659. } else {
  1660. vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1661. DP_MOD_ID_MESH);
  1662. if (vdev && vdev->osif_tx_free_ext)
  1663. vdev->osif_tx_free_ext((nbuf));
  1664. else
  1665. qdf_nbuf_free(nbuf);
  1666. if (vdev)
  1667. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  1668. }
  1669. }
  1670. #else
  1671. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1672. struct dp_vdev *vdev,
  1673. struct dp_tx_desc_s *tx_desc)
  1674. {
  1675. }
  1676. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1677. struct dp_tx_desc_s *tx_desc)
  1678. {
  1679. }
  1680. #endif
  1681. /**
  1682. * dp_tx_frame_is_drop() - checks if the packet is loopback
  1683. * @vdev: DP vdev handle
  1684. * @nbuf: skb
  1685. *
  1686. * Return: 1 if frame needs to be dropped else 0
  1687. */
  1688. int dp_tx_frame_is_drop(struct dp_vdev *vdev, uint8_t *srcmac, uint8_t *dstmac)
  1689. {
  1690. struct dp_pdev *pdev = NULL;
  1691. struct dp_ast_entry *src_ast_entry = NULL;
  1692. struct dp_ast_entry *dst_ast_entry = NULL;
  1693. struct dp_soc *soc = NULL;
  1694. qdf_assert(vdev);
  1695. pdev = vdev->pdev;
  1696. qdf_assert(pdev);
  1697. soc = pdev->soc;
  1698. dst_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1699. (soc, dstmac, vdev->pdev->pdev_id);
  1700. src_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1701. (soc, srcmac, vdev->pdev->pdev_id);
  1702. if (dst_ast_entry && src_ast_entry) {
  1703. if (dst_ast_entry->peer_id ==
  1704. src_ast_entry->peer_id)
  1705. return 1;
  1706. }
  1707. return 0;
  1708. }
  1709. /**
  1710. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1711. * @vdev: DP vdev handle
  1712. * @nbuf: skb
  1713. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1714. * @meta_data: Metadata to the fw
  1715. * @tx_q: Tx queue to be used for this Tx frame
  1716. * @peer_id: peer_id of the peer in case of NAWDS frames
  1717. * @tx_exc_metadata: Handle that holds exception path metadata
  1718. *
  1719. * Return: NULL on success,
  1720. * nbuf when it fails to send
  1721. */
  1722. qdf_nbuf_t
  1723. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1724. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1725. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1726. {
  1727. struct dp_pdev *pdev = vdev->pdev;
  1728. struct dp_soc *soc = pdev->soc;
  1729. struct dp_tx_desc_s *tx_desc;
  1730. QDF_STATUS status;
  1731. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1732. uint16_t htt_tcl_metadata = 0;
  1733. enum cdp_tx_sw_drop drop_code = TX_MAX_DROP;
  1734. uint8_t tid = msdu_info->tid;
  1735. struct cdp_tid_tx_stats *tid_stats = NULL;
  1736. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1737. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1738. msdu_info, tx_exc_metadata);
  1739. if (!tx_desc) {
  1740. dp_err_rl("Tx_desc prepare Fail vdev %pK queue %d",
  1741. vdev, tx_q->desc_pool_id);
  1742. drop_code = TX_DESC_ERR;
  1743. goto fail_return;
  1744. }
  1745. if (qdf_unlikely(soc->cce_disable)) {
  1746. if (dp_cce_classify(vdev, nbuf) == true) {
  1747. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1748. tid = DP_VO_TID;
  1749. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1750. }
  1751. }
  1752. dp_tx_update_tdls_flags(soc, vdev, tx_desc);
  1753. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1754. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1755. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1756. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1757. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1758. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1759. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1760. peer_id);
  1761. } else
  1762. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1763. if (msdu_info->exception_fw)
  1764. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1765. dp_tx_desc_update_fast_comp_flag(soc, tx_desc,
  1766. !pdev->enhanced_stats_en);
  1767. dp_tx_update_mesh_flags(soc, vdev, tx_desc);
  1768. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  1769. dp_tx_msdu_single_map(vdev, tx_desc, nbuf))) {
  1770. /* Handle failure */
  1771. dp_err("qdf_nbuf_map failed");
  1772. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  1773. drop_code = TX_DMA_MAP_ERR;
  1774. goto release_desc;
  1775. }
  1776. tx_desc->dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  1777. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1778. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, htt_tcl_metadata,
  1779. tx_exc_metadata, msdu_info);
  1780. if (status != QDF_STATUS_SUCCESS) {
  1781. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1782. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1783. __func__, tx_desc, tx_q->ring_id);
  1784. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  1785. QDF_DMA_TO_DEVICE,
  1786. nbuf->len);
  1787. drop_code = TX_HW_ENQUEUE;
  1788. goto release_desc;
  1789. }
  1790. return NULL;
  1791. release_desc:
  1792. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1793. fail_return:
  1794. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1795. tid_stats = &pdev->stats.tid_stats.
  1796. tid_tx_stats[tx_q->ring_id][tid];
  1797. tid_stats->swdrop_cnt[drop_code]++;
  1798. return nbuf;
  1799. }
  1800. /**
  1801. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  1802. * @soc: Soc handle
  1803. * @desc: software Tx descriptor to be processed
  1804. *
  1805. * Return: none
  1806. */
  1807. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  1808. struct dp_tx_desc_s *desc)
  1809. {
  1810. qdf_nbuf_t nbuf = desc->nbuf;
  1811. /* nbuf already freed in vdev detach path */
  1812. if (!nbuf)
  1813. return;
  1814. /* If it is TDLS mgmt, don't unmap or free the frame */
  1815. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  1816. return dp_non_std_tx_comp_free_buff(soc, desc);
  1817. /* 0 : MSDU buffer, 1 : MLE */
  1818. if (desc->msdu_ext_desc) {
  1819. /* TSO free */
  1820. if (hal_tx_ext_desc_get_tso_enable(
  1821. desc->msdu_ext_desc->vaddr)) {
  1822. /* unmap eash TSO seg before free the nbuf */
  1823. dp_tx_tso_unmap_segment(soc, desc->tso_desc,
  1824. desc->tso_num_desc);
  1825. qdf_nbuf_free(nbuf);
  1826. return;
  1827. }
  1828. }
  1829. /* If it's ME frame, dont unmap the cloned nbuf's */
  1830. if ((desc->flags & DP_TX_DESC_FLAG_ME) && qdf_nbuf_is_cloned(nbuf))
  1831. goto nbuf_free;
  1832. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf,
  1833. QDF_DMA_TO_DEVICE, nbuf->len);
  1834. if (desc->flags & DP_TX_DESC_FLAG_MESH_MODE)
  1835. return dp_mesh_tx_comp_free_buff(soc, desc);
  1836. nbuf_free:
  1837. qdf_nbuf_free(nbuf);
  1838. }
  1839. /**
  1840. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1841. * @vdev: DP vdev handle
  1842. * @nbuf: skb
  1843. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1844. *
  1845. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1846. *
  1847. * Return: NULL on success,
  1848. * nbuf when it fails to send
  1849. */
  1850. #if QDF_LOCK_STATS
  1851. noinline
  1852. #else
  1853. #endif
  1854. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1855. struct dp_tx_msdu_info_s *msdu_info)
  1856. {
  1857. uint32_t i;
  1858. struct dp_pdev *pdev = vdev->pdev;
  1859. struct dp_soc *soc = pdev->soc;
  1860. struct dp_tx_desc_s *tx_desc;
  1861. bool is_cce_classified = false;
  1862. QDF_STATUS status;
  1863. uint16_t htt_tcl_metadata = 0;
  1864. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1865. struct cdp_tid_tx_stats *tid_stats = NULL;
  1866. uint8_t prep_desc_fail = 0, hw_enq_fail = 0;
  1867. if (qdf_unlikely(soc->cce_disable)) {
  1868. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1869. if (is_cce_classified) {
  1870. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1871. msdu_info->tid = DP_VO_TID;
  1872. }
  1873. }
  1874. if (msdu_info->frm_type == dp_tx_frm_me)
  1875. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1876. i = 0;
  1877. /* Print statement to track i and num_seg */
  1878. /*
  1879. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1880. * descriptors using information in msdu_info
  1881. */
  1882. while (i < msdu_info->num_seg) {
  1883. /*
  1884. * Setup Tx descriptor for an MSDU, and MSDU extension
  1885. * descriptor
  1886. */
  1887. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1888. tx_q->desc_pool_id);
  1889. if (!tx_desc) {
  1890. if (msdu_info->frm_type == dp_tx_frm_me) {
  1891. prep_desc_fail++;
  1892. dp_tx_me_free_buf(pdev,
  1893. (void *)(msdu_info->u.sg_info
  1894. .curr_seg->frags[0].vaddr));
  1895. if (prep_desc_fail == msdu_info->num_seg) {
  1896. /*
  1897. * Unmap is needed only if descriptor
  1898. * preparation failed for all segments.
  1899. */
  1900. qdf_nbuf_unmap(soc->osdev,
  1901. msdu_info->u.sg_info.
  1902. curr_seg->nbuf,
  1903. QDF_DMA_TO_DEVICE);
  1904. }
  1905. /*
  1906. * Free the nbuf for the current segment
  1907. * and make it point to the next in the list.
  1908. * For me, there are as many segments as there
  1909. * are no of clients.
  1910. */
  1911. qdf_nbuf_free(msdu_info->u.sg_info
  1912. .curr_seg->nbuf);
  1913. if (msdu_info->u.sg_info.curr_seg->next) {
  1914. msdu_info->u.sg_info.curr_seg =
  1915. msdu_info->u.sg_info
  1916. .curr_seg->next;
  1917. nbuf = msdu_info->u.sg_info
  1918. .curr_seg->nbuf;
  1919. }
  1920. i++;
  1921. continue;
  1922. }
  1923. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1924. dp_tx_tso_unmap_segment(soc,
  1925. msdu_info->u.tso_info.
  1926. curr_seg,
  1927. msdu_info->u.tso_info.
  1928. tso_num_seg_list);
  1929. if (msdu_info->u.tso_info.curr_seg->next) {
  1930. msdu_info->u.tso_info.curr_seg =
  1931. msdu_info->u.tso_info.curr_seg->next;
  1932. i++;
  1933. continue;
  1934. }
  1935. }
  1936. goto done;
  1937. }
  1938. if (msdu_info->frm_type == dp_tx_frm_me) {
  1939. tx_desc->me_buffer =
  1940. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1941. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1942. }
  1943. if (is_cce_classified)
  1944. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1945. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1946. if (msdu_info->exception_fw) {
  1947. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1948. }
  1949. /*
  1950. * For frames with multiple segments (TSO, ME), jump to next
  1951. * segment.
  1952. */
  1953. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1954. if (msdu_info->u.tso_info.curr_seg->next) {
  1955. msdu_info->u.tso_info.curr_seg =
  1956. msdu_info->u.tso_info.curr_seg->next;
  1957. /*
  1958. * If this is a jumbo nbuf, then increment the
  1959. * number of nbuf users for each additional
  1960. * segment of the msdu. This will ensure that
  1961. * the skb is freed only after receiving tx
  1962. * completion for all segments of an nbuf
  1963. */
  1964. qdf_nbuf_inc_users(nbuf);
  1965. /* Check with MCL if this is needed */
  1966. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf;
  1967. */
  1968. }
  1969. }
  1970. /*
  1971. * Enqueue the Tx MSDU descriptor to HW for transmit
  1972. */
  1973. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, htt_tcl_metadata,
  1974. NULL, msdu_info);
  1975. if (status != QDF_STATUS_SUCCESS) {
  1976. dp_info("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1977. tx_desc, tx_q->ring_id);
  1978. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1979. tid_stats = &pdev->stats.tid_stats.
  1980. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1981. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1982. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1983. if (msdu_info->frm_type == dp_tx_frm_me) {
  1984. hw_enq_fail++;
  1985. if (hw_enq_fail == msdu_info->num_seg) {
  1986. /*
  1987. * Unmap is needed only if enqueue
  1988. * failed for all segments.
  1989. */
  1990. qdf_nbuf_unmap(soc->osdev,
  1991. msdu_info->u.sg_info.
  1992. curr_seg->nbuf,
  1993. QDF_DMA_TO_DEVICE);
  1994. }
  1995. /*
  1996. * Free the nbuf for the current segment
  1997. * and make it point to the next in the list.
  1998. * For me, there are as many segments as there
  1999. * are no of clients.
  2000. */
  2001. qdf_nbuf_free(msdu_info->u.sg_info
  2002. .curr_seg->nbuf);
  2003. if (msdu_info->u.sg_info.curr_seg->next) {
  2004. msdu_info->u.sg_info.curr_seg =
  2005. msdu_info->u.sg_info
  2006. .curr_seg->next;
  2007. nbuf = msdu_info->u.sg_info
  2008. .curr_seg->nbuf;
  2009. }
  2010. i++;
  2011. continue;
  2012. }
  2013. /*
  2014. * For TSO frames, the nbuf users increment done for
  2015. * the current segment has to be reverted, since the
  2016. * hw enqueue for this segment failed
  2017. */
  2018. if (msdu_info->frm_type == dp_tx_frm_tso &&
  2019. msdu_info->u.tso_info.curr_seg) {
  2020. /*
  2021. * unmap and free current,
  2022. * retransmit remaining segments
  2023. */
  2024. dp_tx_comp_free_buf(soc, tx_desc);
  2025. i++;
  2026. continue;
  2027. }
  2028. goto done;
  2029. }
  2030. /*
  2031. * TODO
  2032. * if tso_info structure can be modified to have curr_seg
  2033. * as first element, following 2 blocks of code (for TSO and SG)
  2034. * can be combined into 1
  2035. */
  2036. /*
  2037. * For Multicast-Unicast converted packets,
  2038. * each converted frame (for a client) is represented as
  2039. * 1 segment
  2040. */
  2041. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  2042. (msdu_info->frm_type == dp_tx_frm_me)) {
  2043. if (msdu_info->u.sg_info.curr_seg->next) {
  2044. msdu_info->u.sg_info.curr_seg =
  2045. msdu_info->u.sg_info.curr_seg->next;
  2046. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2047. }
  2048. }
  2049. i++;
  2050. }
  2051. nbuf = NULL;
  2052. done:
  2053. return nbuf;
  2054. }
  2055. /**
  2056. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  2057. * for SG frames
  2058. * @vdev: DP vdev handle
  2059. * @nbuf: skb
  2060. * @seg_info: Pointer to Segment info Descriptor to be prepared
  2061. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2062. *
  2063. * Return: NULL on success,
  2064. * nbuf when it fails to send
  2065. */
  2066. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2067. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  2068. {
  2069. uint32_t cur_frag, nr_frags, i;
  2070. qdf_dma_addr_t paddr;
  2071. struct dp_tx_sg_info_s *sg_info;
  2072. sg_info = &msdu_info->u.sg_info;
  2073. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  2074. if (QDF_STATUS_SUCCESS !=
  2075. qdf_nbuf_map_nbytes_single(vdev->osdev, nbuf,
  2076. QDF_DMA_TO_DEVICE,
  2077. qdf_nbuf_headlen(nbuf))) {
  2078. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2079. "dma map error");
  2080. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2081. qdf_nbuf_free(nbuf);
  2082. return NULL;
  2083. }
  2084. paddr = qdf_nbuf_mapped_paddr_get(nbuf);
  2085. seg_info->frags[0].paddr_lo = paddr;
  2086. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  2087. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  2088. seg_info->frags[0].vaddr = (void *) nbuf;
  2089. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  2090. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  2091. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  2092. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2093. "frag dma map error");
  2094. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2095. goto map_err;
  2096. }
  2097. paddr = qdf_nbuf_get_tx_frag_paddr(nbuf);
  2098. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  2099. seg_info->frags[cur_frag + 1].paddr_hi =
  2100. ((uint64_t) paddr) >> 32;
  2101. seg_info->frags[cur_frag + 1].len =
  2102. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  2103. }
  2104. seg_info->frag_cnt = (cur_frag + 1);
  2105. seg_info->total_len = qdf_nbuf_len(nbuf);
  2106. seg_info->next = NULL;
  2107. sg_info->curr_seg = seg_info;
  2108. msdu_info->frm_type = dp_tx_frm_sg;
  2109. msdu_info->num_seg = 1;
  2110. return nbuf;
  2111. map_err:
  2112. /* restore paddr into nbuf before calling unmap */
  2113. qdf_nbuf_mapped_paddr_set(nbuf,
  2114. (qdf_dma_addr_t)(seg_info->frags[0].paddr_lo |
  2115. ((uint64_t)
  2116. seg_info->frags[0].paddr_hi) << 32));
  2117. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  2118. QDF_DMA_TO_DEVICE,
  2119. seg_info->frags[0].len);
  2120. for (i = 1; i <= cur_frag; i++) {
  2121. qdf_mem_unmap_page(vdev->osdev, (qdf_dma_addr_t)
  2122. (seg_info->frags[i].paddr_lo | ((uint64_t)
  2123. seg_info->frags[i].paddr_hi) << 32),
  2124. seg_info->frags[i].len,
  2125. QDF_DMA_TO_DEVICE);
  2126. }
  2127. qdf_nbuf_free(nbuf);
  2128. return NULL;
  2129. }
  2130. /**
  2131. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  2132. * @vdev: DP vdev handle
  2133. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2134. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  2135. *
  2136. * Return: NULL on failure,
  2137. * nbuf when extracted successfully
  2138. */
  2139. static
  2140. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  2141. struct dp_tx_msdu_info_s *msdu_info,
  2142. uint16_t ppdu_cookie)
  2143. {
  2144. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2145. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2146. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2147. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  2148. (msdu_info->meta_data[5], 1);
  2149. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  2150. (msdu_info->meta_data[5], 1);
  2151. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  2152. (msdu_info->meta_data[6], ppdu_cookie);
  2153. msdu_info->exception_fw = 1;
  2154. msdu_info->is_tx_sniffer = 1;
  2155. }
  2156. #ifdef MESH_MODE_SUPPORT
  2157. /**
  2158. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  2159. and prepare msdu_info for mesh frames.
  2160. * @vdev: DP vdev handle
  2161. * @nbuf: skb
  2162. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2163. *
  2164. * Return: NULL on failure,
  2165. * nbuf when extracted successfully
  2166. */
  2167. static
  2168. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2169. struct dp_tx_msdu_info_s *msdu_info)
  2170. {
  2171. struct meta_hdr_s *mhdr;
  2172. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2173. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2174. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2175. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  2176. msdu_info->exception_fw = 0;
  2177. goto remove_meta_hdr;
  2178. }
  2179. msdu_info->exception_fw = 1;
  2180. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2181. meta_data->host_tx_desc_pool = 1;
  2182. meta_data->update_peer_cache = 1;
  2183. meta_data->learning_frame = 1;
  2184. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  2185. meta_data->power = mhdr->power;
  2186. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  2187. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  2188. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  2189. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  2190. meta_data->dyn_bw = 1;
  2191. meta_data->valid_pwr = 1;
  2192. meta_data->valid_mcs_mask = 1;
  2193. meta_data->valid_nss_mask = 1;
  2194. meta_data->valid_preamble_type = 1;
  2195. meta_data->valid_retries = 1;
  2196. meta_data->valid_bw_info = 1;
  2197. }
  2198. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  2199. meta_data->encrypt_type = 0;
  2200. meta_data->valid_encrypt_type = 1;
  2201. meta_data->learning_frame = 0;
  2202. }
  2203. meta_data->valid_key_flags = 1;
  2204. meta_data->key_flags = (mhdr->keyix & 0x3);
  2205. remove_meta_hdr:
  2206. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2207. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2208. "qdf_nbuf_pull_head failed");
  2209. qdf_nbuf_free(nbuf);
  2210. return NULL;
  2211. }
  2212. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  2213. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2214. "%s , Meta hdr %0x %0x %0x %0x %0x %0x"
  2215. " tid %d to_fw %d",
  2216. __func__, msdu_info->meta_data[0],
  2217. msdu_info->meta_data[1],
  2218. msdu_info->meta_data[2],
  2219. msdu_info->meta_data[3],
  2220. msdu_info->meta_data[4],
  2221. msdu_info->meta_data[5],
  2222. msdu_info->tid, msdu_info->exception_fw);
  2223. return nbuf;
  2224. }
  2225. #else
  2226. static
  2227. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2228. struct dp_tx_msdu_info_s *msdu_info)
  2229. {
  2230. return nbuf;
  2231. }
  2232. #endif
  2233. /**
  2234. * dp_check_exc_metadata() - Checks if parameters are valid
  2235. * @tx_exc - holds all exception path parameters
  2236. *
  2237. * Returns true when all the parameters are valid else false
  2238. *
  2239. */
  2240. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  2241. {
  2242. bool invalid_tid = (tx_exc->tid > DP_MAX_TIDS && tx_exc->tid !=
  2243. HTT_INVALID_TID);
  2244. bool invalid_encap_type =
  2245. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  2246. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  2247. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  2248. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  2249. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  2250. tx_exc->ppdu_cookie == 0);
  2251. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  2252. invalid_cookie) {
  2253. return false;
  2254. }
  2255. return true;
  2256. }
  2257. #ifdef ATH_SUPPORT_IQUE
  2258. /**
  2259. * dp_tx_mcast_enhance() - Multicast enhancement on TX
  2260. * @vdev: vdev handle
  2261. * @nbuf: skb
  2262. *
  2263. * Return: true on success,
  2264. * false on failure
  2265. */
  2266. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2267. {
  2268. qdf_ether_header_t *eh;
  2269. /* Mcast to Ucast Conversion*/
  2270. if (qdf_likely(!vdev->mcast_enhancement_en))
  2271. return true;
  2272. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2273. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2274. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2275. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  2276. DP_STATS_INC_PKT(vdev, tx_i.mcast_en.mcast_pkt, 1,
  2277. qdf_nbuf_len(nbuf));
  2278. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  2279. QDF_STATUS_SUCCESS) {
  2280. return false;
  2281. }
  2282. if (qdf_unlikely(vdev->igmp_mcast_enhanc_en > 0)) {
  2283. if (dp_tx_prepare_send_igmp_me(vdev, nbuf) ==
  2284. QDF_STATUS_SUCCESS) {
  2285. return false;
  2286. }
  2287. }
  2288. }
  2289. return true;
  2290. }
  2291. #else
  2292. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2293. {
  2294. return true;
  2295. }
  2296. #endif
  2297. /**
  2298. * dp_tx_per_pkt_vdev_id_check() - vdev id check for frame
  2299. * @nbuf: qdf_nbuf_t
  2300. * @vdev: struct dp_vdev *
  2301. *
  2302. * Allow packet for processing only if it is for peer client which is
  2303. * connected with same vap. Drop packet if client is connected to
  2304. * different vap.
  2305. *
  2306. * Return: QDF_STATUS
  2307. */
  2308. static inline QDF_STATUS
  2309. dp_tx_per_pkt_vdev_id_check(qdf_nbuf_t nbuf, struct dp_vdev *vdev)
  2310. {
  2311. struct dp_ast_entry *dst_ast_entry = NULL;
  2312. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2313. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) ||
  2314. DP_FRAME_IS_BROADCAST((eh)->ether_dhost))
  2315. return QDF_STATUS_SUCCESS;
  2316. qdf_spin_lock_bh(&vdev->pdev->soc->ast_lock);
  2317. dst_ast_entry = dp_peer_ast_hash_find_by_vdevid(vdev->pdev->soc,
  2318. eh->ether_dhost,
  2319. vdev->vdev_id);
  2320. /* If there is no ast entry, return failure */
  2321. if (qdf_unlikely(!dst_ast_entry)) {
  2322. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2323. return QDF_STATUS_E_FAILURE;
  2324. }
  2325. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2326. return QDF_STATUS_SUCCESS;
  2327. }
  2328. /**
  2329. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  2330. * @soc: DP soc handle
  2331. * @vdev_id: id of DP vdev handle
  2332. * @nbuf: skb
  2333. * @tx_exc_metadata: Handle that holds exception path meta data
  2334. *
  2335. * Entry point for Core Tx layer (DP_TX) invoked from
  2336. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2337. *
  2338. * Return: NULL on success,
  2339. * nbuf when it fails to send
  2340. */
  2341. qdf_nbuf_t
  2342. dp_tx_send_exception(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2343. qdf_nbuf_t nbuf,
  2344. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2345. {
  2346. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2347. qdf_ether_header_t *eh = NULL;
  2348. struct dp_tx_msdu_info_s msdu_info;
  2349. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2350. DP_MOD_ID_TX_EXCEPTION);
  2351. if (qdf_unlikely(!vdev))
  2352. goto fail;
  2353. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2354. if (!tx_exc_metadata)
  2355. goto fail;
  2356. msdu_info.tid = tx_exc_metadata->tid;
  2357. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2358. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2359. QDF_MAC_ADDR_REF(nbuf->data));
  2360. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2361. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  2362. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2363. "Invalid parameters in exception path");
  2364. goto fail;
  2365. }
  2366. /* Basic sanity checks for unsupported packets */
  2367. /* MESH mode */
  2368. if (qdf_unlikely(vdev->mesh_vdev)) {
  2369. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2370. "Mesh mode is not supported in exception path");
  2371. goto fail;
  2372. }
  2373. /*
  2374. * Classify the frame and call corresponding
  2375. * "prepare" function which extracts the segment (TSO)
  2376. * and fragmentation information (for TSO , SG, ME, or Raw)
  2377. * into MSDU_INFO structure which is later used to fill
  2378. * SW and HW descriptors.
  2379. */
  2380. if (qdf_nbuf_is_tso(nbuf)) {
  2381. dp_verbose_debug("TSO frame %pK", vdev);
  2382. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2383. qdf_nbuf_len(nbuf));
  2384. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2385. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2386. qdf_nbuf_len(nbuf));
  2387. return nbuf;
  2388. }
  2389. goto send_multiple;
  2390. }
  2391. /* SG */
  2392. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2393. struct dp_tx_seg_info_s seg_info = {0};
  2394. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2395. if (!nbuf)
  2396. return NULL;
  2397. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2398. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2399. qdf_nbuf_len(nbuf));
  2400. goto send_multiple;
  2401. }
  2402. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  2403. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  2404. qdf_nbuf_len(nbuf));
  2405. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  2406. tx_exc_metadata->ppdu_cookie);
  2407. }
  2408. /*
  2409. * Get HW Queue to use for this frame.
  2410. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2411. * dedicated for data and 1 for command.
  2412. * "queue_id" maps to one hardware ring.
  2413. * With each ring, we also associate a unique Tx descriptor pool
  2414. * to minimize lock contention for these resources.
  2415. */
  2416. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2417. /*
  2418. * Check exception descriptors
  2419. */
  2420. if (dp_tx_exception_limit_check(vdev))
  2421. goto fail;
  2422. /* Single linear frame */
  2423. /*
  2424. * If nbuf is a simple linear frame, use send_single function to
  2425. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2426. * SRNG. There is no need to setup a MSDU extension descriptor.
  2427. */
  2428. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2429. tx_exc_metadata->peer_id, tx_exc_metadata);
  2430. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2431. return nbuf;
  2432. send_multiple:
  2433. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2434. fail:
  2435. if (vdev)
  2436. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2437. dp_verbose_debug("pkt send failed");
  2438. return nbuf;
  2439. }
  2440. /**
  2441. * dp_tx_send_exception_vdev_id_check() - Transmit a frame on a given VAP
  2442. * in exception path in special case to avoid regular exception path chk.
  2443. * @soc: DP soc handle
  2444. * @vdev_id: id of DP vdev handle
  2445. * @nbuf: skb
  2446. * @tx_exc_metadata: Handle that holds exception path meta data
  2447. *
  2448. * Entry point for Core Tx layer (DP_TX) invoked from
  2449. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2450. *
  2451. * Return: NULL on success,
  2452. * nbuf when it fails to send
  2453. */
  2454. qdf_nbuf_t
  2455. dp_tx_send_exception_vdev_id_check(struct cdp_soc_t *soc_hdl,
  2456. uint8_t vdev_id, qdf_nbuf_t nbuf,
  2457. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2458. {
  2459. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2460. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2461. DP_MOD_ID_TX_EXCEPTION);
  2462. if (qdf_unlikely(!vdev))
  2463. goto fail;
  2464. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  2465. == QDF_STATUS_E_FAILURE)) {
  2466. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  2467. goto fail;
  2468. }
  2469. /* Unref count as it will agin be taken inside dp_tx_exception */
  2470. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2471. return dp_tx_send_exception(soc_hdl, vdev_id, nbuf, tx_exc_metadata);
  2472. fail:
  2473. if (vdev)
  2474. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2475. dp_verbose_debug("pkt send failed");
  2476. return nbuf;
  2477. }
  2478. /**
  2479. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  2480. * @soc: DP soc handle
  2481. * @vdev_id: DP vdev handle
  2482. * @nbuf: skb
  2483. *
  2484. * Entry point for Core Tx layer (DP_TX) invoked from
  2485. * hard_start_xmit in OSIF/HDD
  2486. *
  2487. * Return: NULL on success,
  2488. * nbuf when it fails to send
  2489. */
  2490. #ifdef MESH_MODE_SUPPORT
  2491. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2492. qdf_nbuf_t nbuf)
  2493. {
  2494. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2495. struct meta_hdr_s *mhdr;
  2496. qdf_nbuf_t nbuf_mesh = NULL;
  2497. qdf_nbuf_t nbuf_clone = NULL;
  2498. struct dp_vdev *vdev;
  2499. uint8_t no_enc_frame = 0;
  2500. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  2501. if (!nbuf_mesh) {
  2502. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2503. "qdf_nbuf_unshare failed");
  2504. return nbuf;
  2505. }
  2506. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_MESH);
  2507. if (!vdev) {
  2508. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2509. "vdev is NULL for vdev_id %d", vdev_id);
  2510. return nbuf;
  2511. }
  2512. nbuf = nbuf_mesh;
  2513. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2514. if ((vdev->sec_type != cdp_sec_type_none) &&
  2515. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  2516. no_enc_frame = 1;
  2517. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  2518. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  2519. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  2520. !no_enc_frame) {
  2521. nbuf_clone = qdf_nbuf_clone(nbuf);
  2522. if (!nbuf_clone) {
  2523. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2524. "qdf_nbuf_clone failed");
  2525. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2526. return nbuf;
  2527. }
  2528. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  2529. }
  2530. if (nbuf_clone) {
  2531. if (!dp_tx_send(soc_hdl, vdev_id, nbuf_clone)) {
  2532. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2533. } else {
  2534. qdf_nbuf_free(nbuf_clone);
  2535. }
  2536. }
  2537. if (no_enc_frame)
  2538. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  2539. else
  2540. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  2541. nbuf = dp_tx_send(soc_hdl, vdev_id, nbuf);
  2542. if ((!nbuf) && no_enc_frame) {
  2543. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2544. }
  2545. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2546. return nbuf;
  2547. }
  2548. #else
  2549. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc, uint8_t vdev_id,
  2550. qdf_nbuf_t nbuf)
  2551. {
  2552. return dp_tx_send(soc, vdev_id, nbuf);
  2553. }
  2554. #endif
  2555. /**
  2556. * dp_tx_nawds_handler() - NAWDS handler
  2557. *
  2558. * @soc: DP soc handle
  2559. * @vdev_id: id of DP vdev handle
  2560. * @msdu_info: msdu_info required to create HTT metadata
  2561. * @nbuf: skb
  2562. *
  2563. * This API transfers the multicast frames with the peer id
  2564. * on NAWDS enabled peer.
  2565. * Return: none
  2566. */
  2567. static inline
  2568. void dp_tx_nawds_handler(struct dp_soc *soc, struct dp_vdev *vdev,
  2569. struct dp_tx_msdu_info_s *msdu_info, qdf_nbuf_t nbuf)
  2570. {
  2571. struct dp_peer *peer = NULL;
  2572. qdf_nbuf_t nbuf_clone = NULL;
  2573. uint16_t peer_id = DP_INVALID_PEER;
  2574. uint16_t sa_peer_id = DP_INVALID_PEER;
  2575. struct dp_ast_entry *ast_entry = NULL;
  2576. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2577. qdf_spin_lock_bh(&soc->ast_lock);
  2578. ast_entry = dp_peer_ast_hash_find_by_pdevid
  2579. (soc,
  2580. (uint8_t *)(eh->ether_shost),
  2581. vdev->pdev->pdev_id);
  2582. if (ast_entry)
  2583. sa_peer_id = ast_entry->peer_id;
  2584. qdf_spin_unlock_bh(&soc->ast_lock);
  2585. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2586. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2587. if (!peer->bss_peer && peer->nawds_enabled) {
  2588. peer_id = peer->peer_id;
  2589. /* Multicast packets needs to be
  2590. * dropped in case of intra bss forwarding
  2591. */
  2592. if (sa_peer_id == peer->peer_id) {
  2593. QDF_TRACE(QDF_MODULE_ID_DP,
  2594. QDF_TRACE_LEVEL_DEBUG,
  2595. " %s: multicast packet", __func__);
  2596. DP_STATS_INC(peer, tx.nawds_mcast_drop, 1);
  2597. continue;
  2598. }
  2599. nbuf_clone = qdf_nbuf_clone(nbuf);
  2600. if (!nbuf_clone) {
  2601. QDF_TRACE(QDF_MODULE_ID_DP,
  2602. QDF_TRACE_LEVEL_ERROR,
  2603. FL("nbuf clone failed"));
  2604. break;
  2605. }
  2606. nbuf_clone = dp_tx_send_msdu_single(vdev, nbuf_clone,
  2607. msdu_info, peer_id,
  2608. NULL);
  2609. if (nbuf_clone) {
  2610. QDF_TRACE(QDF_MODULE_ID_DP,
  2611. QDF_TRACE_LEVEL_DEBUG,
  2612. FL("pkt send failed"));
  2613. qdf_nbuf_free(nbuf_clone);
  2614. } else {
  2615. if (peer_id != DP_INVALID_PEER)
  2616. DP_STATS_INC_PKT(peer, tx.nawds_mcast,
  2617. 1, qdf_nbuf_len(nbuf));
  2618. }
  2619. }
  2620. }
  2621. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2622. }
  2623. /**
  2624. * dp_tx_send() - Transmit a frame on a given VAP
  2625. * @soc: DP soc handle
  2626. * @vdev_id: id of DP vdev handle
  2627. * @nbuf: skb
  2628. *
  2629. * Entry point for Core Tx layer (DP_TX) invoked from
  2630. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  2631. * cases
  2632. *
  2633. * Return: NULL on success,
  2634. * nbuf when it fails to send
  2635. */
  2636. qdf_nbuf_t dp_tx_send(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2637. qdf_nbuf_t nbuf)
  2638. {
  2639. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2640. uint16_t peer_id = HTT_INVALID_PEER;
  2641. /*
  2642. * doing a memzero is causing additional function call overhead
  2643. * so doing static stack clearing
  2644. */
  2645. struct dp_tx_msdu_info_s msdu_info = {0};
  2646. struct dp_vdev *vdev = NULL;
  2647. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  2648. return nbuf;
  2649. /*
  2650. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  2651. * this in per packet path.
  2652. *
  2653. * As in this path vdev memory is already protected with netdev
  2654. * tx lock
  2655. */
  2656. vdev = soc->vdev_id_map[vdev_id];
  2657. if (qdf_unlikely(!vdev))
  2658. return nbuf;
  2659. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2660. QDF_MAC_ADDR_REF(nbuf->data));
  2661. /*
  2662. * Set Default Host TID value to invalid TID
  2663. * (TID override disabled)
  2664. */
  2665. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  2666. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2667. if (qdf_unlikely(vdev->mesh_vdev)) {
  2668. qdf_nbuf_t nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  2669. &msdu_info);
  2670. if (!nbuf_mesh) {
  2671. dp_verbose_debug("Extracting mesh metadata failed");
  2672. return nbuf;
  2673. }
  2674. nbuf = nbuf_mesh;
  2675. }
  2676. /*
  2677. * Get HW Queue to use for this frame.
  2678. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2679. * dedicated for data and 1 for command.
  2680. * "queue_id" maps to one hardware ring.
  2681. * With each ring, we also associate a unique Tx descriptor pool
  2682. * to minimize lock contention for these resources.
  2683. */
  2684. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2685. /*
  2686. * TCL H/W supports 2 DSCP-TID mapping tables.
  2687. * Table 1 - Default DSCP-TID mapping table
  2688. * Table 2 - 1 DSCP-TID override table
  2689. *
  2690. * If we need a different DSCP-TID mapping for this vap,
  2691. * call tid_classify to extract DSCP/ToS from frame and
  2692. * map to a TID and store in msdu_info. This is later used
  2693. * to fill in TCL Input descriptor (per-packet TID override).
  2694. */
  2695. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  2696. /*
  2697. * Classify the frame and call corresponding
  2698. * "prepare" function which extracts the segment (TSO)
  2699. * and fragmentation information (for TSO , SG, ME, or Raw)
  2700. * into MSDU_INFO structure which is later used to fill
  2701. * SW and HW descriptors.
  2702. */
  2703. if (qdf_nbuf_is_tso(nbuf)) {
  2704. dp_verbose_debug("TSO frame %pK", vdev);
  2705. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2706. qdf_nbuf_len(nbuf));
  2707. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2708. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2709. qdf_nbuf_len(nbuf));
  2710. return nbuf;
  2711. }
  2712. goto send_multiple;
  2713. }
  2714. /* SG */
  2715. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2716. struct dp_tx_seg_info_s seg_info = {0};
  2717. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2718. if (!nbuf)
  2719. return NULL;
  2720. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2721. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2722. qdf_nbuf_len(nbuf));
  2723. goto send_multiple;
  2724. }
  2725. if (qdf_unlikely(!dp_tx_mcast_enhance(vdev, nbuf)))
  2726. return NULL;
  2727. /* RAW */
  2728. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  2729. struct dp_tx_seg_info_s seg_info = {0};
  2730. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  2731. if (!nbuf)
  2732. return NULL;
  2733. dp_verbose_debug("Raw frame %pK", vdev);
  2734. goto send_multiple;
  2735. }
  2736. if (qdf_unlikely(vdev->nawds_enabled)) {
  2737. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  2738. qdf_nbuf_data(nbuf);
  2739. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost))
  2740. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf);
  2741. peer_id = DP_INVALID_PEER;
  2742. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2743. 1, qdf_nbuf_len(nbuf));
  2744. }
  2745. /* Single linear frame */
  2746. /*
  2747. * If nbuf is a simple linear frame, use send_single function to
  2748. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2749. * SRNG. There is no need to setup a MSDU extension descriptor.
  2750. */
  2751. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  2752. return nbuf;
  2753. send_multiple:
  2754. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2755. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  2756. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  2757. return nbuf;
  2758. }
  2759. /**
  2760. * dp_tx_send_vdev_id_check() - Transmit a frame on a given VAP in special
  2761. * case to vaoid check in perpkt path.
  2762. * @soc: DP soc handle
  2763. * @vdev_id: id of DP vdev handle
  2764. * @nbuf: skb
  2765. *
  2766. * Entry point for Core Tx layer (DP_TX) invoked from
  2767. * hard_start_xmit in OSIF/HDD to transmit packet through dp_tx_send
  2768. * with special condition to avoid per pkt check in dp_tx_send
  2769. *
  2770. * Return: NULL on success,
  2771. * nbuf when it fails to send
  2772. */
  2773. qdf_nbuf_t dp_tx_send_vdev_id_check(struct cdp_soc_t *soc_hdl,
  2774. uint8_t vdev_id, qdf_nbuf_t nbuf)
  2775. {
  2776. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2777. struct dp_vdev *vdev = NULL;
  2778. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  2779. return nbuf;
  2780. /*
  2781. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  2782. * this in per packet path.
  2783. *
  2784. * As in this path vdev memory is already protected with netdev
  2785. * tx lock
  2786. */
  2787. vdev = soc->vdev_id_map[vdev_id];
  2788. if (qdf_unlikely(!vdev))
  2789. return nbuf;
  2790. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  2791. == QDF_STATUS_E_FAILURE)) {
  2792. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  2793. return nbuf;
  2794. }
  2795. return dp_tx_send(soc_hdl, vdev_id, nbuf);
  2796. }
  2797. /**
  2798. * dp_tx_reinject_handler() - Tx Reinject Handler
  2799. * @soc: datapath soc handle
  2800. * @vdev: datapath vdev handle
  2801. * @tx_desc: software descriptor head pointer
  2802. * @status : Tx completion status from HTT descriptor
  2803. *
  2804. * This function reinjects frames back to Target.
  2805. * Todo - Host queue needs to be added
  2806. *
  2807. * Return: none
  2808. */
  2809. static
  2810. void dp_tx_reinject_handler(struct dp_soc *soc,
  2811. struct dp_vdev *vdev,
  2812. struct dp_tx_desc_s *tx_desc,
  2813. uint8_t *status)
  2814. {
  2815. struct dp_peer *peer = NULL;
  2816. uint32_t peer_id = HTT_INVALID_PEER;
  2817. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2818. qdf_nbuf_t nbuf_copy = NULL;
  2819. struct dp_tx_msdu_info_s msdu_info;
  2820. #ifdef WDS_VENDOR_EXTENSION
  2821. int is_mcast = 0, is_ucast = 0;
  2822. int num_peers_3addr = 0;
  2823. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  2824. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  2825. #endif
  2826. qdf_assert(vdev);
  2827. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2828. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2829. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2830. "%s Tx reinject path", __func__);
  2831. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  2832. qdf_nbuf_len(tx_desc->nbuf));
  2833. #ifdef WDS_VENDOR_EXTENSION
  2834. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  2835. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  2836. } else {
  2837. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  2838. }
  2839. is_ucast = !is_mcast;
  2840. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2841. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2842. if (peer->bss_peer)
  2843. continue;
  2844. /* Detect wds peers that use 3-addr framing for mcast.
  2845. * if there are any, the bss_peer is used to send the
  2846. * the mcast frame using 3-addr format. all wds enabled
  2847. * peers that use 4-addr framing for mcast frames will
  2848. * be duplicated and sent as 4-addr frames below.
  2849. */
  2850. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  2851. num_peers_3addr = 1;
  2852. break;
  2853. }
  2854. }
  2855. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2856. #endif
  2857. if (qdf_unlikely(vdev->mesh_vdev)) {
  2858. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  2859. } else {
  2860. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2861. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2862. if ((peer->peer_id != HTT_INVALID_PEER) &&
  2863. #ifdef WDS_VENDOR_EXTENSION
  2864. /*
  2865. * . if 3-addr STA, then send on BSS Peer
  2866. * . if Peer WDS enabled and accept 4-addr mcast,
  2867. * send mcast on that peer only
  2868. * . if Peer WDS enabled and accept 4-addr ucast,
  2869. * send ucast on that peer only
  2870. */
  2871. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  2872. (peer->wds_enabled &&
  2873. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  2874. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  2875. #else
  2876. ((peer->bss_peer &&
  2877. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))))) {
  2878. #endif
  2879. peer_id = DP_INVALID_PEER;
  2880. nbuf_copy = qdf_nbuf_copy(nbuf);
  2881. if (!nbuf_copy) {
  2882. QDF_TRACE(QDF_MODULE_ID_DP,
  2883. QDF_TRACE_LEVEL_DEBUG,
  2884. FL("nbuf copy failed"));
  2885. break;
  2886. }
  2887. nbuf_copy = dp_tx_send_msdu_single(vdev,
  2888. nbuf_copy,
  2889. &msdu_info,
  2890. peer_id,
  2891. NULL);
  2892. if (nbuf_copy) {
  2893. QDF_TRACE(QDF_MODULE_ID_DP,
  2894. QDF_TRACE_LEVEL_DEBUG,
  2895. FL("pkt send failed"));
  2896. qdf_nbuf_free(nbuf_copy);
  2897. }
  2898. }
  2899. }
  2900. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2901. }
  2902. qdf_nbuf_free(nbuf);
  2903. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2904. }
  2905. /**
  2906. * dp_tx_inspect_handler() - Tx Inspect Handler
  2907. * @soc: datapath soc handle
  2908. * @vdev: datapath vdev handle
  2909. * @tx_desc: software descriptor head pointer
  2910. * @status : Tx completion status from HTT descriptor
  2911. *
  2912. * Handles Tx frames sent back to Host for inspection
  2913. * (ProxyARP)
  2914. *
  2915. * Return: none
  2916. */
  2917. static void dp_tx_inspect_handler(struct dp_soc *soc,
  2918. struct dp_vdev *vdev,
  2919. struct dp_tx_desc_s *tx_desc,
  2920. uint8_t *status)
  2921. {
  2922. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2923. "%s Tx inspect path",
  2924. __func__);
  2925. DP_STATS_INC_PKT(vdev, tx_i.inspect_pkts, 1,
  2926. qdf_nbuf_len(tx_desc->nbuf));
  2927. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  2928. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2929. }
  2930. #ifdef FEATURE_PERPKT_INFO
  2931. /**
  2932. * dp_get_completion_indication_for_stack() - send completion to stack
  2933. * @soc : dp_soc handle
  2934. * @pdev: dp_pdev handle
  2935. * @peer: dp peer handle
  2936. * @ts: transmit completion status structure
  2937. * @netbuf: Buffer pointer for free
  2938. *
  2939. * This function is used for indication whether buffer needs to be
  2940. * sent to stack for freeing or not
  2941. */
  2942. QDF_STATUS
  2943. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2944. struct dp_pdev *pdev,
  2945. struct dp_peer *peer,
  2946. struct hal_tx_completion_status *ts,
  2947. qdf_nbuf_t netbuf,
  2948. uint64_t time_latency)
  2949. {
  2950. struct tx_capture_hdr *ppdu_hdr;
  2951. uint16_t peer_id = ts->peer_id;
  2952. uint32_t ppdu_id = ts->ppdu_id;
  2953. uint8_t first_msdu = ts->first_msdu;
  2954. uint8_t last_msdu = ts->last_msdu;
  2955. uint32_t txcap_hdr_size = sizeof(struct tx_capture_hdr);
  2956. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode &&
  2957. !pdev->latency_capture_enable))
  2958. return QDF_STATUS_E_NOSUPPORT;
  2959. if (!peer) {
  2960. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2961. FL("Peer Invalid"));
  2962. return QDF_STATUS_E_INVAL;
  2963. }
  2964. if (pdev->mcopy_mode) {
  2965. /* If mcopy is enabled and mcopy_mode is M_COPY deliver 1st MSDU
  2966. * per PPDU. If mcopy_mode is M_COPY_EXTENDED deliver 1st MSDU
  2967. * for each MPDU
  2968. */
  2969. if (pdev->mcopy_mode == M_COPY) {
  2970. if ((pdev->m_copy_id.tx_ppdu_id == ppdu_id) &&
  2971. (pdev->m_copy_id.tx_peer_id == peer_id)) {
  2972. return QDF_STATUS_E_INVAL;
  2973. }
  2974. }
  2975. if (!first_msdu)
  2976. return QDF_STATUS_E_INVAL;
  2977. pdev->m_copy_id.tx_ppdu_id = ppdu_id;
  2978. pdev->m_copy_id.tx_peer_id = peer_id;
  2979. }
  2980. if (qdf_unlikely(qdf_nbuf_headroom(netbuf) < txcap_hdr_size)) {
  2981. netbuf = qdf_nbuf_realloc_headroom(netbuf, txcap_hdr_size);
  2982. if (!netbuf) {
  2983. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2984. FL("No headroom"));
  2985. return QDF_STATUS_E_NOMEM;
  2986. }
  2987. }
  2988. if (!qdf_nbuf_push_head(netbuf, txcap_hdr_size)) {
  2989. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2990. FL("No headroom"));
  2991. return QDF_STATUS_E_NOMEM;
  2992. }
  2993. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  2994. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  2995. QDF_MAC_ADDR_SIZE);
  2996. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  2997. QDF_MAC_ADDR_SIZE);
  2998. ppdu_hdr->ppdu_id = ppdu_id;
  2999. ppdu_hdr->peer_id = peer_id;
  3000. ppdu_hdr->first_msdu = first_msdu;
  3001. ppdu_hdr->last_msdu = last_msdu;
  3002. if (qdf_unlikely(pdev->latency_capture_enable)) {
  3003. ppdu_hdr->tsf = ts->tsf;
  3004. ppdu_hdr->time_latency = time_latency;
  3005. }
  3006. return QDF_STATUS_SUCCESS;
  3007. }
  3008. /**
  3009. * dp_send_completion_to_stack() - send completion to stack
  3010. * @soc : dp_soc handle
  3011. * @pdev: dp_pdev handle
  3012. * @peer_id: peer_id of the peer for which completion came
  3013. * @ppdu_id: ppdu_id
  3014. * @netbuf: Buffer pointer for free
  3015. *
  3016. * This function is used to send completion to stack
  3017. * to free buffer
  3018. */
  3019. void dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  3020. uint16_t peer_id, uint32_t ppdu_id,
  3021. qdf_nbuf_t netbuf)
  3022. {
  3023. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  3024. netbuf, peer_id,
  3025. WDI_NO_VAL, pdev->pdev_id);
  3026. }
  3027. #else
  3028. static QDF_STATUS
  3029. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  3030. struct dp_pdev *pdev,
  3031. struct dp_peer *peer,
  3032. struct hal_tx_completion_status *ts,
  3033. qdf_nbuf_t netbuf,
  3034. uint64_t time_latency)
  3035. {
  3036. return QDF_STATUS_E_NOSUPPORT;
  3037. }
  3038. static void
  3039. dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  3040. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  3041. {
  3042. }
  3043. #endif
  3044. #ifdef MESH_MODE_SUPPORT
  3045. /**
  3046. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  3047. * in mesh meta header
  3048. * @tx_desc: software descriptor head pointer
  3049. * @ts: pointer to tx completion stats
  3050. * Return: none
  3051. */
  3052. static
  3053. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3054. struct hal_tx_completion_status *ts)
  3055. {
  3056. struct meta_hdr_s *mhdr;
  3057. qdf_nbuf_t netbuf = tx_desc->nbuf;
  3058. if (!tx_desc->msdu_ext_desc) {
  3059. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  3060. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3061. "netbuf %pK offset %d",
  3062. netbuf, tx_desc->pkt_offset);
  3063. return;
  3064. }
  3065. }
  3066. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  3067. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3068. "netbuf %pK offset %lu", netbuf,
  3069. sizeof(struct meta_hdr_s));
  3070. return;
  3071. }
  3072. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  3073. mhdr->rssi = ts->ack_frame_rssi;
  3074. mhdr->band = tx_desc->pdev->operating_channel.band;
  3075. mhdr->channel = tx_desc->pdev->operating_channel.num;
  3076. }
  3077. #else
  3078. static
  3079. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3080. struct hal_tx_completion_status *ts)
  3081. {
  3082. }
  3083. #endif
  3084. #ifdef QCA_PEER_EXT_STATS
  3085. /*
  3086. * dp_tx_compute_tid_delay() - Compute per TID delay
  3087. * @stats: Per TID delay stats
  3088. * @tx_desc: Software Tx descriptor
  3089. *
  3090. * Compute the software enqueue and hw enqueue delays and
  3091. * update the respective histograms
  3092. *
  3093. * Return: void
  3094. */
  3095. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  3096. struct dp_tx_desc_s *tx_desc)
  3097. {
  3098. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  3099. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3100. uint32_t sw_enqueue_delay, fwhw_transmit_delay;
  3101. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3102. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3103. timestamp_hw_enqueue = tx_desc->timestamp;
  3104. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3105. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3106. timestamp_hw_enqueue);
  3107. /*
  3108. * Update the Tx software enqueue delay and HW enque-Completion delay.
  3109. */
  3110. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  3111. dp_hist_update_stats(&tx_delay->hwtx_delay, fwhw_transmit_delay);
  3112. }
  3113. /*
  3114. * dp_tx_update_peer_ext_stats() - Update the peer extended stats
  3115. * @peer: DP peer context
  3116. * @tx_desc: Tx software descriptor
  3117. * @tid: Transmission ID
  3118. * @ring_id: Rx CPU context ID/CPU_ID
  3119. *
  3120. * Update the peer extended stats. These are enhanced other
  3121. * delay stats per msdu level.
  3122. *
  3123. * Return: void
  3124. */
  3125. static void dp_tx_update_peer_ext_stats(struct dp_peer *peer,
  3126. struct dp_tx_desc_s *tx_desc,
  3127. uint8_t tid, uint8_t ring_id)
  3128. {
  3129. struct dp_pdev *pdev = peer->vdev->pdev;
  3130. struct dp_soc *soc = NULL;
  3131. struct cdp_peer_ext_stats *pext_stats = NULL;
  3132. soc = pdev->soc;
  3133. if (qdf_likely(!wlan_cfg_is_peer_ext_stats_enabled(soc->wlan_cfg_ctx)))
  3134. return;
  3135. pext_stats = peer->pext_stats;
  3136. qdf_assert(pext_stats);
  3137. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  3138. /*
  3139. * For non-TID packets use the TID 9
  3140. */
  3141. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3142. tid = CDP_MAX_DATA_TIDS - 1;
  3143. dp_tx_compute_tid_delay(&pext_stats->delay_stats[tid][ring_id],
  3144. tx_desc);
  3145. }
  3146. #else
  3147. static inline void dp_tx_update_peer_ext_stats(struct dp_peer *peer,
  3148. struct dp_tx_desc_s *tx_desc,
  3149. uint8_t tid, uint8_t ring_id)
  3150. {
  3151. }
  3152. #endif
  3153. /**
  3154. * dp_tx_compute_delay() - Compute and fill in all timestamps
  3155. * to pass in correct fields
  3156. *
  3157. * @vdev: pdev handle
  3158. * @tx_desc: tx descriptor
  3159. * @tid: tid value
  3160. * @ring_id: TCL or WBM ring number for transmit path
  3161. * Return: none
  3162. */
  3163. static void dp_tx_compute_delay(struct dp_vdev *vdev,
  3164. struct dp_tx_desc_s *tx_desc,
  3165. uint8_t tid, uint8_t ring_id)
  3166. {
  3167. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3168. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  3169. if (qdf_likely(!vdev->pdev->delay_stats_flag))
  3170. return;
  3171. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3172. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3173. timestamp_hw_enqueue = tx_desc->timestamp;
  3174. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3175. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3176. timestamp_hw_enqueue);
  3177. interframe_delay = (uint32_t)(timestamp_ingress -
  3178. vdev->prev_tx_enq_tstamp);
  3179. /*
  3180. * Delay in software enqueue
  3181. */
  3182. dp_update_delay_stats(vdev->pdev, sw_enqueue_delay, tid,
  3183. CDP_DELAY_STATS_SW_ENQ, ring_id);
  3184. /*
  3185. * Delay between packet enqueued to HW and Tx completion
  3186. */
  3187. dp_update_delay_stats(vdev->pdev, fwhw_transmit_delay, tid,
  3188. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id);
  3189. /*
  3190. * Update interframe delay stats calculated at hardstart receive point.
  3191. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  3192. * interframe delay will not be calculate correctly for 1st frame.
  3193. * On the other side, this will help in avoiding extra per packet check
  3194. * of !vdev->prev_tx_enq_tstamp.
  3195. */
  3196. dp_update_delay_stats(vdev->pdev, interframe_delay, tid,
  3197. CDP_DELAY_STATS_TX_INTERFRAME, ring_id);
  3198. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  3199. }
  3200. #ifdef DISABLE_DP_STATS
  3201. static
  3202. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_peer *peer)
  3203. {
  3204. }
  3205. #else
  3206. static
  3207. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_peer *peer)
  3208. {
  3209. enum qdf_proto_subtype subtype = QDF_PROTO_INVALID;
  3210. DPTRACE(qdf_dp_track_noack_check(nbuf, &subtype));
  3211. if (subtype != QDF_PROTO_INVALID)
  3212. DP_STATS_INC(peer, tx.no_ack_count[subtype], 1);
  3213. }
  3214. #endif
  3215. /**
  3216. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  3217. * per wbm ring
  3218. *
  3219. * @tx_desc: software descriptor head pointer
  3220. * @ts: Tx completion status
  3221. * @peer: peer handle
  3222. * @ring_id: ring number
  3223. *
  3224. * Return: None
  3225. */
  3226. static inline void
  3227. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  3228. struct hal_tx_completion_status *ts,
  3229. struct dp_peer *peer, uint8_t ring_id)
  3230. {
  3231. struct dp_pdev *pdev = peer->vdev->pdev;
  3232. struct dp_soc *soc = NULL;
  3233. uint8_t mcs, pkt_type;
  3234. uint8_t tid = ts->tid;
  3235. uint32_t length;
  3236. struct cdp_tid_tx_stats *tid_stats;
  3237. if (!pdev)
  3238. return;
  3239. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3240. tid = CDP_MAX_DATA_TIDS - 1;
  3241. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3242. soc = pdev->soc;
  3243. mcs = ts->mcs;
  3244. pkt_type = ts->pkt_type;
  3245. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  3246. dp_err("Release source is not from TQM");
  3247. return;
  3248. }
  3249. length = qdf_nbuf_len(tx_desc->nbuf);
  3250. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  3251. if (qdf_unlikely(pdev->delay_stats_flag))
  3252. dp_tx_compute_delay(peer->vdev, tx_desc, tid, ring_id);
  3253. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  3254. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  3255. DP_STATS_INCC_PKT(peer, tx.dropped.fw_rem, 1, length,
  3256. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  3257. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  3258. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  3259. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  3260. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  3261. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  3262. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  3263. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  3264. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  3265. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  3266. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  3267. /*
  3268. * tx_failed is ideally supposed to be updated from HTT ppdu completion
  3269. * stats. But in IPQ807X/IPQ6018 chipsets owing to hw limitation there
  3270. * are no completions for failed cases. Hence updating tx_failed from
  3271. * data path. Please note that if tx_failed is fixed to be from ppdu,
  3272. * then this has to be removed
  3273. */
  3274. peer->stats.tx.tx_failed = peer->stats.tx.dropped.fw_rem.num +
  3275. peer->stats.tx.dropped.fw_rem_notx +
  3276. peer->stats.tx.dropped.fw_rem_tx +
  3277. peer->stats.tx.dropped.age_out +
  3278. peer->stats.tx.dropped.fw_reason1 +
  3279. peer->stats.tx.dropped.fw_reason2 +
  3280. peer->stats.tx.dropped.fw_reason3;
  3281. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  3282. tid_stats->tqm_status_cnt[ts->status]++;
  3283. }
  3284. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  3285. dp_update_no_ack_stats(tx_desc->nbuf, peer);
  3286. return;
  3287. }
  3288. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  3289. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  3290. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  3291. /*
  3292. * Following Rate Statistics are updated from HTT PPDU events from FW.
  3293. * Return from here if HTT PPDU events are enabled.
  3294. */
  3295. if (!(soc->process_tx_status))
  3296. return;
  3297. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3298. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  3299. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3300. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  3301. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3302. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  3303. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3304. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  3305. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3306. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  3307. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3308. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  3309. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3310. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  3311. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3312. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  3313. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3314. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  3315. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3316. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  3317. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  3318. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  3319. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  3320. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  3321. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  3322. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  3323. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  3324. #if defined(FEATURE_PERPKT_INFO) && WDI_EVENT_ENABLE
  3325. dp_wdi_event_handler(WDI_EVENT_UPDATE_DP_STATS, pdev->soc,
  3326. &peer->stats, ts->peer_id,
  3327. UPDATE_PEER_STATS, pdev->pdev_id);
  3328. #endif
  3329. }
  3330. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3331. /**
  3332. * dp_tx_flow_pool_lock() - take flow pool lock
  3333. * @soc: core txrx main context
  3334. * @tx_desc: tx desc
  3335. *
  3336. * Return: None
  3337. */
  3338. static inline
  3339. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  3340. struct dp_tx_desc_s *tx_desc)
  3341. {
  3342. struct dp_tx_desc_pool_s *pool;
  3343. uint8_t desc_pool_id;
  3344. desc_pool_id = tx_desc->pool_id;
  3345. pool = &soc->tx_desc[desc_pool_id];
  3346. qdf_spin_lock_bh(&pool->flow_pool_lock);
  3347. }
  3348. /**
  3349. * dp_tx_flow_pool_unlock() - release flow pool lock
  3350. * @soc: core txrx main context
  3351. * @tx_desc: tx desc
  3352. *
  3353. * Return: None
  3354. */
  3355. static inline
  3356. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  3357. struct dp_tx_desc_s *tx_desc)
  3358. {
  3359. struct dp_tx_desc_pool_s *pool;
  3360. uint8_t desc_pool_id;
  3361. desc_pool_id = tx_desc->pool_id;
  3362. pool = &soc->tx_desc[desc_pool_id];
  3363. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  3364. }
  3365. #else
  3366. static inline
  3367. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3368. {
  3369. }
  3370. static inline
  3371. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3372. {
  3373. }
  3374. #endif
  3375. /**
  3376. * dp_tx_notify_completion() - Notify tx completion for this desc
  3377. * @soc: core txrx main context
  3378. * @vdev: datapath vdev handle
  3379. * @tx_desc: tx desc
  3380. * @netbuf: buffer
  3381. * @status: tx status
  3382. *
  3383. * Return: none
  3384. */
  3385. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  3386. struct dp_vdev *vdev,
  3387. struct dp_tx_desc_s *tx_desc,
  3388. qdf_nbuf_t netbuf,
  3389. uint8_t status)
  3390. {
  3391. void *osif_dev;
  3392. ol_txrx_completion_fp tx_compl_cbk = NULL;
  3393. uint16_t flag = BIT(QDF_TX_RX_STATUS_DOWNLOAD_SUCC);
  3394. qdf_assert(tx_desc);
  3395. dp_tx_flow_pool_lock(soc, tx_desc);
  3396. if (!vdev ||
  3397. !vdev->osif_vdev) {
  3398. dp_tx_flow_pool_unlock(soc, tx_desc);
  3399. return;
  3400. }
  3401. osif_dev = vdev->osif_vdev;
  3402. tx_compl_cbk = vdev->tx_comp;
  3403. dp_tx_flow_pool_unlock(soc, tx_desc);
  3404. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3405. flag |= BIT(QDF_TX_RX_STATUS_OK);
  3406. if (tx_compl_cbk)
  3407. tx_compl_cbk(netbuf, osif_dev, flag);
  3408. }
  3409. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  3410. * @pdev: pdev handle
  3411. * @tid: tid value
  3412. * @txdesc_ts: timestamp from txdesc
  3413. * @ppdu_id: ppdu id
  3414. *
  3415. * Return: none
  3416. */
  3417. #ifdef FEATURE_PERPKT_INFO
  3418. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3419. struct dp_peer *peer,
  3420. uint8_t tid,
  3421. uint64_t txdesc_ts,
  3422. uint32_t ppdu_id)
  3423. {
  3424. uint64_t delta_ms;
  3425. struct cdp_tx_sojourn_stats *sojourn_stats;
  3426. if (qdf_unlikely(pdev->enhanced_stats_en == 0))
  3427. return;
  3428. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  3429. tid >= CDP_DATA_TID_MAX))
  3430. return;
  3431. if (qdf_unlikely(!pdev->sojourn_buf))
  3432. return;
  3433. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  3434. qdf_nbuf_data(pdev->sojourn_buf);
  3435. sojourn_stats->cookie = (void *)peer->rdkstats_ctx;
  3436. delta_ms = qdf_ktime_to_ms(qdf_ktime_get()) -
  3437. txdesc_ts;
  3438. qdf_ewma_tx_lag_add(&peer->avg_sojourn_msdu[tid],
  3439. delta_ms);
  3440. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  3441. sojourn_stats->num_msdus[tid] = 1;
  3442. sojourn_stats->avg_sojourn_msdu[tid].internal =
  3443. peer->avg_sojourn_msdu[tid].internal;
  3444. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  3445. pdev->sojourn_buf, HTT_INVALID_PEER,
  3446. WDI_NO_VAL, pdev->pdev_id);
  3447. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  3448. sojourn_stats->num_msdus[tid] = 0;
  3449. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  3450. }
  3451. #else
  3452. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3453. struct dp_peer *peer,
  3454. uint8_t tid,
  3455. uint64_t txdesc_ts,
  3456. uint32_t ppdu_id)
  3457. {
  3458. }
  3459. #endif
  3460. /**
  3461. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  3462. * @soc: DP Soc handle
  3463. * @tx_desc: software Tx descriptor
  3464. * @ts : Tx completion status from HAL/HTT descriptor
  3465. *
  3466. * Return: none
  3467. */
  3468. static inline void
  3469. dp_tx_comp_process_desc(struct dp_soc *soc,
  3470. struct dp_tx_desc_s *desc,
  3471. struct hal_tx_completion_status *ts,
  3472. struct dp_peer *peer)
  3473. {
  3474. uint64_t time_latency = 0;
  3475. /*
  3476. * m_copy/tx_capture modes are not supported for
  3477. * scatter gather packets
  3478. */
  3479. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  3480. time_latency = (qdf_ktime_to_ms(qdf_ktime_real_get()) -
  3481. desc->timestamp);
  3482. }
  3483. if (!(desc->msdu_ext_desc)) {
  3484. if (QDF_STATUS_SUCCESS ==
  3485. dp_tx_add_to_comp_queue(soc, desc, ts, peer)) {
  3486. return;
  3487. }
  3488. if (QDF_STATUS_SUCCESS ==
  3489. dp_get_completion_indication_for_stack(soc,
  3490. desc->pdev,
  3491. peer, ts,
  3492. desc->nbuf,
  3493. time_latency)) {
  3494. qdf_nbuf_unmap_nbytes_single(soc->osdev, desc->nbuf,
  3495. QDF_DMA_TO_DEVICE,
  3496. desc->nbuf->len);
  3497. dp_send_completion_to_stack(soc,
  3498. desc->pdev,
  3499. ts->peer_id,
  3500. ts->ppdu_id,
  3501. desc->nbuf);
  3502. return;
  3503. }
  3504. }
  3505. dp_tx_comp_free_buf(soc, desc);
  3506. }
  3507. #ifdef DISABLE_DP_STATS
  3508. /**
  3509. * dp_tx_update_connectivity_stats() - update tx connectivity stats
  3510. * @soc: core txrx main context
  3511. * @tx_desc: tx desc
  3512. * @status: tx status
  3513. *
  3514. * Return: none
  3515. */
  3516. static inline
  3517. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3518. struct dp_vdev *vdev,
  3519. struct dp_tx_desc_s *tx_desc,
  3520. uint8_t status)
  3521. {
  3522. }
  3523. #else
  3524. static inline
  3525. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3526. struct dp_vdev *vdev,
  3527. struct dp_tx_desc_s *tx_desc,
  3528. uint8_t status)
  3529. {
  3530. void *osif_dev;
  3531. ol_txrx_stats_rx_fp stats_cbk;
  3532. uint8_t pkt_type;
  3533. qdf_assert(tx_desc);
  3534. if (!vdev ||
  3535. !vdev->osif_vdev ||
  3536. !vdev->stats_cb)
  3537. return;
  3538. osif_dev = vdev->osif_vdev;
  3539. stats_cbk = vdev->stats_cb;
  3540. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_HOST_FW_SENT, &pkt_type);
  3541. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3542. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_ACK_CNT,
  3543. &pkt_type);
  3544. }
  3545. #endif
  3546. /**
  3547. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  3548. * @soc: DP soc handle
  3549. * @tx_desc: software descriptor head pointer
  3550. * @ts: Tx completion status
  3551. * @peer: peer handle
  3552. * @ring_id: ring number
  3553. *
  3554. * Return: none
  3555. */
  3556. static inline
  3557. void dp_tx_comp_process_tx_status(struct dp_soc *soc,
  3558. struct dp_tx_desc_s *tx_desc,
  3559. struct hal_tx_completion_status *ts,
  3560. struct dp_peer *peer, uint8_t ring_id)
  3561. {
  3562. uint32_t length;
  3563. qdf_ether_header_t *eh;
  3564. struct dp_vdev *vdev = NULL;
  3565. qdf_nbuf_t nbuf = tx_desc->nbuf;
  3566. enum qdf_dp_tx_rx_status dp_status;
  3567. if (!nbuf) {
  3568. dp_info_rl("invalid tx descriptor. nbuf NULL");
  3569. goto out;
  3570. }
  3571. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  3572. length = qdf_nbuf_len(nbuf);
  3573. dp_status = dp_tx_hw_to_qdf(ts->status);
  3574. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  3575. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  3576. QDF_TRACE_DEFAULT_PDEV_ID,
  3577. qdf_nbuf_data_addr(nbuf),
  3578. sizeof(qdf_nbuf_data(nbuf)),
  3579. tx_desc->id, ts->status, dp_status));
  3580. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  3581. "-------------------- \n"
  3582. "Tx Completion Stats: \n"
  3583. "-------------------- \n"
  3584. "ack_frame_rssi = %d \n"
  3585. "first_msdu = %d \n"
  3586. "last_msdu = %d \n"
  3587. "msdu_part_of_amsdu = %d \n"
  3588. "rate_stats valid = %d \n"
  3589. "bw = %d \n"
  3590. "pkt_type = %d \n"
  3591. "stbc = %d \n"
  3592. "ldpc = %d \n"
  3593. "sgi = %d \n"
  3594. "mcs = %d \n"
  3595. "ofdma = %d \n"
  3596. "tones_in_ru = %d \n"
  3597. "tsf = %d \n"
  3598. "ppdu_id = %d \n"
  3599. "transmit_cnt = %d \n"
  3600. "tid = %d \n"
  3601. "peer_id = %d\n",
  3602. ts->ack_frame_rssi, ts->first_msdu,
  3603. ts->last_msdu, ts->msdu_part_of_amsdu,
  3604. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  3605. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  3606. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  3607. ts->transmit_cnt, ts->tid, ts->peer_id);
  3608. /* Update SoC level stats */
  3609. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  3610. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  3611. if (!peer) {
  3612. dp_info_rl("peer is null or deletion in progress");
  3613. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  3614. goto out;
  3615. }
  3616. vdev = peer->vdev;
  3617. dp_tx_update_connectivity_stats(soc, vdev, tx_desc, ts->status);
  3618. /* Update per-packet stats for mesh mode */
  3619. if (qdf_unlikely(vdev->mesh_vdev) &&
  3620. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  3621. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  3622. /* Update peer level stats */
  3623. if (qdf_unlikely(peer->bss_peer && vdev->opmode == wlan_op_mode_ap)) {
  3624. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  3625. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  3626. if ((peer->vdev->tx_encap_type ==
  3627. htt_cmn_pkt_type_ethernet) &&
  3628. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  3629. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  3630. }
  3631. }
  3632. } else {
  3633. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  3634. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED) {
  3635. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  3636. if (qdf_unlikely(peer->in_twt)) {
  3637. DP_STATS_INC_PKT(peer,
  3638. tx.tx_success_twt,
  3639. 1, length);
  3640. }
  3641. }
  3642. }
  3643. dp_tx_update_peer_stats(tx_desc, ts, peer, ring_id);
  3644. dp_tx_update_peer_ext_stats(peer, tx_desc, ts->tid, ring_id);
  3645. #ifdef QCA_SUPPORT_RDK_STATS
  3646. if (soc->rdkstats_enabled)
  3647. dp_tx_sojourn_stats_process(vdev->pdev, peer, ts->tid,
  3648. tx_desc->timestamp,
  3649. ts->ppdu_id);
  3650. #endif
  3651. out:
  3652. return;
  3653. }
  3654. /**
  3655. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  3656. * @soc: core txrx main context
  3657. * @comp_head: software descriptor head pointer
  3658. * @ring_id: ring number
  3659. *
  3660. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  3661. * and release the software descriptors after processing is complete
  3662. *
  3663. * Return: none
  3664. */
  3665. static void
  3666. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  3667. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  3668. {
  3669. struct dp_tx_desc_s *desc;
  3670. struct dp_tx_desc_s *next;
  3671. struct hal_tx_completion_status ts;
  3672. struct dp_peer *peer = NULL;
  3673. uint16_t peer_id = DP_INVALID_PEER;
  3674. qdf_nbuf_t netbuf;
  3675. desc = comp_head;
  3676. while (desc) {
  3677. if (peer_id != desc->peer_id) {
  3678. if (peer)
  3679. dp_peer_unref_delete(peer,
  3680. DP_MOD_ID_TX_COMP);
  3681. peer_id = desc->peer_id;
  3682. peer = dp_peer_get_ref_by_id(soc, peer_id,
  3683. DP_MOD_ID_TX_COMP);
  3684. }
  3685. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  3686. struct dp_pdev *pdev = desc->pdev;
  3687. if (qdf_likely(peer)) {
  3688. /*
  3689. * Increment peer statistics
  3690. * Minimal statistics update done here
  3691. */
  3692. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1,
  3693. desc->length);
  3694. if (desc->tx_status !=
  3695. HAL_TX_TQM_RR_FRAME_ACKED)
  3696. DP_STATS_INC(peer, tx.tx_failed, 1);
  3697. }
  3698. qdf_assert(pdev);
  3699. dp_tx_outstanding_dec(pdev);
  3700. /*
  3701. * Calling a QDF WRAPPER here is creating signifcant
  3702. * performance impact so avoided the wrapper call here
  3703. */
  3704. next = desc->next;
  3705. qdf_mem_unmap_nbytes_single(soc->osdev,
  3706. desc->dma_addr,
  3707. QDF_DMA_TO_DEVICE,
  3708. desc->length);
  3709. qdf_nbuf_free(desc->nbuf);
  3710. dp_tx_desc_free(soc, desc, desc->pool_id);
  3711. desc = next;
  3712. continue;
  3713. }
  3714. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  3715. dp_tx_comp_process_tx_status(soc, desc, &ts, peer, ring_id);
  3716. netbuf = desc->nbuf;
  3717. /* check tx complete notification */
  3718. if (peer && qdf_nbuf_tx_notify_comp_get(netbuf))
  3719. dp_tx_notify_completion(soc, peer->vdev, desc,
  3720. netbuf, ts.status);
  3721. dp_tx_comp_process_desc(soc, desc, &ts, peer);
  3722. next = desc->next;
  3723. dp_tx_desc_release(desc, desc->pool_id);
  3724. desc = next;
  3725. }
  3726. if (peer)
  3727. dp_peer_unref_delete(peer, DP_MOD_ID_TX_COMP);
  3728. }
  3729. /**
  3730. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  3731. * @soc: Handle to DP soc structure
  3732. * @tx_desc: software descriptor head pointer
  3733. * @status : Tx completion status from HTT descriptor
  3734. * @ring_id: ring number
  3735. *
  3736. * This function will process HTT Tx indication messages from Target
  3737. *
  3738. * Return: none
  3739. */
  3740. static
  3741. void dp_tx_process_htt_completion(struct dp_soc *soc,
  3742. struct dp_tx_desc_s *tx_desc, uint8_t *status,
  3743. uint8_t ring_id)
  3744. {
  3745. uint8_t tx_status;
  3746. struct dp_pdev *pdev;
  3747. struct dp_vdev *vdev;
  3748. struct hal_tx_completion_status ts = {0};
  3749. uint32_t *htt_desc = (uint32_t *)status;
  3750. struct dp_peer *peer;
  3751. struct cdp_tid_tx_stats *tid_stats = NULL;
  3752. struct htt_soc *htt_handle;
  3753. uint8_t vdev_id;
  3754. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  3755. htt_handle = (struct htt_soc *)soc->htt_handle;
  3756. htt_wbm_event_record(htt_handle->htt_logger_handle, tx_status, status);
  3757. /*
  3758. * There can be scenario where WBM consuming descriptor enqueued
  3759. * from TQM2WBM first and TQM completion can happen before MEC
  3760. * notification comes from FW2WBM. Avoid access any field of tx
  3761. * descriptor in case of MEC notify.
  3762. */
  3763. if (tx_status == HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY) {
  3764. /*
  3765. * Get vdev id from HTT status word in case of MEC
  3766. * notification
  3767. */
  3768. vdev_id = HTT_TX_WBM_COMPLETION_V2_VDEV_ID_GET(htt_desc[3]);
  3769. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  3770. return;
  3771. vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3772. DP_MOD_ID_HTT_COMP);
  3773. if (!vdev)
  3774. return;
  3775. dp_tx_mec_handler(vdev, status);
  3776. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  3777. return;
  3778. }
  3779. /*
  3780. * If the descriptor is already freed in vdev_detach,
  3781. * continue to next descriptor
  3782. */
  3783. if ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) && !tx_desc->flags) {
  3784. QDF_TRACE(QDF_MODULE_ID_DP,
  3785. QDF_TRACE_LEVEL_INFO,
  3786. "Descriptor freed in vdev_detach %d",
  3787. tx_desc->id);
  3788. return;
  3789. }
  3790. pdev = tx_desc->pdev;
  3791. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  3792. QDF_TRACE(QDF_MODULE_ID_DP,
  3793. QDF_TRACE_LEVEL_INFO,
  3794. "pdev in down state %d",
  3795. tx_desc->id);
  3796. dp_tx_comp_free_buf(soc, tx_desc);
  3797. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3798. return;
  3799. }
  3800. qdf_assert(tx_desc->pdev);
  3801. vdev_id = tx_desc->vdev_id;
  3802. vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3803. DP_MOD_ID_HTT_COMP);
  3804. if (!vdev)
  3805. return;
  3806. switch (tx_status) {
  3807. case HTT_TX_FW2WBM_TX_STATUS_OK:
  3808. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  3809. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  3810. {
  3811. uint8_t tid;
  3812. if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
  3813. ts.peer_id =
  3814. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
  3815. htt_desc[2]);
  3816. ts.tid =
  3817. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
  3818. htt_desc[2]);
  3819. } else {
  3820. ts.peer_id = HTT_INVALID_PEER;
  3821. ts.tid = HTT_INVALID_TID;
  3822. }
  3823. ts.ppdu_id =
  3824. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
  3825. htt_desc[1]);
  3826. ts.ack_frame_rssi =
  3827. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
  3828. htt_desc[1]);
  3829. ts.tsf = htt_desc[3];
  3830. ts.first_msdu = 1;
  3831. ts.last_msdu = 1;
  3832. tid = ts.tid;
  3833. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3834. tid = CDP_MAX_DATA_TIDS - 1;
  3835. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3836. if (qdf_unlikely(pdev->delay_stats_flag))
  3837. dp_tx_compute_delay(vdev, tx_desc, tid, ring_id);
  3838. if (tx_status < CDP_MAX_TX_HTT_STATUS) {
  3839. tid_stats->htt_status_cnt[tx_status]++;
  3840. }
  3841. peer = dp_peer_get_ref_by_id(soc, ts.peer_id,
  3842. DP_MOD_ID_HTT_COMP);
  3843. dp_tx_comp_process_tx_status(soc, tx_desc, &ts, peer, ring_id);
  3844. dp_tx_comp_process_desc(soc, tx_desc, &ts, peer);
  3845. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3846. if (qdf_likely(peer))
  3847. dp_peer_unref_delete(peer, DP_MOD_ID_HTT_COMP);
  3848. break;
  3849. }
  3850. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  3851. {
  3852. dp_tx_reinject_handler(soc, vdev, tx_desc, status);
  3853. break;
  3854. }
  3855. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  3856. {
  3857. dp_tx_inspect_handler(soc, vdev, tx_desc, status);
  3858. break;
  3859. }
  3860. default:
  3861. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  3862. "%s Invalid HTT tx_status %d\n",
  3863. __func__, tx_status);
  3864. break;
  3865. }
  3866. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  3867. }
  3868. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  3869. static inline
  3870. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  3871. {
  3872. bool limit_hit = false;
  3873. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  3874. limit_hit =
  3875. (num_reaped >= cfg->tx_comp_loop_pkt_limit) ? true : false;
  3876. if (limit_hit)
  3877. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  3878. return limit_hit;
  3879. }
  3880. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  3881. {
  3882. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  3883. }
  3884. #else
  3885. static inline
  3886. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  3887. {
  3888. return false;
  3889. }
  3890. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  3891. {
  3892. return false;
  3893. }
  3894. #endif
  3895. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  3896. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  3897. uint32_t quota)
  3898. {
  3899. void *tx_comp_hal_desc;
  3900. uint8_t buffer_src;
  3901. uint8_t pool_id;
  3902. uint32_t tx_desc_id;
  3903. struct dp_tx_desc_s *tx_desc = NULL;
  3904. struct dp_tx_desc_s *head_desc = NULL;
  3905. struct dp_tx_desc_s *tail_desc = NULL;
  3906. uint32_t num_processed = 0;
  3907. uint32_t count;
  3908. uint32_t num_avail_for_reap = 0;
  3909. bool force_break = false;
  3910. DP_HIST_INIT();
  3911. more_data:
  3912. /* Re-initialize local variables to be re-used */
  3913. head_desc = NULL;
  3914. tail_desc = NULL;
  3915. count = 0;
  3916. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  3917. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  3918. return 0;
  3919. }
  3920. num_avail_for_reap = hal_srng_dst_num_valid(soc->hal_soc, hal_ring_hdl, 0);
  3921. if (num_avail_for_reap >= quota)
  3922. num_avail_for_reap = quota;
  3923. dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap);
  3924. /* Find head descriptor from completion ring */
  3925. while (qdf_likely(num_avail_for_reap)) {
  3926. tx_comp_hal_desc = dp_srng_dst_get_next(soc, hal_ring_hdl);
  3927. if (qdf_unlikely(!tx_comp_hal_desc))
  3928. break;
  3929. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  3930. /* If this buffer was not released by TQM or FW, then it is not
  3931. * Tx completion indication, assert */
  3932. if (qdf_unlikely(buffer_src !=
  3933. HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  3934. (qdf_unlikely(buffer_src !=
  3935. HAL_TX_COMP_RELEASE_SOURCE_FW))) {
  3936. uint8_t wbm_internal_error;
  3937. dp_err_rl(
  3938. "Tx comp release_src != TQM | FW but from %d",
  3939. buffer_src);
  3940. hal_dump_comp_desc(tx_comp_hal_desc);
  3941. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  3942. /* When WBM sees NULL buffer_addr_info in any of
  3943. * ingress rings it sends an error indication,
  3944. * with wbm_internal_error=1, to a specific ring.
  3945. * The WBM2SW ring used to indicate these errors is
  3946. * fixed in HW, and that ring is being used as Tx
  3947. * completion ring. These errors are not related to
  3948. * Tx completions, and should just be ignored
  3949. */
  3950. wbm_internal_error = hal_get_wbm_internal_error(
  3951. soc->hal_soc,
  3952. tx_comp_hal_desc);
  3953. if (wbm_internal_error) {
  3954. dp_err_rl("Tx comp wbm_internal_error!!");
  3955. DP_STATS_INC(soc, tx.wbm_internal_error[WBM_INT_ERROR_ALL], 1);
  3956. if (HAL_TX_COMP_RELEASE_SOURCE_REO ==
  3957. buffer_src)
  3958. dp_handle_wbm_internal_error(
  3959. soc,
  3960. tx_comp_hal_desc,
  3961. hal_tx_comp_get_buffer_type(
  3962. tx_comp_hal_desc));
  3963. } else {
  3964. dp_err_rl("Tx comp wbm_internal_error false");
  3965. DP_STATS_INC(soc, tx.non_wbm_internal_err, 1);
  3966. }
  3967. continue;
  3968. }
  3969. /* Get descriptor id */
  3970. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  3971. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  3972. DP_TX_DESC_ID_POOL_OS;
  3973. /* Find Tx descriptor */
  3974. tx_desc = dp_tx_desc_find(soc, pool_id,
  3975. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  3976. DP_TX_DESC_ID_PAGE_OS,
  3977. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  3978. DP_TX_DESC_ID_OFFSET_OS);
  3979. /*
  3980. * If the release source is FW, process the HTT status
  3981. */
  3982. if (qdf_unlikely(buffer_src ==
  3983. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  3984. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  3985. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  3986. htt_tx_status);
  3987. dp_tx_process_htt_completion(soc, tx_desc,
  3988. htt_tx_status, ring_id);
  3989. } else {
  3990. tx_desc->peer_id =
  3991. hal_tx_comp_get_peer_id(tx_comp_hal_desc);
  3992. tx_desc->tx_status =
  3993. hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  3994. /*
  3995. * If the fast completion mode is enabled extended
  3996. * metadata from descriptor is not copied
  3997. */
  3998. if (qdf_likely(tx_desc->flags &
  3999. DP_TX_DESC_FLAG_SIMPLE))
  4000. goto add_to_pool;
  4001. /*
  4002. * If the descriptor is already freed in vdev_detach,
  4003. * continue to next descriptor
  4004. */
  4005. if (qdf_unlikely
  4006. ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) &&
  4007. !tx_desc->flags)) {
  4008. QDF_TRACE(QDF_MODULE_ID_DP,
  4009. QDF_TRACE_LEVEL_INFO,
  4010. "Descriptor freed in vdev_detach %d",
  4011. tx_desc_id);
  4012. continue;
  4013. }
  4014. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  4015. QDF_TRACE(QDF_MODULE_ID_DP,
  4016. QDF_TRACE_LEVEL_INFO,
  4017. "pdev in down state %d",
  4018. tx_desc_id);
  4019. dp_tx_comp_free_buf(soc, tx_desc);
  4020. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  4021. goto next_desc;
  4022. }
  4023. /* Pool id is not matching. Error */
  4024. if (tx_desc->pool_id != pool_id) {
  4025. QDF_TRACE(QDF_MODULE_ID_DP,
  4026. QDF_TRACE_LEVEL_FATAL,
  4027. "Tx Comp pool id %d not matched %d",
  4028. pool_id, tx_desc->pool_id);
  4029. qdf_assert_always(0);
  4030. }
  4031. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  4032. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  4033. QDF_TRACE(QDF_MODULE_ID_DP,
  4034. QDF_TRACE_LEVEL_FATAL,
  4035. "Txdesc invalid, flgs = %x,id = %d",
  4036. tx_desc->flags, tx_desc_id);
  4037. qdf_assert_always(0);
  4038. }
  4039. /* Collect hw completion contents */
  4040. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  4041. &tx_desc->comp, 1);
  4042. add_to_pool:
  4043. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  4044. /* First ring descriptor on the cycle */
  4045. if (!head_desc) {
  4046. head_desc = tx_desc;
  4047. tail_desc = tx_desc;
  4048. }
  4049. tail_desc->next = tx_desc;
  4050. tx_desc->next = NULL;
  4051. tail_desc = tx_desc;
  4052. }
  4053. next_desc:
  4054. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  4055. /*
  4056. * Processed packet count is more than given quota
  4057. * stop to processing
  4058. */
  4059. count++;
  4060. if (dp_tx_comp_loop_pkt_limit_hit(soc, count))
  4061. break;
  4062. }
  4063. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  4064. /* Process the reaped descriptors */
  4065. if (head_desc)
  4066. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  4067. if (dp_tx_comp_enable_eol_data_check(soc)) {
  4068. if (num_processed >= quota)
  4069. force_break = true;
  4070. if (!force_break &&
  4071. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  4072. hal_ring_hdl)) {
  4073. DP_STATS_INC(soc, tx.hp_oos2, 1);
  4074. if (!hif_exec_should_yield(soc->hif_handle,
  4075. int_ctx->dp_intr_id))
  4076. goto more_data;
  4077. }
  4078. }
  4079. DP_TX_HIST_STATS_PER_PDEV();
  4080. return num_processed;
  4081. }
  4082. #ifdef FEATURE_WLAN_TDLS
  4083. qdf_nbuf_t dp_tx_non_std(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4084. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  4085. {
  4086. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4087. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4088. DP_MOD_ID_TDLS);
  4089. if (!vdev) {
  4090. dp_err("vdev handle for id %d is NULL", vdev_id);
  4091. return NULL;
  4092. }
  4093. if (tx_spec & OL_TX_SPEC_NO_FREE)
  4094. vdev->is_tdls_frame = true;
  4095. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  4096. return dp_tx_send(soc_hdl, vdev_id, msdu_list);
  4097. }
  4098. #endif
  4099. static void dp_tx_vdev_update_feature_flags(struct dp_vdev *vdev)
  4100. {
  4101. struct wlan_cfg_dp_soc_ctxt *cfg;
  4102. struct dp_soc *soc;
  4103. soc = vdev->pdev->soc;
  4104. if (!soc)
  4105. return;
  4106. cfg = soc->wlan_cfg_ctx;
  4107. if (!cfg)
  4108. return;
  4109. if (vdev->opmode == wlan_op_mode_ndi)
  4110. vdev->csum_enabled = wlan_cfg_get_nan_checksum_offload(cfg);
  4111. else if ((vdev->subtype == wlan_op_subtype_p2p_device) ||
  4112. (vdev->subtype == wlan_op_subtype_p2p_cli) ||
  4113. (vdev->subtype == wlan_op_subtype_p2p_go))
  4114. vdev->csum_enabled = wlan_cfg_get_p2p_checksum_offload(cfg);
  4115. else
  4116. vdev->csum_enabled = wlan_cfg_get_checksum_offload(cfg);
  4117. }
  4118. /**
  4119. * dp_tx_vdev_attach() - attach vdev to dp tx
  4120. * @vdev: virtual device instance
  4121. *
  4122. * Return: QDF_STATUS_SUCCESS: success
  4123. * QDF_STATUS_E_RESOURCES: Error return
  4124. */
  4125. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  4126. {
  4127. int pdev_id;
  4128. /*
  4129. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  4130. */
  4131. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  4132. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  4133. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  4134. vdev->vdev_id);
  4135. pdev_id =
  4136. dp_get_target_pdev_id_for_host_pdev_id(vdev->pdev->soc,
  4137. vdev->pdev->pdev_id);
  4138. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata, pdev_id);
  4139. /*
  4140. * Set HTT Extension Valid bit to 0 by default
  4141. */
  4142. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  4143. dp_tx_vdev_update_search_flags(vdev);
  4144. dp_tx_vdev_update_feature_flags(vdev);
  4145. return QDF_STATUS_SUCCESS;
  4146. }
  4147. #ifndef FEATURE_WDS
  4148. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  4149. {
  4150. return false;
  4151. }
  4152. #endif
  4153. /**
  4154. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  4155. * @vdev: virtual device instance
  4156. *
  4157. * Return: void
  4158. *
  4159. */
  4160. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  4161. {
  4162. struct dp_soc *soc = vdev->pdev->soc;
  4163. /*
  4164. * Enable both AddrY (SA based search) and AddrX (Da based search)
  4165. * for TDLS link
  4166. *
  4167. * Enable AddrY (SA based search) only for non-WDS STA and
  4168. * ProxySTA VAP (in HKv1) modes.
  4169. *
  4170. * In all other VAP modes, only DA based search should be
  4171. * enabled
  4172. */
  4173. if (vdev->opmode == wlan_op_mode_sta &&
  4174. vdev->tdls_link_connected)
  4175. vdev->hal_desc_addr_search_flags =
  4176. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  4177. else if ((vdev->opmode == wlan_op_mode_sta) &&
  4178. !dp_tx_da_search_override(vdev))
  4179. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  4180. else
  4181. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  4182. /* Set search type only when peer map v2 messaging is enabled
  4183. * as we will have the search index (AST hash) only when v2 is
  4184. * enabled
  4185. */
  4186. if (soc->is_peer_map_unmap_v2 && vdev->opmode == wlan_op_mode_sta)
  4187. vdev->search_type = HAL_TX_ADDR_INDEX_SEARCH;
  4188. else
  4189. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  4190. }
  4191. static inline bool
  4192. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  4193. struct dp_vdev *vdev,
  4194. struct dp_tx_desc_s *tx_desc)
  4195. {
  4196. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  4197. return false;
  4198. /*
  4199. * if vdev is given, then only check whether desc
  4200. * vdev match. if vdev is NULL, then check whether
  4201. * desc pdev match.
  4202. */
  4203. return vdev ? (tx_desc->vdev_id == vdev->vdev_id) :
  4204. (tx_desc->pdev == pdev);
  4205. }
  4206. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4207. /**
  4208. * dp_tx_desc_flush() - release resources associated
  4209. * to TX Desc
  4210. *
  4211. * @dp_pdev: Handle to DP pdev structure
  4212. * @vdev: virtual device instance
  4213. * NULL: no specific Vdev is required and check all allcated TX desc
  4214. * on this pdev.
  4215. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  4216. *
  4217. * @force_free:
  4218. * true: flush the TX desc.
  4219. * false: only reset the Vdev in each allocated TX desc
  4220. * that associated to current Vdev.
  4221. *
  4222. * This function will go through the TX desc pool to flush
  4223. * the outstanding TX data or reset Vdev to NULL in associated TX
  4224. * Desc.
  4225. */
  4226. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  4227. bool force_free)
  4228. {
  4229. uint8_t i;
  4230. uint32_t j;
  4231. uint32_t num_desc, page_id, offset;
  4232. uint16_t num_desc_per_page;
  4233. struct dp_soc *soc = pdev->soc;
  4234. struct dp_tx_desc_s *tx_desc = NULL;
  4235. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  4236. if (!vdev && !force_free) {
  4237. dp_err("Reset TX desc vdev, Vdev param is required!");
  4238. return;
  4239. }
  4240. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  4241. tx_desc_pool = &soc->tx_desc[i];
  4242. if (!(tx_desc_pool->pool_size) ||
  4243. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  4244. !(tx_desc_pool->desc_pages.cacheable_pages))
  4245. continue;
  4246. /*
  4247. * Add flow pool lock protection in case pool is freed
  4248. * due to all tx_desc is recycled when handle TX completion.
  4249. * this is not necessary when do force flush as:
  4250. * a. double lock will happen if dp_tx_desc_release is
  4251. * also trying to acquire it.
  4252. * b. dp interrupt has been disabled before do force TX desc
  4253. * flush in dp_pdev_deinit().
  4254. */
  4255. if (!force_free)
  4256. qdf_spin_lock_bh(&tx_desc_pool->flow_pool_lock);
  4257. num_desc = tx_desc_pool->pool_size;
  4258. num_desc_per_page =
  4259. tx_desc_pool->desc_pages.num_element_per_page;
  4260. for (j = 0; j < num_desc; j++) {
  4261. page_id = j / num_desc_per_page;
  4262. offset = j % num_desc_per_page;
  4263. if (qdf_unlikely(!(tx_desc_pool->
  4264. desc_pages.cacheable_pages)))
  4265. break;
  4266. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  4267. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  4268. /*
  4269. * Free TX desc if force free is
  4270. * required, otherwise only reset vdev
  4271. * in this TX desc.
  4272. */
  4273. if (force_free) {
  4274. dp_tx_comp_free_buf(soc, tx_desc);
  4275. dp_tx_desc_release(tx_desc, i);
  4276. } else {
  4277. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  4278. }
  4279. }
  4280. }
  4281. if (!force_free)
  4282. qdf_spin_unlock_bh(&tx_desc_pool->flow_pool_lock);
  4283. }
  4284. }
  4285. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  4286. /**
  4287. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  4288. *
  4289. * @soc: Handle to DP soc structure
  4290. * @tx_desc: pointer of one TX desc
  4291. * @desc_pool_id: TX Desc pool id
  4292. */
  4293. static inline void
  4294. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  4295. uint8_t desc_pool_id)
  4296. {
  4297. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  4298. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  4299. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  4300. }
  4301. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  4302. bool force_free)
  4303. {
  4304. uint8_t i, num_pool;
  4305. uint32_t j;
  4306. uint32_t num_desc, page_id, offset;
  4307. uint16_t num_desc_per_page;
  4308. struct dp_soc *soc = pdev->soc;
  4309. struct dp_tx_desc_s *tx_desc = NULL;
  4310. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  4311. if (!vdev && !force_free) {
  4312. dp_err("Reset TX desc vdev, Vdev param is required!");
  4313. return;
  4314. }
  4315. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4316. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4317. for (i = 0; i < num_pool; i++) {
  4318. tx_desc_pool = &soc->tx_desc[i];
  4319. if (!tx_desc_pool->desc_pages.cacheable_pages)
  4320. continue;
  4321. num_desc_per_page =
  4322. tx_desc_pool->desc_pages.num_element_per_page;
  4323. for (j = 0; j < num_desc; j++) {
  4324. page_id = j / num_desc_per_page;
  4325. offset = j % num_desc_per_page;
  4326. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  4327. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  4328. if (force_free) {
  4329. dp_tx_comp_free_buf(soc, tx_desc);
  4330. dp_tx_desc_release(tx_desc, i);
  4331. } else {
  4332. dp_tx_desc_reset_vdev(soc, tx_desc,
  4333. i);
  4334. }
  4335. }
  4336. }
  4337. }
  4338. }
  4339. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  4340. /**
  4341. * dp_tx_vdev_detach() - detach vdev from dp tx
  4342. * @vdev: virtual device instance
  4343. *
  4344. * Return: QDF_STATUS_SUCCESS: success
  4345. * QDF_STATUS_E_RESOURCES: Error return
  4346. */
  4347. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  4348. {
  4349. struct dp_pdev *pdev = vdev->pdev;
  4350. /* Reset TX desc associated to this Vdev as NULL */
  4351. dp_tx_desc_flush(pdev, vdev, false);
  4352. dp_tx_vdev_multipass_deinit(vdev);
  4353. return QDF_STATUS_SUCCESS;
  4354. }
  4355. /**
  4356. * dp_tx_pdev_attach() - attach pdev to dp tx
  4357. * @pdev: physical device instance
  4358. *
  4359. * Return: QDF_STATUS_SUCCESS: success
  4360. * QDF_STATUS_E_RESOURCES: Error return
  4361. */
  4362. QDF_STATUS dp_tx_pdev_init(struct dp_pdev *pdev)
  4363. {
  4364. struct dp_soc *soc = pdev->soc;
  4365. /* Initialize Flow control counters */
  4366. qdf_atomic_init(&pdev->num_tx_outstanding);
  4367. pdev->tx_descs_max = 0;
  4368. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  4369. /* Initialize descriptors in TCL Ring */
  4370. hal_tx_init_data_ring(soc->hal_soc,
  4371. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  4372. }
  4373. return QDF_STATUS_SUCCESS;
  4374. }
  4375. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4376. /* Pools will be allocated dynamically */
  4377. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  4378. int num_desc)
  4379. {
  4380. uint8_t i;
  4381. for (i = 0; i < num_pool; i++) {
  4382. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  4383. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  4384. }
  4385. return QDF_STATUS_SUCCESS;
  4386. }
  4387. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  4388. int num_desc)
  4389. {
  4390. return QDF_STATUS_SUCCESS;
  4391. }
  4392. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  4393. {
  4394. }
  4395. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  4396. {
  4397. uint8_t i;
  4398. for (i = 0; i < num_pool; i++)
  4399. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  4400. }
  4401. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  4402. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  4403. int num_desc)
  4404. {
  4405. uint8_t i, count;
  4406. /* Allocate software Tx descriptor pools */
  4407. for (i = 0; i < num_pool; i++) {
  4408. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  4409. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4410. FL("Tx Desc Pool alloc %d failed %pK"),
  4411. i, soc);
  4412. goto fail;
  4413. }
  4414. }
  4415. return QDF_STATUS_SUCCESS;
  4416. fail:
  4417. for (count = 0; count < i; count++)
  4418. dp_tx_desc_pool_free(soc, count);
  4419. return QDF_STATUS_E_NOMEM;
  4420. }
  4421. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  4422. int num_desc)
  4423. {
  4424. uint8_t i;
  4425. for (i = 0; i < num_pool; i++) {
  4426. if (dp_tx_desc_pool_init(soc, i, num_desc)) {
  4427. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4428. FL("Tx Desc Pool init %d failed %pK"),
  4429. i, soc);
  4430. return QDF_STATUS_E_NOMEM;
  4431. }
  4432. }
  4433. return QDF_STATUS_SUCCESS;
  4434. }
  4435. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  4436. {
  4437. uint8_t i;
  4438. for (i = 0; i < num_pool; i++)
  4439. dp_tx_desc_pool_deinit(soc, i);
  4440. }
  4441. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  4442. {
  4443. uint8_t i;
  4444. for (i = 0; i < num_pool; i++)
  4445. dp_tx_desc_pool_free(soc, i);
  4446. }
  4447. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  4448. /**
  4449. * dp_tx_tso_cmn_desc_pool_deinit() - de-initialize TSO descriptors
  4450. * @soc: core txrx main context
  4451. * @num_pool: number of pools
  4452. *
  4453. */
  4454. void dp_tx_tso_cmn_desc_pool_deinit(struct dp_soc *soc, uint8_t num_pool)
  4455. {
  4456. dp_tx_tso_desc_pool_deinit(soc, num_pool);
  4457. dp_tx_tso_num_seg_pool_deinit(soc, num_pool);
  4458. }
  4459. /**
  4460. * dp_tx_tso_cmn_desc_pool_free() - free TSO descriptors
  4461. * @soc: core txrx main context
  4462. * @num_pool: number of pools
  4463. *
  4464. */
  4465. void dp_tx_tso_cmn_desc_pool_free(struct dp_soc *soc, uint8_t num_pool)
  4466. {
  4467. dp_tx_tso_desc_pool_free(soc, num_pool);
  4468. dp_tx_tso_num_seg_pool_free(soc, num_pool);
  4469. }
  4470. /**
  4471. * dp_soc_tx_desc_sw_pools_free() - free all TX descriptors
  4472. * @soc: core txrx main context
  4473. *
  4474. * This function frees all tx related descriptors as below
  4475. * 1. Regular TX descriptors (static pools)
  4476. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  4477. * 3. TSO descriptors
  4478. *
  4479. */
  4480. void dp_soc_tx_desc_sw_pools_free(struct dp_soc *soc)
  4481. {
  4482. uint8_t num_pool;
  4483. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4484. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  4485. dp_tx_ext_desc_pool_free(soc, num_pool);
  4486. dp_tx_delete_static_pools(soc, num_pool);
  4487. }
  4488. /**
  4489. * dp_soc_tx_desc_sw_pools_deinit() - de-initialize all TX descriptors
  4490. * @soc: core txrx main context
  4491. *
  4492. * This function de-initializes all tx related descriptors as below
  4493. * 1. Regular TX descriptors (static pools)
  4494. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  4495. * 3. TSO descriptors
  4496. *
  4497. */
  4498. void dp_soc_tx_desc_sw_pools_deinit(struct dp_soc *soc)
  4499. {
  4500. uint8_t num_pool;
  4501. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4502. dp_tx_flow_control_deinit(soc);
  4503. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  4504. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  4505. dp_tx_deinit_static_pools(soc, num_pool);
  4506. }
  4507. /**
  4508. * dp_tso_attach() - TSO attach handler
  4509. * @txrx_soc: Opaque Dp handle
  4510. *
  4511. * Reserve TSO descriptor buffers
  4512. *
  4513. * Return: QDF_STATUS_E_FAILURE on failure or
  4514. * QDF_STATUS_SUCCESS on success
  4515. */
  4516. QDF_STATUS dp_tx_tso_cmn_desc_pool_alloc(struct dp_soc *soc,
  4517. uint8_t num_pool,
  4518. uint16_t num_desc)
  4519. {
  4520. if (dp_tx_tso_desc_pool_alloc(soc, num_pool, num_desc)) {
  4521. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  4522. return QDF_STATUS_E_FAILURE;
  4523. }
  4524. if (dp_tx_tso_num_seg_pool_alloc(soc, num_pool, num_desc)) {
  4525. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  4526. num_pool, soc);
  4527. return QDF_STATUS_E_FAILURE;
  4528. }
  4529. return QDF_STATUS_SUCCESS;
  4530. }
  4531. /**
  4532. * dp_tx_tso_cmn_desc_pool_init() - TSO cmn desc pool init
  4533. * @soc: DP soc handle
  4534. * @num_pool: Number of pools
  4535. * @num_desc: Number of descriptors
  4536. *
  4537. * Initialize TSO descriptor pools
  4538. *
  4539. * Return: QDF_STATUS_E_FAILURE on failure or
  4540. * QDF_STATUS_SUCCESS on success
  4541. */
  4542. QDF_STATUS dp_tx_tso_cmn_desc_pool_init(struct dp_soc *soc,
  4543. uint8_t num_pool,
  4544. uint16_t num_desc)
  4545. {
  4546. if (dp_tx_tso_desc_pool_init(soc, num_pool, num_desc)) {
  4547. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  4548. return QDF_STATUS_E_FAILURE;
  4549. }
  4550. if (dp_tx_tso_num_seg_pool_init(soc, num_pool, num_desc)) {
  4551. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  4552. num_pool, soc);
  4553. return QDF_STATUS_E_FAILURE;
  4554. }
  4555. return QDF_STATUS_SUCCESS;
  4556. }
  4557. /**
  4558. * dp_soc_tx_desc_sw_pools_alloc() - Allocate tx descriptor pool memory
  4559. * @soc: core txrx main context
  4560. *
  4561. * This function allocates memory for following descriptor pools
  4562. * 1. regular sw tx descriptor pools (static pools)
  4563. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  4564. * 3. TSO descriptor pools
  4565. *
  4566. * Return: QDF_STATUS_SUCCESS: success
  4567. * QDF_STATUS_E_RESOURCES: Error return
  4568. */
  4569. QDF_STATUS dp_soc_tx_desc_sw_pools_alloc(struct dp_soc *soc)
  4570. {
  4571. uint8_t num_pool;
  4572. uint32_t num_desc;
  4573. uint32_t num_ext_desc;
  4574. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4575. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4576. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4577. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4578. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  4579. __func__, num_pool, num_desc);
  4580. if ((num_pool > MAX_TXDESC_POOLS) ||
  4581. (num_desc > WLAN_CFG_NUM_TX_DESC_MAX))
  4582. goto fail1;
  4583. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  4584. goto fail1;
  4585. if (dp_tx_ext_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4586. goto fail2;
  4587. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  4588. return QDF_STATUS_SUCCESS;
  4589. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4590. goto fail3;
  4591. return QDF_STATUS_SUCCESS;
  4592. fail3:
  4593. dp_tx_ext_desc_pool_free(soc, num_pool);
  4594. fail2:
  4595. dp_tx_delete_static_pools(soc, num_pool);
  4596. fail1:
  4597. return QDF_STATUS_E_RESOURCES;
  4598. }
  4599. /**
  4600. * dp_soc_tx_desc_sw_pools_init() - Initialise TX descriptor pools
  4601. * @soc: core txrx main context
  4602. *
  4603. * This function initializes the following TX descriptor pools
  4604. * 1. regular sw tx descriptor pools (static pools)
  4605. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  4606. * 3. TSO descriptor pools
  4607. *
  4608. * Return: QDF_STATUS_SUCCESS: success
  4609. * QDF_STATUS_E_RESOURCES: Error return
  4610. */
  4611. QDF_STATUS dp_soc_tx_desc_sw_pools_init(struct dp_soc *soc)
  4612. {
  4613. uint8_t num_pool;
  4614. uint32_t num_desc;
  4615. uint32_t num_ext_desc;
  4616. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4617. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4618. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4619. if (dp_tx_init_static_pools(soc, num_pool, num_desc))
  4620. goto fail1;
  4621. if (dp_tx_ext_desc_pool_init(soc, num_pool, num_ext_desc))
  4622. goto fail2;
  4623. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  4624. return QDF_STATUS_SUCCESS;
  4625. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  4626. goto fail3;
  4627. dp_tx_flow_control_init(soc);
  4628. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  4629. return QDF_STATUS_SUCCESS;
  4630. fail3:
  4631. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  4632. fail2:
  4633. dp_tx_deinit_static_pools(soc, num_pool);
  4634. fail1:
  4635. return QDF_STATUS_E_RESOURCES;
  4636. }
  4637. /**
  4638. * dp_tso_soc_attach() - Allocate and initialize TSO descriptors
  4639. * @txrx_soc: dp soc handle
  4640. *
  4641. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  4642. * QDF_STATUS_E_FAILURE
  4643. */
  4644. QDF_STATUS dp_tso_soc_attach(struct cdp_soc_t *txrx_soc)
  4645. {
  4646. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  4647. uint8_t num_pool;
  4648. uint32_t num_desc;
  4649. uint32_t num_ext_desc;
  4650. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4651. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4652. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4653. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4654. return QDF_STATUS_E_FAILURE;
  4655. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  4656. return QDF_STATUS_E_FAILURE;
  4657. return QDF_STATUS_SUCCESS;
  4658. }
  4659. /**
  4660. * dp_tso_soc_detach() - de-initialize and free the TSO descriptors
  4661. * @txrx_soc: dp soc handle
  4662. *
  4663. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  4664. */
  4665. QDF_STATUS dp_tso_soc_detach(struct cdp_soc_t *txrx_soc)
  4666. {
  4667. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  4668. uint8_t num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4669. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  4670. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  4671. return QDF_STATUS_SUCCESS;
  4672. }