dp_ipa.c 64 KB

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  1. /*
  2. * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #ifdef IPA_OFFLOAD
  17. #include <qdf_ipa_wdi3.h>
  18. #include <qdf_types.h>
  19. #include <qdf_lock.h>
  20. #include <hal_hw_headers.h>
  21. #include <hal_api.h>
  22. #include <hif.h>
  23. #include <htt.h>
  24. #include <wdi_event.h>
  25. #include <queue.h>
  26. #include "dp_types.h"
  27. #include "dp_htt.h"
  28. #include "dp_tx.h"
  29. #include "dp_rx.h"
  30. #include "dp_ipa.h"
  31. /* Ring index for WBM2SW2 release ring */
  32. #define IPA_TX_COMP_RING_IDX HAL_IPA_TX_COMP_RING_IDX
  33. /* Hard coded config parameters until dp_ops_cfg.cfg_attach implemented */
  34. #define CFG_IPA_UC_TX_BUF_SIZE_DEFAULT (2048)
  35. /* WAR for IPA_OFFLOAD case. In some cases, its observed that WBM tries to
  36. * release a buffer into WBM2SW RELEASE ring for IPA, and the ring is full.
  37. * This causes back pressure, resulting in a FW crash.
  38. * By leaving some entries with no buffer attached, WBM will be able to write
  39. * to the ring, and from dumps we can figure out the buffer which is causing
  40. * this issue.
  41. */
  42. #define DP_IPA_WAR_WBM2SW_REL_RING_NO_BUF_ENTRIES 16
  43. /**
  44. *struct dp_ipa_reo_remap_record - history for dp ipa reo remaps
  45. * @ix0_reg: reo destination ring IX0 value
  46. * @ix2_reg: reo destination ring IX2 value
  47. * @ix3_reg: reo destination ring IX3 value
  48. */
  49. struct dp_ipa_reo_remap_record {
  50. uint64_t timestamp;
  51. uint32_t ix0_reg;
  52. uint32_t ix2_reg;
  53. uint32_t ix3_reg;
  54. };
  55. #define REO_REMAP_HISTORY_SIZE 32
  56. struct dp_ipa_reo_remap_record dp_ipa_reo_remap_history[REO_REMAP_HISTORY_SIZE];
  57. static qdf_atomic_t dp_ipa_reo_remap_history_index;
  58. static int dp_ipa_reo_remap_record_index_next(qdf_atomic_t *index)
  59. {
  60. int next = qdf_atomic_inc_return(index);
  61. if (next == REO_REMAP_HISTORY_SIZE)
  62. qdf_atomic_sub(REO_REMAP_HISTORY_SIZE, index);
  63. return next % REO_REMAP_HISTORY_SIZE;
  64. }
  65. /**
  66. * dp_ipa_reo_remap_history_add() - Record dp ipa reo remap values
  67. * @ix0_val: reo destination ring IX0 value
  68. * @ix2_val: reo destination ring IX2 value
  69. * @ix3_val: reo destination ring IX3 value
  70. *
  71. * Return: None
  72. */
  73. static void dp_ipa_reo_remap_history_add(uint32_t ix0_val, uint32_t ix2_val,
  74. uint32_t ix3_val)
  75. {
  76. int idx = dp_ipa_reo_remap_record_index_next(
  77. &dp_ipa_reo_remap_history_index);
  78. struct dp_ipa_reo_remap_record *record = &dp_ipa_reo_remap_history[idx];
  79. record->timestamp = qdf_get_log_timestamp();
  80. record->ix0_reg = ix0_val;
  81. record->ix2_reg = ix2_val;
  82. record->ix3_reg = ix3_val;
  83. }
  84. static QDF_STATUS __dp_ipa_handle_buf_smmu_mapping(struct dp_soc *soc,
  85. qdf_nbuf_t nbuf,
  86. uint32_t size,
  87. bool create)
  88. {
  89. qdf_mem_info_t mem_map_table = {0};
  90. if (!qdf_ipa_is_ready())
  91. return QDF_STATUS_SUCCESS;
  92. qdf_update_mem_map_table(soc->osdev, &mem_map_table,
  93. qdf_nbuf_get_frag_paddr(nbuf, 0),
  94. size);
  95. if (create)
  96. return qdf_ipa_wdi_create_smmu_mapping(1, &mem_map_table);
  97. else
  98. return qdf_ipa_wdi_release_smmu_mapping(1, &mem_map_table);
  99. }
  100. QDF_STATUS dp_ipa_handle_rx_buf_smmu_mapping(struct dp_soc *soc,
  101. qdf_nbuf_t nbuf,
  102. uint32_t size,
  103. bool create)
  104. {
  105. struct dp_pdev *pdev;
  106. int i;
  107. for (i = 0; i < soc->pdev_count; i++) {
  108. pdev = soc->pdev_list[i];
  109. if (pdev && pdev->monitor_configured)
  110. return QDF_STATUS_SUCCESS;
  111. }
  112. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx) ||
  113. !qdf_mem_smmu_s1_enabled(soc->osdev))
  114. return QDF_STATUS_SUCCESS;
  115. /**
  116. * Even if ipa pipes is disabled, but if it's unmap
  117. * operation and nbuf has done ipa smmu map before,
  118. * do ipa smmu unmap as well.
  119. */
  120. if (!qdf_atomic_read(&soc->ipa_pipes_enabled)) {
  121. if (!create && qdf_nbuf_is_rx_ipa_smmu_map(nbuf)) {
  122. DP_STATS_INC(soc, rx.err.ipa_unmap_no_pipe, 1);
  123. } else {
  124. return QDF_STATUS_SUCCESS;
  125. }
  126. }
  127. if (qdf_unlikely(create == qdf_nbuf_is_rx_ipa_smmu_map(nbuf))) {
  128. if (create) {
  129. DP_STATS_INC(soc, rx.err.ipa_smmu_map_dup, 1);
  130. } else {
  131. DP_STATS_INC(soc, rx.err.ipa_smmu_unmap_dup, 1);
  132. }
  133. return QDF_STATUS_E_INVAL;
  134. }
  135. qdf_nbuf_set_rx_ipa_smmu_map(nbuf, create);
  136. return __dp_ipa_handle_buf_smmu_mapping(soc, nbuf, size, create);
  137. }
  138. static QDF_STATUS __dp_ipa_tx_buf_smmu_mapping(
  139. struct dp_soc *soc,
  140. struct dp_pdev *pdev,
  141. bool create)
  142. {
  143. uint32_t index;
  144. QDF_STATUS ret = QDF_STATUS_SUCCESS;
  145. uint32_t tx_buffer_cnt = soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt;
  146. qdf_nbuf_t nbuf;
  147. uint32_t buf_len;
  148. if (!ipa_is_ready()) {
  149. dp_info("IPA is not READY");
  150. return 0;
  151. }
  152. for (index = 0; index < tx_buffer_cnt; index++) {
  153. nbuf = (qdf_nbuf_t)
  154. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned[index];
  155. if (!nbuf)
  156. continue;
  157. buf_len = qdf_nbuf_get_data_len(nbuf);
  158. ret = __dp_ipa_handle_buf_smmu_mapping(
  159. soc, nbuf, buf_len, create);
  160. qdf_assert_always(!ret);
  161. }
  162. return ret;
  163. }
  164. #ifdef RX_DESC_MULTI_PAGE_ALLOC
  165. static QDF_STATUS dp_ipa_handle_rx_buf_pool_smmu_mapping(struct dp_soc *soc,
  166. struct dp_pdev *pdev,
  167. bool create)
  168. {
  169. struct rx_desc_pool *rx_pool;
  170. uint8_t pdev_id;
  171. uint32_t num_desc, page_id, offset, i;
  172. uint16_t num_desc_per_page;
  173. union dp_rx_desc_list_elem_t *rx_desc_elem;
  174. struct dp_rx_desc *rx_desc;
  175. qdf_nbuf_t nbuf;
  176. if (!qdf_mem_smmu_s1_enabled(soc->osdev))
  177. return QDF_STATUS_SUCCESS;
  178. pdev_id = pdev->pdev_id;
  179. rx_pool = &soc->rx_desc_buf[pdev_id];
  180. qdf_spin_lock_bh(&rx_pool->lock);
  181. num_desc = rx_pool->pool_size;
  182. num_desc_per_page = rx_pool->desc_pages.num_element_per_page;
  183. for (i = 0; i < num_desc; i++) {
  184. page_id = i / num_desc_per_page;
  185. offset = i % num_desc_per_page;
  186. if (qdf_unlikely(!(rx_pool->desc_pages.cacheable_pages)))
  187. break;
  188. rx_desc_elem = dp_rx_desc_find(page_id, offset, rx_pool);
  189. rx_desc = &rx_desc_elem->rx_desc;
  190. if ((!(rx_desc->in_use)) || rx_desc->unmapped)
  191. continue;
  192. nbuf = rx_desc->nbuf;
  193. if (qdf_unlikely(create ==
  194. qdf_nbuf_is_rx_ipa_smmu_map(nbuf))) {
  195. if (create) {
  196. DP_STATS_INC(soc,
  197. rx.err.ipa_smmu_map_dup, 1);
  198. } else {
  199. DP_STATS_INC(soc,
  200. rx.err.ipa_smmu_unmap_dup, 1);
  201. }
  202. continue;
  203. }
  204. qdf_nbuf_set_rx_ipa_smmu_map(nbuf, create);
  205. __dp_ipa_handle_buf_smmu_mapping(soc, nbuf,
  206. rx_pool->buf_size, create);
  207. }
  208. qdf_spin_unlock_bh(&rx_pool->lock);
  209. return QDF_STATUS_SUCCESS;
  210. }
  211. #else
  212. static QDF_STATUS dp_ipa_handle_rx_buf_pool_smmu_mapping(struct dp_soc *soc,
  213. struct dp_pdev *pdev,
  214. bool create)
  215. {
  216. struct rx_desc_pool *rx_pool;
  217. uint8_t pdev_id;
  218. qdf_nbuf_t nbuf;
  219. int i;
  220. if (!qdf_mem_smmu_s1_enabled(soc->osdev))
  221. return QDF_STATUS_SUCCESS;
  222. pdev_id = pdev->pdev_id;
  223. rx_pool = &soc->rx_desc_buf[pdev_id];
  224. qdf_spin_lock_bh(&rx_pool->lock);
  225. for (i = 0; i < rx_pool->pool_size; i++) {
  226. if ((!(rx_pool->array[i].rx_desc.in_use)) ||
  227. rx_pool->array[i].rx_desc.unmapped)
  228. continue;
  229. nbuf = rx_pool->array[i].rx_desc.nbuf;
  230. if (qdf_unlikely(create ==
  231. qdf_nbuf_is_rx_ipa_smmu_map(nbuf))) {
  232. if (create) {
  233. DP_STATS_INC(soc,
  234. rx.err.ipa_smmu_map_dup, 1);
  235. } else {
  236. DP_STATS_INC(soc,
  237. rx.err.ipa_smmu_unmap_dup, 1);
  238. }
  239. continue;
  240. }
  241. qdf_nbuf_set_rx_ipa_smmu_map(nbuf, create);
  242. __dp_ipa_handle_buf_smmu_mapping(soc, nbuf,
  243. rx_pool->buf_size, create);
  244. }
  245. qdf_spin_unlock_bh(&rx_pool->lock);
  246. return QDF_STATUS_SUCCESS;
  247. }
  248. #endif /* RX_DESC_MULTI_PAGE_ALLOC */
  249. /**
  250. * dp_tx_ipa_uc_detach - Free autonomy TX resources
  251. * @soc: data path instance
  252. * @pdev: core txrx pdev context
  253. *
  254. * Free allocated TX buffers with WBM SRNG
  255. *
  256. * Return: none
  257. */
  258. static void dp_tx_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  259. {
  260. int idx;
  261. qdf_nbuf_t nbuf;
  262. struct dp_ipa_resources *ipa_res;
  263. for (idx = 0; idx < soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt; idx++) {
  264. nbuf = (qdf_nbuf_t)
  265. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned[idx];
  266. if (!nbuf)
  267. continue;
  268. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_BIDIRECTIONAL);
  269. qdf_mem_dp_tx_skb_cnt_dec();
  270. qdf_mem_dp_tx_skb_dec(qdf_nbuf_get_data_len(nbuf));
  271. qdf_nbuf_free(nbuf);
  272. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned[idx] =
  273. (void *)NULL;
  274. }
  275. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned);
  276. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned = NULL;
  277. ipa_res = &pdev->ipa_resource;
  278. if (!ipa_res->is_db_ddr_mapped)
  279. iounmap(ipa_res->tx_comp_doorbell_vaddr);
  280. qdf_mem_free_sgtable(&ipa_res->tx_ring.sgtable);
  281. qdf_mem_free_sgtable(&ipa_res->tx_comp_ring.sgtable);
  282. }
  283. /**
  284. * dp_rx_ipa_uc_detach - free autonomy RX resources
  285. * @soc: data path instance
  286. * @pdev: core txrx pdev context
  287. *
  288. * This function will detach DP RX into main device context
  289. * will free DP Rx resources.
  290. *
  291. * Return: none
  292. */
  293. static void dp_rx_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  294. {
  295. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  296. qdf_mem_free_sgtable(&ipa_res->rx_rdy_ring.sgtable);
  297. qdf_mem_free_sgtable(&ipa_res->rx_refill_ring.sgtable);
  298. }
  299. int dp_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  300. {
  301. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  302. return QDF_STATUS_SUCCESS;
  303. /* TX resource detach */
  304. dp_tx_ipa_uc_detach(soc, pdev);
  305. /* RX resource detach */
  306. dp_rx_ipa_uc_detach(soc, pdev);
  307. return QDF_STATUS_SUCCESS; /* success */
  308. }
  309. /**
  310. * dp_tx_ipa_uc_attach - Allocate autonomy TX resources
  311. * @soc: data path instance
  312. * @pdev: Physical device handle
  313. *
  314. * Allocate TX buffer from non-cacheable memory
  315. * Attache allocated TX buffers with WBM SRNG
  316. *
  317. * Return: int
  318. */
  319. static int dp_tx_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  320. {
  321. uint32_t tx_buffer_count;
  322. uint32_t ring_base_align = 8;
  323. qdf_dma_addr_t buffer_paddr;
  324. struct hal_srng *wbm_srng = (struct hal_srng *)
  325. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  326. struct hal_srng_params srng_params;
  327. uint32_t paddr_lo;
  328. uint32_t paddr_hi;
  329. void *ring_entry;
  330. int num_entries;
  331. qdf_nbuf_t nbuf;
  332. int retval = QDF_STATUS_SUCCESS;
  333. int max_alloc_count = 0;
  334. /*
  335. * Uncomment when dp_ops_cfg.cfg_attach is implemented
  336. * unsigned int uc_tx_buf_sz =
  337. * dp_cfg_ipa_uc_tx_buf_size(pdev->osif_pdev);
  338. */
  339. unsigned int uc_tx_buf_sz = CFG_IPA_UC_TX_BUF_SIZE_DEFAULT;
  340. unsigned int alloc_size = uc_tx_buf_sz + ring_base_align - 1;
  341. hal_get_srng_params(soc->hal_soc, hal_srng_to_hal_ring_handle(wbm_srng),
  342. &srng_params);
  343. num_entries = srng_params.num_entries;
  344. max_alloc_count =
  345. num_entries - DP_IPA_WAR_WBM2SW_REL_RING_NO_BUF_ENTRIES;
  346. if (max_alloc_count <= 0) {
  347. dp_err("incorrect value for buffer count %u", max_alloc_count);
  348. return -EINVAL;
  349. }
  350. dp_info("requested %d buffers to be posted to wbm ring",
  351. max_alloc_count);
  352. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned =
  353. qdf_mem_malloc(num_entries *
  354. sizeof(*soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned));
  355. if (!soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned) {
  356. dp_err("IPA WBM Ring Tx buf pool vaddr alloc fail");
  357. return -ENOMEM;
  358. }
  359. hal_srng_access_start_unlocked(soc->hal_soc,
  360. hal_srng_to_hal_ring_handle(wbm_srng));
  361. /*
  362. * Allocate Tx buffers as many as possible.
  363. * Leave DP_IPA_WAR_WBM2SW_REL_RING_NO_BUF_ENTRIES empty
  364. * Populate Tx buffers into WBM2IPA ring
  365. * This initial buffer population will simulate H/W as source ring,
  366. * and update HP
  367. */
  368. for (tx_buffer_count = 0;
  369. tx_buffer_count < max_alloc_count - 1; tx_buffer_count++) {
  370. nbuf = qdf_nbuf_alloc(soc->osdev, alloc_size, 0, 256, FALSE);
  371. if (!nbuf)
  372. break;
  373. ring_entry = hal_srng_dst_get_next_hp(soc->hal_soc,
  374. hal_srng_to_hal_ring_handle(wbm_srng));
  375. if (!ring_entry) {
  376. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  377. "%s: Failed to get WBM ring entry",
  378. __func__);
  379. qdf_nbuf_free(nbuf);
  380. break;
  381. }
  382. qdf_nbuf_map_single(soc->osdev, nbuf,
  383. QDF_DMA_BIDIRECTIONAL);
  384. buffer_paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  385. qdf_mem_dp_tx_skb_cnt_inc();
  386. qdf_mem_dp_tx_skb_inc(qdf_nbuf_get_data_len(nbuf));
  387. paddr_lo = ((uint64_t)buffer_paddr & 0x00000000ffffffff);
  388. paddr_hi = ((uint64_t)buffer_paddr & 0x0000001f00000000) >> 32;
  389. HAL_RXDMA_PADDR_LO_SET(ring_entry, paddr_lo);
  390. HAL_RXDMA_PADDR_HI_SET(ring_entry, paddr_hi);
  391. HAL_RXDMA_MANAGER_SET(ring_entry, (IPA_TCL_DATA_RING_IDX +
  392. HAL_WBM_SW0_BM_ID));
  393. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned[tx_buffer_count]
  394. = (void *)nbuf;
  395. }
  396. hal_srng_access_end_unlocked(soc->hal_soc,
  397. hal_srng_to_hal_ring_handle(wbm_srng));
  398. soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt = tx_buffer_count;
  399. if (tx_buffer_count) {
  400. dp_info("IPA WDI TX buffer: %d allocated", tx_buffer_count);
  401. } else {
  402. dp_err("No IPA WDI TX buffer allocated!");
  403. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned);
  404. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned = NULL;
  405. retval = -ENOMEM;
  406. }
  407. return retval;
  408. }
  409. /**
  410. * dp_rx_ipa_uc_attach - Allocate autonomy RX resources
  411. * @soc: data path instance
  412. * @pdev: core txrx pdev context
  413. *
  414. * This function will attach a DP RX instance into the main
  415. * device (SOC) context.
  416. *
  417. * Return: QDF_STATUS_SUCCESS: success
  418. * QDF_STATUS_E_RESOURCES: Error return
  419. */
  420. static int dp_rx_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  421. {
  422. return QDF_STATUS_SUCCESS;
  423. }
  424. int dp_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  425. {
  426. int error;
  427. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  428. return QDF_STATUS_SUCCESS;
  429. /* TX resource attach */
  430. error = dp_tx_ipa_uc_attach(soc, pdev);
  431. if (error) {
  432. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  433. "%s: DP IPA UC TX attach fail code %d",
  434. __func__, error);
  435. return error;
  436. }
  437. /* RX resource attach */
  438. error = dp_rx_ipa_uc_attach(soc, pdev);
  439. if (error) {
  440. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  441. "%s: DP IPA UC RX attach fail code %d",
  442. __func__, error);
  443. dp_tx_ipa_uc_detach(soc, pdev);
  444. return error;
  445. }
  446. return QDF_STATUS_SUCCESS; /* success */
  447. }
  448. /*
  449. * dp_ipa_ring_resource_setup() - setup IPA ring resources
  450. * @soc: data path SoC handle
  451. *
  452. * Return: none
  453. */
  454. int dp_ipa_ring_resource_setup(struct dp_soc *soc,
  455. struct dp_pdev *pdev)
  456. {
  457. struct hal_soc *hal_soc = (struct hal_soc *)soc->hal_soc;
  458. struct hal_srng *hal_srng;
  459. struct hal_srng_params srng_params;
  460. qdf_dma_addr_t hp_addr;
  461. unsigned long addr_offset, dev_base_paddr;
  462. uint32_t ix0;
  463. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  464. return QDF_STATUS_SUCCESS;
  465. /* IPA TCL_DATA Ring - HAL_SRNG_SW2TCL3 */
  466. hal_srng = (struct hal_srng *)
  467. soc->tcl_data_ring[IPA_TCL_DATA_RING_IDX].hal_srng;
  468. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  469. hal_srng_to_hal_ring_handle(hal_srng),
  470. &srng_params);
  471. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_paddr =
  472. srng_params.ring_base_paddr;
  473. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_vaddr =
  474. srng_params.ring_base_vaddr;
  475. soc->ipa_uc_tx_rsc.ipa_tcl_ring_size =
  476. (srng_params.num_entries * srng_params.entry_size) << 2;
  477. /*
  478. * For the register backed memory addresses, use the scn->mem_pa to
  479. * calculate the physical address of the shadow registers
  480. */
  481. dev_base_paddr =
  482. (unsigned long)
  483. ((struct hif_softc *)(hal_soc->hif_handle))->mem_pa;
  484. addr_offset = (unsigned long)(hal_srng->u.src_ring.hp_addr) -
  485. (unsigned long)(hal_soc->dev_base_addr);
  486. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr =
  487. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  488. dp_info("IPA TCL_DATA Ring addr_offset=%x, dev_base_paddr=%x, hp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  489. (unsigned int)addr_offset,
  490. (unsigned int)dev_base_paddr,
  491. (unsigned int)(soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr),
  492. (void *)soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_paddr,
  493. (void *)soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_vaddr,
  494. srng_params.num_entries,
  495. soc->ipa_uc_tx_rsc.ipa_tcl_ring_size);
  496. /* IPA TX COMP Ring - HAL_SRNG_WBM2SW2_RELEASE */
  497. hal_srng = (struct hal_srng *)
  498. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  499. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  500. hal_srng_to_hal_ring_handle(hal_srng),
  501. &srng_params);
  502. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_paddr =
  503. srng_params.ring_base_paddr;
  504. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_vaddr =
  505. srng_params.ring_base_vaddr;
  506. soc->ipa_uc_tx_rsc.ipa_wbm_ring_size =
  507. (srng_params.num_entries * srng_params.entry_size) << 2;
  508. addr_offset = (unsigned long)(hal_srng->u.dst_ring.tp_addr) -
  509. (unsigned long)(hal_soc->dev_base_addr);
  510. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr =
  511. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  512. dp_info("IPA TX COMP Ring addr_offset=%x, dev_base_paddr=%x, ipa_wbm_tp_paddr=%x paddr=%pK vaddr=0%pK size= %u(%u bytes)",
  513. (unsigned int)addr_offset,
  514. (unsigned int)dev_base_paddr,
  515. (unsigned int)(soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr),
  516. (void *)soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_paddr,
  517. (void *)soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_vaddr,
  518. srng_params.num_entries,
  519. soc->ipa_uc_tx_rsc.ipa_wbm_ring_size);
  520. /* IPA REO_DEST Ring - HAL_SRNG_REO2SW4 */
  521. hal_srng = (struct hal_srng *)
  522. soc->reo_dest_ring[IPA_REO_DEST_RING_IDX].hal_srng;
  523. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  524. hal_srng_to_hal_ring_handle(hal_srng),
  525. &srng_params);
  526. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_paddr =
  527. srng_params.ring_base_paddr;
  528. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_vaddr =
  529. srng_params.ring_base_vaddr;
  530. soc->ipa_uc_rx_rsc.ipa_reo_ring_size =
  531. (srng_params.num_entries * srng_params.entry_size) << 2;
  532. addr_offset = (unsigned long)(hal_srng->u.dst_ring.tp_addr) -
  533. (unsigned long)(hal_soc->dev_base_addr);
  534. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr =
  535. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  536. dp_info("IPA REO_DEST Ring addr_offset=%x, dev_base_paddr=%x, tp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  537. (unsigned int)addr_offset,
  538. (unsigned int)dev_base_paddr,
  539. (unsigned int)(soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr),
  540. (void *)soc->ipa_uc_rx_rsc.ipa_reo_ring_base_paddr,
  541. (void *)soc->ipa_uc_rx_rsc.ipa_reo_ring_base_vaddr,
  542. srng_params.num_entries,
  543. soc->ipa_uc_rx_rsc.ipa_reo_ring_size);
  544. hal_srng = (struct hal_srng *)
  545. pdev->rx_refill_buf_ring2.hal_srng;
  546. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  547. hal_srng_to_hal_ring_handle(hal_srng),
  548. &srng_params);
  549. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_paddr =
  550. srng_params.ring_base_paddr;
  551. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_vaddr =
  552. srng_params.ring_base_vaddr;
  553. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_size =
  554. (srng_params.num_entries * srng_params.entry_size) << 2;
  555. hp_addr = hal_srng_get_hp_addr(hal_soc_to_hal_soc_handle(hal_soc),
  556. hal_srng_to_hal_ring_handle(hal_srng));
  557. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr =
  558. qdf_mem_paddr_from_dmaaddr(soc->osdev, hp_addr);
  559. dp_info("IPA REFILL_BUF Ring hp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  560. (unsigned int)(soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr),
  561. (void *)soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_paddr,
  562. (void *)soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_vaddr,
  563. srng_params.num_entries,
  564. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_size);
  565. /*
  566. * Set DEST_RING_MAPPING_4 to SW2 as default value for
  567. * DESTINATION_RING_CTRL_IX_0.
  568. */
  569. ix0 = HAL_REO_REMAP_IX0(REO_REMAP_TCL, 0) |
  570. HAL_REO_REMAP_IX0(REO_REMAP_SW1, 1) |
  571. HAL_REO_REMAP_IX0(REO_REMAP_SW2, 2) |
  572. HAL_REO_REMAP_IX0(REO_REMAP_SW3, 3) |
  573. HAL_REO_REMAP_IX0(REO_REMAP_SW2, 4) |
  574. HAL_REO_REMAP_IX0(REO_REMAP_RELEASE, 5) |
  575. HAL_REO_REMAP_IX0(REO_REMAP_FW, 6) |
  576. HAL_REO_REMAP_IX0(REO_REMAP_FW, 7);
  577. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL, NULL, NULL);
  578. return 0;
  579. }
  580. static QDF_STATUS dp_ipa_get_shared_mem_info(qdf_device_t osdev,
  581. qdf_shared_mem_t *shared_mem,
  582. void *cpu_addr,
  583. qdf_dma_addr_t dma_addr,
  584. uint32_t size)
  585. {
  586. qdf_dma_addr_t paddr;
  587. int ret;
  588. shared_mem->vaddr = cpu_addr;
  589. qdf_mem_set_dma_size(osdev, &shared_mem->mem_info, size);
  590. *qdf_mem_get_dma_addr_ptr(osdev, &shared_mem->mem_info) = dma_addr;
  591. paddr = qdf_mem_paddr_from_dmaaddr(osdev, dma_addr);
  592. qdf_mem_set_dma_pa(osdev, &shared_mem->mem_info, paddr);
  593. ret = qdf_mem_dma_get_sgtable(osdev->dev, &shared_mem->sgtable,
  594. shared_mem->vaddr, dma_addr, size);
  595. if (ret) {
  596. dp_err("Unable to get DMA sgtable");
  597. return QDF_STATUS_E_NOMEM;
  598. }
  599. qdf_dma_get_sgtable_dma_addr(&shared_mem->sgtable);
  600. return QDF_STATUS_SUCCESS;
  601. }
  602. QDF_STATUS dp_ipa_get_resource(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  603. {
  604. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  605. struct dp_pdev *pdev =
  606. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  607. struct dp_ipa_resources *ipa_res;
  608. if (!pdev) {
  609. dp_err("Invalid instance");
  610. return QDF_STATUS_E_FAILURE;
  611. }
  612. ipa_res = &pdev->ipa_resource;
  613. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  614. return QDF_STATUS_SUCCESS;
  615. ipa_res->tx_num_alloc_buffer =
  616. (uint32_t)soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt;
  617. dp_ipa_get_shared_mem_info(soc->osdev, &ipa_res->tx_ring,
  618. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_vaddr,
  619. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_paddr,
  620. soc->ipa_uc_tx_rsc.ipa_tcl_ring_size);
  621. dp_ipa_get_shared_mem_info(soc->osdev, &ipa_res->tx_comp_ring,
  622. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_vaddr,
  623. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_paddr,
  624. soc->ipa_uc_tx_rsc.ipa_wbm_ring_size);
  625. dp_ipa_get_shared_mem_info(soc->osdev, &ipa_res->rx_rdy_ring,
  626. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_vaddr,
  627. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_paddr,
  628. soc->ipa_uc_rx_rsc.ipa_reo_ring_size);
  629. dp_ipa_get_shared_mem_info(
  630. soc->osdev, &ipa_res->rx_refill_ring,
  631. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_vaddr,
  632. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_paddr,
  633. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_size);
  634. if (!qdf_mem_get_dma_addr(soc->osdev, &ipa_res->tx_ring.mem_info) ||
  635. !qdf_mem_get_dma_addr(soc->osdev,
  636. &ipa_res->tx_comp_ring.mem_info) ||
  637. !qdf_mem_get_dma_addr(soc->osdev, &ipa_res->rx_rdy_ring.mem_info) ||
  638. !qdf_mem_get_dma_addr(soc->osdev,
  639. &ipa_res->rx_refill_ring.mem_info))
  640. return QDF_STATUS_E_FAILURE;
  641. return QDF_STATUS_SUCCESS;
  642. }
  643. QDF_STATUS dp_ipa_set_doorbell_paddr(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  644. {
  645. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  646. struct dp_pdev *pdev =
  647. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  648. struct dp_ipa_resources *ipa_res;
  649. struct hal_srng *wbm_srng = (struct hal_srng *)
  650. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  651. struct hal_srng *reo_srng = (struct hal_srng *)
  652. soc->reo_dest_ring[IPA_REO_DEST_RING_IDX].hal_srng;
  653. uint32_t tx_comp_doorbell_dmaaddr;
  654. uint32_t rx_ready_doorbell_dmaaddr;
  655. if (!pdev) {
  656. dp_err("Invalid instance");
  657. return QDF_STATUS_E_FAILURE;
  658. }
  659. ipa_res = &pdev->ipa_resource;
  660. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  661. return QDF_STATUS_SUCCESS;
  662. if (ipa_res->is_db_ddr_mapped)
  663. ipa_res->tx_comp_doorbell_vaddr =
  664. phys_to_virt(ipa_res->tx_comp_doorbell_paddr);
  665. else
  666. ipa_res->tx_comp_doorbell_vaddr =
  667. ioremap(ipa_res->tx_comp_doorbell_paddr, 4);
  668. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  669. pld_smmu_map(soc->osdev->dev, ipa_res->tx_comp_doorbell_paddr,
  670. &tx_comp_doorbell_dmaaddr, sizeof(uint32_t));
  671. ipa_res->tx_comp_doorbell_paddr = tx_comp_doorbell_dmaaddr;
  672. pld_smmu_map(soc->osdev->dev, ipa_res->rx_ready_doorbell_paddr,
  673. &rx_ready_doorbell_dmaaddr, sizeof(uint32_t));
  674. ipa_res->rx_ready_doorbell_paddr = rx_ready_doorbell_dmaaddr;
  675. }
  676. hal_srng_dst_set_hp_paddr(wbm_srng, ipa_res->tx_comp_doorbell_paddr);
  677. dp_info("paddr %pK vaddr %pK",
  678. (void *)ipa_res->tx_comp_doorbell_paddr,
  679. (void *)ipa_res->tx_comp_doorbell_vaddr);
  680. /*
  681. * For RX, REO module on Napier/Hastings does reordering on incoming
  682. * Ethernet packets and writes one or more descriptors to REO2IPA Rx
  683. * ring.It then updates the ring’s Write/Head ptr and rings a doorbell
  684. * to IPA.
  685. * Set the doorbell addr for the REO ring.
  686. */
  687. hal_srng_dst_set_hp_paddr(reo_srng, ipa_res->rx_ready_doorbell_paddr);
  688. return QDF_STATUS_SUCCESS;
  689. }
  690. QDF_STATUS dp_ipa_op_response(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  691. uint8_t *op_msg)
  692. {
  693. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  694. struct dp_pdev *pdev =
  695. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  696. if (!pdev) {
  697. dp_err("Invalid instance");
  698. return QDF_STATUS_E_FAILURE;
  699. }
  700. if (!wlan_cfg_is_ipa_enabled(pdev->soc->wlan_cfg_ctx))
  701. return QDF_STATUS_SUCCESS;
  702. if (pdev->ipa_uc_op_cb) {
  703. pdev->ipa_uc_op_cb(op_msg, pdev->usr_ctxt);
  704. } else {
  705. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  706. "%s: IPA callback function is not registered", __func__);
  707. qdf_mem_free(op_msg);
  708. return QDF_STATUS_E_FAILURE;
  709. }
  710. return QDF_STATUS_SUCCESS;
  711. }
  712. QDF_STATUS dp_ipa_register_op_cb(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  713. ipa_uc_op_cb_type op_cb,
  714. void *usr_ctxt)
  715. {
  716. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  717. struct dp_pdev *pdev =
  718. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  719. if (!pdev) {
  720. dp_err("Invalid instance");
  721. return QDF_STATUS_E_FAILURE;
  722. }
  723. if (!wlan_cfg_is_ipa_enabled(pdev->soc->wlan_cfg_ctx))
  724. return QDF_STATUS_SUCCESS;
  725. pdev->ipa_uc_op_cb = op_cb;
  726. pdev->usr_ctxt = usr_ctxt;
  727. return QDF_STATUS_SUCCESS;
  728. }
  729. void dp_ipa_deregister_op_cb(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  730. {
  731. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  732. struct dp_pdev *pdev = dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  733. if (!pdev) {
  734. dp_err("Invalid instance");
  735. return;
  736. }
  737. dp_debug("Deregister OP handler callback");
  738. pdev->ipa_uc_op_cb = NULL;
  739. pdev->usr_ctxt = NULL;
  740. }
  741. QDF_STATUS dp_ipa_get_stat(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  742. {
  743. /* TBD */
  744. return QDF_STATUS_SUCCESS;
  745. }
  746. /**
  747. * dp_tx_send_ipa_data_frame() - send IPA data frame
  748. * @soc_hdl: datapath soc handle
  749. * @vdev_id: id of the virtual device
  750. * @skb: skb to transmit
  751. *
  752. * Return: skb/ NULL is for success
  753. */
  754. qdf_nbuf_t dp_tx_send_ipa_data_frame(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  755. qdf_nbuf_t skb)
  756. {
  757. qdf_nbuf_t ret;
  758. /* Terminate the (single-element) list of tx frames */
  759. qdf_nbuf_set_next(skb, NULL);
  760. ret = dp_tx_send(soc_hdl, vdev_id, skb);
  761. if (ret) {
  762. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  763. "%s: Failed to tx", __func__);
  764. return ret;
  765. }
  766. return NULL;
  767. }
  768. QDF_STATUS dp_ipa_enable_autonomy(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  769. {
  770. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  771. struct dp_pdev *pdev =
  772. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  773. uint32_t ix0;
  774. uint32_t ix2;
  775. if (!pdev) {
  776. dp_err("Invalid instance");
  777. return QDF_STATUS_E_FAILURE;
  778. }
  779. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  780. return QDF_STATUS_SUCCESS;
  781. if (!hif_is_target_ready(HIF_GET_SOFTC(soc->hif_handle)))
  782. return QDF_STATUS_E_AGAIN;
  783. /* Call HAL API to remap REO rings to REO2IPA ring */
  784. ix0 = HAL_REO_REMAP_IX0(REO_REMAP_TCL, 0) |
  785. HAL_REO_REMAP_IX0(REO_REMAP_SW4, 1) |
  786. HAL_REO_REMAP_IX0(REO_REMAP_SW1, 2) |
  787. HAL_REO_REMAP_IX0(REO_REMAP_SW4, 3) |
  788. HAL_REO_REMAP_IX0(REO_REMAP_SW4, 4) |
  789. HAL_REO_REMAP_IX0(REO_REMAP_RELEASE, 5) |
  790. HAL_REO_REMAP_IX0(REO_REMAP_FW, 6) |
  791. HAL_REO_REMAP_IX0(REO_REMAP_FW, 7);
  792. if (wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  793. ix2 = HAL_REO_REMAP_IX2(REO_REMAP_SW4, 16) |
  794. HAL_REO_REMAP_IX2(REO_REMAP_SW4, 17) |
  795. HAL_REO_REMAP_IX2(REO_REMAP_SW4, 18) |
  796. HAL_REO_REMAP_IX2(REO_REMAP_SW4, 19) |
  797. HAL_REO_REMAP_IX2(REO_REMAP_SW4, 20) |
  798. HAL_REO_REMAP_IX2(REO_REMAP_SW4, 21) |
  799. HAL_REO_REMAP_IX2(REO_REMAP_SW4, 22) |
  800. HAL_REO_REMAP_IX2(REO_REMAP_SW4, 23);
  801. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL,
  802. &ix2, &ix2);
  803. dp_ipa_reo_remap_history_add(ix0, ix2, ix2);
  804. } else {
  805. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL,
  806. NULL, NULL);
  807. dp_ipa_reo_remap_history_add(ix0, 0, 0);
  808. }
  809. return QDF_STATUS_SUCCESS;
  810. }
  811. QDF_STATUS dp_ipa_disable_autonomy(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  812. {
  813. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  814. struct dp_pdev *pdev =
  815. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  816. uint32_t ix0;
  817. uint32_t ix2;
  818. uint32_t ix3;
  819. if (!pdev) {
  820. dp_err("Invalid instance");
  821. return QDF_STATUS_E_FAILURE;
  822. }
  823. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  824. return QDF_STATUS_SUCCESS;
  825. if (!hif_is_target_ready(HIF_GET_SOFTC(soc->hif_handle)))
  826. return QDF_STATUS_E_AGAIN;
  827. /* Call HAL API to remap REO rings to REO2IPA ring */
  828. ix0 = HAL_REO_REMAP_IX0(REO_REMAP_TCL, 0) |
  829. HAL_REO_REMAP_IX0(REO_REMAP_SW1, 1) |
  830. HAL_REO_REMAP_IX0(REO_REMAP_SW2, 2) |
  831. HAL_REO_REMAP_IX0(REO_REMAP_SW3, 3) |
  832. HAL_REO_REMAP_IX0(REO_REMAP_SW2, 4) |
  833. HAL_REO_REMAP_IX0(REO_REMAP_RELEASE, 5) |
  834. HAL_REO_REMAP_IX0(REO_REMAP_FW, 6) |
  835. HAL_REO_REMAP_IX0(REO_REMAP_FW, 7);
  836. if (wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  837. dp_reo_remap_config(soc, &ix2, &ix3);
  838. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL,
  839. &ix2, &ix3);
  840. dp_ipa_reo_remap_history_add(ix0, ix2, ix3);
  841. } else {
  842. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL,
  843. NULL, NULL);
  844. dp_ipa_reo_remap_history_add(ix0, 0, 0);
  845. }
  846. return QDF_STATUS_SUCCESS;
  847. }
  848. /* This should be configurable per H/W configuration enable status */
  849. #define L3_HEADER_PADDING 2
  850. #ifdef CONFIG_IPA_WDI_UNIFIED_API
  851. #ifndef QCA_LL_TX_FLOW_CONTROL_V2
  852. static inline void dp_setup_mcc_sys_pipes(
  853. qdf_ipa_sys_connect_params_t *sys_in,
  854. qdf_ipa_wdi_conn_in_params_t *pipe_in)
  855. {
  856. /* Setup MCC sys pipe */
  857. QDF_IPA_WDI_CONN_IN_PARAMS_NUM_SYS_PIPE_NEEDED(pipe_in) =
  858. DP_IPA_MAX_IFACE;
  859. for (int i = 0; i < DP_IPA_MAX_IFACE; i++)
  860. memcpy(&QDF_IPA_WDI_CONN_IN_PARAMS_SYS_IN(pipe_in)[i],
  861. &sys_in[i], sizeof(qdf_ipa_sys_connect_params_t));
  862. }
  863. #else
  864. static inline void dp_setup_mcc_sys_pipes(
  865. qdf_ipa_sys_connect_params_t *sys_in,
  866. qdf_ipa_wdi_conn_in_params_t *pipe_in)
  867. {
  868. QDF_IPA_WDI_CONN_IN_PARAMS_NUM_SYS_PIPE_NEEDED(pipe_in) = 0;
  869. }
  870. #endif
  871. static void dp_ipa_wdi_tx_params(struct dp_soc *soc,
  872. struct dp_ipa_resources *ipa_res,
  873. qdf_ipa_wdi_pipe_setup_info_t *tx,
  874. bool over_gsi)
  875. {
  876. struct tcl_data_cmd *tcl_desc_ptr;
  877. uint8_t *desc_addr;
  878. uint32_t desc_size;
  879. if (over_gsi)
  880. QDF_IPA_WDI_SETUP_INFO_CLIENT(tx) = IPA_CLIENT_WLAN2_CONS;
  881. else
  882. QDF_IPA_WDI_SETUP_INFO_CLIENT(tx) = IPA_CLIENT_WLAN1_CONS;
  883. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(tx) =
  884. qdf_mem_get_dma_addr(soc->osdev,
  885. &ipa_res->tx_comp_ring.mem_info);
  886. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(tx) =
  887. qdf_mem_get_dma_size(soc->osdev,
  888. &ipa_res->tx_comp_ring.mem_info);
  889. /* WBM Tail Pointer Address */
  890. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(tx) =
  891. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr;
  892. QDF_IPA_WDI_SETUP_INFO_IS_TXR_RN_DB_PCIE_ADDR(tx) = true;
  893. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(tx) =
  894. qdf_mem_get_dma_addr(soc->osdev,
  895. &ipa_res->tx_ring.mem_info);
  896. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(tx) =
  897. qdf_mem_get_dma_size(soc->osdev,
  898. &ipa_res->tx_ring.mem_info);
  899. /* TCL Head Pointer Address */
  900. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(tx) =
  901. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr;
  902. QDF_IPA_WDI_SETUP_INFO_IS_EVT_RN_DB_PCIE_ADDR(tx) = true;
  903. QDF_IPA_WDI_SETUP_INFO_NUM_PKT_BUFFERS(tx) =
  904. ipa_res->tx_num_alloc_buffer;
  905. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(tx) = 0;
  906. /* Preprogram TCL descriptor */
  907. desc_addr =
  908. (uint8_t *)QDF_IPA_WDI_SETUP_INFO_DESC_FORMAT_TEMPLATE(tx);
  909. desc_size = sizeof(struct tcl_data_cmd);
  910. HAL_TX_DESC_SET_TLV_HDR(desc_addr, HAL_TX_TCL_DATA_TAG, desc_size);
  911. tcl_desc_ptr = (struct tcl_data_cmd *)
  912. (QDF_IPA_WDI_SETUP_INFO_DESC_FORMAT_TEMPLATE(tx) + 1);
  913. tcl_desc_ptr->buf_addr_info.return_buffer_manager =
  914. HAL_RX_BUF_RBM_SW2_BM;
  915. tcl_desc_ptr->addrx_en = 1; /* Address X search enable in ASE */
  916. tcl_desc_ptr->encap_type = HAL_TX_ENCAP_TYPE_ETHERNET;
  917. tcl_desc_ptr->packet_offset = 2; /* padding for alignment */
  918. }
  919. static void dp_ipa_wdi_rx_params(struct dp_soc *soc,
  920. struct dp_ipa_resources *ipa_res,
  921. qdf_ipa_wdi_pipe_setup_info_t *rx,
  922. bool over_gsi)
  923. {
  924. if (over_gsi)
  925. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) =
  926. IPA_CLIENT_WLAN2_PROD;
  927. else
  928. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) =
  929. IPA_CLIENT_WLAN1_PROD;
  930. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(rx) =
  931. qdf_mem_get_dma_addr(soc->osdev,
  932. &ipa_res->rx_rdy_ring.mem_info);
  933. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(rx) =
  934. qdf_mem_get_dma_size(soc->osdev,
  935. &ipa_res->rx_rdy_ring.mem_info);
  936. /* REO Tail Pointer Address */
  937. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(rx) =
  938. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr;
  939. QDF_IPA_WDI_SETUP_INFO_IS_TXR_RN_DB_PCIE_ADDR(rx) = true;
  940. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(rx) =
  941. qdf_mem_get_dma_addr(soc->osdev,
  942. &ipa_res->rx_refill_ring.mem_info);
  943. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(rx) =
  944. qdf_mem_get_dma_size(soc->osdev,
  945. &ipa_res->rx_refill_ring.mem_info);
  946. /* FW Head Pointer Address */
  947. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(rx) =
  948. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr;
  949. QDF_IPA_WDI_SETUP_INFO_IS_EVT_RN_DB_PCIE_ADDR(rx) = false;
  950. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(rx) =
  951. RX_PKT_TLVS_LEN + L3_HEADER_PADDING;
  952. }
  953. static void
  954. dp_ipa_wdi_tx_smmu_params(struct dp_soc *soc,
  955. struct dp_ipa_resources *ipa_res,
  956. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu,
  957. bool over_gsi)
  958. {
  959. struct tcl_data_cmd *tcl_desc_ptr;
  960. uint8_t *desc_addr;
  961. uint32_t desc_size;
  962. if (over_gsi)
  963. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(tx_smmu) =
  964. IPA_CLIENT_WLAN2_CONS;
  965. else
  966. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(tx_smmu) =
  967. IPA_CLIENT_WLAN1_CONS;
  968. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_BASE(tx_smmu),
  969. &ipa_res->tx_comp_ring.sgtable,
  970. sizeof(sgtable_t));
  971. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_SIZE(tx_smmu) =
  972. qdf_mem_get_dma_size(soc->osdev,
  973. &ipa_res->tx_comp_ring.mem_info);
  974. /* WBM Tail Pointer Address */
  975. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_DOORBELL_PA(tx_smmu) =
  976. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr;
  977. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_TXR_RN_DB_PCIE_ADDR(tx_smmu) = true;
  978. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_BASE(tx_smmu),
  979. &ipa_res->tx_ring.sgtable,
  980. sizeof(sgtable_t));
  981. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_SIZE(tx_smmu) =
  982. qdf_mem_get_dma_size(soc->osdev,
  983. &ipa_res->tx_ring.mem_info);
  984. /* TCL Head Pointer Address */
  985. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_DOORBELL_PA(tx_smmu) =
  986. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr;
  987. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_EVT_RN_DB_PCIE_ADDR(tx_smmu) = true;
  988. QDF_IPA_WDI_SETUP_INFO_SMMU_NUM_PKT_BUFFERS(tx_smmu) =
  989. ipa_res->tx_num_alloc_buffer;
  990. QDF_IPA_WDI_SETUP_INFO_SMMU_PKT_OFFSET(tx_smmu) = 0;
  991. /* Preprogram TCL descriptor */
  992. desc_addr = (uint8_t *)QDF_IPA_WDI_SETUP_INFO_SMMU_DESC_FORMAT_TEMPLATE(
  993. tx_smmu);
  994. desc_size = sizeof(struct tcl_data_cmd);
  995. HAL_TX_DESC_SET_TLV_HDR(desc_addr, HAL_TX_TCL_DATA_TAG, desc_size);
  996. tcl_desc_ptr = (struct tcl_data_cmd *)
  997. (QDF_IPA_WDI_SETUP_INFO_SMMU_DESC_FORMAT_TEMPLATE(tx_smmu) + 1);
  998. tcl_desc_ptr->buf_addr_info.return_buffer_manager =
  999. HAL_RX_BUF_RBM_SW2_BM;
  1000. tcl_desc_ptr->addrx_en = 1; /* Address X search enable in ASE */
  1001. tcl_desc_ptr->encap_type = HAL_TX_ENCAP_TYPE_ETHERNET;
  1002. tcl_desc_ptr->packet_offset = 2; /* padding for alignment */
  1003. }
  1004. static void
  1005. dp_ipa_wdi_rx_smmu_params(struct dp_soc *soc,
  1006. struct dp_ipa_resources *ipa_res,
  1007. qdf_ipa_wdi_pipe_setup_info_smmu_t *rx_smmu,
  1008. bool over_gsi)
  1009. {
  1010. if (over_gsi)
  1011. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  1012. IPA_CLIENT_WLAN2_PROD;
  1013. else
  1014. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  1015. IPA_CLIENT_WLAN1_PROD;
  1016. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_BASE(rx_smmu),
  1017. &ipa_res->rx_rdy_ring.sgtable,
  1018. sizeof(sgtable_t));
  1019. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_SIZE(rx_smmu) =
  1020. qdf_mem_get_dma_size(soc->osdev,
  1021. &ipa_res->rx_rdy_ring.mem_info);
  1022. /* REO Tail Pointer Address */
  1023. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_DOORBELL_PA(rx_smmu) =
  1024. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr;
  1025. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_TXR_RN_DB_PCIE_ADDR(rx_smmu) = true;
  1026. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_BASE(rx_smmu),
  1027. &ipa_res->rx_refill_ring.sgtable,
  1028. sizeof(sgtable_t));
  1029. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_SIZE(rx_smmu) =
  1030. qdf_mem_get_dma_size(soc->osdev,
  1031. &ipa_res->rx_refill_ring.mem_info);
  1032. /* FW Head Pointer Address */
  1033. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_DOORBELL_PA(rx_smmu) =
  1034. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr;
  1035. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_EVT_RN_DB_PCIE_ADDR(rx_smmu) = false;
  1036. QDF_IPA_WDI_SETUP_INFO_SMMU_PKT_OFFSET(rx_smmu) =
  1037. RX_PKT_TLVS_LEN + L3_HEADER_PADDING;
  1038. }
  1039. QDF_STATUS dp_ipa_setup(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  1040. void *ipa_i2w_cb, void *ipa_w2i_cb,
  1041. void *ipa_wdi_meter_notifier_cb,
  1042. uint32_t ipa_desc_size, void *ipa_priv,
  1043. bool is_rm_enabled, uint32_t *tx_pipe_handle,
  1044. uint32_t *rx_pipe_handle, bool is_smmu_enabled,
  1045. qdf_ipa_sys_connect_params_t *sys_in, bool over_gsi)
  1046. {
  1047. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1048. struct dp_pdev *pdev =
  1049. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1050. struct dp_ipa_resources *ipa_res;
  1051. qdf_ipa_ep_cfg_t *tx_cfg;
  1052. qdf_ipa_ep_cfg_t *rx_cfg;
  1053. qdf_ipa_wdi_pipe_setup_info_t *tx = NULL;
  1054. qdf_ipa_wdi_pipe_setup_info_t *rx = NULL;
  1055. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu;
  1056. qdf_ipa_wdi_pipe_setup_info_smmu_t *rx_smmu;
  1057. qdf_ipa_wdi_conn_in_params_t pipe_in;
  1058. qdf_ipa_wdi_conn_out_params_t pipe_out;
  1059. int ret;
  1060. if (!pdev) {
  1061. dp_err("Invalid instance");
  1062. return QDF_STATUS_E_FAILURE;
  1063. }
  1064. ipa_res = &pdev->ipa_resource;
  1065. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1066. return QDF_STATUS_SUCCESS;
  1067. qdf_mem_zero(&pipe_in, sizeof(pipe_in));
  1068. qdf_mem_zero(&pipe_out, sizeof(pipe_out));
  1069. if (is_smmu_enabled)
  1070. QDF_IPA_WDI_CONN_IN_PARAMS_SMMU_ENABLED(&pipe_in) = true;
  1071. else
  1072. QDF_IPA_WDI_CONN_IN_PARAMS_SMMU_ENABLED(&pipe_in) = false;
  1073. dp_setup_mcc_sys_pipes(sys_in, &pipe_in);
  1074. /* TX PIPE */
  1075. if (QDF_IPA_WDI_CONN_IN_PARAMS_SMMU_ENABLED(&pipe_in)) {
  1076. tx_smmu = &QDF_IPA_WDI_CONN_IN_PARAMS_TX_SMMU(&pipe_in);
  1077. tx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(tx_smmu);
  1078. } else {
  1079. tx = &QDF_IPA_WDI_CONN_IN_PARAMS_TX(&pipe_in);
  1080. tx_cfg = &QDF_IPA_WDI_SETUP_INFO_EP_CFG(tx);
  1081. }
  1082. QDF_IPA_EP_CFG_NAT_EN(tx_cfg) = IPA_BYPASS_NAT;
  1083. QDF_IPA_EP_CFG_HDR_LEN(tx_cfg) = DP_IPA_UC_WLAN_TX_HDR_LEN;
  1084. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE_VALID(tx_cfg) = 0;
  1085. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE(tx_cfg) = 0;
  1086. QDF_IPA_EP_CFG_HDR_ADDITIONAL_CONST_LEN(tx_cfg) = 0;
  1087. QDF_IPA_EP_CFG_MODE(tx_cfg) = IPA_BASIC;
  1088. QDF_IPA_EP_CFG_HDR_LITTLE_ENDIAN(tx_cfg) = true;
  1089. /**
  1090. * Transfer Ring: WBM Ring
  1091. * Transfer Ring Doorbell PA: WBM Tail Pointer Address
  1092. * Event Ring: TCL ring
  1093. * Event Ring Doorbell PA: TCL Head Pointer Address
  1094. */
  1095. if (is_smmu_enabled)
  1096. dp_ipa_wdi_tx_smmu_params(soc, ipa_res, tx_smmu, over_gsi);
  1097. else
  1098. dp_ipa_wdi_tx_params(soc, ipa_res, tx, over_gsi);
  1099. /* RX PIPE */
  1100. if (QDF_IPA_WDI_CONN_IN_PARAMS_SMMU_ENABLED(&pipe_in)) {
  1101. rx_smmu = &QDF_IPA_WDI_CONN_IN_PARAMS_RX_SMMU(&pipe_in);
  1102. rx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(rx_smmu);
  1103. } else {
  1104. rx = &QDF_IPA_WDI_CONN_IN_PARAMS_RX(&pipe_in);
  1105. rx_cfg = &QDF_IPA_WDI_SETUP_INFO_EP_CFG(rx);
  1106. }
  1107. QDF_IPA_EP_CFG_NAT_EN(rx_cfg) = IPA_BYPASS_NAT;
  1108. QDF_IPA_EP_CFG_HDR_LEN(rx_cfg) = DP_IPA_UC_WLAN_RX_HDR_LEN;
  1109. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE_VALID(rx_cfg) = 1;
  1110. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE(rx_cfg) = 0;
  1111. QDF_IPA_EP_CFG_HDR_ADDITIONAL_CONST_LEN(rx_cfg) = 0;
  1112. QDF_IPA_EP_CFG_HDR_OFST_METADATA_VALID(rx_cfg) = 0;
  1113. QDF_IPA_EP_CFG_HDR_METADATA_REG_VALID(rx_cfg) = 1;
  1114. QDF_IPA_EP_CFG_MODE(rx_cfg) = IPA_BASIC;
  1115. QDF_IPA_EP_CFG_HDR_LITTLE_ENDIAN(rx_cfg) = true;
  1116. /**
  1117. * Transfer Ring: REO Ring
  1118. * Transfer Ring Doorbell PA: REO Tail Pointer Address
  1119. * Event Ring: FW ring
  1120. * Event Ring Doorbell PA: FW Head Pointer Address
  1121. */
  1122. if (is_smmu_enabled)
  1123. dp_ipa_wdi_rx_smmu_params(soc, ipa_res, rx_smmu, over_gsi);
  1124. else
  1125. dp_ipa_wdi_rx_params(soc, ipa_res, rx, over_gsi);
  1126. QDF_IPA_WDI_CONN_IN_PARAMS_NOTIFY(&pipe_in) = ipa_w2i_cb;
  1127. QDF_IPA_WDI_CONN_IN_PARAMS_PRIV(&pipe_in) = ipa_priv;
  1128. /* Connect WDI IPA PIPEs */
  1129. ret = qdf_ipa_wdi_conn_pipes(&pipe_in, &pipe_out);
  1130. if (ret) {
  1131. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1132. "%s: ipa_wdi_conn_pipes: IPA pipe setup failed: ret=%d",
  1133. __func__, ret);
  1134. return QDF_STATUS_E_FAILURE;
  1135. }
  1136. /* IPA uC Doorbell registers */
  1137. dp_info("Tx DB PA=0x%x, Rx DB PA=0x%x",
  1138. (unsigned int)QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_PA(&pipe_out),
  1139. (unsigned int)QDF_IPA_WDI_CONN_OUT_PARAMS_RX_UC_DB_PA(&pipe_out));
  1140. ipa_res->tx_comp_doorbell_paddr =
  1141. QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_PA(&pipe_out);
  1142. ipa_res->rx_ready_doorbell_paddr =
  1143. QDF_IPA_WDI_CONN_OUT_PARAMS_RX_UC_DB_PA(&pipe_out);
  1144. ipa_res->is_db_ddr_mapped =
  1145. QDF_IPA_WDI_CONN_OUT_PARAMS_IS_DB_DDR_MAPPED(&pipe_out);
  1146. soc->ipa_first_tx_db_access = true;
  1147. return QDF_STATUS_SUCCESS;
  1148. }
  1149. /**
  1150. * dp_ipa_setup_iface() - Setup IPA header and register interface
  1151. * @ifname: Interface name
  1152. * @mac_addr: Interface MAC address
  1153. * @prod_client: IPA prod client type
  1154. * @cons_client: IPA cons client type
  1155. * @session_id: Session ID
  1156. * @is_ipv6_enabled: Is IPV6 enabled or not
  1157. *
  1158. * Return: QDF_STATUS
  1159. */
  1160. QDF_STATUS dp_ipa_setup_iface(char *ifname, uint8_t *mac_addr,
  1161. qdf_ipa_client_type_t prod_client,
  1162. qdf_ipa_client_type_t cons_client,
  1163. uint8_t session_id, bool is_ipv6_enabled)
  1164. {
  1165. qdf_ipa_wdi_reg_intf_in_params_t in;
  1166. qdf_ipa_wdi_hdr_info_t hdr_info;
  1167. struct dp_ipa_uc_tx_hdr uc_tx_hdr;
  1168. struct dp_ipa_uc_tx_hdr uc_tx_hdr_v6;
  1169. int ret = -EINVAL;
  1170. dp_debug("Add Partial hdr: %s, "QDF_MAC_ADDR_FMT, ifname,
  1171. QDF_MAC_ADDR_REF(mac_addr));
  1172. qdf_mem_zero(&hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  1173. qdf_ether_addr_copy(uc_tx_hdr.eth.h_source, mac_addr);
  1174. /* IPV4 header */
  1175. uc_tx_hdr.eth.h_proto = qdf_htons(ETH_P_IP);
  1176. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) = (uint8_t *)&uc_tx_hdr;
  1177. QDF_IPA_WDI_HDR_INFO_HDR_LEN(&hdr_info) = DP_IPA_UC_WLAN_TX_HDR_LEN;
  1178. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(&hdr_info) = IPA_HDR_L2_ETHERNET_II;
  1179. QDF_IPA_WDI_HDR_INFO_DST_MAC_ADDR_OFFSET(&hdr_info) =
  1180. DP_IPA_UC_WLAN_HDR_DES_MAC_OFFSET;
  1181. QDF_IPA_WDI_REG_INTF_IN_PARAMS_NETDEV_NAME(&in) = ifname;
  1182. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(&in)[IPA_IP_v4]),
  1183. &hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  1184. QDF_IPA_WDI_REG_INTF_IN_PARAMS_ALT_DST_PIPE(&in) = cons_client;
  1185. QDF_IPA_WDI_REG_INTF_IN_PARAMS_IS_META_DATA_VALID(&in) = 1;
  1186. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA(&in) =
  1187. htonl(session_id << 16);
  1188. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA_MASK(&in) = htonl(0x00FF0000);
  1189. /* IPV6 header */
  1190. if (is_ipv6_enabled) {
  1191. qdf_mem_copy(&uc_tx_hdr_v6, &uc_tx_hdr,
  1192. DP_IPA_UC_WLAN_TX_HDR_LEN);
  1193. uc_tx_hdr_v6.eth.h_proto = qdf_htons(ETH_P_IPV6);
  1194. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) = (uint8_t *)&uc_tx_hdr_v6;
  1195. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(&in)[IPA_IP_v6]),
  1196. &hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  1197. }
  1198. dp_debug("registering for session_id: %u", session_id);
  1199. ret = qdf_ipa_wdi_reg_intf(&in);
  1200. if (ret) {
  1201. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1202. "%s: ipa_wdi_reg_intf: register IPA interface falied: ret=%d",
  1203. __func__, ret);
  1204. return QDF_STATUS_E_FAILURE;
  1205. }
  1206. return QDF_STATUS_SUCCESS;
  1207. }
  1208. #else /* CONFIG_IPA_WDI_UNIFIED_API */
  1209. QDF_STATUS dp_ipa_setup(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  1210. void *ipa_i2w_cb, void *ipa_w2i_cb,
  1211. void *ipa_wdi_meter_notifier_cb,
  1212. uint32_t ipa_desc_size, void *ipa_priv,
  1213. bool is_rm_enabled, uint32_t *tx_pipe_handle,
  1214. uint32_t *rx_pipe_handle)
  1215. {
  1216. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1217. struct dp_pdev *pdev =
  1218. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1219. struct dp_ipa_resources *ipa_res;
  1220. qdf_ipa_wdi_pipe_setup_info_t *tx;
  1221. qdf_ipa_wdi_pipe_setup_info_t *rx;
  1222. qdf_ipa_wdi_conn_in_params_t pipe_in;
  1223. qdf_ipa_wdi_conn_out_params_t pipe_out;
  1224. struct tcl_data_cmd *tcl_desc_ptr;
  1225. uint8_t *desc_addr;
  1226. uint32_t desc_size;
  1227. int ret;
  1228. if (!pdev) {
  1229. dp_err("Invalid instance");
  1230. return QDF_STATUS_E_FAILURE;
  1231. }
  1232. ipa_res = &pdev->ipa_resource;
  1233. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1234. return QDF_STATUS_SUCCESS;
  1235. qdf_mem_zero(&tx, sizeof(qdf_ipa_wdi_pipe_setup_info_t));
  1236. qdf_mem_zero(&rx, sizeof(qdf_ipa_wdi_pipe_setup_info_t));
  1237. qdf_mem_zero(&pipe_in, sizeof(pipe_in));
  1238. qdf_mem_zero(&pipe_out, sizeof(pipe_out));
  1239. /* TX PIPE */
  1240. /**
  1241. * Transfer Ring: WBM Ring
  1242. * Transfer Ring Doorbell PA: WBM Tail Pointer Address
  1243. * Event Ring: TCL ring
  1244. * Event Ring Doorbell PA: TCL Head Pointer Address
  1245. */
  1246. tx = &QDF_IPA_WDI_CONN_IN_PARAMS_TX(&pipe_in);
  1247. QDF_IPA_WDI_SETUP_INFO_NAT_EN(tx) = IPA_BYPASS_NAT;
  1248. QDF_IPA_WDI_SETUP_INFO_HDR_LEN(tx) = DP_IPA_UC_WLAN_TX_HDR_LEN;
  1249. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_PKT_SIZE_VALID(tx) = 0;
  1250. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_PKT_SIZE(tx) = 0;
  1251. QDF_IPA_WDI_SETUP_INFO_HDR_ADDITIONAL_CONST_LEN(tx) = 0;
  1252. QDF_IPA_WDI_SETUP_INFO_MODE(tx) = IPA_BASIC;
  1253. QDF_IPA_WDI_SETUP_INFO_HDR_LITTLE_ENDIAN(tx) = true;
  1254. QDF_IPA_WDI_SETUP_INFO_CLIENT(tx) = IPA_CLIENT_WLAN1_CONS;
  1255. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(tx) =
  1256. ipa_res->tx_comp_ring_base_paddr;
  1257. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(tx) =
  1258. ipa_res->tx_comp_ring_size;
  1259. /* WBM Tail Pointer Address */
  1260. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(tx) =
  1261. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr;
  1262. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(tx) =
  1263. ipa_res->tx_ring_base_paddr;
  1264. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(tx) = ipa_res->tx_ring_size;
  1265. /* TCL Head Pointer Address */
  1266. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(tx) =
  1267. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr;
  1268. QDF_IPA_WDI_SETUP_INFO_NUM_PKT_BUFFERS(tx) =
  1269. ipa_res->tx_num_alloc_buffer;
  1270. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(tx) = 0;
  1271. /* Preprogram TCL descriptor */
  1272. desc_addr =
  1273. (uint8_t *)QDF_IPA_WDI_SETUP_INFO_DESC_FORMAT_TEMPLATE(tx);
  1274. desc_size = sizeof(struct tcl_data_cmd);
  1275. HAL_TX_DESC_SET_TLV_HDR(desc_addr, HAL_TX_TCL_DATA_TAG, desc_size);
  1276. tcl_desc_ptr = (struct tcl_data_cmd *)
  1277. (QDF_IPA_WDI_SETUP_INFO_DESC_FORMAT_TEMPLATE(tx) + 1);
  1278. tcl_desc_ptr->buf_addr_info.return_buffer_manager =
  1279. HAL_RX_BUF_RBM_SW2_BM;
  1280. tcl_desc_ptr->addrx_en = 1; /* Address X search enable in ASE */
  1281. tcl_desc_ptr->encap_type = HAL_TX_ENCAP_TYPE_ETHERNET;
  1282. tcl_desc_ptr->packet_offset = 2; /* padding for alignment */
  1283. /* RX PIPE */
  1284. /**
  1285. * Transfer Ring: REO Ring
  1286. * Transfer Ring Doorbell PA: REO Tail Pointer Address
  1287. * Event Ring: FW ring
  1288. * Event Ring Doorbell PA: FW Head Pointer Address
  1289. */
  1290. rx = &QDF_IPA_WDI_CONN_IN_PARAMS_RX(&pipe_in);
  1291. QDF_IPA_WDI_SETUP_INFO_NAT_EN(rx) = IPA_BYPASS_NAT;
  1292. QDF_IPA_WDI_SETUP_INFO_HDR_LEN(rx) = DP_IPA_UC_WLAN_RX_HDR_LEN;
  1293. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_PKT_SIZE_VALID(rx) = 0;
  1294. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_PKT_SIZE(rx) = 0;
  1295. QDF_IPA_WDI_SETUP_INFO_HDR_ADDITIONAL_CONST_LEN(rx) = 0;
  1296. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_METADATA_VALID(rx) = 0;
  1297. QDF_IPA_WDI_SETUP_INFO_HDR_METADATA_REG_VALID(rx) = 1;
  1298. QDF_IPA_WDI_SETUP_INFO_MODE(rx) = IPA_BASIC;
  1299. QDF_IPA_WDI_SETUP_INFO_HDR_LITTLE_ENDIAN(rx) = true;
  1300. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) = IPA_CLIENT_WLAN1_PROD;
  1301. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(rx) =
  1302. ipa_res->rx_rdy_ring_base_paddr;
  1303. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(rx) =
  1304. ipa_res->rx_rdy_ring_size;
  1305. /* REO Tail Pointer Address */
  1306. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(rx) =
  1307. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr;
  1308. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(rx) =
  1309. ipa_res->rx_refill_ring_base_paddr;
  1310. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(rx) =
  1311. ipa_res->rx_refill_ring_size;
  1312. /* FW Head Pointer Address */
  1313. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(rx) =
  1314. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr;
  1315. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(rx) = RX_PKT_TLVS_LEN +
  1316. L3_HEADER_PADDING;
  1317. QDF_IPA_WDI_CONN_IN_PARAMS_NOTIFY(&pipe_in) = ipa_w2i_cb;
  1318. QDF_IPA_WDI_CONN_IN_PARAMS_PRIV(&pipe_in) = ipa_priv;
  1319. /* Connect WDI IPA PIPE */
  1320. ret = qdf_ipa_wdi_conn_pipes(&pipe_in, &pipe_out);
  1321. if (ret) {
  1322. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1323. "%s: ipa_wdi_conn_pipes: IPA pipe setup failed: ret=%d",
  1324. __func__, ret);
  1325. return QDF_STATUS_E_FAILURE;
  1326. }
  1327. /* IPA uC Doorbell registers */
  1328. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  1329. "%s: Tx DB PA=0x%x, Rx DB PA=0x%x",
  1330. __func__,
  1331. (unsigned int)QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_PA(&pipe_out),
  1332. (unsigned int)QDF_IPA_WDI_CONN_OUT_PARAMS_RX_UC_DB_PA(&pipe_out));
  1333. ipa_res->tx_comp_doorbell_paddr =
  1334. QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_PA(&pipe_out);
  1335. ipa_res->tx_comp_doorbell_vaddr =
  1336. QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_VA(&pipe_out);
  1337. ipa_res->rx_ready_doorbell_paddr =
  1338. QDF_IPA_WDI_CONN_OUT_PARAMS_RX_UC_DB_PA(&pipe_out);
  1339. soc->ipa_first_tx_db_access = true;
  1340. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  1341. "%s: Tx: %s=%pK, %s=%d, %s=%pK, %s=%pK, %s=%d, %s=%pK, %s=%d, %s=%pK",
  1342. __func__,
  1343. "transfer_ring_base_pa",
  1344. (void *)QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(tx),
  1345. "transfer_ring_size",
  1346. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(tx),
  1347. "transfer_ring_doorbell_pa",
  1348. (void *)QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(tx),
  1349. "event_ring_base_pa",
  1350. (void *)QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(tx),
  1351. "event_ring_size",
  1352. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(tx),
  1353. "event_ring_doorbell_pa",
  1354. (void *)QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(tx),
  1355. "num_pkt_buffers",
  1356. QDF_IPA_WDI_SETUP_INFO_NUM_PKT_BUFFERS(tx),
  1357. "tx_comp_doorbell_paddr",
  1358. (void *)ipa_res->tx_comp_doorbell_paddr);
  1359. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  1360. "%s: Rx: %s=%pK, %s=%d, %s=%pK, %s=%pK, %s=%d, %s=%pK, %s=%d, %s=%pK",
  1361. __func__,
  1362. "transfer_ring_base_pa",
  1363. (void *)QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(rx),
  1364. "transfer_ring_size",
  1365. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(rx),
  1366. "transfer_ring_doorbell_pa",
  1367. (void *)QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(rx),
  1368. "event_ring_base_pa",
  1369. (void *)QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(rx),
  1370. "event_ring_size",
  1371. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(rx),
  1372. "event_ring_doorbell_pa",
  1373. (void *)QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(rx),
  1374. "num_pkt_buffers",
  1375. QDF_IPA_WDI_SETUP_INFO_NUM_PKT_BUFFERS(rx),
  1376. "tx_comp_doorbell_paddr",
  1377. (void *)ipa_res->rx_ready_doorbell_paddr);
  1378. return QDF_STATUS_SUCCESS;
  1379. }
  1380. /**
  1381. * dp_ipa_setup_iface() - Setup IPA header and register interface
  1382. * @ifname: Interface name
  1383. * @mac_addr: Interface MAC address
  1384. * @prod_client: IPA prod client type
  1385. * @cons_client: IPA cons client type
  1386. * @session_id: Session ID
  1387. * @is_ipv6_enabled: Is IPV6 enabled or not
  1388. *
  1389. * Return: QDF_STATUS
  1390. */
  1391. QDF_STATUS dp_ipa_setup_iface(char *ifname, uint8_t *mac_addr,
  1392. qdf_ipa_client_type_t prod_client,
  1393. qdf_ipa_client_type_t cons_client,
  1394. uint8_t session_id, bool is_ipv6_enabled)
  1395. {
  1396. qdf_ipa_wdi_reg_intf_in_params_t in;
  1397. qdf_ipa_wdi_hdr_info_t hdr_info;
  1398. struct dp_ipa_uc_tx_hdr uc_tx_hdr;
  1399. struct dp_ipa_uc_tx_hdr uc_tx_hdr_v6;
  1400. int ret = -EINVAL;
  1401. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  1402. "%s: Add Partial hdr: %s, "QDF_MAC_ADDR_FMT,
  1403. __func__, ifname, QDF_MAC_ADDR_REF(mac_addr));
  1404. qdf_mem_zero(&hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  1405. qdf_ether_addr_copy(uc_tx_hdr.eth.h_source, mac_addr);
  1406. /* IPV4 header */
  1407. uc_tx_hdr.eth.h_proto = qdf_htons(ETH_P_IP);
  1408. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) = (uint8_t *)&uc_tx_hdr;
  1409. QDF_IPA_WDI_HDR_INFO_HDR_LEN(&hdr_info) = DP_IPA_UC_WLAN_TX_HDR_LEN;
  1410. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(&hdr_info) = IPA_HDR_L2_ETHERNET_II;
  1411. QDF_IPA_WDI_HDR_INFO_DST_MAC_ADDR_OFFSET(&hdr_info) =
  1412. DP_IPA_UC_WLAN_HDR_DES_MAC_OFFSET;
  1413. QDF_IPA_WDI_REG_INTF_IN_PARAMS_NETDEV_NAME(&in) = ifname;
  1414. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(&in)[IPA_IP_v4]),
  1415. &hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  1416. QDF_IPA_WDI_REG_INTF_IN_PARAMS_IS_META_DATA_VALID(&in) = 1;
  1417. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA(&in) =
  1418. htonl(session_id << 16);
  1419. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA_MASK(&in) = htonl(0x00FF0000);
  1420. /* IPV6 header */
  1421. if (is_ipv6_enabled) {
  1422. qdf_mem_copy(&uc_tx_hdr_v6, &uc_tx_hdr,
  1423. DP_IPA_UC_WLAN_TX_HDR_LEN);
  1424. uc_tx_hdr_v6.eth.h_proto = qdf_htons(ETH_P_IPV6);
  1425. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) = (uint8_t *)&uc_tx_hdr_v6;
  1426. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(&in)[IPA_IP_v6]),
  1427. &hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  1428. }
  1429. ret = qdf_ipa_wdi_reg_intf(&in);
  1430. if (ret) {
  1431. dp_err("ipa_wdi_reg_intf: register IPA interface falied: ret=%d",
  1432. ret);
  1433. return QDF_STATUS_E_FAILURE;
  1434. }
  1435. return QDF_STATUS_SUCCESS;
  1436. }
  1437. #endif /* CONFIG_IPA_WDI_UNIFIED_API */
  1438. /**
  1439. * dp_ipa_cleanup() - Disconnect IPA pipes
  1440. * @soc_hdl: dp soc handle
  1441. * @pdev_id: dp pdev id
  1442. * @tx_pipe_handle: Tx pipe handle
  1443. * @rx_pipe_handle: Rx pipe handle
  1444. *
  1445. * Return: QDF_STATUS
  1446. */
  1447. QDF_STATUS dp_ipa_cleanup(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  1448. uint32_t tx_pipe_handle, uint32_t rx_pipe_handle)
  1449. {
  1450. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1451. QDF_STATUS status = QDF_STATUS_SUCCESS;
  1452. struct dp_ipa_resources *ipa_res;
  1453. struct dp_pdev *pdev;
  1454. int ret;
  1455. ret = qdf_ipa_wdi_disconn_pipes();
  1456. if (ret) {
  1457. dp_err("ipa_wdi_disconn_pipes: IPA pipe cleanup failed: ret=%d",
  1458. ret);
  1459. status = QDF_STATUS_E_FAILURE;
  1460. }
  1461. pdev = dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1462. if (qdf_unlikely(!pdev)) {
  1463. dp_err_rl("Invalid pdev for pdev_id %d", pdev_id);
  1464. status = QDF_STATUS_E_FAILURE;
  1465. goto exit;
  1466. }
  1467. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  1468. ipa_res = &pdev->ipa_resource;
  1469. /* unmap has to be the reverse order of smmu map */
  1470. ret = pld_smmu_unmap(soc->osdev->dev,
  1471. ipa_res->rx_ready_doorbell_paddr,
  1472. sizeof(uint32_t));
  1473. if (ret)
  1474. dp_err_rl("IPA RX DB smmu unmap failed");
  1475. ret = pld_smmu_unmap(soc->osdev->dev,
  1476. ipa_res->tx_comp_doorbell_paddr,
  1477. sizeof(uint32_t));
  1478. if (ret)
  1479. dp_err_rl("IPA TX DB smmu unmap failed");
  1480. }
  1481. exit:
  1482. return status;
  1483. }
  1484. /**
  1485. * dp_ipa_cleanup_iface() - Cleanup IPA header and deregister interface
  1486. * @ifname: Interface name
  1487. * @is_ipv6_enabled: Is IPV6 enabled or not
  1488. *
  1489. * Return: QDF_STATUS
  1490. */
  1491. QDF_STATUS dp_ipa_cleanup_iface(char *ifname, bool is_ipv6_enabled)
  1492. {
  1493. int ret;
  1494. ret = qdf_ipa_wdi_dereg_intf(ifname);
  1495. if (ret) {
  1496. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1497. "%s: ipa_wdi_dereg_intf: IPA pipe deregistration failed: ret=%d",
  1498. __func__, ret);
  1499. return QDF_STATUS_E_FAILURE;
  1500. }
  1501. return QDF_STATUS_SUCCESS;
  1502. }
  1503. QDF_STATUS dp_ipa_enable_pipes(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1504. {
  1505. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1506. struct dp_pdev *pdev =
  1507. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1508. struct hal_srng *wbm_srng = (struct hal_srng *)
  1509. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1510. struct dp_ipa_resources *ipa_res;
  1511. QDF_STATUS result;
  1512. if (!pdev) {
  1513. dp_err("Invalid instance");
  1514. return QDF_STATUS_E_FAILURE;
  1515. }
  1516. ipa_res = &pdev->ipa_resource;
  1517. qdf_atomic_set(&soc->ipa_pipes_enabled, 1);
  1518. dp_ipa_handle_rx_buf_pool_smmu_mapping(soc, pdev, true);
  1519. result = qdf_ipa_wdi_enable_pipes();
  1520. if (result) {
  1521. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1522. "%s: Enable WDI PIPE fail, code %d",
  1523. __func__, result);
  1524. qdf_atomic_set(&soc->ipa_pipes_enabled, 0);
  1525. dp_ipa_handle_rx_buf_pool_smmu_mapping(soc, pdev, false);
  1526. return QDF_STATUS_E_FAILURE;
  1527. }
  1528. if (soc->ipa_first_tx_db_access) {
  1529. hal_srng_dst_init_hp(
  1530. soc->hal_soc, wbm_srng,
  1531. ipa_res->tx_comp_doorbell_vaddr);
  1532. soc->ipa_first_tx_db_access = false;
  1533. }
  1534. return QDF_STATUS_SUCCESS;
  1535. }
  1536. #ifdef DEVICE_FORCE_WAKE_ENABLED
  1537. /*
  1538. * dp_ipa_get_tx_comp_pending_check() - Check if tx completions are pending.
  1539. * @soc: DP pdev Context
  1540. *
  1541. * Ring full condition is checked to find if buffers are left for
  1542. * processing as host only allocates buffers in this ring and IPA HW processes
  1543. * the buffer.
  1544. *
  1545. * Return: True if tx completions are pending
  1546. */
  1547. static bool dp_ipa_get_tx_comp_pending_check(struct dp_soc *soc)
  1548. {
  1549. struct dp_srng *tx_comp_ring =
  1550. &soc->tx_comp_ring[IPA_TX_COMP_RING_IDX];
  1551. uint32_t hp, tp, entry_size, buf_cnt;
  1552. hal_get_hw_hptp(soc->hal_soc, tx_comp_ring->hal_srng, &hp, &tp,
  1553. WBM2SW_RELEASE);
  1554. entry_size = hal_srng_get_entrysize(soc->hal_soc, WBM2SW_RELEASE) >> 2;
  1555. if (hp > tp)
  1556. buf_cnt = (hp - tp) / entry_size;
  1557. else
  1558. buf_cnt = (tx_comp_ring->num_entries - tp + hp) / entry_size;
  1559. return (soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt != buf_cnt);
  1560. }
  1561. #endif
  1562. QDF_STATUS dp_ipa_disable_pipes(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1563. {
  1564. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1565. struct dp_pdev *pdev =
  1566. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1567. int timeout = TX_COMP_DRAIN_WAIT_TIMEOUT_MS;
  1568. QDF_STATUS result;
  1569. if (!pdev) {
  1570. dp_err("Invalid instance");
  1571. return QDF_STATUS_E_FAILURE;
  1572. }
  1573. /*
  1574. * The tx completions pending check will trigger register read
  1575. * for HP and TP of wbm2sw2 ring. There is a possibility for
  1576. * these reg read to cause a NOC error if UMAC is in low power
  1577. * state. The WAR is to sleep for the drain timeout without checking
  1578. * for the pending tx completions. This WAR can be replaced with
  1579. * poll logic for HP/TP difference once force wake is in place.
  1580. */
  1581. #ifdef DEVICE_FORCE_WAKE_ENABLED
  1582. while (dp_ipa_get_tx_comp_pending_check(soc)) {
  1583. qdf_sleep(TX_COMP_DRAIN_WAIT_MS);
  1584. timeout -= TX_COMP_DRAIN_WAIT_MS;
  1585. if (timeout <= 0) {
  1586. dp_err("Tx completions pending. Force Disabling pipes");
  1587. break;
  1588. }
  1589. }
  1590. #else
  1591. qdf_sleep(timeout);
  1592. #endif
  1593. result = qdf_ipa_wdi_disable_pipes();
  1594. if (result) {
  1595. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1596. "%s: Disable WDI PIPE fail, code %d",
  1597. __func__, result);
  1598. qdf_assert_always(0);
  1599. return QDF_STATUS_E_FAILURE;
  1600. }
  1601. qdf_atomic_set(&soc->ipa_pipes_enabled, 0);
  1602. dp_ipa_handle_rx_buf_pool_smmu_mapping(soc, pdev, false);
  1603. return result ? QDF_STATUS_E_FAILURE : QDF_STATUS_SUCCESS;
  1604. }
  1605. /**
  1606. * dp_ipa_set_perf_level() - Set IPA clock bandwidth based on data rates
  1607. * @client: Client type
  1608. * @max_supported_bw_mbps: Maximum bandwidth needed (in Mbps)
  1609. *
  1610. * Return: QDF_STATUS
  1611. */
  1612. QDF_STATUS dp_ipa_set_perf_level(int client, uint32_t max_supported_bw_mbps)
  1613. {
  1614. qdf_ipa_wdi_perf_profile_t profile;
  1615. QDF_STATUS result;
  1616. profile.client = client;
  1617. profile.max_supported_bw_mbps = max_supported_bw_mbps;
  1618. result = qdf_ipa_wdi_set_perf_profile(&profile);
  1619. if (result) {
  1620. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1621. "%s: ipa_wdi_set_perf_profile fail, code %d",
  1622. __func__, result);
  1623. return QDF_STATUS_E_FAILURE;
  1624. }
  1625. return QDF_STATUS_SUCCESS;
  1626. }
  1627. /**
  1628. * dp_ipa_intrabss_send - send IPA RX intra-bss frames
  1629. * @pdev: pdev
  1630. * @vdev: vdev
  1631. * @nbuf: skb
  1632. *
  1633. * Return: nbuf if TX fails and NULL if TX succeeds
  1634. */
  1635. static qdf_nbuf_t dp_ipa_intrabss_send(struct dp_pdev *pdev,
  1636. struct dp_vdev *vdev,
  1637. qdf_nbuf_t nbuf)
  1638. {
  1639. struct dp_peer *vdev_peer;
  1640. uint16_t len;
  1641. vdev_peer = dp_vdev_bss_peer_ref_n_get(pdev->soc, vdev, DP_MOD_ID_IPA);
  1642. if (qdf_unlikely(!vdev_peer))
  1643. return nbuf;
  1644. qdf_mem_zero(nbuf->cb, sizeof(nbuf->cb));
  1645. len = qdf_nbuf_len(nbuf);
  1646. if (dp_tx_send((struct cdp_soc_t *)pdev->soc, vdev->vdev_id, nbuf)) {
  1647. DP_STATS_INC_PKT(vdev_peer, rx.intra_bss.fail, 1, len);
  1648. dp_peer_unref_delete(vdev_peer, DP_MOD_ID_IPA);
  1649. return nbuf;
  1650. }
  1651. DP_STATS_INC_PKT(vdev_peer, rx.intra_bss.pkts, 1, len);
  1652. dp_peer_unref_delete(vdev_peer, DP_MOD_ID_IPA);
  1653. return NULL;
  1654. }
  1655. bool dp_ipa_rx_intrabss_fwd(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  1656. qdf_nbuf_t nbuf, bool *fwd_success)
  1657. {
  1658. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1659. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  1660. DP_MOD_ID_IPA);
  1661. struct dp_pdev *pdev;
  1662. struct dp_peer *da_peer;
  1663. struct dp_peer *sa_peer;
  1664. qdf_nbuf_t nbuf_copy;
  1665. uint8_t da_is_bcmc;
  1666. struct ethhdr *eh;
  1667. bool status = false;
  1668. *fwd_success = false; /* set default as failure */
  1669. /*
  1670. * WDI 3.0 skb->cb[] info from IPA driver
  1671. * skb->cb[0] = vdev_id
  1672. * skb->cb[1].bit#1 = da_is_bcmc
  1673. */
  1674. da_is_bcmc = ((uint8_t)nbuf->cb[1]) & 0x2;
  1675. if (qdf_unlikely(!vdev))
  1676. return false;
  1677. pdev = vdev->pdev;
  1678. if (qdf_unlikely(!pdev))
  1679. goto out;
  1680. /* no fwd for station mode and just pass up to stack */
  1681. if (vdev->opmode == wlan_op_mode_sta)
  1682. goto out;
  1683. if (da_is_bcmc) {
  1684. nbuf_copy = qdf_nbuf_copy(nbuf);
  1685. if (!nbuf_copy)
  1686. goto out;
  1687. if (dp_ipa_intrabss_send(pdev, vdev, nbuf_copy))
  1688. qdf_nbuf_free(nbuf_copy);
  1689. else
  1690. *fwd_success = true;
  1691. /* return false to pass original pkt up to stack */
  1692. goto out;
  1693. }
  1694. eh = (struct ethhdr *)qdf_nbuf_data(nbuf);
  1695. if (!qdf_mem_cmp(eh->h_dest, vdev->mac_addr.raw, QDF_MAC_ADDR_SIZE))
  1696. goto out;
  1697. da_peer = dp_peer_find_hash_find(soc, eh->h_dest, 0, vdev->vdev_id,
  1698. DP_MOD_ID_IPA);
  1699. if (!da_peer)
  1700. goto out;
  1701. dp_peer_unref_delete(da_peer, DP_MOD_ID_IPA);
  1702. sa_peer = dp_peer_find_hash_find(soc, eh->h_source, 0, vdev->vdev_id,
  1703. DP_MOD_ID_IPA);
  1704. if (!sa_peer)
  1705. goto out;
  1706. dp_peer_unref_delete(sa_peer, DP_MOD_ID_IPA);
  1707. /*
  1708. * In intra-bss forwarding scenario, skb is allocated by IPA driver.
  1709. * Need to add skb to internal tracking table to avoid nbuf memory
  1710. * leak check for unallocated skb.
  1711. */
  1712. qdf_net_buf_debug_acquire_skb(nbuf, __FILE__, __LINE__);
  1713. if (dp_ipa_intrabss_send(pdev, vdev, nbuf))
  1714. qdf_nbuf_free(nbuf);
  1715. else
  1716. *fwd_success = true;
  1717. status = true;
  1718. out:
  1719. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_IPA);
  1720. return status;
  1721. }
  1722. #ifdef MDM_PLATFORM
  1723. bool dp_ipa_is_mdm_platform(void)
  1724. {
  1725. return true;
  1726. }
  1727. #else
  1728. bool dp_ipa_is_mdm_platform(void)
  1729. {
  1730. return false;
  1731. }
  1732. #endif
  1733. /**
  1734. * dp_ipa_frag_nbuf_linearize - linearize nbuf for IPA
  1735. * @soc: soc
  1736. * @nbuf: source skb
  1737. *
  1738. * Return: new nbuf if success and otherwise NULL
  1739. */
  1740. static qdf_nbuf_t dp_ipa_frag_nbuf_linearize(struct dp_soc *soc,
  1741. qdf_nbuf_t nbuf)
  1742. {
  1743. uint8_t *src_nbuf_data;
  1744. uint8_t *dst_nbuf_data;
  1745. qdf_nbuf_t dst_nbuf;
  1746. qdf_nbuf_t temp_nbuf = nbuf;
  1747. uint32_t nbuf_len = qdf_nbuf_len(nbuf);
  1748. bool is_nbuf_head = true;
  1749. uint32_t copy_len = 0;
  1750. dst_nbuf = qdf_nbuf_alloc(soc->osdev, RX_DATA_BUFFER_SIZE,
  1751. RX_BUFFER_RESERVATION,
  1752. RX_DATA_BUFFER_ALIGNMENT, FALSE);
  1753. if (!dst_nbuf) {
  1754. dp_err_rl("nbuf allocate fail");
  1755. return NULL;
  1756. }
  1757. if ((nbuf_len + L3_HEADER_PADDING) > RX_DATA_BUFFER_SIZE) {
  1758. qdf_nbuf_free(dst_nbuf);
  1759. dp_err_rl("nbuf is jumbo data");
  1760. return NULL;
  1761. }
  1762. /* prepeare to copy all data into new skb */
  1763. dst_nbuf_data = qdf_nbuf_data(dst_nbuf);
  1764. while (temp_nbuf) {
  1765. src_nbuf_data = qdf_nbuf_data(temp_nbuf);
  1766. /* first head nbuf */
  1767. if (is_nbuf_head) {
  1768. qdf_mem_copy(dst_nbuf_data, src_nbuf_data,
  1769. RX_PKT_TLVS_LEN);
  1770. /* leave extra 2 bytes L3_HEADER_PADDING */
  1771. dst_nbuf_data += (RX_PKT_TLVS_LEN + L3_HEADER_PADDING);
  1772. src_nbuf_data += RX_PKT_TLVS_LEN;
  1773. copy_len = qdf_nbuf_headlen(temp_nbuf) -
  1774. RX_PKT_TLVS_LEN;
  1775. temp_nbuf = qdf_nbuf_get_ext_list(temp_nbuf);
  1776. is_nbuf_head = false;
  1777. } else {
  1778. copy_len = qdf_nbuf_len(temp_nbuf);
  1779. temp_nbuf = qdf_nbuf_queue_next(temp_nbuf);
  1780. }
  1781. qdf_mem_copy(dst_nbuf_data, src_nbuf_data, copy_len);
  1782. dst_nbuf_data += copy_len;
  1783. }
  1784. qdf_nbuf_set_len(dst_nbuf, nbuf_len);
  1785. /* copy is done, free original nbuf */
  1786. qdf_nbuf_free(nbuf);
  1787. return dst_nbuf;
  1788. }
  1789. /**
  1790. * dp_ipa_handle_rx_reo_reinject - Handle RX REO reinject skb buffer
  1791. * @soc: soc
  1792. * @nbuf: skb
  1793. *
  1794. * Return: nbuf if success and otherwise NULL
  1795. */
  1796. qdf_nbuf_t dp_ipa_handle_rx_reo_reinject(struct dp_soc *soc, qdf_nbuf_t nbuf)
  1797. {
  1798. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1799. return nbuf;
  1800. /* WLAN IPA is run-time disabled */
  1801. if (!qdf_atomic_read(&soc->ipa_pipes_enabled))
  1802. return nbuf;
  1803. if (!qdf_nbuf_is_frag(nbuf))
  1804. return nbuf;
  1805. /* linearize skb for IPA */
  1806. return dp_ipa_frag_nbuf_linearize(soc, nbuf);
  1807. }
  1808. QDF_STATUS dp_ipa_tx_buf_smmu_mapping(
  1809. struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1810. {
  1811. QDF_STATUS ret;
  1812. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1813. struct dp_pdev *pdev =
  1814. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1815. if (!pdev) {
  1816. dp_err("%s invalid instance", __func__);
  1817. return QDF_STATUS_E_FAILURE;
  1818. }
  1819. if (!qdf_mem_smmu_s1_enabled(soc->osdev)) {
  1820. dp_debug("SMMU S1 disabled");
  1821. return QDF_STATUS_SUCCESS;
  1822. }
  1823. ret = __dp_ipa_tx_buf_smmu_mapping(soc, pdev, true);
  1824. return ret;
  1825. }
  1826. QDF_STATUS dp_ipa_tx_buf_smmu_unmapping(
  1827. struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1828. {
  1829. QDF_STATUS ret;
  1830. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1831. struct dp_pdev *pdev =
  1832. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1833. if (!pdev) {
  1834. dp_err("%s invalid instance", __func__);
  1835. return QDF_STATUS_E_FAILURE;
  1836. }
  1837. if (!qdf_mem_smmu_s1_enabled(soc->osdev)) {
  1838. dp_debug("SMMU S1 disabled");
  1839. return QDF_STATUS_SUCCESS;
  1840. }
  1841. ret = __dp_ipa_tx_buf_smmu_mapping(soc, pdev, false);
  1842. return ret;
  1843. }
  1844. #endif