holi.c 190 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/clk.h>
  6. #include <linux/delay.h>
  7. #include <linux/gpio.h>
  8. #include <linux/of_gpio.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/slab.h>
  11. #include <linux/io.h>
  12. #include <linux/module.h>
  13. #include <linux/input.h>
  14. #include <linux/of_device.h>
  15. #include <linux/soc/qcom/fsa4480-i2c.h>
  16. #include <sound/core.h>
  17. #include <sound/soc.h>
  18. #include <sound/soc-dapm.h>
  19. #include <sound/pcm.h>
  20. #include <sound/pcm_params.h>
  21. #include <sound/info.h>
  22. #include <soc/snd_event.h>
  23. #include <dsp/audio_notifier.h>
  24. #include <soc/swr-common.h>
  25. #include <dsp/q6afe-v2.h>
  26. #include <dsp/q6core.h>
  27. #include <soc/soundwire.h>
  28. #include "device_event.h"
  29. #include "msm-pcm-routing-v2.h"
  30. #include "asoc/msm-cdc-pinctrl.h"
  31. #include "asoc/wcd-mbhc-v2.h"
  32. #include "codecs/wsa881x-analog.h"
  33. #include "codecs/wcd937x/wcd937x-mbhc.h"
  34. #include "codecs/wcd937x/wcd937x.h"
  35. #include "codecs/wcd938x/wcd938x-mbhc.h"
  36. #include "codecs/wcd938x/wcd938x.h"
  37. #include "codecs/bolero/bolero-cdc.h"
  38. #include <dt-bindings/sound/audio-codec-port-types.h>
  39. #include "holi-port-config.h"
  40. #include "msm_holi_dailink.h"
  41. #define DRV_NAME "holi-asoc-snd"
  42. #define __CHIPSET__ "HOLI "
  43. #define MSM_DAILINK_NAME(name) (__CHIPSET__#name)
  44. #define SAMPLING_RATE_8KHZ 8000
  45. #define SAMPLING_RATE_11P025KHZ 11025
  46. #define SAMPLING_RATE_16KHZ 16000
  47. #define SAMPLING_RATE_22P05KHZ 22050
  48. #define SAMPLING_RATE_32KHZ 32000
  49. #define SAMPLING_RATE_44P1KHZ 44100
  50. #define SAMPLING_RATE_48KHZ 48000
  51. #define SAMPLING_RATE_88P2KHZ 88200
  52. #define SAMPLING_RATE_96KHZ 96000
  53. #define SAMPLING_RATE_176P4KHZ 176400
  54. #define SAMPLING_RATE_192KHZ 192000
  55. #define SAMPLING_RATE_352P8KHZ 352800
  56. #define SAMPLING_RATE_384KHZ 384000
  57. #define IS_FRACTIONAL(x) \
  58. ((x == SAMPLING_RATE_11P025KHZ) || (x == SAMPLING_RATE_22P05KHZ) || \
  59. (x == SAMPLING_RATE_44P1KHZ) || (x == SAMPLING_RATE_88P2KHZ) || \
  60. (x == SAMPLING_RATE_176P4KHZ) || (x == SAMPLING_RATE_352P8KHZ))
  61. #define IS_MSM_INTERFACE_MI2S(x) \
  62. ((x == PRIM_MI2S) || (x == SEC_MI2S) || (x == TERT_MI2S))
  63. #define WCD9XXX_MBHC_DEF_RLOADS 5
  64. #define WCD9XXX_MBHC_DEF_BUTTONS 8
  65. #define CODEC_EXT_CLK_RATE 9600000
  66. #define ADSP_STATE_READY_TIMEOUT_MS 3000
  67. #define DEV_NAME_STR_LEN 32
  68. #define WCD_MBHC_HS_V_MAX 1600
  69. #define TDM_CHANNEL_MAX 8
  70. #define DEV_NAME_STR_LEN 32
  71. /* time in us to ensure LPM doesn't go in C3/C4 */
  72. #define MSM_LL_QOS_VALUE 300
  73. #define ADSP_STATE_READY_TIMEOUT_MS 3000
  74. #define WCN_CDC_SLIM_RX_CH_MAX 2
  75. #define WCN_CDC_SLIM_TX_CH_MAX 2
  76. #define WCN_CDC_SLIM_TX_CH_MAX_LITO 3
  77. enum {
  78. RX_PATH = 0,
  79. TX_PATH,
  80. MAX_PATH,
  81. };
  82. enum {
  83. TDM_0 = 0,
  84. TDM_1,
  85. TDM_2,
  86. TDM_3,
  87. TDM_4,
  88. TDM_5,
  89. TDM_6,
  90. TDM_7,
  91. TDM_PORT_MAX,
  92. };
  93. #define TDM_MAX_SLOTS 8
  94. #define TDM_SLOT_WIDTH_BITS 32
  95. enum {
  96. TDM_PRI = 0,
  97. TDM_SEC,
  98. TDM_TERT,
  99. TDM_QUAT,
  100. TDM_INTERFACE_MAX,
  101. };
  102. enum {
  103. PRIM_AUX_PCM = 0,
  104. SEC_AUX_PCM,
  105. TERT_AUX_PCM,
  106. QUAT_AUX_PCM,
  107. AUX_PCM_MAX,
  108. };
  109. enum {
  110. PRIM_MI2S = 0,
  111. SEC_MI2S,
  112. TERT_MI2S,
  113. QUAT_MI2S,
  114. MI2S_MAX,
  115. };
  116. enum {
  117. RX_CDC_DMA_RX_0 = 0,
  118. RX_CDC_DMA_RX_1,
  119. RX_CDC_DMA_RX_2,
  120. RX_CDC_DMA_RX_3,
  121. RX_CDC_DMA_RX_5,
  122. RX_CDC_DMA_RX_6,
  123. CDC_DMA_RX_MAX,
  124. };
  125. enum {
  126. TX_CDC_DMA_TX_0 = 0,
  127. TX_CDC_DMA_TX_3,
  128. TX_CDC_DMA_TX_4,
  129. VA_CDC_DMA_TX_0,
  130. VA_CDC_DMA_TX_1,
  131. VA_CDC_DMA_TX_2,
  132. CDC_DMA_TX_MAX,
  133. };
  134. enum {
  135. SLIM_RX_7 = 0,
  136. SLIM_RX_MAX,
  137. };
  138. enum {
  139. SLIM_TX_7 = 0,
  140. SLIM_TX_8,
  141. SLIM_TX_MAX,
  142. };
  143. enum {
  144. AFE_LOOPBACK_TX_IDX = 0,
  145. AFE_LOOPBACK_TX_IDX_MAX,
  146. };
  147. struct msm_asoc_mach_data {
  148. struct snd_info_entry *codec_root;
  149. int usbc_en2_gpio; /* used by gpio driver API */
  150. struct device_node *dmic01_gpio_p; /* used by pinctrl API */
  151. struct device_node *dmic23_gpio_p; /* used by pinctrl API */
  152. struct device_node *dmic45_gpio_p; /* used by pinctrl API */
  153. struct device_node *mi2s_gpio_p[MI2S_MAX]; /* used by pinctrl API */
  154. atomic_t mi2s_gpio_ref_count[MI2S_MAX]; /* used by pinctrl API */
  155. struct device_node *us_euro_gpio_p; /* used by pinctrl API */
  156. struct pinctrl *usbc_en2_gpio_p; /* used by pinctrl API */
  157. struct device_node *hph_en1_gpio_p; /* used by pinctrl API */
  158. struct device_node *hph_en0_gpio_p; /* used by pinctrl API */
  159. bool is_afe_config_done;
  160. struct device_node *fsa_handle;
  161. struct clk *lpass_audio_hw_vote;
  162. int core_audio_vote_count;
  163. u32 wcd_disabled;
  164. };
  165. struct tdm_port {
  166. u32 mode;
  167. u32 channel;
  168. };
  169. struct tdm_dev_config {
  170. unsigned int tdm_slot_offset[TDM_MAX_SLOTS];
  171. };
  172. struct dev_config {
  173. u32 sample_rate;
  174. u32 bit_format;
  175. u32 channels;
  176. };
  177. /* Default configuration of slimbus channels */
  178. static struct dev_config slim_rx_cfg[] = {
  179. [SLIM_RX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  180. };
  181. static struct dev_config slim_tx_cfg[] = {
  182. [SLIM_TX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  183. [SLIM_TX_8] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  184. };
  185. static struct dev_config usb_rx_cfg = {
  186. .sample_rate = SAMPLING_RATE_48KHZ,
  187. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  188. .channels = 2,
  189. };
  190. static struct dev_config usb_tx_cfg = {
  191. .sample_rate = SAMPLING_RATE_48KHZ,
  192. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  193. .channels = 1,
  194. };
  195. static struct dev_config proxy_rx_cfg = {
  196. .sample_rate = SAMPLING_RATE_48KHZ,
  197. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  198. .channels = 2,
  199. };
  200. static struct afe_clk_set mi2s_clk[MI2S_MAX] = {
  201. {
  202. AFE_API_VERSION_I2S_CONFIG,
  203. Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
  204. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  205. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  206. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  207. 0,
  208. },
  209. {
  210. AFE_API_VERSION_I2S_CONFIG,
  211. Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
  212. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  213. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  214. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  215. 0,
  216. },
  217. {
  218. AFE_API_VERSION_I2S_CONFIG,
  219. Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
  220. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  221. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  222. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  223. 0,
  224. },
  225. {
  226. AFE_API_VERSION_I2S_CONFIG,
  227. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT,
  228. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  229. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  230. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  231. 0,
  232. },
  233. };
  234. struct mi2s_conf {
  235. struct mutex lock;
  236. u32 ref_cnt;
  237. u32 msm_is_mi2s_master;
  238. };
  239. static u32 mi2s_ebit_clk[MI2S_MAX] = {
  240. Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT,
  241. Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT,
  242. Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT,
  243. };
  244. static struct mi2s_conf mi2s_intf_conf[MI2S_MAX];
  245. /* Default configuration of TDM channels */
  246. static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  247. { /* PRI TDM */
  248. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  249. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  250. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  251. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  252. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  253. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  254. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  255. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  256. },
  257. { /* SEC TDM */
  258. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  259. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  260. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  261. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  262. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  263. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  264. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  265. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  266. },
  267. { /* TERT TDM */
  268. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  269. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  270. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  271. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  272. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  273. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  274. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  275. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  276. },
  277. { /* QUAT TDM */
  278. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  279. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  280. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  281. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  282. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  283. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  284. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  285. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  286. },
  287. };
  288. static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  289. { /* PRI TDM */
  290. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  291. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  292. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  293. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  294. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  295. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  296. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  297. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  298. },
  299. { /* SEC TDM */
  300. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  301. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  302. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  303. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  304. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  305. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  306. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  307. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  308. },
  309. { /* TERT TDM */
  310. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  311. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  312. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  313. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  314. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  315. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  316. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  317. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  318. },
  319. { /* QUAT TDM */
  320. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  321. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  322. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  323. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  324. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  325. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  326. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  327. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  328. },
  329. };
  330. /* Default configuration of AUX PCM channels */
  331. static struct dev_config aux_pcm_rx_cfg[] = {
  332. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  333. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  334. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  335. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  336. };
  337. static struct dev_config aux_pcm_tx_cfg[] = {
  338. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  339. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  340. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  341. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  342. };
  343. /* Default configuration of MI2S channels */
  344. static struct dev_config mi2s_rx_cfg[] = {
  345. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  346. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  347. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  348. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  349. };
  350. static struct dev_config mi2s_tx_cfg[] = {
  351. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  352. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  353. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  354. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  355. };
  356. static struct tdm_dev_config pri_tdm_dev_config[MAX_PATH][TDM_PORT_MAX] = {
  357. { /* PRI TDM */
  358. { {0, 4, 0xFFFF} }, /* RX_0 */
  359. { {8, 12, 0xFFFF} }, /* RX_1 */
  360. { {16, 20, 0xFFFF} }, /* RX_2 */
  361. { {24, 28, 0xFFFF} }, /* RX_3 */
  362. { {0xFFFF} }, /* RX_4 */
  363. { {0xFFFF} }, /* RX_5 */
  364. { {0xFFFF} }, /* RX_6 */
  365. { {0xFFFF} }, /* RX_7 */
  366. },
  367. {
  368. { {0, 4, 8, 12, 0xFFFF} }, /* TX_0 */
  369. { {8, 12, 0xFFFF} }, /* TX_1 */
  370. { {16, 20, 0xFFFF} }, /* TX_2 */
  371. { {24, 28, 0xFFFF} }, /* TX_3 */
  372. { {0xFFFF} }, /* TX_4 */
  373. { {0xFFFF} }, /* TX_5 */
  374. { {0xFFFF} }, /* TX_6 */
  375. { {0xFFFF} }, /* TX_7 */
  376. },
  377. };
  378. static struct tdm_dev_config sec_tdm_dev_config[MAX_PATH][TDM_PORT_MAX] = {
  379. { /* SEC TDM */
  380. { {0, 4, 0xFFFF} }, /* RX_0 */
  381. { {8, 12, 0xFFFF} }, /* RX_1 */
  382. { {16, 20, 0xFFFF} }, /* RX_2 */
  383. { {24, 28, 0xFFFF} }, /* RX_3 */
  384. { {0xFFFF} }, /* RX_4 */
  385. { {0xFFFF} }, /* RX_5 */
  386. { {0xFFFF} }, /* RX_6 */
  387. { {0xFFFF} }, /* RX_7 */
  388. },
  389. {
  390. { {0, 4, 0xFFFF} }, /* TX_0 */
  391. { {8, 12, 0xFFFF} }, /* TX_1 */
  392. { {16, 20, 0xFFFF} }, /* TX_2 */
  393. { {24, 28, 0xFFFF} }, /* TX_3 */
  394. { {0xFFFF} }, /* TX_4 */
  395. { {0xFFFF} }, /* TX_5 */
  396. { {0xFFFF} }, /* TX_6 */
  397. { {0xFFFF} }, /* TX_7 */
  398. },
  399. };
  400. static struct tdm_dev_config tert_tdm_dev_config[MAX_PATH][TDM_PORT_MAX] = {
  401. { /* TERT TDM */
  402. { {0, 4, 0xFFFF} }, /* RX_0 */
  403. { {8, 12, 0xFFFF} }, /* RX_1 */
  404. { {16, 20, 0xFFFF} }, /* RX_2 */
  405. { {24, 28, 0xFFFF} }, /* RX_3 */
  406. { {0xFFFF} }, /* RX_4 */
  407. { {0xFFFF} }, /* RX_5 */
  408. { {0xFFFF} }, /* RX_6 */
  409. { {0xFFFF} }, /* RX_7 */
  410. },
  411. {
  412. { {0, 4, 0xFFFF} }, /* TX_0 */
  413. { {8, 12, 0xFFFF} }, /* TX_1 */
  414. { {16, 20, 0xFFFF} }, /* TX_2 */
  415. { {24, 28, 0xFFFF} }, /* TX_3 */
  416. { {0xFFFF} }, /* TX_4 */
  417. { {0xFFFF} }, /* TX_5 */
  418. { {0xFFFF} }, /* TX_6 */
  419. { {0xFFFF} }, /* TX_7 */
  420. },
  421. };
  422. static struct tdm_dev_config quat_tdm_dev_config[MAX_PATH][TDM_PORT_MAX] = {
  423. { /* QUAT TDM */
  424. { {0, 4, 0xFFFF} }, /* RX_0 */
  425. { {8, 12, 0xFFFF} }, /* RX_1 */
  426. { {16, 20, 0xFFFF} }, /* RX_2 */
  427. { {24, 28, 0xFFFF} }, /* RX_3 */
  428. { {0xFFFF} }, /* RX_4 */
  429. { {0xFFFF} }, /* RX_5 */
  430. { {0xFFFF} }, /* RX_6 */
  431. { {0xFFFF} }, /* RX_7 */
  432. },
  433. {
  434. { {0, 4, 0xFFFF} }, /* TX_0 */
  435. { {8, 12, 0xFFFF} }, /* TX_1 */
  436. { {16, 20, 0xFFFF} }, /* TX_2 */
  437. { {24, 28, 0xFFFF} }, /* TX_3 */
  438. { {0xFFFF} }, /* TX_4 */
  439. { {0xFFFF} }, /* TX_5 */
  440. { {0xFFFF} }, /* TX_6 */
  441. { {0xFFFF} }, /* TX_7 */
  442. },
  443. };
  444. static void *tdm_cfg[TDM_INTERFACE_MAX] = {
  445. pri_tdm_dev_config,
  446. sec_tdm_dev_config,
  447. tert_tdm_dev_config,
  448. quat_tdm_dev_config,
  449. };
  450. /* Default configuration of Codec DMA Interface RX */
  451. static struct dev_config cdc_dma_rx_cfg[] = {
  452. [RX_CDC_DMA_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  453. [RX_CDC_DMA_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  454. [RX_CDC_DMA_RX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  455. [RX_CDC_DMA_RX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  456. [RX_CDC_DMA_RX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  457. [RX_CDC_DMA_RX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  458. };
  459. /* Default configuration of Codec DMA Interface TX */
  460. static struct dev_config cdc_dma_tx_cfg[] = {
  461. [TX_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  462. [TX_CDC_DMA_TX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  463. [TX_CDC_DMA_TX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  464. [VA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  465. [VA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  466. [VA_CDC_DMA_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  467. };
  468. static struct dev_config afe_loopback_tx_cfg[] = {
  469. [AFE_LOOPBACK_TX_IDX] =
  470. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  471. };
  472. static int msm_vi_feed_tx_ch = 2;
  473. static const char *const vi_feed_ch_text[] = {"One", "Two"};
  474. static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
  475. "S32_LE"};
  476. static char const *cdc80_bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE"};
  477. static char const *ch_text[] = {"Two", "Three", "Four", "Five",
  478. "Six", "Seven", "Eight"};
  479. static char const *usb_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  480. "KHZ_16", "KHZ_22P05",
  481. "KHZ_32", "KHZ_44P1", "KHZ_48",
  482. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  483. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  484. static const char *const usb_ch_text[] = {"One", "Two", "Three", "Four",
  485. "Five", "Six", "Seven",
  486. "Eight"};
  487. static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32",
  488. "KHZ_48", "KHZ_176P4",
  489. "KHZ_352P8"};
  490. static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"};
  491. static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four",
  492. "Five", "Six", "Seven", "Eight"};
  493. static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"};
  494. static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_11P025", "KHZ_16",
  495. "KHZ_22P05", "KHZ_32", "KHZ_44P1",
  496. "KHZ_48", "KHZ_88P2", "KHZ_96",
  497. "KHZ_176P4", "KHZ_192", "KHZ_352P8",
  498. "KHZ_384"};
  499. static const char *const mi2s_ch_text[] = {"One", "Two", "Three", "Four",
  500. "Five", "Six", "Seven",
  501. "Eight"};
  502. static const char *const cdc_dma_rx_ch_text[] = {"One", "Two"};
  503. static const char *const cdc_dma_tx_ch_text[] = {"One", "Two", "Three", "Four",
  504. "Five", "Six", "Seven",
  505. "Eight"};
  506. static char const *cdc_dma_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  507. "KHZ_16", "KHZ_22P05",
  508. "KHZ_32", "KHZ_44P1", "KHZ_48",
  509. "KHZ_88P2", "KHZ_96",
  510. "KHZ_176P4", "KHZ_192",
  511. "KHZ_352P8", "KHZ_384"};
  512. static char const *cdc80_dma_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  513. "KHZ_16", "KHZ_22P05",
  514. "KHZ_32", "KHZ_44P1", "KHZ_48",
  515. "KHZ_88P2", "KHZ_96",
  516. "KHZ_176P4", "KHZ_192"};
  517. static char const *bt_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  518. "KHZ_44P1", "KHZ_48",
  519. "KHZ_88P2", "KHZ_96"};
  520. static char const *bt_sample_rate_rx_text[] = {"KHZ_8", "KHZ_16",
  521. "KHZ_44P1", "KHZ_48",
  522. "KHZ_88P2", "KHZ_96"};
  523. static char const *bt_sample_rate_tx_text[] = {"KHZ_8", "KHZ_16",
  524. "KHZ_44P1", "KHZ_48",
  525. "KHZ_88P2", "KHZ_96"};
  526. static const char *const afe_loopback_tx_ch_text[] = {"One", "Two"};
  527. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_sample_rate, usb_sample_rate_text);
  528. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_sample_rate, usb_sample_rate_text);
  529. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_format, bit_format_text);
  530. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_format, bit_format_text);
  531. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_chs, usb_ch_text);
  532. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_chs, usb_ch_text);
  533. static SOC_ENUM_SINGLE_EXT_DECL(vi_feed_tx_chs, vi_feed_ch_text);
  534. static SOC_ENUM_SINGLE_EXT_DECL(proxy_rx_chs, ch_text);
  535. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text);
  536. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text);
  537. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text);
  538. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_format, tdm_bit_format_text);
  539. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_chs, tdm_ch_text);
  540. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text);
  541. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  542. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  543. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  544. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  545. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  546. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  547. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  548. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  549. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_rx_format, bit_format_text);
  550. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_tx_format, bit_format_text);
  551. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_sample_rate, mi2s_rate_text);
  552. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_sample_rate, mi2s_rate_text);
  553. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_sample_rate, mi2s_rate_text);
  554. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_sample_rate, mi2s_rate_text);
  555. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_sample_rate, mi2s_rate_text);
  556. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_sample_rate, mi2s_rate_text);
  557. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_sample_rate, mi2s_rate_text);
  558. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_sample_rate, mi2s_rate_text);
  559. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_rx_format, bit_format_text);
  560. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_tx_format, bit_format_text);
  561. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_chs, mi2s_ch_text);
  562. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_chs, mi2s_ch_text);
  563. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_chs, mi2s_ch_text);
  564. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_chs, mi2s_ch_text);
  565. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_chs, mi2s_ch_text);
  566. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_chs, mi2s_ch_text);
  567. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_chs, mi2s_ch_text);
  568. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_chs, mi2s_ch_text);
  569. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_0_chs, cdc_dma_rx_ch_text);
  570. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_1_chs, cdc_dma_rx_ch_text);
  571. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_2_chs, cdc_dma_rx_ch_text);
  572. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_3_chs, cdc_dma_rx_ch_text);
  573. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_5_chs, cdc_dma_rx_ch_text);
  574. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_6_chs, cdc_dma_rx_ch_text);
  575. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  576. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_3_chs, cdc_dma_tx_ch_text);
  577. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_4_chs, cdc_dma_tx_ch_text);
  578. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  579. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  580. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_2_chs, cdc_dma_tx_ch_text);
  581. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_0_format, bit_format_text);
  582. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_3_format, bit_format_text);
  583. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_4_format, bit_format_text);
  584. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_format, bit_format_text);
  585. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_format, bit_format_text);
  586. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_2_format, bit_format_text);
  587. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_0_sample_rate,
  588. cdc_dma_sample_rate_text);
  589. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_3_sample_rate,
  590. cdc_dma_sample_rate_text);
  591. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_4_sample_rate,
  592. cdc_dma_sample_rate_text);
  593. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_sample_rate,
  594. cdc_dma_sample_rate_text);
  595. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_sample_rate,
  596. cdc_dma_sample_rate_text);
  597. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_2_sample_rate,
  598. cdc_dma_sample_rate_text);
  599. /* WCD9380 */
  600. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_0_format, cdc80_bit_format_text);
  601. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_1_format, cdc80_bit_format_text);
  602. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_2_format, cdc80_bit_format_text);
  603. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_3_format, cdc80_bit_format_text);
  604. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_5_format, cdc80_bit_format_text);
  605. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_6_format, cdc80_bit_format_text);
  606. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_0_sample_rate,
  607. cdc80_dma_sample_rate_text);
  608. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_1_sample_rate,
  609. cdc80_dma_sample_rate_text);
  610. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_2_sample_rate,
  611. cdc80_dma_sample_rate_text);
  612. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_3_sample_rate,
  613. cdc80_dma_sample_rate_text);
  614. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_5_sample_rate,
  615. cdc80_dma_sample_rate_text);
  616. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_6_sample_rate,
  617. cdc80_dma_sample_rate_text);
  618. /* WCD9385 */
  619. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_0_format, bit_format_text);
  620. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_1_format, bit_format_text);
  621. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_2_format, bit_format_text);
  622. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_3_format, bit_format_text);
  623. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_5_format, bit_format_text);
  624. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_6_format, bit_format_text);
  625. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_0_sample_rate,
  626. cdc_dma_sample_rate_text);
  627. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_1_sample_rate,
  628. cdc_dma_sample_rate_text);
  629. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_2_sample_rate,
  630. cdc_dma_sample_rate_text);
  631. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_3_sample_rate,
  632. cdc_dma_sample_rate_text);
  633. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_5_sample_rate,
  634. cdc_dma_sample_rate_text);
  635. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_6_sample_rate,
  636. cdc_dma_sample_rate_text);
  637. /* WCD937x */
  638. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_0_format, bit_format_text);
  639. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_1_format, bit_format_text);
  640. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_2_format, bit_format_text);
  641. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_3_format, bit_format_text);
  642. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_5_format, bit_format_text);
  643. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_0_sample_rate,
  644. cdc_dma_sample_rate_text);
  645. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_1_sample_rate,
  646. cdc_dma_sample_rate_text);
  647. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_2_sample_rate,
  648. cdc_dma_sample_rate_text);
  649. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_3_sample_rate,
  650. cdc_dma_sample_rate_text);
  651. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_5_sample_rate,
  652. cdc_dma_sample_rate_text);
  653. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate, bt_sample_rate_text);
  654. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate_rx, bt_sample_rate_rx_text);
  655. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate_tx, bt_sample_rate_tx_text);
  656. static SOC_ENUM_SINGLE_EXT_DECL(afe_loopback_tx_chs, afe_loopback_tx_ch_text);
  657. static bool is_initial_boot;
  658. static bool codec_reg_done;
  659. static struct snd_soc_card snd_soc_card_holi_msm;
  660. static int dmic_0_1_gpio_cnt;
  661. static int dmic_2_3_gpio_cnt;
  662. static int dmic_4_5_gpio_cnt;
  663. static void *def_wcd_mbhc_cal(void);
  664. static int msm_aux_codec_init(struct snd_soc_pcm_runtime *);
  665. static int msm_int_audrx_init(struct snd_soc_pcm_runtime *);
  666. /*
  667. * Need to report LINEIN
  668. * if R/L channel impedance is larger than 5K ohm
  669. */
  670. static struct wcd_mbhc_config wcd_mbhc_cfg = {
  671. .read_fw_bin = false,
  672. .calibration = NULL,
  673. .detect_extn_cable = true,
  674. .mono_stero_detection = false,
  675. .swap_gnd_mic = NULL,
  676. .hs_ext_micbias = true,
  677. .key_code[0] = KEY_MEDIA,
  678. .key_code[1] = KEY_VOICECOMMAND,
  679. .key_code[2] = KEY_VOLUMEUP,
  680. .key_code[3] = KEY_VOLUMEDOWN,
  681. .key_code[4] = 0,
  682. .key_code[5] = 0,
  683. .key_code[6] = 0,
  684. .key_code[7] = 0,
  685. .linein_th = 5000,
  686. .moisture_en = false,
  687. .mbhc_micbias = MIC_BIAS_2,
  688. .anc_micbias = MIC_BIAS_2,
  689. .enable_anc_mic_detect = false,
  690. .moisture_duty_cycle_en = true,
  691. };
  692. /* set audio task affinity to core 1 & 2 */
  693. static const unsigned int audio_core_list[] = {1, 2};
  694. static cpumask_t audio_cpu_map = CPU_MASK_NONE;
  695. static struct dev_pm_qos_request *msm_audio_req = NULL;
  696. static unsigned int qos_client_active_cnt = 0;
  697. static void msm_audio_add_qos_request()
  698. {
  699. int i;
  700. int cpu = 0;
  701. msm_audio_req = kzalloc(sizeof(struct dev_pm_qos_request) * NR_CPUS,
  702. GFP_KERNEL);
  703. if (!msm_audio_req) {
  704. pr_err("%s failed to alloc mem for qos req.\n", __func__);
  705. return;
  706. }
  707. for (i = 0; i < ARRAY_SIZE(audio_core_list); i++) {
  708. if (audio_core_list[i] >= NR_CPUS)
  709. pr_err("%s incorrect cpu id: %d specified.\n",
  710. __func__, audio_core_list[i]);
  711. else
  712. cpumask_set_cpu(audio_core_list[i], &audio_cpu_map);
  713. }
  714. for_each_cpu(cpu, &audio_cpu_map) {
  715. dev_pm_qos_add_request(get_cpu_device(cpu),
  716. &msm_audio_req[cpu],
  717. DEV_PM_QOS_RESUME_LATENCY,
  718. PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE);
  719. pr_debug("%s set cpu affinity to core %d.\n", __func__, cpu);
  720. }
  721. }
  722. static void msm_audio_remove_qos_request()
  723. {
  724. int cpu = 0;
  725. if (msm_audio_req) {
  726. for_each_cpu(cpu, &audio_cpu_map) {
  727. dev_pm_qos_remove_request(
  728. &msm_audio_req[cpu]);
  729. pr_debug("%s remove cpu affinity of core %d.\n",
  730. __func__, cpu);
  731. }
  732. kfree(msm_audio_req);
  733. }
  734. }
  735. static void msm_audio_update_qos_request(u32 latency)
  736. {
  737. int cpu = 0;
  738. if (msm_audio_req) {
  739. for_each_cpu(cpu, &audio_cpu_map) {
  740. dev_pm_qos_update_request(
  741. &msm_audio_req[cpu], latency);
  742. pr_debug("%s update latency of core %d to %ul.\n",
  743. __func__, cpu, latency);
  744. }
  745. }
  746. }
  747. static inline int param_is_mask(int p)
  748. {
  749. return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) &&
  750. (p <= SNDRV_PCM_HW_PARAM_LAST_MASK);
  751. }
  752. static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p,
  753. int n)
  754. {
  755. return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]);
  756. }
  757. static void param_set_mask(struct snd_pcm_hw_params *p, int n,
  758. unsigned int bit)
  759. {
  760. if (bit >= SNDRV_MASK_MAX)
  761. return;
  762. if (param_is_mask(n)) {
  763. struct snd_mask *m = param_to_mask(p, n);
  764. m->bits[0] = 0;
  765. m->bits[1] = 0;
  766. m->bits[bit >> 5] |= (1 << (bit & 31));
  767. }
  768. }
  769. static int usb_audio_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  770. struct snd_ctl_elem_value *ucontrol)
  771. {
  772. int sample_rate_val = 0;
  773. switch (usb_rx_cfg.sample_rate) {
  774. case SAMPLING_RATE_384KHZ:
  775. sample_rate_val = 12;
  776. break;
  777. case SAMPLING_RATE_352P8KHZ:
  778. sample_rate_val = 11;
  779. break;
  780. case SAMPLING_RATE_192KHZ:
  781. sample_rate_val = 10;
  782. break;
  783. case SAMPLING_RATE_176P4KHZ:
  784. sample_rate_val = 9;
  785. break;
  786. case SAMPLING_RATE_96KHZ:
  787. sample_rate_val = 8;
  788. break;
  789. case SAMPLING_RATE_88P2KHZ:
  790. sample_rate_val = 7;
  791. break;
  792. case SAMPLING_RATE_48KHZ:
  793. sample_rate_val = 6;
  794. break;
  795. case SAMPLING_RATE_44P1KHZ:
  796. sample_rate_val = 5;
  797. break;
  798. case SAMPLING_RATE_32KHZ:
  799. sample_rate_val = 4;
  800. break;
  801. case SAMPLING_RATE_22P05KHZ:
  802. sample_rate_val = 3;
  803. break;
  804. case SAMPLING_RATE_16KHZ:
  805. sample_rate_val = 2;
  806. break;
  807. case SAMPLING_RATE_11P025KHZ:
  808. sample_rate_val = 1;
  809. break;
  810. case SAMPLING_RATE_8KHZ:
  811. default:
  812. sample_rate_val = 0;
  813. break;
  814. }
  815. ucontrol->value.integer.value[0] = sample_rate_val;
  816. pr_debug("%s: usb_audio_rx_sample_rate = %d\n", __func__,
  817. usb_rx_cfg.sample_rate);
  818. return 0;
  819. }
  820. static int usb_audio_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  821. struct snd_ctl_elem_value *ucontrol)
  822. {
  823. switch (ucontrol->value.integer.value[0]) {
  824. case 12:
  825. usb_rx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  826. break;
  827. case 11:
  828. usb_rx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  829. break;
  830. case 10:
  831. usb_rx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  832. break;
  833. case 9:
  834. usb_rx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  835. break;
  836. case 8:
  837. usb_rx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  838. break;
  839. case 7:
  840. usb_rx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  841. break;
  842. case 6:
  843. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  844. break;
  845. case 5:
  846. usb_rx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  847. break;
  848. case 4:
  849. usb_rx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  850. break;
  851. case 3:
  852. usb_rx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  853. break;
  854. case 2:
  855. usb_rx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  856. break;
  857. case 1:
  858. usb_rx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  859. break;
  860. case 0:
  861. usb_rx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  862. break;
  863. default:
  864. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  865. break;
  866. }
  867. pr_debug("%s: control value = %ld, usb_audio_rx_sample_rate = %d\n",
  868. __func__, ucontrol->value.integer.value[0],
  869. usb_rx_cfg.sample_rate);
  870. return 0;
  871. }
  872. static int usb_audio_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  873. struct snd_ctl_elem_value *ucontrol)
  874. {
  875. int sample_rate_val = 0;
  876. switch (usb_tx_cfg.sample_rate) {
  877. case SAMPLING_RATE_384KHZ:
  878. sample_rate_val = 12;
  879. break;
  880. case SAMPLING_RATE_352P8KHZ:
  881. sample_rate_val = 11;
  882. break;
  883. case SAMPLING_RATE_192KHZ:
  884. sample_rate_val = 10;
  885. break;
  886. case SAMPLING_RATE_176P4KHZ:
  887. sample_rate_val = 9;
  888. break;
  889. case SAMPLING_RATE_96KHZ:
  890. sample_rate_val = 8;
  891. break;
  892. case SAMPLING_RATE_88P2KHZ:
  893. sample_rate_val = 7;
  894. break;
  895. case SAMPLING_RATE_48KHZ:
  896. sample_rate_val = 6;
  897. break;
  898. case SAMPLING_RATE_44P1KHZ:
  899. sample_rate_val = 5;
  900. break;
  901. case SAMPLING_RATE_32KHZ:
  902. sample_rate_val = 4;
  903. break;
  904. case SAMPLING_RATE_22P05KHZ:
  905. sample_rate_val = 3;
  906. break;
  907. case SAMPLING_RATE_16KHZ:
  908. sample_rate_val = 2;
  909. break;
  910. case SAMPLING_RATE_11P025KHZ:
  911. sample_rate_val = 1;
  912. break;
  913. case SAMPLING_RATE_8KHZ:
  914. sample_rate_val = 0;
  915. break;
  916. default:
  917. sample_rate_val = 6;
  918. break;
  919. }
  920. ucontrol->value.integer.value[0] = sample_rate_val;
  921. pr_debug("%s: usb_audio_tx_sample_rate = %d\n", __func__,
  922. usb_tx_cfg.sample_rate);
  923. return 0;
  924. }
  925. static int usb_audio_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  926. struct snd_ctl_elem_value *ucontrol)
  927. {
  928. switch (ucontrol->value.integer.value[0]) {
  929. case 12:
  930. usb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  931. break;
  932. case 11:
  933. usb_tx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  934. break;
  935. case 10:
  936. usb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  937. break;
  938. case 9:
  939. usb_tx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  940. break;
  941. case 8:
  942. usb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  943. break;
  944. case 7:
  945. usb_tx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  946. break;
  947. case 6:
  948. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  949. break;
  950. case 5:
  951. usb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  952. break;
  953. case 4:
  954. usb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  955. break;
  956. case 3:
  957. usb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  958. break;
  959. case 2:
  960. usb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  961. break;
  962. case 1:
  963. usb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  964. break;
  965. case 0:
  966. usb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  967. break;
  968. default:
  969. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  970. break;
  971. }
  972. pr_debug("%s: control value = %ld, usb_audio_tx_sample_rate = %d\n",
  973. __func__, ucontrol->value.integer.value[0],
  974. usb_tx_cfg.sample_rate);
  975. return 0;
  976. }
  977. static int afe_loopback_tx_ch_get(struct snd_kcontrol *kcontrol,
  978. struct snd_ctl_elem_value *ucontrol)
  979. {
  980. pr_debug("%s: afe_loopback_tx_ch = %d\n", __func__,
  981. afe_loopback_tx_cfg[0].channels);
  982. ucontrol->value.enumerated.item[0] =
  983. afe_loopback_tx_cfg[0].channels - 1;
  984. return 0;
  985. }
  986. static int afe_loopback_tx_ch_put(struct snd_kcontrol *kcontrol,
  987. struct snd_ctl_elem_value *ucontrol)
  988. {
  989. afe_loopback_tx_cfg[0].channels =
  990. ucontrol->value.enumerated.item[0] + 1;
  991. pr_debug("%s: afe_loopback_tx_ch = %d\n", __func__,
  992. afe_loopback_tx_cfg[0].channels);
  993. return 1;
  994. }
  995. static int usb_audio_rx_format_get(struct snd_kcontrol *kcontrol,
  996. struct snd_ctl_elem_value *ucontrol)
  997. {
  998. switch (usb_rx_cfg.bit_format) {
  999. case SNDRV_PCM_FORMAT_S32_LE:
  1000. ucontrol->value.integer.value[0] = 3;
  1001. break;
  1002. case SNDRV_PCM_FORMAT_S24_3LE:
  1003. ucontrol->value.integer.value[0] = 2;
  1004. break;
  1005. case SNDRV_PCM_FORMAT_S24_LE:
  1006. ucontrol->value.integer.value[0] = 1;
  1007. break;
  1008. case SNDRV_PCM_FORMAT_S16_LE:
  1009. default:
  1010. ucontrol->value.integer.value[0] = 0;
  1011. break;
  1012. }
  1013. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1014. __func__, usb_rx_cfg.bit_format,
  1015. ucontrol->value.integer.value[0]);
  1016. return 0;
  1017. }
  1018. static int usb_audio_rx_format_put(struct snd_kcontrol *kcontrol,
  1019. struct snd_ctl_elem_value *ucontrol)
  1020. {
  1021. int rc = 0;
  1022. switch (ucontrol->value.integer.value[0]) {
  1023. case 3:
  1024. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1025. break;
  1026. case 2:
  1027. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1028. break;
  1029. case 1:
  1030. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1031. break;
  1032. case 0:
  1033. default:
  1034. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1035. break;
  1036. }
  1037. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1038. __func__, usb_rx_cfg.bit_format,
  1039. ucontrol->value.integer.value[0]);
  1040. return rc;
  1041. }
  1042. static int usb_audio_tx_format_get(struct snd_kcontrol *kcontrol,
  1043. struct snd_ctl_elem_value *ucontrol)
  1044. {
  1045. switch (usb_tx_cfg.bit_format) {
  1046. case SNDRV_PCM_FORMAT_S32_LE:
  1047. ucontrol->value.integer.value[0] = 3;
  1048. break;
  1049. case SNDRV_PCM_FORMAT_S24_3LE:
  1050. ucontrol->value.integer.value[0] = 2;
  1051. break;
  1052. case SNDRV_PCM_FORMAT_S24_LE:
  1053. ucontrol->value.integer.value[0] = 1;
  1054. break;
  1055. case SNDRV_PCM_FORMAT_S16_LE:
  1056. default:
  1057. ucontrol->value.integer.value[0] = 0;
  1058. break;
  1059. }
  1060. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1061. __func__, usb_tx_cfg.bit_format,
  1062. ucontrol->value.integer.value[0]);
  1063. return 0;
  1064. }
  1065. static int usb_audio_tx_format_put(struct snd_kcontrol *kcontrol,
  1066. struct snd_ctl_elem_value *ucontrol)
  1067. {
  1068. int rc = 0;
  1069. switch (ucontrol->value.integer.value[0]) {
  1070. case 3:
  1071. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1072. break;
  1073. case 2:
  1074. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1075. break;
  1076. case 1:
  1077. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1078. break;
  1079. case 0:
  1080. default:
  1081. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1082. break;
  1083. }
  1084. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1085. __func__, usb_tx_cfg.bit_format,
  1086. ucontrol->value.integer.value[0]);
  1087. return rc;
  1088. }
  1089. static int usb_audio_rx_ch_get(struct snd_kcontrol *kcontrol,
  1090. struct snd_ctl_elem_value *ucontrol)
  1091. {
  1092. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__,
  1093. usb_rx_cfg.channels);
  1094. ucontrol->value.integer.value[0] = usb_rx_cfg.channels - 1;
  1095. return 0;
  1096. }
  1097. static int usb_audio_rx_ch_put(struct snd_kcontrol *kcontrol,
  1098. struct snd_ctl_elem_value *ucontrol)
  1099. {
  1100. usb_rx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1101. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, usb_rx_cfg.channels);
  1102. return 1;
  1103. }
  1104. static int usb_audio_tx_ch_get(struct snd_kcontrol *kcontrol,
  1105. struct snd_ctl_elem_value *ucontrol)
  1106. {
  1107. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__,
  1108. usb_tx_cfg.channels);
  1109. ucontrol->value.integer.value[0] = usb_tx_cfg.channels - 1;
  1110. return 0;
  1111. }
  1112. static int usb_audio_tx_ch_put(struct snd_kcontrol *kcontrol,
  1113. struct snd_ctl_elem_value *ucontrol)
  1114. {
  1115. usb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1116. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, usb_tx_cfg.channels);
  1117. return 1;
  1118. }
  1119. static int msm_vi_feed_tx_ch_get(struct snd_kcontrol *kcontrol,
  1120. struct snd_ctl_elem_value *ucontrol)
  1121. {
  1122. ucontrol->value.integer.value[0] = msm_vi_feed_tx_ch - 1;
  1123. pr_debug("%s: msm_vi_feed_tx_ch = %ld\n", __func__,
  1124. ucontrol->value.integer.value[0]);
  1125. return 0;
  1126. }
  1127. static int msm_vi_feed_tx_ch_put(struct snd_kcontrol *kcontrol,
  1128. struct snd_ctl_elem_value *ucontrol)
  1129. {
  1130. msm_vi_feed_tx_ch = ucontrol->value.integer.value[0] + 1;
  1131. pr_debug("%s: msm_vi_feed_tx_ch = %d\n", __func__, msm_vi_feed_tx_ch);
  1132. return 1;
  1133. }
  1134. static int proxy_rx_ch_get(struct snd_kcontrol *kcontrol,
  1135. struct snd_ctl_elem_value *ucontrol)
  1136. {
  1137. pr_debug("%s: proxy_rx channels = %d\n",
  1138. __func__, proxy_rx_cfg.channels);
  1139. ucontrol->value.integer.value[0] = proxy_rx_cfg.channels - 2;
  1140. return 0;
  1141. }
  1142. static int proxy_rx_ch_put(struct snd_kcontrol *kcontrol,
  1143. struct snd_ctl_elem_value *ucontrol)
  1144. {
  1145. proxy_rx_cfg.channels = ucontrol->value.integer.value[0] + 2;
  1146. pr_debug("%s: proxy_rx channels = %d\n",
  1147. __func__, proxy_rx_cfg.channels);
  1148. return 1;
  1149. }
  1150. static int tdm_get_port_idx(struct snd_kcontrol *kcontrol,
  1151. struct tdm_port *port)
  1152. {
  1153. if (port) {
  1154. if (strnstr(kcontrol->id.name, "PRI",
  1155. sizeof(kcontrol->id.name))) {
  1156. port->mode = TDM_PRI;
  1157. } else if (strnstr(kcontrol->id.name, "SEC",
  1158. sizeof(kcontrol->id.name))) {
  1159. port->mode = TDM_SEC;
  1160. } else if (strnstr(kcontrol->id.name, "TERT",
  1161. sizeof(kcontrol->id.name))) {
  1162. port->mode = TDM_TERT;
  1163. } else if (strnstr(kcontrol->id.name, "QUAT",
  1164. sizeof(kcontrol->id.name))) {
  1165. port->mode = TDM_QUAT;
  1166. } else {
  1167. pr_err("%s: unsupported mode in: %s\n",
  1168. __func__, kcontrol->id.name);
  1169. return -EINVAL;
  1170. }
  1171. if (strnstr(kcontrol->id.name, "RX_0",
  1172. sizeof(kcontrol->id.name)) ||
  1173. strnstr(kcontrol->id.name, "TX_0",
  1174. sizeof(kcontrol->id.name))) {
  1175. port->channel = TDM_0;
  1176. } else if (strnstr(kcontrol->id.name, "RX_1",
  1177. sizeof(kcontrol->id.name)) ||
  1178. strnstr(kcontrol->id.name, "TX_1",
  1179. sizeof(kcontrol->id.name))) {
  1180. port->channel = TDM_1;
  1181. } else if (strnstr(kcontrol->id.name, "RX_2",
  1182. sizeof(kcontrol->id.name)) ||
  1183. strnstr(kcontrol->id.name, "TX_2",
  1184. sizeof(kcontrol->id.name))) {
  1185. port->channel = TDM_2;
  1186. } else if (strnstr(kcontrol->id.name, "RX_3",
  1187. sizeof(kcontrol->id.name)) ||
  1188. strnstr(kcontrol->id.name, "TX_3",
  1189. sizeof(kcontrol->id.name))) {
  1190. port->channel = TDM_3;
  1191. } else if (strnstr(kcontrol->id.name, "RX_4",
  1192. sizeof(kcontrol->id.name)) ||
  1193. strnstr(kcontrol->id.name, "TX_4",
  1194. sizeof(kcontrol->id.name))) {
  1195. port->channel = TDM_4;
  1196. } else if (strnstr(kcontrol->id.name, "RX_5",
  1197. sizeof(kcontrol->id.name)) ||
  1198. strnstr(kcontrol->id.name, "TX_5",
  1199. sizeof(kcontrol->id.name))) {
  1200. port->channel = TDM_5;
  1201. } else if (strnstr(kcontrol->id.name, "RX_6",
  1202. sizeof(kcontrol->id.name)) ||
  1203. strnstr(kcontrol->id.name, "TX_6",
  1204. sizeof(kcontrol->id.name))) {
  1205. port->channel = TDM_6;
  1206. } else if (strnstr(kcontrol->id.name, "RX_7",
  1207. sizeof(kcontrol->id.name)) ||
  1208. strnstr(kcontrol->id.name, "TX_7",
  1209. sizeof(kcontrol->id.name))) {
  1210. port->channel = TDM_7;
  1211. } else {
  1212. pr_err("%s: unsupported channel in: %s\n",
  1213. __func__, kcontrol->id.name);
  1214. return -EINVAL;
  1215. }
  1216. } else {
  1217. return -EINVAL;
  1218. }
  1219. return 0;
  1220. }
  1221. static int tdm_get_sample_rate(int value)
  1222. {
  1223. int sample_rate = 0;
  1224. switch (value) {
  1225. case 0:
  1226. sample_rate = SAMPLING_RATE_8KHZ;
  1227. break;
  1228. case 1:
  1229. sample_rate = SAMPLING_RATE_16KHZ;
  1230. break;
  1231. case 2:
  1232. sample_rate = SAMPLING_RATE_32KHZ;
  1233. break;
  1234. case 3:
  1235. sample_rate = SAMPLING_RATE_48KHZ;
  1236. break;
  1237. case 4:
  1238. sample_rate = SAMPLING_RATE_176P4KHZ;
  1239. break;
  1240. case 5:
  1241. sample_rate = SAMPLING_RATE_352P8KHZ;
  1242. break;
  1243. default:
  1244. sample_rate = SAMPLING_RATE_48KHZ;
  1245. break;
  1246. }
  1247. return sample_rate;
  1248. }
  1249. static int tdm_get_sample_rate_val(int sample_rate)
  1250. {
  1251. int sample_rate_val = 0;
  1252. switch (sample_rate) {
  1253. case SAMPLING_RATE_8KHZ:
  1254. sample_rate_val = 0;
  1255. break;
  1256. case SAMPLING_RATE_16KHZ:
  1257. sample_rate_val = 1;
  1258. break;
  1259. case SAMPLING_RATE_32KHZ:
  1260. sample_rate_val = 2;
  1261. break;
  1262. case SAMPLING_RATE_48KHZ:
  1263. sample_rate_val = 3;
  1264. break;
  1265. case SAMPLING_RATE_176P4KHZ:
  1266. sample_rate_val = 4;
  1267. break;
  1268. case SAMPLING_RATE_352P8KHZ:
  1269. sample_rate_val = 5;
  1270. break;
  1271. default:
  1272. sample_rate_val = 3;
  1273. break;
  1274. }
  1275. return sample_rate_val;
  1276. }
  1277. static int tdm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1278. struct snd_ctl_elem_value *ucontrol)
  1279. {
  1280. struct tdm_port port;
  1281. int ret = tdm_get_port_idx(kcontrol, &port);
  1282. if (ret) {
  1283. pr_err("%s: unsupported control: %s\n",
  1284. __func__, kcontrol->id.name);
  1285. } else {
  1286. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1287. tdm_rx_cfg[port.mode][port.channel].sample_rate);
  1288. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1289. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1290. ucontrol->value.enumerated.item[0]);
  1291. }
  1292. return ret;
  1293. }
  1294. static int tdm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1295. struct snd_ctl_elem_value *ucontrol)
  1296. {
  1297. struct tdm_port port;
  1298. int ret = tdm_get_port_idx(kcontrol, &port);
  1299. if (ret) {
  1300. pr_err("%s: unsupported control: %s\n",
  1301. __func__, kcontrol->id.name);
  1302. } else {
  1303. tdm_rx_cfg[port.mode][port.channel].sample_rate =
  1304. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1305. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1306. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1307. ucontrol->value.enumerated.item[0]);
  1308. }
  1309. return ret;
  1310. }
  1311. static int tdm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1312. struct snd_ctl_elem_value *ucontrol)
  1313. {
  1314. struct tdm_port port;
  1315. int ret = tdm_get_port_idx(kcontrol, &port);
  1316. if (ret) {
  1317. pr_err("%s: unsupported control: %s\n",
  1318. __func__, kcontrol->id.name);
  1319. } else {
  1320. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1321. tdm_tx_cfg[port.mode][port.channel].sample_rate);
  1322. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1323. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1324. ucontrol->value.enumerated.item[0]);
  1325. }
  1326. return ret;
  1327. }
  1328. static int tdm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1329. struct snd_ctl_elem_value *ucontrol)
  1330. {
  1331. struct tdm_port port;
  1332. int ret = tdm_get_port_idx(kcontrol, &port);
  1333. if (ret) {
  1334. pr_err("%s: unsupported control: %s\n",
  1335. __func__, kcontrol->id.name);
  1336. } else {
  1337. tdm_tx_cfg[port.mode][port.channel].sample_rate =
  1338. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1339. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1340. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1341. ucontrol->value.enumerated.item[0]);
  1342. }
  1343. return ret;
  1344. }
  1345. static int tdm_get_format(int value)
  1346. {
  1347. int format = 0;
  1348. switch (value) {
  1349. case 0:
  1350. format = SNDRV_PCM_FORMAT_S16_LE;
  1351. break;
  1352. case 1:
  1353. format = SNDRV_PCM_FORMAT_S24_LE;
  1354. break;
  1355. case 2:
  1356. format = SNDRV_PCM_FORMAT_S32_LE;
  1357. break;
  1358. default:
  1359. format = SNDRV_PCM_FORMAT_S16_LE;
  1360. break;
  1361. }
  1362. return format;
  1363. }
  1364. static int tdm_get_format_val(int format)
  1365. {
  1366. int value = 0;
  1367. switch (format) {
  1368. case SNDRV_PCM_FORMAT_S16_LE:
  1369. value = 0;
  1370. break;
  1371. case SNDRV_PCM_FORMAT_S24_LE:
  1372. value = 1;
  1373. break;
  1374. case SNDRV_PCM_FORMAT_S32_LE:
  1375. value = 2;
  1376. break;
  1377. default:
  1378. value = 0;
  1379. break;
  1380. }
  1381. return value;
  1382. }
  1383. static int tdm_rx_format_get(struct snd_kcontrol *kcontrol,
  1384. struct snd_ctl_elem_value *ucontrol)
  1385. {
  1386. struct tdm_port port;
  1387. int ret = tdm_get_port_idx(kcontrol, &port);
  1388. if (ret) {
  1389. pr_err("%s: unsupported control: %s\n",
  1390. __func__, kcontrol->id.name);
  1391. } else {
  1392. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  1393. tdm_rx_cfg[port.mode][port.channel].bit_format);
  1394. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  1395. tdm_rx_cfg[port.mode][port.channel].bit_format,
  1396. ucontrol->value.enumerated.item[0]);
  1397. }
  1398. return ret;
  1399. }
  1400. static int tdm_rx_format_put(struct snd_kcontrol *kcontrol,
  1401. struct snd_ctl_elem_value *ucontrol)
  1402. {
  1403. struct tdm_port port;
  1404. int ret = tdm_get_port_idx(kcontrol, &port);
  1405. if (ret) {
  1406. pr_err("%s: unsupported control: %s\n",
  1407. __func__, kcontrol->id.name);
  1408. } else {
  1409. tdm_rx_cfg[port.mode][port.channel].bit_format =
  1410. tdm_get_format(ucontrol->value.enumerated.item[0]);
  1411. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  1412. tdm_rx_cfg[port.mode][port.channel].bit_format,
  1413. ucontrol->value.enumerated.item[0]);
  1414. }
  1415. return ret;
  1416. }
  1417. static int tdm_tx_format_get(struct snd_kcontrol *kcontrol,
  1418. struct snd_ctl_elem_value *ucontrol)
  1419. {
  1420. struct tdm_port port;
  1421. int ret = tdm_get_port_idx(kcontrol, &port);
  1422. if (ret) {
  1423. pr_err("%s: unsupported control: %s\n",
  1424. __func__, kcontrol->id.name);
  1425. } else {
  1426. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  1427. tdm_tx_cfg[port.mode][port.channel].bit_format);
  1428. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  1429. tdm_tx_cfg[port.mode][port.channel].bit_format,
  1430. ucontrol->value.enumerated.item[0]);
  1431. }
  1432. return ret;
  1433. }
  1434. static int tdm_tx_format_put(struct snd_kcontrol *kcontrol,
  1435. struct snd_ctl_elem_value *ucontrol)
  1436. {
  1437. struct tdm_port port;
  1438. int ret = tdm_get_port_idx(kcontrol, &port);
  1439. if (ret) {
  1440. pr_err("%s: unsupported control: %s\n",
  1441. __func__, kcontrol->id.name);
  1442. } else {
  1443. tdm_tx_cfg[port.mode][port.channel].bit_format =
  1444. tdm_get_format(ucontrol->value.enumerated.item[0]);
  1445. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  1446. tdm_tx_cfg[port.mode][port.channel].bit_format,
  1447. ucontrol->value.enumerated.item[0]);
  1448. }
  1449. return ret;
  1450. }
  1451. static int tdm_rx_ch_get(struct snd_kcontrol *kcontrol,
  1452. struct snd_ctl_elem_value *ucontrol)
  1453. {
  1454. struct tdm_port port;
  1455. int ret = tdm_get_port_idx(kcontrol, &port);
  1456. if (ret) {
  1457. pr_err("%s: unsupported control: %s\n",
  1458. __func__, kcontrol->id.name);
  1459. } else {
  1460. ucontrol->value.enumerated.item[0] =
  1461. tdm_rx_cfg[port.mode][port.channel].channels - 1;
  1462. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  1463. tdm_rx_cfg[port.mode][port.channel].channels - 1,
  1464. ucontrol->value.enumerated.item[0]);
  1465. }
  1466. return ret;
  1467. }
  1468. static int tdm_rx_ch_put(struct snd_kcontrol *kcontrol,
  1469. struct snd_ctl_elem_value *ucontrol)
  1470. {
  1471. struct tdm_port port;
  1472. int ret = tdm_get_port_idx(kcontrol, &port);
  1473. if (ret) {
  1474. pr_err("%s: unsupported control: %s\n",
  1475. __func__, kcontrol->id.name);
  1476. } else {
  1477. tdm_rx_cfg[port.mode][port.channel].channels =
  1478. ucontrol->value.enumerated.item[0] + 1;
  1479. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  1480. tdm_rx_cfg[port.mode][port.channel].channels,
  1481. ucontrol->value.enumerated.item[0] + 1);
  1482. }
  1483. return ret;
  1484. }
  1485. static int tdm_tx_ch_get(struct snd_kcontrol *kcontrol,
  1486. struct snd_ctl_elem_value *ucontrol)
  1487. {
  1488. struct tdm_port port;
  1489. int ret = tdm_get_port_idx(kcontrol, &port);
  1490. if (ret) {
  1491. pr_err("%s: unsupported control: %s\n",
  1492. __func__, kcontrol->id.name);
  1493. } else {
  1494. ucontrol->value.enumerated.item[0] =
  1495. tdm_tx_cfg[port.mode][port.channel].channels - 1;
  1496. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  1497. tdm_tx_cfg[port.mode][port.channel].channels - 1,
  1498. ucontrol->value.enumerated.item[0]);
  1499. }
  1500. return ret;
  1501. }
  1502. static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol,
  1503. struct snd_ctl_elem_value *ucontrol)
  1504. {
  1505. struct tdm_port port;
  1506. int ret = tdm_get_port_idx(kcontrol, &port);
  1507. if (ret) {
  1508. pr_err("%s: unsupported control: %s\n",
  1509. __func__, kcontrol->id.name);
  1510. } else {
  1511. tdm_tx_cfg[port.mode][port.channel].channels =
  1512. ucontrol->value.enumerated.item[0] + 1;
  1513. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  1514. tdm_tx_cfg[port.mode][port.channel].channels,
  1515. ucontrol->value.enumerated.item[0] + 1);
  1516. }
  1517. return ret;
  1518. }
  1519. static int tdm_slot_map_put(struct snd_kcontrol *kcontrol,
  1520. struct snd_ctl_elem_value *ucontrol)
  1521. {
  1522. int slot_index = 0;
  1523. int interface = ucontrol->value.integer.value[0];
  1524. int channel = ucontrol->value.integer.value[1];
  1525. unsigned int offset_val = 0;
  1526. unsigned int *slot_offset = NULL;
  1527. struct tdm_dev_config *config = NULL;
  1528. if (interface < 0 || interface >= (TDM_INTERFACE_MAX * MAX_PATH)) {
  1529. pr_err("%s: incorrect interface = %d\n", __func__, interface);
  1530. return -EINVAL;
  1531. }
  1532. if (channel < 0 || channel >= TDM_PORT_MAX) {
  1533. pr_err("%s: incorrect channel = %d\n", __func__, channel);
  1534. return -EINVAL;
  1535. }
  1536. pr_debug("%s: interface = %d, channel = %d\n", __func__,
  1537. interface, channel);
  1538. config = ((struct tdm_dev_config *) tdm_cfg[interface / MAX_PATH]) +
  1539. ((interface % MAX_PATH) * TDM_PORT_MAX) + channel;
  1540. slot_offset = config->tdm_slot_offset;
  1541. for (slot_index = 0; slot_index < TDM_MAX_SLOTS; slot_index++) {
  1542. offset_val = ucontrol->value.integer.value[MAX_PATH +
  1543. slot_index];
  1544. /* Offset value can only be 0, 4, 8, ..28 */
  1545. if (offset_val % 4 == 0 && offset_val <= 28)
  1546. slot_offset[slot_index] = offset_val;
  1547. pr_debug("%s: slot offset[%d] = %d\n", __func__,
  1548. slot_index, slot_offset[slot_index]);
  1549. }
  1550. return 0;
  1551. }
  1552. static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol)
  1553. {
  1554. int idx = 0;
  1555. if (strnstr(kcontrol->id.name, "PRIM_AUX_PCM",
  1556. sizeof("PRIM_AUX_PCM"))) {
  1557. idx = PRIM_AUX_PCM;
  1558. } else if (strnstr(kcontrol->id.name, "SEC_AUX_PCM",
  1559. sizeof("SEC_AUX_PCM"))) {
  1560. idx = SEC_AUX_PCM;
  1561. } else if (strnstr(kcontrol->id.name, "TERT_AUX_PCM",
  1562. sizeof("TERT_AUX_PCM"))) {
  1563. idx = TERT_AUX_PCM;
  1564. } else if (strnstr(kcontrol->id.name, "QUAT_AUX_PCM",
  1565. sizeof("QUAT_AUX_PCM"))) {
  1566. idx = QUAT_AUX_PCM;
  1567. } else {
  1568. pr_err("%s: unsupported port: %s\n",
  1569. __func__, kcontrol->id.name);
  1570. idx = -EINVAL;
  1571. }
  1572. return idx;
  1573. }
  1574. static int aux_pcm_get_sample_rate(int value)
  1575. {
  1576. int sample_rate = 0;
  1577. switch (value) {
  1578. case 1:
  1579. sample_rate = SAMPLING_RATE_16KHZ;
  1580. break;
  1581. case 0:
  1582. default:
  1583. sample_rate = SAMPLING_RATE_8KHZ;
  1584. break;
  1585. }
  1586. return sample_rate;
  1587. }
  1588. static int aux_pcm_get_sample_rate_val(int sample_rate)
  1589. {
  1590. int sample_rate_val = 0;
  1591. switch (sample_rate) {
  1592. case SAMPLING_RATE_16KHZ:
  1593. sample_rate_val = 1;
  1594. break;
  1595. case SAMPLING_RATE_8KHZ:
  1596. default:
  1597. sample_rate_val = 0;
  1598. break;
  1599. }
  1600. return sample_rate_val;
  1601. }
  1602. static int mi2s_auxpcm_get_format(int value)
  1603. {
  1604. int format = 0;
  1605. switch (value) {
  1606. case 0:
  1607. format = SNDRV_PCM_FORMAT_S16_LE;
  1608. break;
  1609. case 1:
  1610. format = SNDRV_PCM_FORMAT_S24_LE;
  1611. break;
  1612. case 2:
  1613. format = SNDRV_PCM_FORMAT_S24_3LE;
  1614. break;
  1615. case 3:
  1616. format = SNDRV_PCM_FORMAT_S32_LE;
  1617. break;
  1618. default:
  1619. format = SNDRV_PCM_FORMAT_S16_LE;
  1620. break;
  1621. }
  1622. return format;
  1623. }
  1624. static int mi2s_auxpcm_get_format_value(int format)
  1625. {
  1626. int value = 0;
  1627. switch (format) {
  1628. case SNDRV_PCM_FORMAT_S16_LE:
  1629. value = 0;
  1630. break;
  1631. case SNDRV_PCM_FORMAT_S24_LE:
  1632. value = 1;
  1633. break;
  1634. case SNDRV_PCM_FORMAT_S24_3LE:
  1635. value = 2;
  1636. break;
  1637. case SNDRV_PCM_FORMAT_S32_LE:
  1638. value = 3;
  1639. break;
  1640. default:
  1641. value = 0;
  1642. break;
  1643. }
  1644. return value;
  1645. }
  1646. static int aux_pcm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1647. struct snd_ctl_elem_value *ucontrol)
  1648. {
  1649. int idx = aux_pcm_get_port_idx(kcontrol);
  1650. if (idx < 0)
  1651. return idx;
  1652. ucontrol->value.enumerated.item[0] =
  1653. aux_pcm_get_sample_rate_val(aux_pcm_rx_cfg[idx].sample_rate);
  1654. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1655. idx, aux_pcm_rx_cfg[idx].sample_rate,
  1656. ucontrol->value.enumerated.item[0]);
  1657. return 0;
  1658. }
  1659. static int aux_pcm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1660. struct snd_ctl_elem_value *ucontrol)
  1661. {
  1662. int idx = aux_pcm_get_port_idx(kcontrol);
  1663. if (idx < 0)
  1664. return idx;
  1665. aux_pcm_rx_cfg[idx].sample_rate =
  1666. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1667. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1668. idx, aux_pcm_rx_cfg[idx].sample_rate,
  1669. ucontrol->value.enumerated.item[0]);
  1670. return 0;
  1671. }
  1672. static int aux_pcm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1673. struct snd_ctl_elem_value *ucontrol)
  1674. {
  1675. int idx = aux_pcm_get_port_idx(kcontrol);
  1676. if (idx < 0)
  1677. return idx;
  1678. ucontrol->value.enumerated.item[0] =
  1679. aux_pcm_get_sample_rate_val(aux_pcm_tx_cfg[idx].sample_rate);
  1680. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1681. idx, aux_pcm_tx_cfg[idx].sample_rate,
  1682. ucontrol->value.enumerated.item[0]);
  1683. return 0;
  1684. }
  1685. static int aux_pcm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1686. struct snd_ctl_elem_value *ucontrol)
  1687. {
  1688. int idx = aux_pcm_get_port_idx(kcontrol);
  1689. if (idx < 0)
  1690. return idx;
  1691. aux_pcm_tx_cfg[idx].sample_rate =
  1692. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1693. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1694. idx, aux_pcm_tx_cfg[idx].sample_rate,
  1695. ucontrol->value.enumerated.item[0]);
  1696. return 0;
  1697. }
  1698. static int msm_aux_pcm_rx_format_get(struct snd_kcontrol *kcontrol,
  1699. struct snd_ctl_elem_value *ucontrol)
  1700. {
  1701. int idx = aux_pcm_get_port_idx(kcontrol);
  1702. if (idx < 0)
  1703. return idx;
  1704. ucontrol->value.enumerated.item[0] =
  1705. mi2s_auxpcm_get_format_value(aux_pcm_rx_cfg[idx].bit_format);
  1706. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1707. idx, aux_pcm_rx_cfg[idx].bit_format,
  1708. ucontrol->value.enumerated.item[0]);
  1709. return 0;
  1710. }
  1711. static int msm_aux_pcm_rx_format_put(struct snd_kcontrol *kcontrol,
  1712. struct snd_ctl_elem_value *ucontrol)
  1713. {
  1714. int idx = aux_pcm_get_port_idx(kcontrol);
  1715. if (idx < 0)
  1716. return idx;
  1717. aux_pcm_rx_cfg[idx].bit_format =
  1718. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  1719. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1720. idx, aux_pcm_rx_cfg[idx].bit_format,
  1721. ucontrol->value.enumerated.item[0]);
  1722. return 0;
  1723. }
  1724. static int msm_aux_pcm_tx_format_get(struct snd_kcontrol *kcontrol,
  1725. struct snd_ctl_elem_value *ucontrol)
  1726. {
  1727. int idx = aux_pcm_get_port_idx(kcontrol);
  1728. if (idx < 0)
  1729. return idx;
  1730. ucontrol->value.enumerated.item[0] =
  1731. mi2s_auxpcm_get_format_value(aux_pcm_tx_cfg[idx].bit_format);
  1732. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  1733. idx, aux_pcm_tx_cfg[idx].bit_format,
  1734. ucontrol->value.enumerated.item[0]);
  1735. return 0;
  1736. }
  1737. static int msm_aux_pcm_tx_format_put(struct snd_kcontrol *kcontrol,
  1738. struct snd_ctl_elem_value *ucontrol)
  1739. {
  1740. int idx = aux_pcm_get_port_idx(kcontrol);
  1741. if (idx < 0)
  1742. return idx;
  1743. aux_pcm_tx_cfg[idx].bit_format =
  1744. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  1745. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  1746. idx, aux_pcm_tx_cfg[idx].bit_format,
  1747. ucontrol->value.enumerated.item[0]);
  1748. return 0;
  1749. }
  1750. static int mi2s_get_port_idx(struct snd_kcontrol *kcontrol)
  1751. {
  1752. int idx = 0;
  1753. if (strnstr(kcontrol->id.name, "PRIM_MI2S_RX",
  1754. sizeof("PRIM_MI2S_RX"))) {
  1755. idx = PRIM_MI2S;
  1756. } else if (strnstr(kcontrol->id.name, "SEC_MI2S_RX",
  1757. sizeof("SEC_MI2S_RX"))) {
  1758. idx = SEC_MI2S;
  1759. } else if (strnstr(kcontrol->id.name, "TERT_MI2S_RX",
  1760. sizeof("TERT_MI2S_RX"))) {
  1761. idx = TERT_MI2S;
  1762. } else if (strnstr(kcontrol->id.name, "QUAT_MI2S_RX",
  1763. sizeof("QUAT_MI2S_RX"))) {
  1764. idx = QUAT_MI2S;
  1765. } else if (strnstr(kcontrol->id.name, "PRIM_MI2S_TX",
  1766. sizeof("PRIM_MI2S_TX"))) {
  1767. idx = PRIM_MI2S;
  1768. } else if (strnstr(kcontrol->id.name, "SEC_MI2S_TX",
  1769. sizeof("SEC_MI2S_TX"))) {
  1770. idx = SEC_MI2S;
  1771. } else if (strnstr(kcontrol->id.name, "TERT_MI2S_TX",
  1772. sizeof("TERT_MI2S_TX"))) {
  1773. idx = TERT_MI2S;
  1774. } else if (strnstr(kcontrol->id.name, "QUAT_MI2S_TX",
  1775. sizeof("QUAT_MI2S_TX"))) {
  1776. idx = QUAT_MI2S;
  1777. } else {
  1778. pr_err("%s: unsupported channel: %s\n",
  1779. __func__, kcontrol->id.name);
  1780. idx = -EINVAL;
  1781. }
  1782. return idx;
  1783. }
  1784. static int mi2s_get_sample_rate(int value)
  1785. {
  1786. int sample_rate = 0;
  1787. switch (value) {
  1788. case 0:
  1789. sample_rate = SAMPLING_RATE_8KHZ;
  1790. break;
  1791. case 1:
  1792. sample_rate = SAMPLING_RATE_11P025KHZ;
  1793. break;
  1794. case 2:
  1795. sample_rate = SAMPLING_RATE_16KHZ;
  1796. break;
  1797. case 3:
  1798. sample_rate = SAMPLING_RATE_22P05KHZ;
  1799. break;
  1800. case 4:
  1801. sample_rate = SAMPLING_RATE_32KHZ;
  1802. break;
  1803. case 5:
  1804. sample_rate = SAMPLING_RATE_44P1KHZ;
  1805. break;
  1806. case 6:
  1807. sample_rate = SAMPLING_RATE_48KHZ;
  1808. break;
  1809. case 7:
  1810. sample_rate = SAMPLING_RATE_88P2KHZ;
  1811. break;
  1812. case 8:
  1813. sample_rate = SAMPLING_RATE_96KHZ;
  1814. break;
  1815. case 9:
  1816. sample_rate = SAMPLING_RATE_176P4KHZ;
  1817. break;
  1818. case 10:
  1819. sample_rate = SAMPLING_RATE_192KHZ;
  1820. break;
  1821. case 11:
  1822. sample_rate = SAMPLING_RATE_352P8KHZ;
  1823. break;
  1824. case 12:
  1825. sample_rate = SAMPLING_RATE_384KHZ;
  1826. break;
  1827. default:
  1828. sample_rate = SAMPLING_RATE_48KHZ;
  1829. break;
  1830. }
  1831. return sample_rate;
  1832. }
  1833. static int mi2s_get_sample_rate_val(int sample_rate)
  1834. {
  1835. int sample_rate_val = 0;
  1836. switch (sample_rate) {
  1837. case SAMPLING_RATE_8KHZ:
  1838. sample_rate_val = 0;
  1839. break;
  1840. case SAMPLING_RATE_11P025KHZ:
  1841. sample_rate_val = 1;
  1842. break;
  1843. case SAMPLING_RATE_16KHZ:
  1844. sample_rate_val = 2;
  1845. break;
  1846. case SAMPLING_RATE_22P05KHZ:
  1847. sample_rate_val = 3;
  1848. break;
  1849. case SAMPLING_RATE_32KHZ:
  1850. sample_rate_val = 4;
  1851. break;
  1852. case SAMPLING_RATE_44P1KHZ:
  1853. sample_rate_val = 5;
  1854. break;
  1855. case SAMPLING_RATE_48KHZ:
  1856. sample_rate_val = 6;
  1857. break;
  1858. case SAMPLING_RATE_88P2KHZ:
  1859. sample_rate_val = 7;
  1860. break;
  1861. case SAMPLING_RATE_96KHZ:
  1862. sample_rate_val = 8;
  1863. break;
  1864. case SAMPLING_RATE_176P4KHZ:
  1865. sample_rate_val = 9;
  1866. break;
  1867. case SAMPLING_RATE_192KHZ:
  1868. sample_rate_val = 10;
  1869. break;
  1870. case SAMPLING_RATE_352P8KHZ:
  1871. sample_rate_val = 11;
  1872. break;
  1873. case SAMPLING_RATE_384KHZ:
  1874. sample_rate_val = 12;
  1875. break;
  1876. default:
  1877. sample_rate_val = 6;
  1878. break;
  1879. }
  1880. return sample_rate_val;
  1881. }
  1882. static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1883. struct snd_ctl_elem_value *ucontrol)
  1884. {
  1885. int idx = mi2s_get_port_idx(kcontrol);
  1886. if (idx < 0)
  1887. return idx;
  1888. ucontrol->value.enumerated.item[0] =
  1889. mi2s_get_sample_rate_val(mi2s_rx_cfg[idx].sample_rate);
  1890. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1891. idx, mi2s_rx_cfg[idx].sample_rate,
  1892. ucontrol->value.enumerated.item[0]);
  1893. return 0;
  1894. }
  1895. static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1896. struct snd_ctl_elem_value *ucontrol)
  1897. {
  1898. int idx = mi2s_get_port_idx(kcontrol);
  1899. if (idx < 0)
  1900. return idx;
  1901. mi2s_rx_cfg[idx].sample_rate =
  1902. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1903. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1904. idx, mi2s_rx_cfg[idx].sample_rate,
  1905. ucontrol->value.enumerated.item[0]);
  1906. return 0;
  1907. }
  1908. static int mi2s_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1909. struct snd_ctl_elem_value *ucontrol)
  1910. {
  1911. int idx = mi2s_get_port_idx(kcontrol);
  1912. if (idx < 0)
  1913. return idx;
  1914. ucontrol->value.enumerated.item[0] =
  1915. mi2s_get_sample_rate_val(mi2s_tx_cfg[idx].sample_rate);
  1916. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1917. idx, mi2s_tx_cfg[idx].sample_rate,
  1918. ucontrol->value.enumerated.item[0]);
  1919. return 0;
  1920. }
  1921. static int mi2s_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1922. struct snd_ctl_elem_value *ucontrol)
  1923. {
  1924. int idx = mi2s_get_port_idx(kcontrol);
  1925. if (idx < 0)
  1926. return idx;
  1927. mi2s_tx_cfg[idx].sample_rate =
  1928. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1929. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1930. idx, mi2s_tx_cfg[idx].sample_rate,
  1931. ucontrol->value.enumerated.item[0]);
  1932. return 0;
  1933. }
  1934. static int msm_mi2s_rx_format_get(struct snd_kcontrol *kcontrol,
  1935. struct snd_ctl_elem_value *ucontrol)
  1936. {
  1937. int idx = mi2s_get_port_idx(kcontrol);
  1938. if (idx < 0)
  1939. return idx;
  1940. ucontrol->value.enumerated.item[0] =
  1941. mi2s_auxpcm_get_format_value(mi2s_rx_cfg[idx].bit_format);
  1942. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1943. idx, mi2s_rx_cfg[idx].bit_format,
  1944. ucontrol->value.enumerated.item[0]);
  1945. return 0;
  1946. }
  1947. static int msm_mi2s_rx_format_put(struct snd_kcontrol *kcontrol,
  1948. struct snd_ctl_elem_value *ucontrol)
  1949. {
  1950. int idx = mi2s_get_port_idx(kcontrol);
  1951. if (idx < 0)
  1952. return idx;
  1953. mi2s_rx_cfg[idx].bit_format =
  1954. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  1955. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1956. idx, mi2s_rx_cfg[idx].bit_format,
  1957. ucontrol->value.enumerated.item[0]);
  1958. return 0;
  1959. }
  1960. static int msm_mi2s_tx_format_get(struct snd_kcontrol *kcontrol,
  1961. struct snd_ctl_elem_value *ucontrol)
  1962. {
  1963. int idx = mi2s_get_port_idx(kcontrol);
  1964. if (idx < 0)
  1965. return idx;
  1966. ucontrol->value.enumerated.item[0] =
  1967. mi2s_auxpcm_get_format_value(mi2s_tx_cfg[idx].bit_format);
  1968. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  1969. idx, mi2s_tx_cfg[idx].bit_format,
  1970. ucontrol->value.enumerated.item[0]);
  1971. return 0;
  1972. }
  1973. static int msm_mi2s_tx_format_put(struct snd_kcontrol *kcontrol,
  1974. struct snd_ctl_elem_value *ucontrol)
  1975. {
  1976. int idx = mi2s_get_port_idx(kcontrol);
  1977. if (idx < 0)
  1978. return idx;
  1979. mi2s_tx_cfg[idx].bit_format =
  1980. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  1981. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  1982. idx, mi2s_tx_cfg[idx].bit_format,
  1983. ucontrol->value.enumerated.item[0]);
  1984. return 0;
  1985. }
  1986. static int msm_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
  1987. struct snd_ctl_elem_value *ucontrol)
  1988. {
  1989. int idx = mi2s_get_port_idx(kcontrol);
  1990. if (idx < 0)
  1991. return idx;
  1992. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  1993. idx, mi2s_rx_cfg[idx].channels);
  1994. ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].channels - 1;
  1995. return 0;
  1996. }
  1997. static int msm_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
  1998. struct snd_ctl_elem_value *ucontrol)
  1999. {
  2000. int idx = mi2s_get_port_idx(kcontrol);
  2001. if (idx < 0)
  2002. return idx;
  2003. mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2004. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2005. idx, mi2s_rx_cfg[idx].channels);
  2006. return 1;
  2007. }
  2008. static int msm_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol,
  2009. struct snd_ctl_elem_value *ucontrol)
  2010. {
  2011. int idx = mi2s_get_port_idx(kcontrol);
  2012. if (idx < 0)
  2013. return idx;
  2014. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2015. idx, mi2s_tx_cfg[idx].channels);
  2016. ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].channels - 1;
  2017. return 0;
  2018. }
  2019. static int msm_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol,
  2020. struct snd_ctl_elem_value *ucontrol)
  2021. {
  2022. int idx = mi2s_get_port_idx(kcontrol);
  2023. if (idx < 0)
  2024. return idx;
  2025. mi2s_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2026. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2027. idx, mi2s_tx_cfg[idx].channels);
  2028. return 1;
  2029. }
  2030. static int msm_get_port_id(int be_id)
  2031. {
  2032. int afe_port_id = 0;
  2033. switch (be_id) {
  2034. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  2035. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX;
  2036. break;
  2037. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  2038. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX;
  2039. break;
  2040. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  2041. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_RX;
  2042. break;
  2043. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  2044. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX;
  2045. break;
  2046. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  2047. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_RX;
  2048. break;
  2049. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  2050. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX;
  2051. break;
  2052. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  2053. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_RX;
  2054. break;
  2055. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  2056. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_TX;
  2057. break;
  2058. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  2059. afe_port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_0;
  2060. break;
  2061. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  2062. afe_port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_1;
  2063. break;
  2064. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  2065. afe_port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_2;
  2066. break;
  2067. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_0:
  2068. afe_port_id = AFE_PORT_ID_RX_CODEC_DMA_RX_0;
  2069. break;
  2070. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_0:
  2071. afe_port_id = AFE_PORT_ID_TX_CODEC_DMA_TX_0;
  2072. break;
  2073. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_1:
  2074. afe_port_id = AFE_PORT_ID_RX_CODEC_DMA_RX_1;
  2075. break;
  2076. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_1:
  2077. afe_port_id = AFE_PORT_ID_TX_CODEC_DMA_TX_1;
  2078. break;
  2079. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_2:
  2080. afe_port_id = AFE_PORT_ID_RX_CODEC_DMA_RX_2;
  2081. break;
  2082. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_2:
  2083. afe_port_id = AFE_PORT_ID_TX_CODEC_DMA_TX_2;
  2084. break;
  2085. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_3:
  2086. afe_port_id = AFE_PORT_ID_RX_CODEC_DMA_RX_3;
  2087. break;
  2088. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_3:
  2089. afe_port_id = AFE_PORT_ID_TX_CODEC_DMA_TX_3;
  2090. break;
  2091. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_4:
  2092. afe_port_id = AFE_PORT_ID_RX_CODEC_DMA_RX_4;
  2093. break;
  2094. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_4:
  2095. afe_port_id = AFE_PORT_ID_TX_CODEC_DMA_TX_4;
  2096. break;
  2097. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_5:
  2098. afe_port_id = AFE_PORT_ID_RX_CODEC_DMA_RX_5;
  2099. break;
  2100. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_5:
  2101. afe_port_id = AFE_PORT_ID_TX_CODEC_DMA_TX_5;
  2102. break;
  2103. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_6:
  2104. afe_port_id = AFE_PORT_ID_RX_CODEC_DMA_RX_6;
  2105. break;
  2106. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_7:
  2107. afe_port_id = AFE_PORT_ID_RX_CODEC_DMA_RX_7;
  2108. break;
  2109. default:
  2110. pr_err("%s: Invalid BE id: %d\n", __func__, be_id);
  2111. afe_port_id = -EINVAL;
  2112. }
  2113. return afe_port_id;
  2114. }
  2115. static u32 get_mi2s_bits_per_sample(u32 bit_format)
  2116. {
  2117. u32 bit_per_sample = 0;
  2118. switch (bit_format) {
  2119. case SNDRV_PCM_FORMAT_S32_LE:
  2120. case SNDRV_PCM_FORMAT_S24_3LE:
  2121. case SNDRV_PCM_FORMAT_S24_LE:
  2122. bit_per_sample = 32;
  2123. break;
  2124. case SNDRV_PCM_FORMAT_S16_LE:
  2125. default:
  2126. bit_per_sample = 16;
  2127. break;
  2128. }
  2129. return bit_per_sample;
  2130. }
  2131. static void update_mi2s_clk_val(int dai_id, int stream)
  2132. {
  2133. u32 bit_per_sample = 0;
  2134. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  2135. bit_per_sample =
  2136. get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format);
  2137. mi2s_clk[dai_id].clk_freq_in_hz =
  2138. mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  2139. } else {
  2140. bit_per_sample =
  2141. get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format);
  2142. mi2s_clk[dai_id].clk_freq_in_hz =
  2143. mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  2144. }
  2145. }
  2146. static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable)
  2147. {
  2148. int ret = 0;
  2149. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  2150. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  2151. int port_id = 0;
  2152. int index = cpu_dai->id;
  2153. port_id = msm_get_port_id(rtd->dai_link->id);
  2154. if (port_id < 0) {
  2155. dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__);
  2156. ret = port_id;
  2157. goto err;
  2158. }
  2159. if (enable) {
  2160. update_mi2s_clk_val(index, substream->stream);
  2161. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  2162. mi2s_clk[index].clk_freq_in_hz);
  2163. }
  2164. mi2s_clk[index].enable = enable;
  2165. ret = afe_set_lpass_clock_v2(port_id,
  2166. &mi2s_clk[index]);
  2167. if (ret < 0) {
  2168. dev_err(rtd->card->dev,
  2169. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  2170. __func__, port_id, ret);
  2171. goto err;
  2172. }
  2173. err:
  2174. return ret;
  2175. }
  2176. static int cdc_dma_get_port_idx(struct snd_kcontrol *kcontrol)
  2177. {
  2178. int idx = 0;
  2179. if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_0",
  2180. sizeof("RX_CDC_DMA_RX_0")))
  2181. idx = RX_CDC_DMA_RX_0;
  2182. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_1",
  2183. sizeof("RX_CDC_DMA_RX_1")))
  2184. idx = RX_CDC_DMA_RX_1;
  2185. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_2",
  2186. sizeof("RX_CDC_DMA_RX_2")))
  2187. idx = RX_CDC_DMA_RX_2;
  2188. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_3",
  2189. sizeof("RX_CDC_DMA_RX_3")))
  2190. idx = RX_CDC_DMA_RX_3;
  2191. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_5",
  2192. sizeof("RX_CDC_DMA_RX_5")))
  2193. idx = RX_CDC_DMA_RX_5;
  2194. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_6",
  2195. sizeof("RX_CDC_DMA_RX_6")))
  2196. idx = RX_CDC_DMA_RX_6;
  2197. else if (strnstr(kcontrol->id.name, "TX_CDC_DMA_TX_0",
  2198. sizeof("TX_CDC_DMA_TX_0")))
  2199. idx = TX_CDC_DMA_TX_0;
  2200. else if (strnstr(kcontrol->id.name, "TX_CDC_DMA_TX_3",
  2201. sizeof("TX_CDC_DMA_TX_3")))
  2202. idx = TX_CDC_DMA_TX_3;
  2203. else if (strnstr(kcontrol->id.name, "TX_CDC_DMA_TX_4",
  2204. sizeof("TX_CDC_DMA_TX_4")))
  2205. idx = TX_CDC_DMA_TX_4;
  2206. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_0",
  2207. sizeof("VA_CDC_DMA_TX_0")))
  2208. idx = VA_CDC_DMA_TX_0;
  2209. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_1",
  2210. sizeof("VA_CDC_DMA_TX_1")))
  2211. idx = VA_CDC_DMA_TX_1;
  2212. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_2",
  2213. sizeof("VA_CDC_DMA_TX_2")))
  2214. idx = VA_CDC_DMA_TX_2;
  2215. else {
  2216. pr_err("%s: unsupported channel: %s\n",
  2217. __func__, kcontrol->id.name);
  2218. return -EINVAL;
  2219. }
  2220. return idx;
  2221. }
  2222. static int cdc_dma_rx_ch_get(struct snd_kcontrol *kcontrol,
  2223. struct snd_ctl_elem_value *ucontrol)
  2224. {
  2225. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2226. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2227. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2228. return ch_num;
  2229. }
  2230. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  2231. cdc_dma_rx_cfg[ch_num].channels - 1);
  2232. ucontrol->value.integer.value[0] = cdc_dma_rx_cfg[ch_num].channels - 1;
  2233. return 0;
  2234. }
  2235. static int cdc_dma_rx_ch_put(struct snd_kcontrol *kcontrol,
  2236. struct snd_ctl_elem_value *ucontrol)
  2237. {
  2238. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2239. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2240. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2241. return ch_num;
  2242. }
  2243. cdc_dma_rx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  2244. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  2245. cdc_dma_rx_cfg[ch_num].channels);
  2246. return 1;
  2247. }
  2248. static int cdc_dma_rx_format_get(struct snd_kcontrol *kcontrol,
  2249. struct snd_ctl_elem_value *ucontrol)
  2250. {
  2251. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2252. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2253. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2254. return ch_num;
  2255. }
  2256. switch (cdc_dma_rx_cfg[ch_num].bit_format) {
  2257. case SNDRV_PCM_FORMAT_S32_LE:
  2258. ucontrol->value.integer.value[0] = 3;
  2259. break;
  2260. case SNDRV_PCM_FORMAT_S24_3LE:
  2261. ucontrol->value.integer.value[0] = 2;
  2262. break;
  2263. case SNDRV_PCM_FORMAT_S24_LE:
  2264. ucontrol->value.integer.value[0] = 1;
  2265. break;
  2266. case SNDRV_PCM_FORMAT_S16_LE:
  2267. default:
  2268. ucontrol->value.integer.value[0] = 0;
  2269. break;
  2270. }
  2271. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  2272. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  2273. ucontrol->value.integer.value[0]);
  2274. return 0;
  2275. }
  2276. static int cdc_dma_rx_format_put(struct snd_kcontrol *kcontrol,
  2277. struct snd_ctl_elem_value *ucontrol)
  2278. {
  2279. int rc = 0;
  2280. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2281. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2282. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2283. return ch_num;
  2284. }
  2285. switch (ucontrol->value.integer.value[0]) {
  2286. case 3:
  2287. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  2288. break;
  2289. case 2:
  2290. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  2291. break;
  2292. case 1:
  2293. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  2294. break;
  2295. case 0:
  2296. default:
  2297. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  2298. break;
  2299. }
  2300. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  2301. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  2302. ucontrol->value.integer.value[0]);
  2303. return rc;
  2304. }
  2305. static int cdc_dma_get_sample_rate_val(int sample_rate)
  2306. {
  2307. int sample_rate_val = 0;
  2308. switch (sample_rate) {
  2309. case SAMPLING_RATE_8KHZ:
  2310. sample_rate_val = 0;
  2311. break;
  2312. case SAMPLING_RATE_11P025KHZ:
  2313. sample_rate_val = 1;
  2314. break;
  2315. case SAMPLING_RATE_16KHZ:
  2316. sample_rate_val = 2;
  2317. break;
  2318. case SAMPLING_RATE_22P05KHZ:
  2319. sample_rate_val = 3;
  2320. break;
  2321. case SAMPLING_RATE_32KHZ:
  2322. sample_rate_val = 4;
  2323. break;
  2324. case SAMPLING_RATE_44P1KHZ:
  2325. sample_rate_val = 5;
  2326. break;
  2327. case SAMPLING_RATE_48KHZ:
  2328. sample_rate_val = 6;
  2329. break;
  2330. case SAMPLING_RATE_88P2KHZ:
  2331. sample_rate_val = 7;
  2332. break;
  2333. case SAMPLING_RATE_96KHZ:
  2334. sample_rate_val = 8;
  2335. break;
  2336. case SAMPLING_RATE_176P4KHZ:
  2337. sample_rate_val = 9;
  2338. break;
  2339. case SAMPLING_RATE_192KHZ:
  2340. sample_rate_val = 10;
  2341. break;
  2342. case SAMPLING_RATE_352P8KHZ:
  2343. sample_rate_val = 11;
  2344. break;
  2345. case SAMPLING_RATE_384KHZ:
  2346. sample_rate_val = 12;
  2347. break;
  2348. default:
  2349. sample_rate_val = 6;
  2350. break;
  2351. }
  2352. return sample_rate_val;
  2353. }
  2354. static int cdc_dma_get_sample_rate(int value)
  2355. {
  2356. int sample_rate = 0;
  2357. switch (value) {
  2358. case 0:
  2359. sample_rate = SAMPLING_RATE_8KHZ;
  2360. break;
  2361. case 1:
  2362. sample_rate = SAMPLING_RATE_11P025KHZ;
  2363. break;
  2364. case 2:
  2365. sample_rate = SAMPLING_RATE_16KHZ;
  2366. break;
  2367. case 3:
  2368. sample_rate = SAMPLING_RATE_22P05KHZ;
  2369. break;
  2370. case 4:
  2371. sample_rate = SAMPLING_RATE_32KHZ;
  2372. break;
  2373. case 5:
  2374. sample_rate = SAMPLING_RATE_44P1KHZ;
  2375. break;
  2376. case 6:
  2377. sample_rate = SAMPLING_RATE_48KHZ;
  2378. break;
  2379. case 7:
  2380. sample_rate = SAMPLING_RATE_88P2KHZ;
  2381. break;
  2382. case 8:
  2383. sample_rate = SAMPLING_RATE_96KHZ;
  2384. break;
  2385. case 9:
  2386. sample_rate = SAMPLING_RATE_176P4KHZ;
  2387. break;
  2388. case 10:
  2389. sample_rate = SAMPLING_RATE_192KHZ;
  2390. break;
  2391. case 11:
  2392. sample_rate = SAMPLING_RATE_352P8KHZ;
  2393. break;
  2394. case 12:
  2395. sample_rate = SAMPLING_RATE_384KHZ;
  2396. break;
  2397. default:
  2398. sample_rate = SAMPLING_RATE_48KHZ;
  2399. break;
  2400. }
  2401. return sample_rate;
  2402. }
  2403. static int cdc_dma_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2404. struct snd_ctl_elem_value *ucontrol)
  2405. {
  2406. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2407. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2408. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2409. return ch_num;
  2410. }
  2411. ucontrol->value.enumerated.item[0] =
  2412. cdc_dma_get_sample_rate_val(cdc_dma_rx_cfg[ch_num].sample_rate);
  2413. pr_debug("%s: cdc_dma_rx_sample_rate = %d\n", __func__,
  2414. cdc_dma_rx_cfg[ch_num].sample_rate);
  2415. return 0;
  2416. }
  2417. static int cdc_dma_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2418. struct snd_ctl_elem_value *ucontrol)
  2419. {
  2420. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2421. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2422. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2423. return ch_num;
  2424. }
  2425. cdc_dma_rx_cfg[ch_num].sample_rate =
  2426. cdc_dma_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2427. pr_debug("%s: control value = %d, cdc_dma_rx_sample_rate = %d\n",
  2428. __func__, ucontrol->value.enumerated.item[0],
  2429. cdc_dma_rx_cfg[ch_num].sample_rate);
  2430. return 0;
  2431. }
  2432. static int cdc_dma_tx_ch_get(struct snd_kcontrol *kcontrol,
  2433. struct snd_ctl_elem_value *ucontrol)
  2434. {
  2435. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2436. if (ch_num < 0) {
  2437. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2438. return ch_num;
  2439. }
  2440. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  2441. cdc_dma_tx_cfg[ch_num].channels);
  2442. ucontrol->value.integer.value[0] = cdc_dma_tx_cfg[ch_num].channels - 1;
  2443. return 0;
  2444. }
  2445. static int cdc_dma_tx_ch_put(struct snd_kcontrol *kcontrol,
  2446. struct snd_ctl_elem_value *ucontrol)
  2447. {
  2448. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2449. if (ch_num < 0) {
  2450. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2451. return ch_num;
  2452. }
  2453. cdc_dma_tx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  2454. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  2455. cdc_dma_tx_cfg[ch_num].channels);
  2456. return 1;
  2457. }
  2458. static int cdc_dma_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2459. struct snd_ctl_elem_value *ucontrol)
  2460. {
  2461. int sample_rate_val;
  2462. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2463. if (ch_num < 0) {
  2464. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2465. return ch_num;
  2466. }
  2467. switch (cdc_dma_tx_cfg[ch_num].sample_rate) {
  2468. case SAMPLING_RATE_384KHZ:
  2469. sample_rate_val = 12;
  2470. break;
  2471. case SAMPLING_RATE_352P8KHZ:
  2472. sample_rate_val = 11;
  2473. break;
  2474. case SAMPLING_RATE_192KHZ:
  2475. sample_rate_val = 10;
  2476. break;
  2477. case SAMPLING_RATE_176P4KHZ:
  2478. sample_rate_val = 9;
  2479. break;
  2480. case SAMPLING_RATE_96KHZ:
  2481. sample_rate_val = 8;
  2482. break;
  2483. case SAMPLING_RATE_88P2KHZ:
  2484. sample_rate_val = 7;
  2485. break;
  2486. case SAMPLING_RATE_48KHZ:
  2487. sample_rate_val = 6;
  2488. break;
  2489. case SAMPLING_RATE_44P1KHZ:
  2490. sample_rate_val = 5;
  2491. break;
  2492. case SAMPLING_RATE_32KHZ:
  2493. sample_rate_val = 4;
  2494. break;
  2495. case SAMPLING_RATE_22P05KHZ:
  2496. sample_rate_val = 3;
  2497. break;
  2498. case SAMPLING_RATE_16KHZ:
  2499. sample_rate_val = 2;
  2500. break;
  2501. case SAMPLING_RATE_11P025KHZ:
  2502. sample_rate_val = 1;
  2503. break;
  2504. case SAMPLING_RATE_8KHZ:
  2505. sample_rate_val = 0;
  2506. break;
  2507. default:
  2508. sample_rate_val = 6;
  2509. break;
  2510. }
  2511. ucontrol->value.integer.value[0] = sample_rate_val;
  2512. pr_debug("%s: cdc_dma_tx_sample_rate = %d\n", __func__,
  2513. cdc_dma_tx_cfg[ch_num].sample_rate);
  2514. return 0;
  2515. }
  2516. static int cdc_dma_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2517. struct snd_ctl_elem_value *ucontrol)
  2518. {
  2519. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2520. if (ch_num < 0) {
  2521. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2522. return ch_num;
  2523. }
  2524. switch (ucontrol->value.integer.value[0]) {
  2525. case 12:
  2526. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_384KHZ;
  2527. break;
  2528. case 11:
  2529. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_352P8KHZ;
  2530. break;
  2531. case 10:
  2532. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_192KHZ;
  2533. break;
  2534. case 9:
  2535. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_176P4KHZ;
  2536. break;
  2537. case 8:
  2538. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_96KHZ;
  2539. break;
  2540. case 7:
  2541. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_88P2KHZ;
  2542. break;
  2543. case 6:
  2544. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  2545. break;
  2546. case 5:
  2547. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_44P1KHZ;
  2548. break;
  2549. case 4:
  2550. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_32KHZ;
  2551. break;
  2552. case 3:
  2553. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_22P05KHZ;
  2554. break;
  2555. case 2:
  2556. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_16KHZ;
  2557. break;
  2558. case 1:
  2559. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_11P025KHZ;
  2560. break;
  2561. case 0:
  2562. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_8KHZ;
  2563. break;
  2564. default:
  2565. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  2566. break;
  2567. }
  2568. pr_debug("%s: control value = %ld, cdc_dma_tx_sample_rate = %d\n",
  2569. __func__, ucontrol->value.integer.value[0],
  2570. cdc_dma_tx_cfg[ch_num].sample_rate);
  2571. return 0;
  2572. }
  2573. static int cdc_dma_tx_format_get(struct snd_kcontrol *kcontrol,
  2574. struct snd_ctl_elem_value *ucontrol)
  2575. {
  2576. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2577. if (ch_num < 0) {
  2578. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2579. return ch_num;
  2580. }
  2581. switch (cdc_dma_tx_cfg[ch_num].bit_format) {
  2582. case SNDRV_PCM_FORMAT_S32_LE:
  2583. ucontrol->value.integer.value[0] = 3;
  2584. break;
  2585. case SNDRV_PCM_FORMAT_S24_3LE:
  2586. ucontrol->value.integer.value[0] = 2;
  2587. break;
  2588. case SNDRV_PCM_FORMAT_S24_LE:
  2589. ucontrol->value.integer.value[0] = 1;
  2590. break;
  2591. case SNDRV_PCM_FORMAT_S16_LE:
  2592. default:
  2593. ucontrol->value.integer.value[0] = 0;
  2594. break;
  2595. }
  2596. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  2597. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  2598. ucontrol->value.integer.value[0]);
  2599. return 0;
  2600. }
  2601. static int cdc_dma_tx_format_put(struct snd_kcontrol *kcontrol,
  2602. struct snd_ctl_elem_value *ucontrol)
  2603. {
  2604. int rc = 0;
  2605. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2606. if (ch_num < 0) {
  2607. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2608. return ch_num;
  2609. }
  2610. switch (ucontrol->value.integer.value[0]) {
  2611. case 3:
  2612. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  2613. break;
  2614. case 2:
  2615. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  2616. break;
  2617. case 1:
  2618. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  2619. break;
  2620. case 0:
  2621. default:
  2622. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  2623. break;
  2624. }
  2625. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  2626. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  2627. ucontrol->value.integer.value[0]);
  2628. return rc;
  2629. }
  2630. static int msm_cdc_dma_get_idx_from_beid(int32_t be_id)
  2631. {
  2632. int idx = 0;
  2633. switch (be_id) {
  2634. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_0:
  2635. idx = RX_CDC_DMA_RX_0;
  2636. break;
  2637. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_1:
  2638. idx = RX_CDC_DMA_RX_1;
  2639. break;
  2640. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_2:
  2641. idx = RX_CDC_DMA_RX_2;
  2642. break;
  2643. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_3:
  2644. idx = RX_CDC_DMA_RX_3;
  2645. break;
  2646. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_5:
  2647. idx = RX_CDC_DMA_RX_5;
  2648. break;
  2649. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_6:
  2650. idx = RX_CDC_DMA_RX_6;
  2651. break;
  2652. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_0:
  2653. idx = TX_CDC_DMA_TX_0;
  2654. break;
  2655. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_3:
  2656. idx = TX_CDC_DMA_TX_3;
  2657. break;
  2658. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_4:
  2659. idx = TX_CDC_DMA_TX_4;
  2660. break;
  2661. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  2662. idx = VA_CDC_DMA_TX_0;
  2663. break;
  2664. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  2665. idx = VA_CDC_DMA_TX_1;
  2666. break;
  2667. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  2668. idx = VA_CDC_DMA_TX_2;
  2669. break;
  2670. default:
  2671. idx = RX_CDC_DMA_RX_0;
  2672. break;
  2673. }
  2674. return idx;
  2675. }
  2676. static int msm_bt_sample_rate_get(struct snd_kcontrol *kcontrol,
  2677. struct snd_ctl_elem_value *ucontrol)
  2678. {
  2679. /*
  2680. * Slimbus_7_Rx/Tx sample rate values should always be in sync (same)
  2681. * when used for BT_SCO use case. Return either Rx or Tx sample rate
  2682. * value.
  2683. */
  2684. switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
  2685. case SAMPLING_RATE_96KHZ:
  2686. ucontrol->value.integer.value[0] = 5;
  2687. break;
  2688. case SAMPLING_RATE_88P2KHZ:
  2689. ucontrol->value.integer.value[0] = 4;
  2690. break;
  2691. case SAMPLING_RATE_48KHZ:
  2692. ucontrol->value.integer.value[0] = 3;
  2693. break;
  2694. case SAMPLING_RATE_44P1KHZ:
  2695. ucontrol->value.integer.value[0] = 2;
  2696. break;
  2697. case SAMPLING_RATE_16KHZ:
  2698. ucontrol->value.integer.value[0] = 1;
  2699. break;
  2700. case SAMPLING_RATE_8KHZ:
  2701. default:
  2702. ucontrol->value.integer.value[0] = 0;
  2703. break;
  2704. }
  2705. pr_debug("%s: sample rate = %d\n", __func__,
  2706. slim_rx_cfg[SLIM_RX_7].sample_rate);
  2707. return 0;
  2708. }
  2709. static int msm_bt_sample_rate_put(struct snd_kcontrol *kcontrol,
  2710. struct snd_ctl_elem_value *ucontrol)
  2711. {
  2712. switch (ucontrol->value.integer.value[0]) {
  2713. case 1:
  2714. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
  2715. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
  2716. break;
  2717. case 2:
  2718. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  2719. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  2720. break;
  2721. case 3:
  2722. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
  2723. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
  2724. break;
  2725. case 4:
  2726. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  2727. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  2728. break;
  2729. case 5:
  2730. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
  2731. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
  2732. break;
  2733. case 0:
  2734. default:
  2735. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
  2736. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
  2737. break;
  2738. }
  2739. pr_debug("%s: sample rates: slim7_rx = %d, slim7_tx = %d, value = %d\n",
  2740. __func__,
  2741. slim_rx_cfg[SLIM_RX_7].sample_rate,
  2742. slim_tx_cfg[SLIM_TX_7].sample_rate,
  2743. ucontrol->value.enumerated.item[0]);
  2744. return 0;
  2745. }
  2746. static int msm_bt_sample_rate_rx_get(struct snd_kcontrol *kcontrol,
  2747. struct snd_ctl_elem_value *ucontrol)
  2748. {
  2749. switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
  2750. case SAMPLING_RATE_96KHZ:
  2751. ucontrol->value.integer.value[0] = 5;
  2752. break;
  2753. case SAMPLING_RATE_88P2KHZ:
  2754. ucontrol->value.integer.value[0] = 4;
  2755. break;
  2756. case SAMPLING_RATE_48KHZ:
  2757. ucontrol->value.integer.value[0] = 3;
  2758. break;
  2759. case SAMPLING_RATE_44P1KHZ:
  2760. ucontrol->value.integer.value[0] = 2;
  2761. break;
  2762. case SAMPLING_RATE_16KHZ:
  2763. ucontrol->value.integer.value[0] = 1;
  2764. break;
  2765. case SAMPLING_RATE_8KHZ:
  2766. default:
  2767. ucontrol->value.integer.value[0] = 0;
  2768. break;
  2769. }
  2770. pr_debug("%s: sample rate rx = %d\n", __func__,
  2771. slim_rx_cfg[SLIM_RX_7].sample_rate);
  2772. return 0;
  2773. }
  2774. static int msm_bt_sample_rate_rx_put(struct snd_kcontrol *kcontrol,
  2775. struct snd_ctl_elem_value *ucontrol)
  2776. {
  2777. switch (ucontrol->value.integer.value[0]) {
  2778. case 1:
  2779. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
  2780. break;
  2781. case 2:
  2782. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  2783. break;
  2784. case 3:
  2785. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
  2786. break;
  2787. case 4:
  2788. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  2789. break;
  2790. case 5:
  2791. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
  2792. break;
  2793. case 0:
  2794. default:
  2795. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
  2796. break;
  2797. }
  2798. pr_debug("%s: sample rate: slim7_rx = %d, value = %d\n",
  2799. __func__,
  2800. slim_rx_cfg[SLIM_RX_7].sample_rate,
  2801. ucontrol->value.enumerated.item[0]);
  2802. return 0;
  2803. }
  2804. static int msm_bt_sample_rate_tx_get(struct snd_kcontrol *kcontrol,
  2805. struct snd_ctl_elem_value *ucontrol)
  2806. {
  2807. switch (slim_tx_cfg[SLIM_TX_7].sample_rate) {
  2808. case SAMPLING_RATE_96KHZ:
  2809. ucontrol->value.integer.value[0] = 5;
  2810. break;
  2811. case SAMPLING_RATE_88P2KHZ:
  2812. ucontrol->value.integer.value[0] = 4;
  2813. break;
  2814. case SAMPLING_RATE_48KHZ:
  2815. ucontrol->value.integer.value[0] = 3;
  2816. break;
  2817. case SAMPLING_RATE_44P1KHZ:
  2818. ucontrol->value.integer.value[0] = 2;
  2819. break;
  2820. case SAMPLING_RATE_16KHZ:
  2821. ucontrol->value.integer.value[0] = 1;
  2822. break;
  2823. case SAMPLING_RATE_8KHZ:
  2824. default:
  2825. ucontrol->value.integer.value[0] = 0;
  2826. break;
  2827. }
  2828. pr_debug("%s: sample rate tx = %d\n", __func__,
  2829. slim_tx_cfg[SLIM_TX_7].sample_rate);
  2830. return 0;
  2831. }
  2832. static int msm_bt_sample_rate_tx_put(struct snd_kcontrol *kcontrol,
  2833. struct snd_ctl_elem_value *ucontrol)
  2834. {
  2835. switch (ucontrol->value.integer.value[0]) {
  2836. case 1:
  2837. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
  2838. break;
  2839. case 2:
  2840. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  2841. break;
  2842. case 3:
  2843. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
  2844. break;
  2845. case 4:
  2846. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  2847. break;
  2848. case 5:
  2849. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
  2850. break;
  2851. case 0:
  2852. default:
  2853. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
  2854. break;
  2855. }
  2856. pr_debug("%s: sample rate: slim7_tx = %d, value = %d\n",
  2857. __func__,
  2858. slim_tx_cfg[SLIM_TX_7].sample_rate,
  2859. ucontrol->value.enumerated.item[0]);
  2860. return 0;
  2861. }
  2862. static const struct snd_kcontrol_new msm_int_wcd937x_snd_controls[] = {
  2863. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 Format", rx_cdc_dma_rx_0_format,
  2864. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2865. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 Format", rx_cdc_dma_rx_1_format,
  2866. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2867. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 Format", rx_cdc_dma_rx_2_format,
  2868. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2869. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 Format", rx_cdc_dma_rx_3_format,
  2870. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2871. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 Format", rx_cdc_dma_rx_5_format,
  2872. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2873. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 SampleRate",
  2874. rx_cdc_dma_rx_0_sample_rate,
  2875. cdc_dma_rx_sample_rate_get,
  2876. cdc_dma_rx_sample_rate_put),
  2877. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 SampleRate",
  2878. rx_cdc_dma_rx_1_sample_rate,
  2879. cdc_dma_rx_sample_rate_get,
  2880. cdc_dma_rx_sample_rate_put),
  2881. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 SampleRate",
  2882. rx_cdc_dma_rx_2_sample_rate,
  2883. cdc_dma_rx_sample_rate_get,
  2884. cdc_dma_rx_sample_rate_put),
  2885. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 SampleRate",
  2886. rx_cdc_dma_rx_3_sample_rate,
  2887. cdc_dma_rx_sample_rate_get,
  2888. cdc_dma_rx_sample_rate_put),
  2889. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 SampleRate",
  2890. rx_cdc_dma_rx_5_sample_rate,
  2891. cdc_dma_rx_sample_rate_get,
  2892. cdc_dma_rx_sample_rate_put),
  2893. };
  2894. static const struct snd_kcontrol_new msm_int_snd_controls[] = {
  2895. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 Channels", rx_cdc_dma_rx_0_chs,
  2896. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2897. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 Channels", rx_cdc_dma_rx_1_chs,
  2898. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2899. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 Channels", rx_cdc_dma_rx_2_chs,
  2900. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2901. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 Channels", rx_cdc_dma_rx_3_chs,
  2902. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2903. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 Channels", rx_cdc_dma_rx_5_chs,
  2904. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2905. SOC_ENUM_EXT("RX_CDC_DMA_RX_6 Channels", rx_cdc_dma_rx_6_chs,
  2906. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2907. SOC_ENUM_EXT("TX_CDC_DMA_TX_0 Channels", tx_cdc_dma_tx_0_chs,
  2908. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2909. SOC_ENUM_EXT("TX_CDC_DMA_TX_3 Channels", tx_cdc_dma_tx_3_chs,
  2910. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2911. SOC_ENUM_EXT("TX_CDC_DMA_TX_4 Channels", tx_cdc_dma_tx_4_chs,
  2912. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2913. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Channels", va_cdc_dma_tx_0_chs,
  2914. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2915. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Channels", va_cdc_dma_tx_1_chs,
  2916. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2917. SOC_ENUM_EXT("VA_CDC_DMA_TX_2 Channels", va_cdc_dma_tx_2_chs,
  2918. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2919. SOC_ENUM_EXT("TX_CDC_DMA_TX_0 Format", tx_cdc_dma_tx_0_format,
  2920. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2921. SOC_ENUM_EXT("TX_CDC_DMA_TX_3 Format", tx_cdc_dma_tx_3_format,
  2922. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2923. SOC_ENUM_EXT("TX_CDC_DMA_TX_4 Format", tx_cdc_dma_tx_4_format,
  2924. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2925. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Format", va_cdc_dma_tx_0_format,
  2926. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2927. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Format", va_cdc_dma_tx_1_format,
  2928. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2929. SOC_ENUM_EXT("VA_CDC_DMA_TX_2 Format", va_cdc_dma_tx_2_format,
  2930. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2931. SOC_ENUM_EXT("TX_CDC_DMA_TX_0 SampleRate",
  2932. tx_cdc_dma_tx_0_sample_rate,
  2933. cdc_dma_tx_sample_rate_get,
  2934. cdc_dma_tx_sample_rate_put),
  2935. SOC_ENUM_EXT("TX_CDC_DMA_TX_3 SampleRate",
  2936. tx_cdc_dma_tx_3_sample_rate,
  2937. cdc_dma_tx_sample_rate_get,
  2938. cdc_dma_tx_sample_rate_put),
  2939. SOC_ENUM_EXT("TX_CDC_DMA_TX_4 SampleRate",
  2940. tx_cdc_dma_tx_4_sample_rate,
  2941. cdc_dma_tx_sample_rate_get,
  2942. cdc_dma_tx_sample_rate_put),
  2943. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 SampleRate",
  2944. va_cdc_dma_tx_0_sample_rate,
  2945. cdc_dma_tx_sample_rate_get,
  2946. cdc_dma_tx_sample_rate_put),
  2947. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 SampleRate",
  2948. va_cdc_dma_tx_1_sample_rate,
  2949. cdc_dma_tx_sample_rate_get,
  2950. cdc_dma_tx_sample_rate_put),
  2951. SOC_ENUM_EXT("VA_CDC_DMA_TX_2 SampleRate",
  2952. va_cdc_dma_tx_2_sample_rate,
  2953. cdc_dma_tx_sample_rate_get,
  2954. cdc_dma_tx_sample_rate_put),
  2955. };
  2956. static const struct snd_kcontrol_new msm_int_wcd9380_snd_controls[] = {
  2957. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 Format", rx_cdc80_dma_rx_0_format,
  2958. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2959. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 Format", rx_cdc80_dma_rx_1_format,
  2960. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2961. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 Format", rx_cdc80_dma_rx_2_format,
  2962. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2963. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 Format", rx_cdc80_dma_rx_3_format,
  2964. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2965. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 Format", rx_cdc80_dma_rx_5_format,
  2966. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2967. SOC_ENUM_EXT("RX_CDC_DMA_RX_6 Format", rx_cdc80_dma_rx_6_format,
  2968. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2969. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 SampleRate",
  2970. rx_cdc80_dma_rx_0_sample_rate,
  2971. cdc_dma_rx_sample_rate_get,
  2972. cdc_dma_rx_sample_rate_put),
  2973. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 SampleRate",
  2974. rx_cdc80_dma_rx_1_sample_rate,
  2975. cdc_dma_rx_sample_rate_get,
  2976. cdc_dma_rx_sample_rate_put),
  2977. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 SampleRate",
  2978. rx_cdc80_dma_rx_2_sample_rate,
  2979. cdc_dma_rx_sample_rate_get,
  2980. cdc_dma_rx_sample_rate_put),
  2981. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 SampleRate",
  2982. rx_cdc80_dma_rx_3_sample_rate,
  2983. cdc_dma_rx_sample_rate_get,
  2984. cdc_dma_rx_sample_rate_put),
  2985. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 SampleRate",
  2986. rx_cdc80_dma_rx_5_sample_rate,
  2987. cdc_dma_rx_sample_rate_get,
  2988. cdc_dma_rx_sample_rate_put),
  2989. SOC_ENUM_EXT("RX_CDC_DMA_RX_6 SampleRate",
  2990. rx_cdc80_dma_rx_6_sample_rate,
  2991. cdc_dma_rx_sample_rate_get,
  2992. cdc_dma_rx_sample_rate_put),
  2993. };
  2994. static const struct snd_kcontrol_new msm_int_wcd9385_snd_controls[] = {
  2995. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 Format", rx_cdc85_dma_rx_0_format,
  2996. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2997. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 Format", rx_cdc85_dma_rx_1_format,
  2998. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2999. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 Format", rx_cdc85_dma_rx_2_format,
  3000. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3001. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 Format", rx_cdc85_dma_rx_3_format,
  3002. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3003. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 Format", rx_cdc85_dma_rx_5_format,
  3004. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3005. SOC_ENUM_EXT("RX_CDC_DMA_RX_6 Format", rx_cdc85_dma_rx_6_format,
  3006. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3007. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 SampleRate",
  3008. rx_cdc85_dma_rx_0_sample_rate,
  3009. cdc_dma_rx_sample_rate_get,
  3010. cdc_dma_rx_sample_rate_put),
  3011. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 SampleRate",
  3012. rx_cdc85_dma_rx_1_sample_rate,
  3013. cdc_dma_rx_sample_rate_get,
  3014. cdc_dma_rx_sample_rate_put),
  3015. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 SampleRate",
  3016. rx_cdc85_dma_rx_2_sample_rate,
  3017. cdc_dma_rx_sample_rate_get,
  3018. cdc_dma_rx_sample_rate_put),
  3019. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 SampleRate",
  3020. rx_cdc85_dma_rx_3_sample_rate,
  3021. cdc_dma_rx_sample_rate_get,
  3022. cdc_dma_rx_sample_rate_put),
  3023. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 SampleRate",
  3024. rx_cdc85_dma_rx_5_sample_rate,
  3025. cdc_dma_rx_sample_rate_get,
  3026. cdc_dma_rx_sample_rate_put),
  3027. SOC_ENUM_EXT("RX_CDC_DMA_RX_6 SampleRate",
  3028. rx_cdc85_dma_rx_6_sample_rate,
  3029. cdc_dma_rx_sample_rate_get,
  3030. cdc_dma_rx_sample_rate_put),
  3031. };
  3032. static const struct snd_kcontrol_new msm_common_snd_controls[] = {
  3033. SOC_ENUM_EXT("USB_AUDIO_RX SampleRate", usb_rx_sample_rate,
  3034. usb_audio_rx_sample_rate_get,
  3035. usb_audio_rx_sample_rate_put),
  3036. SOC_ENUM_EXT("USB_AUDIO_TX SampleRate", usb_tx_sample_rate,
  3037. usb_audio_tx_sample_rate_get,
  3038. usb_audio_tx_sample_rate_put),
  3039. SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3040. tdm_rx_sample_rate_get,
  3041. tdm_rx_sample_rate_put),
  3042. SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3043. tdm_rx_sample_rate_get,
  3044. tdm_rx_sample_rate_put),
  3045. SOC_ENUM_EXT("TERT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3046. tdm_rx_sample_rate_get,
  3047. tdm_rx_sample_rate_put),
  3048. SOC_ENUM_EXT("QUAT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3049. tdm_rx_sample_rate_get,
  3050. tdm_rx_sample_rate_put),
  3051. SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3052. tdm_tx_sample_rate_get,
  3053. tdm_tx_sample_rate_put),
  3054. SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3055. tdm_tx_sample_rate_get,
  3056. tdm_tx_sample_rate_put),
  3057. SOC_ENUM_EXT("TERT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3058. tdm_tx_sample_rate_get,
  3059. tdm_tx_sample_rate_put),
  3060. SOC_ENUM_EXT("QUAT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3061. tdm_tx_sample_rate_get,
  3062. tdm_tx_sample_rate_put),
  3063. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  3064. aux_pcm_rx_sample_rate_get,
  3065. aux_pcm_rx_sample_rate_put),
  3066. SOC_ENUM_EXT("SEC_AUX_PCM_RX SampleRate", sec_aux_pcm_rx_sample_rate,
  3067. aux_pcm_rx_sample_rate_get,
  3068. aux_pcm_rx_sample_rate_put),
  3069. SOC_ENUM_EXT("TERT_AUX_PCM_RX SampleRate", tert_aux_pcm_rx_sample_rate,
  3070. aux_pcm_rx_sample_rate_get,
  3071. aux_pcm_rx_sample_rate_put),
  3072. SOC_ENUM_EXT("QUAT_AUX_PCM_RX SampleRate", quat_aux_pcm_rx_sample_rate,
  3073. aux_pcm_rx_sample_rate_get,
  3074. aux_pcm_rx_sample_rate_put),
  3075. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  3076. aux_pcm_tx_sample_rate_get,
  3077. aux_pcm_tx_sample_rate_put),
  3078. SOC_ENUM_EXT("SEC_AUX_PCM_TX SampleRate", sec_aux_pcm_tx_sample_rate,
  3079. aux_pcm_tx_sample_rate_get,
  3080. aux_pcm_tx_sample_rate_put),
  3081. SOC_ENUM_EXT("TERT_AUX_PCM_TX SampleRate", tert_aux_pcm_tx_sample_rate,
  3082. aux_pcm_tx_sample_rate_get,
  3083. aux_pcm_tx_sample_rate_put),
  3084. SOC_ENUM_EXT("QUAT_AUX_PCM_TX SampleRate", quat_aux_pcm_tx_sample_rate,
  3085. aux_pcm_tx_sample_rate_get,
  3086. aux_pcm_tx_sample_rate_put),
  3087. SOC_ENUM_EXT("PRIM_MI2S_RX SampleRate", prim_mi2s_rx_sample_rate,
  3088. mi2s_rx_sample_rate_get,
  3089. mi2s_rx_sample_rate_put),
  3090. SOC_ENUM_EXT("SEC_MI2S_RX SampleRate", sec_mi2s_rx_sample_rate,
  3091. mi2s_rx_sample_rate_get,
  3092. mi2s_rx_sample_rate_put),
  3093. SOC_ENUM_EXT("TERT_MI2S_RX SampleRate", tert_mi2s_rx_sample_rate,
  3094. mi2s_rx_sample_rate_get,
  3095. mi2s_rx_sample_rate_put),
  3096. SOC_ENUM_EXT("QUAT_MI2S_RX SampleRate", quat_mi2s_rx_sample_rate,
  3097. mi2s_rx_sample_rate_get,
  3098. mi2s_rx_sample_rate_put),
  3099. SOC_ENUM_EXT("PRIM_MI2S_TX SampleRate", prim_mi2s_tx_sample_rate,
  3100. mi2s_tx_sample_rate_get,
  3101. mi2s_tx_sample_rate_put),
  3102. SOC_ENUM_EXT("SEC_MI2S_TX SampleRate", sec_mi2s_tx_sample_rate,
  3103. mi2s_tx_sample_rate_get,
  3104. mi2s_tx_sample_rate_put),
  3105. SOC_ENUM_EXT("TERT_MI2S_TX SampleRate", tert_mi2s_tx_sample_rate,
  3106. mi2s_tx_sample_rate_get,
  3107. mi2s_tx_sample_rate_put),
  3108. SOC_ENUM_EXT("QUAT_MI2S_TX SampleRate", quat_mi2s_tx_sample_rate,
  3109. mi2s_tx_sample_rate_get,
  3110. mi2s_tx_sample_rate_put),
  3111. SOC_ENUM_EXT("USB_AUDIO_RX Format", usb_rx_format,
  3112. usb_audio_rx_format_get, usb_audio_rx_format_put),
  3113. SOC_ENUM_EXT("USB_AUDIO_TX Format", usb_tx_format,
  3114. usb_audio_tx_format_get, usb_audio_tx_format_put),
  3115. SOC_ENUM_EXT("PRI_TDM_RX_0 Format", tdm_rx_format,
  3116. tdm_rx_format_get,
  3117. tdm_rx_format_put),
  3118. SOC_ENUM_EXT("SEC_TDM_RX_0 Format", tdm_rx_format,
  3119. tdm_rx_format_get,
  3120. tdm_rx_format_put),
  3121. SOC_ENUM_EXT("TERT_TDM_RX_0 Format", tdm_rx_format,
  3122. tdm_rx_format_get,
  3123. tdm_rx_format_put),
  3124. SOC_ENUM_EXT("QUAT_TDM_RX_0 Format", tdm_rx_format,
  3125. tdm_rx_format_get,
  3126. tdm_rx_format_put),
  3127. SOC_ENUM_EXT("PRI_TDM_TX_0 Format", tdm_tx_format,
  3128. tdm_tx_format_get,
  3129. tdm_tx_format_put),
  3130. SOC_ENUM_EXT("SEC_TDM_TX_0 Format", tdm_tx_format,
  3131. tdm_tx_format_get,
  3132. tdm_tx_format_put),
  3133. SOC_ENUM_EXT("TERT_TDM_TX_0 Format", tdm_tx_format,
  3134. tdm_tx_format_get,
  3135. tdm_tx_format_put),
  3136. SOC_ENUM_EXT("QUAT_TDM_TX_0 Format", tdm_tx_format,
  3137. tdm_tx_format_get,
  3138. tdm_tx_format_put),
  3139. SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
  3140. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3141. SOC_ENUM_EXT("SEC_AUX_PCM_RX Format", aux_pcm_rx_format,
  3142. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3143. SOC_ENUM_EXT("TERT_AUX_PCM_RX Format", aux_pcm_rx_format,
  3144. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3145. SOC_ENUM_EXT("QUAT_AUX_PCM_RX Format", aux_pcm_rx_format,
  3146. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3147. SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
  3148. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3149. SOC_ENUM_EXT("SEC_AUX_PCM_TX Format", aux_pcm_tx_format,
  3150. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3151. SOC_ENUM_EXT("TERT_AUX_PCM_TX Format", aux_pcm_tx_format,
  3152. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3153. SOC_ENUM_EXT("QUAT_AUX_PCM_TX Format", aux_pcm_tx_format,
  3154. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3155. SOC_ENUM_EXT("PRIM_MI2S_RX Format", mi2s_rx_format,
  3156. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3157. SOC_ENUM_EXT("SEC_MI2S_RX Format", mi2s_rx_format,
  3158. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3159. SOC_ENUM_EXT("TERT_MI2S_RX Format", mi2s_rx_format,
  3160. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3161. SOC_ENUM_EXT("QUAT_MI2S_RX Format", mi2s_rx_format,
  3162. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3163. SOC_ENUM_EXT("PRIM_MI2S_TX Format", mi2s_tx_format,
  3164. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3165. SOC_ENUM_EXT("SEC_MI2S_TX Format", mi2s_tx_format,
  3166. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3167. SOC_ENUM_EXT("TERT_MI2S_TX Format", mi2s_tx_format,
  3168. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3169. SOC_ENUM_EXT("QUAT_MI2S_TX Format", mi2s_tx_format,
  3170. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3171. SOC_ENUM_EXT("USB_AUDIO_RX Channels", usb_rx_chs,
  3172. usb_audio_rx_ch_get, usb_audio_rx_ch_put),
  3173. SOC_ENUM_EXT("USB_AUDIO_TX Channels", usb_tx_chs,
  3174. usb_audio_tx_ch_get, usb_audio_tx_ch_put),
  3175. SOC_ENUM_EXT("PROXY_RX Channels", proxy_rx_chs,
  3176. proxy_rx_ch_get, proxy_rx_ch_put),
  3177. SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", tdm_rx_chs,
  3178. tdm_rx_ch_get,
  3179. tdm_rx_ch_put),
  3180. SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", tdm_rx_chs,
  3181. tdm_rx_ch_get,
  3182. tdm_rx_ch_put),
  3183. SOC_ENUM_EXT("TERT_TDM_RX_0 Channels", tdm_rx_chs,
  3184. tdm_rx_ch_get,
  3185. tdm_rx_ch_put),
  3186. SOC_ENUM_EXT("QUAT_TDM_RX_0 Channels", tdm_rx_chs,
  3187. tdm_rx_ch_get,
  3188. tdm_rx_ch_put),
  3189. SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", tdm_tx_chs,
  3190. tdm_tx_ch_get,
  3191. tdm_tx_ch_put),
  3192. SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", tdm_tx_chs,
  3193. tdm_tx_ch_get,
  3194. tdm_tx_ch_put),
  3195. SOC_ENUM_EXT("TERT_TDM_TX_0 Channels", tdm_tx_chs,
  3196. tdm_tx_ch_get,
  3197. tdm_tx_ch_put),
  3198. SOC_ENUM_EXT("QUAT_TDM_TX_0 Channels", tdm_tx_chs,
  3199. tdm_tx_ch_get,
  3200. tdm_tx_ch_put),
  3201. SOC_ENUM_EXT("PRIM_MI2S_RX Channels", prim_mi2s_rx_chs,
  3202. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3203. SOC_ENUM_EXT("SEC_MI2S_RX Channels", sec_mi2s_rx_chs,
  3204. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3205. SOC_ENUM_EXT("TERT_MI2S_RX Channels", tert_mi2s_rx_chs,
  3206. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3207. SOC_ENUM_EXT("QUAT_MI2S_RX Channels", quat_mi2s_rx_chs,
  3208. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3209. SOC_ENUM_EXT("PRIM_MI2S_TX Channels", prim_mi2s_tx_chs,
  3210. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3211. SOC_ENUM_EXT("SEC_MI2S_TX Channels", sec_mi2s_tx_chs,
  3212. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3213. SOC_ENUM_EXT("TERT_MI2S_TX Channels", tert_mi2s_tx_chs,
  3214. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3215. SOC_ENUM_EXT("QUAT_MI2S_TX Channels", quat_mi2s_tx_chs,
  3216. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3217. SOC_ENUM_EXT("BT SampleRate", bt_sample_rate,
  3218. msm_bt_sample_rate_get,
  3219. msm_bt_sample_rate_put),
  3220. SOC_ENUM_EXT("BT SampleRate RX", bt_sample_rate_rx,
  3221. msm_bt_sample_rate_rx_get,
  3222. msm_bt_sample_rate_rx_put),
  3223. SOC_ENUM_EXT("BT SampleRate TX", bt_sample_rate_tx,
  3224. msm_bt_sample_rate_tx_get,
  3225. msm_bt_sample_rate_tx_put),
  3226. SOC_ENUM_EXT("AFE_LOOPBACK_TX Channels", afe_loopback_tx_chs,
  3227. afe_loopback_tx_ch_get, afe_loopback_tx_ch_put),
  3228. SOC_ENUM_EXT("VI_FEED_TX Channels", vi_feed_tx_chs,
  3229. msm_vi_feed_tx_ch_get, msm_vi_feed_tx_ch_put),
  3230. SOC_SINGLE_MULTI_EXT("TDM Slot Map", SND_SOC_NOPM, 0, 255, 0,
  3231. TDM_MAX_SLOTS + MAX_PATH, NULL, tdm_slot_map_put),
  3232. };
  3233. static const struct snd_kcontrol_new msm_snd_controls[] = {
  3234. SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
  3235. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3236. SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
  3237. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3238. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  3239. aux_pcm_rx_sample_rate_get,
  3240. aux_pcm_rx_sample_rate_put),
  3241. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  3242. aux_pcm_tx_sample_rate_get,
  3243. aux_pcm_tx_sample_rate_put),
  3244. };
  3245. static int holi_send_island_va_config(int32_t be_id)
  3246. {
  3247. int rc = 0;
  3248. int port_id = 0xFFFF;
  3249. port_id = msm_get_port_id(be_id);
  3250. if (port_id < 0) {
  3251. pr_err("%s: Invalid island interface, be_id: %d\n",
  3252. __func__, be_id);
  3253. rc = -EINVAL;
  3254. } else {
  3255. /*
  3256. * send island mode config
  3257. * This should be the first configuration
  3258. */
  3259. rc = afe_send_port_island_mode(port_id);
  3260. if (rc)
  3261. pr_err("%s: afe send island mode failed %d\n",
  3262. __func__, rc);
  3263. }
  3264. return rc;
  3265. }
  3266. static int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  3267. struct snd_pcm_hw_params *params)
  3268. {
  3269. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3270. struct snd_interval *rate = hw_param_interval(params,
  3271. SNDRV_PCM_HW_PARAM_RATE);
  3272. struct snd_interval *channels = hw_param_interval(params,
  3273. SNDRV_PCM_HW_PARAM_CHANNELS);
  3274. int idx = 0, rc = 0;
  3275. pr_debug("%s: dai_id= %d, format = %d, rate = %d\n",
  3276. __func__, dai_link->id, params_format(params),
  3277. params_rate(params));
  3278. switch (dai_link->id) {
  3279. case MSM_BACKEND_DAI_USB_RX:
  3280. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3281. usb_rx_cfg.bit_format);
  3282. rate->min = rate->max = usb_rx_cfg.sample_rate;
  3283. channels->min = channels->max = usb_rx_cfg.channels;
  3284. break;
  3285. case MSM_BACKEND_DAI_USB_TX:
  3286. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3287. usb_tx_cfg.bit_format);
  3288. rate->min = rate->max = usb_tx_cfg.sample_rate;
  3289. channels->min = channels->max = usb_tx_cfg.channels;
  3290. break;
  3291. case MSM_BACKEND_DAI_AFE_PCM_RX:
  3292. channels->min = channels->max = proxy_rx_cfg.channels;
  3293. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3294. break;
  3295. case MSM_BACKEND_DAI_PRI_TDM_RX_0:
  3296. channels->min = channels->max =
  3297. tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  3298. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3299. tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
  3300. rate->min = rate->max = tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
  3301. break;
  3302. case MSM_BACKEND_DAI_PRI_TDM_TX_0:
  3303. channels->min = channels->max =
  3304. tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  3305. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3306. tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
  3307. rate->min = rate->max = tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
  3308. break;
  3309. case MSM_BACKEND_DAI_SEC_TDM_RX_0:
  3310. channels->min = channels->max =
  3311. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  3312. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3313. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  3314. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  3315. break;
  3316. case MSM_BACKEND_DAI_SEC_TDM_TX_0:
  3317. channels->min = channels->max =
  3318. tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  3319. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3320. tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
  3321. rate->min = rate->max = tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
  3322. break;
  3323. case MSM_BACKEND_DAI_TERT_TDM_RX_0:
  3324. channels->min = channels->max =
  3325. tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  3326. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3327. tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
  3328. rate->min = rate->max = tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
  3329. break;
  3330. case MSM_BACKEND_DAI_TERT_TDM_TX_0:
  3331. channels->min = channels->max =
  3332. tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  3333. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3334. tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
  3335. rate->min = rate->max = tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
  3336. break;
  3337. case MSM_BACKEND_DAI_QUAT_TDM_RX_0:
  3338. channels->min = channels->max =
  3339. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  3340. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3341. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  3342. rate->min = rate->max = tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3343. break;
  3344. case MSM_BACKEND_DAI_QUAT_TDM_TX_0:
  3345. channels->min = channels->max =
  3346. tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  3347. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3348. tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
  3349. rate->min = rate->max = tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3350. break;
  3351. case MSM_BACKEND_DAI_AUXPCM_RX:
  3352. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3353. aux_pcm_rx_cfg[PRIM_AUX_PCM].bit_format);
  3354. rate->min = rate->max =
  3355. aux_pcm_rx_cfg[PRIM_AUX_PCM].sample_rate;
  3356. channels->min = channels->max =
  3357. aux_pcm_rx_cfg[PRIM_AUX_PCM].channels;
  3358. break;
  3359. case MSM_BACKEND_DAI_AUXPCM_TX:
  3360. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3361. aux_pcm_tx_cfg[PRIM_AUX_PCM].bit_format);
  3362. rate->min = rate->max =
  3363. aux_pcm_tx_cfg[PRIM_AUX_PCM].sample_rate;
  3364. channels->min = channels->max =
  3365. aux_pcm_tx_cfg[PRIM_AUX_PCM].channels;
  3366. break;
  3367. case MSM_BACKEND_DAI_SEC_AUXPCM_RX:
  3368. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3369. aux_pcm_rx_cfg[SEC_AUX_PCM].bit_format);
  3370. rate->min = rate->max =
  3371. aux_pcm_rx_cfg[SEC_AUX_PCM].sample_rate;
  3372. channels->min = channels->max =
  3373. aux_pcm_rx_cfg[SEC_AUX_PCM].channels;
  3374. break;
  3375. case MSM_BACKEND_DAI_SEC_AUXPCM_TX:
  3376. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3377. aux_pcm_tx_cfg[SEC_AUX_PCM].bit_format);
  3378. rate->min = rate->max =
  3379. aux_pcm_tx_cfg[SEC_AUX_PCM].sample_rate;
  3380. channels->min = channels->max =
  3381. aux_pcm_tx_cfg[SEC_AUX_PCM].channels;
  3382. break;
  3383. case MSM_BACKEND_DAI_TERT_AUXPCM_RX:
  3384. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3385. aux_pcm_rx_cfg[TERT_AUX_PCM].bit_format);
  3386. rate->min = rate->max =
  3387. aux_pcm_rx_cfg[TERT_AUX_PCM].sample_rate;
  3388. channels->min = channels->max =
  3389. aux_pcm_rx_cfg[TERT_AUX_PCM].channels;
  3390. break;
  3391. case MSM_BACKEND_DAI_TERT_AUXPCM_TX:
  3392. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3393. aux_pcm_tx_cfg[TERT_AUX_PCM].bit_format);
  3394. rate->min = rate->max =
  3395. aux_pcm_tx_cfg[TERT_AUX_PCM].sample_rate;
  3396. channels->min = channels->max =
  3397. aux_pcm_tx_cfg[TERT_AUX_PCM].channels;
  3398. break;
  3399. case MSM_BACKEND_DAI_QUAT_AUXPCM_RX:
  3400. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3401. aux_pcm_rx_cfg[QUAT_AUX_PCM].bit_format);
  3402. rate->min = rate->max =
  3403. aux_pcm_rx_cfg[QUAT_AUX_PCM].sample_rate;
  3404. channels->min = channels->max =
  3405. aux_pcm_rx_cfg[QUAT_AUX_PCM].channels;
  3406. break;
  3407. case MSM_BACKEND_DAI_QUAT_AUXPCM_TX:
  3408. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3409. aux_pcm_tx_cfg[QUAT_AUX_PCM].bit_format);
  3410. rate->min = rate->max =
  3411. aux_pcm_tx_cfg[QUAT_AUX_PCM].sample_rate;
  3412. channels->min = channels->max =
  3413. aux_pcm_tx_cfg[QUAT_AUX_PCM].channels;
  3414. break;
  3415. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  3416. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3417. mi2s_rx_cfg[PRIM_MI2S].bit_format);
  3418. rate->min = rate->max = mi2s_rx_cfg[PRIM_MI2S].sample_rate;
  3419. channels->min = channels->max =
  3420. mi2s_rx_cfg[PRIM_MI2S].channels;
  3421. break;
  3422. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  3423. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3424. mi2s_tx_cfg[PRIM_MI2S].bit_format);
  3425. rate->min = rate->max = mi2s_tx_cfg[PRIM_MI2S].sample_rate;
  3426. channels->min = channels->max =
  3427. mi2s_tx_cfg[PRIM_MI2S].channels;
  3428. break;
  3429. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  3430. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3431. mi2s_rx_cfg[SEC_MI2S].bit_format);
  3432. rate->min = rate->max = mi2s_rx_cfg[SEC_MI2S].sample_rate;
  3433. channels->min = channels->max =
  3434. mi2s_rx_cfg[SEC_MI2S].channels;
  3435. break;
  3436. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  3437. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3438. mi2s_tx_cfg[SEC_MI2S].bit_format);
  3439. rate->min = rate->max = mi2s_tx_cfg[SEC_MI2S].sample_rate;
  3440. channels->min = channels->max =
  3441. mi2s_tx_cfg[SEC_MI2S].channels;
  3442. break;
  3443. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  3444. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3445. mi2s_rx_cfg[TERT_MI2S].bit_format);
  3446. rate->min = rate->max = mi2s_rx_cfg[TERT_MI2S].sample_rate;
  3447. channels->min = channels->max =
  3448. mi2s_rx_cfg[TERT_MI2S].channels;
  3449. break;
  3450. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  3451. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3452. mi2s_tx_cfg[TERT_MI2S].bit_format);
  3453. rate->min = rate->max = mi2s_tx_cfg[TERT_MI2S].sample_rate;
  3454. channels->min = channels->max =
  3455. mi2s_tx_cfg[TERT_MI2S].channels;
  3456. break;
  3457. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  3458. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3459. mi2s_rx_cfg[QUAT_MI2S].bit_format);
  3460. rate->min = rate->max = mi2s_rx_cfg[QUAT_MI2S].sample_rate;
  3461. channels->min = channels->max =
  3462. mi2s_rx_cfg[QUAT_MI2S].channels;
  3463. break;
  3464. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  3465. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3466. mi2s_tx_cfg[QUAT_MI2S].bit_format);
  3467. rate->min = rate->max = mi2s_tx_cfg[QUAT_MI2S].sample_rate;
  3468. channels->min = channels->max =
  3469. mi2s_tx_cfg[QUAT_MI2S].channels;
  3470. break;
  3471. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_0:
  3472. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_1:
  3473. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_2:
  3474. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_3:
  3475. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_6:
  3476. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3477. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3478. cdc_dma_rx_cfg[idx].bit_format);
  3479. rate->min = rate->max = cdc_dma_rx_cfg[idx].sample_rate;
  3480. channels->min = channels->max = cdc_dma_rx_cfg[idx].channels;
  3481. break;
  3482. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_0:
  3483. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_3:
  3484. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_4:
  3485. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3486. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3487. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  3488. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3489. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3490. cdc_dma_tx_cfg[idx].bit_format);
  3491. rate->min = rate->max = cdc_dma_tx_cfg[idx].sample_rate;
  3492. channels->min = channels->max = cdc_dma_tx_cfg[idx].channels;
  3493. break;
  3494. case MSM_BACKEND_DAI_SLIMBUS_7_RX:
  3495. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3496. slim_rx_cfg[SLIM_RX_7].bit_format);
  3497. rate->min = rate->max = slim_rx_cfg[SLIM_RX_7].sample_rate;
  3498. channels->min = channels->max =
  3499. slim_rx_cfg[SLIM_RX_7].channels;
  3500. break;
  3501. case MSM_BACKEND_DAI_SLIMBUS_7_TX:
  3502. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3503. slim_tx_cfg[SLIM_TX_7].bit_format);
  3504. rate->min = rate->max = slim_tx_cfg[SLIM_TX_7].sample_rate;
  3505. channels->min = channels->max =
  3506. slim_tx_cfg[SLIM_TX_7].channels;
  3507. break;
  3508. case MSM_BACKEND_DAI_SLIMBUS_8_TX:
  3509. rate->min = rate->max = slim_tx_cfg[SLIM_TX_8].sample_rate;
  3510. channels->min = channels->max =
  3511. slim_tx_cfg[SLIM_TX_8].channels;
  3512. break;
  3513. case MSM_BACKEND_DAI_AFE_LOOPBACK_TX:
  3514. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3515. afe_loopback_tx_cfg[idx].bit_format);
  3516. rate->min = rate->max = afe_loopback_tx_cfg[idx].sample_rate;
  3517. channels->min = channels->max =
  3518. afe_loopback_tx_cfg[idx].channels;
  3519. break;
  3520. default:
  3521. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3522. break;
  3523. }
  3524. return rc;
  3525. }
  3526. static bool msm_usbc_swap_gnd_mic(struct snd_soc_component *component,
  3527. bool active)
  3528. {
  3529. struct snd_soc_card *card = component->card;
  3530. struct msm_asoc_mach_data *pdata =
  3531. snd_soc_card_get_drvdata(card);
  3532. if (!pdata->fsa_handle)
  3533. return false;
  3534. return fsa4480_switch_event(pdata->fsa_handle, FSA_MIC_GND_SWAP);
  3535. }
  3536. static bool msm_swap_gnd_mic(struct snd_soc_component *component, bool active)
  3537. {
  3538. int value = 0;
  3539. bool ret = false;
  3540. struct snd_soc_card *card;
  3541. struct msm_asoc_mach_data *pdata;
  3542. if (!component) {
  3543. pr_err("%s component is NULL\n", __func__);
  3544. return false;
  3545. }
  3546. card = component->card;
  3547. pdata = snd_soc_card_get_drvdata(card);
  3548. if (!pdata)
  3549. return false;
  3550. if (wcd_mbhc_cfg.enable_usbc_analog)
  3551. return msm_usbc_swap_gnd_mic(component, active);
  3552. /* if usbc is not defined, swap using us_euro_gpio_p */
  3553. if (pdata->us_euro_gpio_p) {
  3554. value = msm_cdc_pinctrl_get_state(
  3555. pdata->us_euro_gpio_p);
  3556. if (value)
  3557. msm_cdc_pinctrl_select_sleep_state(
  3558. pdata->us_euro_gpio_p);
  3559. else
  3560. msm_cdc_pinctrl_select_active_state(
  3561. pdata->us_euro_gpio_p);
  3562. dev_dbg(component->dev, "%s: swap select switch %d to %d\n",
  3563. __func__, value, !value);
  3564. ret = true;
  3565. }
  3566. return ret;
  3567. }
  3568. static int holi_tdm_snd_hw_params(struct snd_pcm_substream *substream,
  3569. struct snd_pcm_hw_params *params)
  3570. {
  3571. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3572. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3573. int ret = 0;
  3574. int slot_width = TDM_SLOT_WIDTH_BITS;
  3575. int channels, slots = TDM_MAX_SLOTS;
  3576. unsigned int slot_mask, rate, clk_freq;
  3577. unsigned int *slot_offset;
  3578. struct tdm_dev_config *config;
  3579. unsigned int path_dir = 0, interface = 0, channel_interface = 0;
  3580. pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id);
  3581. if (cpu_dai->id < AFE_PORT_ID_TDM_PORT_RANGE_START) {
  3582. pr_err("%s: dai id 0x%x not supported\n",
  3583. __func__, cpu_dai->id);
  3584. return -EINVAL;
  3585. }
  3586. /* RX or TX */
  3587. path_dir = cpu_dai->id % MAX_PATH;
  3588. /* PRI, SEC, TERT, QUAT ... */
  3589. interface = (cpu_dai->id - AFE_PORT_ID_TDM_PORT_RANGE_START)
  3590. / (MAX_PATH * TDM_PORT_MAX);
  3591. /* 0, 1, 2, .. 7 */
  3592. channel_interface =
  3593. ((cpu_dai->id - AFE_PORT_ID_TDM_PORT_RANGE_START) / MAX_PATH)
  3594. % TDM_PORT_MAX;
  3595. pr_debug("%s: path dir: %u, interface %u, channel interface %u\n",
  3596. __func__, path_dir, interface, channel_interface);
  3597. config = ((struct tdm_dev_config *) tdm_cfg[interface]) +
  3598. (path_dir * TDM_PORT_MAX) + channel_interface;
  3599. slot_offset = config->tdm_slot_offset;
  3600. if (path_dir)
  3601. channels = tdm_tx_cfg[interface][channel_interface].channels;
  3602. else
  3603. channels = tdm_rx_cfg[interface][channel_interface].channels;
  3604. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  3605. /*2 slot config - bits 0 and 1 set for the first two slots */
  3606. slot_mask = 0x0000FFFF >> (16 - slots);
  3607. pr_debug("%s: tdm rx slot_width %d slots %d slot_mask %x\n",
  3608. __func__, slot_width, slots, slot_mask);
  3609. ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, slot_mask,
  3610. slots, slot_width);
  3611. if (ret < 0) {
  3612. pr_err("%s: failed to set tdm rx slot, err:%d\n",
  3613. __func__, ret);
  3614. goto end;
  3615. }
  3616. pr_debug("%s: tdm rx channels: %d\n", __func__, channels);
  3617. ret = snd_soc_dai_set_channel_map(cpu_dai,
  3618. 0, NULL, channels, slot_offset);
  3619. if (ret < 0) {
  3620. pr_err("%s: failed to set tdm rx channel map, err:%d\n",
  3621. __func__, ret);
  3622. goto end;
  3623. }
  3624. } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  3625. /*2 slot config - bits 0 and 1 set for the first two slots */
  3626. slot_mask = 0x0000FFFF >> (16 - slots);
  3627. pr_debug("%s: tdm tx slot_width %d slots %d slot_mask %x\n",
  3628. __func__, slot_width, slots, slot_mask);
  3629. ret = snd_soc_dai_set_tdm_slot(cpu_dai, slot_mask, 0,
  3630. slots, slot_width);
  3631. if (ret < 0) {
  3632. pr_err("%s: failed to set tdm tx slot, err:%d\n",
  3633. __func__, ret);
  3634. goto end;
  3635. }
  3636. pr_debug("%s: tdm tx channels: %d\n", __func__, channels);
  3637. ret = snd_soc_dai_set_channel_map(cpu_dai,
  3638. channels, slot_offset, 0, NULL);
  3639. if (ret < 0) {
  3640. pr_err("%s: failed to set tdm tx channel map, err:%d\n",
  3641. __func__, ret);
  3642. goto end;
  3643. }
  3644. } else {
  3645. ret = -EINVAL;
  3646. pr_err("%s: invalid use case, err:%d\n",
  3647. __func__, ret);
  3648. goto end;
  3649. }
  3650. rate = params_rate(params);
  3651. clk_freq = rate * slot_width * slots;
  3652. ret = snd_soc_dai_set_sysclk(cpu_dai, 0, clk_freq, SND_SOC_CLOCK_OUT);
  3653. if (ret < 0)
  3654. pr_err("%s: failed to set tdm clk, err:%d\n",
  3655. __func__, ret);
  3656. end:
  3657. return ret;
  3658. }
  3659. static int msm_get_tdm_mode(u32 port_id)
  3660. {
  3661. int tdm_mode;
  3662. switch (port_id) {
  3663. case AFE_PORT_ID_PRIMARY_TDM_RX:
  3664. case AFE_PORT_ID_PRIMARY_TDM_TX:
  3665. tdm_mode = TDM_PRI;
  3666. break;
  3667. case AFE_PORT_ID_SECONDARY_TDM_RX:
  3668. case AFE_PORT_ID_SECONDARY_TDM_TX:
  3669. tdm_mode = TDM_SEC;
  3670. break;
  3671. case AFE_PORT_ID_TERTIARY_TDM_RX:
  3672. case AFE_PORT_ID_TERTIARY_TDM_TX:
  3673. tdm_mode = TDM_TERT;
  3674. break;
  3675. case AFE_PORT_ID_QUATERNARY_TDM_RX:
  3676. case AFE_PORT_ID_QUATERNARY_TDM_TX:
  3677. tdm_mode = TDM_QUAT;
  3678. break;
  3679. default:
  3680. pr_err("%s: Invalid port id: %d\n", __func__, port_id);
  3681. tdm_mode = -EINVAL;
  3682. }
  3683. return tdm_mode;
  3684. }
  3685. static int holi_tdm_snd_startup(struct snd_pcm_substream *substream)
  3686. {
  3687. int ret = 0;
  3688. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3689. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3690. struct snd_soc_card *card = rtd->card;
  3691. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  3692. int tdm_mode = msm_get_tdm_mode(cpu_dai->id);
  3693. if (tdm_mode >= TDM_INTERFACE_MAX || tdm_mode < 0) {
  3694. ret = -EINVAL;
  3695. pr_err("%s: Invalid TDM interface %d\n",
  3696. __func__, ret);
  3697. return ret;
  3698. }
  3699. if (pdata->mi2s_gpio_p[tdm_mode]) {
  3700. if (atomic_read(&(pdata->mi2s_gpio_ref_count[tdm_mode]))
  3701. == 0) {
  3702. ret = msm_cdc_pinctrl_select_active_state(
  3703. pdata->mi2s_gpio_p[tdm_mode]);
  3704. if (ret) {
  3705. pr_err("%s: TDM GPIO pinctrl set active failed with %d\n",
  3706. __func__, ret);
  3707. goto done;
  3708. }
  3709. }
  3710. atomic_inc(&(pdata->mi2s_gpio_ref_count[tdm_mode]));
  3711. }
  3712. done:
  3713. return ret;
  3714. }
  3715. static void holi_tdm_snd_shutdown(struct snd_pcm_substream *substream)
  3716. {
  3717. int ret = 0;
  3718. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3719. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3720. struct snd_soc_card *card = rtd->card;
  3721. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  3722. int tdm_mode = msm_get_tdm_mode(cpu_dai->id);
  3723. if (tdm_mode >= TDM_INTERFACE_MAX || tdm_mode < 0) {
  3724. ret = -EINVAL;
  3725. pr_err("%s: Invalid TDM interface %d\n",
  3726. __func__, ret);
  3727. return;
  3728. }
  3729. if (pdata->mi2s_gpio_p[tdm_mode]) {
  3730. atomic_dec(&(pdata->mi2s_gpio_ref_count[tdm_mode]));
  3731. if (atomic_read(&(pdata->mi2s_gpio_ref_count[tdm_mode]))
  3732. == 0) {
  3733. ret = msm_cdc_pinctrl_select_sleep_state(
  3734. pdata->mi2s_gpio_p[tdm_mode]);
  3735. if (ret)
  3736. pr_err("%s: TDM GPIO pinctrl set sleep failed with %d\n",
  3737. __func__, ret);
  3738. }
  3739. }
  3740. }
  3741. static int holi_aux_snd_startup(struct snd_pcm_substream *substream)
  3742. {
  3743. int ret = 0;
  3744. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3745. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3746. struct snd_soc_card *card = rtd->card;
  3747. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  3748. u32 aux_mode = cpu_dai->id - 1;
  3749. if (aux_mode >= AUX_PCM_MAX) {
  3750. ret = -EINVAL;
  3751. pr_err("%s: Invalid AUX interface %d\n",
  3752. __func__, ret);
  3753. return ret;
  3754. }
  3755. if (pdata->mi2s_gpio_p[aux_mode]) {
  3756. if (atomic_read(&(pdata->mi2s_gpio_ref_count[aux_mode]))
  3757. == 0) {
  3758. ret = msm_cdc_pinctrl_select_active_state(
  3759. pdata->mi2s_gpio_p[aux_mode]);
  3760. if (ret) {
  3761. pr_err("%s: AUX GPIO pinctrl set active failed with %d\n",
  3762. __func__, ret);
  3763. goto done;
  3764. }
  3765. }
  3766. atomic_inc(&(pdata->mi2s_gpio_ref_count[aux_mode]));
  3767. }
  3768. done:
  3769. return ret;
  3770. }
  3771. static void holi_aux_snd_shutdown(struct snd_pcm_substream *substream)
  3772. {
  3773. int ret = 0;
  3774. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3775. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3776. struct snd_soc_card *card = rtd->card;
  3777. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  3778. u32 aux_mode = cpu_dai->id - 1;
  3779. if (aux_mode >= AUX_PCM_MAX) {
  3780. pr_err("%s: Invalid AUX interface %d\n",
  3781. __func__, ret);
  3782. return;
  3783. }
  3784. if (pdata->mi2s_gpio_p[aux_mode]) {
  3785. atomic_dec(&(pdata->mi2s_gpio_ref_count[aux_mode]));
  3786. if (atomic_read(&(pdata->mi2s_gpio_ref_count[aux_mode]))
  3787. == 0) {
  3788. ret = msm_cdc_pinctrl_select_sleep_state(
  3789. pdata->mi2s_gpio_p[aux_mode]);
  3790. if (ret)
  3791. pr_err("%s: AUX GPIO pinctrl set sleep failed with %d\n",
  3792. __func__, ret);
  3793. }
  3794. }
  3795. }
  3796. static int msm_snd_cdc_dma_startup(struct snd_pcm_substream *substream)
  3797. {
  3798. int ret = 0;
  3799. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3800. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3801. switch (dai_link->id) {
  3802. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3803. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3804. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  3805. ret = holi_send_island_va_config(dai_link->id);
  3806. if (ret)
  3807. pr_err("%s: send island va cfg failed, err: %d\n",
  3808. __func__, ret);
  3809. break;
  3810. }
  3811. return ret;
  3812. }
  3813. static int msm_snd_cdc_dma_hw_params(struct snd_pcm_substream *substream,
  3814. struct snd_pcm_hw_params *params)
  3815. {
  3816. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3817. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3818. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3819. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3820. int ret = 0;
  3821. u32 rx_ch_cdc_dma, tx_ch_cdc_dma;
  3822. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  3823. u32 user_set_tx_ch = 0;
  3824. u32 user_set_rx_ch = 0;
  3825. u32 ch_id;
  3826. ret = snd_soc_dai_get_channel_map(codec_dai,
  3827. &tx_ch_cnt, &tx_ch_cdc_dma, &rx_ch_cnt,
  3828. &rx_ch_cdc_dma);
  3829. if (ret < 0) {
  3830. pr_err("%s: failed to get codec chan map, err:%d\n",
  3831. __func__, ret);
  3832. goto err;
  3833. }
  3834. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  3835. switch (dai_link->id) {
  3836. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_0:
  3837. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_1:
  3838. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_2:
  3839. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_3:
  3840. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_4:
  3841. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_5:
  3842. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_6:
  3843. {
  3844. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3845. pr_debug("%s: id %d rx_ch=%d\n", __func__,
  3846. ch_id, cdc_dma_rx_cfg[ch_id].channels);
  3847. user_set_rx_ch = cdc_dma_rx_cfg[ch_id].channels;
  3848. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  3849. user_set_rx_ch, &rx_ch_cdc_dma);
  3850. if (ret < 0) {
  3851. pr_err("%s: failed to set cpu chan map, err:%d\n",
  3852. __func__, ret);
  3853. goto err;
  3854. }
  3855. }
  3856. break;
  3857. }
  3858. } else {
  3859. switch (dai_link->id) {
  3860. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_0:
  3861. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_3:
  3862. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_4:
  3863. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3864. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3865. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  3866. {
  3867. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3868. pr_debug("%s: id %d tx_ch=%d\n", __func__,
  3869. ch_id, cdc_dma_tx_cfg[ch_id].channels);
  3870. user_set_tx_ch = cdc_dma_tx_cfg[ch_id].channels;
  3871. }
  3872. break;
  3873. }
  3874. ret = snd_soc_dai_set_channel_map(cpu_dai, user_set_tx_ch,
  3875. &tx_ch_cdc_dma, 0, 0);
  3876. if (ret < 0) {
  3877. pr_err("%s: failed to set cpu chan map, err:%d\n",
  3878. __func__, ret);
  3879. goto err;
  3880. }
  3881. }
  3882. err:
  3883. return ret;
  3884. }
  3885. static int msm_fe_qos_prepare(struct snd_pcm_substream *substream)
  3886. {
  3887. (void)substream;
  3888. qos_client_active_cnt++;
  3889. if (qos_client_active_cnt == 1)
  3890. msm_audio_update_qos_request(MSM_LL_QOS_VALUE);
  3891. return 0;
  3892. }
  3893. static void msm_fe_qos_shutdown(struct snd_pcm_substream *substream)
  3894. {
  3895. (void)substream;
  3896. if (qos_client_active_cnt > 0)
  3897. qos_client_active_cnt--;
  3898. if (qos_client_active_cnt == 0)
  3899. msm_audio_update_qos_request(PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE);
  3900. }
  3901. void mi2s_disable_audio_vote(struct snd_pcm_substream *substream)
  3902. {
  3903. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3904. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3905. int index = cpu_dai->id;
  3906. struct snd_soc_card *card = rtd->card;
  3907. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  3908. int sample_rate = 0;
  3909. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  3910. sample_rate = mi2s_rx_cfg[index].sample_rate;
  3911. } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  3912. sample_rate = mi2s_tx_cfg[index].sample_rate;
  3913. } else {
  3914. pr_err("%s: invalid stream %d\n", __func__, substream->stream);
  3915. return;
  3916. }
  3917. if (IS_MSM_INTERFACE_MI2S(index) && IS_FRACTIONAL(sample_rate)) {
  3918. if (pdata->lpass_audio_hw_vote != NULL) {
  3919. if (--pdata->core_audio_vote_count == 0) {
  3920. clk_disable_unprepare(
  3921. pdata->lpass_audio_hw_vote);
  3922. } else if (pdata->core_audio_vote_count < 0) {
  3923. pr_err("%s: audio vote mismatch\n", __func__);
  3924. pdata->core_audio_vote_count = 0;
  3925. }
  3926. } else {
  3927. pr_err("%s: Invalid lpass audio hw node\n", __func__);
  3928. }
  3929. }
  3930. }
  3931. static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
  3932. {
  3933. int ret = 0;
  3934. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3935. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3936. int index = cpu_dai->id;
  3937. unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
  3938. struct snd_soc_card *card = rtd->card;
  3939. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  3940. int sample_rate = 0;
  3941. dev_dbg(rtd->card->dev,
  3942. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  3943. __func__, substream->name, substream->stream,
  3944. cpu_dai->name, cpu_dai->id);
  3945. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  3946. ret = -EINVAL;
  3947. dev_err(rtd->card->dev,
  3948. "%s: CPU DAI id (%d) out of range\n",
  3949. __func__, cpu_dai->id);
  3950. goto err;
  3951. }
  3952. /*
  3953. * Mutex protection in case the same MI2S
  3954. * interface using for both TX and RX so
  3955. * that the same clock won't be enable twice.
  3956. */
  3957. mutex_lock(&mi2s_intf_conf[index].lock);
  3958. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  3959. sample_rate = mi2s_rx_cfg[index].sample_rate;
  3960. } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  3961. sample_rate = mi2s_tx_cfg[index].sample_rate;
  3962. } else {
  3963. pr_err("%s: invalid stream %d\n", __func__, substream->stream);
  3964. ret = -EINVAL;
  3965. goto vote_err;
  3966. }
  3967. if (IS_MSM_INTERFACE_MI2S(index) && IS_FRACTIONAL(sample_rate)) {
  3968. if (pdata->lpass_audio_hw_vote == NULL) {
  3969. dev_err(rtd->card->dev, "%s: Invalid lpass audio hw node\n",
  3970. __func__);
  3971. ret = -EINVAL;
  3972. goto vote_err;
  3973. }
  3974. if (pdata->core_audio_vote_count == 0) {
  3975. ret = clk_prepare_enable(pdata->lpass_audio_hw_vote);
  3976. if (ret < 0) {
  3977. dev_err(rtd->card->dev, "%s: audio vote error\n",
  3978. __func__);
  3979. goto vote_err;
  3980. }
  3981. }
  3982. pdata->core_audio_vote_count++;
  3983. }
  3984. if (++mi2s_intf_conf[index].ref_cnt == 1) {
  3985. /* Check if msm needs to provide the clock to the interface */
  3986. if (!mi2s_intf_conf[index].msm_is_mi2s_master) {
  3987. mi2s_clk[index].clk_id = mi2s_ebit_clk[index];
  3988. fmt = SND_SOC_DAIFMT_CBM_CFM;
  3989. }
  3990. ret = msm_mi2s_set_sclk(substream, true);
  3991. if (ret < 0) {
  3992. dev_err(rtd->card->dev,
  3993. "%s: afe lpass clock failed to enable MI2S clock, err:%d\n",
  3994. __func__, ret);
  3995. goto clean_up;
  3996. }
  3997. ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
  3998. if (ret < 0) {
  3999. pr_err("%s: set fmt cpu dai failed for MI2S (%d), err:%d\n",
  4000. __func__, index, ret);
  4001. goto clk_off;
  4002. }
  4003. if (pdata->mi2s_gpio_p[index]) {
  4004. if (atomic_read(&(pdata->mi2s_gpio_ref_count[index]))
  4005. == 0) {
  4006. ret = msm_cdc_pinctrl_select_active_state(
  4007. pdata->mi2s_gpio_p[index]);
  4008. if (ret) {
  4009. pr_err("%s: MI2S GPIO pinctrl set active failed with %d\n",
  4010. __func__, ret);
  4011. goto clk_off;
  4012. }
  4013. }
  4014. atomic_inc(&(pdata->mi2s_gpio_ref_count[index]));
  4015. }
  4016. }
  4017. clk_off:
  4018. if (ret < 0)
  4019. msm_mi2s_set_sclk(substream, false);
  4020. clean_up:
  4021. if (ret < 0) {
  4022. mi2s_intf_conf[index].ref_cnt--;
  4023. mi2s_disable_audio_vote(substream);
  4024. }
  4025. vote_err:
  4026. mutex_unlock(&mi2s_intf_conf[index].lock);
  4027. err:
  4028. return ret;
  4029. }
  4030. static void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
  4031. {
  4032. int ret = 0;
  4033. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4034. int index = rtd->cpu_dai->id;
  4035. struct snd_soc_card *card = rtd->card;
  4036. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4037. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  4038. substream->name, substream->stream);
  4039. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  4040. pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index);
  4041. return;
  4042. }
  4043. mutex_lock(&mi2s_intf_conf[index].lock);
  4044. if (--mi2s_intf_conf[index].ref_cnt == 0) {
  4045. if (pdata->mi2s_gpio_p[index]) {
  4046. atomic_dec(&(pdata->mi2s_gpio_ref_count[index]));
  4047. if (atomic_read(&(pdata->mi2s_gpio_ref_count[index]))
  4048. == 0) {
  4049. ret = msm_cdc_pinctrl_select_sleep_state(
  4050. pdata->mi2s_gpio_p[index]);
  4051. if (ret)
  4052. pr_err("%s: MI2S GPIO pinctrl set sleep failed with %d\n",
  4053. __func__, ret);
  4054. }
  4055. }
  4056. ret = msm_mi2s_set_sclk(substream, false);
  4057. if (ret < 0)
  4058. pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n",
  4059. __func__, index, ret);
  4060. }
  4061. mi2s_disable_audio_vote(substream);
  4062. mutex_unlock(&mi2s_intf_conf[index].lock);
  4063. }
  4064. static int msm_wcn_hw_params_lito(struct snd_pcm_substream *substream,
  4065. struct snd_pcm_hw_params *params)
  4066. {
  4067. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4068. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4069. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4070. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4071. u32 rx_ch[WCN_CDC_SLIM_RX_CH_MAX], tx_ch[WCN_CDC_SLIM_TX_CH_MAX_LITO];
  4072. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4073. int ret = 0;
  4074. dev_dbg(rtd->dev, "%s: %s_tx_dai_id_%d\n", __func__,
  4075. codec_dai->name, codec_dai->id);
  4076. ret = snd_soc_dai_get_channel_map(codec_dai,
  4077. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4078. if (ret) {
  4079. dev_err(rtd->dev,
  4080. "%s: failed to get BTFM codec chan map\n, err:%d\n",
  4081. __func__, ret);
  4082. goto err;
  4083. }
  4084. dev_dbg(rtd->dev, "%s: tx_ch_cnt(%d) BE id %d\n",
  4085. __func__, tx_ch_cnt, dai_link->id);
  4086. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4087. tx_ch_cnt, tx_ch, rx_ch_cnt, rx_ch);
  4088. if (ret)
  4089. dev_err(rtd->dev, "%s: failed to set cpu chan map, err:%d\n",
  4090. __func__, ret);
  4091. err:
  4092. return ret;
  4093. }
  4094. static struct snd_soc_ops holi_aux_be_ops = {
  4095. .startup = holi_aux_snd_startup,
  4096. .shutdown = holi_aux_snd_shutdown
  4097. };
  4098. static struct snd_soc_ops holi_tdm_be_ops = {
  4099. .hw_params = holi_tdm_snd_hw_params,
  4100. .startup = holi_tdm_snd_startup,
  4101. .shutdown = holi_tdm_snd_shutdown
  4102. };
  4103. static struct snd_soc_ops msm_mi2s_be_ops = {
  4104. .startup = msm_mi2s_snd_startup,
  4105. .shutdown = msm_mi2s_snd_shutdown,
  4106. };
  4107. static struct snd_soc_ops msm_fe_qos_ops = {
  4108. .prepare = msm_fe_qos_prepare,
  4109. .shutdown = msm_fe_qos_shutdown,
  4110. };
  4111. static struct snd_soc_ops msm_cdc_dma_be_ops = {
  4112. .startup = msm_snd_cdc_dma_startup,
  4113. .hw_params = msm_snd_cdc_dma_hw_params,
  4114. };
  4115. static struct snd_soc_ops msm_wcn_ops_lito = {
  4116. .hw_params = msm_wcn_hw_params_lito,
  4117. };
  4118. static int msm_dmic_event(struct snd_soc_dapm_widget *w,
  4119. struct snd_kcontrol *kcontrol, int event)
  4120. {
  4121. struct msm_asoc_mach_data *pdata = NULL;
  4122. struct snd_soc_component *component =
  4123. snd_soc_dapm_to_component(w->dapm);
  4124. int ret = 0;
  4125. u32 dmic_idx;
  4126. int *dmic_gpio_cnt;
  4127. struct device_node *dmic_gpio;
  4128. char *wname;
  4129. wname = strpbrk(w->name, "012345");
  4130. if (!wname) {
  4131. dev_err(component->dev, "%s: widget not found\n", __func__);
  4132. return -EINVAL;
  4133. }
  4134. ret = kstrtouint(wname, 10, &dmic_idx);
  4135. if (ret < 0) {
  4136. dev_err(component->dev, "%s: Invalid DMIC line on the codec\n",
  4137. __func__);
  4138. return -EINVAL;
  4139. }
  4140. pdata = snd_soc_card_get_drvdata(component->card);
  4141. switch (dmic_idx) {
  4142. case 0:
  4143. case 1:
  4144. dmic_gpio_cnt = &dmic_0_1_gpio_cnt;
  4145. dmic_gpio = pdata->dmic01_gpio_p;
  4146. break;
  4147. case 2:
  4148. case 3:
  4149. dmic_gpio_cnt = &dmic_2_3_gpio_cnt;
  4150. dmic_gpio = pdata->dmic23_gpio_p;
  4151. break;
  4152. case 4:
  4153. case 5:
  4154. dmic_gpio_cnt = &dmic_4_5_gpio_cnt;
  4155. dmic_gpio = pdata->dmic45_gpio_p;
  4156. break;
  4157. default:
  4158. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  4159. __func__);
  4160. return -EINVAL;
  4161. }
  4162. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_gpio_cnt %d\n",
  4163. __func__, event, dmic_idx, *dmic_gpio_cnt);
  4164. switch (event) {
  4165. case SND_SOC_DAPM_PRE_PMU:
  4166. (*dmic_gpio_cnt)++;
  4167. if (*dmic_gpio_cnt == 1) {
  4168. ret = msm_cdc_pinctrl_select_active_state(
  4169. dmic_gpio);
  4170. if (ret < 0) {
  4171. pr_err("%s: gpio set cannot be activated %sd",
  4172. __func__, "dmic_gpio");
  4173. return ret;
  4174. }
  4175. }
  4176. break;
  4177. case SND_SOC_DAPM_POST_PMD:
  4178. (*dmic_gpio_cnt)--;
  4179. if (*dmic_gpio_cnt == 0) {
  4180. ret = msm_cdc_pinctrl_select_sleep_state(
  4181. dmic_gpio);
  4182. if (ret < 0) {
  4183. pr_err("%s: gpio set cannot be de-activated %sd",
  4184. __func__, "dmic_gpio");
  4185. return ret;
  4186. }
  4187. }
  4188. break;
  4189. default:
  4190. pr_err("%s: invalid DAPM event %d\n", __func__, event);
  4191. return -EINVAL;
  4192. }
  4193. return 0;
  4194. }
  4195. static const struct snd_soc_dapm_widget msm_int_dapm_widgets[] = {
  4196. SND_SOC_DAPM_MIC("Analog Mic1", NULL),
  4197. SND_SOC_DAPM_MIC("Analog Mic2", NULL),
  4198. SND_SOC_DAPM_MIC("Analog Mic3", NULL),
  4199. SND_SOC_DAPM_MIC("Analog Mic4", NULL),
  4200. SND_SOC_DAPM_MIC("Analog Mic5", NULL),
  4201. SND_SOC_DAPM_MIC("Digital Mic0", msm_dmic_event),
  4202. SND_SOC_DAPM_MIC("Digital Mic1", msm_dmic_event),
  4203. SND_SOC_DAPM_MIC("Digital Mic2", msm_dmic_event),
  4204. SND_SOC_DAPM_MIC("Digital Mic3", msm_dmic_event),
  4205. SND_SOC_DAPM_MIC("Digital Mic4", msm_dmic_event),
  4206. SND_SOC_DAPM_MIC("Digital Mic5", msm_dmic_event),
  4207. SND_SOC_DAPM_MIC("Digital Mic6", NULL),
  4208. SND_SOC_DAPM_MIC("Digital Mic7", NULL),
  4209. };
  4210. static int msm_wcn_init_lito(struct snd_soc_pcm_runtime *rtd)
  4211. {
  4212. unsigned int rx_ch[WCN_CDC_SLIM_RX_CH_MAX] = {157, 158};
  4213. unsigned int tx_ch[WCN_CDC_SLIM_TX_CH_MAX_LITO] = {159, 160, 161};
  4214. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4215. return snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  4216. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  4217. }
  4218. static struct snd_info_entry *msm_snd_info_create_subdir(struct module *mod,
  4219. const char *name,
  4220. struct snd_info_entry *parent)
  4221. {
  4222. struct snd_info_entry *entry;
  4223. entry = snd_info_create_module_entry(mod, name, parent);
  4224. if (!entry)
  4225. return NULL;
  4226. entry->mode = S_IFDIR | 0555;
  4227. if (snd_info_register(entry) < 0) {
  4228. snd_info_free_entry(entry);
  4229. return NULL;
  4230. }
  4231. return entry;
  4232. }
  4233. static void *def_wcd_mbhc_cal(void)
  4234. {
  4235. void *wcd_mbhc_cal;
  4236. struct wcd_mbhc_btn_detect_cfg *btn_cfg;
  4237. u16 *btn_high;
  4238. wcd_mbhc_cal = kzalloc(WCD_MBHC_CAL_SIZE(WCD_MBHC_DEF_BUTTONS,
  4239. WCD9XXX_MBHC_DEF_RLOADS), GFP_KERNEL);
  4240. if (!wcd_mbhc_cal)
  4241. return NULL;
  4242. WCD_MBHC_CAL_PLUG_TYPE_PTR(wcd_mbhc_cal)->v_hs_max = WCD_MBHC_HS_V_MAX;
  4243. WCD_MBHC_CAL_BTN_DET_PTR(wcd_mbhc_cal)->num_btn = WCD_MBHC_DEF_BUTTONS;
  4244. btn_cfg = WCD_MBHC_CAL_BTN_DET_PTR(wcd_mbhc_cal);
  4245. btn_high = ((void *)&btn_cfg->_v_btn_low) +
  4246. (sizeof(btn_cfg->_v_btn_low[0]) * btn_cfg->num_btn);
  4247. btn_high[0] = 75;
  4248. btn_high[1] = 150;
  4249. btn_high[2] = 237;
  4250. btn_high[3] = 500;
  4251. btn_high[4] = 500;
  4252. btn_high[5] = 500;
  4253. btn_high[6] = 500;
  4254. btn_high[7] = 500;
  4255. return wcd_mbhc_cal;
  4256. }
  4257. /* Digital audio interface glue - connects codec <---> CPU */
  4258. static struct snd_soc_dai_link msm_common_dai_links[] = {
  4259. /* FrontEnd DAI Links */
  4260. {/* hw:x,0 */
  4261. .name = MSM_DAILINK_NAME(Media1),
  4262. .stream_name = "MultiMedia1",
  4263. .dynamic = 1,
  4264. #if IS_ENABLED(CONFIG_AUDIO_QGKI)
  4265. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4266. #endif /* CONFIG_AUDIO_QGKI */
  4267. .dpcm_playback = 1,
  4268. .dpcm_capture = 1,
  4269. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4270. SND_SOC_DPCM_TRIGGER_POST},
  4271. .ignore_suspend = 1,
  4272. /* this dainlink has playback support */
  4273. .ignore_pmdown_time = 1,
  4274. .id = MSM_FRONTEND_DAI_MULTIMEDIA1,
  4275. SND_SOC_DAILINK_REG(multimedia1),
  4276. },
  4277. {/* hw:x,1 */
  4278. .name = MSM_DAILINK_NAME(Media2),
  4279. .stream_name = "MultiMedia2",
  4280. .dynamic = 1,
  4281. .dpcm_playback = 1,
  4282. .dpcm_capture = 1,
  4283. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4284. SND_SOC_DPCM_TRIGGER_POST},
  4285. .ignore_suspend = 1,
  4286. /* this dainlink has playback support */
  4287. .ignore_pmdown_time = 1,
  4288. .id = MSM_FRONTEND_DAI_MULTIMEDIA2,
  4289. SND_SOC_DAILINK_REG(multimedia2),
  4290. },
  4291. {/* hw:x,2 */
  4292. .name = "VoiceMMode1",
  4293. .stream_name = "VoiceMMode1",
  4294. .dynamic = 1,
  4295. .dpcm_playback = 1,
  4296. .dpcm_capture = 1,
  4297. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4298. SND_SOC_DPCM_TRIGGER_POST},
  4299. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4300. .ignore_suspend = 1,
  4301. .ignore_pmdown_time = 1,
  4302. .id = MSM_FRONTEND_DAI_VOICEMMODE1,
  4303. SND_SOC_DAILINK_REG(voicemmode1),
  4304. },
  4305. {/* hw:x,3 */
  4306. .name = "MSM VoIP",
  4307. .stream_name = "VoIP",
  4308. .dynamic = 1,
  4309. .dpcm_playback = 1,
  4310. .dpcm_capture = 1,
  4311. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4312. SND_SOC_DPCM_TRIGGER_POST},
  4313. .ignore_suspend = 1,
  4314. /* this dainlink has playback support */
  4315. .ignore_pmdown_time = 1,
  4316. .id = MSM_FRONTEND_DAI_VOIP,
  4317. SND_SOC_DAILINK_REG(msmvoip),
  4318. },
  4319. {/* hw:x,4 */
  4320. .name = MSM_DAILINK_NAME(ULL),
  4321. .stream_name = "MultiMedia3",
  4322. .dynamic = 1,
  4323. #if IS_ENABLED(CONFIG_AUDIO_QGKI)
  4324. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4325. #endif /* CONFIG_AUDIO_QGKI */
  4326. .dpcm_playback = 1,
  4327. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4328. SND_SOC_DPCM_TRIGGER_POST},
  4329. .ignore_suspend = 1,
  4330. /* this dainlink has playback support */
  4331. .ignore_pmdown_time = 1,
  4332. .id = MSM_FRONTEND_DAI_MULTIMEDIA3,
  4333. SND_SOC_DAILINK_REG(multimedia3),
  4334. },
  4335. {/* hw:x,5 */
  4336. .name = "MSM AFE-PCM RX",
  4337. .stream_name = "AFE-PROXY RX",
  4338. .dpcm_playback = 1,
  4339. .ignore_suspend = 1,
  4340. /* this dainlink has playback support */
  4341. .ignore_pmdown_time = 1,
  4342. SND_SOC_DAILINK_REG(afepcm_rx),
  4343. },
  4344. {/* hw:x,6 */
  4345. .name = "MSM AFE-PCM TX",
  4346. .stream_name = "AFE-PROXY TX",
  4347. .dpcm_capture = 1,
  4348. .ignore_suspend = 1,
  4349. SND_SOC_DAILINK_REG(afepcm_tx),
  4350. },
  4351. {/* hw:x,7 */
  4352. .name = MSM_DAILINK_NAME(Compress1),
  4353. .stream_name = "Compress1",
  4354. .dynamic = 1,
  4355. #if IS_ENABLED(CONFIG_AUDIO_QGKI)
  4356. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  4357. #endif /* CONFIG_AUDIO_QGKI */
  4358. .dpcm_playback = 1,
  4359. .dpcm_capture = 1,
  4360. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4361. SND_SOC_DPCM_TRIGGER_POST},
  4362. .ignore_suspend = 1,
  4363. .ignore_pmdown_time = 1,
  4364. /* this dainlink has playback support */
  4365. .id = MSM_FRONTEND_DAI_MULTIMEDIA4,
  4366. SND_SOC_DAILINK_REG(multimedia4),
  4367. },
  4368. /* Hostless PCM purpose */
  4369. {/* hw:x,8 */
  4370. .name = "AUXPCM Hostless",
  4371. .stream_name = "AUXPCM Hostless",
  4372. .dynamic = 1,
  4373. .dpcm_playback = 1,
  4374. .dpcm_capture = 1,
  4375. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4376. SND_SOC_DPCM_TRIGGER_POST},
  4377. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4378. .ignore_suspend = 1,
  4379. /* this dainlink has playback support */
  4380. .ignore_pmdown_time = 1,
  4381. SND_SOC_DAILINK_REG(auxpcm_hostless),
  4382. },
  4383. {/* hw:x,9 */
  4384. .name = MSM_DAILINK_NAME(LowLatency),
  4385. .stream_name = "MultiMedia5",
  4386. .dynamic = 1,
  4387. #if IS_ENABLED(CONFIG_AUDIO_QGKI)
  4388. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4389. #endif /* CONFIG_AUDIO_QGKI */
  4390. .dpcm_playback = 1,
  4391. .dpcm_capture = 1,
  4392. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4393. SND_SOC_DPCM_TRIGGER_POST},
  4394. .ignore_suspend = 1,
  4395. /* this dainlink has playback support */
  4396. .ignore_pmdown_time = 1,
  4397. .id = MSM_FRONTEND_DAI_MULTIMEDIA5,
  4398. .ops = &msm_fe_qos_ops,
  4399. SND_SOC_DAILINK_REG(multimedia5),
  4400. },
  4401. {/* hw:x,10 */
  4402. .name = "Listen 1 Audio Service",
  4403. .stream_name = "Listen 1 Audio Service",
  4404. .dynamic = 1,
  4405. .dpcm_capture = 1,
  4406. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4407. SND_SOC_DPCM_TRIGGER_POST },
  4408. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4409. .ignore_suspend = 1,
  4410. .id = MSM_FRONTEND_DAI_LSM1,
  4411. SND_SOC_DAILINK_REG(listen1),
  4412. },
  4413. /* Multiple Tunnel instances */
  4414. {/* hw:x,11 */
  4415. .name = MSM_DAILINK_NAME(Compress2),
  4416. .stream_name = "Compress2",
  4417. .dynamic = 1,
  4418. .dpcm_playback = 1,
  4419. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4420. SND_SOC_DPCM_TRIGGER_POST},
  4421. .ignore_suspend = 1,
  4422. .ignore_pmdown_time = 1,
  4423. /* this dainlink has playback support */
  4424. .id = MSM_FRONTEND_DAI_MULTIMEDIA7,
  4425. SND_SOC_DAILINK_REG(multimedia7),
  4426. },
  4427. {/* hw:x,12 */
  4428. .name = MSM_DAILINK_NAME(MultiMedia10),
  4429. .stream_name = "MultiMedia10",
  4430. .dynamic = 1,
  4431. .dpcm_playback = 1,
  4432. .dpcm_capture = 1,
  4433. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4434. SND_SOC_DPCM_TRIGGER_POST},
  4435. .ignore_suspend = 1,
  4436. .ignore_pmdown_time = 1,
  4437. /* this dainlink has playback support */
  4438. .id = MSM_FRONTEND_DAI_MULTIMEDIA10,
  4439. SND_SOC_DAILINK_REG(multimedia10),
  4440. },
  4441. {/* hw:x,13 */
  4442. .name = MSM_DAILINK_NAME(ULL_NOIRQ),
  4443. .stream_name = "MM_NOIRQ",
  4444. .dynamic = 1,
  4445. .dpcm_playback = 1,
  4446. .dpcm_capture = 1,
  4447. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4448. SND_SOC_DPCM_TRIGGER_POST},
  4449. .ignore_suspend = 1,
  4450. .ignore_pmdown_time = 1,
  4451. /* this dainlink has playback support */
  4452. .id = MSM_FRONTEND_DAI_MULTIMEDIA8,
  4453. .ops = &msm_fe_qos_ops,
  4454. SND_SOC_DAILINK_REG(multimedia8),
  4455. },
  4456. /* HDMI Hostless */
  4457. {/* hw:x,14 */
  4458. .name = "HDMI_RX_HOSTLESS",
  4459. .stream_name = "HDMI_RX_HOSTLESS",
  4460. .dynamic = 1,
  4461. .dpcm_playback = 1,
  4462. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4463. SND_SOC_DPCM_TRIGGER_POST},
  4464. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4465. .ignore_suspend = 1,
  4466. .ignore_pmdown_time = 1,
  4467. SND_SOC_DAILINK_REG(hdmi_rx_hostless),
  4468. },
  4469. {/* hw:x,15 */
  4470. .name = "VoiceMMode2",
  4471. .stream_name = "VoiceMMode2",
  4472. .dynamic = 1,
  4473. .dpcm_playback = 1,
  4474. .dpcm_capture = 1,
  4475. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4476. SND_SOC_DPCM_TRIGGER_POST},
  4477. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4478. .ignore_suspend = 1,
  4479. .ignore_pmdown_time = 1,
  4480. .id = MSM_FRONTEND_DAI_VOICEMMODE2,
  4481. SND_SOC_DAILINK_REG(voicemmode2),
  4482. },
  4483. /* LSM FE */
  4484. {/* hw:x,16 */
  4485. .name = "Listen 2 Audio Service",
  4486. .stream_name = "Listen 2 Audio Service",
  4487. .dynamic = 1,
  4488. .dpcm_capture = 1,
  4489. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4490. SND_SOC_DPCM_TRIGGER_POST },
  4491. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4492. .ignore_suspend = 1,
  4493. .id = MSM_FRONTEND_DAI_LSM2,
  4494. SND_SOC_DAILINK_REG(listen2),
  4495. },
  4496. {/* hw:x,17 */
  4497. .name = "Listen 3 Audio Service",
  4498. .stream_name = "Listen 3 Audio Service",
  4499. .dynamic = 1,
  4500. .dpcm_capture = 1,
  4501. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4502. SND_SOC_DPCM_TRIGGER_POST },
  4503. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4504. .ignore_suspend = 1,
  4505. .id = MSM_FRONTEND_DAI_LSM3,
  4506. SND_SOC_DAILINK_REG(listen3),
  4507. },
  4508. {/* hw:x,18 */
  4509. .name = "Listen 4 Audio Service",
  4510. .stream_name = "Listen 4 Audio Service",
  4511. .dynamic = 1,
  4512. .dpcm_capture = 1,
  4513. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4514. SND_SOC_DPCM_TRIGGER_POST },
  4515. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4516. .ignore_suspend = 1,
  4517. .id = MSM_FRONTEND_DAI_LSM4,
  4518. SND_SOC_DAILINK_REG(listen4),
  4519. },
  4520. {/* hw:x,19 */
  4521. .name = "Listen 5 Audio Service",
  4522. .stream_name = "Listen 5 Audio Service",
  4523. .dynamic = 1,
  4524. .dpcm_capture = 1,
  4525. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4526. SND_SOC_DPCM_TRIGGER_POST },
  4527. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4528. .ignore_suspend = 1,
  4529. .id = MSM_FRONTEND_DAI_LSM5,
  4530. SND_SOC_DAILINK_REG(listen5),
  4531. },
  4532. {/* hw:x,20 */
  4533. .name = "Listen 6 Audio Service",
  4534. .stream_name = "Listen 6 Audio Service",
  4535. .dynamic = 1,
  4536. .dpcm_capture = 1,
  4537. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4538. SND_SOC_DPCM_TRIGGER_POST },
  4539. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4540. .ignore_suspend = 1,
  4541. .id = MSM_FRONTEND_DAI_LSM6,
  4542. SND_SOC_DAILINK_REG(listen6),
  4543. },
  4544. {/* hw:x,21 */
  4545. .name = "Listen 7 Audio Service",
  4546. .stream_name = "Listen 7 Audio Service",
  4547. .dynamic = 1,
  4548. .dpcm_capture = 1,
  4549. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4550. SND_SOC_DPCM_TRIGGER_POST },
  4551. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4552. .ignore_suspend = 1,
  4553. .id = MSM_FRONTEND_DAI_LSM7,
  4554. SND_SOC_DAILINK_REG(listen7),
  4555. },
  4556. {/* hw:x,22 */
  4557. .name = "Listen 8 Audio Service",
  4558. .stream_name = "Listen 8 Audio Service",
  4559. .dynamic = 1,
  4560. .dpcm_capture = 1,
  4561. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4562. SND_SOC_DPCM_TRIGGER_POST },
  4563. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4564. .ignore_suspend = 1,
  4565. .id = MSM_FRONTEND_DAI_LSM8,
  4566. SND_SOC_DAILINK_REG(listen8),
  4567. },
  4568. {/* hw:x,23 */
  4569. .name = MSM_DAILINK_NAME(Media9),
  4570. .stream_name = "MultiMedia9",
  4571. .dynamic = 1,
  4572. .dpcm_playback = 1,
  4573. .dpcm_capture = 1,
  4574. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4575. SND_SOC_DPCM_TRIGGER_POST},
  4576. .ignore_suspend = 1,
  4577. /* this dainlink has playback support */
  4578. .ignore_pmdown_time = 1,
  4579. .id = MSM_FRONTEND_DAI_MULTIMEDIA9,
  4580. SND_SOC_DAILINK_REG(multimedia9),
  4581. },
  4582. {/* hw:x,24 */
  4583. .name = MSM_DAILINK_NAME(Compress4),
  4584. .stream_name = "Compress4",
  4585. .dynamic = 1,
  4586. .dpcm_playback = 1,
  4587. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4588. SND_SOC_DPCM_TRIGGER_POST},
  4589. .ignore_suspend = 1,
  4590. .ignore_pmdown_time = 1,
  4591. /* this dainlink has playback support */
  4592. .id = MSM_FRONTEND_DAI_MULTIMEDIA11,
  4593. SND_SOC_DAILINK_REG(multimedia11),
  4594. },
  4595. {/* hw:x,25 */
  4596. .name = MSM_DAILINK_NAME(Compress5),
  4597. .stream_name = "Compress5",
  4598. .dynamic = 1,
  4599. .dpcm_playback = 1,
  4600. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4601. SND_SOC_DPCM_TRIGGER_POST},
  4602. .ignore_suspend = 1,
  4603. .ignore_pmdown_time = 1,
  4604. /* this dainlink has playback support */
  4605. .id = MSM_FRONTEND_DAI_MULTIMEDIA12,
  4606. SND_SOC_DAILINK_REG(multimedia12),
  4607. },
  4608. {/* hw:x,26 */
  4609. .name = MSM_DAILINK_NAME(Compress6),
  4610. .stream_name = "Compress6",
  4611. .dynamic = 1,
  4612. .dpcm_playback = 1,
  4613. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4614. SND_SOC_DPCM_TRIGGER_POST},
  4615. .ignore_suspend = 1,
  4616. .ignore_pmdown_time = 1,
  4617. /* this dainlink has playback support */
  4618. .id = MSM_FRONTEND_DAI_MULTIMEDIA13,
  4619. SND_SOC_DAILINK_REG(multimedia13),
  4620. },
  4621. {/* hw:x,27 */
  4622. .name = MSM_DAILINK_NAME(Compress7),
  4623. .stream_name = "Compress7",
  4624. .dynamic = 1,
  4625. .dpcm_playback = 1,
  4626. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4627. SND_SOC_DPCM_TRIGGER_POST},
  4628. .ignore_suspend = 1,
  4629. .ignore_pmdown_time = 1,
  4630. /* this dainlink has playback support */
  4631. .id = MSM_FRONTEND_DAI_MULTIMEDIA14,
  4632. SND_SOC_DAILINK_REG(multimedia14),
  4633. },
  4634. {/* hw:x,28 */
  4635. .name = MSM_DAILINK_NAME(Compress8),
  4636. .stream_name = "Compress8",
  4637. .dynamic = 1,
  4638. .dpcm_playback = 1,
  4639. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4640. SND_SOC_DPCM_TRIGGER_POST},
  4641. .ignore_suspend = 1,
  4642. .ignore_pmdown_time = 1,
  4643. /* this dainlink has playback support */
  4644. .id = MSM_FRONTEND_DAI_MULTIMEDIA15,
  4645. SND_SOC_DAILINK_REG(multimedia15),
  4646. },
  4647. {/* hw:x,29 */
  4648. .name = MSM_DAILINK_NAME(ULL_NOIRQ_2),
  4649. .stream_name = "MM_NOIRQ_2",
  4650. .dynamic = 1,
  4651. .dpcm_playback = 1,
  4652. .dpcm_capture = 1,
  4653. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4654. SND_SOC_DPCM_TRIGGER_POST},
  4655. .ignore_suspend = 1,
  4656. .ignore_pmdown_time = 1,
  4657. /* this dainlink has playback support */
  4658. .id = MSM_FRONTEND_DAI_MULTIMEDIA16,
  4659. .ops = &msm_fe_qos_ops,
  4660. SND_SOC_DAILINK_REG(multimedia16),
  4661. },
  4662. {/* hw:x,30 */
  4663. .name = "CDC_DMA Hostless",
  4664. .stream_name = "CDC_DMA Hostless",
  4665. .dynamic = 1,
  4666. .dpcm_playback = 1,
  4667. .dpcm_capture = 1,
  4668. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4669. SND_SOC_DPCM_TRIGGER_POST},
  4670. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4671. .ignore_suspend = 1,
  4672. /* this dailink has playback support */
  4673. .ignore_pmdown_time = 1,
  4674. SND_SOC_DAILINK_REG(cdcdma_hostless),
  4675. },
  4676. {/* hw:x,31 */
  4677. .name = "TX3_CDC_DMA Hostless",
  4678. .stream_name = "TX3_CDC_DMA Hostless",
  4679. .dynamic = 1,
  4680. .dpcm_capture = 1,
  4681. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4682. SND_SOC_DPCM_TRIGGER_POST},
  4683. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4684. .ignore_suspend = 1,
  4685. SND_SOC_DAILINK_REG(tx3_cdcdma_hostless),
  4686. },
  4687. {/* hw:x,32 */
  4688. .name = "Tertiary MI2S TX_Hostless",
  4689. .stream_name = "Tertiary MI2S_TX Hostless Capture",
  4690. .dynamic = 1,
  4691. .dpcm_capture = 1,
  4692. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4693. SND_SOC_DPCM_TRIGGER_POST},
  4694. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4695. .ignore_suspend = 1,
  4696. .ignore_pmdown_time = 1,
  4697. SND_SOC_DAILINK_REG(tert_mi2s_tx_hostless),
  4698. },
  4699. };
  4700. static struct snd_soc_dai_link msm_common_misc_fe_dai_links[] = {
  4701. {/* hw:x,33 */
  4702. .name = MSM_DAILINK_NAME(ASM Loopback),
  4703. .stream_name = "MultiMedia6",
  4704. .dynamic = 1,
  4705. .dpcm_playback = 1,
  4706. .dpcm_capture = 1,
  4707. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4708. SND_SOC_DPCM_TRIGGER_POST},
  4709. .ignore_suspend = 1,
  4710. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4711. .ignore_pmdown_time = 1,
  4712. .id = MSM_FRONTEND_DAI_MULTIMEDIA6,
  4713. SND_SOC_DAILINK_REG(multimedia6),
  4714. },
  4715. {/* hw:x,34 */
  4716. .name = "USB Audio Hostless",
  4717. .stream_name = "USB Audio Hostless",
  4718. .dynamic = 1,
  4719. .dpcm_playback = 1,
  4720. .dpcm_capture = 1,
  4721. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4722. SND_SOC_DPCM_TRIGGER_POST},
  4723. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4724. .ignore_suspend = 1,
  4725. .ignore_pmdown_time = 1,
  4726. SND_SOC_DAILINK_REG(usbaudio_hostless),
  4727. },
  4728. {/* hw:x,35 */
  4729. .name = "SLIMBUS_7 Hostless",
  4730. .stream_name = "SLIMBUS_7 Hostless",
  4731. .dynamic = 1,
  4732. .dpcm_capture = 1,
  4733. .dpcm_playback = 1,
  4734. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4735. SND_SOC_DPCM_TRIGGER_POST},
  4736. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4737. .ignore_suspend = 1,
  4738. .ignore_pmdown_time = 1,
  4739. SND_SOC_DAILINK_REG(slimbus7_hostless),
  4740. },
  4741. {/* hw:x,36 */
  4742. .name = "Compress Capture",
  4743. .stream_name = "Compress9",
  4744. .dynamic = 1,
  4745. .dpcm_capture = 1,
  4746. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4747. SND_SOC_DPCM_TRIGGER_POST},
  4748. .ignore_suspend = 1,
  4749. .ignore_pmdown_time = 1,
  4750. .id = MSM_FRONTEND_DAI_MULTIMEDIA17,
  4751. SND_SOC_DAILINK_REG(multimedia17),
  4752. },
  4753. {/* hw:x,37 */
  4754. .name = "SLIMBUS_8 Hostless",
  4755. .stream_name = "SLIMBUS_8 Hostless",
  4756. .dynamic = 1,
  4757. .dpcm_capture = 1,
  4758. .dpcm_playback = 1,
  4759. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4760. SND_SOC_DPCM_TRIGGER_POST},
  4761. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4762. .ignore_suspend = 1,
  4763. .ignore_pmdown_time = 1,
  4764. SND_SOC_DAILINK_REG(slimbus8_hostless),
  4765. },
  4766. {/* hw:x,38 */
  4767. .name = LPASS_BE_TX_CDC_DMA_TX_5,
  4768. .stream_name = "TX CDC DMA5 Capture",
  4769. .id = MSM_BACKEND_DAI_TX_CDC_DMA_TX_5,
  4770. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4771. .ignore_suspend = 1,
  4772. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4773. .ops = &msm_cdc_dma_be_ops,
  4774. SND_SOC_DAILINK_REG(tx_cdcdma5_tx),
  4775. },
  4776. {/* hw:x,39 */
  4777. .name = MSM_DAILINK_NAME(Media31),
  4778. .stream_name = "MultiMedia31",
  4779. .dynamic = 1,
  4780. #if IS_ENABLED(CONFIG_AUDIO_QGKI)
  4781. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4782. #endif /* CONFIG_AUDIO_QGKI */
  4783. .dpcm_playback = 1,
  4784. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4785. SND_SOC_DPCM_TRIGGER_POST},
  4786. .ignore_suspend = 1,
  4787. /* this dainlink has playback support */
  4788. .ignore_pmdown_time = 1,
  4789. .id = MSM_FRONTEND_DAI_MULTIMEDIA31,
  4790. SND_SOC_DAILINK_REG(multimedia31),
  4791. },
  4792. {/* hw:x,40 */
  4793. .name = MSM_DAILINK_NAME(Media32),
  4794. .stream_name = "MultiMedia32",
  4795. .dynamic = 1,
  4796. #if IS_ENABLED(CONFIG_AUDIO_QGKI)
  4797. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4798. #endif /* CONFIG_AUDIO_QGKI */
  4799. .dpcm_playback = 1,
  4800. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4801. SND_SOC_DPCM_TRIGGER_POST},
  4802. .ignore_suspend = 1,
  4803. /* this dainlink has playback support */
  4804. .ignore_pmdown_time = 1,
  4805. .id = MSM_FRONTEND_DAI_MULTIMEDIA32,
  4806. SND_SOC_DAILINK_REG(multimedia32),
  4807. },
  4808. {/* hw:x,41 */
  4809. .name = "MSM AFE-PCM TX1",
  4810. .stream_name = "AFE-PROXY TX1",
  4811. .dpcm_capture = 1,
  4812. .ignore_suspend = 1,
  4813. SND_SOC_DAILINK_REG(afepcm_tx1),
  4814. },
  4815. };
  4816. static struct snd_soc_dai_link msm_common_be_dai_links[] = {
  4817. /* Backend AFE DAI Links */
  4818. {
  4819. .name = LPASS_BE_AFE_PCM_RX,
  4820. .stream_name = "AFE Playback",
  4821. .no_pcm = 1,
  4822. .dpcm_playback = 1,
  4823. .id = MSM_BACKEND_DAI_AFE_PCM_RX,
  4824. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4825. /* this dainlink has playback support */
  4826. .ignore_pmdown_time = 1,
  4827. .ignore_suspend = 1,
  4828. SND_SOC_DAILINK_REG(afe_pcm_rx),
  4829. },
  4830. {
  4831. .name = LPASS_BE_AFE_PCM_TX,
  4832. .stream_name = "AFE Capture",
  4833. .no_pcm = 1,
  4834. .dpcm_capture = 1,
  4835. .id = MSM_BACKEND_DAI_AFE_PCM_TX,
  4836. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4837. .ignore_suspend = 1,
  4838. SND_SOC_DAILINK_REG(afe_pcm_tx),
  4839. },
  4840. /* Incall Record Uplink BACK END DAI Link */
  4841. {
  4842. .name = LPASS_BE_INCALL_RECORD_TX,
  4843. .stream_name = "Voice Uplink Capture",
  4844. .no_pcm = 1,
  4845. .dpcm_capture = 1,
  4846. .id = MSM_BACKEND_DAI_INCALL_RECORD_TX,
  4847. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4848. .ignore_suspend = 1,
  4849. SND_SOC_DAILINK_REG(incall_record_tx),
  4850. },
  4851. /* Incall Record Downlink BACK END DAI Link */
  4852. {
  4853. .name = LPASS_BE_INCALL_RECORD_RX,
  4854. .stream_name = "Voice Downlink Capture",
  4855. .no_pcm = 1,
  4856. .dpcm_capture = 1,
  4857. .id = MSM_BACKEND_DAI_INCALL_RECORD_RX,
  4858. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4859. .ignore_suspend = 1,
  4860. SND_SOC_DAILINK_REG(incall_record_rx),
  4861. },
  4862. /* Incall Music BACK END DAI Link */
  4863. {
  4864. .name = LPASS_BE_VOICE_PLAYBACK_TX,
  4865. .stream_name = "Voice Farend Playback",
  4866. .no_pcm = 1,
  4867. .dpcm_playback = 1,
  4868. .id = MSM_BACKEND_DAI_VOICE_PLAYBACK_TX,
  4869. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4870. .ignore_suspend = 1,
  4871. .ignore_pmdown_time = 1,
  4872. SND_SOC_DAILINK_REG(voice_playback_tx),
  4873. },
  4874. /* Incall Music 2 BACK END DAI Link */
  4875. {
  4876. .name = LPASS_BE_VOICE2_PLAYBACK_TX,
  4877. .stream_name = "Voice2 Farend Playback",
  4878. .no_pcm = 1,
  4879. .dpcm_playback = 1,
  4880. .id = MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX,
  4881. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4882. .ignore_suspend = 1,
  4883. .ignore_pmdown_time = 1,
  4884. SND_SOC_DAILINK_REG(voice2_playback_tx),
  4885. },
  4886. /* Proxy Tx BACK END DAI Link */
  4887. {
  4888. .name = LPASS_BE_PROXY_TX,
  4889. .stream_name = "Proxy Capture",
  4890. .no_pcm = 1,
  4891. .dpcm_capture = 1,
  4892. .id = MSM_BACKEND_DAI_PROXY_TX,
  4893. .ignore_suspend = 1,
  4894. SND_SOC_DAILINK_REG(proxy_tx),
  4895. },
  4896. /* Proxy Rx BACK END DAI Link */
  4897. {
  4898. .name = LPASS_BE_PROXY_RX,
  4899. .stream_name = "Proxy Playback",
  4900. .no_pcm = 1,
  4901. .dpcm_playback = 1,
  4902. .id = MSM_BACKEND_DAI_PROXY_RX,
  4903. .ignore_pmdown_time = 1,
  4904. .ignore_suspend = 1,
  4905. SND_SOC_DAILINK_REG(proxy_rx),
  4906. },
  4907. {
  4908. .name = LPASS_BE_USB_AUDIO_RX,
  4909. .stream_name = "USB Audio Playback",
  4910. #if IS_ENABLED(CONFIG_AUDIO_QGKI)
  4911. .dynamic_be = 1,
  4912. #endif /* CONFIG_AUDIO_QGKI */
  4913. .no_pcm = 1,
  4914. .dpcm_playback = 1,
  4915. .id = MSM_BACKEND_DAI_USB_RX,
  4916. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4917. .ignore_pmdown_time = 1,
  4918. .ignore_suspend = 1,
  4919. SND_SOC_DAILINK_REG(usb_audio_rx),
  4920. },
  4921. {
  4922. .name = LPASS_BE_USB_AUDIO_TX,
  4923. .stream_name = "USB Audio Capture",
  4924. .no_pcm = 1,
  4925. .dpcm_capture = 1,
  4926. .id = MSM_BACKEND_DAI_USB_TX,
  4927. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4928. .ignore_suspend = 1,
  4929. SND_SOC_DAILINK_REG(usb_audio_tx),
  4930. },
  4931. {
  4932. .name = LPASS_BE_PRI_TDM_RX_0,
  4933. .stream_name = "Primary TDM0 Playback",
  4934. .no_pcm = 1,
  4935. .dpcm_playback = 1,
  4936. .id = MSM_BACKEND_DAI_PRI_TDM_RX_0,
  4937. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4938. .ops = &holi_tdm_be_ops,
  4939. .ignore_suspend = 1,
  4940. .ignore_pmdown_time = 1,
  4941. SND_SOC_DAILINK_REG(pri_tdm_rx_0),
  4942. },
  4943. {
  4944. .name = LPASS_BE_PRI_TDM_TX_0,
  4945. .stream_name = "Primary TDM0 Capture",
  4946. .no_pcm = 1,
  4947. .dpcm_capture = 1,
  4948. .id = MSM_BACKEND_DAI_PRI_TDM_TX_0,
  4949. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4950. .ops = &holi_tdm_be_ops,
  4951. .ignore_suspend = 1,
  4952. SND_SOC_DAILINK_REG(pri_tdm_tx_0),
  4953. },
  4954. {
  4955. .name = LPASS_BE_SEC_TDM_RX_0,
  4956. .stream_name = "Secondary TDM0 Playback",
  4957. .no_pcm = 1,
  4958. .dpcm_playback = 1,
  4959. .id = MSM_BACKEND_DAI_SEC_TDM_RX_0,
  4960. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4961. .ops = &holi_tdm_be_ops,
  4962. .ignore_suspend = 1,
  4963. .ignore_pmdown_time = 1,
  4964. SND_SOC_DAILINK_REG(sec_tdm_rx_0),
  4965. },
  4966. {
  4967. .name = LPASS_BE_SEC_TDM_TX_0,
  4968. .stream_name = "Secondary TDM0 Capture",
  4969. .no_pcm = 1,
  4970. .dpcm_capture = 1,
  4971. .id = MSM_BACKEND_DAI_SEC_TDM_TX_0,
  4972. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4973. .ops = &holi_tdm_be_ops,
  4974. .ignore_suspend = 1,
  4975. SND_SOC_DAILINK_REG(sec_tdm_tx_0),
  4976. },
  4977. {
  4978. .name = LPASS_BE_TERT_TDM_RX_0,
  4979. .stream_name = "Tertiary TDM0 Playback",
  4980. .no_pcm = 1,
  4981. .dpcm_playback = 1,
  4982. .id = MSM_BACKEND_DAI_TERT_TDM_RX_0,
  4983. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4984. .ops = &holi_tdm_be_ops,
  4985. .ignore_suspend = 1,
  4986. .ignore_pmdown_time = 1,
  4987. SND_SOC_DAILINK_REG(tert_tdm_rx_0),
  4988. },
  4989. {
  4990. .name = LPASS_BE_TERT_TDM_TX_0,
  4991. .stream_name = "Tertiary TDM0 Capture",
  4992. .no_pcm = 1,
  4993. .dpcm_capture = 1,
  4994. .id = MSM_BACKEND_DAI_TERT_TDM_TX_0,
  4995. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4996. .ops = &holi_tdm_be_ops,
  4997. .ignore_suspend = 1,
  4998. SND_SOC_DAILINK_REG(tert_tdm_tx_0),
  4999. },
  5000. {
  5001. .name = LPASS_BE_QUAT_TDM_RX_0,
  5002. .stream_name = "Quaternary TDM0 Playback",
  5003. .no_pcm = 1,
  5004. .dpcm_playback = 1,
  5005. .id = MSM_BACKEND_DAI_QUAT_TDM_RX_0,
  5006. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5007. .ops = &holi_tdm_be_ops,
  5008. .ignore_suspend = 1,
  5009. .ignore_pmdown_time = 1,
  5010. SND_SOC_DAILINK_REG(quat_tdm_rx_0),
  5011. },
  5012. {
  5013. .name = LPASS_BE_QUAT_TDM_TX_0,
  5014. .stream_name = "Quaternary TDM0 Capture",
  5015. .no_pcm = 1,
  5016. .dpcm_capture = 1,
  5017. .id = MSM_BACKEND_DAI_QUAT_TDM_TX_0,
  5018. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5019. .ops = &holi_tdm_be_ops,
  5020. .ignore_suspend = 1,
  5021. SND_SOC_DAILINK_REG(quat_tdm_tx_0),
  5022. },
  5023. };
  5024. static struct snd_soc_dai_link msm_wcn_btfm_be_dai_links[] = {
  5025. {
  5026. .name = LPASS_BE_SLIMBUS_7_RX,
  5027. .stream_name = "Slimbus7 Playback",
  5028. .no_pcm = 1,
  5029. .dpcm_playback = 1,
  5030. .id = MSM_BACKEND_DAI_SLIMBUS_7_RX,
  5031. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5032. .init = &msm_wcn_init_lito,
  5033. .ops = &msm_wcn_ops_lito,
  5034. /* dai link has playback support */
  5035. .ignore_pmdown_time = 1,
  5036. .ignore_suspend = 1,
  5037. SND_SOC_DAILINK_REG(slimbus_7_rx),
  5038. },
  5039. {
  5040. .name = LPASS_BE_SLIMBUS_7_TX,
  5041. .stream_name = "Slimbus7 Capture",
  5042. .no_pcm = 1,
  5043. .dpcm_capture = 1,
  5044. .id = MSM_BACKEND_DAI_SLIMBUS_7_TX,
  5045. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5046. .ops = &msm_wcn_ops_lito,
  5047. .ignore_suspend = 1,
  5048. SND_SOC_DAILINK_REG(slimbus_7_tx),
  5049. },
  5050. {
  5051. .name = LPASS_BE_SLIMBUS_8_TX,
  5052. .stream_name = "Slimbus8 Capture",
  5053. .no_pcm = 1,
  5054. .dpcm_capture = 1,
  5055. .id = MSM_BACKEND_DAI_SLIMBUS_8_TX,
  5056. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5057. .ops = &msm_wcn_ops_lito,
  5058. .ignore_suspend = 1,
  5059. SND_SOC_DAILINK_REG(slimbus_8_tx),
  5060. },
  5061. };
  5062. static struct snd_soc_dai_link msm_mi2s_be_dai_links[] = {
  5063. {
  5064. .name = LPASS_BE_PRI_MI2S_RX,
  5065. .stream_name = "Primary MI2S Playback",
  5066. .no_pcm = 1,
  5067. .dpcm_playback = 1,
  5068. .id = MSM_BACKEND_DAI_PRI_MI2S_RX,
  5069. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5070. .ops = &msm_mi2s_be_ops,
  5071. .ignore_suspend = 1,
  5072. .ignore_pmdown_time = 1,
  5073. SND_SOC_DAILINK_REG(pri_mi2s_rx),
  5074. },
  5075. {
  5076. .name = LPASS_BE_PRI_MI2S_TX,
  5077. .stream_name = "Primary MI2S Capture",
  5078. .no_pcm = 1,
  5079. .dpcm_capture = 1,
  5080. .id = MSM_BACKEND_DAI_PRI_MI2S_TX,
  5081. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5082. .ops = &msm_mi2s_be_ops,
  5083. .ignore_suspend = 1,
  5084. SND_SOC_DAILINK_REG(pri_mi2s_tx),
  5085. },
  5086. {
  5087. .name = LPASS_BE_SEC_MI2S_RX,
  5088. .stream_name = "Secondary MI2S Playback",
  5089. .no_pcm = 1,
  5090. .dpcm_playback = 1,
  5091. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX,
  5092. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5093. .ops = &msm_mi2s_be_ops,
  5094. .ignore_suspend = 1,
  5095. .ignore_pmdown_time = 1,
  5096. SND_SOC_DAILINK_REG(sec_mi2s_rx),
  5097. },
  5098. {
  5099. .name = LPASS_BE_SEC_MI2S_TX,
  5100. .stream_name = "Secondary MI2S Capture",
  5101. .no_pcm = 1,
  5102. .dpcm_capture = 1,
  5103. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_TX,
  5104. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5105. .ops = &msm_mi2s_be_ops,
  5106. .ignore_suspend = 1,
  5107. SND_SOC_DAILINK_REG(sec_mi2s_tx),
  5108. },
  5109. {
  5110. .name = LPASS_BE_TERT_MI2S_RX,
  5111. .stream_name = "Tertiary MI2S Playback",
  5112. .no_pcm = 1,
  5113. .dpcm_playback = 1,
  5114. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_RX,
  5115. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5116. .ops = &msm_mi2s_be_ops,
  5117. .ignore_suspend = 1,
  5118. .ignore_pmdown_time = 1,
  5119. SND_SOC_DAILINK_REG(tert_mi2s_rx),
  5120. },
  5121. {
  5122. .name = LPASS_BE_TERT_MI2S_TX,
  5123. .stream_name = "Tertiary MI2S Capture",
  5124. .no_pcm = 1,
  5125. .dpcm_capture = 1,
  5126. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX,
  5127. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5128. .ops = &msm_mi2s_be_ops,
  5129. .ignore_suspend = 1,
  5130. SND_SOC_DAILINK_REG(tert_mi2s_tx),
  5131. },
  5132. {
  5133. .name = LPASS_BE_QUAT_MI2S_RX,
  5134. .stream_name = "Quaternary MI2S Playback",
  5135. .no_pcm = 1,
  5136. .dpcm_playback = 1,
  5137. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX,
  5138. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5139. .ops = &msm_mi2s_be_ops,
  5140. .ignore_suspend = 1,
  5141. .ignore_pmdown_time = 1,
  5142. SND_SOC_DAILINK_REG(quat_mi2s_rx),
  5143. },
  5144. {
  5145. .name = LPASS_BE_QUAT_MI2S_TX,
  5146. .stream_name = "Quaternary MI2S Capture",
  5147. .no_pcm = 1,
  5148. .dpcm_capture = 1,
  5149. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX,
  5150. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5151. .ops = &msm_mi2s_be_ops,
  5152. .ignore_suspend = 1,
  5153. SND_SOC_DAILINK_REG(quat_mi2s_tx),
  5154. },
  5155. };
  5156. static struct snd_soc_dai_link msm_auxpcm_be_dai_links[] = {
  5157. /* Primary AUX PCM Backend DAI Links */
  5158. {
  5159. .name = LPASS_BE_AUXPCM_RX,
  5160. .stream_name = "AUX PCM Playback",
  5161. .no_pcm = 1,
  5162. .dpcm_playback = 1,
  5163. .id = MSM_BACKEND_DAI_AUXPCM_RX,
  5164. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5165. .ops = &holi_aux_be_ops,
  5166. .ignore_pmdown_time = 1,
  5167. .ignore_suspend = 1,
  5168. SND_SOC_DAILINK_REG(auxpcm_rx),
  5169. },
  5170. {
  5171. .name = LPASS_BE_AUXPCM_TX,
  5172. .stream_name = "AUX PCM Capture",
  5173. .no_pcm = 1,
  5174. .dpcm_capture = 1,
  5175. .id = MSM_BACKEND_DAI_AUXPCM_TX,
  5176. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5177. .ops = &holi_aux_be_ops,
  5178. .ignore_suspend = 1,
  5179. SND_SOC_DAILINK_REG(auxpcm_tx),
  5180. },
  5181. /* Secondary AUX PCM Backend DAI Links */
  5182. {
  5183. .name = LPASS_BE_SEC_AUXPCM_RX,
  5184. .stream_name = "Sec AUX PCM Playback",
  5185. .no_pcm = 1,
  5186. .dpcm_playback = 1,
  5187. .id = MSM_BACKEND_DAI_SEC_AUXPCM_RX,
  5188. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5189. .ops = &holi_aux_be_ops,
  5190. .ignore_pmdown_time = 1,
  5191. .ignore_suspend = 1,
  5192. SND_SOC_DAILINK_REG(sec_auxpcm_rx),
  5193. },
  5194. {
  5195. .name = LPASS_BE_SEC_AUXPCM_TX,
  5196. .stream_name = "Sec AUX PCM Capture",
  5197. .no_pcm = 1,
  5198. .dpcm_capture = 1,
  5199. .id = MSM_BACKEND_DAI_SEC_AUXPCM_TX,
  5200. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5201. .ops = &holi_aux_be_ops,
  5202. .ignore_suspend = 1,
  5203. SND_SOC_DAILINK_REG(sec_auxpcm_tx),
  5204. },
  5205. /* Tertiary AUX PCM Backend DAI Links */
  5206. {
  5207. .name = LPASS_BE_TERT_AUXPCM_RX,
  5208. .stream_name = "Tert AUX PCM Playback",
  5209. .no_pcm = 1,
  5210. .dpcm_playback = 1,
  5211. .id = MSM_BACKEND_DAI_TERT_AUXPCM_RX,
  5212. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5213. .ops = &holi_aux_be_ops,
  5214. .ignore_suspend = 1,
  5215. SND_SOC_DAILINK_REG(tert_auxpcm_rx),
  5216. },
  5217. {
  5218. .name = LPASS_BE_TERT_AUXPCM_TX,
  5219. .stream_name = "Tert AUX PCM Capture",
  5220. .no_pcm = 1,
  5221. .dpcm_capture = 1,
  5222. .id = MSM_BACKEND_DAI_TERT_AUXPCM_TX,
  5223. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5224. .ops = &holi_aux_be_ops,
  5225. .ignore_suspend = 1,
  5226. SND_SOC_DAILINK_REG(tert_auxpcm_tx),
  5227. },
  5228. /* Quaternary AUX PCM Backend DAI Links */
  5229. {
  5230. .name = LPASS_BE_QUAT_AUXPCM_RX,
  5231. .stream_name = "Quat AUX PCM Playback",
  5232. .no_pcm = 1,
  5233. .dpcm_playback = 1,
  5234. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_RX,
  5235. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5236. .ops = &holi_aux_be_ops,
  5237. .ignore_suspend = 1,
  5238. SND_SOC_DAILINK_REG(quat_auxpcm_rx),
  5239. },
  5240. {
  5241. .name = LPASS_BE_QUAT_AUXPCM_TX,
  5242. .stream_name = "Quat AUX PCM Capture",
  5243. .no_pcm = 1,
  5244. .dpcm_capture = 1,
  5245. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_TX,
  5246. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5247. .ops = &holi_aux_be_ops,
  5248. .ignore_suspend = 1,
  5249. SND_SOC_DAILINK_REG(quat_auxpcm_tx),
  5250. },
  5251. };
  5252. static struct snd_soc_dai_link msm_rx_tx_cdc_dma_be_dai_links[] = {
  5253. /* RX CDC DMA Backend DAI Links */
  5254. {
  5255. .name = LPASS_BE_RX_CDC_DMA_RX_0,
  5256. .stream_name = "RX CDC DMA0 Playback",
  5257. #if IS_ENABLED(CONFIG_AUDIO_QGKI)
  5258. .dynamic_be = 1,
  5259. #endif /* CONFIG_AUDIO_QGKI */
  5260. .no_pcm = 1,
  5261. .dpcm_playback = 1,
  5262. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_0,
  5263. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5264. .ignore_pmdown_time = 1,
  5265. .ignore_suspend = 1,
  5266. .ops = &msm_cdc_dma_be_ops,
  5267. SND_SOC_DAILINK_REG(rx_dma_rx0),
  5268. .init = &msm_aux_codec_init,
  5269. },
  5270. {
  5271. .name = LPASS_BE_RX_CDC_DMA_RX_1,
  5272. .stream_name = "RX CDC DMA1 Playback",
  5273. #if IS_ENABLED(CONFIG_AUDIO_QGKI)
  5274. .dynamic_be = 1,
  5275. #endif /* CONFIG_AUDIO_QGKI */
  5276. .no_pcm = 1,
  5277. .dpcm_playback = 1,
  5278. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_1,
  5279. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5280. .ignore_pmdown_time = 1,
  5281. .ignore_suspend = 1,
  5282. .ops = &msm_cdc_dma_be_ops,
  5283. SND_SOC_DAILINK_REG(rx_dma_rx1),
  5284. },
  5285. {
  5286. .name = LPASS_BE_RX_CDC_DMA_RX_2,
  5287. .stream_name = "RX CDC DMA2 Playback",
  5288. #if IS_ENABLED(CONFIG_AUDIO_QGKI)
  5289. .dynamic_be = 1,
  5290. #endif /* CONFIG_AUDIO_QGKI */
  5291. .no_pcm = 1,
  5292. .dpcm_playback = 1,
  5293. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_2,
  5294. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5295. .ignore_pmdown_time = 1,
  5296. .ignore_suspend = 1,
  5297. .ops = &msm_cdc_dma_be_ops,
  5298. SND_SOC_DAILINK_REG(rx_dma_rx2),
  5299. },
  5300. {
  5301. .name = LPASS_BE_RX_CDC_DMA_RX_3,
  5302. .stream_name = "RX CDC DMA3 Playback",
  5303. #if IS_ENABLED(CONFIG_AUDIO_QGKI)
  5304. .dynamic_be = 1,
  5305. #endif /* CONFIG_AUDIO_QGKI */
  5306. .no_pcm = 1,
  5307. .dpcm_playback = 1,
  5308. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_3,
  5309. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5310. .ignore_pmdown_time = 1,
  5311. .ignore_suspend = 1,
  5312. .ops = &msm_cdc_dma_be_ops,
  5313. SND_SOC_DAILINK_REG(rx_dma_rx3),
  5314. },
  5315. /* TX CDC DMA Backend DAI Links */
  5316. {
  5317. .name = LPASS_BE_TX_CDC_DMA_TX_3,
  5318. .stream_name = "TX CDC DMA3 Capture",
  5319. .no_pcm = 1,
  5320. .dpcm_capture = 1,
  5321. .id = MSM_BACKEND_DAI_TX_CDC_DMA_TX_3,
  5322. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5323. .ignore_suspend = 1,
  5324. .ops = &msm_cdc_dma_be_ops,
  5325. SND_SOC_DAILINK_REG(tx_dma_tx3),
  5326. },
  5327. {
  5328. .name = LPASS_BE_TX_CDC_DMA_TX_4,
  5329. .stream_name = "TX CDC DMA4 Capture",
  5330. .no_pcm = 1,
  5331. .dpcm_capture = 1,
  5332. .id = MSM_BACKEND_DAI_TX_CDC_DMA_TX_4,
  5333. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5334. .ignore_suspend = 1,
  5335. .ops = &msm_cdc_dma_be_ops,
  5336. SND_SOC_DAILINK_REG(tx_dma_tx4),
  5337. },
  5338. };
  5339. static struct snd_soc_dai_link msm_va_cdc_dma_be_dai_links[] = {
  5340. {
  5341. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  5342. .stream_name = "VA CDC DMA0 Capture",
  5343. .no_pcm = 1,
  5344. .dpcm_capture = 1,
  5345. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  5346. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5347. .ignore_suspend = 1,
  5348. .ops = &msm_cdc_dma_be_ops,
  5349. SND_SOC_DAILINK_REG(va_dma_tx0),
  5350. .init = &msm_int_audrx_init,
  5351. },
  5352. {
  5353. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  5354. .stream_name = "VA CDC DMA1 Capture",
  5355. .no_pcm = 1,
  5356. .dpcm_capture = 1,
  5357. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  5358. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5359. .ignore_suspend = 1,
  5360. .ops = &msm_cdc_dma_be_ops,
  5361. SND_SOC_DAILINK_REG(va_dma_tx1),
  5362. },
  5363. {
  5364. .name = LPASS_BE_VA_CDC_DMA_TX_2,
  5365. .stream_name = "VA CDC DMA2 Capture",
  5366. .no_pcm = 1,
  5367. .dpcm_capture = 1,
  5368. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_2,
  5369. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5370. .ignore_suspend = 1,
  5371. .ops = &msm_cdc_dma_be_ops,
  5372. SND_SOC_DAILINK_REG(va_dma_tx2),
  5373. },
  5374. };
  5375. static struct snd_soc_dai_link msm_afe_rxtx_lb_be_dai_link[] = {
  5376. {
  5377. .name = LPASS_BE_AFE_LOOPBACK_TX,
  5378. .stream_name = "AFE Loopback Capture",
  5379. .no_pcm = 1,
  5380. .dpcm_capture = 1,
  5381. .id = MSM_BACKEND_DAI_AFE_LOOPBACK_TX,
  5382. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5383. .ignore_pmdown_time = 1,
  5384. .ignore_suspend = 1,
  5385. SND_SOC_DAILINK_REG(afe_loopback_tx),
  5386. },
  5387. };
  5388. static struct snd_soc_dai_link msm_holi_dai_links[
  5389. ARRAY_SIZE(msm_common_dai_links) +
  5390. ARRAY_SIZE(msm_common_misc_fe_dai_links) +
  5391. ARRAY_SIZE(msm_common_be_dai_links) +
  5392. ARRAY_SIZE(msm_mi2s_be_dai_links) +
  5393. ARRAY_SIZE(msm_auxpcm_be_dai_links) +
  5394. ARRAY_SIZE(msm_rx_tx_cdc_dma_be_dai_links) +
  5395. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links) +
  5396. ARRAY_SIZE(msm_afe_rxtx_lb_be_dai_link) +
  5397. ARRAY_SIZE(msm_wcn_btfm_be_dai_links)];
  5398. static int msm_populate_dai_link_component_of_node(
  5399. struct snd_soc_card *card)
  5400. {
  5401. int i, j, index, ret = 0;
  5402. struct device *cdev = card->dev;
  5403. struct snd_soc_dai_link *dai_link = card->dai_link;
  5404. struct device_node *np = NULL;
  5405. int codecs_enabled = 0;
  5406. struct snd_soc_dai_link_component *codecs_comp = NULL;
  5407. if (!cdev) {
  5408. dev_err(cdev, "%s: Sound card device memory NULL\n", __func__);
  5409. return -ENODEV;
  5410. }
  5411. for (i = 0; i < card->num_links; i++) {
  5412. if (dai_link[i].platforms->of_node && dai_link[i].cpus->of_node)
  5413. continue;
  5414. /* populate platform_of_node for snd card dai links */
  5415. if (dai_link[i].platforms->name &&
  5416. !dai_link[i].platforms->of_node) {
  5417. index = of_property_match_string(cdev->of_node,
  5418. "asoc-platform-names",
  5419. dai_link[i].platforms->name);
  5420. if (index < 0) {
  5421. dev_err(cdev, "%s: No match found for platform name: %s\n",
  5422. __func__, dai_link[i].platforms->name);
  5423. ret = index;
  5424. goto err;
  5425. }
  5426. np = of_parse_phandle(cdev->of_node, "asoc-platform",
  5427. index);
  5428. if (!np) {
  5429. dev_err(cdev, "%s: retrieving phandle for platform %s, index %d failed\n",
  5430. __func__, dai_link[i].platforms->name,
  5431. index);
  5432. ret = -ENODEV;
  5433. goto err;
  5434. }
  5435. dai_link[i].platforms->of_node = np;
  5436. dai_link[i].platforms->name = NULL;
  5437. }
  5438. /* populate cpu_of_node for snd card dai links */
  5439. if (dai_link[i].cpus->dai_name && !dai_link[i].cpus->of_node) {
  5440. index = of_property_match_string(cdev->of_node,
  5441. "asoc-cpu-names",
  5442. dai_link[i].cpus->dai_name);
  5443. if (index >= 0) {
  5444. np = of_parse_phandle(cdev->of_node, "asoc-cpu",
  5445. index);
  5446. if (!np) {
  5447. dev_err(cdev, "%s: retrieving phandle for cpu dai %s failed\n",
  5448. __func__,
  5449. dai_link[i].cpus->dai_name);
  5450. ret = -ENODEV;
  5451. goto err;
  5452. }
  5453. dai_link[i].cpus->of_node = np;
  5454. dai_link[i].cpus->dai_name = NULL;
  5455. }
  5456. }
  5457. /* populate codec_of_node for snd card dai links */
  5458. if (dai_link[i].num_codecs > 0) {
  5459. for (j = 0; j < dai_link[i].num_codecs; j++) {
  5460. if (dai_link[i].codecs[j].of_node ||
  5461. !dai_link[i].codecs[j].name)
  5462. continue;
  5463. index = of_property_match_string(cdev->of_node,
  5464. "asoc-codec-names",
  5465. dai_link[i].codecs[j].name);
  5466. if (index < 0)
  5467. continue;
  5468. np = of_parse_phandle(cdev->of_node,
  5469. "asoc-codec",
  5470. index);
  5471. if (!np) {
  5472. dev_err(cdev, "%s: retrieving phandle for codec %s failed\n",
  5473. __func__,
  5474. dai_link[i].codecs[j].name);
  5475. ret = -ENODEV;
  5476. goto err;
  5477. }
  5478. dai_link[i].codecs[j].of_node = np;
  5479. dai_link[i].codecs[j].name = NULL;
  5480. }
  5481. }
  5482. }
  5483. /* In multi-codec scenario, check if codecs are enabled for this platform */
  5484. for (i = 0; i < card->num_links; i++) {
  5485. codecs_enabled = 0;
  5486. if (dai_link[i].num_codecs > 1) {
  5487. for (j = 0; j < dai_link[i].num_codecs; j++) {
  5488. if (!dai_link[i].codecs[j].of_node)
  5489. continue;
  5490. np = dai_link[i].codecs[j].of_node;
  5491. if (!of_device_is_available(np)) {
  5492. dev_err(cdev, "%s: codec is disabled: %s\n",
  5493. __func__,
  5494. np->full_name);
  5495. dai_link[i].codecs[j].of_node = NULL;
  5496. continue;
  5497. }
  5498. codecs_enabled++;
  5499. }
  5500. if (codecs_enabled > 0 &&
  5501. codecs_enabled < dai_link[i].num_codecs) {
  5502. codecs_comp = devm_kzalloc(cdev,
  5503. sizeof(struct snd_soc_dai_link_component)
  5504. * codecs_enabled, GFP_KERNEL);
  5505. if (!codecs_comp) {
  5506. dev_err(cdev, "%s: %s dailink codec component alloc failed\n",
  5507. __func__, dai_link[i].name);
  5508. ret = -ENOMEM;
  5509. goto err;
  5510. }
  5511. index = 0;
  5512. for (j = 0; j < dai_link[i].num_codecs; j++) {
  5513. if (dai_link[i].codecs[j].of_node) {
  5514. codecs_comp[index].of_node =
  5515. dai_link[i].codecs[j].of_node;
  5516. codecs_comp[index].dai_name =
  5517. dai_link[i].codecs[j].dai_name;
  5518. codecs_comp[index].name = NULL;
  5519. index++;
  5520. }
  5521. }
  5522. dai_link[i].codecs = codecs_comp;
  5523. dai_link[i].num_codecs = codecs_enabled;
  5524. }
  5525. }
  5526. }
  5527. err:
  5528. return ret;
  5529. }
  5530. static int msm_audrx_stub_init(struct snd_soc_pcm_runtime *rtd)
  5531. {
  5532. int ret = -EINVAL;
  5533. struct snd_soc_component *component =
  5534. snd_soc_rtdcom_lookup(rtd, "msm-stub-codec");
  5535. if (!component) {
  5536. pr_err("* %s: No match for msm-stub-codec component\n", __func__);
  5537. return ret;
  5538. }
  5539. ret = snd_soc_add_component_controls(component, msm_snd_controls,
  5540. ARRAY_SIZE(msm_snd_controls));
  5541. if (ret < 0) {
  5542. dev_err(component->dev,
  5543. "%s: add_codec_controls failed, err = %d\n",
  5544. __func__, ret);
  5545. return ret;
  5546. }
  5547. return ret;
  5548. }
  5549. static int msm_snd_stub_hw_params(struct snd_pcm_substream *substream,
  5550. struct snd_pcm_hw_params *params)
  5551. {
  5552. return 0;
  5553. }
  5554. static struct snd_soc_ops msm_stub_be_ops = {
  5555. .hw_params = msm_snd_stub_hw_params,
  5556. };
  5557. struct snd_soc_card snd_soc_card_stub_msm = {
  5558. .name = "holi-stub-snd-card",
  5559. };
  5560. static struct snd_soc_dai_link msm_stub_fe_dai_links[] = {
  5561. /* FrontEnd DAI Links */
  5562. {
  5563. .name = "MSMSTUB Media1",
  5564. .stream_name = "MultiMedia1",
  5565. .dynamic = 1,
  5566. #if IS_ENABLED(CONFIG_AUDIO_QGKI)
  5567. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  5568. #endif /* CONFIG_AUDIO_QGKI */
  5569. .dpcm_playback = 1,
  5570. .dpcm_capture = 1,
  5571. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5572. SND_SOC_DPCM_TRIGGER_POST},
  5573. .ignore_suspend = 1,
  5574. /* this dainlink has playback support */
  5575. .ignore_pmdown_time = 1,
  5576. .id = MSM_FRONTEND_DAI_MULTIMEDIA1,
  5577. SND_SOC_DAILINK_REG(multimedia1),
  5578. },
  5579. };
  5580. static struct snd_soc_dai_link msm_stub_be_dai_links[] = {
  5581. /* Backend DAI Links */
  5582. {
  5583. .name = LPASS_BE_AUXPCM_RX,
  5584. .stream_name = "AUX PCM Playback",
  5585. .no_pcm = 1,
  5586. .dpcm_playback = 1,
  5587. .id = MSM_BACKEND_DAI_AUXPCM_RX,
  5588. .init = &msm_audrx_stub_init,
  5589. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5590. .ignore_pmdown_time = 1,
  5591. .ignore_suspend = 1,
  5592. .ops = &msm_stub_be_ops,
  5593. SND_SOC_DAILINK_REG(auxpcm_rx),
  5594. },
  5595. {
  5596. .name = LPASS_BE_AUXPCM_TX,
  5597. .stream_name = "AUX PCM Capture",
  5598. .no_pcm = 1,
  5599. .dpcm_capture = 1,
  5600. .id = MSM_BACKEND_DAI_AUXPCM_TX,
  5601. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5602. .ignore_suspend = 1,
  5603. .ops = &msm_stub_be_ops,
  5604. SND_SOC_DAILINK_REG(auxpcm_tx),
  5605. },
  5606. };
  5607. static struct snd_soc_dai_link msm_stub_dai_links[
  5608. ARRAY_SIZE(msm_stub_fe_dai_links) +
  5609. ARRAY_SIZE(msm_stub_be_dai_links)];
  5610. static const struct of_device_id holi_asoc_machine_of_match[] = {
  5611. { .compatible = "qcom,holi-asoc-snd",
  5612. .data = "codec"},
  5613. { .compatible = "qcom,holi-asoc-snd-stub",
  5614. .data = "stub_codec"},
  5615. {},
  5616. };
  5617. static struct snd_soc_card *populate_snd_card_dailinks(struct device *dev)
  5618. {
  5619. struct snd_soc_card *card = NULL;
  5620. struct snd_soc_dai_link *dailink = NULL;
  5621. int len_1 = 0;
  5622. int len_2 = 0;
  5623. int total_links = 0;
  5624. int rc = 0;
  5625. u32 mi2s_audio_intf = 0;
  5626. u32 auxpcm_audio_intf = 0;
  5627. u32 val = 0;
  5628. u32 wcn_btfm_intf = 0;
  5629. const struct of_device_id *match;
  5630. match = of_match_node(holi_asoc_machine_of_match, dev->of_node);
  5631. if (!match) {
  5632. dev_err(dev, "%s: No DT match found for sound card\n",
  5633. __func__);
  5634. return NULL;
  5635. }
  5636. if (!strcmp(match->data, "codec")) {
  5637. card = &snd_soc_card_holi_msm;
  5638. memcpy(msm_holi_dai_links + total_links,
  5639. msm_common_dai_links,
  5640. sizeof(msm_common_dai_links));
  5641. total_links += ARRAY_SIZE(msm_common_dai_links);
  5642. memcpy(msm_holi_dai_links + total_links,
  5643. msm_common_misc_fe_dai_links,
  5644. sizeof(msm_common_misc_fe_dai_links));
  5645. total_links += ARRAY_SIZE(msm_common_misc_fe_dai_links);
  5646. memcpy(msm_holi_dai_links + total_links,
  5647. msm_common_be_dai_links,
  5648. sizeof(msm_common_be_dai_links));
  5649. total_links += ARRAY_SIZE(msm_common_be_dai_links);
  5650. memcpy(msm_holi_dai_links + total_links,
  5651. msm_rx_tx_cdc_dma_be_dai_links,
  5652. sizeof(msm_rx_tx_cdc_dma_be_dai_links));
  5653. total_links +=
  5654. ARRAY_SIZE(msm_rx_tx_cdc_dma_be_dai_links);
  5655. memcpy(msm_holi_dai_links + total_links,
  5656. msm_va_cdc_dma_be_dai_links,
  5657. sizeof(msm_va_cdc_dma_be_dai_links));
  5658. total_links +=
  5659. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links);
  5660. rc = of_property_read_u32(dev->of_node, "qcom,mi2s-audio-intf",
  5661. &mi2s_audio_intf);
  5662. if (rc) {
  5663. dev_dbg(dev, "%s: No DT match MI2S audio interface\n",
  5664. __func__);
  5665. } else {
  5666. if (mi2s_audio_intf) {
  5667. memcpy(msm_holi_dai_links + total_links,
  5668. msm_mi2s_be_dai_links,
  5669. sizeof(msm_mi2s_be_dai_links));
  5670. total_links +=
  5671. ARRAY_SIZE(msm_mi2s_be_dai_links);
  5672. }
  5673. }
  5674. rc = of_property_read_u32(dev->of_node,
  5675. "qcom,auxpcm-audio-intf",
  5676. &auxpcm_audio_intf);
  5677. if (rc) {
  5678. dev_dbg(dev, "%s: No DT match Aux PCM interface\n",
  5679. __func__);
  5680. } else {
  5681. if (auxpcm_audio_intf) {
  5682. memcpy(msm_holi_dai_links + total_links,
  5683. msm_auxpcm_be_dai_links,
  5684. sizeof(msm_auxpcm_be_dai_links));
  5685. total_links +=
  5686. ARRAY_SIZE(msm_auxpcm_be_dai_links);
  5687. }
  5688. }
  5689. rc = of_property_read_u32(dev->of_node, "qcom,afe-rxtx-lb",
  5690. &val);
  5691. if (!rc && val) {
  5692. memcpy(msm_holi_dai_links + total_links,
  5693. msm_afe_rxtx_lb_be_dai_link,
  5694. sizeof(msm_afe_rxtx_lb_be_dai_link));
  5695. total_links +=
  5696. ARRAY_SIZE(msm_afe_rxtx_lb_be_dai_link);
  5697. }
  5698. rc = of_property_read_u32(dev->of_node, "qcom,wcn-btfm",
  5699. &wcn_btfm_intf);
  5700. if (rc) {
  5701. dev_dbg(dev, "%s: No DT match wcn btfm interface\n",
  5702. __func__);
  5703. } else {
  5704. if (wcn_btfm_intf) {
  5705. memcpy(msm_holi_dai_links + total_links,
  5706. msm_wcn_btfm_be_dai_links,
  5707. sizeof(msm_wcn_btfm_be_dai_links));
  5708. total_links +=
  5709. ARRAY_SIZE(msm_wcn_btfm_be_dai_links);
  5710. }
  5711. }
  5712. dailink = msm_holi_dai_links;
  5713. } else if (!strcmp(match->data, "stub_codec")) {
  5714. card = &snd_soc_card_stub_msm;
  5715. len_1 = ARRAY_SIZE(msm_stub_fe_dai_links);
  5716. len_2 = len_1 + ARRAY_SIZE(msm_stub_be_dai_links);
  5717. memcpy(msm_stub_dai_links,
  5718. msm_stub_fe_dai_links,
  5719. sizeof(msm_stub_fe_dai_links));
  5720. memcpy(msm_stub_dai_links + len_1,
  5721. msm_stub_be_dai_links,
  5722. sizeof(msm_stub_be_dai_links));
  5723. dailink = msm_stub_dai_links;
  5724. total_links = len_2;
  5725. }
  5726. if (card) {
  5727. card->dai_link = dailink;
  5728. card->num_links = total_links;
  5729. }
  5730. return card;
  5731. }
  5732. static int msm_int_audrx_init(struct snd_soc_pcm_runtime *rtd)
  5733. {
  5734. struct snd_soc_component *component = NULL;
  5735. struct snd_soc_dapm_context *dapm = NULL;
  5736. struct snd_card *card = NULL;
  5737. struct snd_info_entry *entry = NULL;
  5738. struct msm_asoc_mach_data *pdata =
  5739. snd_soc_card_get_drvdata(rtd->card);
  5740. int ret = 0;
  5741. component = snd_soc_rtdcom_lookup(rtd, "bolero_codec");
  5742. if (!component) {
  5743. pr_err("%s: could not find component for bolero_codec\n",
  5744. __func__);
  5745. return ret;
  5746. }
  5747. dapm = snd_soc_component_get_dapm(component);
  5748. ret = snd_soc_add_component_controls(component, msm_int_snd_controls,
  5749. ARRAY_SIZE(msm_int_snd_controls));
  5750. if (ret < 0) {
  5751. pr_err("%s: add_component_controls failed: %d\n",
  5752. __func__, ret);
  5753. return ret;
  5754. }
  5755. ret = snd_soc_add_component_controls(component, msm_common_snd_controls,
  5756. ARRAY_SIZE(msm_common_snd_controls));
  5757. if (ret < 0) {
  5758. pr_err("%s: add common snd controls failed: %d\n",
  5759. __func__, ret);
  5760. return ret;
  5761. }
  5762. snd_soc_dapm_new_controls(dapm, msm_int_dapm_widgets,
  5763. ARRAY_SIZE(msm_int_dapm_widgets));
  5764. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic0");
  5765. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic1");
  5766. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic2");
  5767. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic3");
  5768. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic4");
  5769. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic5");
  5770. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic6");
  5771. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic7");
  5772. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic1");
  5773. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic2");
  5774. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic3");
  5775. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic4");
  5776. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic5");
  5777. snd_soc_dapm_sync(dapm);
  5778. card = rtd->card->snd_card;
  5779. if (!pdata->codec_root) {
  5780. entry = msm_snd_info_create_subdir(card->module, "codecs",
  5781. card->proc_root);
  5782. if (!entry) {
  5783. pr_debug("%s: Cannot create codecs module entry\n",
  5784. __func__);
  5785. ret = 0;
  5786. goto err;
  5787. }
  5788. pdata->codec_root = entry;
  5789. }
  5790. bolero_info_create_codec_entry(pdata->codec_root, component);
  5791. bolero_register_wake_irq(component, false);
  5792. codec_reg_done = true;
  5793. err:
  5794. return ret;
  5795. }
  5796. static int msm_aux_codec_init(struct snd_soc_pcm_runtime *rtd)
  5797. {
  5798. struct snd_soc_component *bolero_component = NULL;
  5799. struct snd_soc_component *component = NULL;
  5800. struct snd_soc_dapm_context *dapm = NULL;
  5801. int ret = 0;
  5802. int codec_variant = -1;
  5803. void *mbhc_calibration;
  5804. struct snd_info_entry *entry;
  5805. struct snd_card *card = NULL;
  5806. struct msm_asoc_mach_data *pdata;
  5807. bool is_wcd938x = false;
  5808. pdata = snd_soc_card_get_drvdata(rtd->card);
  5809. if(!pdata)
  5810. return -EINVAL;
  5811. bolero_component = snd_soc_rtdcom_lookup(rtd, "bolero_codec");
  5812. if (!bolero_component) {
  5813. pr_err("%s: could not find component for bolero_codec\n",
  5814. __func__);
  5815. return -EINVAL;
  5816. }
  5817. if (pdata->wcd_disabled) {
  5818. bolero_set_port_map(bolero_component,
  5819. ARRAY_SIZE(sm_port_map), sm_port_map);
  5820. return 0;
  5821. }
  5822. component = snd_soc_rtdcom_lookup(rtd, WCD938X_DRV_NAME);
  5823. if (!component)
  5824. component = snd_soc_rtdcom_lookup(rtd, WCD937X_DRV_NAME);
  5825. else
  5826. is_wcd938x = true;
  5827. if (!component) {
  5828. pr_err("%s component is NULL\n", __func__);
  5829. return -EINVAL;
  5830. }
  5831. dapm = snd_soc_component_get_dapm(component);
  5832. card = component->card->snd_card;
  5833. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  5834. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  5835. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  5836. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  5837. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  5838. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  5839. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  5840. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  5841. snd_soc_dapm_sync(dapm);
  5842. if (!pdata->codec_root) {
  5843. entry = msm_snd_info_create_subdir(card->module, "codecs",
  5844. card->proc_root);
  5845. if (!entry) {
  5846. dev_dbg(component->dev, "%s: Cannot create codecs module entry\n",
  5847. __func__);
  5848. ret = 0;
  5849. goto mbhc_cfg_cal;
  5850. }
  5851. pdata->codec_root = entry;
  5852. }
  5853. if (!strncmp(component->driver->name, WCD937X_DRV_NAME, 13)) {
  5854. wcd937x_info_create_codec_entry(pdata->codec_root, component);
  5855. ret = snd_soc_add_component_controls(component,
  5856. msm_int_wcd937x_snd_controls,
  5857. ARRAY_SIZE(msm_int_wcd937x_snd_controls));
  5858. bolero_set_port_map(bolero_component,
  5859. ARRAY_SIZE(sm_port_map_wcd937x), sm_port_map_wcd937x);
  5860. } else if (!strncmp(component->driver->name, WCD938X_DRV_NAME, 13)) {
  5861. wcd938x_info_create_codec_entry(pdata->codec_root, component);
  5862. codec_variant = wcd938x_get_codec_variant(component);
  5863. dev_dbg(component->dev, "%s: variant %d\n",
  5864. __func__, codec_variant);
  5865. if (codec_variant == WCD9380)
  5866. ret = snd_soc_add_component_controls(component,
  5867. msm_int_wcd9380_snd_controls,
  5868. ARRAY_SIZE(msm_int_wcd9380_snd_controls));
  5869. else if (codec_variant == WCD9385)
  5870. ret = snd_soc_add_component_controls(component,
  5871. msm_int_wcd9385_snd_controls,
  5872. ARRAY_SIZE(msm_int_wcd9385_snd_controls));
  5873. bolero_set_port_map(bolero_component, ARRAY_SIZE(sm_port_map),
  5874. sm_port_map);
  5875. } else {
  5876. bolero_set_port_map(bolero_component, ARRAY_SIZE(sm_port_map),
  5877. sm_port_map);
  5878. }
  5879. if (ret < 0) {
  5880. dev_err(component->dev,
  5881. "%s: add codec specific snd controls failed: %d\n",
  5882. __func__, ret);
  5883. return ret;
  5884. }
  5885. mbhc_cfg_cal:
  5886. mbhc_calibration = def_wcd_mbhc_cal();
  5887. if (!mbhc_calibration)
  5888. return -ENOMEM;
  5889. wcd_mbhc_cfg.calibration = mbhc_calibration;
  5890. if (is_wcd938x)
  5891. ret = wcd938x_mbhc_hs_detect(component, &wcd_mbhc_cfg);
  5892. else
  5893. ret = wcd937x_mbhc_hs_detect(component, &wcd_mbhc_cfg);
  5894. if (ret) {
  5895. dev_err(component->dev, "%s: mbhc hs detect failed, err:%d\n",
  5896. __func__, ret);
  5897. goto err_hs_detect;
  5898. }
  5899. return 0;
  5900. err_hs_detect:
  5901. kfree(mbhc_calibration);
  5902. return ret;
  5903. }
  5904. static void msm_i2s_auxpcm_init(struct platform_device *pdev)
  5905. {
  5906. int count = 0;
  5907. u32 mi2s_master_slave[MI2S_MAX];
  5908. int ret = 0;
  5909. for (count = 0; count < MI2S_MAX; count++) {
  5910. mutex_init(&mi2s_intf_conf[count].lock);
  5911. mi2s_intf_conf[count].ref_cnt = 0;
  5912. }
  5913. ret = of_property_read_u32_array(pdev->dev.of_node,
  5914. "qcom,msm-mi2s-master",
  5915. mi2s_master_slave, MI2S_MAX);
  5916. if (ret) {
  5917. dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-master in DT node\n",
  5918. __func__);
  5919. } else {
  5920. for (count = 0; count < MI2S_MAX; count++) {
  5921. mi2s_intf_conf[count].msm_is_mi2s_master =
  5922. mi2s_master_slave[count];
  5923. }
  5924. }
  5925. }
  5926. static void msm_i2s_auxpcm_deinit(void)
  5927. {
  5928. int count = 0;
  5929. for (count = 0; count < MI2S_MAX; count++) {
  5930. mutex_destroy(&mi2s_intf_conf[count].lock);
  5931. mi2s_intf_conf[count].ref_cnt = 0;
  5932. mi2s_intf_conf[count].msm_is_mi2s_master = 0;
  5933. }
  5934. }
  5935. static int holi_ssr_enable(struct device *dev, void *data)
  5936. {
  5937. struct platform_device *pdev = to_platform_device(dev);
  5938. struct snd_soc_card *card = platform_get_drvdata(pdev);
  5939. int ret = 0;
  5940. if (!card) {
  5941. dev_err(dev, "%s: card is NULL\n", __func__);
  5942. ret = -EINVAL;
  5943. goto err;
  5944. }
  5945. if (!strcmp(card->name, "holi-stub-snd-card")) {
  5946. /* TODO */
  5947. dev_dbg(dev, "%s: TODO \n", __func__);
  5948. }
  5949. #if IS_ENABLED(CONFIG_AUDIO_QGKI)
  5950. snd_soc_card_change_online_state(card, 1);
  5951. #endif /* CONFIG_AUDIO_QGKI */
  5952. dev_dbg(dev, "%s: setting snd_card to ONLINE\n", __func__);
  5953. err:
  5954. return ret;
  5955. }
  5956. static void holi_ssr_disable(struct device *dev, void *data)
  5957. {
  5958. struct platform_device *pdev = to_platform_device(dev);
  5959. struct snd_soc_card *card = platform_get_drvdata(pdev);
  5960. if (!card) {
  5961. dev_err(dev, "%s: card is NULL\n", __func__);
  5962. return;
  5963. }
  5964. dev_dbg(dev, "%s: setting snd_card to OFFLINE\n", __func__);
  5965. #if IS_ENABLED(CONFIG_AUDIO_QGKI)
  5966. snd_soc_card_change_online_state(card, 0);
  5967. #endif /* CONFIG_AUDIO_QGKI */
  5968. if (!strcmp(card->name, "holi-stub-snd-card")) {
  5969. /* TODO */
  5970. dev_dbg(dev, "%s: TODO \n", __func__);
  5971. }
  5972. }
  5973. static const struct snd_event_ops holi_ssr_ops = {
  5974. .enable = holi_ssr_enable,
  5975. .disable = holi_ssr_disable,
  5976. };
  5977. static int msm_audio_ssr_compare(struct device *dev, void *data)
  5978. {
  5979. struct device_node *node = data;
  5980. dev_dbg(dev, "%s: dev->of_node = 0x%p, node = 0x%p\n",
  5981. __func__, dev->of_node, node);
  5982. return (dev->of_node && dev->of_node == node);
  5983. }
  5984. static int msm_audio_ssr_register(struct device *dev)
  5985. {
  5986. struct device_node *np = dev->of_node;
  5987. struct snd_event_clients *ssr_clients = NULL;
  5988. struct device_node *node = NULL;
  5989. int ret = 0;
  5990. int i = 0;
  5991. for (i = 0; ; i++) {
  5992. node = of_parse_phandle(np, "qcom,msm_audio_ssr_devs", i);
  5993. if (!node)
  5994. break;
  5995. snd_event_mstr_add_client(&ssr_clients,
  5996. msm_audio_ssr_compare, node);
  5997. }
  5998. ret = snd_event_master_register(dev, &holi_ssr_ops,
  5999. ssr_clients, NULL);
  6000. if (!ret)
  6001. snd_event_notify(dev, SND_EVENT_UP);
  6002. return ret;
  6003. }
  6004. static int msm_asoc_machine_probe(struct platform_device *pdev)
  6005. {
  6006. struct snd_soc_card *card = NULL;
  6007. struct msm_asoc_mach_data *pdata = NULL;
  6008. const char *mbhc_audio_jack_type = NULL;
  6009. int ret = 0;
  6010. uint index = 0;
  6011. struct clk *lpass_audio_hw_vote = NULL;
  6012. if (!pdev->dev.of_node) {
  6013. dev_err(&pdev->dev,
  6014. "%s: No platform supplied from device tree\n", __func__);
  6015. return -EINVAL;
  6016. }
  6017. pdata = devm_kzalloc(&pdev->dev,
  6018. sizeof(struct msm_asoc_mach_data), GFP_KERNEL);
  6019. if (!pdata)
  6020. return -ENOMEM;
  6021. of_property_read_u32(pdev->dev.of_node,
  6022. "qcom,wcd-disabled",
  6023. &pdata->wcd_disabled);
  6024. card = populate_snd_card_dailinks(&pdev->dev);
  6025. if (!card) {
  6026. dev_err(&pdev->dev, "%s: Card uninitialized\n", __func__);
  6027. ret = -EINVAL;
  6028. goto err;
  6029. }
  6030. card->dev = &pdev->dev;
  6031. platform_set_drvdata(pdev, card);
  6032. snd_soc_card_set_drvdata(card, pdata);
  6033. ret = snd_soc_of_parse_card_name(card, "qcom,model");
  6034. if (ret) {
  6035. dev_err(&pdev->dev, "%s: parse card name failed, err:%d\n",
  6036. __func__, ret);
  6037. goto err;
  6038. }
  6039. ret = snd_soc_of_parse_audio_routing(card, "qcom,audio-routing");
  6040. if (ret) {
  6041. dev_err(&pdev->dev, "%s: parse audio routing failed, err:%d\n",
  6042. __func__, ret);
  6043. goto err;
  6044. }
  6045. ret = msm_populate_dai_link_component_of_node(card);
  6046. if (ret) {
  6047. ret = -EPROBE_DEFER;
  6048. goto err;
  6049. }
  6050. ret = devm_snd_soc_register_card(&pdev->dev, card);
  6051. if (ret == -EPROBE_DEFER) {
  6052. if (codec_reg_done)
  6053. ret = -EINVAL;
  6054. goto err;
  6055. } else if (ret) {
  6056. dev_err(&pdev->dev, "%s: snd_soc_register_card failed (%d)\n",
  6057. __func__, ret);
  6058. goto err;
  6059. }
  6060. dev_info(&pdev->dev, "%s: Sound card %s registered\n",
  6061. __func__, card->name);
  6062. pdata->hph_en1_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6063. "qcom,hph-en1-gpio", 0);
  6064. if (!pdata->hph_en1_gpio_p) {
  6065. dev_dbg(&pdev->dev, "%s: property %s not detected in node %s\n",
  6066. __func__, "qcom,hph-en1-gpio",
  6067. pdev->dev.of_node->full_name);
  6068. }
  6069. pdata->hph_en0_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6070. "qcom,hph-en0-gpio", 0);
  6071. if (!pdata->hph_en0_gpio_p) {
  6072. dev_dbg(&pdev->dev, "%s: property %s not detected in node %s\n",
  6073. __func__, "qcom,hph-en0-gpio",
  6074. pdev->dev.of_node->full_name);
  6075. }
  6076. ret = of_property_read_string(pdev->dev.of_node,
  6077. "qcom,mbhc-audio-jack-type", &mbhc_audio_jack_type);
  6078. if (ret) {
  6079. dev_dbg(&pdev->dev, "%s: Looking up %s property in node %s failed\n",
  6080. __func__, "qcom,mbhc-audio-jack-type",
  6081. pdev->dev.of_node->full_name);
  6082. dev_dbg(&pdev->dev, "Jack type properties set to default\n");
  6083. } else {
  6084. if (!strcmp(mbhc_audio_jack_type, "4-pole-jack")) {
  6085. wcd_mbhc_cfg.enable_anc_mic_detect = false;
  6086. dev_dbg(&pdev->dev, "This hardware has 4 pole jack");
  6087. } else if (!strcmp(mbhc_audio_jack_type, "5-pole-jack")) {
  6088. wcd_mbhc_cfg.enable_anc_mic_detect = true;
  6089. dev_dbg(&pdev->dev, "This hardware has 5 pole jack");
  6090. } else if (!strcmp(mbhc_audio_jack_type, "6-pole-jack")) {
  6091. wcd_mbhc_cfg.enable_anc_mic_detect = true;
  6092. dev_dbg(&pdev->dev, "This hardware has 6 pole jack");
  6093. } else {
  6094. wcd_mbhc_cfg.enable_anc_mic_detect = false;
  6095. dev_dbg(&pdev->dev, "Unknown value, set to default\n");
  6096. }
  6097. }
  6098. /*
  6099. * Parse US-Euro gpio info from DT. Report no error if us-euro
  6100. * entry is not found in DT file as some targets do not support
  6101. * US-Euro detection
  6102. */
  6103. pdata->us_euro_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6104. "qcom,us-euro-gpios", 0);
  6105. if (!pdata->us_euro_gpio_p) {
  6106. dev_dbg(&pdev->dev, "property %s not detected in node %s",
  6107. "qcom,us-euro-gpios", pdev->dev.of_node->full_name);
  6108. } else {
  6109. dev_dbg(&pdev->dev, "%s detected\n",
  6110. "qcom,us-euro-gpios");
  6111. wcd_mbhc_cfg.swap_gnd_mic = msm_swap_gnd_mic;
  6112. }
  6113. if (wcd_mbhc_cfg.enable_usbc_analog)
  6114. wcd_mbhc_cfg.swap_gnd_mic = msm_usbc_swap_gnd_mic;
  6115. pdata->fsa_handle = of_parse_phandle(pdev->dev.of_node,
  6116. "fsa4480-i2c-handle", 0);
  6117. if (!pdata->fsa_handle)
  6118. dev_dbg(&pdev->dev, "property %s not detected in node %s\n",
  6119. "fsa4480-i2c-handle", pdev->dev.of_node->full_name);
  6120. msm_i2s_auxpcm_init(pdev);
  6121. pdata->dmic01_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6122. "qcom,cdc-dmic01-gpios",
  6123. 0);
  6124. pdata->dmic23_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6125. "qcom,cdc-dmic23-gpios",
  6126. 0);
  6127. pdata->dmic45_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6128. "qcom,cdc-dmic45-gpios",
  6129. 0);
  6130. if (pdata->dmic01_gpio_p)
  6131. msm_cdc_pinctrl_set_wakeup_capable(pdata->dmic01_gpio_p, false);
  6132. if (pdata->dmic23_gpio_p)
  6133. msm_cdc_pinctrl_set_wakeup_capable(pdata->dmic23_gpio_p, false);
  6134. if (pdata->dmic45_gpio_p)
  6135. msm_cdc_pinctrl_set_wakeup_capable(pdata->dmic45_gpio_p, false);
  6136. pdata->mi2s_gpio_p[PRIM_MI2S] = of_parse_phandle(pdev->dev.of_node,
  6137. "qcom,pri-mi2s-gpios", 0);
  6138. pdata->mi2s_gpio_p[SEC_MI2S] = of_parse_phandle(pdev->dev.of_node,
  6139. "qcom,sec-mi2s-gpios", 0);
  6140. pdata->mi2s_gpio_p[TERT_MI2S] = of_parse_phandle(pdev->dev.of_node,
  6141. "qcom,tert-mi2s-gpios", 0);
  6142. pdata->mi2s_gpio_p[QUAT_MI2S] = of_parse_phandle(pdev->dev.of_node,
  6143. "qcom,quat-mi2s-gpios", 0);
  6144. for (index = PRIM_MI2S; index < MI2S_MAX; index++)
  6145. atomic_set(&(pdata->mi2s_gpio_ref_count[index]), 0);
  6146. /* Register LPASS audio hw vote */
  6147. lpass_audio_hw_vote = devm_clk_get(&pdev->dev, "lpass_audio_hw_vote");
  6148. if (IS_ERR(lpass_audio_hw_vote)) {
  6149. ret = PTR_ERR(lpass_audio_hw_vote);
  6150. dev_dbg(&pdev->dev, "%s: clk get %s failed %d\n",
  6151. __func__, "lpass_audio_hw_vote", ret);
  6152. lpass_audio_hw_vote = NULL;
  6153. ret = 0;
  6154. }
  6155. pdata->lpass_audio_hw_vote = lpass_audio_hw_vote;
  6156. pdata->core_audio_vote_count = 0;
  6157. ret = msm_audio_ssr_register(&pdev->dev);
  6158. if (ret)
  6159. pr_err("%s: Registration with SND event FWK failed ret = %d\n",
  6160. __func__, ret);
  6161. is_initial_boot = true;
  6162. /* Add QoS request for audio tasks */
  6163. msm_audio_add_qos_request();
  6164. return 0;
  6165. err:
  6166. devm_kfree(&pdev->dev, pdata);
  6167. return ret;
  6168. }
  6169. static int msm_asoc_machine_remove(struct platform_device *pdev)
  6170. {
  6171. struct snd_soc_card *card = platform_get_drvdata(pdev);
  6172. snd_event_master_deregister(&pdev->dev);
  6173. snd_soc_unregister_card(card);
  6174. msm_i2s_auxpcm_deinit();
  6175. msm_audio_remove_qos_request();
  6176. return 0;
  6177. }
  6178. static struct platform_driver holi_asoc_machine_driver = {
  6179. .driver = {
  6180. .name = DRV_NAME,
  6181. .owner = THIS_MODULE,
  6182. .pm = &snd_soc_pm_ops,
  6183. .of_match_table = holi_asoc_machine_of_match,
  6184. .suppress_bind_attrs = true,
  6185. },
  6186. .probe = msm_asoc_machine_probe,
  6187. .remove = msm_asoc_machine_remove,
  6188. };
  6189. module_platform_driver(holi_asoc_machine_driver);
  6190. MODULE_SOFTDEP("pre: bt_fm_slim");
  6191. MODULE_DESCRIPTION("ALSA SoC msm");
  6192. MODULE_LICENSE("GPL v2");
  6193. MODULE_ALIAS("platform:" DRV_NAME);
  6194. MODULE_DEVICE_TABLE(of, holi_asoc_machine_of_match);