wcd937x.c 96 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/slab.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/device.h>
  9. #include <linux/delay.h>
  10. #include <linux/kernel.h>
  11. #include <linux/component.h>
  12. #include <linux/regmap.h>
  13. #include <linux/pm_runtime.h>
  14. #include <sound/soc.h>
  15. #include <sound/tlv.h>
  16. #include <soc/soundwire.h>
  17. #include <sound/soc.h>
  18. #include <sound/soc-dapm.h>
  19. #include <asoc/wcdcal-hwdep.h>
  20. #include <asoc/msm-cdc-pinctrl.h>
  21. #include <dt-bindings/sound/audio-codec-port-types.h>
  22. #include <asoc/msm-cdc-supply.h>
  23. #include "wcd937x-registers.h"
  24. #include "wcd937x.h"
  25. #include "internal.h"
  26. #define WCD9370_VARIANT 0
  27. #define WCD9375_VARIANT 5
  28. #define WCD937X_VARIANT_ENTRY_SIZE 32
  29. #define NUM_SWRS_DT_PARAMS 5
  30. #define WCD937X_VERSION_1_0 1
  31. #define WCD937X_VERSION_ENTRY_SIZE 32
  32. #define EAR_RX_PATH_AUX 1
  33. #define NUM_ATTEMPTS 5
  34. #define WCD937X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  35. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  36. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
  37. SNDRV_PCM_RATE_384000)
  38. /* Fractional Rates */
  39. #define WCD937X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  40. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
  41. #define WCD937X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  42. SNDRV_PCM_FMTBIT_S24_LE |\
  43. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
  44. enum {
  45. CODEC_TX = 0,
  46. CODEC_RX,
  47. };
  48. enum {
  49. ALLOW_BUCK_DISABLE,
  50. HPH_COMP_DELAY,
  51. HPH_PA_DELAY,
  52. AMIC2_BCS_ENABLE,
  53. };
  54. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  55. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  56. static int wcd937x_handle_post_irq(void *data);
  57. static int wcd937x_reset(struct device *dev);
  58. static int wcd937x_reset_low(struct device *dev);
  59. static const struct regmap_irq wcd937x_irqs[WCD937X_NUM_IRQS] = {
  60. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  61. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  62. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  63. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  64. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_SW_DET, 0, 0x10),
  65. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_OCP_INT, 0, 0x20),
  66. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_CNP_INT, 0, 0x40),
  67. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_OCP_INT, 0, 0x80),
  68. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_CNP_INT, 1, 0x01),
  69. REGMAP_IRQ_REG(WCD937X_IRQ_EAR_CNP_INT, 1, 0x02),
  70. REGMAP_IRQ_REG(WCD937X_IRQ_EAR_SCD_INT, 1, 0x04),
  71. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_CNP_INT, 1, 0x08),
  72. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_SCD_INT, 1, 0x10),
  73. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  74. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  75. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  76. REGMAP_IRQ_REG(WCD937X_IRQ_LDORT_SCD_INT, 2, 0x01),
  77. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  78. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  79. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  80. };
  81. static struct regmap_irq_chip wcd937x_regmap_irq_chip = {
  82. .name = "wcd937x",
  83. .irqs = wcd937x_irqs,
  84. .num_irqs = ARRAY_SIZE(wcd937x_irqs),
  85. .num_regs = 3,
  86. .status_base = WCD937X_DIGITAL_INTR_STATUS_0,
  87. .mask_base = WCD937X_DIGITAL_INTR_MASK_0,
  88. .ack_base = WCD937X_DIGITAL_INTR_CLEAR_0,
  89. .use_ack = 1,
  90. #if IS_ENABLED(CONFIG_AUDIO_QGKI)
  91. .clear_ack = 1,
  92. #endif
  93. .type_base = WCD937X_DIGITAL_INTR_LEVEL_0,
  94. .runtime_pm = false,
  95. .handle_post_irq = wcd937x_handle_post_irq,
  96. .irq_drv_data = NULL,
  97. };
  98. static struct snd_soc_dai_driver wcd937x_dai[] = {
  99. {
  100. .name = "wcd937x_cdc",
  101. .playback = {
  102. .stream_name = "WCD937X_AIF Playback",
  103. .rates = WCD937X_RATES | WCD937X_FRAC_RATES,
  104. .formats = WCD937X_FORMATS,
  105. .rate_max = 384000,
  106. .rate_min = 8000,
  107. .channels_min = 1,
  108. .channels_max = 4,
  109. },
  110. .capture = {
  111. .stream_name = "WCD937X_AIF Capture",
  112. .rates = WCD937X_RATES,
  113. .formats = WCD937X_FORMATS,
  114. .rate_max = 192000,
  115. .rate_min = 8000,
  116. .channels_min = 1,
  117. .channels_max = 4,
  118. },
  119. },
  120. };
  121. static int wcd937x_handle_post_irq(void *data)
  122. {
  123. struct wcd937x_priv *wcd937x = data;
  124. u32 status1 = 0, status2 = 0, status3 = 0;
  125. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_0, &status1);
  126. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_1, &status2);
  127. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_2, &status3);
  128. wcd937x->tx_swr_dev->slave_irq_pending =
  129. ((status1 || status2 || status3) ? true : false);
  130. return IRQ_HANDLED;
  131. }
  132. static int wcd937x_init_reg(struct snd_soc_component *component)
  133. {
  134. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  135. 0x0E, 0x0E);
  136. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  137. 0x80, 0x80);
  138. usleep_range(1000, 1010);
  139. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  140. 0x40, 0x40);
  141. usleep_range(1000, 1010);
  142. snd_soc_component_update_bits(component, WCD937X_LDORXTX_CONFIG,
  143. 0x10, 0x00);
  144. snd_soc_component_update_bits(component, WCD937X_BIAS_VBG_FINE_ADJ,
  145. 0xF0, 0x80);
  146. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  147. 0x80, 0x80);
  148. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  149. 0x40, 0x40);
  150. usleep_range(10000, 10010);
  151. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  152. 0x40, 0x00);
  153. snd_soc_component_update_bits(component,
  154. WCD937X_HPH_SURGE_HPHLR_SURGE_EN,
  155. 0xFF, 0xD9);
  156. snd_soc_component_update_bits(component, WCD937X_MICB1_TEST_CTL_1,
  157. 0xFF, 0xFA);
  158. snd_soc_component_update_bits(component, WCD937X_MICB2_TEST_CTL_1,
  159. 0xFF, 0xFA);
  160. snd_soc_component_update_bits(component, WCD937X_MICB3_TEST_CTL_1,
  161. 0xFF, 0xFA);
  162. return 0;
  163. }
  164. static int wcd937x_set_port_params(struct snd_soc_component *component,
  165. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  166. u8 *ch_mask, u32 *ch_rate,
  167. u8 *port_type, u8 path)
  168. {
  169. int i, j;
  170. u8 num_ports = 0;
  171. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT] = NULL;
  172. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  173. switch (path) {
  174. case CODEC_RX:
  175. map = &wcd937x->rx_port_mapping;
  176. num_ports = wcd937x->num_rx_ports;
  177. break;
  178. case CODEC_TX:
  179. map = &wcd937x->tx_port_mapping;
  180. num_ports = wcd937x->num_tx_ports;
  181. break;
  182. default:
  183. dev_err(component->dev, "%s Invalid path selected %u\n",
  184. __func__, path);
  185. return -EINVAL;
  186. }
  187. for (i = 0; i <= num_ports; i++) {
  188. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  189. if ((*map)[i][j].slave_port_type == slv_prt_type)
  190. goto found;
  191. }
  192. }
  193. found:
  194. if (i > num_ports || j == MAX_CH_PER_PORT) {
  195. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  196. __func__, slv_prt_type);
  197. return -EINVAL;
  198. }
  199. *port_id = i;
  200. *num_ch = (*map)[i][j].num_ch;
  201. *ch_mask = (*map)[i][j].ch_mask;
  202. *ch_rate = (*map)[i][j].ch_rate;
  203. *port_type = (*map)[i][j].master_port_type;
  204. return 0;
  205. }
  206. static int wcd937x_parse_port_mapping(struct device *dev,
  207. char *prop, u8 path)
  208. {
  209. u32 *dt_array, map_size, map_length;
  210. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  211. u32 slave_port_type, master_port_type;
  212. u32 i, ch_iter = 0;
  213. int ret = 0;
  214. u8 *num_ports = NULL;
  215. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT] = NULL;
  216. struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
  217. switch (path) {
  218. case CODEC_RX:
  219. map = &wcd937x->rx_port_mapping;
  220. num_ports = &wcd937x->num_rx_ports;
  221. break;
  222. case CODEC_TX:
  223. map = &wcd937x->tx_port_mapping;
  224. num_ports = &wcd937x->num_tx_ports;
  225. break;
  226. default:
  227. dev_err(dev, "%s Invalid path selected %u\n",
  228. __func__, path);
  229. return -EINVAL;
  230. }
  231. if (!of_find_property(dev->of_node, prop,
  232. &map_size)) {
  233. dev_err(dev, "missing port mapping prop %s\n", prop);
  234. ret = -EINVAL;
  235. goto err;
  236. }
  237. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  238. dt_array = kzalloc(map_size, GFP_KERNEL);
  239. if (!dt_array) {
  240. ret = -ENOMEM;
  241. goto err;
  242. }
  243. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  244. NUM_SWRS_DT_PARAMS * map_length);
  245. if (ret) {
  246. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  247. __func__, prop);
  248. ret = -EINVAL;
  249. goto err_pdata_fail;
  250. }
  251. for (i = 0; i < map_length; i++) {
  252. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  253. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  254. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  255. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  256. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  257. if (port_num != old_port_num)
  258. ch_iter = 0;
  259. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  260. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  261. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  262. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  263. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  264. old_port_num = port_num;
  265. }
  266. *num_ports = port_num;
  267. kfree(dt_array);
  268. return 0;
  269. err_pdata_fail:
  270. kfree(dt_array);
  271. err:
  272. return ret;
  273. }
  274. static int wcd937x_tx_connect_port(struct snd_soc_component *component,
  275. u8 slv_port_type, u8 enable)
  276. {
  277. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  278. u8 port_id;
  279. u8 num_ch;
  280. u8 ch_mask;
  281. u32 ch_rate;
  282. u8 ch_type = 0;
  283. int slave_ch_idx;
  284. u8 num_port = 1;
  285. int ret = 0;
  286. ret = wcd937x_set_port_params(component, slv_port_type, &port_id,
  287. &num_ch, &ch_mask, &ch_rate,
  288. &ch_type, CODEC_TX);
  289. if (ret)
  290. return ret;
  291. slave_ch_idx = wcd937x_slave_get_slave_ch_val(slv_port_type);
  292. if (slave_ch_idx != -EINVAL)
  293. ch_type = wcd937x->tx_master_ch_map[slave_ch_idx];
  294. dev_dbg(component->dev, "%s slv_ch_idx: %d, mstr_ch_type: %d\n",
  295. __func__, slave_ch_idx, ch_type);
  296. if (enable)
  297. ret = swr_connect_port(wcd937x->tx_swr_dev, &port_id,
  298. num_port, &ch_mask, &ch_rate,
  299. &num_ch, &ch_type);
  300. else
  301. ret = swr_disconnect_port(wcd937x->tx_swr_dev, &port_id,
  302. num_port, &ch_mask, &ch_type);
  303. return ret;
  304. }
  305. static int wcd937x_rx_connect_port(struct snd_soc_component *component,
  306. u8 slv_port_type, u8 enable)
  307. {
  308. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  309. u8 port_id;
  310. u8 num_ch;
  311. u8 ch_mask;
  312. u32 ch_rate;
  313. u8 port_type;
  314. u8 num_port = 1;
  315. int ret = 0;
  316. ret = wcd937x_set_port_params(component, slv_port_type, &port_id,
  317. &num_ch, &ch_mask, &ch_rate,
  318. &port_type, CODEC_RX);
  319. if (ret)
  320. return ret;
  321. if (enable)
  322. ret = swr_connect_port(wcd937x->rx_swr_dev, &port_id,
  323. num_port, &ch_mask, &ch_rate,
  324. &num_ch, &port_type);
  325. else
  326. ret = swr_disconnect_port(wcd937x->rx_swr_dev, &port_id,
  327. num_port, &ch_mask, &port_type);
  328. return ret;
  329. }
  330. static int wcd937x_rx_clk_enable(struct snd_soc_component *component)
  331. {
  332. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  333. if (wcd937x->rx_clk_cnt == 0) {
  334. snd_soc_component_update_bits(component,
  335. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x08, 0x08);
  336. snd_soc_component_update_bits(component,
  337. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
  338. snd_soc_component_update_bits(component,
  339. WCD937X_ANA_RX_SUPPLIES, 0x01, 0x01);
  340. snd_soc_component_update_bits(component,
  341. WCD937X_DIGITAL_CDC_RX0_CTL, 0x40, 0x00);
  342. snd_soc_component_update_bits(component,
  343. WCD937X_DIGITAL_CDC_RX1_CTL, 0x40, 0x00);
  344. snd_soc_component_update_bits(component,
  345. WCD937X_DIGITAL_CDC_RX2_CTL, 0x40, 0x00);
  346. snd_soc_component_update_bits(component,
  347. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
  348. }
  349. wcd937x->rx_clk_cnt++;
  350. return 0;
  351. }
  352. static int wcd937x_rx_clk_disable(struct snd_soc_component *component)
  353. {
  354. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  355. if (wcd937x->rx_clk_cnt == 0) {
  356. dev_dbg(wcd937x->dev, "%s:clk already disabled\n", __func__);
  357. return 0;
  358. }
  359. wcd937x->rx_clk_cnt--;
  360. if (wcd937x->rx_clk_cnt == 0) {
  361. snd_soc_component_update_bits(component,
  362. WCD937X_ANA_RX_SUPPLIES, 0x01, 0x00);
  363. snd_soc_component_update_bits(component,
  364. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  365. 0x02, 0x00);
  366. snd_soc_component_update_bits(component,
  367. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  368. 0x01, 0x00);
  369. }
  370. return 0;
  371. }
  372. /*
  373. * wcd937x_soc_get_mbhc: get wcd937x_mbhc handle of corresponding component
  374. * @component: handle to snd_soc_component *
  375. *
  376. * return wcd937x_mbhc handle or error code in case of failure
  377. */
  378. struct wcd937x_mbhc *wcd937x_soc_get_mbhc(struct snd_soc_component *component)
  379. {
  380. struct wcd937x_priv *wcd937x;
  381. if (!component) {
  382. pr_err("%s: Invalid params, NULL component\n", __func__);
  383. return NULL;
  384. }
  385. wcd937x = snd_soc_component_get_drvdata(component);
  386. if (!wcd937x) {
  387. pr_err("%s: Invalid params, NULL tavil\n", __func__);
  388. return NULL;
  389. }
  390. return wcd937x->mbhc;
  391. }
  392. EXPORT_SYMBOL(wcd937x_soc_get_mbhc);
  393. static int wcd937x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  394. struct snd_kcontrol *kcontrol,
  395. int event)
  396. {
  397. struct snd_soc_component *component =
  398. snd_soc_dapm_to_component(w->dapm);
  399. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  400. int hph_mode = wcd937x->hph_mode;
  401. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  402. w->name, event);
  403. switch (event) {
  404. case SND_SOC_DAPM_PRE_PMU:
  405. wcd937x_rx_clk_enable(component);
  406. snd_soc_component_update_bits(component,
  407. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  408. 0x01, 0x01);
  409. snd_soc_component_update_bits(component,
  410. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL,
  411. 0x04, 0x04);
  412. snd_soc_component_update_bits(component,
  413. WCD937X_HPH_RDAC_CLK_CTL1,
  414. 0x80, 0x00);
  415. set_bit(HPH_COMP_DELAY, &wcd937x->status_mask);
  416. break;
  417. case SND_SOC_DAPM_POST_PMU:
  418. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  419. snd_soc_component_update_bits(component,
  420. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  421. 0x0F, 0x02);
  422. else if (hph_mode == CLS_H_LOHIFI)
  423. snd_soc_component_update_bits(component,
  424. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  425. 0x0F, 0x06);
  426. if (wcd937x->comp1_enable) {
  427. snd_soc_component_update_bits(component,
  428. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  429. 0x02, 0x02);
  430. snd_soc_component_update_bits(component,
  431. WCD937X_HPH_L_EN, 0x20, 0x00);
  432. if (wcd937x->comp2_enable) {
  433. snd_soc_component_update_bits(component,
  434. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  435. 0x01, 0x01);
  436. snd_soc_component_update_bits(component,
  437. WCD937X_HPH_R_EN, 0x20, 0x00);
  438. }
  439. /*
  440. * 5ms sleep is required after COMP is enabled as per
  441. * HW requirement
  442. */
  443. if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) {
  444. usleep_range(5000, 5100);
  445. clear_bit(HPH_COMP_DELAY,
  446. &wcd937x->status_mask);
  447. }
  448. } else {
  449. snd_soc_component_update_bits(component,
  450. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  451. 0x02, 0x00);
  452. snd_soc_component_update_bits(component,
  453. WCD937X_HPH_L_EN, 0x20, 0x20);
  454. }
  455. snd_soc_component_update_bits(component,
  456. WCD937X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  457. break;
  458. case SND_SOC_DAPM_POST_PMD:
  459. snd_soc_component_update_bits(component,
  460. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  461. 0x0F, 0x01);
  462. break;
  463. }
  464. return 0;
  465. }
  466. static int wcd937x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  467. struct snd_kcontrol *kcontrol,
  468. int event)
  469. {
  470. struct snd_soc_component *component =
  471. snd_soc_dapm_to_component(w->dapm);
  472. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  473. int hph_mode = wcd937x->hph_mode;
  474. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  475. w->name, event);
  476. switch (event) {
  477. case SND_SOC_DAPM_PRE_PMU:
  478. wcd937x_rx_clk_enable(component);
  479. snd_soc_component_update_bits(component,
  480. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
  481. snd_soc_component_update_bits(component,
  482. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL, 0x08, 0x08);
  483. snd_soc_component_update_bits(component,
  484. WCD937X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  485. set_bit(HPH_COMP_DELAY, &wcd937x->status_mask);
  486. break;
  487. case SND_SOC_DAPM_POST_PMU:
  488. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  489. snd_soc_component_update_bits(component,
  490. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  491. 0x0F, 0x02);
  492. else if (hph_mode == CLS_H_LOHIFI)
  493. snd_soc_component_update_bits(component,
  494. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  495. 0x0F, 0x06);
  496. if (wcd937x->comp2_enable) {
  497. snd_soc_component_update_bits(component,
  498. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  499. 0x01, 0x01);
  500. snd_soc_component_update_bits(component,
  501. WCD937X_HPH_R_EN, 0x20, 0x00);
  502. if (wcd937x->comp1_enable) {
  503. snd_soc_component_update_bits(component,
  504. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  505. 0x02, 0x02);
  506. snd_soc_component_update_bits(component,
  507. WCD937X_HPH_L_EN, 0x20, 0x00);
  508. }
  509. /*
  510. * 5ms sleep is required after COMP is enabled as per
  511. * HW requirement
  512. */
  513. if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) {
  514. usleep_range(5000, 5100);
  515. clear_bit(HPH_COMP_DELAY,
  516. &wcd937x->status_mask);
  517. }
  518. } else {
  519. snd_soc_component_update_bits(component,
  520. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  521. 0x01, 0x00);
  522. snd_soc_component_update_bits(component,
  523. WCD937X_HPH_R_EN, 0x20, 0x20);
  524. }
  525. snd_soc_component_update_bits(component,
  526. WCD937X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  527. break;
  528. case SND_SOC_DAPM_POST_PMD:
  529. snd_soc_component_update_bits(component,
  530. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  531. 0x0F, 0x01);
  532. break;
  533. }
  534. return 0;
  535. }
  536. static int wcd937x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  537. struct snd_kcontrol *kcontrol,
  538. int event)
  539. {
  540. struct snd_soc_component *component =
  541. snd_soc_dapm_to_component(w->dapm);
  542. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  543. int hph_mode = wcd937x->hph_mode;
  544. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  545. w->name, event);
  546. switch (event) {
  547. case SND_SOC_DAPM_PRE_PMU:
  548. wcd937x_rx_clk_enable(component);
  549. snd_soc_component_update_bits(component,
  550. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL,
  551. 0x04, 0x04);
  552. snd_soc_component_update_bits(component,
  553. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  554. 0x01, 0x01);
  555. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  556. snd_soc_component_update_bits(component,
  557. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  558. 0x0F, 0x02);
  559. else if (hph_mode == CLS_H_LOHIFI)
  560. snd_soc_component_update_bits(component,
  561. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  562. 0x0F, 0x06);
  563. if (wcd937x->comp1_enable)
  564. snd_soc_component_update_bits(component,
  565. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  566. 0x02, 0x02);
  567. usleep_range(5000, 5010);
  568. snd_soc_component_update_bits(component, WCD937X_FLYBACK_EN,
  569. 0x04, 0x00);
  570. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  571. WCD_CLSH_EVENT_PRE_DAC,
  572. WCD_CLSH_STATE_EAR,
  573. hph_mode);
  574. break;
  575. case SND_SOC_DAPM_POST_PMD:
  576. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_LOHIFI ||
  577. hph_mode == CLS_H_HIFI)
  578. snd_soc_component_update_bits(component,
  579. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  580. 0x0F, 0x01);
  581. if (wcd937x->comp1_enable)
  582. snd_soc_component_update_bits(component,
  583. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  584. 0x02, 0x00);
  585. break;
  586. };
  587. return 0;
  588. }
  589. static int wcd937x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  590. struct snd_kcontrol *kcontrol,
  591. int event)
  592. {
  593. struct snd_soc_component *component =
  594. snd_soc_dapm_to_component(w->dapm);
  595. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  596. int hph_mode = wcd937x->hph_mode;
  597. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  598. w->name, event);
  599. switch (event) {
  600. case SND_SOC_DAPM_PRE_PMU:
  601. wcd937x_rx_clk_enable(component);
  602. snd_soc_component_update_bits(component,
  603. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  604. 0x04, 0x04);
  605. snd_soc_component_update_bits(component,
  606. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  607. 0x04, 0x04);
  608. snd_soc_component_update_bits(component,
  609. WCD937X_DIGITAL_CDC_AUX_GAIN_CTL,
  610. 0x01, 0x01);
  611. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  612. WCD_CLSH_EVENT_PRE_DAC,
  613. WCD_CLSH_STATE_AUX,
  614. hph_mode);
  615. break;
  616. case SND_SOC_DAPM_POST_PMD:
  617. snd_soc_component_update_bits(component,
  618. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  619. 0x04, 0x00);
  620. break;
  621. };
  622. return 0;
  623. }
  624. static int wcd937x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  625. struct snd_kcontrol *kcontrol,
  626. int event)
  627. {
  628. struct snd_soc_component *component =
  629. snd_soc_dapm_to_component(w->dapm);
  630. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  631. int ret = 0;
  632. int hph_mode = wcd937x->hph_mode;
  633. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  634. w->name, event);
  635. switch (event) {
  636. case SND_SOC_DAPM_PRE_PMU:
  637. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  638. wcd937x->rx_swr_dev->dev_num,
  639. true);
  640. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  641. WCD_CLSH_EVENT_PRE_DAC,
  642. WCD_CLSH_STATE_HPHR,
  643. hph_mode);
  644. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  645. 0x10, 0x10);
  646. usleep_range(100, 110);
  647. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  648. snd_soc_component_update_bits(component,
  649. WCD937X_DIGITAL_PDM_WD_CTL1, 0x17, 0x13);
  650. break;
  651. case SND_SOC_DAPM_POST_PMU:
  652. /*
  653. * 7ms sleep is required after PA is enabled as per
  654. * HW requirement. If compander is disabled, then
  655. * 20ms delay is required.
  656. */
  657. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  658. if (!wcd937x->comp2_enable)
  659. usleep_range(20000, 20100);
  660. else
  661. usleep_range(7000, 7100);
  662. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  663. }
  664. snd_soc_component_update_bits(component,
  665. WCD937X_HPH_NEW_INT_HPH_TIMER1,
  666. 0x02, 0x02);
  667. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  668. snd_soc_component_update_bits(component,
  669. WCD937X_ANA_RX_SUPPLIES,
  670. 0x02, 0x02);
  671. if (wcd937x->update_wcd_event)
  672. wcd937x->update_wcd_event(wcd937x->handle,
  673. WCD_BOLERO_EVT_RX_MUTE,
  674. (WCD_RX2 << 0x10));
  675. wcd_enable_irq(&wcd937x->irq_info,
  676. WCD937X_IRQ_HPHR_PDM_WD_INT);
  677. break;
  678. case SND_SOC_DAPM_PRE_PMD:
  679. wcd_disable_irq(&wcd937x->irq_info,
  680. WCD937X_IRQ_HPHR_PDM_WD_INT);
  681. if (wcd937x->update_wcd_event)
  682. wcd937x->update_wcd_event(wcd937x->handle,
  683. WCD_BOLERO_EVT_RX_MUTE,
  684. (WCD_RX2 << 0x10 | 0x1));
  685. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  686. WCD_EVENT_PRE_HPHR_PA_OFF,
  687. &wcd937x->mbhc->wcd_mbhc);
  688. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  689. break;
  690. case SND_SOC_DAPM_POST_PMD:
  691. /*
  692. * 7ms sleep is required after PA is disabled as per
  693. * HW requirement. If compander is disabled, then
  694. * 20ms delay is required.
  695. */
  696. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  697. if (!wcd937x->comp2_enable)
  698. usleep_range(20000, 20100);
  699. else
  700. usleep_range(7000, 7100);
  701. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  702. }
  703. snd_soc_component_update_bits(component,
  704. WCD937X_DIGITAL_PDM_WD_CTL1, 0x17, 0x00);
  705. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  706. WCD_EVENT_POST_HPHR_PA_OFF,
  707. &wcd937x->mbhc->wcd_mbhc);
  708. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  709. 0x10, 0x00);
  710. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  711. WCD_CLSH_EVENT_POST_PA,
  712. WCD_CLSH_STATE_HPHR,
  713. hph_mode);
  714. break;
  715. };
  716. return ret;
  717. }
  718. static int wcd937x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  719. struct snd_kcontrol *kcontrol,
  720. int event)
  721. {
  722. struct snd_soc_component *component =
  723. snd_soc_dapm_to_component(w->dapm);
  724. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  725. int ret = 0;
  726. int hph_mode = wcd937x->hph_mode;
  727. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  728. w->name, event);
  729. switch (event) {
  730. case SND_SOC_DAPM_PRE_PMU:
  731. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  732. wcd937x->rx_swr_dev->dev_num,
  733. true);
  734. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  735. WCD_CLSH_EVENT_PRE_DAC,
  736. WCD_CLSH_STATE_HPHL,
  737. hph_mode);
  738. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  739. 0x20, 0x20);
  740. usleep_range(100, 110);
  741. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  742. snd_soc_component_update_bits(component,
  743. WCD937X_DIGITAL_PDM_WD_CTL0, 0x17, 0x13);
  744. break;
  745. case SND_SOC_DAPM_POST_PMU:
  746. /*
  747. * 7ms sleep is required after PA is enabled as per
  748. * HW requirement. If compander is disabled, then
  749. * 20ms delay is required.
  750. */
  751. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  752. if (!wcd937x->comp1_enable)
  753. usleep_range(20000, 20100);
  754. else
  755. usleep_range(7000, 7100);
  756. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  757. }
  758. snd_soc_component_update_bits(component,
  759. WCD937X_HPH_NEW_INT_HPH_TIMER1,
  760. 0x02, 0x02);
  761. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  762. snd_soc_component_update_bits(component,
  763. WCD937X_ANA_RX_SUPPLIES,
  764. 0x02, 0x02);
  765. if (wcd937x->update_wcd_event)
  766. wcd937x->update_wcd_event(wcd937x->handle,
  767. WCD_BOLERO_EVT_RX_MUTE,
  768. (WCD_RX1 << 0x10));
  769. wcd_enable_irq(&wcd937x->irq_info,
  770. WCD937X_IRQ_HPHL_PDM_WD_INT);
  771. break;
  772. case SND_SOC_DAPM_PRE_PMD:
  773. wcd_disable_irq(&wcd937x->irq_info,
  774. WCD937X_IRQ_HPHL_PDM_WD_INT);
  775. if (wcd937x->update_wcd_event)
  776. wcd937x->update_wcd_event(wcd937x->handle,
  777. WCD_BOLERO_EVT_RX_MUTE,
  778. (WCD_RX1 << 0x10 | 0x1));
  779. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  780. WCD_EVENT_PRE_HPHL_PA_OFF,
  781. &wcd937x->mbhc->wcd_mbhc);
  782. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  783. break;
  784. case SND_SOC_DAPM_POST_PMD:
  785. /*
  786. * 7ms sleep is required after PA is disabled as per
  787. * HW requirement. If compander is disabled, then
  788. * 20ms delay is required.
  789. */
  790. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  791. if (!wcd937x->comp1_enable)
  792. usleep_range(20000, 20100);
  793. else
  794. usleep_range(7000, 7100);
  795. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  796. }
  797. snd_soc_component_update_bits(component,
  798. WCD937X_DIGITAL_PDM_WD_CTL0, 0x17, 0x00);
  799. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  800. WCD_EVENT_POST_HPHL_PA_OFF,
  801. &wcd937x->mbhc->wcd_mbhc);
  802. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  803. 0x20, 0x00);
  804. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  805. WCD_CLSH_EVENT_POST_PA,
  806. WCD_CLSH_STATE_HPHL,
  807. hph_mode);
  808. break;
  809. };
  810. return ret;
  811. }
  812. static int wcd937x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  813. struct snd_kcontrol *kcontrol,
  814. int event)
  815. {
  816. struct snd_soc_component *component =
  817. snd_soc_dapm_to_component(w->dapm);
  818. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  819. int hph_mode = wcd937x->hph_mode;
  820. int ret = 0;
  821. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  822. w->name, event);
  823. switch (event) {
  824. case SND_SOC_DAPM_PRE_PMU:
  825. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  826. wcd937x->rx_swr_dev->dev_num,
  827. true);
  828. snd_soc_component_update_bits(component,
  829. WCD937X_DIGITAL_PDM_WD_CTL2, 0x05, 0x05);
  830. break;
  831. case SND_SOC_DAPM_POST_PMU:
  832. usleep_range(1000, 1010);
  833. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  834. snd_soc_component_update_bits(component,
  835. WCD937X_ANA_RX_SUPPLIES,
  836. 0x02, 0x02);
  837. if (wcd937x->update_wcd_event)
  838. wcd937x->update_wcd_event(wcd937x->handle,
  839. WCD_BOLERO_EVT_RX_MUTE,
  840. (WCD_RX3 << 0x10));
  841. wcd_enable_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT);
  842. break;
  843. case SND_SOC_DAPM_PRE_PMD:
  844. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT);
  845. if (wcd937x->update_wcd_event)
  846. wcd937x->update_wcd_event(wcd937x->handle,
  847. WCD_BOLERO_EVT_RX_MUTE,
  848. (WCD_RX3 << 0x10 | 0x1));
  849. break;
  850. case SND_SOC_DAPM_POST_PMD:
  851. /* Add delay as per hw requirement */
  852. usleep_range(2000, 2010);
  853. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  854. WCD_CLSH_EVENT_POST_PA,
  855. WCD_CLSH_STATE_AUX,
  856. hph_mode);
  857. snd_soc_component_update_bits(component,
  858. WCD937X_DIGITAL_PDM_WD_CTL2, 0x05, 0x00);
  859. break;
  860. };
  861. return ret;
  862. }
  863. static int wcd937x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  864. struct snd_kcontrol *kcontrol,
  865. int event)
  866. {
  867. struct snd_soc_component *component =
  868. snd_soc_dapm_to_component(w->dapm);
  869. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  870. int hph_mode = wcd937x->hph_mode;
  871. int ret = 0;
  872. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  873. w->name, event);
  874. switch (event) {
  875. case SND_SOC_DAPM_PRE_PMU:
  876. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  877. wcd937x->rx_swr_dev->dev_num,
  878. true);
  879. /*
  880. * Enable watchdog interrupt for HPHL or AUX
  881. * depending on mux value
  882. */
  883. wcd937x->ear_rx_path =
  884. snd_soc_component_read32(
  885. component, WCD937X_DIGITAL_CDC_EAR_PATH_CTL);
  886. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  887. snd_soc_component_update_bits(component,
  888. WCD937X_DIGITAL_PDM_WD_CTL2,
  889. 0x05, 0x05);
  890. else
  891. snd_soc_component_update_bits(component,
  892. WCD937X_DIGITAL_PDM_WD_CTL0,
  893. 0x17, 0x13);
  894. if (!wcd937x->comp1_enable)
  895. snd_soc_component_update_bits(component,
  896. WCD937X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  897. break;
  898. case SND_SOC_DAPM_POST_PMU:
  899. usleep_range(6000, 6010);
  900. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  901. snd_soc_component_update_bits(component,
  902. WCD937X_ANA_RX_SUPPLIES,
  903. 0x02, 0x02);
  904. if (wcd937x->update_wcd_event)
  905. wcd937x->update_wcd_event(wcd937x->handle,
  906. WCD_BOLERO_EVT_RX_MUTE,
  907. (WCD_RX1 << 0x10));
  908. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  909. wcd_enable_irq(&wcd937x->irq_info,
  910. WCD937X_IRQ_AUX_PDM_WD_INT);
  911. else
  912. wcd_enable_irq(&wcd937x->irq_info,
  913. WCD937X_IRQ_HPHL_PDM_WD_INT);
  914. break;
  915. case SND_SOC_DAPM_PRE_PMD:
  916. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  917. wcd_disable_irq(&wcd937x->irq_info,
  918. WCD937X_IRQ_AUX_PDM_WD_INT);
  919. else
  920. wcd_disable_irq(&wcd937x->irq_info,
  921. WCD937X_IRQ_HPHL_PDM_WD_INT);
  922. if (wcd937x->update_wcd_event)
  923. wcd937x->update_wcd_event(wcd937x->handle,
  924. WCD_BOLERO_EVT_RX_MUTE,
  925. (WCD_RX1 << 0x10 | 0x1));
  926. break;
  927. case SND_SOC_DAPM_POST_PMD:
  928. if (!wcd937x->comp1_enable)
  929. snd_soc_component_update_bits(component,
  930. WCD937X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  931. usleep_range(7000, 7010);
  932. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  933. WCD_CLSH_EVENT_POST_PA,
  934. WCD_CLSH_STATE_EAR,
  935. hph_mode);
  936. snd_soc_component_update_bits(component, WCD937X_FLYBACK_EN,
  937. 0x04, 0x04);
  938. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  939. snd_soc_component_update_bits(component,
  940. WCD937X_DIGITAL_PDM_WD_CTL2,
  941. 0x05, 0x00);
  942. else
  943. snd_soc_component_update_bits(component,
  944. WCD937X_DIGITAL_PDM_WD_CTL0,
  945. 0x17, 0x00);
  946. break;
  947. };
  948. return ret;
  949. }
  950. static int wcd937x_enable_clsh(struct snd_soc_dapm_widget *w,
  951. struct snd_kcontrol *kcontrol,
  952. int event)
  953. {
  954. struct snd_soc_component *component =
  955. snd_soc_dapm_to_component(w->dapm);
  956. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  957. int mode = wcd937x->hph_mode;
  958. int ret = 0;
  959. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  960. w->name, event);
  961. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  962. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  963. wcd937x_rx_connect_port(component, CLSH,
  964. SND_SOC_DAPM_EVENT_ON(event));
  965. }
  966. if (SND_SOC_DAPM_EVENT_OFF(event))
  967. ret = swr_slvdev_datapath_control(
  968. wcd937x->rx_swr_dev,
  969. wcd937x->rx_swr_dev->dev_num,
  970. false);
  971. return ret;
  972. }
  973. static int wcd937x_enable_rx1(struct snd_soc_dapm_widget *w,
  974. struct snd_kcontrol *kcontrol,
  975. int event)
  976. {
  977. struct snd_soc_component *component =
  978. snd_soc_dapm_to_component(w->dapm);
  979. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  980. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  981. w->name, event);
  982. switch (event) {
  983. case SND_SOC_DAPM_PRE_PMU:
  984. wcd937x_rx_connect_port(component, HPH_L, true);
  985. if (wcd937x->comp1_enable)
  986. wcd937x_rx_connect_port(component, COMP_L, true);
  987. break;
  988. case SND_SOC_DAPM_POST_PMD:
  989. wcd937x_rx_connect_port(component, HPH_L, false);
  990. if (wcd937x->comp1_enable)
  991. wcd937x_rx_connect_port(component, COMP_L, false);
  992. wcd937x_rx_clk_disable(component);
  993. snd_soc_component_update_bits(component,
  994. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  995. 0x01, 0x00);
  996. break;
  997. };
  998. return 0;
  999. }
  1000. static int wcd937x_enable_rx2(struct snd_soc_dapm_widget *w,
  1001. struct snd_kcontrol *kcontrol, int event)
  1002. {
  1003. struct snd_soc_component *component =
  1004. snd_soc_dapm_to_component(w->dapm);
  1005. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1006. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1007. w->name, event);
  1008. switch (event) {
  1009. case SND_SOC_DAPM_PRE_PMU:
  1010. wcd937x_rx_connect_port(component, HPH_R, true);
  1011. if (wcd937x->comp2_enable)
  1012. wcd937x_rx_connect_port(component, COMP_R, true);
  1013. break;
  1014. case SND_SOC_DAPM_POST_PMD:
  1015. wcd937x_rx_connect_port(component, HPH_R, false);
  1016. if (wcd937x->comp2_enable)
  1017. wcd937x_rx_connect_port(component, COMP_R, false);
  1018. wcd937x_rx_clk_disable(component);
  1019. snd_soc_component_update_bits(component,
  1020. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  1021. 0x02, 0x00);
  1022. break;
  1023. };
  1024. return 0;
  1025. }
  1026. static int wcd937x_enable_rx3(struct snd_soc_dapm_widget *w,
  1027. struct snd_kcontrol *kcontrol,
  1028. int event)
  1029. {
  1030. struct snd_soc_component *component =
  1031. snd_soc_dapm_to_component(w->dapm);
  1032. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1033. w->name, event);
  1034. switch (event) {
  1035. case SND_SOC_DAPM_PRE_PMU:
  1036. wcd937x_rx_connect_port(component, LO, true);
  1037. break;
  1038. case SND_SOC_DAPM_POST_PMD:
  1039. wcd937x_rx_connect_port(component, LO, false);
  1040. usleep_range(6000, 6010);
  1041. wcd937x_rx_clk_disable(component);
  1042. snd_soc_component_update_bits(component,
  1043. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  1044. break;
  1045. }
  1046. return 0;
  1047. }
  1048. static int wcd937x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  1049. struct snd_kcontrol *kcontrol,
  1050. int event)
  1051. {
  1052. struct snd_soc_component *component =
  1053. snd_soc_dapm_to_component(w->dapm);
  1054. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1055. u16 dmic_clk_reg;
  1056. s32 *dmic_clk_cnt;
  1057. unsigned int dmic;
  1058. char *wname;
  1059. int ret = 0;
  1060. wname = strpbrk(w->name, "012345");
  1061. if (!wname) {
  1062. dev_err(component->dev, "%s: widget not found\n", __func__);
  1063. return -EINVAL;
  1064. }
  1065. ret = kstrtouint(wname, 10, &dmic);
  1066. if (ret < 0) {
  1067. dev_err(component->dev, "%s: Invalid DMIC line on the codec\n",
  1068. __func__);
  1069. return -EINVAL;
  1070. }
  1071. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1072. w->name, event);
  1073. switch (dmic) {
  1074. case 0:
  1075. case 1:
  1076. dmic_clk_cnt = &(wcd937x->dmic_0_1_clk_cnt);
  1077. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC1_CTL;
  1078. break;
  1079. case 2:
  1080. case 3:
  1081. dmic_clk_cnt = &(wcd937x->dmic_2_3_clk_cnt);
  1082. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC2_CTL;
  1083. break;
  1084. case 4:
  1085. case 5:
  1086. dmic_clk_cnt = &(wcd937x->dmic_4_5_clk_cnt);
  1087. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC3_CTL;
  1088. break;
  1089. default:
  1090. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  1091. __func__);
  1092. return -EINVAL;
  1093. };
  1094. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  1095. __func__, event, dmic, *dmic_clk_cnt);
  1096. switch (event) {
  1097. case SND_SOC_DAPM_PRE_PMU:
  1098. snd_soc_component_update_bits(component,
  1099. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1100. snd_soc_component_update_bits(component,
  1101. dmic_clk_reg, 0x07, 0x02);
  1102. snd_soc_component_update_bits(component,
  1103. dmic_clk_reg, 0x08, 0x08);
  1104. snd_soc_component_update_bits(component,
  1105. dmic_clk_reg, 0x70, 0x20);
  1106. ret = swr_slvdev_datapath_control(wcd937x->tx_swr_dev,
  1107. wcd937x->tx_swr_dev->dev_num,
  1108. true);
  1109. break;
  1110. case SND_SOC_DAPM_POST_PMD:
  1111. wcd937x_tx_connect_port(component, DMIC0 + (w->shift), false);
  1112. break;
  1113. };
  1114. return 0;
  1115. }
  1116. /*
  1117. * wcd937x_get_micb_vout_ctl_val: converts micbias from volts to register value
  1118. * @micb_mv: micbias in mv
  1119. *
  1120. * return register value converted
  1121. */
  1122. int wcd937x_get_micb_vout_ctl_val(u32 micb_mv)
  1123. {
  1124. /* min micbias voltage is 1V and maximum is 2.85V */
  1125. if (micb_mv < 1000 || micb_mv > 2850) {
  1126. pr_err("%s: unsupported micbias voltage\n", __func__);
  1127. return -EINVAL;
  1128. }
  1129. return (micb_mv - 1000) / 50;
  1130. }
  1131. EXPORT_SYMBOL(wcd937x_get_micb_vout_ctl_val);
  1132. /*
  1133. * wcd937x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  1134. * @component: handle to snd_soc_component *
  1135. * @req_volt: micbias voltage to be set
  1136. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  1137. *
  1138. * return 0 if adjustment is success or error code in case of failure
  1139. */
  1140. int wcd937x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  1141. int req_volt, int micb_num)
  1142. {
  1143. struct wcd937x_priv *wcd937x =
  1144. snd_soc_component_get_drvdata(component);
  1145. int cur_vout_ctl, req_vout_ctl;
  1146. int micb_reg, micb_val, micb_en;
  1147. int ret = 0;
  1148. switch (micb_num) {
  1149. case MIC_BIAS_1:
  1150. micb_reg = WCD937X_ANA_MICB1;
  1151. break;
  1152. case MIC_BIAS_2:
  1153. micb_reg = WCD937X_ANA_MICB2;
  1154. break;
  1155. case MIC_BIAS_3:
  1156. micb_reg = WCD937X_ANA_MICB3;
  1157. break;
  1158. default:
  1159. return -EINVAL;
  1160. }
  1161. mutex_lock(&wcd937x->micb_lock);
  1162. /*
  1163. * If requested micbias voltage is same as current micbias
  1164. * voltage, then just return. Otherwise, adjust voltage as
  1165. * per requested value. If micbias is already enabled, then
  1166. * to avoid slow micbias ramp-up or down enable pull-up
  1167. * momentarily, change the micbias value and then re-enable
  1168. * micbias.
  1169. */
  1170. micb_val = snd_soc_component_read32(component, micb_reg);
  1171. micb_en = (micb_val & 0xC0) >> 6;
  1172. cur_vout_ctl = micb_val & 0x3F;
  1173. req_vout_ctl = wcd937x_get_micb_vout_ctl_val(req_volt);
  1174. if (req_vout_ctl < 0) {
  1175. ret = -EINVAL;
  1176. goto exit;
  1177. }
  1178. if (cur_vout_ctl == req_vout_ctl) {
  1179. ret = 0;
  1180. goto exit;
  1181. }
  1182. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  1183. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  1184. req_volt, micb_en);
  1185. if (micb_en == 0x1)
  1186. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  1187. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  1188. if (micb_en == 0x1) {
  1189. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  1190. /*
  1191. * Add 2ms delay as per HW requirement after enabling
  1192. * micbias
  1193. */
  1194. usleep_range(2000, 2100);
  1195. }
  1196. exit:
  1197. mutex_unlock(&wcd937x->micb_lock);
  1198. return ret;
  1199. }
  1200. EXPORT_SYMBOL(wcd937x_mbhc_micb_adjust_voltage);
  1201. static int wcd937x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1202. struct snd_kcontrol *kcontrol,
  1203. int event)
  1204. {
  1205. struct snd_soc_component *component =
  1206. snd_soc_dapm_to_component(w->dapm);
  1207. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1208. int ret = 0;
  1209. switch (event) {
  1210. case SND_SOC_DAPM_PRE_PMU:
  1211. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1212. /* Enable BCS for Headset mic */
  1213. if (w->shift == 1 && !(snd_soc_component_read32(component,
  1214. WCD937X_TX_NEW_TX_CH2_SEL) & 0x80)) {
  1215. wcd937x_tx_connect_port(component, MBHC, true);
  1216. set_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask);
  1217. }
  1218. wcd937x_tx_connect_port(component, ADC1 + (w->shift), true);
  1219. } else {
  1220. wcd937x_tx_connect_port(component, DMIC0 + (w->shift), true);
  1221. }
  1222. break;
  1223. case SND_SOC_DAPM_POST_PMD:
  1224. ret = swr_slvdev_datapath_control(wcd937x->tx_swr_dev,
  1225. wcd937x->tx_swr_dev->dev_num,
  1226. false);
  1227. break;
  1228. };
  1229. return ret;
  1230. }
  1231. static int wcd937x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  1232. struct snd_kcontrol *kcontrol,
  1233. int event){
  1234. struct snd_soc_component *component =
  1235. snd_soc_dapm_to_component(w->dapm);
  1236. struct wcd937x_priv *wcd937x =
  1237. snd_soc_component_get_drvdata(component);
  1238. int ret = 0;
  1239. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1240. w->name, event);
  1241. switch (event) {
  1242. case SND_SOC_DAPM_PRE_PMU:
  1243. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1244. wcd937x->ana_clk_count++;
  1245. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1246. snd_soc_component_update_bits(component,
  1247. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1248. snd_soc_component_update_bits(component,
  1249. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x08);
  1250. snd_soc_component_update_bits(component,
  1251. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1252. ret = swr_slvdev_datapath_control(wcd937x->tx_swr_dev,
  1253. wcd937x->tx_swr_dev->dev_num,
  1254. true);
  1255. break;
  1256. case SND_SOC_DAPM_POST_PMD:
  1257. wcd937x_tx_connect_port(component, ADC1 + (w->shift), false);
  1258. if (w->shift == 1 &&
  1259. test_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask)) {
  1260. wcd937x_tx_connect_port(component, MBHC, false);
  1261. clear_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask);
  1262. }
  1263. snd_soc_component_update_bits(component,
  1264. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x00);
  1265. break;
  1266. };
  1267. return ret;
  1268. }
  1269. static int wcd937x_enable_req(struct snd_soc_dapm_widget *w,
  1270. struct snd_kcontrol *kcontrol, int event)
  1271. {
  1272. struct snd_soc_component *component =
  1273. snd_soc_dapm_to_component(w->dapm);
  1274. struct wcd937x_priv *wcd937x =
  1275. snd_soc_component_get_drvdata(component);
  1276. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1277. w->name, event);
  1278. switch (event) {
  1279. case SND_SOC_DAPM_PRE_PMU:
  1280. snd_soc_component_update_bits(component,
  1281. WCD937X_DIGITAL_CDC_REQ_CTL, 0x02, 0x02);
  1282. snd_soc_component_update_bits(component,
  1283. WCD937X_DIGITAL_CDC_REQ_CTL, 0x01, 0x00);
  1284. snd_soc_component_update_bits(component,
  1285. WCD937X_ANA_TX_CH2, 0x40, 0x40);
  1286. snd_soc_component_update_bits(component,
  1287. WCD937X_ANA_TX_CH3_HPF, 0x40, 0x40);
  1288. snd_soc_component_update_bits(component,
  1289. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x70, 0x70);
  1290. snd_soc_component_update_bits(component,
  1291. WCD937X_ANA_TX_CH1, 0x80, 0x80);
  1292. snd_soc_component_update_bits(component,
  1293. WCD937X_ANA_TX_CH2, 0x40, 0x00);
  1294. snd_soc_component_update_bits(component,
  1295. WCD937X_ANA_TX_CH2, 0x80, 0x80);
  1296. snd_soc_component_update_bits(component,
  1297. WCD937X_ANA_TX_CH3, 0x80, 0x80);
  1298. break;
  1299. case SND_SOC_DAPM_POST_PMD:
  1300. snd_soc_component_update_bits(component,
  1301. WCD937X_ANA_TX_CH1, 0x80, 0x00);
  1302. snd_soc_component_update_bits(component,
  1303. WCD937X_ANA_TX_CH2, 0x80, 0x00);
  1304. snd_soc_component_update_bits(component,
  1305. WCD937X_ANA_TX_CH3, 0x80, 0x00);
  1306. snd_soc_component_update_bits(component,
  1307. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x00);
  1308. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1309. wcd937x->ana_clk_count--;
  1310. if (wcd937x->ana_clk_count <= 0) {
  1311. snd_soc_component_update_bits(component,
  1312. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
  1313. wcd937x->ana_clk_count = 0;
  1314. }
  1315. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1316. snd_soc_component_update_bits(component,
  1317. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00);
  1318. break;
  1319. };
  1320. return 0;
  1321. }
  1322. int wcd937x_micbias_control(struct snd_soc_component *component,
  1323. int micb_num, int req, bool is_dapm)
  1324. {
  1325. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1326. int micb_index = micb_num - 1;
  1327. u16 micb_reg;
  1328. int pre_off_event = 0, post_off_event = 0;
  1329. int post_on_event = 0, post_dapm_off = 0;
  1330. int post_dapm_on = 0;
  1331. if ((micb_index < 0) || (micb_index > WCD937X_MAX_MICBIAS - 1)) {
  1332. dev_err(component->dev, "%s: Invalid micbias index, micb_ind:%d\n",
  1333. __func__, micb_index);
  1334. return -EINVAL;
  1335. }
  1336. switch (micb_num) {
  1337. case MIC_BIAS_1:
  1338. micb_reg = WCD937X_ANA_MICB1;
  1339. break;
  1340. case MIC_BIAS_2:
  1341. micb_reg = WCD937X_ANA_MICB2;
  1342. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1343. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1344. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1345. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1346. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1347. break;
  1348. case MIC_BIAS_3:
  1349. micb_reg = WCD937X_ANA_MICB3;
  1350. break;
  1351. default:
  1352. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1353. __func__, micb_num);
  1354. return -EINVAL;
  1355. };
  1356. mutex_lock(&wcd937x->micb_lock);
  1357. switch (req) {
  1358. case MICB_PULLUP_ENABLE:
  1359. wcd937x->pullup_ref[micb_index]++;
  1360. if ((wcd937x->pullup_ref[micb_index] == 1) &&
  1361. (wcd937x->micb_ref[micb_index] == 0))
  1362. snd_soc_component_update_bits(component, micb_reg,
  1363. 0xC0, 0x80);
  1364. break;
  1365. case MICB_PULLUP_DISABLE:
  1366. if (wcd937x->pullup_ref[micb_index] > 0)
  1367. wcd937x->pullup_ref[micb_index]--;
  1368. if ((wcd937x->pullup_ref[micb_index] == 0) &&
  1369. (wcd937x->micb_ref[micb_index] == 0))
  1370. snd_soc_component_update_bits(component, micb_reg,
  1371. 0xC0, 0x00);
  1372. break;
  1373. case MICB_ENABLE:
  1374. wcd937x->micb_ref[micb_index]++;
  1375. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1376. wcd937x->ana_clk_count++;
  1377. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1378. if (wcd937x->micb_ref[micb_index] == 1) {
  1379. snd_soc_component_update_bits(component,
  1380. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0xF0, 0xF0);
  1381. snd_soc_component_update_bits(component,
  1382. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1383. snd_soc_component_update_bits(component,
  1384. WCD937X_MICB1_TEST_CTL_2, 0x01, 0x01);
  1385. snd_soc_component_update_bits(component,
  1386. WCD937X_MICB2_TEST_CTL_2, 0x01, 0x01);
  1387. snd_soc_component_update_bits(component,
  1388. WCD937X_MICB3_TEST_CTL_2, 0x01, 0x01);
  1389. snd_soc_component_update_bits(component,
  1390. micb_reg, 0xC0, 0x40);
  1391. if (post_on_event)
  1392. blocking_notifier_call_chain(
  1393. &wcd937x->mbhc->notifier, post_on_event,
  1394. &wcd937x->mbhc->wcd_mbhc);
  1395. }
  1396. if (is_dapm && post_dapm_on && wcd937x->mbhc)
  1397. blocking_notifier_call_chain(
  1398. &wcd937x->mbhc->notifier, post_dapm_on,
  1399. &wcd937x->mbhc->wcd_mbhc);
  1400. break;
  1401. case MICB_DISABLE:
  1402. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1403. wcd937x->ana_clk_count--;
  1404. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1405. if (wcd937x->micb_ref[micb_index] > 0)
  1406. wcd937x->micb_ref[micb_index]--;
  1407. if ((wcd937x->micb_ref[micb_index] == 0) &&
  1408. (wcd937x->pullup_ref[micb_index] > 0))
  1409. snd_soc_component_update_bits(component, micb_reg,
  1410. 0xC0, 0x80);
  1411. else if ((wcd937x->micb_ref[micb_index] == 0) &&
  1412. (wcd937x->pullup_ref[micb_index] == 0)) {
  1413. if (pre_off_event && wcd937x->mbhc)
  1414. blocking_notifier_call_chain(
  1415. &wcd937x->mbhc->notifier, pre_off_event,
  1416. &wcd937x->mbhc->wcd_mbhc);
  1417. snd_soc_component_update_bits(component, micb_reg,
  1418. 0xC0, 0x00);
  1419. if (post_off_event && wcd937x->mbhc)
  1420. blocking_notifier_call_chain(
  1421. &wcd937x->mbhc->notifier,
  1422. post_off_event,
  1423. &wcd937x->mbhc->wcd_mbhc);
  1424. }
  1425. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1426. if (wcd937x->ana_clk_count <= 0) {
  1427. snd_soc_component_update_bits(component,
  1428. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  1429. 0x10, 0x00);
  1430. wcd937x->ana_clk_count = 0;
  1431. }
  1432. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1433. if (is_dapm && post_dapm_off && wcd937x->mbhc)
  1434. blocking_notifier_call_chain(
  1435. &wcd937x->mbhc->notifier, post_dapm_off,
  1436. &wcd937x->mbhc->wcd_mbhc);
  1437. break;
  1438. };
  1439. dev_dbg(component->dev, "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1440. __func__, micb_num, wcd937x->micb_ref[micb_index],
  1441. wcd937x->pullup_ref[micb_index]);
  1442. mutex_unlock(&wcd937x->micb_lock);
  1443. return 0;
  1444. }
  1445. EXPORT_SYMBOL(wcd937x_micbias_control);
  1446. void wcd937x_disable_bcs_before_slow_insert(struct snd_soc_component *component,
  1447. bool bcs_disable)
  1448. {
  1449. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1450. if (wcd937x->update_wcd_event) {
  1451. if (bcs_disable)
  1452. wcd937x->update_wcd_event(wcd937x->handle,
  1453. WCD_BOLERO_EVT_BCS_CLK_OFF, 0);
  1454. else
  1455. wcd937x->update_wcd_event(wcd937x->handle,
  1456. WCD_BOLERO_EVT_BCS_CLK_OFF, 1);
  1457. }
  1458. }
  1459. static int wcd937x_get_logical_addr(struct swr_device *swr_dev)
  1460. {
  1461. int ret = 0;
  1462. uint8_t devnum = 0;
  1463. int num_retry = NUM_ATTEMPTS;
  1464. do {
  1465. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1466. if (ret) {
  1467. dev_err(&swr_dev->dev,
  1468. "%s get devnum %d for dev addr %lx failed\n",
  1469. __func__, devnum, swr_dev->addr);
  1470. /* retry after 1ms */
  1471. usleep_range(1000, 1010);
  1472. }
  1473. } while (ret && --num_retry);
  1474. swr_dev->dev_num = devnum;
  1475. return 0;
  1476. }
  1477. static bool get_usbc_hs_status(struct snd_soc_component *component,
  1478. struct wcd_mbhc_config *mbhc_cfg)
  1479. {
  1480. if (mbhc_cfg->enable_usbc_analog) {
  1481. if (!(snd_soc_component_read32(component, WCD937X_ANA_MBHC_MECH)
  1482. & 0x20))
  1483. return true;
  1484. }
  1485. return false;
  1486. }
  1487. static int wcd937x_event_notify(struct notifier_block *block,
  1488. unsigned long val,
  1489. void *data)
  1490. {
  1491. u16 event = (val & 0xffff);
  1492. u16 amic = (val >> 0x10);
  1493. u16 mask = 0x40, reg = 0x0;
  1494. int ret = 0;
  1495. struct wcd937x_priv *wcd937x = dev_get_drvdata((struct device *)data);
  1496. struct snd_soc_component *component = wcd937x->component;
  1497. struct wcd_mbhc *mbhc;
  1498. switch (event) {
  1499. case BOLERO_WCD_EVT_TX_CH_HOLD_CLEAR:
  1500. if (amic == 0x1 || amic == 0x2)
  1501. reg = WCD937X_ANA_TX_CH2;
  1502. else if (amic == 0x3)
  1503. reg = WCD937X_ANA_TX_CH3_HPF;
  1504. else
  1505. return 0;
  1506. if (amic == 0x2)
  1507. mask = 0x20;
  1508. snd_soc_component_update_bits(component, reg, mask, 0x00);
  1509. break;
  1510. case BOLERO_WCD_EVT_PA_OFF_PRE_SSR:
  1511. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  1512. 0xC0, 0x00);
  1513. snd_soc_component_update_bits(component, WCD937X_ANA_EAR,
  1514. 0x80, 0x00);
  1515. snd_soc_component_update_bits(component, WCD937X_AUX_AUXPA,
  1516. 0x80, 0x00);
  1517. break;
  1518. case BOLERO_WCD_EVT_SSR_DOWN:
  1519. wcd937x->mbhc->wcd_mbhc.deinit_in_progress = true;
  1520. mbhc = &wcd937x->mbhc->wcd_mbhc;
  1521. wcd937x->usbc_hs_status = get_usbc_hs_status(component,
  1522. mbhc->mbhc_cfg);
  1523. wcd937x_mbhc_ssr_down(wcd937x->mbhc, component);
  1524. wcd937x_reset_low(wcd937x->dev);
  1525. break;
  1526. case BOLERO_WCD_EVT_SSR_UP:
  1527. wcd937x_reset(wcd937x->dev);
  1528. /* allow reset to take effect */
  1529. usleep_range(10000, 10010);
  1530. wcd937x_get_logical_addr(wcd937x->tx_swr_dev);
  1531. wcd937x_get_logical_addr(wcd937x->rx_swr_dev);
  1532. wcd937x_init_reg(component);
  1533. regcache_mark_dirty(wcd937x->regmap);
  1534. regcache_sync(wcd937x->regmap);
  1535. /* Initialize MBHC module */
  1536. mbhc = &wcd937x->mbhc->wcd_mbhc;
  1537. ret = wcd937x_mbhc_post_ssr_init(wcd937x->mbhc, component);
  1538. if (ret) {
  1539. dev_err(component->dev, "%s: mbhc initialization failed\n",
  1540. __func__);
  1541. } else {
  1542. wcd937x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  1543. if (wcd937x->usbc_hs_status)
  1544. mdelay(500);
  1545. }
  1546. wcd937x->mbhc->wcd_mbhc.deinit_in_progress = false;
  1547. break;
  1548. default:
  1549. dev_err(component->dev, "%s: invalid event %d\n", __func__,
  1550. event);
  1551. break;
  1552. }
  1553. return 0;
  1554. }
  1555. static int __wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1556. int event)
  1557. {
  1558. struct snd_soc_component *component =
  1559. snd_soc_dapm_to_component(w->dapm);
  1560. int micb_num;
  1561. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1562. __func__, w->name, event);
  1563. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  1564. micb_num = MIC_BIAS_1;
  1565. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  1566. micb_num = MIC_BIAS_2;
  1567. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  1568. micb_num = MIC_BIAS_3;
  1569. else
  1570. return -EINVAL;
  1571. switch (event) {
  1572. case SND_SOC_DAPM_PRE_PMU:
  1573. wcd937x_micbias_control(component, micb_num,
  1574. MICB_ENABLE, true);
  1575. break;
  1576. case SND_SOC_DAPM_POST_PMU:
  1577. usleep_range(1000, 1100);
  1578. break;
  1579. case SND_SOC_DAPM_POST_PMD:
  1580. wcd937x_micbias_control(component, micb_num,
  1581. MICB_DISABLE, true);
  1582. break;
  1583. };
  1584. return 0;
  1585. }
  1586. static int wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1587. struct snd_kcontrol *kcontrol,
  1588. int event)
  1589. {
  1590. return __wcd937x_codec_enable_micbias(w, event);
  1591. }
  1592. static int __wcd937x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1593. int event)
  1594. {
  1595. struct snd_soc_component *component =
  1596. snd_soc_dapm_to_component(w->dapm);
  1597. int micb_num;
  1598. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1599. __func__, w->name, event);
  1600. if (strnstr(w->name, "VA MIC BIAS1", sizeof("VA MIC BIAS1")))
  1601. micb_num = MIC_BIAS_1;
  1602. else if (strnstr(w->name, "VA MIC BIAS2", sizeof("VA MIC BIAS2")))
  1603. micb_num = MIC_BIAS_2;
  1604. else if (strnstr(w->name, "VA MIC BIAS3", sizeof("VA MIC BIAS3")))
  1605. micb_num = MIC_BIAS_3;
  1606. else
  1607. return -EINVAL;
  1608. switch (event) {
  1609. case SND_SOC_DAPM_PRE_PMU:
  1610. wcd937x_micbias_control(component, micb_num,
  1611. MICB_PULLUP_ENABLE, true);
  1612. break;
  1613. case SND_SOC_DAPM_POST_PMU:
  1614. /* 1 msec delay as per HW requirement */
  1615. usleep_range(1000, 1100);
  1616. break;
  1617. case SND_SOC_DAPM_POST_PMD:
  1618. wcd937x_micbias_control(component, micb_num,
  1619. MICB_PULLUP_DISABLE, true);
  1620. break;
  1621. };
  1622. return 0;
  1623. }
  1624. static int wcd937x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1625. struct snd_kcontrol *kcontrol,
  1626. int event)
  1627. {
  1628. return __wcd937x_codec_enable_micbias_pullup(w, event);
  1629. }
  1630. static int wcd937x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  1631. struct snd_ctl_elem_value *ucontrol)
  1632. {
  1633. struct snd_soc_component *component =
  1634. snd_soc_kcontrol_component(kcontrol);
  1635. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1636. ucontrol->value.integer.value[0] = wcd937x->hph_mode;
  1637. return 0;
  1638. }
  1639. static int wcd937x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  1640. struct snd_ctl_elem_value *ucontrol)
  1641. {
  1642. struct snd_soc_component *component =
  1643. snd_soc_kcontrol_component(kcontrol);
  1644. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1645. u32 mode_val;
  1646. mode_val = ucontrol->value.enumerated.item[0];
  1647. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  1648. if (mode_val == 0) {
  1649. dev_warn(component->dev, "%s:Invalid HPH Mode, default to class_AB\n",
  1650. __func__);
  1651. mode_val = 3; /* enum will be updated later */
  1652. }
  1653. wcd937x->hph_mode = mode_val;
  1654. return 0;
  1655. }
  1656. static int wcd937x_tx_ch_pwr_level_get(struct snd_kcontrol *kcontrol,
  1657. struct snd_ctl_elem_value *ucontrol)
  1658. {
  1659. struct snd_soc_component *component =
  1660. snd_soc_kcontrol_component(kcontrol);
  1661. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1662. if (strnstr(kcontrol->id.name, "CH1", sizeof(kcontrol->id.name)))
  1663. ucontrol->value.integer.value[0] = wcd937x->tx_ch_pwr[0];
  1664. else if (strnstr(kcontrol->id.name, "CH3", sizeof(kcontrol->id.name)))
  1665. ucontrol->value.integer.value[0] = wcd937x->tx_ch_pwr[1];
  1666. return 0;
  1667. }
  1668. static int wcd937x_tx_ch_pwr_level_put(struct snd_kcontrol *kcontrol,
  1669. struct snd_ctl_elem_value *ucontrol)
  1670. {
  1671. struct snd_soc_component *component =
  1672. snd_soc_kcontrol_component(kcontrol);
  1673. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1674. u32 pwr_level = ucontrol->value.enumerated.item[0];
  1675. dev_dbg(component->dev, "%s: tx ch pwr_level: %d\n",
  1676. __func__, pwr_level);
  1677. if (strnstr(kcontrol->id.name, "CH1",
  1678. sizeof(kcontrol->id.name))) {
  1679. snd_soc_component_update_bits(component,
  1680. WCD937X_ANA_TX_CH1, 0x60,
  1681. pwr_level << 0x5);
  1682. wcd937x->tx_ch_pwr[0] = pwr_level;
  1683. } else if (strnstr(kcontrol->id.name, "CH3",
  1684. sizeof(kcontrol->id.name))) {
  1685. snd_soc_component_update_bits(component,
  1686. WCD937X_ANA_TX_CH3, 0x60,
  1687. pwr_level << 0x5);
  1688. wcd937x->tx_ch_pwr[1] = pwr_level;
  1689. }
  1690. return 0;
  1691. }
  1692. static int wcd937x_ear_pa_gain_get(struct snd_kcontrol *kcontrol,
  1693. struct snd_ctl_elem_value *ucontrol)
  1694. {
  1695. u8 ear_pa_gain = 0;
  1696. struct snd_soc_component *component =
  1697. snd_soc_kcontrol_component(kcontrol);
  1698. ear_pa_gain = snd_soc_component_read32(component,
  1699. WCD937X_ANA_EAR_COMPANDER_CTL);
  1700. ear_pa_gain = (ear_pa_gain & 0x7C) >> 2;
  1701. ucontrol->value.integer.value[0] = ear_pa_gain;
  1702. dev_dbg(component->dev, "%s: ear_pa_gain = 0x%x\n", __func__,
  1703. ear_pa_gain);
  1704. return 0;
  1705. }
  1706. static int wcd937x_ear_pa_gain_put(struct snd_kcontrol *kcontrol,
  1707. struct snd_ctl_elem_value *ucontrol)
  1708. {
  1709. u8 ear_pa_gain = 0;
  1710. struct snd_soc_component *component =
  1711. snd_soc_kcontrol_component(kcontrol);
  1712. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1713. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  1714. __func__, ucontrol->value.integer.value[0]);
  1715. ear_pa_gain = ucontrol->value.integer.value[0] << 2;
  1716. if (!wcd937x->comp1_enable) {
  1717. snd_soc_component_update_bits(component,
  1718. WCD937X_ANA_EAR_COMPANDER_CTL,
  1719. 0x7C, ear_pa_gain);
  1720. }
  1721. return 0;
  1722. }
  1723. static int wcd937x_get_compander(struct snd_kcontrol *kcontrol,
  1724. struct snd_ctl_elem_value *ucontrol)
  1725. {
  1726. struct snd_soc_component *component =
  1727. snd_soc_kcontrol_component(kcontrol);
  1728. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1729. bool hphr;
  1730. struct soc_multi_mixer_control *mc;
  1731. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1732. hphr = mc->shift;
  1733. ucontrol->value.integer.value[0] = hphr ? wcd937x->comp2_enable :
  1734. wcd937x->comp1_enable;
  1735. return 0;
  1736. }
  1737. static int wcd937x_set_compander(struct snd_kcontrol *kcontrol,
  1738. struct snd_ctl_elem_value *ucontrol)
  1739. {
  1740. struct snd_soc_component *component =
  1741. snd_soc_kcontrol_component(kcontrol);
  1742. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1743. int value = ucontrol->value.integer.value[0];
  1744. bool hphr;
  1745. struct soc_multi_mixer_control *mc;
  1746. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1747. hphr = mc->shift;
  1748. if (hphr)
  1749. wcd937x->comp2_enable = value;
  1750. else
  1751. wcd937x->comp1_enable = value;
  1752. return 0;
  1753. }
  1754. static int wcd937x_codec_enable_vdd_buck(struct snd_soc_dapm_widget *w,
  1755. struct snd_kcontrol *kcontrol,
  1756. int event)
  1757. {
  1758. struct snd_soc_component *component =
  1759. snd_soc_dapm_to_component(w->dapm);
  1760. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1761. struct wcd937x_pdata *pdata = NULL;
  1762. int ret = 0;
  1763. pdata = dev_get_platdata(wcd937x->dev);
  1764. if (!pdata) {
  1765. dev_err(component->dev, "%s: pdata is NULL\n", __func__);
  1766. return -EINVAL;
  1767. }
  1768. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1769. w->name, event);
  1770. switch (event) {
  1771. case SND_SOC_DAPM_PRE_PMU:
  1772. if (test_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask)) {
  1773. dev_dbg(component->dev,
  1774. "%s: buck already in enabled state\n",
  1775. __func__);
  1776. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1777. return 0;
  1778. }
  1779. ret = msm_cdc_enable_ondemand_supply(wcd937x->dev,
  1780. wcd937x->supplies,
  1781. pdata->regulator,
  1782. pdata->num_supplies,
  1783. "cdc-vdd-buck");
  1784. if (ret == -EINVAL) {
  1785. dev_err(component->dev, "%s: vdd buck is not enabled\n",
  1786. __func__);
  1787. return ret;
  1788. }
  1789. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1790. /*
  1791. * 200us sleep is required after LDO15 is enabled as per
  1792. * HW requirement
  1793. */
  1794. usleep_range(200, 250);
  1795. break;
  1796. case SND_SOC_DAPM_POST_PMD:
  1797. set_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1798. break;
  1799. }
  1800. return 0;
  1801. }
  1802. static const char * const rx_hph_mode_mux_text[] = {
  1803. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  1804. "CLS_H_ULP", "CLS_AB_HIFI",
  1805. };
  1806. const char * const tx_master_ch_text[] = {
  1807. "ZERO", "SWRM_TX1_CH1", "SWRM_TX1_CH2", "SWRM_TX1_CH3", "SWRM_TX1_CH4",
  1808. "SWRM_TX2_CH1", "SWRM_TX2_CH2", "SWRM_TX2_CH3", "SWRM_TX2_CH4",
  1809. "SWRM_TX3_CH1", "SWRM_TX3_CH2", "SWRM_TX3_CH3", "SWRM_TX3_CH4",
  1810. "SWRM_PCM_IN",
  1811. };
  1812. const struct soc_enum tx_master_ch_enum =
  1813. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_master_ch_text),
  1814. tx_master_ch_text);
  1815. static void wcd937x_tx_get_slave_ch_type_idx(const char *wname, int *ch_idx)
  1816. {
  1817. u8 ch_type = 0;
  1818. if (strnstr(wname, "ADC1", sizeof("ADC1")))
  1819. ch_type = ADC1;
  1820. else if (strnstr(wname, "ADC2", sizeof("ADC2")))
  1821. ch_type = ADC2;
  1822. else if (strnstr(wname, "ADC3", sizeof("ADC3")))
  1823. ch_type = ADC3;
  1824. else if (strnstr(wname, "DMIC0", sizeof("DMIC0")))
  1825. ch_type = DMIC0;
  1826. else if (strnstr(wname, "DMIC1", sizeof("DMIC1")))
  1827. ch_type = DMIC1;
  1828. else if (strnstr(wname, "MBHC", sizeof("MBHC")))
  1829. ch_type = MBHC;
  1830. else if (strnstr(wname, "DMIC2", sizeof("DMIC2")))
  1831. ch_type = DMIC2;
  1832. else if (strnstr(wname, "DMIC3", sizeof("DMIC3")))
  1833. ch_type = DMIC3;
  1834. else if (strnstr(wname, "DMIC4", sizeof("DMIC4")))
  1835. ch_type = DMIC4;
  1836. else if (strnstr(wname, "DMIC5", sizeof("DMIC5")))
  1837. ch_type = DMIC5;
  1838. else
  1839. pr_err("%s: ch name: %s is not listed\n", __func__, wname);
  1840. if (ch_type)
  1841. *ch_idx = wcd937x_slave_get_slave_ch_val(ch_type);
  1842. else
  1843. *ch_idx = -EINVAL;
  1844. }
  1845. static int wcd937x_tx_master_ch_get(struct snd_kcontrol *kcontrol,
  1846. struct snd_ctl_elem_value *ucontrol)
  1847. {
  1848. struct snd_soc_component *component =
  1849. snd_soc_kcontrol_component(kcontrol);
  1850. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1851. int slave_ch_idx;
  1852. wcd937x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  1853. if (slave_ch_idx != -EINVAL)
  1854. ucontrol->value.integer.value[0] =
  1855. wcd937x_slave_get_master_ch_val(
  1856. wcd937x->tx_master_ch_map[slave_ch_idx]);
  1857. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  1858. __func__, ucontrol->value.integer.value[0]);
  1859. return 0;
  1860. }
  1861. static int wcd937x_tx_master_ch_put(struct snd_kcontrol *kcontrol,
  1862. struct snd_ctl_elem_value *ucontrol)
  1863. {
  1864. struct snd_soc_component *component =
  1865. snd_soc_kcontrol_component(kcontrol);
  1866. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1867. int slave_ch_idx;
  1868. wcd937x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  1869. dev_dbg(component->dev, "%s: slave_ch_idx: %d", __func__, slave_ch_idx);
  1870. dev_dbg(component->dev, "%s: ucontrol->value.enumerated.item[0] = %ld\n",
  1871. __func__, ucontrol->value.enumerated.item[0]);
  1872. if (slave_ch_idx != -EINVAL)
  1873. wcd937x->tx_master_ch_map[slave_ch_idx] =
  1874. wcd937x_slave_get_master_ch(
  1875. ucontrol->value.enumerated.item[0]);
  1876. return 0;
  1877. }
  1878. static const char * const wcd937x_tx_ch_pwr_level_text[] = {
  1879. "L0", "L1", "L2", "L3",
  1880. };
  1881. static const char * const wcd937x_ear_pa_gain_text[] = {
  1882. "G_6_DB", "G_4P5_DB", "G_3_DB", "G_1P5_DB", "G_0_DB",
  1883. "G_M1P5_DB", "G_M3_DB", "G_M4P5_DB",
  1884. "G_M6_DB", "G_7P5_DB", "G_M9_DB",
  1885. "G_M10P5_DB", "G_M12_DB", "G_M13P5_DB",
  1886. "G_M15_DB", "G_M16P5_DB", "G_M18_DB",
  1887. };
  1888. static const struct soc_enum rx_hph_mode_mux_enum =
  1889. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  1890. rx_hph_mode_mux_text);
  1891. static SOC_ENUM_SINGLE_EXT_DECL(wcd937x_ear_pa_gain_enum,
  1892. wcd937x_ear_pa_gain_text);
  1893. static SOC_ENUM_SINGLE_EXT_DECL(wcd937x_tx_ch_pwr_level_enum,
  1894. wcd937x_tx_ch_pwr_level_text);
  1895. static const struct snd_kcontrol_new wcd937x_snd_controls[] = {
  1896. SOC_ENUM_EXT("EAR PA GAIN", wcd937x_ear_pa_gain_enum,
  1897. wcd937x_ear_pa_gain_get, wcd937x_ear_pa_gain_put),
  1898. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  1899. wcd937x_rx_hph_mode_get, wcd937x_rx_hph_mode_put),
  1900. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  1901. wcd937x_get_compander, wcd937x_set_compander),
  1902. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  1903. wcd937x_get_compander, wcd937x_set_compander),
  1904. SOC_SINGLE_TLV("HPHL Volume", WCD937X_HPH_L_EN, 0, 20, 1, line_gain),
  1905. SOC_SINGLE_TLV("HPHR Volume", WCD937X_HPH_R_EN, 0, 20, 1, line_gain),
  1906. SOC_SINGLE_TLV("ADC1 Volume", WCD937X_ANA_TX_CH1, 0, 20, 0,
  1907. analog_gain),
  1908. SOC_SINGLE_TLV("ADC2 Volume", WCD937X_ANA_TX_CH2, 0, 20, 0,
  1909. analog_gain),
  1910. SOC_SINGLE_TLV("ADC3 Volume", WCD937X_ANA_TX_CH3, 0, 20, 0,
  1911. analog_gain),
  1912. SOC_ENUM_EXT("ADC1 ChMap", tx_master_ch_enum,
  1913. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1914. SOC_ENUM_EXT("ADC2 ChMap", tx_master_ch_enum,
  1915. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1916. SOC_ENUM_EXT("ADC3 ChMap", tx_master_ch_enum,
  1917. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1918. SOC_ENUM_EXT("DMIC0 ChMap", tx_master_ch_enum,
  1919. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1920. SOC_ENUM_EXT("DMIC1 ChMap", tx_master_ch_enum,
  1921. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1922. SOC_ENUM_EXT("MBHC ChMap", tx_master_ch_enum,
  1923. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1924. SOC_ENUM_EXT("DMIC2 ChMap", tx_master_ch_enum,
  1925. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1926. SOC_ENUM_EXT("DMIC3 ChMap", tx_master_ch_enum,
  1927. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1928. SOC_ENUM_EXT("DMIC4 ChMap", tx_master_ch_enum,
  1929. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1930. SOC_ENUM_EXT("DMIC5 ChMap", tx_master_ch_enum,
  1931. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1932. SOC_ENUM_EXT("TX CH1 PWR", wcd937x_tx_ch_pwr_level_enum,
  1933. wcd937x_tx_ch_pwr_level_get, wcd937x_tx_ch_pwr_level_put),
  1934. SOC_ENUM_EXT("TX CH3 PWR", wcd937x_tx_ch_pwr_level_enum,
  1935. wcd937x_tx_ch_pwr_level_get, wcd937x_tx_ch_pwr_level_put),
  1936. };
  1937. static const struct snd_kcontrol_new adc1_switch[] = {
  1938. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1939. };
  1940. static const struct snd_kcontrol_new adc2_switch[] = {
  1941. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1942. };
  1943. static const struct snd_kcontrol_new adc3_switch[] = {
  1944. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1945. };
  1946. static const struct snd_kcontrol_new dmic1_switch[] = {
  1947. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1948. };
  1949. static const struct snd_kcontrol_new dmic2_switch[] = {
  1950. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1951. };
  1952. static const struct snd_kcontrol_new dmic3_switch[] = {
  1953. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1954. };
  1955. static const struct snd_kcontrol_new dmic4_switch[] = {
  1956. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1957. };
  1958. static const struct snd_kcontrol_new dmic5_switch[] = {
  1959. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1960. };
  1961. static const struct snd_kcontrol_new dmic6_switch[] = {
  1962. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1963. };
  1964. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  1965. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1966. };
  1967. static const struct snd_kcontrol_new aux_rdac_switch[] = {
  1968. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1969. };
  1970. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  1971. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1972. };
  1973. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  1974. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1975. };
  1976. static const char * const adc2_mux_text[] = {
  1977. "INP2", "INP3"
  1978. };
  1979. static const char * const rdac3_mux_text[] = {
  1980. "RX1", "RX3"
  1981. };
  1982. static const struct soc_enum adc2_enum =
  1983. SOC_ENUM_SINGLE(WCD937X_TX_NEW_TX_CH2_SEL, 7,
  1984. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  1985. static const struct soc_enum rdac3_enum =
  1986. SOC_ENUM_SINGLE(WCD937X_DIGITAL_CDC_EAR_PATH_CTL, 0,
  1987. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  1988. static const struct snd_kcontrol_new tx_adc2_mux =
  1989. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  1990. static const struct snd_kcontrol_new rx_rdac3_mux =
  1991. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  1992. static const struct snd_soc_dapm_widget wcd937x_dapm_widgets[] = {
  1993. /*input widgets*/
  1994. SND_SOC_DAPM_INPUT("AMIC1"),
  1995. SND_SOC_DAPM_INPUT("AMIC2"),
  1996. SND_SOC_DAPM_INPUT("AMIC3"),
  1997. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  1998. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  1999. SND_SOC_DAPM_INPUT("IN3_AUX"),
  2000. /*
  2001. * These dummy widgets are null connected to WCD937x dapm input and
  2002. * output widgets which are not actual path endpoints. This ensures
  2003. * dapm doesnt set these dapm input and output widgets as endpoints.
  2004. */
  2005. SND_SOC_DAPM_INPUT("WCD_TX_DUMMY"),
  2006. SND_SOC_DAPM_OUTPUT("WCD_RX_DUMMY"),
  2007. /*tx widgets*/
  2008. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  2009. wcd937x_codec_enable_adc,
  2010. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2011. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
  2012. wcd937x_codec_enable_adc,
  2013. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2014. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  2015. NULL, 0, wcd937x_enable_req,
  2016. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2017. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 0, 0,
  2018. NULL, 0, wcd937x_enable_req,
  2019. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2020. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  2021. &tx_adc2_mux),
  2022. /*tx mixers*/
  2023. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0,
  2024. adc1_switch, ARRAY_SIZE(adc1_switch),
  2025. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2026. SND_SOC_DAPM_POST_PMD),
  2027. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 1, 0,
  2028. adc2_switch, ARRAY_SIZE(adc2_switch),
  2029. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2030. SND_SOC_DAPM_POST_PMD),
  2031. /* micbias widgets*/
  2032. SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2033. wcd937x_codec_enable_micbias,
  2034. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2035. SND_SOC_DAPM_POST_PMD),
  2036. SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2037. wcd937x_codec_enable_micbias,
  2038. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2039. SND_SOC_DAPM_POST_PMD),
  2040. SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2041. wcd937x_codec_enable_micbias,
  2042. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2043. SND_SOC_DAPM_POST_PMD),
  2044. SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0,
  2045. wcd937x_codec_enable_vdd_buck,
  2046. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2047. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  2048. wcd937x_enable_clsh,
  2049. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2050. /*rx widgets*/
  2051. SND_SOC_DAPM_PGA_E("EAR PGA", WCD937X_ANA_EAR, 7, 0, NULL, 0,
  2052. wcd937x_codec_enable_ear_pa,
  2053. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2054. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2055. SND_SOC_DAPM_PGA_E("AUX PGA", WCD937X_AUX_AUXPA, 7, 0, NULL, 0,
  2056. wcd937x_codec_enable_aux_pa,
  2057. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2058. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2059. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD937X_ANA_HPH, 7, 0, NULL, 0,
  2060. wcd937x_codec_enable_hphl_pa,
  2061. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2062. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2063. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD937X_ANA_HPH, 6, 0, NULL, 0,
  2064. wcd937x_codec_enable_hphr_pa,
  2065. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2066. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2067. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  2068. wcd937x_codec_hphl_dac_event,
  2069. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2070. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2071. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  2072. wcd937x_codec_hphr_dac_event,
  2073. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2074. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2075. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  2076. wcd937x_codec_ear_dac_event,
  2077. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2078. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2079. SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
  2080. wcd937x_codec_aux_dac_event,
  2081. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2082. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2083. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  2084. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  2085. wcd937x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  2086. SND_SOC_DAPM_POST_PMD),
  2087. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  2088. wcd937x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  2089. SND_SOC_DAPM_POST_PMD),
  2090. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  2091. wcd937x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  2092. SND_SOC_DAPM_POST_PMD),
  2093. /* rx mixer widgets*/
  2094. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  2095. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  2096. SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
  2097. aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
  2098. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  2099. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  2100. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  2101. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  2102. /*output widgets tx*/
  2103. SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
  2104. SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
  2105. SND_SOC_DAPM_OUTPUT("WCD_TX_OUTPUT"),
  2106. /*output widgets rx*/
  2107. SND_SOC_DAPM_OUTPUT("EAR"),
  2108. SND_SOC_DAPM_OUTPUT("AUX"),
  2109. SND_SOC_DAPM_OUTPUT("HPHL"),
  2110. SND_SOC_DAPM_OUTPUT("HPHR"),
  2111. /* micbias pull up widgets*/
  2112. SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2113. wcd937x_codec_enable_micbias_pullup,
  2114. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2115. SND_SOC_DAPM_POST_PMD),
  2116. SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2117. wcd937x_codec_enable_micbias_pullup,
  2118. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2119. SND_SOC_DAPM_POST_PMD),
  2120. SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2121. wcd937x_codec_enable_micbias_pullup,
  2122. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2123. SND_SOC_DAPM_POST_PMD),
  2124. };
  2125. static const struct snd_soc_dapm_widget wcd9375_dapm_widgets[] = {
  2126. /*input widgets*/
  2127. SND_SOC_DAPM_INPUT("AMIC4"),
  2128. /*tx widgets*/
  2129. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
  2130. wcd937x_codec_enable_adc,
  2131. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2132. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 0, 0,
  2133. NULL, 0, wcd937x_enable_req,
  2134. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2135. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  2136. wcd937x_codec_enable_dmic,
  2137. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2138. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  2139. wcd937x_codec_enable_dmic,
  2140. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2141. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  2142. wcd937x_codec_enable_dmic,
  2143. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2144. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  2145. wcd937x_codec_enable_dmic,
  2146. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2147. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  2148. wcd937x_codec_enable_dmic,
  2149. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2150. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  2151. wcd937x_codec_enable_dmic,
  2152. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2153. /*tx mixer widgets*/
  2154. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0,
  2155. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  2156. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2157. SND_SOC_DAPM_POST_PMD),
  2158. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 1,
  2159. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  2160. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2161. SND_SOC_DAPM_POST_PMD),
  2162. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 2,
  2163. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  2164. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2165. SND_SOC_DAPM_POST_PMD),
  2166. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 3,
  2167. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  2168. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2169. SND_SOC_DAPM_POST_PMD),
  2170. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 4,
  2171. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  2172. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2173. SND_SOC_DAPM_POST_PMD),
  2174. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 5,
  2175. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  2176. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2177. SND_SOC_DAPM_POST_PMD),
  2178. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 2, 0, adc3_switch,
  2179. ARRAY_SIZE(adc3_switch), wcd937x_tx_swr_ctrl,
  2180. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2181. /*output widgets*/
  2182. SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
  2183. SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
  2184. SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
  2185. SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
  2186. SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
  2187. SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
  2188. SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
  2189. };
  2190. static const struct snd_soc_dapm_route wcd937x_audio_map[] = {
  2191. {"WCD_TX_DUMMY", NULL, "WCD_TX_OUTPUT"},
  2192. {"WCD_TX_OUTPUT", NULL, "ADC1_MIXER"},
  2193. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  2194. {"ADC1 REQ", NULL, "ADC1"},
  2195. {"ADC1", NULL, "AMIC1"},
  2196. {"WCD_TX_OUTPUT", NULL, "ADC2_MIXER"},
  2197. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  2198. {"ADC2 REQ", NULL, "ADC2"},
  2199. {"ADC2", NULL, "ADC2 MUX"},
  2200. {"ADC2 MUX", "INP3", "AMIC3"},
  2201. {"ADC2 MUX", "INP2", "AMIC2"},
  2202. {"IN1_HPHL", NULL, "WCD_RX_DUMMY"},
  2203. {"IN1_HPHL", NULL, "VDD_BUCK"},
  2204. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  2205. {"RX1", NULL, "IN1_HPHL"},
  2206. {"RDAC1", NULL, "RX1"},
  2207. {"HPHL_RDAC", "Switch", "RDAC1"},
  2208. {"HPHL PGA", NULL, "HPHL_RDAC"},
  2209. {"HPHL", NULL, "HPHL PGA"},
  2210. {"IN2_HPHR", NULL, "WCD_RX_DUMMY"},
  2211. {"IN2_HPHR", NULL, "VDD_BUCK"},
  2212. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  2213. {"RX2", NULL, "IN2_HPHR"},
  2214. {"RDAC2", NULL, "RX2"},
  2215. {"HPHR_RDAC", "Switch", "RDAC2"},
  2216. {"HPHR PGA", NULL, "HPHR_RDAC"},
  2217. {"HPHR", NULL, "HPHR PGA"},
  2218. {"IN3_AUX", NULL, "WCD_RX_DUMMY"},
  2219. {"IN3_AUX", NULL, "VDD_BUCK"},
  2220. {"IN3_AUX", NULL, "CLS_H_PORT"},
  2221. {"RX3", NULL, "IN3_AUX"},
  2222. {"RDAC4", NULL, "RX3"},
  2223. {"AUX_RDAC", "Switch", "RDAC4"},
  2224. {"AUX PGA", NULL, "AUX_RDAC"},
  2225. {"AUX", NULL, "AUX PGA"},
  2226. {"RDAC3_MUX", "RX3", "RX3"},
  2227. {"RDAC3_MUX", "RX1", "RX1"},
  2228. {"RDAC3", NULL, "RDAC3_MUX"},
  2229. {"EAR_RDAC", "Switch", "RDAC3"},
  2230. {"EAR PGA", NULL, "EAR_RDAC"},
  2231. {"EAR", NULL, "EAR PGA"},
  2232. };
  2233. static const struct snd_soc_dapm_route wcd9375_audio_map[] = {
  2234. {"WCD_TX_DUMMY", NULL, "WCD_TX_OUTPUT"},
  2235. {"WCD_TX_OUTPUT", NULL, "ADC3_MIXER"},
  2236. {"ADC3_OUTPUT", NULL, "ADC3_MIXER"},
  2237. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  2238. {"ADC3 REQ", NULL, "ADC3"},
  2239. {"ADC3", NULL, "AMIC4"},
  2240. {"WCD_TX_OUTPUT", NULL, "DMIC1_MIXER"},
  2241. {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
  2242. {"DMIC1_MIXER", "Switch", "DMIC1"},
  2243. {"WCD_TX_OUTPUT", NULL, "DMIC2_MIXER"},
  2244. {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
  2245. {"DMIC2_MIXER", "Switch", "DMIC2"},
  2246. {"WCD_TX_OUTPUT", NULL, "DMIC3_MIXER"},
  2247. {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
  2248. {"DMIC3_MIXER", "Switch", "DMIC3"},
  2249. {"WCD_TX_OUTPUT", NULL, "DMIC4_MIXER"},
  2250. {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
  2251. {"DMIC4_MIXER", "Switch", "DMIC4"},
  2252. {"WCD_TX_OUTPUT", NULL, "DMIC5_MIXER"},
  2253. {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
  2254. {"DMIC5_MIXER", "Switch", "DMIC5"},
  2255. {"WCD_TX_OUTPUT", NULL, "DMIC6_MIXER"},
  2256. {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
  2257. {"DMIC6_MIXER", "Switch", "DMIC6"},
  2258. };
  2259. static ssize_t wcd937x_version_read(struct snd_info_entry *entry,
  2260. void *file_private_data,
  2261. struct file *file,
  2262. char __user *buf, size_t count,
  2263. loff_t pos)
  2264. {
  2265. struct wcd937x_priv *priv;
  2266. char buffer[WCD937X_VERSION_ENTRY_SIZE];
  2267. int len = 0;
  2268. priv = (struct wcd937x_priv *) entry->private_data;
  2269. if (!priv) {
  2270. pr_err("%s: wcd937x priv is null\n", __func__);
  2271. return -EINVAL;
  2272. }
  2273. switch (priv->version) {
  2274. case WCD937X_VERSION_1_0:
  2275. len = snprintf(buffer, sizeof(buffer), "WCD937X_1_0\n");
  2276. break;
  2277. default:
  2278. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2279. }
  2280. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2281. }
  2282. static struct snd_info_entry_ops wcd937x_info_ops = {
  2283. .read = wcd937x_version_read,
  2284. };
  2285. static ssize_t wcd937x_variant_read(struct snd_info_entry *entry,
  2286. void *file_private_data,
  2287. struct file *file,
  2288. char __user *buf, size_t count,
  2289. loff_t pos)
  2290. {
  2291. struct wcd937x_priv *priv;
  2292. char buffer[WCD937X_VARIANT_ENTRY_SIZE];
  2293. int len = 0;
  2294. priv = (struct wcd937x_priv *) entry->private_data;
  2295. if (!priv) {
  2296. pr_err("%s: wcd937x priv is null\n", __func__);
  2297. return -EINVAL;
  2298. }
  2299. switch (priv->variant) {
  2300. case WCD9370_VARIANT:
  2301. len = snprintf(buffer, sizeof(buffer), "WCD9370\n");
  2302. break;
  2303. case WCD9375_VARIANT:
  2304. len = snprintf(buffer, sizeof(buffer), "WCD9375\n");
  2305. break;
  2306. default:
  2307. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2308. }
  2309. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2310. }
  2311. static struct snd_info_entry_ops wcd937x_variant_ops = {
  2312. .read = wcd937x_variant_read,
  2313. };
  2314. /*
  2315. * wcd937x_info_create_codec_entry - creates wcd937x module
  2316. * @codec_root: The parent directory
  2317. * @component: component instance
  2318. *
  2319. * Creates wcd937x module, variant and version entry under the given
  2320. * parent directory.
  2321. *
  2322. * Return: 0 on success or negative error code on failure.
  2323. */
  2324. int wcd937x_info_create_codec_entry(struct snd_info_entry *codec_root,
  2325. struct snd_soc_component *component)
  2326. {
  2327. struct snd_info_entry *version_entry;
  2328. struct snd_info_entry *variant_entry;
  2329. struct wcd937x_priv *priv;
  2330. struct snd_soc_card *card;
  2331. if (!codec_root || !component)
  2332. return -EINVAL;
  2333. priv = snd_soc_component_get_drvdata(component);
  2334. if (priv->entry) {
  2335. dev_dbg(priv->dev,
  2336. "%s:wcd937x module already created\n", __func__);
  2337. return 0;
  2338. }
  2339. card = component->card;
  2340. priv->entry = snd_info_create_module_entry(codec_root->module,
  2341. "wcd937x", codec_root);
  2342. if (!priv->entry) {
  2343. dev_dbg(component->dev, "%s: failed to create wcd937x entry\n",
  2344. __func__);
  2345. return -ENOMEM;
  2346. }
  2347. priv->entry->mode = S_IFDIR | 0555;
  2348. if (snd_info_register(priv->entry) < 0) {
  2349. snd_info_free_entry(priv->entry);
  2350. return -ENOMEM;
  2351. }
  2352. version_entry = snd_info_create_card_entry(card->snd_card,
  2353. "version",
  2354. priv->entry);
  2355. if (!version_entry) {
  2356. dev_dbg(component->dev, "%s: failed to create wcd937x version entry\n",
  2357. __func__);
  2358. snd_info_free_entry(priv->entry);
  2359. return -ENOMEM;
  2360. }
  2361. version_entry->private_data = priv;
  2362. version_entry->size = WCD937X_VERSION_ENTRY_SIZE;
  2363. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  2364. version_entry->c.ops = &wcd937x_info_ops;
  2365. if (snd_info_register(version_entry) < 0) {
  2366. snd_info_free_entry(version_entry);
  2367. snd_info_free_entry(priv->entry);
  2368. return -ENOMEM;
  2369. }
  2370. priv->version_entry = version_entry;
  2371. variant_entry = snd_info_create_card_entry(card->snd_card,
  2372. "variant",
  2373. priv->entry);
  2374. if (!variant_entry) {
  2375. dev_dbg(component->dev,
  2376. "%s: failed to create wcd937x variant entry\n",
  2377. __func__);
  2378. snd_info_free_entry(version_entry);
  2379. snd_info_free_entry(priv->entry);
  2380. return -ENOMEM;
  2381. }
  2382. variant_entry->private_data = priv;
  2383. variant_entry->size = WCD937X_VARIANT_ENTRY_SIZE;
  2384. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  2385. variant_entry->c.ops = &wcd937x_variant_ops;
  2386. if (snd_info_register(variant_entry) < 0) {
  2387. snd_info_free_entry(variant_entry);
  2388. snd_info_free_entry(version_entry);
  2389. snd_info_free_entry(priv->entry);
  2390. return -ENOMEM;
  2391. }
  2392. priv->variant_entry = variant_entry;
  2393. return 0;
  2394. }
  2395. EXPORT_SYMBOL(wcd937x_info_create_codec_entry);
  2396. static int wcd937x_set_micbias_data(struct wcd937x_priv *wcd937x,
  2397. struct wcd937x_pdata *pdata)
  2398. {
  2399. int vout_ctl_1 = 0, vout_ctl_2 = 0, vout_ctl_3 = 0;
  2400. int rc = 0;
  2401. if (!pdata) {
  2402. dev_err(wcd937x->dev, "%s: NULL pdata\n", __func__);
  2403. return -ENODEV;
  2404. }
  2405. /* set micbias voltage */
  2406. vout_ctl_1 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb1_mv);
  2407. vout_ctl_2 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb2_mv);
  2408. vout_ctl_3 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb3_mv);
  2409. if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0) {
  2410. rc = -EINVAL;
  2411. goto done;
  2412. }
  2413. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB1, 0x3F,
  2414. vout_ctl_1);
  2415. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB2, 0x3F,
  2416. vout_ctl_2);
  2417. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB3, 0x3F,
  2418. vout_ctl_3);
  2419. done:
  2420. return rc;
  2421. }
  2422. static int wcd937x_soc_codec_probe(struct snd_soc_component *component)
  2423. {
  2424. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  2425. struct snd_soc_dapm_context *dapm =
  2426. snd_soc_component_get_dapm(component);
  2427. int variant;
  2428. int ret = -EINVAL;
  2429. dev_info(component->dev, "%s()\n", __func__);
  2430. wcd937x = snd_soc_component_get_drvdata(component);
  2431. if (!wcd937x)
  2432. return -EINVAL;
  2433. wcd937x->component = component;
  2434. snd_soc_component_init_regmap(component, wcd937x->regmap);
  2435. variant = (snd_soc_component_read32(
  2436. component, WCD937X_DIGITAL_EFUSE_REG_0) & 0x1E) >> 1;
  2437. wcd937x->variant = variant;
  2438. wcd937x->fw_data = devm_kzalloc(component->dev,
  2439. sizeof(*(wcd937x->fw_data)),
  2440. GFP_KERNEL);
  2441. if (!wcd937x->fw_data) {
  2442. dev_err(component->dev, "Failed to allocate fw_data\n");
  2443. ret = -ENOMEM;
  2444. goto err;
  2445. }
  2446. set_bit(WCD9XXX_MBHC_CAL, wcd937x->fw_data->cal_bit);
  2447. ret = wcd_cal_create_hwdep(wcd937x->fw_data,
  2448. WCD9XXX_CODEC_HWDEP_NODE, component);
  2449. if (ret < 0) {
  2450. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  2451. goto err_hwdep;
  2452. }
  2453. ret = wcd937x_mbhc_init(&wcd937x->mbhc, component, wcd937x->fw_data);
  2454. if (ret) {
  2455. pr_err("%s: mbhc initialization failed\n", __func__);
  2456. goto err_hwdep;
  2457. }
  2458. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  2459. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  2460. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  2461. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  2462. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  2463. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  2464. snd_soc_dapm_ignore_suspend(dapm, "ADC1_OUTPUT");
  2465. snd_soc_dapm_ignore_suspend(dapm, "ADC2_OUTPUT");
  2466. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_OUTPUT");
  2467. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  2468. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  2469. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  2470. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  2471. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_DUMMY");
  2472. snd_soc_dapm_ignore_suspend(dapm, "WCD_RX_DUMMY");
  2473. snd_soc_dapm_sync(dapm);
  2474. wcd_cls_h_init(&wcd937x->clsh_info);
  2475. wcd937x_init_reg(component);
  2476. if (wcd937x->variant == WCD9375_VARIANT) {
  2477. ret = snd_soc_dapm_new_controls(dapm, wcd9375_dapm_widgets,
  2478. ARRAY_SIZE(wcd9375_dapm_widgets));
  2479. if (ret < 0) {
  2480. dev_err(component->dev, "%s: Failed to add snd_ctls\n",
  2481. __func__);
  2482. goto err_hwdep;
  2483. }
  2484. ret = snd_soc_dapm_add_routes(dapm, wcd9375_audio_map,
  2485. ARRAY_SIZE(wcd9375_audio_map));
  2486. if (ret < 0) {
  2487. dev_err(component->dev, "%s: Failed to add routes\n",
  2488. __func__);
  2489. goto err_hwdep;
  2490. }
  2491. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  2492. snd_soc_dapm_ignore_suspend(dapm, "DMIC1_OUTPUT");
  2493. snd_soc_dapm_ignore_suspend(dapm, "DMIC2_OUTPUT");
  2494. snd_soc_dapm_ignore_suspend(dapm, "DMIC3_OUTPUT");
  2495. snd_soc_dapm_ignore_suspend(dapm, "DMIC4_OUTPUT");
  2496. snd_soc_dapm_ignore_suspend(dapm, "DMIC5_OUTPUT");
  2497. snd_soc_dapm_ignore_suspend(dapm, "DMIC6_OUTPUT");
  2498. snd_soc_dapm_ignore_suspend(dapm, "ADC3_OUTPUT");
  2499. snd_soc_dapm_sync(dapm);
  2500. }
  2501. wcd937x->version = WCD937X_VERSION_1_0;
  2502. /* Register event notifier */
  2503. wcd937x->nblock.notifier_call = wcd937x_event_notify;
  2504. if (wcd937x->register_notifier) {
  2505. ret = wcd937x->register_notifier(wcd937x->handle,
  2506. &wcd937x->nblock,
  2507. true);
  2508. if (ret) {
  2509. dev_err(component->dev,
  2510. "%s: Failed to register notifier %d\n",
  2511. __func__, ret);
  2512. return ret;
  2513. }
  2514. }
  2515. return ret;
  2516. err_hwdep:
  2517. wcd937x->fw_data = NULL;
  2518. err:
  2519. return ret;
  2520. }
  2521. static void wcd937x_soc_codec_remove(struct snd_soc_component *component)
  2522. {
  2523. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  2524. if (!wcd937x)
  2525. return;
  2526. if (wcd937x->register_notifier)
  2527. wcd937x->register_notifier(wcd937x->handle,
  2528. &wcd937x->nblock,
  2529. false);
  2530. return;
  2531. }
  2532. static const struct snd_soc_component_driver soc_codec_dev_wcd937x = {
  2533. .name = WCD937X_DRV_NAME,
  2534. .probe = wcd937x_soc_codec_probe,
  2535. .remove = wcd937x_soc_codec_remove,
  2536. .controls = wcd937x_snd_controls,
  2537. .num_controls = ARRAY_SIZE(wcd937x_snd_controls),
  2538. .dapm_widgets = wcd937x_dapm_widgets,
  2539. .num_dapm_widgets = ARRAY_SIZE(wcd937x_dapm_widgets),
  2540. .dapm_routes = wcd937x_audio_map,
  2541. .num_dapm_routes = ARRAY_SIZE(wcd937x_audio_map),
  2542. };
  2543. #ifdef CONFIG_PM_SLEEP
  2544. static int wcd937x_suspend(struct device *dev)
  2545. {
  2546. struct wcd937x_priv *wcd937x = NULL;
  2547. int ret = 0;
  2548. struct wcd937x_pdata *pdata = NULL;
  2549. if (!dev)
  2550. return -ENODEV;
  2551. wcd937x = dev_get_drvdata(dev);
  2552. if (!wcd937x)
  2553. return -EINVAL;
  2554. pdata = dev_get_platdata(wcd937x->dev);
  2555. if (!pdata) {
  2556. dev_err(dev, "%s: pdata is NULL\n", __func__);
  2557. return -EINVAL;
  2558. }
  2559. if (test_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask)) {
  2560. ret = msm_cdc_disable_ondemand_supply(wcd937x->dev,
  2561. wcd937x->supplies,
  2562. pdata->regulator,
  2563. pdata->num_supplies,
  2564. "cdc-vdd-buck");
  2565. if (ret == -EINVAL) {
  2566. dev_err(dev, "%s: vdd buck is not disabled\n",
  2567. __func__);
  2568. return 0;
  2569. }
  2570. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  2571. }
  2572. return 0;
  2573. }
  2574. static int wcd937x_resume(struct device *dev)
  2575. {
  2576. return 0;
  2577. }
  2578. #endif
  2579. static int wcd937x_reset(struct device *dev)
  2580. {
  2581. struct wcd937x_priv *wcd937x = NULL;
  2582. int rc = 0;
  2583. int value = 0;
  2584. if (!dev)
  2585. return -ENODEV;
  2586. wcd937x = dev_get_drvdata(dev);
  2587. if (!wcd937x)
  2588. return -EINVAL;
  2589. if (!wcd937x->rst_np) {
  2590. dev_err(dev, "%s: reset gpio device node not specified\n",
  2591. __func__);
  2592. return -EINVAL;
  2593. }
  2594. value = msm_cdc_pinctrl_get_state(wcd937x->rst_np);
  2595. if (value > 0)
  2596. return 0;
  2597. rc = msm_cdc_pinctrl_select_sleep_state(wcd937x->rst_np);
  2598. if (rc) {
  2599. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2600. __func__);
  2601. return rc;
  2602. }
  2603. /* 20ms sleep required after pulling the reset gpio to LOW */
  2604. usleep_range(20, 30);
  2605. rc = msm_cdc_pinctrl_select_active_state(wcd937x->rst_np);
  2606. if (rc) {
  2607. dev_err(dev, "%s: wcd active state request fail!\n",
  2608. __func__);
  2609. return rc;
  2610. }
  2611. /* 20ms sleep required after pulling the reset gpio to HIGH */
  2612. usleep_range(20, 30);
  2613. return rc;
  2614. }
  2615. static int wcd937x_read_of_property_u32(struct device *dev, const char *name,
  2616. u32 *val)
  2617. {
  2618. int rc = 0;
  2619. rc = of_property_read_u32(dev->of_node, name, val);
  2620. if (rc)
  2621. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2622. __func__, name, dev->of_node->full_name);
  2623. return rc;
  2624. }
  2625. static void wcd937x_dt_parse_micbias_info(struct device *dev,
  2626. struct wcd937x_micbias_setting *mb)
  2627. {
  2628. u32 prop_val = 0;
  2629. int rc = 0;
  2630. /* MB1 */
  2631. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  2632. NULL)) {
  2633. rc = wcd937x_read_of_property_u32(dev,
  2634. "qcom,cdc-micbias1-mv",
  2635. &prop_val);
  2636. if (!rc)
  2637. mb->micb1_mv = prop_val;
  2638. } else {
  2639. dev_info(dev, "%s: Micbias1 DT property not found\n",
  2640. __func__);
  2641. }
  2642. /* MB2 */
  2643. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  2644. NULL)) {
  2645. rc = wcd937x_read_of_property_u32(dev,
  2646. "qcom,cdc-micbias2-mv",
  2647. &prop_val);
  2648. if (!rc)
  2649. mb->micb2_mv = prop_val;
  2650. } else {
  2651. dev_info(dev, "%s: Micbias2 DT property not found\n",
  2652. __func__);
  2653. }
  2654. /* MB3 */
  2655. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  2656. NULL)) {
  2657. rc = wcd937x_read_of_property_u32(dev,
  2658. "qcom,cdc-micbias3-mv",
  2659. &prop_val);
  2660. if (!rc)
  2661. mb->micb3_mv = prop_val;
  2662. } else {
  2663. dev_info(dev, "%s: Micbias3 DT property not found\n",
  2664. __func__);
  2665. }
  2666. }
  2667. static int wcd937x_reset_low(struct device *dev)
  2668. {
  2669. struct wcd937x_priv *wcd937x = NULL;
  2670. int rc = 0;
  2671. if (!dev)
  2672. return -ENODEV;
  2673. wcd937x = dev_get_drvdata(dev);
  2674. if (!wcd937x)
  2675. return -EINVAL;
  2676. if (!wcd937x->rst_np) {
  2677. dev_err(dev, "%s: reset gpio device node not specified\n",
  2678. __func__);
  2679. return -EINVAL;
  2680. }
  2681. rc = msm_cdc_pinctrl_select_sleep_state(wcd937x->rst_np);
  2682. if (rc) {
  2683. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2684. __func__);
  2685. return rc;
  2686. }
  2687. /* 20ms sleep required after pulling the reset gpio to LOW */
  2688. usleep_range(20, 30);
  2689. return rc;
  2690. }
  2691. struct wcd937x_pdata *wcd937x_populate_dt_data(struct device *dev)
  2692. {
  2693. struct wcd937x_pdata *pdata = NULL;
  2694. pdata = kzalloc(sizeof(struct wcd937x_pdata),
  2695. GFP_KERNEL);
  2696. if (!pdata)
  2697. return NULL;
  2698. pdata->rst_np = of_parse_phandle(dev->of_node,
  2699. "qcom,wcd-rst-gpio-node", 0);
  2700. if (!pdata->rst_np) {
  2701. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2702. __func__, "qcom,wcd-rst-gpio-node",
  2703. dev->of_node->full_name);
  2704. return NULL;
  2705. }
  2706. /* Parse power supplies */
  2707. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  2708. &pdata->num_supplies);
  2709. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  2710. dev_err(dev, "%s: no power supplies defined for codec\n",
  2711. __func__);
  2712. return NULL;
  2713. }
  2714. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  2715. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  2716. wcd937x_dt_parse_micbias_info(dev, &pdata->micbias);
  2717. return pdata;
  2718. }
  2719. static int wcd937x_wakeup(void *handle, bool enable)
  2720. {
  2721. struct wcd937x_priv *priv;
  2722. if (!handle) {
  2723. pr_err("%s: NULL handle\n", __func__);
  2724. return -EINVAL;
  2725. }
  2726. priv = (struct wcd937x_priv *)handle;
  2727. if (!priv->tx_swr_dev) {
  2728. pr_err("%s: tx swr dev is NULL\n", __func__);
  2729. return -EINVAL;
  2730. }
  2731. if (enable)
  2732. return swr_device_wakeup_vote(priv->tx_swr_dev);
  2733. else
  2734. return swr_device_wakeup_unvote(priv->tx_swr_dev);
  2735. }
  2736. static irqreturn_t wcd937x_wd_handle_irq(int irq, void *data)
  2737. {
  2738. pr_err_ratelimited("%s: Watchdog interrupt for irq =%d triggered\n",
  2739. __func__, irq);
  2740. return IRQ_HANDLED;
  2741. }
  2742. static int wcd937x_bind(struct device *dev)
  2743. {
  2744. int ret = 0, i = 0;
  2745. struct wcd937x_priv *wcd937x = NULL;
  2746. struct wcd937x_pdata *pdata = NULL;
  2747. struct wcd_ctrl_platform_data *plat_data = NULL;
  2748. wcd937x = kzalloc(sizeof(struct wcd937x_priv), GFP_KERNEL);
  2749. if (!wcd937x)
  2750. return -ENOMEM;
  2751. dev_set_drvdata(dev, wcd937x);
  2752. pdata = wcd937x_populate_dt_data(dev);
  2753. if (!pdata) {
  2754. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  2755. return -EINVAL;
  2756. }
  2757. wcd937x->dev = dev;
  2758. wcd937x->dev->platform_data = pdata;
  2759. wcd937x->rst_np = pdata->rst_np;
  2760. ret = msm_cdc_init_supplies(dev, &wcd937x->supplies,
  2761. pdata->regulator, pdata->num_supplies);
  2762. if (!wcd937x->supplies) {
  2763. dev_err(dev, "%s: Cannot init wcd supplies\n",
  2764. __func__);
  2765. goto err_bind_all;
  2766. }
  2767. plat_data = dev_get_platdata(dev->parent);
  2768. if (!plat_data) {
  2769. dev_err(dev, "%s: platform data from parent is NULL\n",
  2770. __func__);
  2771. ret = -EINVAL;
  2772. goto err_bind_all;
  2773. }
  2774. wcd937x->handle = (void *)plat_data->handle;
  2775. if (!wcd937x->handle) {
  2776. dev_err(dev, "%s: handle is NULL\n", __func__);
  2777. ret = -EINVAL;
  2778. goto err_bind_all;
  2779. }
  2780. wcd937x->update_wcd_event = plat_data->update_wcd_event;
  2781. if (!wcd937x->update_wcd_event) {
  2782. dev_err(dev, "%s: update_wcd_event api is null!\n",
  2783. __func__);
  2784. ret = -EINVAL;
  2785. goto err_bind_all;
  2786. }
  2787. wcd937x->register_notifier = plat_data->register_notifier;
  2788. if (!wcd937x->register_notifier) {
  2789. dev_err(dev, "%s: register_notifier api is null!\n",
  2790. __func__);
  2791. ret = -EINVAL;
  2792. goto err_bind_all;
  2793. }
  2794. ret = msm_cdc_enable_static_supplies(dev, wcd937x->supplies,
  2795. pdata->regulator,
  2796. pdata->num_supplies);
  2797. if (ret) {
  2798. dev_err(dev, "%s: wcd static supply enable failed!\n",
  2799. __func__);
  2800. goto err_bind_all;
  2801. }
  2802. wcd937x_reset(dev);
  2803. /*
  2804. * Add 5msec delay to provide sufficient time for
  2805. * soundwire auto enumeration of slave devices as
  2806. * as per HW requirement.
  2807. */
  2808. usleep_range(5000, 5010);
  2809. wcd937x->wakeup = wcd937x_wakeup;
  2810. ret = component_bind_all(dev, wcd937x);
  2811. if (ret) {
  2812. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  2813. __func__, ret);
  2814. goto err_bind_all;
  2815. }
  2816. ret = wcd937x_parse_port_mapping(dev, "qcom,rx_swr_ch_map", CODEC_RX);
  2817. ret |= wcd937x_parse_port_mapping(dev, "qcom,tx_swr_ch_map", CODEC_TX);
  2818. if (ret) {
  2819. dev_err(dev, "Failed to read port mapping\n");
  2820. goto err;
  2821. }
  2822. wcd937x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  2823. if (!wcd937x->rx_swr_dev) {
  2824. dev_err(dev, "%s: Could not find RX swr slave device\n",
  2825. __func__);
  2826. ret = -ENODEV;
  2827. goto err;
  2828. }
  2829. wcd937x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  2830. if (!wcd937x->tx_swr_dev) {
  2831. dev_err(dev, "%s: Could not find TX swr slave device\n",
  2832. __func__);
  2833. ret = -ENODEV;
  2834. goto err;
  2835. }
  2836. wcd937x->regmap = devm_regmap_init_swr(wcd937x->tx_swr_dev,
  2837. &wcd937x_regmap_config);
  2838. if (!wcd937x->regmap) {
  2839. dev_err(dev, "%s: Regmap init failed\n",
  2840. __func__);
  2841. goto err;
  2842. }
  2843. /* Set all interupts as edge triggered */
  2844. for (i = 0; i < wcd937x_regmap_irq_chip.num_regs; i++)
  2845. regmap_write(wcd937x->regmap,
  2846. (WCD937X_DIGITAL_INTR_LEVEL_0 + i), 0);
  2847. wcd937x_regmap_irq_chip.irq_drv_data = wcd937x;
  2848. wcd937x->irq_info.wcd_regmap_irq_chip = &wcd937x_regmap_irq_chip;
  2849. wcd937x->irq_info.codec_name = "WCD937X";
  2850. wcd937x->irq_info.regmap = wcd937x->regmap;
  2851. wcd937x->irq_info.dev = dev;
  2852. ret = wcd_irq_init(&wcd937x->irq_info, &wcd937x->virq);
  2853. if (ret) {
  2854. dev_err(dev, "%s: IRQ init failed: %d\n",
  2855. __func__, ret);
  2856. goto err;
  2857. }
  2858. wcd937x->tx_swr_dev->slave_irq = wcd937x->virq;
  2859. ret = wcd937x_set_micbias_data(wcd937x, pdata);
  2860. if (ret < 0) {
  2861. dev_err(dev, "%s: bad micbias pdata\n", __func__);
  2862. goto err_irq;
  2863. }
  2864. /* default L1 power setting */
  2865. wcd937x->tx_ch_pwr[0] = 1;
  2866. wcd937x->tx_ch_pwr[1] = 1;
  2867. mutex_init(&wcd937x->micb_lock);
  2868. mutex_init(&wcd937x->ana_tx_clk_lock);
  2869. /* Request for watchdog interrupt */
  2870. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHR_PDM_WD_INT,
  2871. "HPHR PDM WD INT", wcd937x_wd_handle_irq, NULL);
  2872. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHL_PDM_WD_INT,
  2873. "HPHL PDM WD INT", wcd937x_wd_handle_irq, NULL);
  2874. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT,
  2875. "AUX PDM WD INT", wcd937x_wd_handle_irq, NULL);
  2876. /* Disable watchdog interrupt for HPH and AUX */
  2877. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHR_PDM_WD_INT);
  2878. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHL_PDM_WD_INT);
  2879. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT);
  2880. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd937x,
  2881. wcd937x_dai, ARRAY_SIZE(wcd937x_dai));
  2882. if (ret) {
  2883. dev_err(dev, "%s: Codec registration failed\n",
  2884. __func__);
  2885. goto err_irq;
  2886. }
  2887. return ret;
  2888. err_irq:
  2889. wcd_irq_exit(&wcd937x->irq_info, wcd937x->virq);
  2890. err:
  2891. component_unbind_all(dev, wcd937x);
  2892. err_bind_all:
  2893. dev_set_drvdata(dev, NULL);
  2894. kfree(pdata);
  2895. kfree(wcd937x);
  2896. return ret;
  2897. }
  2898. static void wcd937x_unbind(struct device *dev)
  2899. {
  2900. struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
  2901. struct wcd937x_pdata *pdata = dev_get_platdata(wcd937x->dev);
  2902. wcd_irq_exit(&wcd937x->irq_info, wcd937x->virq);
  2903. snd_soc_unregister_component(dev);
  2904. component_unbind_all(dev, wcd937x);
  2905. mutex_destroy(&wcd937x->micb_lock);
  2906. mutex_destroy(&wcd937x->ana_tx_clk_lock);
  2907. dev_set_drvdata(dev, NULL);
  2908. kfree(pdata);
  2909. kfree(wcd937x);
  2910. }
  2911. static const struct of_device_id wcd937x_dt_match[] = {
  2912. { .compatible = "qcom,wcd937x-codec" , .data = "wcd937x" },
  2913. {}
  2914. };
  2915. static const struct component_master_ops wcd937x_comp_ops = {
  2916. .bind = wcd937x_bind,
  2917. .unbind = wcd937x_unbind,
  2918. };
  2919. static int wcd937x_compare_of(struct device *dev, void *data)
  2920. {
  2921. return dev->of_node == data;
  2922. }
  2923. static void wcd937x_release_of(struct device *dev, void *data)
  2924. {
  2925. of_node_put(data);
  2926. }
  2927. static int wcd937x_add_slave_components(struct device *dev,
  2928. struct component_match **matchptr)
  2929. {
  2930. struct device_node *np, *rx_node, *tx_node;
  2931. np = dev->of_node;
  2932. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  2933. if (!rx_node) {
  2934. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  2935. return -ENODEV;
  2936. }
  2937. of_node_get(rx_node);
  2938. component_match_add_release(dev, matchptr,
  2939. wcd937x_release_of,
  2940. wcd937x_compare_of,
  2941. rx_node);
  2942. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  2943. if (!tx_node) {
  2944. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  2945. return -ENODEV;
  2946. }
  2947. of_node_get(tx_node);
  2948. component_match_add_release(dev, matchptr,
  2949. wcd937x_release_of,
  2950. wcd937x_compare_of,
  2951. tx_node);
  2952. return 0;
  2953. }
  2954. static int wcd937x_probe(struct platform_device *pdev)
  2955. {
  2956. struct component_match *match = NULL;
  2957. int ret;
  2958. ret = wcd937x_add_slave_components(&pdev->dev, &match);
  2959. if (ret)
  2960. return ret;
  2961. return component_master_add_with_match(&pdev->dev,
  2962. &wcd937x_comp_ops, match);
  2963. }
  2964. static int wcd937x_remove(struct platform_device *pdev)
  2965. {
  2966. component_master_del(&pdev->dev, &wcd937x_comp_ops);
  2967. dev_set_drvdata(&pdev->dev, NULL);
  2968. return 0;
  2969. }
  2970. #ifdef CONFIG_PM_SLEEP
  2971. static const struct dev_pm_ops wcd937x_dev_pm_ops = {
  2972. SET_SYSTEM_SLEEP_PM_OPS(
  2973. wcd937x_suspend,
  2974. wcd937x_resume
  2975. )
  2976. };
  2977. #endif
  2978. static struct platform_driver wcd937x_codec_driver = {
  2979. .probe = wcd937x_probe,
  2980. .remove = wcd937x_remove,
  2981. .driver = {
  2982. .name = "wcd937x_codec",
  2983. .owner = THIS_MODULE,
  2984. .of_match_table = of_match_ptr(wcd937x_dt_match),
  2985. #ifdef CONFIG_PM_SLEEP
  2986. .pm = &wcd937x_dev_pm_ops,
  2987. #endif
  2988. .suppress_bind_attrs = true,
  2989. },
  2990. };
  2991. module_platform_driver(wcd937x_codec_driver);
  2992. MODULE_DESCRIPTION("WCD937X Codec driver");
  2993. MODULE_LICENSE("GPL v2");