wcd938x.c 118 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/slab.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/device.h>
  9. #include <linux/delay.h>
  10. #include <linux/kernel.h>
  11. #include <linux/component.h>
  12. #include <sound/soc.h>
  13. #include <sound/tlv.h>
  14. #include <soc/soundwire.h>
  15. #include <linux/regmap.h>
  16. #include <sound/soc.h>
  17. #include <sound/soc-dapm.h>
  18. #include <asoc/wcdcal-hwdep.h>
  19. #include <asoc/msm-cdc-pinctrl.h>
  20. #include <asoc/msm-cdc-supply.h>
  21. #include <dt-bindings/sound/audio-codec-port-types.h>
  22. #include "wcd938x-registers.h"
  23. #include "wcd938x.h"
  24. #include "internal.h"
  25. #define NUM_SWRS_DT_PARAMS 5
  26. #define WCD938X_VARIANT_ENTRY_SIZE 32
  27. #define WCD938X_VERSION_1_0 1
  28. #define WCD938X_VERSION_ENTRY_SIZE 32
  29. #define EAR_RX_PATH_AUX 1
  30. #define ADC_MODE_VAL_HIFI 0x01
  31. #define ADC_MODE_VAL_LO_HIF 0x02
  32. #define ADC_MODE_VAL_NORMAL 0x03
  33. #define ADC_MODE_VAL_LP 0x05
  34. #define ADC_MODE_VAL_ULP1 0x09
  35. #define ADC_MODE_VAL_ULP2 0x0B
  36. #define NUM_ATTEMPTS 5
  37. #define DAPM_MICBIAS1_STANDALONE "MIC BIAS1 Standalone"
  38. #define DAPM_MICBIAS2_STANDALONE "MIC BIAS2 Standalone"
  39. #define DAPM_MICBIAS3_STANDALONE "MIC BIAS3 Standalone"
  40. #define DAPM_MICBIAS4_STANDALONE "MIC BIAS4 Standalone"
  41. #define WCD938X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  42. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  43. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
  44. SNDRV_PCM_RATE_384000)
  45. /* Fractional Rates */
  46. #define WCD938X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  47. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
  48. #define WCD938X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  49. SNDRV_PCM_FMTBIT_S24_LE |\
  50. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
  51. enum {
  52. CODEC_TX = 0,
  53. CODEC_RX,
  54. };
  55. enum {
  56. WCD_ADC1 = 0,
  57. WCD_ADC2,
  58. WCD_ADC3,
  59. WCD_ADC4,
  60. ALLOW_BUCK_DISABLE,
  61. HPH_COMP_DELAY,
  62. HPH_PA_DELAY,
  63. AMIC2_BCS_ENABLE,
  64. };
  65. enum {
  66. ADC_MODE_INVALID = 0,
  67. ADC_MODE_HIFI,
  68. ADC_MODE_LO_HIF,
  69. ADC_MODE_NORMAL,
  70. ADC_MODE_LP,
  71. ADC_MODE_ULP1,
  72. ADC_MODE_ULP2,
  73. };
  74. static u8 tx_mode_bit[] = {
  75. [ADC_MODE_INVALID] = 0x00,
  76. [ADC_MODE_HIFI] = 0x01,
  77. [ADC_MODE_LO_HIF] = 0x02,
  78. [ADC_MODE_NORMAL] = 0x04,
  79. [ADC_MODE_LP] = 0x08,
  80. [ADC_MODE_ULP1] = 0x10,
  81. [ADC_MODE_ULP2] = 0x20,
  82. };
  83. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  84. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  85. static int wcd938x_handle_post_irq(void *data);
  86. static int wcd938x_reset(struct device *dev);
  87. static int wcd938x_reset_low(struct device *dev);
  88. static const struct regmap_irq wcd938x_irqs[WCD938X_NUM_IRQS] = {
  89. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  90. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  91. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  92. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  93. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_SW_DET, 0, 0x10),
  94. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_OCP_INT, 0, 0x20),
  95. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_CNP_INT, 0, 0x40),
  96. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_OCP_INT, 0, 0x80),
  97. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_CNP_INT, 1, 0x01),
  98. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_CNP_INT, 1, 0x02),
  99. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_SCD_INT, 1, 0x04),
  100. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_CNP_INT, 1, 0x08),
  101. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_SCD_INT, 1, 0x10),
  102. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  103. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  104. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  105. REGMAP_IRQ_REG(WCD938X_IRQ_LDORT_SCD_INT, 2, 0x01),
  106. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  107. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  108. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  109. };
  110. static struct regmap_irq_chip wcd938x_regmap_irq_chip = {
  111. .name = "wcd938x",
  112. .irqs = wcd938x_irqs,
  113. .num_irqs = ARRAY_SIZE(wcd938x_irqs),
  114. .num_regs = 3,
  115. .status_base = WCD938X_DIGITAL_INTR_STATUS_0,
  116. .mask_base = WCD938X_DIGITAL_INTR_MASK_0,
  117. .type_base = WCD938X_DIGITAL_INTR_LEVEL_0,
  118. .ack_base = WCD938X_DIGITAL_INTR_CLEAR_0,
  119. .use_ack = 1,
  120. .runtime_pm = false,
  121. .handle_post_irq = wcd938x_handle_post_irq,
  122. .irq_drv_data = NULL,
  123. };
  124. static int wcd938x_handle_post_irq(void *data)
  125. {
  126. struct wcd938x_priv *wcd938x = data;
  127. u32 sts1 = 0, sts2 = 0, sts3 = 0;
  128. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_0, &sts1);
  129. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_1, &sts2);
  130. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_2, &sts3);
  131. wcd938x->tx_swr_dev->slave_irq_pending =
  132. ((sts1 || sts2 || sts3) ? true : false);
  133. return IRQ_HANDLED;
  134. }
  135. static int wcd938x_swr_slv_get_current_bank(struct swr_device *dev, u8 devnum)
  136. {
  137. int ret = 0;
  138. int bank = 0;
  139. ret = swr_read(dev, devnum, SWR_SCP_CONTROL, &bank, 1);
  140. if (ret)
  141. return -EINVAL;
  142. return ((bank & 0x40) ? 1: 0);
  143. }
  144. static int wcd938x_get_clk_rate(int mode)
  145. {
  146. int rate;
  147. switch (mode) {
  148. case ADC_MODE_ULP2:
  149. rate = SWR_CLK_RATE_0P6MHZ;
  150. break;
  151. case ADC_MODE_ULP1:
  152. rate = SWR_CLK_RATE_1P2MHZ;
  153. break;
  154. case ADC_MODE_LP:
  155. rate = SWR_CLK_RATE_4P8MHZ;
  156. break;
  157. case ADC_MODE_NORMAL:
  158. case ADC_MODE_LO_HIF:
  159. case ADC_MODE_HIFI:
  160. case ADC_MODE_INVALID:
  161. default:
  162. rate = SWR_CLK_RATE_9P6MHZ;
  163. break;
  164. }
  165. return rate;
  166. }
  167. static int wcd938x_set_swr_clk_rate(struct snd_soc_component *component,
  168. int rate, int bank)
  169. {
  170. u8 mask = (bank ? 0xF0 : 0x0F);
  171. u8 val = 0;
  172. switch (rate) {
  173. case SWR_CLK_RATE_0P6MHZ:
  174. val = (bank ? 0x60 : 0x06);
  175. break;
  176. case SWR_CLK_RATE_1P2MHZ:
  177. val = (bank ? 0x50 : 0x05);
  178. break;
  179. case SWR_CLK_RATE_2P4MHZ:
  180. val = (bank ? 0x30 : 0x03);
  181. break;
  182. case SWR_CLK_RATE_4P8MHZ:
  183. val = (bank ? 0x10 : 0x01);
  184. break;
  185. case SWR_CLK_RATE_9P6MHZ:
  186. default:
  187. val = 0x00;
  188. break;
  189. }
  190. snd_soc_component_update_bits(component,
  191. WCD938X_DIGITAL_SWR_TX_CLK_RATE,
  192. mask, val);
  193. return 0;
  194. }
  195. static int wcd938x_init_reg(struct snd_soc_component *component)
  196. {
  197. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x0E, 0x0E);
  198. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x80, 0x80);
  199. /* 1 msec delay as per HW requirement */
  200. usleep_range(1000, 1010);
  201. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x40, 0x40);
  202. /* 1 msec delay as per HW requirement */
  203. usleep_range(1000, 1010);
  204. snd_soc_component_update_bits(component, WCD938X_LDORXTX_CONFIG,
  205. 0x10, 0x00);
  206. snd_soc_component_update_bits(component, WCD938X_BIAS_VBG_FINE_ADJ,
  207. 0xF0, 0x80);
  208. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x80, 0x80);
  209. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x40);
  210. /* 10 msec delay as per HW requirement */
  211. usleep_range(10000, 10010);
  212. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x00);
  213. snd_soc_component_update_bits(component,
  214. WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL,
  215. 0xF0, 0x00);
  216. snd_soc_component_update_bits(component,
  217. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW,
  218. 0x1F, 0x15);
  219. snd_soc_component_update_bits(component,
  220. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW,
  221. 0x1F, 0x15);
  222. snd_soc_component_update_bits(component, WCD938X_HPH_REFBUFF_UHQA_CTL,
  223. 0xC0, 0x80);
  224. snd_soc_component_update_bits(component, WCD938X_DIGITAL_CDC_DMIC_CTL,
  225. 0x02, 0x02);
  226. snd_soc_component_update_bits(component,
  227. WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP,
  228. 0xFF, 0x14);
  229. snd_soc_component_update_bits(component,
  230. WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP,
  231. 0x1F, 0x08);
  232. snd_soc_component_update_bits(component,
  233. WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0xFF, 0x55);
  234. snd_soc_component_update_bits(component,
  235. WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0xFF, 0x44);
  236. snd_soc_component_update_bits(component,
  237. WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0xFF, 0x11);
  238. snd_soc_component_update_bits(component,
  239. WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0xFF, 0x00);
  240. snd_soc_component_update_bits(component,
  241. WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0xFF, 0x00);
  242. snd_soc_component_update_bits(component,
  243. WCD938X_MICB1_TEST_CTL_1, 0xE0, 0xE0);
  244. snd_soc_component_update_bits(component,
  245. WCD938X_MICB2_TEST_CTL_1, 0xE0, 0xE0);
  246. snd_soc_component_update_bits(component,
  247. WCD938X_MICB3_TEST_CTL_1, 0xE0, 0xE0);
  248. snd_soc_component_update_bits(component,
  249. WCD938X_MICB4_TEST_CTL_1, 0xE0, 0xE0);
  250. snd_soc_component_update_bits(component,
  251. WCD938X_TX_3_4_TEST_BLK_EN2, 0x01, 0x00);
  252. return 0;
  253. }
  254. static int wcd938x_set_port_params(struct snd_soc_component *component,
  255. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  256. u8 *ch_mask, u32 *ch_rate,
  257. u8 *port_type, u8 path)
  258. {
  259. int i, j;
  260. u8 num_ports = 0;
  261. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  262. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  263. switch (path) {
  264. case CODEC_RX:
  265. map = &wcd938x->rx_port_mapping;
  266. num_ports = wcd938x->num_rx_ports;
  267. break;
  268. case CODEC_TX:
  269. map = &wcd938x->tx_port_mapping;
  270. num_ports = wcd938x->num_tx_ports;
  271. break;
  272. default:
  273. dev_err(component->dev, "%s Invalid path selected %u\n",
  274. __func__, path);
  275. return -EINVAL;
  276. }
  277. for (i = 0; i <= num_ports; i++) {
  278. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  279. if ((*map)[i][j].slave_port_type == slv_prt_type)
  280. goto found;
  281. }
  282. }
  283. found:
  284. if (i > num_ports || j == MAX_CH_PER_PORT) {
  285. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  286. __func__, slv_prt_type);
  287. return -EINVAL;
  288. }
  289. *port_id = i;
  290. *num_ch = (*map)[i][j].num_ch;
  291. *ch_mask = (*map)[i][j].ch_mask;
  292. *ch_rate = (*map)[i][j].ch_rate;
  293. *port_type = (*map)[i][j].master_port_type;
  294. return 0;
  295. }
  296. static int wcd938x_parse_port_mapping(struct device *dev,
  297. char *prop, u8 path)
  298. {
  299. u32 *dt_array, map_size, map_length;
  300. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  301. u32 slave_port_type, master_port_type;
  302. u32 i, ch_iter = 0;
  303. int ret = 0;
  304. u8 *num_ports = NULL;
  305. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  306. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  307. switch (path) {
  308. case CODEC_RX:
  309. map = &wcd938x->rx_port_mapping;
  310. num_ports = &wcd938x->num_rx_ports;
  311. break;
  312. case CODEC_TX:
  313. map = &wcd938x->tx_port_mapping;
  314. num_ports = &wcd938x->num_tx_ports;
  315. break;
  316. default:
  317. dev_err(dev, "%s Invalid path selected %u\n",
  318. __func__, path);
  319. return -EINVAL;
  320. }
  321. if (!of_find_property(dev->of_node, prop,
  322. &map_size)) {
  323. dev_err(dev, "missing port mapping prop %s\n", prop);
  324. ret = -EINVAL;
  325. goto err_port_map;
  326. }
  327. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  328. dt_array = kzalloc(map_size, GFP_KERNEL);
  329. if (!dt_array) {
  330. ret = -ENOMEM;
  331. goto err_alloc;
  332. }
  333. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  334. NUM_SWRS_DT_PARAMS * map_length);
  335. if (ret) {
  336. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  337. __func__, prop);
  338. goto err_pdata_fail;
  339. }
  340. for (i = 0; i < map_length; i++) {
  341. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  342. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  343. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  344. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  345. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  346. if (port_num != old_port_num)
  347. ch_iter = 0;
  348. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  349. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  350. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  351. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  352. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  353. old_port_num = port_num;
  354. }
  355. *num_ports = port_num;
  356. kfree(dt_array);
  357. return 0;
  358. err_pdata_fail:
  359. kfree(dt_array);
  360. err_alloc:
  361. err_port_map:
  362. return ret;
  363. }
  364. static int wcd938x_tx_connect_port(struct snd_soc_component *component,
  365. u8 slv_port_type, int clk_rate,
  366. u8 enable)
  367. {
  368. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  369. u8 port_id, num_ch, ch_mask;
  370. u8 ch_type = 0;
  371. u32 ch_rate;
  372. int slave_ch_idx;
  373. u8 num_port = 1;
  374. int ret = 0;
  375. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  376. &num_ch, &ch_mask, &ch_rate,
  377. &ch_type, CODEC_TX);
  378. if (ret)
  379. return ret;
  380. if (clk_rate)
  381. ch_rate = clk_rate;
  382. slave_ch_idx = wcd938x_slave_get_slave_ch_val(slv_port_type);
  383. if (slave_ch_idx != -EINVAL)
  384. ch_type = wcd938x->tx_master_ch_map[slave_ch_idx];
  385. dev_dbg(component->dev, "%s slv_ch_idx: %d, mstr_ch_type: %d\n",
  386. __func__, slave_ch_idx, ch_type);
  387. if (enable)
  388. ret = swr_connect_port(wcd938x->tx_swr_dev, &port_id,
  389. num_port, &ch_mask, &ch_rate,
  390. &num_ch, &ch_type);
  391. else
  392. ret = swr_disconnect_port(wcd938x->tx_swr_dev, &port_id,
  393. num_port, &ch_mask, &ch_type);
  394. return ret;
  395. }
  396. static int wcd938x_rx_connect_port(struct snd_soc_component *component,
  397. u8 slv_port_type, u8 enable)
  398. {
  399. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  400. u8 port_id, num_ch, ch_mask, port_type;
  401. u32 ch_rate;
  402. u8 num_port = 1;
  403. int ret = 0;
  404. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  405. &num_ch, &ch_mask, &ch_rate,
  406. &port_type, CODEC_RX);
  407. if (ret)
  408. return ret;
  409. if (enable)
  410. ret = swr_connect_port(wcd938x->rx_swr_dev, &port_id,
  411. num_port, &ch_mask, &ch_rate,
  412. &num_ch, &port_type);
  413. else
  414. ret = swr_disconnect_port(wcd938x->rx_swr_dev, &port_id,
  415. num_port, &ch_mask, &port_type);
  416. return ret;
  417. }
  418. static int wcd938x_rx_clk_enable(struct snd_soc_component *component)
  419. {
  420. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  421. if (wcd938x->rx_clk_cnt == 0) {
  422. snd_soc_component_update_bits(component,
  423. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
  424. snd_soc_component_update_bits(component,
  425. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x01);
  426. snd_soc_component_update_bits(component,
  427. WCD938X_DIGITAL_CDC_RX0_CTL, 0x40, 0x00);
  428. snd_soc_component_update_bits(component,
  429. WCD938X_DIGITAL_CDC_RX1_CTL, 0x40, 0x00);
  430. snd_soc_component_update_bits(component,
  431. WCD938X_DIGITAL_CDC_RX2_CTL, 0x40, 0x00);
  432. snd_soc_component_update_bits(component,
  433. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
  434. snd_soc_component_update_bits(component,
  435. WCD938X_AUX_AUXPA, 0x10, 0x10);
  436. }
  437. wcd938x->rx_clk_cnt++;
  438. return 0;
  439. }
  440. static int wcd938x_rx_clk_disable(struct snd_soc_component *component)
  441. {
  442. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  443. wcd938x->rx_clk_cnt--;
  444. if (wcd938x->rx_clk_cnt == 0) {
  445. snd_soc_component_update_bits(component,
  446. WCD938X_ANA_RX_SUPPLIES, 0x40, 0x00);
  447. snd_soc_component_update_bits(component,
  448. WCD938X_ANA_RX_SUPPLIES, 0x80, 0x00);
  449. snd_soc_component_update_bits(component,
  450. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x00);
  451. snd_soc_component_update_bits(component,
  452. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x00);
  453. snd_soc_component_update_bits(component,
  454. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x00);
  455. }
  456. return 0;
  457. }
  458. /*
  459. * wcd938x_soc_get_mbhc: get wcd938x_mbhc handle of corresponding component
  460. * @component: handle to snd_soc_component *
  461. *
  462. * return wcd938x_mbhc handle or error code in case of failure
  463. */
  464. struct wcd938x_mbhc *wcd938x_soc_get_mbhc(struct snd_soc_component *component)
  465. {
  466. struct wcd938x_priv *wcd938x;
  467. if (!component) {
  468. pr_err("%s: Invalid params, NULL component\n", __func__);
  469. return NULL;
  470. }
  471. wcd938x = snd_soc_component_get_drvdata(component);
  472. if (!wcd938x) {
  473. pr_err("%s: wcd938x is NULL\n", __func__);
  474. return NULL;
  475. }
  476. return wcd938x->mbhc;
  477. }
  478. EXPORT_SYMBOL(wcd938x_soc_get_mbhc);
  479. static int wcd938x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  480. struct snd_kcontrol *kcontrol,
  481. int event)
  482. {
  483. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  484. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  485. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  486. w->name, event);
  487. switch (event) {
  488. case SND_SOC_DAPM_PRE_PMU:
  489. wcd938x_rx_clk_enable(component);
  490. snd_soc_component_update_bits(component,
  491. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  492. snd_soc_component_update_bits(component,
  493. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  494. snd_soc_component_update_bits(component,
  495. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  496. break;
  497. case SND_SOC_DAPM_POST_PMU:
  498. snd_soc_component_update_bits(component,
  499. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x0F, 0x02);
  500. if (wcd938x->comp1_enable) {
  501. snd_soc_component_update_bits(component,
  502. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x02);
  503. /* 5msec compander delay as per HW requirement */
  504. if (!wcd938x->comp2_enable ||
  505. (snd_soc_component_read32(component,
  506. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x01))
  507. usleep_range(5000, 5010);
  508. snd_soc_component_update_bits(component,
  509. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  510. } else {
  511. snd_soc_component_update_bits(component,
  512. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  513. 0x02, 0x00);
  514. snd_soc_component_update_bits(component,
  515. WCD938X_HPH_L_EN, 0x20, 0x20);
  516. }
  517. break;
  518. case SND_SOC_DAPM_POST_PMD:
  519. snd_soc_component_update_bits(component,
  520. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  521. 0x0F, 0x01);
  522. break;
  523. }
  524. return 0;
  525. }
  526. static int wcd938x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  527. struct snd_kcontrol *kcontrol,
  528. int event)
  529. {
  530. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  531. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  532. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  533. w->name, event);
  534. switch (event) {
  535. case SND_SOC_DAPM_PRE_PMU:
  536. wcd938x_rx_clk_enable(component);
  537. snd_soc_component_update_bits(component,
  538. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
  539. snd_soc_component_update_bits(component,
  540. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x08, 0x08);
  541. snd_soc_component_update_bits(component,
  542. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  543. break;
  544. case SND_SOC_DAPM_POST_PMU:
  545. snd_soc_component_update_bits(component,
  546. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x0F, 0x02);
  547. if (wcd938x->comp2_enable) {
  548. snd_soc_component_update_bits(component,
  549. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x01, 0x01);
  550. /* 5msec compander delay as per HW requirement */
  551. if (!wcd938x->comp1_enable ||
  552. (snd_soc_component_read32(component,
  553. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x02))
  554. usleep_range(5000, 5010);
  555. snd_soc_component_update_bits(component,
  556. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  557. } else {
  558. snd_soc_component_update_bits(component,
  559. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  560. 0x01, 0x00);
  561. snd_soc_component_update_bits(component,
  562. WCD938X_HPH_R_EN, 0x20, 0x20);
  563. }
  564. break;
  565. case SND_SOC_DAPM_POST_PMD:
  566. snd_soc_component_update_bits(component,
  567. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  568. 0x0F, 0x01);
  569. break;
  570. }
  571. return 0;
  572. }
  573. static int wcd938x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  574. struct snd_kcontrol *kcontrol,
  575. int event)
  576. {
  577. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  578. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  579. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  580. w->name, event);
  581. switch (event) {
  582. case SND_SOC_DAPM_PRE_PMU:
  583. wcd938x_rx_clk_enable(component);
  584. wcd938x->ear_rx_path =
  585. snd_soc_component_read32(
  586. component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
  587. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  588. snd_soc_component_update_bits(component,
  589. WCD938X_EAR_EAR_DAC_CON, 0x80, 0x00);
  590. snd_soc_component_update_bits(component,
  591. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x01);
  592. snd_soc_component_update_bits(component,
  593. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x04);
  594. snd_soc_component_update_bits(component,
  595. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  596. } else {
  597. snd_soc_component_update_bits(component,
  598. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  599. snd_soc_component_update_bits(component,
  600. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  601. snd_soc_component_update_bits(component,
  602. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x02);
  603. }
  604. /* 5 msec delay as per HW requirement */
  605. usleep_range(5000, 5010);
  606. if (wcd938x->flyback_cur_det_disable == 0)
  607. snd_soc_component_update_bits(component,
  608. WCD938X_FLYBACK_EN,
  609. 0x04, 0x00);
  610. wcd938x->flyback_cur_det_disable++;
  611. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  612. WCD_CLSH_EVENT_PRE_DAC,
  613. WCD_CLSH_STATE_EAR,
  614. wcd938x->hph_mode);
  615. break;
  616. case SND_SOC_DAPM_POST_PMD:
  617. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  618. snd_soc_component_update_bits(component,
  619. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x00);
  620. snd_soc_component_update_bits(component,
  621. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  622. } else {
  623. snd_soc_component_update_bits(component,
  624. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x00);
  625. snd_soc_component_update_bits(component,
  626. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x00);
  627. snd_soc_component_update_bits(component,
  628. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x00);
  629. }
  630. snd_soc_component_update_bits(component,
  631. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  632. snd_soc_component_update_bits(component,
  633. WCD938X_EAR_EAR_DAC_CON, 0x80, 0x80);
  634. break;
  635. };
  636. return 0;
  637. }
  638. static int wcd938x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  639. struct snd_kcontrol *kcontrol,
  640. int event)
  641. {
  642. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  643. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  644. int ret = 0;
  645. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  646. w->name, event);
  647. switch (event) {
  648. case SND_SOC_DAPM_PRE_PMU:
  649. wcd938x_rx_clk_enable(component);
  650. snd_soc_component_update_bits(component,
  651. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x04);
  652. snd_soc_component_update_bits(component,
  653. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x04);
  654. snd_soc_component_update_bits(component,
  655. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x01);
  656. if (wcd938x->flyback_cur_det_disable == 0)
  657. snd_soc_component_update_bits(component,
  658. WCD938X_FLYBACK_EN,
  659. 0x04, 0x00);
  660. wcd938x->flyback_cur_det_disable++;
  661. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  662. WCD_CLSH_EVENT_PRE_DAC,
  663. WCD_CLSH_STATE_AUX,
  664. wcd938x->hph_mode);
  665. break;
  666. case SND_SOC_DAPM_POST_PMD:
  667. snd_soc_component_update_bits(component,
  668. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x00);
  669. break;
  670. };
  671. return ret;
  672. }
  673. static int wcd938x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  674. struct snd_kcontrol *kcontrol,
  675. int event)
  676. {
  677. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  678. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  679. int ret = 0;
  680. int hph_mode = wcd938x->hph_mode;
  681. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  682. w->name, event);
  683. switch (event) {
  684. case SND_SOC_DAPM_PRE_PMU:
  685. if (wcd938x->ldoh)
  686. snd_soc_component_update_bits(component,
  687. WCD938X_LDOH_MODE,
  688. 0x80, 0x80);
  689. if (wcd938x->update_wcd_event)
  690. wcd938x->update_wcd_event(wcd938x->handle,
  691. WCD_BOLERO_EVT_RX_MUTE,
  692. (WCD_RX2 << 0x10 | 0x1));
  693. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  694. wcd938x->rx_swr_dev->dev_num,
  695. true);
  696. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  697. WCD_CLSH_EVENT_PRE_DAC,
  698. WCD_CLSH_STATE_HPHR,
  699. hph_mode);
  700. wcd_clsh_set_hph_mode(component, CLS_H_HIFI);
  701. if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
  702. hph_mode == CLS_H_ULP) {
  703. snd_soc_component_update_bits(component,
  704. WCD938X_HPH_REFBUFF_LP_CTL, 0x01, 0x01);
  705. }
  706. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  707. 0x10, 0x10);
  708. wcd_clsh_set_hph_mode(component, hph_mode);
  709. /* 100 usec delay as per HW requirement */
  710. usleep_range(100, 110);
  711. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  712. snd_soc_component_update_bits(component,
  713. WCD938X_DIGITAL_PDM_WD_CTL1, 0x17, 0x13);
  714. break;
  715. case SND_SOC_DAPM_POST_PMU:
  716. /*
  717. * 7ms sleep is required if compander is enabled as per
  718. * HW requirement. If compander is disabled, then
  719. * 20ms delay is required.
  720. */
  721. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  722. if (!wcd938x->comp2_enable)
  723. usleep_range(20000, 20100);
  724. else
  725. usleep_range(7000, 7100);
  726. if (hph_mode == CLS_H_LP ||
  727. hph_mode == CLS_H_LOHIFI ||
  728. hph_mode == CLS_H_ULP)
  729. snd_soc_component_update_bits(component,
  730. WCD938X_HPH_REFBUFF_LP_CTL, 0x01,
  731. 0x00);
  732. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  733. }
  734. snd_soc_component_update_bits(component,
  735. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  736. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  737. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  738. snd_soc_component_update_bits(component,
  739. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  740. if (wcd938x->update_wcd_event)
  741. wcd938x->update_wcd_event(wcd938x->handle,
  742. WCD_BOLERO_EVT_RX_MUTE,
  743. (WCD_RX2 << 0x10));
  744. wcd_enable_irq(&wcd938x->irq_info,
  745. WCD938X_IRQ_HPHR_PDM_WD_INT);
  746. break;
  747. case SND_SOC_DAPM_PRE_PMD:
  748. if (wcd938x->update_wcd_event)
  749. wcd938x->update_wcd_event(wcd938x->handle,
  750. WCD_BOLERO_EVT_RX_MUTE,
  751. (WCD_RX2 << 0x10 | 0x1));
  752. wcd_disable_irq(&wcd938x->irq_info,
  753. WCD938X_IRQ_HPHR_PDM_WD_INT);
  754. if (wcd938x->update_wcd_event && wcd938x->comp2_enable)
  755. wcd938x->update_wcd_event(wcd938x->handle,
  756. WCD_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  757. (WCD_RX2 << 0x10));
  758. /*
  759. * 7ms sleep is required if compander is enabled as per
  760. * HW requirement. If compander is disabled, then
  761. * 20ms delay is required.
  762. */
  763. if (!wcd938x->comp2_enable)
  764. usleep_range(20000, 20100);
  765. else
  766. usleep_range(7000, 7100);
  767. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  768. 0x40, 0x00);
  769. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  770. WCD_EVENT_PRE_HPHR_PA_OFF,
  771. &wcd938x->mbhc->wcd_mbhc);
  772. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  773. break;
  774. case SND_SOC_DAPM_POST_PMD:
  775. /*
  776. * 7ms sleep is required if compander is enabled as per
  777. * HW requirement. If compander is disabled, then
  778. * 20ms delay is required.
  779. */
  780. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  781. if (!wcd938x->comp2_enable)
  782. usleep_range(20000, 20100);
  783. else
  784. usleep_range(7000, 7100);
  785. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  786. }
  787. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  788. WCD_EVENT_POST_HPHR_PA_OFF,
  789. &wcd938x->mbhc->wcd_mbhc);
  790. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  791. 0x10, 0x00);
  792. snd_soc_component_update_bits(component,
  793. WCD938X_DIGITAL_PDM_WD_CTL1, 0x17, 0x00);
  794. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  795. WCD_CLSH_EVENT_POST_PA,
  796. WCD_CLSH_STATE_HPHR,
  797. hph_mode);
  798. if (wcd938x->ldoh)
  799. snd_soc_component_update_bits(component,
  800. WCD938X_LDOH_MODE,
  801. 0x80, 0x00);
  802. break;
  803. };
  804. return ret;
  805. }
  806. static int wcd938x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  807. struct snd_kcontrol *kcontrol,
  808. int event)
  809. {
  810. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  811. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  812. int ret = 0;
  813. int hph_mode = wcd938x->hph_mode;
  814. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  815. w->name, event);
  816. switch (event) {
  817. case SND_SOC_DAPM_PRE_PMU:
  818. if (wcd938x->ldoh)
  819. snd_soc_component_update_bits(component,
  820. WCD938X_LDOH_MODE,
  821. 0x80, 0x80);
  822. if (wcd938x->update_wcd_event)
  823. wcd938x->update_wcd_event(wcd938x->handle,
  824. WCD_BOLERO_EVT_RX_MUTE,
  825. (WCD_RX1 << 0x10 | 0x01));
  826. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  827. wcd938x->rx_swr_dev->dev_num,
  828. true);
  829. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  830. WCD_CLSH_EVENT_PRE_DAC,
  831. WCD_CLSH_STATE_HPHL,
  832. hph_mode);
  833. wcd_clsh_set_hph_mode(component, CLS_H_HIFI);
  834. if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
  835. hph_mode == CLS_H_ULP) {
  836. snd_soc_component_update_bits(component,
  837. WCD938X_HPH_REFBUFF_LP_CTL, 0x01, 0x01);
  838. }
  839. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  840. 0x20, 0x20);
  841. wcd_clsh_set_hph_mode(component, hph_mode);
  842. /* 100 usec delay as per HW requirement */
  843. usleep_range(100, 110);
  844. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  845. snd_soc_component_update_bits(component,
  846. WCD938X_DIGITAL_PDM_WD_CTL0, 0x17, 0x13);
  847. break;
  848. case SND_SOC_DAPM_POST_PMU:
  849. /*
  850. * 7ms sleep is required if compander is enabled as per
  851. * HW requirement. If compander is disabled, then
  852. * 20ms delay is required.
  853. */
  854. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  855. if (!wcd938x->comp1_enable)
  856. usleep_range(20000, 20100);
  857. else
  858. usleep_range(7000, 7100);
  859. if (hph_mode == CLS_H_LP ||
  860. hph_mode == CLS_H_LOHIFI ||
  861. hph_mode == CLS_H_ULP)
  862. snd_soc_component_update_bits(component,
  863. WCD938X_HPH_REFBUFF_LP_CTL,
  864. 0x01, 0x00);
  865. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  866. }
  867. snd_soc_component_update_bits(component,
  868. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  869. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  870. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  871. snd_soc_component_update_bits(component,
  872. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  873. if (wcd938x->update_wcd_event)
  874. wcd938x->update_wcd_event(wcd938x->handle,
  875. WCD_BOLERO_EVT_RX_MUTE,
  876. (WCD_RX1 << 0x10));
  877. wcd_enable_irq(&wcd938x->irq_info,
  878. WCD938X_IRQ_HPHL_PDM_WD_INT);
  879. break;
  880. case SND_SOC_DAPM_PRE_PMD:
  881. if (wcd938x->update_wcd_event)
  882. wcd938x->update_wcd_event(wcd938x->handle,
  883. WCD_BOLERO_EVT_RX_MUTE,
  884. (WCD_RX1 << 0x10 | 0x1));
  885. wcd_disable_irq(&wcd938x->irq_info,
  886. WCD938X_IRQ_HPHL_PDM_WD_INT);
  887. if (wcd938x->update_wcd_event && wcd938x->comp1_enable)
  888. wcd938x->update_wcd_event(wcd938x->handle,
  889. WCD_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  890. (WCD_RX1 << 0x10));
  891. /*
  892. * 7ms sleep is required if compander is enabled as per
  893. * HW requirement. If compander is disabled, then
  894. * 20ms delay is required.
  895. */
  896. if (!wcd938x->comp1_enable)
  897. usleep_range(20000, 20100);
  898. else
  899. usleep_range(7000, 7100);
  900. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  901. 0x80, 0x00);
  902. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  903. WCD_EVENT_PRE_HPHL_PA_OFF,
  904. &wcd938x->mbhc->wcd_mbhc);
  905. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  906. break;
  907. case SND_SOC_DAPM_POST_PMD:
  908. /*
  909. * 7ms sleep is required if compander is enabled as per
  910. * HW requirement. If compander is disabled, then
  911. * 20ms delay is required.
  912. */
  913. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  914. if (!wcd938x->comp1_enable)
  915. usleep_range(21000, 21100);
  916. else
  917. usleep_range(7000, 7100);
  918. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  919. }
  920. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  921. WCD_EVENT_POST_HPHL_PA_OFF,
  922. &wcd938x->mbhc->wcd_mbhc);
  923. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  924. 0x20, 0x00);
  925. snd_soc_component_update_bits(component,
  926. WCD938X_DIGITAL_PDM_WD_CTL0, 0x17, 0x00);
  927. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  928. WCD_CLSH_EVENT_POST_PA,
  929. WCD_CLSH_STATE_HPHL,
  930. hph_mode);
  931. if (wcd938x->ldoh)
  932. snd_soc_component_update_bits(component,
  933. WCD938X_LDOH_MODE,
  934. 0x80, 0x00);
  935. break;
  936. };
  937. return ret;
  938. }
  939. static int wcd938x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  940. struct snd_kcontrol *kcontrol,
  941. int event)
  942. {
  943. struct snd_soc_component *component =
  944. snd_soc_dapm_to_component(w->dapm);
  945. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  946. int hph_mode = wcd938x->hph_mode;
  947. int ret = 0;
  948. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  949. w->name, event);
  950. switch (event) {
  951. case SND_SOC_DAPM_PRE_PMU:
  952. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  953. wcd938x->rx_swr_dev->dev_num,
  954. true);
  955. snd_soc_component_update_bits(component,
  956. WCD938X_DIGITAL_PDM_WD_CTL2, 0x05, 0x05);
  957. break;
  958. case SND_SOC_DAPM_POST_PMU:
  959. /* 1 msec delay as per HW requirement */
  960. usleep_range(1000, 1010);
  961. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  962. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  963. snd_soc_component_update_bits(component,
  964. WCD938X_ANA_RX_SUPPLIES,
  965. 0x02, 0x02);
  966. if (wcd938x->update_wcd_event)
  967. wcd938x->update_wcd_event(wcd938x->handle,
  968. WCD_BOLERO_EVT_RX_MUTE,
  969. (WCD_RX3 << 0x10));
  970. wcd_enable_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT);
  971. break;
  972. case SND_SOC_DAPM_PRE_PMD:
  973. wcd_disable_irq(&wcd938x->irq_info,
  974. WCD938X_IRQ_AUX_PDM_WD_INT);
  975. if (wcd938x->update_wcd_event)
  976. wcd938x->update_wcd_event(wcd938x->handle,
  977. WCD_BOLERO_EVT_RX_MUTE,
  978. (WCD_RX3 << 0x10 | 0x1));
  979. break;
  980. case SND_SOC_DAPM_POST_PMD:
  981. /* 1 msec delay as per HW requirement */
  982. usleep_range(1000, 1010);
  983. snd_soc_component_update_bits(component,
  984. WCD938X_DIGITAL_PDM_WD_CTL2, 0x05, 0x00);
  985. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  986. WCD_CLSH_EVENT_POST_PA,
  987. WCD_CLSH_STATE_AUX,
  988. hph_mode);
  989. wcd938x->flyback_cur_det_disable--;
  990. if (wcd938x->flyback_cur_det_disable == 0)
  991. snd_soc_component_update_bits(component,
  992. WCD938X_FLYBACK_EN,
  993. 0x04, 0x04);
  994. break;
  995. };
  996. return ret;
  997. }
  998. static int wcd938x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  999. struct snd_kcontrol *kcontrol,
  1000. int event)
  1001. {
  1002. struct snd_soc_component *component =
  1003. snd_soc_dapm_to_component(w->dapm);
  1004. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1005. int hph_mode = wcd938x->hph_mode;
  1006. int ret = 0;
  1007. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1008. w->name, event);
  1009. switch (event) {
  1010. case SND_SOC_DAPM_PRE_PMU:
  1011. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  1012. wcd938x->rx_swr_dev->dev_num,
  1013. true);
  1014. /*
  1015. * Enable watchdog interrupt for HPHL or AUX
  1016. * depending on mux value
  1017. */
  1018. wcd938x->ear_rx_path =
  1019. snd_soc_component_read32(
  1020. component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
  1021. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  1022. snd_soc_component_update_bits(component,
  1023. WCD938X_DIGITAL_PDM_WD_CTL2,
  1024. 0x05, 0x05);
  1025. else
  1026. snd_soc_component_update_bits(component,
  1027. WCD938X_DIGITAL_PDM_WD_CTL0,
  1028. 0x17, 0x13);
  1029. if (!wcd938x->comp1_enable)
  1030. snd_soc_component_update_bits(component,
  1031. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  1032. break;
  1033. case SND_SOC_DAPM_POST_PMU:
  1034. /* 6 msec delay as per HW requirement */
  1035. usleep_range(6000, 6010);
  1036. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  1037. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  1038. snd_soc_component_update_bits(component,
  1039. WCD938X_ANA_RX_SUPPLIES,
  1040. 0x02, 0x02);
  1041. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  1042. if (wcd938x->update_wcd_event)
  1043. wcd938x->update_wcd_event(wcd938x->handle,
  1044. WCD_BOLERO_EVT_RX_MUTE,
  1045. (WCD_RX3 << 0x10));
  1046. wcd_enable_irq(&wcd938x->irq_info,
  1047. WCD938X_IRQ_AUX_PDM_WD_INT);
  1048. } else {
  1049. if (wcd938x->update_wcd_event)
  1050. wcd938x->update_wcd_event(wcd938x->handle,
  1051. WCD_BOLERO_EVT_RX_MUTE,
  1052. (WCD_RX1 << 0x10));
  1053. wcd_enable_irq(&wcd938x->irq_info,
  1054. WCD938X_IRQ_HPHL_PDM_WD_INT);
  1055. }
  1056. break;
  1057. case SND_SOC_DAPM_PRE_PMD:
  1058. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  1059. wcd_disable_irq(&wcd938x->irq_info,
  1060. WCD938X_IRQ_AUX_PDM_WD_INT);
  1061. if (wcd938x->update_wcd_event)
  1062. wcd938x->update_wcd_event(wcd938x->handle,
  1063. WCD_BOLERO_EVT_RX_MUTE,
  1064. (WCD_RX3 << 0x10 | 0x1));
  1065. } else {
  1066. wcd_disable_irq(&wcd938x->irq_info,
  1067. WCD938X_IRQ_HPHL_PDM_WD_INT);
  1068. if (wcd938x->update_wcd_event)
  1069. wcd938x->update_wcd_event(wcd938x->handle,
  1070. WCD_BOLERO_EVT_RX_MUTE,
  1071. (WCD_RX1 << 0x10 | 0x1));
  1072. }
  1073. break;
  1074. case SND_SOC_DAPM_POST_PMD:
  1075. if (!wcd938x->comp1_enable)
  1076. snd_soc_component_update_bits(component,
  1077. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  1078. /* 7 msec delay as per HW requirement */
  1079. usleep_range(7000, 7010);
  1080. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  1081. snd_soc_component_update_bits(component,
  1082. WCD938X_DIGITAL_PDM_WD_CTL2,
  1083. 0x05, 0x00);
  1084. else
  1085. snd_soc_component_update_bits(component,
  1086. WCD938X_DIGITAL_PDM_WD_CTL0,
  1087. 0x17, 0x00);
  1088. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  1089. WCD_CLSH_EVENT_POST_PA,
  1090. WCD_CLSH_STATE_EAR,
  1091. hph_mode);
  1092. wcd938x->flyback_cur_det_disable--;
  1093. if (wcd938x->flyback_cur_det_disable == 0)
  1094. snd_soc_component_update_bits(component,
  1095. WCD938X_FLYBACK_EN,
  1096. 0x04, 0x04);
  1097. break;
  1098. };
  1099. return ret;
  1100. }
  1101. static int wcd938x_enable_clsh(struct snd_soc_dapm_widget *w,
  1102. struct snd_kcontrol *kcontrol,
  1103. int event)
  1104. {
  1105. struct snd_soc_component *component =
  1106. snd_soc_dapm_to_component(w->dapm);
  1107. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1108. int mode = wcd938x->hph_mode;
  1109. int ret = 0;
  1110. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1111. w->name, event);
  1112. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  1113. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  1114. wcd938x_rx_connect_port(component, CLSH,
  1115. SND_SOC_DAPM_EVENT_ON(event));
  1116. }
  1117. if (SND_SOC_DAPM_EVENT_OFF(event))
  1118. ret = swr_slvdev_datapath_control(
  1119. wcd938x->rx_swr_dev,
  1120. wcd938x->rx_swr_dev->dev_num,
  1121. false);
  1122. return ret;
  1123. }
  1124. static int wcd938x_enable_rx1(struct snd_soc_dapm_widget *w,
  1125. struct snd_kcontrol *kcontrol,
  1126. int event)
  1127. {
  1128. struct snd_soc_component *component =
  1129. snd_soc_dapm_to_component(w->dapm);
  1130. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1131. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1132. w->name, event);
  1133. switch (event) {
  1134. case SND_SOC_DAPM_PRE_PMU:
  1135. wcd938x_rx_connect_port(component, HPH_L, true);
  1136. if (wcd938x->comp1_enable)
  1137. wcd938x_rx_connect_port(component, COMP_L, true);
  1138. break;
  1139. case SND_SOC_DAPM_POST_PMD:
  1140. wcd938x_rx_connect_port(component, HPH_L, false);
  1141. if (wcd938x->comp1_enable)
  1142. wcd938x_rx_connect_port(component, COMP_L, false);
  1143. wcd938x_rx_clk_disable(component);
  1144. snd_soc_component_update_bits(component,
  1145. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  1146. 0x01, 0x00);
  1147. break;
  1148. };
  1149. return 0;
  1150. }
  1151. static int wcd938x_enable_rx2(struct snd_soc_dapm_widget *w,
  1152. struct snd_kcontrol *kcontrol, int event)
  1153. {
  1154. struct snd_soc_component *component =
  1155. snd_soc_dapm_to_component(w->dapm);
  1156. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1157. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1158. w->name, event);
  1159. switch (event) {
  1160. case SND_SOC_DAPM_PRE_PMU:
  1161. wcd938x_rx_connect_port(component, HPH_R, true);
  1162. if (wcd938x->comp2_enable)
  1163. wcd938x_rx_connect_port(component, COMP_R, true);
  1164. break;
  1165. case SND_SOC_DAPM_POST_PMD:
  1166. wcd938x_rx_connect_port(component, HPH_R, false);
  1167. if (wcd938x->comp2_enable)
  1168. wcd938x_rx_connect_port(component, COMP_R, false);
  1169. wcd938x_rx_clk_disable(component);
  1170. snd_soc_component_update_bits(component,
  1171. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  1172. 0x02, 0x00);
  1173. break;
  1174. };
  1175. return 0;
  1176. }
  1177. static int wcd938x_enable_rx3(struct snd_soc_dapm_widget *w,
  1178. struct snd_kcontrol *kcontrol,
  1179. int event)
  1180. {
  1181. struct snd_soc_component *component =
  1182. snd_soc_dapm_to_component(w->dapm);
  1183. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1184. w->name, event);
  1185. switch (event) {
  1186. case SND_SOC_DAPM_PRE_PMU:
  1187. wcd938x_rx_connect_port(component, LO, true);
  1188. break;
  1189. case SND_SOC_DAPM_POST_PMD:
  1190. wcd938x_rx_connect_port(component, LO, false);
  1191. /* 6 msec delay as per HW requirement */
  1192. usleep_range(6000, 6010);
  1193. wcd938x_rx_clk_disable(component);
  1194. snd_soc_component_update_bits(component,
  1195. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  1196. break;
  1197. }
  1198. return 0;
  1199. }
  1200. static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  1201. struct snd_kcontrol *kcontrol,
  1202. int event)
  1203. {
  1204. struct snd_soc_component *component =
  1205. snd_soc_dapm_to_component(w->dapm);
  1206. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1207. u16 dmic_clk_reg, dmic_clk_en_reg;
  1208. s32 *dmic_clk_cnt;
  1209. u8 dmic_ctl_shift = 0;
  1210. u8 dmic_clk_shift = 0;
  1211. u8 dmic_clk_mask = 0;
  1212. u16 dmic2_left_en = 0;
  1213. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1214. w->name, event);
  1215. switch (w->shift) {
  1216. case 0:
  1217. case 1:
  1218. dmic_clk_cnt = &(wcd938x->dmic_0_1_clk_cnt);
  1219. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
  1220. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC1_CTL;
  1221. dmic_clk_mask = 0x0F;
  1222. dmic_clk_shift = 0x00;
  1223. dmic_ctl_shift = 0x00;
  1224. break;
  1225. case 2:
  1226. dmic2_left_en = WCD938X_DIGITAL_CDC_DMIC2_CTL;
  1227. case 3:
  1228. dmic_clk_cnt = &(wcd938x->dmic_2_3_clk_cnt);
  1229. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
  1230. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC2_CTL;
  1231. dmic_clk_mask = 0xF0;
  1232. dmic_clk_shift = 0x04;
  1233. dmic_ctl_shift = 0x01;
  1234. break;
  1235. case 4:
  1236. case 5:
  1237. dmic_clk_cnt = &(wcd938x->dmic_4_5_clk_cnt);
  1238. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
  1239. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC3_CTL;
  1240. dmic_clk_mask = 0x0F;
  1241. dmic_clk_shift = 0x00;
  1242. dmic_ctl_shift = 0x02;
  1243. break;
  1244. case 6:
  1245. case 7:
  1246. dmic_clk_cnt = &(wcd938x->dmic_6_7_clk_cnt);
  1247. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
  1248. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC4_CTL;
  1249. dmic_clk_mask = 0xF0;
  1250. dmic_clk_shift = 0x04;
  1251. dmic_ctl_shift = 0x03;
  1252. break;
  1253. default:
  1254. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  1255. __func__);
  1256. return -EINVAL;
  1257. };
  1258. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  1259. __func__, event, (w->shift +1), *dmic_clk_cnt);
  1260. switch (event) {
  1261. case SND_SOC_DAPM_PRE_PMU:
  1262. snd_soc_component_update_bits(component,
  1263. WCD938X_DIGITAL_CDC_AMIC_CTL,
  1264. (0x01 << dmic_ctl_shift), 0x00);
  1265. /* 250us sleep as per HW requirement */
  1266. usleep_range(250, 260);
  1267. if (dmic2_left_en)
  1268. snd_soc_component_update_bits(component,
  1269. dmic2_left_en, 0x80, 0x80);
  1270. /* Setting DMIC clock rate to 2.4MHz */
  1271. snd_soc_component_update_bits(component,
  1272. dmic_clk_reg, dmic_clk_mask,
  1273. (0x03 << dmic_clk_shift));
  1274. snd_soc_component_update_bits(component,
  1275. dmic_clk_en_reg, 0x08, 0x08);
  1276. /* enable clock scaling */
  1277. snd_soc_component_update_bits(component,
  1278. WCD938X_DIGITAL_CDC_DMIC_CTL, 0x06, 0x06);
  1279. wcd938x_tx_connect_port(component, DMIC0 + (w->shift),
  1280. SWR_CLK_RATE_2P4MHZ, true);
  1281. break;
  1282. case SND_SOC_DAPM_POST_PMD:
  1283. wcd938x_tx_connect_port(component, DMIC0 + (w->shift), 0,
  1284. false);
  1285. snd_soc_component_update_bits(component,
  1286. WCD938X_DIGITAL_CDC_AMIC_CTL,
  1287. (0x01 << dmic_ctl_shift),
  1288. (0x01 << dmic_ctl_shift));
  1289. if (dmic2_left_en)
  1290. snd_soc_component_update_bits(component,
  1291. dmic2_left_en, 0x80, 0x00);
  1292. snd_soc_component_update_bits(component,
  1293. dmic_clk_en_reg, 0x08, 0x00);
  1294. break;
  1295. };
  1296. return 0;
  1297. }
  1298. /*
  1299. * wcd938x_get_micb_vout_ctl_val: converts micbias from volts to register value
  1300. * @micb_mv: micbias in mv
  1301. *
  1302. * return register value converted
  1303. */
  1304. int wcd938x_get_micb_vout_ctl_val(u32 micb_mv)
  1305. {
  1306. /* min micbias voltage is 1V and maximum is 2.85V */
  1307. if (micb_mv < 1000 || micb_mv > 2850) {
  1308. pr_err("%s: unsupported micbias voltage\n", __func__);
  1309. return -EINVAL;
  1310. }
  1311. return (micb_mv - 1000) / 50;
  1312. }
  1313. EXPORT_SYMBOL(wcd938x_get_micb_vout_ctl_val);
  1314. /*
  1315. * wcd938x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  1316. * @component: handle to snd_soc_component *
  1317. * @req_volt: micbias voltage to be set
  1318. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  1319. *
  1320. * return 0 if adjustment is success or error code in case of failure
  1321. */
  1322. int wcd938x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  1323. int req_volt, int micb_num)
  1324. {
  1325. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1326. int cur_vout_ctl, req_vout_ctl;
  1327. int micb_reg, micb_val, micb_en;
  1328. int ret = 0;
  1329. switch (micb_num) {
  1330. case MIC_BIAS_1:
  1331. micb_reg = WCD938X_ANA_MICB1;
  1332. break;
  1333. case MIC_BIAS_2:
  1334. micb_reg = WCD938X_ANA_MICB2;
  1335. break;
  1336. case MIC_BIAS_3:
  1337. micb_reg = WCD938X_ANA_MICB3;
  1338. break;
  1339. case MIC_BIAS_4:
  1340. micb_reg = WCD938X_ANA_MICB4;
  1341. break;
  1342. default:
  1343. return -EINVAL;
  1344. }
  1345. mutex_lock(&wcd938x->micb_lock);
  1346. /*
  1347. * If requested micbias voltage is same as current micbias
  1348. * voltage, then just return. Otherwise, adjust voltage as
  1349. * per requested value. If micbias is already enabled, then
  1350. * to avoid slow micbias ramp-up or down enable pull-up
  1351. * momentarily, change the micbias value and then re-enable
  1352. * micbias.
  1353. */
  1354. micb_val = snd_soc_component_read32(component, micb_reg);
  1355. micb_en = (micb_val & 0xC0) >> 6;
  1356. cur_vout_ctl = micb_val & 0x3F;
  1357. req_vout_ctl = wcd938x_get_micb_vout_ctl_val(req_volt);
  1358. if (req_vout_ctl < 0) {
  1359. ret = -EINVAL;
  1360. goto exit;
  1361. }
  1362. if (cur_vout_ctl == req_vout_ctl) {
  1363. ret = 0;
  1364. goto exit;
  1365. }
  1366. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  1367. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  1368. req_volt, micb_en);
  1369. if (micb_en == 0x1)
  1370. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  1371. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  1372. if (micb_en == 0x1) {
  1373. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  1374. /*
  1375. * Add 2ms delay as per HW requirement after enabling
  1376. * micbias
  1377. */
  1378. usleep_range(2000, 2100);
  1379. }
  1380. exit:
  1381. mutex_unlock(&wcd938x->micb_lock);
  1382. return ret;
  1383. }
  1384. EXPORT_SYMBOL(wcd938x_mbhc_micb_adjust_voltage);
  1385. static int wcd938x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1386. struct snd_kcontrol *kcontrol,
  1387. int event)
  1388. {
  1389. struct snd_soc_component *component =
  1390. snd_soc_dapm_to_component(w->dapm);
  1391. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1392. int ret = 0;
  1393. int bank = 0;
  1394. u8 mode = 0;
  1395. int i = 0;
  1396. int rate = 0;
  1397. bank = (wcd938x_swr_slv_get_current_bank(wcd938x->tx_swr_dev,
  1398. wcd938x->tx_swr_dev->dev_num) ? 0 : 1);
  1399. switch (event) {
  1400. case SND_SOC_DAPM_PRE_PMU:
  1401. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1402. if (test_bit(WCD_ADC1, &wcd938x->status_mask))
  1403. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC1]];
  1404. if (test_bit(WCD_ADC2, &wcd938x->status_mask))
  1405. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC2]];
  1406. if (test_bit(WCD_ADC3, &wcd938x->status_mask))
  1407. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC3]];
  1408. if (test_bit(WCD_ADC4, &wcd938x->status_mask))
  1409. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC4]];
  1410. if (mode != 0) {
  1411. for (i = 0; i < ADC_MODE_ULP2; i++) {
  1412. if (mode & (1 << i)) {
  1413. i++;
  1414. break;
  1415. }
  1416. }
  1417. }
  1418. rate = wcd938x_get_clk_rate(i);
  1419. wcd938x_set_swr_clk_rate(component, rate, bank);
  1420. }
  1421. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1422. wcd938x->tx_swr_dev->dev_num,
  1423. true);
  1424. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1425. /* Copy clk settings to active bank */
  1426. wcd938x_set_swr_clk_rate(component, rate, !bank);
  1427. }
  1428. break;
  1429. case SND_SOC_DAPM_POST_PMD:
  1430. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1431. rate = wcd938x_get_clk_rate(ADC_MODE_INVALID);
  1432. wcd938x_set_swr_clk_rate(component, rate, !bank);
  1433. }
  1434. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1435. wcd938x->tx_swr_dev->dev_num,
  1436. false);
  1437. if (strnstr(w->name, "ADC", sizeof("ADC")))
  1438. wcd938x_set_swr_clk_rate(component, rate, bank);
  1439. break;
  1440. };
  1441. return ret;
  1442. }
  1443. static int wcd938x_get_adc_mode(int val)
  1444. {
  1445. int ret = 0;
  1446. switch (val) {
  1447. case ADC_MODE_INVALID:
  1448. ret = ADC_MODE_VAL_NORMAL;
  1449. break;
  1450. case ADC_MODE_HIFI:
  1451. ret = ADC_MODE_VAL_HIFI;
  1452. break;
  1453. case ADC_MODE_LO_HIF:
  1454. ret = ADC_MODE_VAL_LO_HIF;
  1455. break;
  1456. case ADC_MODE_NORMAL:
  1457. ret = ADC_MODE_VAL_NORMAL;
  1458. break;
  1459. case ADC_MODE_LP:
  1460. ret = ADC_MODE_VAL_LP;
  1461. break;
  1462. case ADC_MODE_ULP1:
  1463. ret = ADC_MODE_VAL_ULP1;
  1464. break;
  1465. case ADC_MODE_ULP2:
  1466. ret = ADC_MODE_VAL_ULP2;
  1467. break;
  1468. default:
  1469. ret = -EINVAL;
  1470. pr_err("%s: invalid ADC mode value %d\n", __func__, val);
  1471. break;
  1472. }
  1473. return ret;
  1474. }
  1475. static int wcd938x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  1476. struct snd_kcontrol *kcontrol,
  1477. int event){
  1478. struct snd_soc_component *component =
  1479. snd_soc_dapm_to_component(w->dapm);
  1480. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1481. int clk_rate = 0;
  1482. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1483. w->name, event);
  1484. switch (event) {
  1485. case SND_SOC_DAPM_PRE_PMU:
  1486. snd_soc_component_update_bits(component,
  1487. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x08);
  1488. snd_soc_component_update_bits(component,
  1489. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1490. set_bit(w->shift, &wcd938x->status_mask);
  1491. clk_rate = wcd938x_get_clk_rate(wcd938x->tx_mode[w->shift]);
  1492. /* Enable BCS for Headset mic */
  1493. if (w->shift == 1 && !(snd_soc_component_read32(component,
  1494. WCD938X_TX_NEW_AMIC_MUX_CFG) & 0x80)) {
  1495. if (!wcd938x->bcs_dis)
  1496. wcd938x_tx_connect_port(component, MBHC,
  1497. SWR_CLK_RATE_4P8MHZ, true);
  1498. set_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask);
  1499. }
  1500. wcd938x_tx_connect_port(component, ADC1 + (w->shift), clk_rate,
  1501. true);
  1502. break;
  1503. case SND_SOC_DAPM_POST_PMD:
  1504. wcd938x_tx_connect_port(component, ADC1 + (w->shift), 0, false);
  1505. if (w->shift == 1 &&
  1506. test_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask)) {
  1507. if (!wcd938x->bcs_dis)
  1508. wcd938x_tx_connect_port(component, MBHC, 0,
  1509. false);
  1510. clear_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask);
  1511. }
  1512. snd_soc_component_update_bits(component,
  1513. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x00);
  1514. clear_bit(w->shift, &wcd938x->status_mask);
  1515. break;
  1516. };
  1517. return 0;
  1518. }
  1519. void wcd938x_disable_bcs_before_slow_insert(struct snd_soc_component *component,
  1520. bool bcs_disable)
  1521. {
  1522. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1523. if (wcd938x->update_wcd_event) {
  1524. if (bcs_disable)
  1525. wcd938x->update_wcd_event(wcd938x->handle,
  1526. WCD_BOLERO_EVT_BCS_CLK_OFF, 0);
  1527. else
  1528. wcd938x->update_wcd_event(wcd938x->handle,
  1529. WCD_BOLERO_EVT_BCS_CLK_OFF, 1);
  1530. }
  1531. }
  1532. int wcd938x_tx_channel_config(struct snd_soc_component *component,
  1533. int channel, int mode)
  1534. {
  1535. int reg = WCD938X_ANA_TX_CH2, mask = 0, val = 0;
  1536. int ret = 0;
  1537. switch (channel) {
  1538. case 0:
  1539. reg = WCD938X_ANA_TX_CH2;
  1540. mask = 0x40;
  1541. break;
  1542. case 1:
  1543. reg = WCD938X_ANA_TX_CH2;
  1544. mask = 0x20;
  1545. break;
  1546. case 2:
  1547. reg = WCD938X_ANA_TX_CH4;
  1548. mask = 0x40;
  1549. break;
  1550. case 3:
  1551. reg = WCD938X_ANA_TX_CH4;
  1552. mask = 0x20;
  1553. break;
  1554. default:
  1555. pr_err("%s: Invalid channel num %d\n", __func__, channel);
  1556. ret = -EINVAL;
  1557. break;
  1558. }
  1559. if (!mode)
  1560. val = 0x00;
  1561. else
  1562. val = mask;
  1563. if (!ret)
  1564. snd_soc_component_update_bits(component, reg, mask, val);
  1565. return ret;
  1566. }
  1567. static int wcd938x_enable_req(struct snd_soc_dapm_widget *w,
  1568. struct snd_kcontrol *kcontrol, int event)
  1569. {
  1570. struct snd_soc_component *component =
  1571. snd_soc_dapm_to_component(w->dapm);
  1572. int mode;
  1573. int ret = 0;
  1574. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1575. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1576. w->name, event);
  1577. switch (event) {
  1578. case SND_SOC_DAPM_PRE_PMU:
  1579. snd_soc_component_update_bits(component,
  1580. WCD938X_DIGITAL_CDC_REQ_CTL, 0x02, 0x02);
  1581. snd_soc_component_update_bits(component,
  1582. WCD938X_DIGITAL_CDC_REQ_CTL, 0x01, 0x00);
  1583. ret = wcd938x_tx_channel_config(component, w->shift, 1);
  1584. mode = wcd938x_get_adc_mode(wcd938x->tx_mode[w->shift]);
  1585. if (mode < 0) {
  1586. dev_info(component->dev,
  1587. "%s: invalid mode, setting to normal mode\n",
  1588. __func__);
  1589. mode = ADC_MODE_VAL_NORMAL;
  1590. }
  1591. switch (w->shift) {
  1592. case 0:
  1593. snd_soc_component_update_bits(component,
  1594. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x0F,
  1595. mode);
  1596. snd_soc_component_update_bits(component,
  1597. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x10);
  1598. break;
  1599. case 1:
  1600. snd_soc_component_update_bits(component,
  1601. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0xF0,
  1602. mode << 4);
  1603. snd_soc_component_update_bits(component,
  1604. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x20, 0x20);
  1605. break;
  1606. case 2:
  1607. snd_soc_component_update_bits(component,
  1608. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x0F,
  1609. mode);
  1610. snd_soc_component_update_bits(component,
  1611. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x40, 0x40);
  1612. break;
  1613. case 3:
  1614. snd_soc_component_update_bits(component,
  1615. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0xF0,
  1616. mode << 4);
  1617. snd_soc_component_update_bits(component,
  1618. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1619. break;
  1620. default:
  1621. break;
  1622. }
  1623. ret |= wcd938x_tx_channel_config(component, w->shift, 0);
  1624. break;
  1625. case SND_SOC_DAPM_POST_PMD:
  1626. switch (w->shift) {
  1627. case 0:
  1628. snd_soc_component_update_bits(component,
  1629. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x0F,
  1630. 0x00);
  1631. snd_soc_component_update_bits(component,
  1632. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x00);
  1633. break;
  1634. case 1:
  1635. snd_soc_component_update_bits(component,
  1636. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0xF0,
  1637. 0x00);
  1638. snd_soc_component_update_bits(component,
  1639. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x20, 0x00);
  1640. break;
  1641. case 2:
  1642. snd_soc_component_update_bits(component,
  1643. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x0F,
  1644. 0x00);
  1645. snd_soc_component_update_bits(component,
  1646. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x40, 0x00);
  1647. break;
  1648. case 3:
  1649. snd_soc_component_update_bits(component,
  1650. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0xF0,
  1651. 0x00);
  1652. snd_soc_component_update_bits(component,
  1653. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00);
  1654. break;
  1655. default:
  1656. break;
  1657. }
  1658. snd_soc_component_update_bits(component,
  1659. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
  1660. break;
  1661. };
  1662. return ret;
  1663. }
  1664. int wcd938x_micbias_control(struct snd_soc_component *component,
  1665. int micb_num, int req, bool is_dapm)
  1666. {
  1667. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1668. int micb_index = micb_num - 1;
  1669. u16 micb_reg;
  1670. int pre_off_event = 0, post_off_event = 0;
  1671. int post_on_event = 0, post_dapm_off = 0;
  1672. int post_dapm_on = 0;
  1673. int ret = 0;
  1674. if ((micb_index < 0) || (micb_index > WCD938X_MAX_MICBIAS - 1)) {
  1675. dev_err(component->dev,
  1676. "%s: Invalid micbias index, micb_ind:%d\n",
  1677. __func__, micb_index);
  1678. return -EINVAL;
  1679. }
  1680. if (NULL == wcd938x) {
  1681. dev_err(component->dev,
  1682. "%s: wcd938x private data is NULL\n", __func__);
  1683. return -EINVAL;
  1684. }
  1685. switch (micb_num) {
  1686. case MIC_BIAS_1:
  1687. micb_reg = WCD938X_ANA_MICB1;
  1688. break;
  1689. case MIC_BIAS_2:
  1690. micb_reg = WCD938X_ANA_MICB2;
  1691. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1692. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1693. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1694. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1695. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1696. break;
  1697. case MIC_BIAS_3:
  1698. micb_reg = WCD938X_ANA_MICB3;
  1699. break;
  1700. case MIC_BIAS_4:
  1701. micb_reg = WCD938X_ANA_MICB4;
  1702. break;
  1703. default:
  1704. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1705. __func__, micb_num);
  1706. return -EINVAL;
  1707. };
  1708. mutex_lock(&wcd938x->micb_lock);
  1709. switch (req) {
  1710. case MICB_PULLUP_ENABLE:
  1711. if (!wcd938x->dev_up) {
  1712. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1713. __func__, req);
  1714. ret = -ENODEV;
  1715. goto done;
  1716. }
  1717. wcd938x->pullup_ref[micb_index]++;
  1718. if ((wcd938x->pullup_ref[micb_index] == 1) &&
  1719. (wcd938x->micb_ref[micb_index] == 0))
  1720. snd_soc_component_update_bits(component, micb_reg,
  1721. 0xC0, 0x80);
  1722. break;
  1723. case MICB_PULLUP_DISABLE:
  1724. if (wcd938x->pullup_ref[micb_index] > 0)
  1725. wcd938x->pullup_ref[micb_index]--;
  1726. if (!wcd938x->dev_up) {
  1727. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1728. __func__, req);
  1729. ret = -ENODEV;
  1730. goto done;
  1731. }
  1732. if ((wcd938x->pullup_ref[micb_index] == 0) &&
  1733. (wcd938x->micb_ref[micb_index] == 0))
  1734. snd_soc_component_update_bits(component, micb_reg,
  1735. 0xC0, 0x00);
  1736. break;
  1737. case MICB_ENABLE:
  1738. if (!wcd938x->dev_up) {
  1739. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1740. __func__, req);
  1741. ret = -ENODEV;
  1742. goto done;
  1743. }
  1744. wcd938x->micb_ref[micb_index]++;
  1745. if (wcd938x->micb_ref[micb_index] == 1) {
  1746. snd_soc_component_update_bits(component,
  1747. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xE0, 0xE0);
  1748. snd_soc_component_update_bits(component,
  1749. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1750. snd_soc_component_update_bits(component,
  1751. WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x01, 0x01);
  1752. snd_soc_component_update_bits(component,
  1753. WCD938X_MICB1_TEST_CTL_2, 0x01, 0x01);
  1754. snd_soc_component_update_bits(component,
  1755. WCD938X_MICB2_TEST_CTL_2, 0x01, 0x01);
  1756. snd_soc_component_update_bits(component,
  1757. WCD938X_MICB3_TEST_CTL_2, 0x01, 0x01);
  1758. snd_soc_component_update_bits(component,
  1759. WCD938X_MICB4_TEST_CTL_2, 0x01, 0x01);
  1760. snd_soc_component_update_bits(component,
  1761. micb_reg, 0xC0, 0x40);
  1762. if (post_on_event)
  1763. blocking_notifier_call_chain(
  1764. &wcd938x->mbhc->notifier,
  1765. post_on_event,
  1766. &wcd938x->mbhc->wcd_mbhc);
  1767. }
  1768. if (is_dapm && post_dapm_on && wcd938x->mbhc)
  1769. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1770. post_dapm_on,
  1771. &wcd938x->mbhc->wcd_mbhc);
  1772. break;
  1773. case MICB_DISABLE:
  1774. if (wcd938x->micb_ref[micb_index] > 0)
  1775. wcd938x->micb_ref[micb_index]--;
  1776. if (!wcd938x->dev_up) {
  1777. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1778. __func__, req);
  1779. ret = -ENODEV;
  1780. goto done;
  1781. }
  1782. if ((wcd938x->micb_ref[micb_index] == 0) &&
  1783. (wcd938x->pullup_ref[micb_index] > 0))
  1784. snd_soc_component_update_bits(component, micb_reg,
  1785. 0xC0, 0x80);
  1786. else if ((wcd938x->micb_ref[micb_index] == 0) &&
  1787. (wcd938x->pullup_ref[micb_index] == 0)) {
  1788. if (pre_off_event && wcd938x->mbhc)
  1789. blocking_notifier_call_chain(
  1790. &wcd938x->mbhc->notifier,
  1791. pre_off_event,
  1792. &wcd938x->mbhc->wcd_mbhc);
  1793. snd_soc_component_update_bits(component, micb_reg,
  1794. 0xC0, 0x00);
  1795. if (post_off_event && wcd938x->mbhc)
  1796. blocking_notifier_call_chain(
  1797. &wcd938x->mbhc->notifier,
  1798. post_off_event,
  1799. &wcd938x->mbhc->wcd_mbhc);
  1800. }
  1801. if (is_dapm && post_dapm_off && wcd938x->mbhc)
  1802. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1803. post_dapm_off,
  1804. &wcd938x->mbhc->wcd_mbhc);
  1805. break;
  1806. };
  1807. dev_dbg(component->dev,
  1808. "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1809. __func__, micb_num, wcd938x->micb_ref[micb_index],
  1810. wcd938x->pullup_ref[micb_index]);
  1811. done:
  1812. mutex_unlock(&wcd938x->micb_lock);
  1813. return ret;
  1814. }
  1815. EXPORT_SYMBOL(wcd938x_micbias_control);
  1816. static int wcd938x_get_logical_addr(struct swr_device *swr_dev)
  1817. {
  1818. int ret = 0;
  1819. uint8_t devnum = 0;
  1820. int num_retry = NUM_ATTEMPTS;
  1821. do {
  1822. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1823. if (ret) {
  1824. dev_err(&swr_dev->dev,
  1825. "%s get devnum %d for dev addr %lx failed\n",
  1826. __func__, devnum, swr_dev->addr);
  1827. /* retry after 1ms */
  1828. usleep_range(1000, 1010);
  1829. }
  1830. } while (ret && --num_retry);
  1831. swr_dev->dev_num = devnum;
  1832. return 0;
  1833. }
  1834. static int wcd938x_event_notify(struct notifier_block *block,
  1835. unsigned long val,
  1836. void *data)
  1837. {
  1838. u16 event = (val & 0xffff);
  1839. int ret = 0;
  1840. struct wcd938x_priv *wcd938x = dev_get_drvdata((struct device *)data);
  1841. struct snd_soc_component *component = wcd938x->component;
  1842. struct wcd_mbhc *mbhc;
  1843. switch (event) {
  1844. case BOLERO_WCD_EVT_TX_CH_HOLD_CLEAR:
  1845. if (test_bit(WCD_ADC1, &wcd938x->status_mask)) {
  1846. snd_soc_component_update_bits(component,
  1847. WCD938X_ANA_TX_CH2, 0x40, 0x00);
  1848. clear_bit(WCD_ADC1, &wcd938x->status_mask);
  1849. }
  1850. if (test_bit(WCD_ADC2, &wcd938x->status_mask)) {
  1851. snd_soc_component_update_bits(component,
  1852. WCD938X_ANA_TX_CH2, 0x20, 0x00);
  1853. clear_bit(WCD_ADC2, &wcd938x->status_mask);
  1854. }
  1855. if (test_bit(WCD_ADC3, &wcd938x->status_mask)) {
  1856. snd_soc_component_update_bits(component,
  1857. WCD938X_ANA_TX_CH4, 0x40, 0x00);
  1858. clear_bit(WCD_ADC3, &wcd938x->status_mask);
  1859. }
  1860. if (test_bit(WCD_ADC4, &wcd938x->status_mask)) {
  1861. snd_soc_component_update_bits(component,
  1862. WCD938X_ANA_TX_CH4, 0x20, 0x00);
  1863. clear_bit(WCD_ADC4, &wcd938x->status_mask);
  1864. }
  1865. break;
  1866. case BOLERO_WCD_EVT_PA_OFF_PRE_SSR:
  1867. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  1868. 0xC0, 0x00);
  1869. snd_soc_component_update_bits(component, WCD938X_ANA_EAR,
  1870. 0x80, 0x00);
  1871. snd_soc_component_update_bits(component, WCD938X_AUX_AUXPA,
  1872. 0x80, 0x00);
  1873. break;
  1874. case BOLERO_WCD_EVT_SSR_DOWN:
  1875. wcd938x->dev_up = false;
  1876. mbhc = &wcd938x->mbhc->wcd_mbhc;
  1877. wcd938x_mbhc_ssr_down(wcd938x->mbhc, component);
  1878. wcd938x_reset_low(wcd938x->dev);
  1879. break;
  1880. case BOLERO_WCD_EVT_SSR_UP:
  1881. wcd938x_reset(wcd938x->dev);
  1882. /* allow reset to take effect */
  1883. usleep_range(10000, 10010);
  1884. wcd938x_get_logical_addr(wcd938x->tx_swr_dev);
  1885. wcd938x_get_logical_addr(wcd938x->rx_swr_dev);
  1886. wcd938x_init_reg(component);
  1887. regcache_mark_dirty(wcd938x->regmap);
  1888. regcache_sync(wcd938x->regmap);
  1889. /* Initialize MBHC module */
  1890. mbhc = &wcd938x->mbhc->wcd_mbhc;
  1891. ret = wcd938x_mbhc_post_ssr_init(wcd938x->mbhc, component);
  1892. if (ret) {
  1893. dev_err(component->dev, "%s: mbhc initialization failed\n",
  1894. __func__);
  1895. } else {
  1896. wcd938x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  1897. }
  1898. wcd938x->dev_up = true;
  1899. break;
  1900. case BOLERO_WCD_EVT_CLK_NOTIFY:
  1901. snd_soc_component_update_bits(component,
  1902. WCD938X_DIGITAL_TOP_CLK_CFG, 0x06,
  1903. ((val >> 0x10) << 0x01));
  1904. break;
  1905. default:
  1906. dev_dbg(component->dev, "%s: invalid event %d\n", __func__, event);
  1907. break;
  1908. }
  1909. return 0;
  1910. }
  1911. static int __wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1912. int event)
  1913. {
  1914. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1915. int micb_num;
  1916. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1917. __func__, w->name, event);
  1918. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  1919. micb_num = MIC_BIAS_1;
  1920. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  1921. micb_num = MIC_BIAS_2;
  1922. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  1923. micb_num = MIC_BIAS_3;
  1924. else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4")))
  1925. micb_num = MIC_BIAS_4;
  1926. else
  1927. return -EINVAL;
  1928. switch (event) {
  1929. case SND_SOC_DAPM_PRE_PMU:
  1930. wcd938x_micbias_control(component, micb_num,
  1931. MICB_ENABLE, true);
  1932. break;
  1933. case SND_SOC_DAPM_POST_PMU:
  1934. /* 1 msec delay as per HW requirement */
  1935. usleep_range(1000, 1100);
  1936. break;
  1937. case SND_SOC_DAPM_POST_PMD:
  1938. wcd938x_micbias_control(component, micb_num,
  1939. MICB_DISABLE, true);
  1940. break;
  1941. };
  1942. return 0;
  1943. }
  1944. static int wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1945. struct snd_kcontrol *kcontrol,
  1946. int event)
  1947. {
  1948. return __wcd938x_codec_enable_micbias(w, event);
  1949. }
  1950. static int __wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1951. int event)
  1952. {
  1953. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1954. int micb_num;
  1955. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1956. __func__, w->name, event);
  1957. if (strnstr(w->name, "VA MIC BIAS1", sizeof("VA MIC BIAS1")))
  1958. micb_num = MIC_BIAS_1;
  1959. else if (strnstr(w->name, "VA MIC BIAS2", sizeof("VA MIC BIAS2")))
  1960. micb_num = MIC_BIAS_2;
  1961. else if (strnstr(w->name, "VA MIC BIAS3", sizeof("VA MIC BIAS3")))
  1962. micb_num = MIC_BIAS_3;
  1963. else if (strnstr(w->name, "VA MIC BIAS4", sizeof("VA MIC BIAS4")))
  1964. micb_num = MIC_BIAS_4;
  1965. else
  1966. return -EINVAL;
  1967. switch (event) {
  1968. case SND_SOC_DAPM_PRE_PMU:
  1969. wcd938x_micbias_control(component, micb_num,
  1970. MICB_PULLUP_ENABLE, true);
  1971. break;
  1972. case SND_SOC_DAPM_POST_PMU:
  1973. /* 1 msec delay as per HW requirement */
  1974. usleep_range(1000, 1100);
  1975. break;
  1976. case SND_SOC_DAPM_POST_PMD:
  1977. wcd938x_micbias_control(component, micb_num,
  1978. MICB_PULLUP_DISABLE, true);
  1979. break;
  1980. };
  1981. return 0;
  1982. }
  1983. static int wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1984. struct snd_kcontrol *kcontrol,
  1985. int event)
  1986. {
  1987. return __wcd938x_codec_enable_micbias_pullup(w, event);
  1988. }
  1989. static int wcd938x_wakeup(void *handle, bool enable)
  1990. {
  1991. struct wcd938x_priv *priv;
  1992. int ret = 0;
  1993. if (!handle) {
  1994. pr_err("%s: NULL handle\n", __func__);
  1995. return -EINVAL;
  1996. }
  1997. priv = (struct wcd938x_priv *)handle;
  1998. if (!priv->tx_swr_dev) {
  1999. pr_err("%s: tx swr dev is NULL\n", __func__);
  2000. return -EINVAL;
  2001. }
  2002. mutex_lock(&priv->wakeup_lock);
  2003. if (enable)
  2004. ret = swr_device_wakeup_vote(priv->tx_swr_dev);
  2005. else
  2006. ret = swr_device_wakeup_unvote(priv->tx_swr_dev);
  2007. mutex_unlock(&priv->wakeup_lock);
  2008. return ret;
  2009. }
  2010. static int wcd938x_codec_force_enable_micbias(struct snd_soc_dapm_widget *w,
  2011. struct snd_kcontrol *kcontrol,
  2012. int event)
  2013. {
  2014. int ret = 0;
  2015. struct snd_soc_component *component =
  2016. snd_soc_dapm_to_component(w->dapm);
  2017. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2018. switch (event) {
  2019. case SND_SOC_DAPM_PRE_PMU:
  2020. wcd938x_wakeup(wcd938x, true);
  2021. ret = __wcd938x_codec_enable_micbias(w, SND_SOC_DAPM_PRE_PMU);
  2022. wcd938x_wakeup(wcd938x, false);
  2023. break;
  2024. case SND_SOC_DAPM_POST_PMD:
  2025. wcd938x_wakeup(wcd938x, true);
  2026. ret = __wcd938x_codec_enable_micbias(w, SND_SOC_DAPM_POST_PMD);
  2027. wcd938x_wakeup(wcd938x, false);
  2028. break;
  2029. }
  2030. return ret;
  2031. }
  2032. static int wcd938x_enable_micbias(struct wcd938x_priv *wcd938x,
  2033. int micb_num, int req)
  2034. {
  2035. int micb_index = micb_num - 1;
  2036. u16 micb_reg;
  2037. if (NULL == wcd938x) {
  2038. pr_err("%s: wcd938x private data is NULL\n", __func__);
  2039. return -EINVAL;
  2040. }
  2041. switch (micb_num) {
  2042. case MIC_BIAS_1:
  2043. micb_reg = WCD938X_ANA_MICB1;
  2044. break;
  2045. case MIC_BIAS_2:
  2046. micb_reg = WCD938X_ANA_MICB2;
  2047. break;
  2048. case MIC_BIAS_3:
  2049. micb_reg = WCD938X_ANA_MICB3;
  2050. break;
  2051. case MIC_BIAS_4:
  2052. micb_reg = WCD938X_ANA_MICB4;
  2053. break;
  2054. default:
  2055. pr_err("%s: Invalid micbias number: %d\n", __func__, micb_num);
  2056. return -EINVAL;
  2057. };
  2058. mutex_lock(&wcd938x->micb_lock);
  2059. switch (req) {
  2060. case MICB_ENABLE:
  2061. wcd938x->micb_ref[micb_index]++;
  2062. if (wcd938x->micb_ref[micb_index] == 1) {
  2063. regmap_update_bits(wcd938x->regmap,
  2064. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xE0, 0xE0);
  2065. regmap_update_bits(wcd938x->regmap,
  2066. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  2067. regmap_update_bits(wcd938x->regmap,
  2068. WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x01, 0x01);
  2069. regmap_update_bits(wcd938x->regmap,
  2070. WCD938X_MICB1_TEST_CTL_2, 0x01, 0x01);
  2071. regmap_update_bits(wcd938x->regmap,
  2072. WCD938X_MICB2_TEST_CTL_2, 0x01, 0x01);
  2073. regmap_update_bits(wcd938x->regmap,
  2074. WCD938X_MICB3_TEST_CTL_2, 0x01, 0x01);
  2075. regmap_update_bits(wcd938x->regmap,
  2076. WCD938X_MICB4_TEST_CTL_2, 0x01, 0x01);
  2077. regmap_update_bits(wcd938x->regmap,
  2078. micb_reg, 0xC0, 0x40);
  2079. regmap_update_bits(wcd938x->regmap, micb_reg, 0x3F, 0x10);
  2080. }
  2081. break;
  2082. case MICB_PULLUP_ENABLE:
  2083. wcd938x->pullup_ref[micb_index]++;
  2084. if ((wcd938x->pullup_ref[micb_index] == 1) &&
  2085. (wcd938x->micb_ref[micb_index] == 0))
  2086. regmap_update_bits(wcd938x->regmap, micb_reg,
  2087. 0xC0, 0x80);
  2088. break;
  2089. case MICB_PULLUP_DISABLE:
  2090. if (wcd938x->pullup_ref[micb_index] > 0)
  2091. wcd938x->pullup_ref[micb_index]--;
  2092. if ((wcd938x->pullup_ref[micb_index] == 0) &&
  2093. (wcd938x->micb_ref[micb_index] == 0))
  2094. regmap_update_bits(wcd938x->regmap, micb_reg,
  2095. 0xC0, 0x00);
  2096. break;
  2097. case MICB_DISABLE:
  2098. if (wcd938x->micb_ref[micb_index] > 0)
  2099. wcd938x->micb_ref[micb_index]--;
  2100. if ((wcd938x->micb_ref[micb_index] == 0) &&
  2101. (wcd938x->pullup_ref[micb_index] > 0))
  2102. regmap_update_bits(wcd938x->regmap, micb_reg,
  2103. 0xC0, 0x80);
  2104. else if ((wcd938x->micb_ref[micb_index] == 0) &&
  2105. (wcd938x->pullup_ref[micb_index] == 0))
  2106. regmap_update_bits(wcd938x->regmap, micb_reg,
  2107. 0xC0, 0x00);
  2108. break;
  2109. };
  2110. mutex_unlock(&wcd938x->micb_lock);
  2111. return 0;
  2112. }
  2113. int wcd938x_codec_force_enable_micbias_v2(struct snd_soc_component *component,
  2114. int event, int micb_num)
  2115. {
  2116. struct wcd938x_priv *wcd938x_priv = NULL;
  2117. if(NULL == component) {
  2118. pr_err("%s: wcd938x component is NULL\n", __func__);
  2119. return -EINVAL;
  2120. }
  2121. if(event != SND_SOC_DAPM_PRE_PMU && event != SND_SOC_DAPM_POST_PMD) {
  2122. pr_err("%s: invalid event: %d\n", __func__, event);
  2123. return -EINVAL;
  2124. }
  2125. if(micb_num < MIC_BIAS_1 || micb_num > MIC_BIAS_4) {
  2126. pr_err("%s: invalid mic bias num: %d\n", __func__, micb_num);
  2127. return -EINVAL;
  2128. }
  2129. wcd938x_priv = snd_soc_component_get_drvdata(component);
  2130. switch (event) {
  2131. case SND_SOC_DAPM_PRE_PMU:
  2132. wcd938x_wakeup(wcd938x_priv, true);
  2133. wcd938x_enable_micbias(wcd938x_priv, micb_num, MICB_PULLUP_ENABLE);
  2134. wcd938x_wakeup(wcd938x_priv, false);
  2135. break;
  2136. case SND_SOC_DAPM_POST_PMD:
  2137. wcd938x_wakeup(wcd938x_priv, true);
  2138. wcd938x_enable_micbias(wcd938x_priv, micb_num, MICB_PULLUP_DISABLE);
  2139. wcd938x_wakeup(wcd938x_priv, false);
  2140. break;
  2141. }
  2142. return 0;
  2143. }
  2144. EXPORT_SYMBOL(wcd938x_codec_force_enable_micbias_v2);
  2145. static inline int wcd938x_tx_path_get(const char *wname,
  2146. unsigned int *path_num)
  2147. {
  2148. int ret = 0;
  2149. char *widget_name = NULL;
  2150. char *w_name = NULL;
  2151. char *path_num_char = NULL;
  2152. char *path_name = NULL;
  2153. widget_name = kstrndup(wname, 9, GFP_KERNEL);
  2154. if (!widget_name)
  2155. return -EINVAL;
  2156. w_name = widget_name;
  2157. path_name = strsep(&widget_name, " ");
  2158. if (!path_name) {
  2159. pr_err("%s: Invalid widget name = %s\n",
  2160. __func__, widget_name);
  2161. ret = -EINVAL;
  2162. goto err;
  2163. }
  2164. path_num_char = strpbrk(path_name, "0123");
  2165. if (!path_num_char) {
  2166. pr_err("%s: tx path index not found\n",
  2167. __func__);
  2168. ret = -EINVAL;
  2169. goto err;
  2170. }
  2171. ret = kstrtouint(path_num_char, 10, path_num);
  2172. if (ret < 0)
  2173. pr_err("%s: Invalid tx path = %s\n",
  2174. __func__, w_name);
  2175. err:
  2176. kfree(w_name);
  2177. return ret;
  2178. }
  2179. static int wcd938x_tx_mode_get(struct snd_kcontrol *kcontrol,
  2180. struct snd_ctl_elem_value *ucontrol)
  2181. {
  2182. struct snd_soc_component *component =
  2183. snd_soc_kcontrol_component(kcontrol);
  2184. struct wcd938x_priv *wcd938x = NULL;
  2185. int ret = 0;
  2186. unsigned int path = 0;
  2187. if (!component)
  2188. return -EINVAL;
  2189. wcd938x = snd_soc_component_get_drvdata(component);
  2190. if (!wcd938x)
  2191. return -EINVAL;
  2192. ret = wcd938x_tx_path_get(kcontrol->id.name, &path);
  2193. if (ret < 0)
  2194. return ret;
  2195. ucontrol->value.integer.value[0] = wcd938x->tx_mode[path];
  2196. return 0;
  2197. }
  2198. static int wcd938x_tx_mode_put(struct snd_kcontrol *kcontrol,
  2199. struct snd_ctl_elem_value *ucontrol)
  2200. {
  2201. struct snd_soc_component *component =
  2202. snd_soc_kcontrol_component(kcontrol);
  2203. struct wcd938x_priv *wcd938x = NULL;
  2204. u32 mode_val;
  2205. unsigned int path = 0;
  2206. int ret = 0;
  2207. if (!component)
  2208. return -EINVAL;
  2209. wcd938x = snd_soc_component_get_drvdata(component);
  2210. if (!wcd938x)
  2211. return -EINVAL;
  2212. ret = wcd938x_tx_path_get(kcontrol->id.name, &path);
  2213. if (ret)
  2214. return ret;
  2215. mode_val = ucontrol->value.enumerated.item[0];
  2216. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  2217. wcd938x->tx_mode[path] = mode_val;
  2218. return 0;
  2219. }
  2220. static int wcd938x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  2221. struct snd_ctl_elem_value *ucontrol)
  2222. {
  2223. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2224. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2225. ucontrol->value.integer.value[0] = wcd938x->hph_mode;
  2226. return 0;
  2227. }
  2228. static int wcd938x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  2229. struct snd_ctl_elem_value *ucontrol)
  2230. {
  2231. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2232. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2233. u32 mode_val;
  2234. mode_val = ucontrol->value.enumerated.item[0];
  2235. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  2236. if (wcd938x->variant == WCD9380) {
  2237. if (mode_val == CLS_H_HIFI || mode_val == CLS_AB_HIFI) {
  2238. dev_info(component->dev,
  2239. "%s:Invalid HPH Mode, default to CLS_H_ULP\n",
  2240. __func__);
  2241. mode_val = CLS_H_ULP;
  2242. }
  2243. }
  2244. if (mode_val == CLS_H_NORMAL) {
  2245. dev_info(component->dev,
  2246. "%s:Invalid HPH Mode, default to class_AB\n",
  2247. __func__);
  2248. mode_val = CLS_H_ULP;
  2249. }
  2250. wcd938x->hph_mode = mode_val;
  2251. return 0;
  2252. }
  2253. static int wcd938x_ear_pa_gain_get(struct snd_kcontrol *kcontrol,
  2254. struct snd_ctl_elem_value *ucontrol)
  2255. {
  2256. u8 ear_pa_gain = 0;
  2257. struct snd_soc_component *component =
  2258. snd_soc_kcontrol_component(kcontrol);
  2259. ear_pa_gain = snd_soc_component_read32(component,
  2260. WCD938X_ANA_EAR_COMPANDER_CTL);
  2261. ear_pa_gain = (ear_pa_gain & 0x7C) >> 2;
  2262. ucontrol->value.integer.value[0] = ear_pa_gain;
  2263. dev_dbg(component->dev, "%s: ear_pa_gain = 0x%x\n", __func__,
  2264. ear_pa_gain);
  2265. return 0;
  2266. }
  2267. static int wcd938x_ear_pa_gain_put(struct snd_kcontrol *kcontrol,
  2268. struct snd_ctl_elem_value *ucontrol)
  2269. {
  2270. u8 ear_pa_gain = 0;
  2271. struct snd_soc_component *component =
  2272. snd_soc_kcontrol_component(kcontrol);
  2273. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2274. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  2275. __func__, ucontrol->value.integer.value[0]);
  2276. ear_pa_gain = ucontrol->value.integer.value[0] << 2;
  2277. if (!wcd938x->comp1_enable) {
  2278. snd_soc_component_update_bits(component,
  2279. WCD938X_ANA_EAR_COMPANDER_CTL,
  2280. 0x7C, ear_pa_gain);
  2281. }
  2282. return 0;
  2283. }
  2284. static int wcd938x_get_compander(struct snd_kcontrol *kcontrol,
  2285. struct snd_ctl_elem_value *ucontrol)
  2286. {
  2287. struct snd_soc_component *component =
  2288. snd_soc_kcontrol_component(kcontrol);
  2289. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2290. bool hphr;
  2291. struct soc_multi_mixer_control *mc;
  2292. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2293. hphr = mc->shift;
  2294. ucontrol->value.integer.value[0] = hphr ? wcd938x->comp2_enable :
  2295. wcd938x->comp1_enable;
  2296. return 0;
  2297. }
  2298. static int wcd938x_set_compander(struct snd_kcontrol *kcontrol,
  2299. struct snd_ctl_elem_value *ucontrol)
  2300. {
  2301. struct snd_soc_component *component =
  2302. snd_soc_kcontrol_component(kcontrol);
  2303. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2304. int value = ucontrol->value.integer.value[0];
  2305. bool hphr;
  2306. struct soc_multi_mixer_control *mc;
  2307. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2308. hphr = mc->shift;
  2309. if (hphr)
  2310. wcd938x->comp2_enable = value;
  2311. else
  2312. wcd938x->comp1_enable = value;
  2313. return 0;
  2314. }
  2315. static int wcd938x_ldoh_get(struct snd_kcontrol *kcontrol,
  2316. struct snd_ctl_elem_value *ucontrol)
  2317. {
  2318. struct snd_soc_component *component =
  2319. snd_soc_kcontrol_component(kcontrol);
  2320. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2321. ucontrol->value.integer.value[0] = wcd938x->ldoh;
  2322. return 0;
  2323. }
  2324. static int wcd938x_ldoh_put(struct snd_kcontrol *kcontrol,
  2325. struct snd_ctl_elem_value *ucontrol)
  2326. {
  2327. struct snd_soc_component *component =
  2328. snd_soc_kcontrol_component(kcontrol);
  2329. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2330. wcd938x->ldoh = ucontrol->value.integer.value[0];
  2331. return 0;
  2332. }
  2333. const char * const tx_master_ch_text[] = {
  2334. "ZERO", "SWRM_TX1_CH1", "SWRM_TX1_CH2", "SWRM_TX1_CH3", "SWRM_TX1_CH4",
  2335. "SWRM_TX2_CH1", "SWRM_TX2_CH2", "SWRM_TX2_CH3", "SWRM_TX2_CH4",
  2336. "SWRM_TX3_CH1", "SWRM_TX3_CH2", "SWRM_TX3_CH3", "SWRM_TX3_CH4",
  2337. "SWRM_PCM_IN",
  2338. };
  2339. const struct soc_enum tx_master_ch_enum =
  2340. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_master_ch_text),
  2341. tx_master_ch_text);
  2342. static void wcd938x_tx_get_slave_ch_type_idx(const char *wname, int *ch_idx)
  2343. {
  2344. u8 ch_type = 0;
  2345. if (strnstr(wname, "ADC1", sizeof("ADC1")))
  2346. ch_type = ADC1;
  2347. else if (strnstr(wname, "ADC2", sizeof("ADC2")))
  2348. ch_type = ADC2;
  2349. else if (strnstr(wname, "ADC3", sizeof("ADC3")))
  2350. ch_type = ADC3;
  2351. else if (strnstr(wname, "ADC4", sizeof("ADC4")))
  2352. ch_type = ADC4;
  2353. else if (strnstr(wname, "DMIC0", sizeof("DMIC0")))
  2354. ch_type = DMIC0;
  2355. else if (strnstr(wname, "DMIC1", sizeof("DMIC1")))
  2356. ch_type = DMIC1;
  2357. else if (strnstr(wname, "MBHC", sizeof("MBHC")))
  2358. ch_type = MBHC;
  2359. else if (strnstr(wname, "DMIC2", sizeof("DMIC2")))
  2360. ch_type = DMIC2;
  2361. else if (strnstr(wname, "DMIC3", sizeof("DMIC3")))
  2362. ch_type = DMIC3;
  2363. else if (strnstr(wname, "DMIC4", sizeof("DMIC4")))
  2364. ch_type = DMIC4;
  2365. else if (strnstr(wname, "DMIC5", sizeof("DMIC5")))
  2366. ch_type = DMIC5;
  2367. else if (strnstr(wname, "DMIC6", sizeof("DMIC6")))
  2368. ch_type = DMIC6;
  2369. else if (strnstr(wname, "DMIC7", sizeof("DMIC7")))
  2370. ch_type = DMIC7;
  2371. else
  2372. pr_err("%s: port name: %s is not listed\n", __func__, wname);
  2373. if (ch_type)
  2374. *ch_idx = wcd938x_slave_get_slave_ch_val(ch_type);
  2375. else
  2376. *ch_idx = -EINVAL;
  2377. }
  2378. static int wcd938x_tx_master_ch_get(struct snd_kcontrol *kcontrol,
  2379. struct snd_ctl_elem_value *ucontrol)
  2380. {
  2381. struct snd_soc_component *component =
  2382. snd_soc_kcontrol_component(kcontrol);
  2383. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2384. int slave_ch_idx;
  2385. wcd938x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2386. if (slave_ch_idx != -EINVAL)
  2387. ucontrol->value.integer.value[0] =
  2388. wcd938x_slave_get_master_ch_val(
  2389. wcd938x->tx_master_ch_map[slave_ch_idx]);
  2390. return 0;
  2391. }
  2392. static int wcd938x_tx_master_ch_put(struct snd_kcontrol *kcontrol,
  2393. struct snd_ctl_elem_value *ucontrol)
  2394. {
  2395. struct snd_soc_component *component =
  2396. snd_soc_kcontrol_component(kcontrol);
  2397. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2398. int slave_ch_idx;
  2399. wcd938x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2400. dev_dbg(component->dev, "%s: slave_ch_idx: %d", __func__, slave_ch_idx);
  2401. dev_dbg(component->dev, "%s: ucontrol->value.enumerated.item[0] = %ld\n",
  2402. __func__, ucontrol->value.enumerated.item[0]);
  2403. if (slave_ch_idx != -EINVAL)
  2404. wcd938x->tx_master_ch_map[slave_ch_idx] =
  2405. wcd938x_slave_get_master_ch(
  2406. ucontrol->value.enumerated.item[0]);
  2407. return 0;
  2408. }
  2409. static int wcd938x_bcs_get(struct snd_kcontrol *kcontrol,
  2410. struct snd_ctl_elem_value *ucontrol)
  2411. {
  2412. struct snd_soc_component *component =
  2413. snd_soc_kcontrol_component(kcontrol);
  2414. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2415. ucontrol->value.integer.value[0] = wcd938x->bcs_dis;
  2416. return 0;
  2417. }
  2418. static int wcd938x_bcs_put(struct snd_kcontrol *kcontrol,
  2419. struct snd_ctl_elem_value *ucontrol)
  2420. {
  2421. struct snd_soc_component *component =
  2422. snd_soc_kcontrol_component(kcontrol);
  2423. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2424. wcd938x->bcs_dis = ucontrol->value.integer.value[0];
  2425. return 0;
  2426. }
  2427. static const char * const tx_mode_mux_text_wcd9380[] = {
  2428. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  2429. };
  2430. static const struct soc_enum tx_mode_mux_enum_wcd9380 =
  2431. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text_wcd9380),
  2432. tx_mode_mux_text_wcd9380);
  2433. static const char * const tx_mode_mux_text[] = {
  2434. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  2435. "ADC_ULP1", "ADC_ULP2",
  2436. };
  2437. static const struct soc_enum tx_mode_mux_enum =
  2438. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text),
  2439. tx_mode_mux_text);
  2440. static const char * const rx_hph_mode_mux_text_wcd9380[] = {
  2441. "CLS_H_INVALID", "CLS_H_INVALID_1", "CLS_H_LP", "CLS_AB",
  2442. "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_H_INVALID_2", "CLS_AB_LP",
  2443. "CLS_AB_LOHIFI",
  2444. };
  2445. static const char * const wcd938x_ear_pa_gain_text[] = {
  2446. "G_6_DB", "G_4P5_DB", "G_3_DB", "G_1P5_DB", "G_0_DB",
  2447. "G_M1P5_DB", "G_M3_DB", "G_M4P5_DB",
  2448. "G_M6_DB", "G_7P5_DB", "G_M9_DB",
  2449. "G_M10P5_DB", "G_M12_DB", "G_M13P5_DB",
  2450. "G_M15_DB", "G_M16P5_DB", "G_M18_DB",
  2451. };
  2452. static const struct soc_enum rx_hph_mode_mux_enum_wcd9380 =
  2453. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text_wcd9380),
  2454. rx_hph_mode_mux_text_wcd9380);
  2455. static SOC_ENUM_SINGLE_EXT_DECL(wcd938x_ear_pa_gain_enum,
  2456. wcd938x_ear_pa_gain_text);
  2457. static const char * const rx_hph_mode_mux_text[] = {
  2458. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  2459. "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI",
  2460. };
  2461. static const struct soc_enum rx_hph_mode_mux_enum =
  2462. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  2463. rx_hph_mode_mux_text);
  2464. static const struct snd_kcontrol_new wcd9380_snd_controls[] = {
  2465. SOC_ENUM_EXT("EAR PA GAIN", wcd938x_ear_pa_gain_enum,
  2466. wcd938x_ear_pa_gain_get, wcd938x_ear_pa_gain_put),
  2467. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum_wcd9380,
  2468. wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
  2469. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum_wcd9380,
  2470. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2471. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum_wcd9380,
  2472. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2473. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum_wcd9380,
  2474. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2475. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum_wcd9380,
  2476. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2477. };
  2478. static const struct snd_kcontrol_new wcd9385_snd_controls[] = {
  2479. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  2480. wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
  2481. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum,
  2482. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2483. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum,
  2484. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2485. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum,
  2486. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2487. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum,
  2488. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2489. };
  2490. static const struct snd_kcontrol_new wcd938x_snd_controls[] = {
  2491. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  2492. wcd938x_get_compander, wcd938x_set_compander),
  2493. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  2494. wcd938x_get_compander, wcd938x_set_compander),
  2495. SOC_SINGLE_EXT("LDOH Enable", SND_SOC_NOPM, 0, 1, 0,
  2496. wcd938x_ldoh_get, wcd938x_ldoh_put),
  2497. SOC_SINGLE_EXT("ADC2_BCS Disable", SND_SOC_NOPM, 0, 1, 0,
  2498. wcd938x_bcs_get, wcd938x_bcs_put),
  2499. SOC_SINGLE_TLV("HPHL Volume", WCD938X_HPH_L_EN, 0, 20, 1, line_gain),
  2500. SOC_SINGLE_TLV("HPHR Volume", WCD938X_HPH_R_EN, 0, 20, 1, line_gain),
  2501. SOC_SINGLE_TLV("ADC1 Volume", WCD938X_ANA_TX_CH1, 0, 20, 0,
  2502. analog_gain),
  2503. SOC_SINGLE_TLV("ADC2 Volume", WCD938X_ANA_TX_CH2, 0, 20, 0,
  2504. analog_gain),
  2505. SOC_SINGLE_TLV("ADC3 Volume", WCD938X_ANA_TX_CH3, 0, 20, 0,
  2506. analog_gain),
  2507. SOC_SINGLE_TLV("ADC4 Volume", WCD938X_ANA_TX_CH4, 0, 20, 0,
  2508. analog_gain),
  2509. SOC_ENUM_EXT("ADC1 ChMap", tx_master_ch_enum,
  2510. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2511. SOC_ENUM_EXT("ADC2 ChMap", tx_master_ch_enum,
  2512. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2513. SOC_ENUM_EXT("ADC3 ChMap", tx_master_ch_enum,
  2514. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2515. SOC_ENUM_EXT("ADC4 ChMap", tx_master_ch_enum,
  2516. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2517. SOC_ENUM_EXT("DMIC0 ChMap", tx_master_ch_enum,
  2518. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2519. SOC_ENUM_EXT("DMIC1 ChMap", tx_master_ch_enum,
  2520. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2521. SOC_ENUM_EXT("MBHC ChMap", tx_master_ch_enum,
  2522. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2523. SOC_ENUM_EXT("DMIC2 ChMap", tx_master_ch_enum,
  2524. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2525. SOC_ENUM_EXT("DMIC3 ChMap", tx_master_ch_enum,
  2526. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2527. SOC_ENUM_EXT("DMIC4 ChMap", tx_master_ch_enum,
  2528. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2529. SOC_ENUM_EXT("DMIC5 ChMap", tx_master_ch_enum,
  2530. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2531. SOC_ENUM_EXT("DMIC6 ChMap", tx_master_ch_enum,
  2532. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2533. SOC_ENUM_EXT("DMIC7 ChMap", tx_master_ch_enum,
  2534. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2535. };
  2536. static const struct snd_kcontrol_new adc1_switch[] = {
  2537. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2538. };
  2539. static const struct snd_kcontrol_new adc2_switch[] = {
  2540. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2541. };
  2542. static const struct snd_kcontrol_new adc3_switch[] = {
  2543. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2544. };
  2545. static const struct snd_kcontrol_new adc4_switch[] = {
  2546. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2547. };
  2548. static const struct snd_kcontrol_new dmic1_switch[] = {
  2549. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2550. };
  2551. static const struct snd_kcontrol_new dmic2_switch[] = {
  2552. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2553. };
  2554. static const struct snd_kcontrol_new dmic3_switch[] = {
  2555. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2556. };
  2557. static const struct snd_kcontrol_new dmic4_switch[] = {
  2558. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2559. };
  2560. static const struct snd_kcontrol_new dmic5_switch[] = {
  2561. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2562. };
  2563. static const struct snd_kcontrol_new dmic6_switch[] = {
  2564. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2565. };
  2566. static const struct snd_kcontrol_new dmic7_switch[] = {
  2567. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2568. };
  2569. static const struct snd_kcontrol_new dmic8_switch[] = {
  2570. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2571. };
  2572. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  2573. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2574. };
  2575. static const struct snd_kcontrol_new aux_rdac_switch[] = {
  2576. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2577. };
  2578. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  2579. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2580. };
  2581. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  2582. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2583. };
  2584. static const char * const adc2_mux_text[] = {
  2585. "INP2", "INP3"
  2586. };
  2587. static const struct soc_enum adc2_enum =
  2588. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 7,
  2589. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  2590. static const struct snd_kcontrol_new tx_adc2_mux =
  2591. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  2592. static const char * const adc3_mux_text[] = {
  2593. "INP4", "INP6"
  2594. };
  2595. static const struct soc_enum adc3_enum =
  2596. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 6,
  2597. ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
  2598. static const struct snd_kcontrol_new tx_adc3_mux =
  2599. SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
  2600. static const char * const adc4_mux_text[] = {
  2601. "INP5", "INP7"
  2602. };
  2603. static const struct soc_enum adc4_enum =
  2604. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 5,
  2605. ARRAY_SIZE(adc4_mux_text), adc4_mux_text);
  2606. static const struct snd_kcontrol_new tx_adc4_mux =
  2607. SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum);
  2608. static const char * const rdac3_mux_text[] = {
  2609. "RX1", "RX3"
  2610. };
  2611. static const char * const hdr12_mux_text[] = {
  2612. "NO_HDR12", "HDR12"
  2613. };
  2614. static const struct soc_enum hdr12_enum =
  2615. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 4,
  2616. ARRAY_SIZE(hdr12_mux_text), hdr12_mux_text);
  2617. static const struct snd_kcontrol_new tx_hdr12_mux =
  2618. SOC_DAPM_ENUM("HDR12 MUX Mux", hdr12_enum);
  2619. static const char * const hdr34_mux_text[] = {
  2620. "NO_HDR34", "HDR34"
  2621. };
  2622. static const struct soc_enum hdr34_enum =
  2623. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 3,
  2624. ARRAY_SIZE(hdr34_mux_text), hdr34_mux_text);
  2625. static const struct snd_kcontrol_new tx_hdr34_mux =
  2626. SOC_DAPM_ENUM("HDR34 MUX Mux", hdr34_enum);
  2627. static const struct soc_enum rdac3_enum =
  2628. SOC_ENUM_SINGLE(WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0,
  2629. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  2630. static const struct snd_kcontrol_new rx_rdac3_mux =
  2631. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  2632. static const struct snd_soc_dapm_widget wcd938x_dapm_widgets[] = {
  2633. /*input widgets*/
  2634. SND_SOC_DAPM_INPUT("AMIC1"),
  2635. SND_SOC_DAPM_INPUT("AMIC2"),
  2636. SND_SOC_DAPM_INPUT("AMIC3"),
  2637. SND_SOC_DAPM_INPUT("AMIC4"),
  2638. SND_SOC_DAPM_INPUT("AMIC5"),
  2639. SND_SOC_DAPM_INPUT("AMIC6"),
  2640. SND_SOC_DAPM_INPUT("AMIC7"),
  2641. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  2642. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  2643. SND_SOC_DAPM_INPUT("IN3_AUX"),
  2644. /*tx widgets*/
  2645. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  2646. wcd938x_codec_enable_adc,
  2647. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2648. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
  2649. wcd938x_codec_enable_adc,
  2650. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2651. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
  2652. wcd938x_codec_enable_adc,
  2653. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2654. SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0,
  2655. wcd938x_codec_enable_adc,
  2656. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2657. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  2658. wcd938x_codec_enable_dmic,
  2659. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2660. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  2661. wcd938x_codec_enable_dmic,
  2662. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2663. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  2664. wcd938x_codec_enable_dmic,
  2665. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2666. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  2667. wcd938x_codec_enable_dmic,
  2668. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2669. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  2670. wcd938x_codec_enable_dmic,
  2671. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2672. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  2673. wcd938x_codec_enable_dmic,
  2674. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2675. SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0,
  2676. wcd938x_codec_enable_dmic,
  2677. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2678. SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0,
  2679. wcd938x_codec_enable_dmic,
  2680. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2681. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  2682. NULL, 0, wcd938x_enable_req,
  2683. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2684. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0,
  2685. NULL, 0, wcd938x_enable_req,
  2686. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2687. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0,
  2688. NULL, 0, wcd938x_enable_req,
  2689. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2690. SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0,
  2691. NULL, 0, wcd938x_enable_req,
  2692. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2693. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  2694. &tx_adc2_mux),
  2695. SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0,
  2696. &tx_adc3_mux),
  2697. SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0,
  2698. &tx_adc4_mux),
  2699. SND_SOC_DAPM_MUX("HDR12 MUX", SND_SOC_NOPM, 0, 0,
  2700. &tx_hdr12_mux),
  2701. SND_SOC_DAPM_MUX("HDR34 MUX", SND_SOC_NOPM, 0, 0,
  2702. &tx_hdr34_mux),
  2703. /*tx mixers*/
  2704. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0,
  2705. adc1_switch, ARRAY_SIZE(adc1_switch),
  2706. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2707. SND_SOC_DAPM_POST_PMD),
  2708. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 0, 0,
  2709. adc2_switch, ARRAY_SIZE(adc2_switch),
  2710. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2711. SND_SOC_DAPM_POST_PMD),
  2712. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 0, 0, adc3_switch,
  2713. ARRAY_SIZE(adc3_switch), wcd938x_tx_swr_ctrl,
  2714. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2715. SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, 0, 0, adc4_switch,
  2716. ARRAY_SIZE(adc4_switch), wcd938x_tx_swr_ctrl,
  2717. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2718. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0,
  2719. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  2720. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2721. SND_SOC_DAPM_POST_PMD),
  2722. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 0,
  2723. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  2724. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2725. SND_SOC_DAPM_POST_PMD),
  2726. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 0,
  2727. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  2728. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2729. SND_SOC_DAPM_POST_PMD),
  2730. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 0,
  2731. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  2732. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2733. SND_SOC_DAPM_POST_PMD),
  2734. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 0,
  2735. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  2736. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2737. SND_SOC_DAPM_POST_PMD),
  2738. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 0,
  2739. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  2740. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2741. SND_SOC_DAPM_POST_PMD),
  2742. SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, 0,
  2743. 0, dmic7_switch, ARRAY_SIZE(dmic7_switch),
  2744. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2745. SND_SOC_DAPM_POST_PMD),
  2746. SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, 0,
  2747. 0, dmic8_switch, ARRAY_SIZE(dmic8_switch),
  2748. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2749. SND_SOC_DAPM_POST_PMD),
  2750. /* micbias widgets*/
  2751. SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2752. wcd938x_codec_enable_micbias,
  2753. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2754. SND_SOC_DAPM_POST_PMD),
  2755. SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2756. wcd938x_codec_enable_micbias,
  2757. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2758. SND_SOC_DAPM_POST_PMD),
  2759. SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2760. wcd938x_codec_enable_micbias,
  2761. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2762. SND_SOC_DAPM_POST_PMD),
  2763. SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, 0, 0,
  2764. wcd938x_codec_enable_micbias,
  2765. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2766. SND_SOC_DAPM_POST_PMD),
  2767. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS1_STANDALONE, SND_SOC_NOPM, 0, 0,
  2768. wcd938x_codec_force_enable_micbias,
  2769. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2770. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS2_STANDALONE, SND_SOC_NOPM, 0, 0,
  2771. wcd938x_codec_force_enable_micbias,
  2772. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2773. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS3_STANDALONE, SND_SOC_NOPM, 0, 0,
  2774. wcd938x_codec_force_enable_micbias,
  2775. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2776. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS4_STANDALONE, SND_SOC_NOPM, 0, 0,
  2777. wcd938x_codec_force_enable_micbias,
  2778. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2779. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  2780. wcd938x_enable_clsh,
  2781. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2782. /*rx widgets*/
  2783. SND_SOC_DAPM_PGA_E("EAR PGA", WCD938X_ANA_EAR, 7, 0, NULL, 0,
  2784. wcd938x_codec_enable_ear_pa,
  2785. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2786. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2787. SND_SOC_DAPM_PGA_E("AUX PGA", WCD938X_AUX_AUXPA, 7, 0, NULL, 0,
  2788. wcd938x_codec_enable_aux_pa,
  2789. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2790. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2791. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD938X_ANA_HPH, 7, 0, NULL, 0,
  2792. wcd938x_codec_enable_hphl_pa,
  2793. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2794. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2795. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD938X_ANA_HPH, 6, 0, NULL, 0,
  2796. wcd938x_codec_enable_hphr_pa,
  2797. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2798. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2799. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  2800. wcd938x_codec_hphl_dac_event,
  2801. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2802. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2803. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  2804. wcd938x_codec_hphr_dac_event,
  2805. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2806. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2807. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  2808. wcd938x_codec_ear_dac_event,
  2809. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2810. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2811. SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
  2812. wcd938x_codec_aux_dac_event,
  2813. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2814. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2815. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  2816. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  2817. wcd938x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  2818. SND_SOC_DAPM_POST_PMD),
  2819. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  2820. wcd938x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  2821. SND_SOC_DAPM_POST_PMD),
  2822. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  2823. wcd938x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  2824. SND_SOC_DAPM_POST_PMD),
  2825. /* rx mixer widgets*/
  2826. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  2827. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  2828. SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
  2829. aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
  2830. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  2831. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  2832. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  2833. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  2834. /*output widgets tx*/
  2835. SND_SOC_DAPM_OUTPUT("WCD_TX_OUTPUT"),
  2836. /*output widgets rx*/
  2837. SND_SOC_DAPM_OUTPUT("EAR"),
  2838. SND_SOC_DAPM_OUTPUT("AUX"),
  2839. SND_SOC_DAPM_OUTPUT("HPHL"),
  2840. SND_SOC_DAPM_OUTPUT("HPHR"),
  2841. /* micbias pull up widgets*/
  2842. SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2843. wcd938x_codec_enable_micbias_pullup,
  2844. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2845. SND_SOC_DAPM_POST_PMD),
  2846. SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2847. wcd938x_codec_enable_micbias_pullup,
  2848. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2849. SND_SOC_DAPM_POST_PMD),
  2850. SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2851. wcd938x_codec_enable_micbias_pullup,
  2852. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2853. SND_SOC_DAPM_POST_PMD),
  2854. SND_SOC_DAPM_SUPPLY("VA MIC BIAS4", SND_SOC_NOPM, 0, 0,
  2855. wcd938x_codec_enable_micbias_pullup,
  2856. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2857. SND_SOC_DAPM_POST_PMD),
  2858. };
  2859. static const struct snd_soc_dapm_route wcd938x_audio_map[] = {
  2860. {"WCD_TX_OUTPUT", NULL, "ADC1_MIXER"},
  2861. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  2862. {"ADC1 REQ", NULL, "ADC1"},
  2863. {"ADC1", NULL, "AMIC1"},
  2864. {"WCD_TX_OUTPUT", NULL, "ADC2_MIXER"},
  2865. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  2866. {"ADC2 REQ", NULL, "ADC2"},
  2867. {"ADC2", NULL, "HDR12 MUX"},
  2868. {"HDR12 MUX", "NO_HDR12", "ADC2 MUX"},
  2869. {"HDR12 MUX", "HDR12", "AMIC1"},
  2870. {"ADC2 MUX", "INP3", "AMIC3"},
  2871. {"ADC2 MUX", "INP2", "AMIC2"},
  2872. {"WCD_TX_OUTPUT", NULL, "ADC3_MIXER"},
  2873. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  2874. {"ADC3 REQ", NULL, "ADC3"},
  2875. {"ADC3", NULL, "HDR34 MUX"},
  2876. {"HDR34 MUX", "NO_HDR34", "ADC3 MUX"},
  2877. {"HDR34 MUX", "HDR34", "AMIC5"},
  2878. {"ADC3 MUX", "INP4", "AMIC4"},
  2879. {"ADC3 MUX", "INP6", "AMIC6"},
  2880. {"WCD_TX_OUTPUT", NULL, "ADC4_MIXER"},
  2881. {"ADC4_MIXER", "Switch", "ADC4 REQ"},
  2882. {"ADC4 REQ", NULL, "ADC4"},
  2883. {"ADC4", NULL, "ADC4 MUX"},
  2884. {"ADC4 MUX", "INP5", "AMIC5"},
  2885. {"ADC4 MUX", "INP7", "AMIC7"},
  2886. {"WCD_TX_OUTPUT", NULL, "DMIC1_MIXER"},
  2887. {"DMIC1_MIXER", "Switch", "DMIC1"},
  2888. {"WCD_TX_OUTPUT", NULL, "DMIC2_MIXER"},
  2889. {"DMIC2_MIXER", "Switch", "DMIC2"},
  2890. {"WCD_TX_OUTPUT", NULL, "DMIC3_MIXER"},
  2891. {"DMIC3_MIXER", "Switch", "DMIC3"},
  2892. {"WCD_TX_OUTPUT", NULL, "DMIC4_MIXER"},
  2893. {"DMIC4_MIXER", "Switch", "DMIC4"},
  2894. {"WCD_TX_OUTPUT", NULL, "DMIC5_MIXER"},
  2895. {"DMIC5_MIXER", "Switch", "DMIC5"},
  2896. {"WCD_TX_OUTPUT", NULL, "DMIC6_MIXER"},
  2897. {"DMIC6_MIXER", "Switch", "DMIC6"},
  2898. {"WCD_TX_OUTPUT", NULL, "DMIC7_MIXER"},
  2899. {"DMIC7_MIXER", "Switch", "DMIC7"},
  2900. {"WCD_TX_OUTPUT", NULL, "DMIC8_MIXER"},
  2901. {"DMIC8_MIXER", "Switch", "DMIC8"},
  2902. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  2903. {"RX1", NULL, "IN1_HPHL"},
  2904. {"RDAC1", NULL, "RX1"},
  2905. {"HPHL_RDAC", "Switch", "RDAC1"},
  2906. {"HPHL PGA", NULL, "HPHL_RDAC"},
  2907. {"HPHL", NULL, "HPHL PGA"},
  2908. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  2909. {"RX2", NULL, "IN2_HPHR"},
  2910. {"RDAC2", NULL, "RX2"},
  2911. {"HPHR_RDAC", "Switch", "RDAC2"},
  2912. {"HPHR PGA", NULL, "HPHR_RDAC"},
  2913. {"HPHR", NULL, "HPHR PGA"},
  2914. {"IN3_AUX", NULL, "CLS_H_PORT"},
  2915. {"RX3", NULL, "IN3_AUX"},
  2916. {"RDAC4", NULL, "RX3"},
  2917. {"AUX_RDAC", "Switch", "RDAC4"},
  2918. {"AUX PGA", NULL, "AUX_RDAC"},
  2919. {"AUX", NULL, "AUX PGA"},
  2920. {"RDAC3_MUX", "RX3", "RX3"},
  2921. {"RDAC3_MUX", "RX1", "RX1"},
  2922. {"RDAC3", NULL, "RDAC3_MUX"},
  2923. {"EAR_RDAC", "Switch", "RDAC3"},
  2924. {"EAR PGA", NULL, "EAR_RDAC"},
  2925. {"EAR", NULL, "EAR PGA"},
  2926. };
  2927. static ssize_t wcd938x_version_read(struct snd_info_entry *entry,
  2928. void *file_private_data,
  2929. struct file *file,
  2930. char __user *buf, size_t count,
  2931. loff_t pos)
  2932. {
  2933. struct wcd938x_priv *priv;
  2934. char buffer[WCD938X_VERSION_ENTRY_SIZE];
  2935. int len = 0;
  2936. priv = (struct wcd938x_priv *) entry->private_data;
  2937. if (!priv) {
  2938. pr_err("%s: wcd938x priv is null\n", __func__);
  2939. return -EINVAL;
  2940. }
  2941. switch (priv->version) {
  2942. case WCD938X_VERSION_1_0:
  2943. len = snprintf(buffer, sizeof(buffer), "WCD938X_1_0\n");
  2944. break;
  2945. default:
  2946. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2947. }
  2948. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2949. }
  2950. static struct snd_info_entry_ops wcd938x_info_ops = {
  2951. .read = wcd938x_version_read,
  2952. };
  2953. static ssize_t wcd938x_variant_read(struct snd_info_entry *entry,
  2954. void *file_private_data,
  2955. struct file *file,
  2956. char __user *buf, size_t count,
  2957. loff_t pos)
  2958. {
  2959. struct wcd938x_priv *priv;
  2960. char buffer[WCD938X_VARIANT_ENTRY_SIZE];
  2961. int len = 0;
  2962. priv = (struct wcd938x_priv *) entry->private_data;
  2963. if (!priv) {
  2964. pr_err("%s: wcd938x priv is null\n", __func__);
  2965. return -EINVAL;
  2966. }
  2967. switch (priv->variant) {
  2968. case WCD9380:
  2969. len = snprintf(buffer, sizeof(buffer), "WCD9380\n");
  2970. break;
  2971. case WCD9385:
  2972. len = snprintf(buffer, sizeof(buffer), "WCD9385\n");
  2973. break;
  2974. default:
  2975. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2976. }
  2977. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2978. }
  2979. static struct snd_info_entry_ops wcd938x_variant_ops = {
  2980. .read = wcd938x_variant_read,
  2981. };
  2982. /*
  2983. * wcd938x_get_codec_variant
  2984. * @component: component instance
  2985. *
  2986. * Return: codec variant or -EINVAL in error.
  2987. */
  2988. int wcd938x_get_codec_variant(struct snd_soc_component *component)
  2989. {
  2990. struct wcd938x_priv *priv = NULL;
  2991. if (!component)
  2992. return -EINVAL;
  2993. priv = snd_soc_component_get_drvdata(component);
  2994. if (!priv) {
  2995. dev_err(component->dev,
  2996. "%s:wcd938x not probed\n", __func__);
  2997. return 0;
  2998. }
  2999. return priv->variant;
  3000. }
  3001. EXPORT_SYMBOL(wcd938x_get_codec_variant);
  3002. /*
  3003. * wcd938x_info_create_codec_entry - creates wcd938x module
  3004. * @codec_root: The parent directory
  3005. * @component: component instance
  3006. *
  3007. * Creates wcd938x module, variant and version entry under the given
  3008. * parent directory.
  3009. *
  3010. * Return: 0 on success or negative error code on failure.
  3011. */
  3012. int wcd938x_info_create_codec_entry(struct snd_info_entry *codec_root,
  3013. struct snd_soc_component *component)
  3014. {
  3015. struct snd_info_entry *version_entry;
  3016. struct snd_info_entry *variant_entry;
  3017. struct wcd938x_priv *priv;
  3018. struct snd_soc_card *card;
  3019. if (!codec_root || !component)
  3020. return -EINVAL;
  3021. priv = snd_soc_component_get_drvdata(component);
  3022. if (priv->entry) {
  3023. dev_dbg(priv->dev,
  3024. "%s:wcd938x module already created\n", __func__);
  3025. return 0;
  3026. }
  3027. card = component->card;
  3028. priv->entry = snd_info_create_module_entry(codec_root->module,
  3029. "wcd938x", codec_root);
  3030. if (!priv->entry) {
  3031. dev_dbg(component->dev, "%s: failed to create wcd938x entry\n",
  3032. __func__);
  3033. return -ENOMEM;
  3034. }
  3035. priv->entry->mode = S_IFDIR | 0555;
  3036. if (snd_info_register(priv->entry) < 0) {
  3037. snd_info_free_entry(priv->entry);
  3038. return -ENOMEM;
  3039. }
  3040. version_entry = snd_info_create_card_entry(card->snd_card,
  3041. "version",
  3042. priv->entry);
  3043. if (!version_entry) {
  3044. dev_dbg(component->dev, "%s: failed to create wcd938x version entry\n",
  3045. __func__);
  3046. snd_info_free_entry(priv->entry);
  3047. return -ENOMEM;
  3048. }
  3049. version_entry->private_data = priv;
  3050. version_entry->size = WCD938X_VERSION_ENTRY_SIZE;
  3051. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  3052. version_entry->c.ops = &wcd938x_info_ops;
  3053. if (snd_info_register(version_entry) < 0) {
  3054. snd_info_free_entry(version_entry);
  3055. snd_info_free_entry(priv->entry);
  3056. return -ENOMEM;
  3057. }
  3058. priv->version_entry = version_entry;
  3059. variant_entry = snd_info_create_card_entry(card->snd_card,
  3060. "variant",
  3061. priv->entry);
  3062. if (!variant_entry) {
  3063. dev_dbg(component->dev, "%s: failed to create wcd938x variant entry\n",
  3064. __func__);
  3065. snd_info_free_entry(version_entry);
  3066. snd_info_free_entry(priv->entry);
  3067. return -ENOMEM;
  3068. }
  3069. variant_entry->private_data = priv;
  3070. variant_entry->size = WCD938X_VARIANT_ENTRY_SIZE;
  3071. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  3072. variant_entry->c.ops = &wcd938x_variant_ops;
  3073. if (snd_info_register(variant_entry) < 0) {
  3074. snd_info_free_entry(variant_entry);
  3075. snd_info_free_entry(version_entry);
  3076. snd_info_free_entry(priv->entry);
  3077. return -ENOMEM;
  3078. }
  3079. priv->variant_entry = variant_entry;
  3080. return 0;
  3081. }
  3082. EXPORT_SYMBOL(wcd938x_info_create_codec_entry);
  3083. static int wcd938x_set_micbias_data(struct wcd938x_priv *wcd938x,
  3084. struct wcd938x_pdata *pdata)
  3085. {
  3086. int vout_ctl_1 = 0, vout_ctl_2 = 0, vout_ctl_3 = 0, vout_ctl_4 = 0;
  3087. int rc = 0;
  3088. if (!pdata) {
  3089. dev_err(wcd938x->dev, "%s: NULL pdata\n", __func__);
  3090. return -ENODEV;
  3091. }
  3092. /* set micbias voltage */
  3093. vout_ctl_1 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb1_mv);
  3094. vout_ctl_2 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb2_mv);
  3095. vout_ctl_3 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb3_mv);
  3096. vout_ctl_4 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb4_mv);
  3097. if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0 ||
  3098. vout_ctl_4 < 0) {
  3099. rc = -EINVAL;
  3100. goto done;
  3101. }
  3102. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB1, 0x3F,
  3103. vout_ctl_1);
  3104. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB2, 0x3F,
  3105. vout_ctl_2);
  3106. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB3, 0x3F,
  3107. vout_ctl_3);
  3108. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB4, 0x3F,
  3109. vout_ctl_4);
  3110. done:
  3111. return rc;
  3112. }
  3113. static int wcd938x_soc_codec_probe(struct snd_soc_component *component)
  3114. {
  3115. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  3116. struct snd_soc_dapm_context *dapm =
  3117. snd_soc_component_get_dapm(component);
  3118. int variant;
  3119. int ret = -EINVAL;
  3120. dev_info(component->dev, "%s()\n", __func__);
  3121. wcd938x = snd_soc_component_get_drvdata(component);
  3122. if (!wcd938x)
  3123. return -EINVAL;
  3124. wcd938x->component = component;
  3125. snd_soc_component_init_regmap(component, wcd938x->regmap);
  3126. variant = (snd_soc_component_read32(component,
  3127. WCD938X_DIGITAL_EFUSE_REG_0) & 0x1E) >> 1;
  3128. wcd938x->variant = variant;
  3129. wcd938x->fw_data = devm_kzalloc(component->dev,
  3130. sizeof(*(wcd938x->fw_data)),
  3131. GFP_KERNEL);
  3132. if (!wcd938x->fw_data) {
  3133. dev_err(component->dev, "Failed to allocate fw_data\n");
  3134. ret = -ENOMEM;
  3135. goto err;
  3136. }
  3137. set_bit(WCD9XXX_MBHC_CAL, wcd938x->fw_data->cal_bit);
  3138. ret = wcd_cal_create_hwdep(wcd938x->fw_data,
  3139. WCD9XXX_CODEC_HWDEP_NODE, component);
  3140. if (ret < 0) {
  3141. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  3142. goto err_hwdep;
  3143. }
  3144. ret = wcd938x_mbhc_init(&wcd938x->mbhc, component, wcd938x->fw_data);
  3145. if (ret) {
  3146. pr_err("%s: mbhc initialization failed\n", __func__);
  3147. goto err_hwdep;
  3148. }
  3149. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  3150. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  3151. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  3152. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  3153. snd_soc_dapm_ignore_suspend(dapm, "AMIC5");
  3154. snd_soc_dapm_ignore_suspend(dapm, "AMIC6");
  3155. snd_soc_dapm_ignore_suspend(dapm, "AMIC7");
  3156. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_OUTPUT");
  3157. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  3158. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  3159. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  3160. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  3161. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  3162. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  3163. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  3164. snd_soc_dapm_sync(dapm);
  3165. wcd_cls_h_init(&wcd938x->clsh_info);
  3166. wcd938x_init_reg(component);
  3167. if (wcd938x->variant == WCD9380) {
  3168. ret = snd_soc_add_component_controls(component, wcd9380_snd_controls,
  3169. ARRAY_SIZE(wcd9380_snd_controls));
  3170. if (ret < 0) {
  3171. dev_err(component->dev,
  3172. "%s: Failed to add snd ctrls for variant: %d\n",
  3173. __func__, wcd938x->variant);
  3174. goto err_hwdep;
  3175. }
  3176. }
  3177. if (wcd938x->variant == WCD9385) {
  3178. ret = snd_soc_add_component_controls(component, wcd9385_snd_controls,
  3179. ARRAY_SIZE(wcd9385_snd_controls));
  3180. if (ret < 0) {
  3181. dev_err(component->dev,
  3182. "%s: Failed to add snd ctrls for variant: %d\n",
  3183. __func__, wcd938x->variant);
  3184. goto err_hwdep;
  3185. }
  3186. }
  3187. wcd938x->version = WCD938X_VERSION_1_0;
  3188. /* Register event notifier */
  3189. wcd938x->nblock.notifier_call = wcd938x_event_notify;
  3190. if (wcd938x->register_notifier) {
  3191. ret = wcd938x->register_notifier(wcd938x->handle,
  3192. &wcd938x->nblock,
  3193. true);
  3194. if (ret) {
  3195. dev_err(component->dev,
  3196. "%s: Failed to register notifier %d\n",
  3197. __func__, ret);
  3198. return ret;
  3199. }
  3200. }
  3201. wcd938x->dev_up = true;
  3202. return ret;
  3203. err_hwdep:
  3204. wcd938x->fw_data = NULL;
  3205. err:
  3206. return ret;
  3207. }
  3208. static void wcd938x_soc_codec_remove(struct snd_soc_component *component)
  3209. {
  3210. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  3211. if (!wcd938x) {
  3212. dev_err(component->dev, "%s: wcd938x is already NULL\n",
  3213. __func__);
  3214. return;
  3215. }
  3216. if (wcd938x->register_notifier)
  3217. wcd938x->register_notifier(wcd938x->handle,
  3218. &wcd938x->nblock,
  3219. false);
  3220. }
  3221. static struct snd_soc_component_driver soc_codec_dev_wcd938x = {
  3222. .name = WCD938X_DRV_NAME,
  3223. .probe = wcd938x_soc_codec_probe,
  3224. .remove = wcd938x_soc_codec_remove,
  3225. .controls = wcd938x_snd_controls,
  3226. .num_controls = ARRAY_SIZE(wcd938x_snd_controls),
  3227. .dapm_widgets = wcd938x_dapm_widgets,
  3228. .num_dapm_widgets = ARRAY_SIZE(wcd938x_dapm_widgets),
  3229. .dapm_routes = wcd938x_audio_map,
  3230. .num_dapm_routes = ARRAY_SIZE(wcd938x_audio_map),
  3231. };
  3232. static int wcd938x_reset(struct device *dev)
  3233. {
  3234. struct wcd938x_priv *wcd938x = NULL;
  3235. int rc = 0;
  3236. int value = 0;
  3237. if (!dev)
  3238. return -ENODEV;
  3239. wcd938x = dev_get_drvdata(dev);
  3240. if (!wcd938x)
  3241. return -EINVAL;
  3242. if (!wcd938x->rst_np) {
  3243. dev_err(dev, "%s: reset gpio device node not specified\n",
  3244. __func__);
  3245. return -EINVAL;
  3246. }
  3247. value = msm_cdc_pinctrl_get_state(wcd938x->rst_np);
  3248. if (value > 0)
  3249. return 0;
  3250. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  3251. if (rc) {
  3252. dev_err(dev, "%s: wcd sleep state request fail!\n",
  3253. __func__);
  3254. return rc;
  3255. }
  3256. /* 20us sleep required after pulling the reset gpio to LOW */
  3257. usleep_range(20, 30);
  3258. rc = msm_cdc_pinctrl_select_active_state(wcd938x->rst_np);
  3259. if (rc) {
  3260. dev_err(dev, "%s: wcd active state request fail!\n",
  3261. __func__);
  3262. return rc;
  3263. }
  3264. /* 20us sleep required after pulling the reset gpio to HIGH */
  3265. usleep_range(20, 30);
  3266. return rc;
  3267. }
  3268. static int wcd938x_read_of_property_u32(struct device *dev, const char *name,
  3269. u32 *val)
  3270. {
  3271. int rc = 0;
  3272. rc = of_property_read_u32(dev->of_node, name, val);
  3273. if (rc)
  3274. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  3275. __func__, name, dev->of_node->full_name);
  3276. return rc;
  3277. }
  3278. static void wcd938x_dt_parse_micbias_info(struct device *dev,
  3279. struct wcd938x_micbias_setting *mb)
  3280. {
  3281. u32 prop_val = 0;
  3282. int rc = 0;
  3283. /* MB1 */
  3284. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  3285. NULL)) {
  3286. rc = wcd938x_read_of_property_u32(dev,
  3287. "qcom,cdc-micbias1-mv",
  3288. &prop_val);
  3289. if (!rc)
  3290. mb->micb1_mv = prop_val;
  3291. } else {
  3292. dev_info(dev, "%s: Micbias1 DT property not found\n",
  3293. __func__);
  3294. }
  3295. /* MB2 */
  3296. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  3297. NULL)) {
  3298. rc = wcd938x_read_of_property_u32(dev,
  3299. "qcom,cdc-micbias2-mv",
  3300. &prop_val);
  3301. if (!rc)
  3302. mb->micb2_mv = prop_val;
  3303. } else {
  3304. dev_info(dev, "%s: Micbias2 DT property not found\n",
  3305. __func__);
  3306. }
  3307. /* MB3 */
  3308. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  3309. NULL)) {
  3310. rc = wcd938x_read_of_property_u32(dev,
  3311. "qcom,cdc-micbias3-mv",
  3312. &prop_val);
  3313. if (!rc)
  3314. mb->micb3_mv = prop_val;
  3315. } else {
  3316. dev_info(dev, "%s: Micbias3 DT property not found\n",
  3317. __func__);
  3318. }
  3319. /* MB4 */
  3320. if (of_find_property(dev->of_node, "qcom,cdc-micbias4-mv",
  3321. NULL)) {
  3322. rc = wcd938x_read_of_property_u32(dev,
  3323. "qcom,cdc-micbias4-mv",
  3324. &prop_val);
  3325. if (!rc)
  3326. mb->micb4_mv = prop_val;
  3327. } else {
  3328. dev_info(dev, "%s: Micbias4 DT property not found\n",
  3329. __func__);
  3330. }
  3331. }
  3332. static int wcd938x_reset_low(struct device *dev)
  3333. {
  3334. struct wcd938x_priv *wcd938x = NULL;
  3335. int rc = 0;
  3336. if (!dev)
  3337. return -ENODEV;
  3338. wcd938x = dev_get_drvdata(dev);
  3339. if (!wcd938x)
  3340. return -EINVAL;
  3341. if (!wcd938x->rst_np) {
  3342. dev_err(dev, "%s: reset gpio device node not specified\n",
  3343. __func__);
  3344. return -EINVAL;
  3345. }
  3346. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  3347. if (rc) {
  3348. dev_err(dev, "%s: wcd sleep state request fail!\n",
  3349. __func__);
  3350. return rc;
  3351. }
  3352. /* 20us sleep required after pulling the reset gpio to LOW */
  3353. usleep_range(20, 30);
  3354. return rc;
  3355. }
  3356. struct wcd938x_pdata *wcd938x_populate_dt_data(struct device *dev)
  3357. {
  3358. struct wcd938x_pdata *pdata = NULL;
  3359. pdata = devm_kzalloc(dev, sizeof(struct wcd938x_pdata),
  3360. GFP_KERNEL);
  3361. if (!pdata)
  3362. return NULL;
  3363. pdata->rst_np = of_parse_phandle(dev->of_node,
  3364. "qcom,wcd-rst-gpio-node", 0);
  3365. if (!pdata->rst_np) {
  3366. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  3367. __func__, "qcom,wcd-rst-gpio-node",
  3368. dev->of_node->full_name);
  3369. return NULL;
  3370. }
  3371. /* Parse power supplies */
  3372. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  3373. &pdata->num_supplies);
  3374. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  3375. dev_err(dev, "%s: no power supplies defined for codec\n",
  3376. __func__);
  3377. return NULL;
  3378. }
  3379. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  3380. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  3381. wcd938x_dt_parse_micbias_info(dev, &pdata->micbias);
  3382. return pdata;
  3383. }
  3384. static irqreturn_t wcd938x_wd_handle_irq(int irq, void *data)
  3385. {
  3386. pr_err_ratelimited("%s: Watchdog interrupt for irq =%d triggered\n",
  3387. __func__, irq);
  3388. return IRQ_HANDLED;
  3389. }
  3390. static struct snd_soc_dai_driver wcd938x_dai[] = {
  3391. {
  3392. .name = "wcd938x_cdc",
  3393. .playback = {
  3394. .stream_name = "WCD938X_AIF Playback",
  3395. .rates = WCD938X_RATES | WCD938X_FRAC_RATES,
  3396. .formats = WCD938X_FORMATS,
  3397. .rate_max = 192000,
  3398. .rate_min = 8000,
  3399. .channels_min = 1,
  3400. .channels_max = 4,
  3401. },
  3402. .capture = {
  3403. .stream_name = "WCD938X_AIF Capture",
  3404. .rates = WCD938X_RATES | WCD938X_FRAC_RATES,
  3405. .formats = WCD938X_FORMATS,
  3406. .rate_max = 192000,
  3407. .rate_min = 8000,
  3408. .channels_min = 1,
  3409. .channels_max = 4,
  3410. },
  3411. },
  3412. };
  3413. static int wcd938x_bind(struct device *dev)
  3414. {
  3415. int ret = 0, i = 0;
  3416. struct wcd938x_pdata *pdata = dev_get_platdata(dev);
  3417. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  3418. /*
  3419. * Add 5msec delay to provide sufficient time for
  3420. * soundwire auto enumeration of slave devices as
  3421. * as per HW requirement.
  3422. */
  3423. usleep_range(5000, 5010);
  3424. ret = component_bind_all(dev, wcd938x);
  3425. if (ret) {
  3426. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  3427. __func__, ret);
  3428. return ret;
  3429. }
  3430. wcd938x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  3431. if (!wcd938x->rx_swr_dev) {
  3432. dev_err(dev, "%s: Could not find RX swr slave device\n",
  3433. __func__);
  3434. ret = -ENODEV;
  3435. goto err;
  3436. }
  3437. wcd938x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  3438. if (!wcd938x->tx_swr_dev) {
  3439. dev_err(dev, "%s: Could not find TX swr slave device\n",
  3440. __func__);
  3441. ret = -ENODEV;
  3442. goto err;
  3443. }
  3444. wcd938x->regmap = devm_regmap_init_swr(wcd938x->tx_swr_dev,
  3445. &wcd938x_regmap_config);
  3446. if (!wcd938x->regmap) {
  3447. dev_err(dev, "%s: Regmap init failed\n",
  3448. __func__);
  3449. goto err;
  3450. }
  3451. /* Set all interupts as edge triggered */
  3452. for (i = 0; i < wcd938x_regmap_irq_chip.num_regs; i++)
  3453. regmap_write(wcd938x->regmap,
  3454. (WCD938X_DIGITAL_INTR_LEVEL_0 + i), 0);
  3455. wcd938x_regmap_irq_chip.irq_drv_data = wcd938x;
  3456. wcd938x->irq_info.wcd_regmap_irq_chip = &wcd938x_regmap_irq_chip;
  3457. wcd938x->irq_info.codec_name = "WCD938X";
  3458. wcd938x->irq_info.regmap = wcd938x->regmap;
  3459. wcd938x->irq_info.dev = dev;
  3460. ret = wcd_irq_init(&wcd938x->irq_info, &wcd938x->virq);
  3461. if (ret) {
  3462. dev_err(wcd938x->dev, "%s: IRQ init failed: %d\n",
  3463. __func__, ret);
  3464. goto err;
  3465. }
  3466. wcd938x->tx_swr_dev->slave_irq = wcd938x->virq;
  3467. ret = wcd938x_set_micbias_data(wcd938x, pdata);
  3468. if (ret < 0) {
  3469. dev_err(dev, "%s: bad micbias pdata\n", __func__);
  3470. goto err_irq;
  3471. }
  3472. /* Request for watchdog interrupt */
  3473. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT,
  3474. "HPHR PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3475. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT,
  3476. "HPHL PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3477. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT,
  3478. "AUX PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3479. /* Disable watchdog interrupt for HPH and AUX */
  3480. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT);
  3481. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT);
  3482. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT);
  3483. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd938x,
  3484. wcd938x_dai, ARRAY_SIZE(wcd938x_dai));
  3485. if (ret) {
  3486. dev_err(dev, "%s: Codec registration failed\n",
  3487. __func__);
  3488. goto err_irq;
  3489. }
  3490. return ret;
  3491. err_irq:
  3492. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  3493. err:
  3494. component_unbind_all(dev, wcd938x);
  3495. return ret;
  3496. }
  3497. static void wcd938x_unbind(struct device *dev)
  3498. {
  3499. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  3500. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT, NULL);
  3501. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT, NULL);
  3502. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT, NULL);
  3503. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  3504. snd_soc_unregister_component(dev);
  3505. component_unbind_all(dev, wcd938x);
  3506. }
  3507. static const struct of_device_id wcd938x_dt_match[] = {
  3508. { .compatible = "qcom,wcd938x-codec" },
  3509. {}
  3510. };
  3511. static const struct component_master_ops wcd938x_comp_ops = {
  3512. .bind = wcd938x_bind,
  3513. .unbind = wcd938x_unbind,
  3514. };
  3515. static int wcd938x_compare_of(struct device *dev, void *data)
  3516. {
  3517. return dev->of_node == data;
  3518. }
  3519. static void wcd938x_release_of(struct device *dev, void *data)
  3520. {
  3521. of_node_put(data);
  3522. }
  3523. static int wcd938x_add_slave_components(struct device *dev,
  3524. struct component_match **matchptr)
  3525. {
  3526. struct device_node *np, *rx_node, *tx_node;
  3527. np = dev->of_node;
  3528. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  3529. if (!rx_node) {
  3530. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  3531. return -ENODEV;
  3532. }
  3533. of_node_get(rx_node);
  3534. component_match_add_release(dev, matchptr,
  3535. wcd938x_release_of,
  3536. wcd938x_compare_of,
  3537. rx_node);
  3538. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  3539. if (!tx_node) {
  3540. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  3541. return -ENODEV;
  3542. }
  3543. of_node_get(tx_node);
  3544. component_match_add_release(dev, matchptr,
  3545. wcd938x_release_of,
  3546. wcd938x_compare_of,
  3547. tx_node);
  3548. return 0;
  3549. }
  3550. static int wcd938x_probe(struct platform_device *pdev)
  3551. {
  3552. struct component_match *match = NULL;
  3553. struct wcd938x_priv *wcd938x = NULL;
  3554. struct wcd938x_pdata *pdata = NULL;
  3555. struct wcd_ctrl_platform_data *plat_data = NULL;
  3556. struct device *dev = &pdev->dev;
  3557. int ret;
  3558. wcd938x = devm_kzalloc(dev, sizeof(struct wcd938x_priv),
  3559. GFP_KERNEL);
  3560. if (!wcd938x)
  3561. return -ENOMEM;
  3562. dev_set_drvdata(dev, wcd938x);
  3563. wcd938x->dev = dev;
  3564. pdata = wcd938x_populate_dt_data(dev);
  3565. if (!pdata) {
  3566. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  3567. return -EINVAL;
  3568. }
  3569. dev->platform_data = pdata;
  3570. wcd938x->rst_np = pdata->rst_np;
  3571. ret = msm_cdc_init_supplies(dev, &wcd938x->supplies,
  3572. pdata->regulator, pdata->num_supplies);
  3573. if (!wcd938x->supplies) {
  3574. dev_err(dev, "%s: Cannot init wcd supplies\n",
  3575. __func__);
  3576. return ret;
  3577. }
  3578. plat_data = dev_get_platdata(dev->parent);
  3579. if (!plat_data) {
  3580. dev_err(dev, "%s: platform data from parent is NULL\n",
  3581. __func__);
  3582. return -EINVAL;
  3583. }
  3584. wcd938x->handle = (void *)plat_data->handle;
  3585. if (!wcd938x->handle) {
  3586. dev_err(dev, "%s: handle is NULL\n", __func__);
  3587. return -EINVAL;
  3588. }
  3589. wcd938x->update_wcd_event = plat_data->update_wcd_event;
  3590. if (!wcd938x->update_wcd_event) {
  3591. dev_err(dev, "%s: update_wcd_event api is null!\n",
  3592. __func__);
  3593. return -EINVAL;
  3594. }
  3595. wcd938x->register_notifier = plat_data->register_notifier;
  3596. if (!wcd938x->register_notifier) {
  3597. dev_err(dev, "%s: register_notifier api is null!\n",
  3598. __func__);
  3599. return -EINVAL;
  3600. }
  3601. ret = msm_cdc_enable_static_supplies(&pdev->dev, wcd938x->supplies,
  3602. pdata->regulator,
  3603. pdata->num_supplies);
  3604. if (ret) {
  3605. dev_err(dev, "%s: wcd static supply enable failed!\n",
  3606. __func__);
  3607. return ret;
  3608. }
  3609. ret = wcd938x_parse_port_mapping(dev, "qcom,rx_swr_ch_map",
  3610. CODEC_RX);
  3611. ret |= wcd938x_parse_port_mapping(dev, "qcom,tx_swr_ch_map",
  3612. CODEC_TX);
  3613. if (ret) {
  3614. dev_err(dev, "Failed to read port mapping\n");
  3615. goto err;
  3616. }
  3617. mutex_init(&wcd938x->wakeup_lock);
  3618. mutex_init(&wcd938x->micb_lock);
  3619. ret = wcd938x_add_slave_components(dev, &match);
  3620. if (ret)
  3621. goto err_lock_init;
  3622. wcd938x_reset(dev);
  3623. wcd938x->wakeup = wcd938x_wakeup;
  3624. return component_master_add_with_match(dev,
  3625. &wcd938x_comp_ops, match);
  3626. err_lock_init:
  3627. mutex_destroy(&wcd938x->micb_lock);
  3628. mutex_destroy(&wcd938x->wakeup_lock);
  3629. err:
  3630. return ret;
  3631. }
  3632. static int wcd938x_remove(struct platform_device *pdev)
  3633. {
  3634. struct wcd938x_priv *wcd938x = NULL;
  3635. wcd938x = platform_get_drvdata(pdev);
  3636. component_master_del(&pdev->dev, &wcd938x_comp_ops);
  3637. mutex_destroy(&wcd938x->micb_lock);
  3638. mutex_destroy(&wcd938x->wakeup_lock);
  3639. dev_set_drvdata(&pdev->dev, NULL);
  3640. return 0;
  3641. }
  3642. #ifdef CONFIG_PM_SLEEP
  3643. static int wcd938x_suspend(struct device *dev)
  3644. {
  3645. return 0;
  3646. }
  3647. static int wcd938x_resume(struct device *dev)
  3648. {
  3649. return 0;
  3650. }
  3651. static const struct dev_pm_ops wcd938x_dev_pm_ops = {
  3652. SET_SYSTEM_SLEEP_PM_OPS(
  3653. wcd938x_suspend,
  3654. wcd938x_resume
  3655. )
  3656. };
  3657. #endif
  3658. static struct platform_driver wcd938x_codec_driver = {
  3659. .probe = wcd938x_probe,
  3660. .remove = wcd938x_remove,
  3661. .driver = {
  3662. .name = "wcd938x_codec",
  3663. .owner = THIS_MODULE,
  3664. .of_match_table = of_match_ptr(wcd938x_dt_match),
  3665. #ifdef CONFIG_PM_SLEEP
  3666. .pm = &wcd938x_dev_pm_ops,
  3667. #endif
  3668. .suppress_bind_attrs = true,
  3669. },
  3670. };
  3671. module_platform_driver(wcd938x_codec_driver);
  3672. MODULE_DESCRIPTION("WCD938X Codec driver");
  3673. MODULE_LICENSE("GPL v2");