qcs405.c 237 KB

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  1. /* Copyright (c) 2018, The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. */
  12. #include <linux/clk.h>
  13. #include <linux/delay.h>
  14. #include <linux/gpio.h>
  15. #include <linux/of_gpio.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/slab.h>
  18. #include <linux/i2c.h>
  19. #include <linux/io.h>
  20. #include <linux/module.h>
  21. #include <linux/input.h>
  22. #include <linux/of_device.h>
  23. #include <linux/pm_qos.h>
  24. #include <linux/regulator/consumer.h>
  25. #include <sound/core.h>
  26. #include <sound/soc.h>
  27. #include <sound/soc-dapm.h>
  28. #include <sound/pcm.h>
  29. #include <sound/pcm_params.h>
  30. #include <sound/info.h>
  31. #include <dsp/audio_notifier.h>
  32. #include <dsp/q6afe-v2.h>
  33. #include <dsp/q6core.h>
  34. #include <dsp/msm_mdf.h>
  35. #include "device_event.h"
  36. #include "msm-pcm-routing-v2.h"
  37. #include "codecs/msm-cdc-pinctrl.h"
  38. #include "codecs/wcd9335.h"
  39. #include "codecs/wsa881x.h"
  40. #include "codecs/csra66x0/csra66x0.h"
  41. #include <dt-bindings/sound/audio-codec-port-types.h>
  42. #include "codecs/bolero/bolero-cdc.h"
  43. #include "codecs/bolero/wsa-macro.h"
  44. #define DRV_NAME "qcs405-asoc-snd"
  45. #define __CHIPSET__ "QCS405 "
  46. #define MSM_DAILINK_NAME(name) (__CHIPSET__#name)
  47. #define DEV_NAME_STR_LEN 32
  48. #define SAMPLING_RATE_8KHZ 8000
  49. #define SAMPLING_RATE_11P025KHZ 11025
  50. #define SAMPLING_RATE_16KHZ 16000
  51. #define SAMPLING_RATE_22P05KHZ 22050
  52. #define SAMPLING_RATE_32KHZ 32000
  53. #define SAMPLING_RATE_44P1KHZ 44100
  54. #define SAMPLING_RATE_48KHZ 48000
  55. #define SAMPLING_RATE_88P2KHZ 88200
  56. #define SAMPLING_RATE_96KHZ 96000
  57. #define SAMPLING_RATE_176P4KHZ 176400
  58. #define SAMPLING_RATE_192KHZ 192000
  59. #define SAMPLING_RATE_352P8KHZ 352800
  60. #define SAMPLING_RATE_384KHZ 384000
  61. #define SPDIF_TX_CORE_CLK_163_P84_MHZ 163840000
  62. #define TLMM_EAST_SPARE 0x07BA0000
  63. #define TLMM_SPDIF_HDMI_ARC_CTL 0x07BA2000
  64. #define WSA8810_NAME_1 "wsa881x.20170211"
  65. #define WSA8810_NAME_2 "wsa881x.20170212"
  66. #define WCN_CDC_SLIM_RX_CH_MAX 2
  67. #define WCN_CDC_SLIM_TX_CH_MAX 3
  68. #define TDM_CHANNEL_MAX 8
  69. #define ADSP_STATE_READY_TIMEOUT_MS 3000
  70. #define MSM_LL_QOS_VALUE 300 /* time in us to ensure LPM doesn't go in C3/C4 */
  71. enum {
  72. SLIM_RX_0 = 0,
  73. SLIM_RX_1,
  74. SLIM_RX_2,
  75. SLIM_RX_3,
  76. SLIM_RX_4,
  77. SLIM_RX_5,
  78. SLIM_RX_6,
  79. SLIM_RX_7,
  80. SLIM_RX_MAX,
  81. };
  82. enum {
  83. SLIM_TX_0 = 0,
  84. SLIM_TX_1,
  85. SLIM_TX_2,
  86. SLIM_TX_3,
  87. SLIM_TX_4,
  88. SLIM_TX_5,
  89. SLIM_TX_6,
  90. SLIM_TX_7,
  91. SLIM_TX_8,
  92. SLIM_TX_MAX,
  93. };
  94. enum {
  95. PRIM_MI2S = 0,
  96. SEC_MI2S,
  97. TERT_MI2S,
  98. QUAT_MI2S,
  99. QUIN_MI2S,
  100. SEN_MI2S,
  101. MI2S_MAX,
  102. };
  103. enum {
  104. PRIM_AUX_PCM = 0,
  105. SEC_AUX_PCM,
  106. TERT_AUX_PCM,
  107. QUAT_AUX_PCM,
  108. QUIN_AUX_PCM,
  109. SEN_AUX_PCM,
  110. AUX_PCM_MAX,
  111. };
  112. enum {
  113. WSA_CDC_DMA_RX_0 = 0,
  114. WSA_CDC_DMA_RX_1,
  115. CDC_DMA_RX_MAX,
  116. };
  117. enum {
  118. WSA_CDC_DMA_TX_0 = 0,
  119. WSA_CDC_DMA_TX_1,
  120. WSA_CDC_DMA_TX_2,
  121. VA_CDC_DMA_TX_0,
  122. VA_CDC_DMA_TX_1,
  123. CDC_DMA_TX_MAX,
  124. };
  125. enum {
  126. PRIM_SPDIF_RX = 0,
  127. SEC_SPDIF_RX,
  128. SPDIF_RX_MAX,
  129. };
  130. enum {
  131. PRIM_SPDIF_TX = 0,
  132. SEC_SPDIF_TX,
  133. SPDIF_TX_MAX,
  134. };
  135. struct mi2s_conf {
  136. struct mutex lock;
  137. u32 ref_cnt;
  138. u32 msm_is_mi2s_master;
  139. };
  140. static u32 mi2s_ebit_clk[MI2S_MAX] = {
  141. Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT,
  142. Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT,
  143. Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT,
  144. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_EBIT,
  145. Q6AFE_LPASS_CLK_ID_QUI_MI2S_EBIT,
  146. Q6AFE_LPASS_CLK_ID_SEN_MI2S_EBIT
  147. };
  148. struct dev_config {
  149. u32 sample_rate;
  150. u32 bit_format;
  151. u32 channels;
  152. };
  153. struct msm_wsa881x_dev_info {
  154. struct device_node *of_node;
  155. u32 index;
  156. };
  157. struct msm_csra66x0_dev_info {
  158. struct device_node *of_node;
  159. u32 index;
  160. };
  161. struct msm_asoc_mach_data {
  162. struct snd_info_entry *codec_root;
  163. struct device_node *dmic_01_gpio_p; /* used by pinctrl API */
  164. struct device_node *dmic_23_gpio_p; /* used by pinctrl API */
  165. struct device_node *dmic_45_gpio_p; /* used by pinctrl API */
  166. struct device_node *dmic_67_gpio_p; /* used by pinctrl API */
  167. struct device_node *mi2s_gpio_p[MI2S_MAX]; /* used by pinctrl API */
  168. int dmic_01_gpio_cnt;
  169. int dmic_23_gpio_cnt;
  170. int dmic_45_gpio_cnt;
  171. int dmic_67_gpio_cnt;
  172. struct regulator *tdm_micb_supply;
  173. u32 tdm_micb_voltage;
  174. u32 tdm_micb_current;
  175. bool codec_is_csra;
  176. };
  177. struct msm_asoc_wcd93xx_codec {
  178. void* (*get_afe_config_fn)(struct snd_soc_codec *codec,
  179. enum afe_config_type config_type);
  180. };
  181. static const char *const pin_states[] = {"sleep", "i2s-active",
  182. "tdm-active"};
  183. enum {
  184. TDM_0 = 0,
  185. TDM_1,
  186. TDM_2,
  187. TDM_3,
  188. TDM_4,
  189. TDM_5,
  190. TDM_6,
  191. TDM_7,
  192. TDM_PORT_MAX,
  193. };
  194. enum {
  195. TDM_PRI = 0,
  196. TDM_SEC,
  197. TDM_TERT,
  198. TDM_QUAT,
  199. TDM_QUIN,
  200. TDM_INTERFACE_MAX,
  201. };
  202. struct tdm_port {
  203. u32 mode;
  204. u32 channel;
  205. };
  206. /* TDM default config */
  207. static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  208. { /* PRI TDM */
  209. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  210. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  211. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  212. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  213. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  214. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  215. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  216. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  217. },
  218. { /* SEC TDM */
  219. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  220. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  221. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  222. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  223. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  224. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  225. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  226. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  227. },
  228. { /* TERT TDM */
  229. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  230. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  231. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  232. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  233. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  234. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  235. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  236. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  237. },
  238. { /* QUAT TDM */
  239. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  240. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  241. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  242. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  243. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  244. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  245. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  246. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  247. },
  248. { /* QUIN TDM */
  249. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  250. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  251. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  252. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  253. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  254. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  255. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  256. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  257. }
  258. };
  259. /* TDM default config */
  260. static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  261. { /* PRI TDM */
  262. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  263. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  264. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  265. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  266. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  267. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  268. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  269. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  270. },
  271. { /* SEC TDM */
  272. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  273. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  274. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  275. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  276. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  277. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  278. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  279. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  280. },
  281. { /* TERT TDM */
  282. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  283. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  284. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  285. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  286. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  287. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  288. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  289. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  290. },
  291. { /* QUAT TDM */
  292. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  293. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  294. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  295. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  296. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  297. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  298. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  299. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  300. },
  301. { /* QUIN TDM */
  302. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  303. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  304. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  305. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  306. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  307. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  308. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  309. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  310. }
  311. };
  312. /* Default configuration of slimbus channels */
  313. static struct dev_config slim_rx_cfg[] = {
  314. [SLIM_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  315. [SLIM_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  316. [SLIM_RX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  317. [SLIM_RX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  318. [SLIM_RX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  319. [SLIM_RX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  320. [SLIM_RX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  321. [SLIM_RX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  322. };
  323. static struct dev_config slim_tx_cfg[] = {
  324. [SLIM_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  325. [SLIM_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  326. [SLIM_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  327. [SLIM_TX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  328. [SLIM_TX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  329. [SLIM_TX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  330. [SLIM_TX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  331. [SLIM_TX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  332. [SLIM_TX_8] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  333. };
  334. /* Default configuration of Codec DMA Interface Tx */
  335. static struct dev_config cdc_dma_rx_cfg[] = {
  336. [WSA_CDC_DMA_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  337. [WSA_CDC_DMA_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  338. };
  339. /* Default configuration of Codec DMA Interface Rx */
  340. static struct dev_config cdc_dma_tx_cfg[] = {
  341. [WSA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  342. [WSA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  343. [WSA_CDC_DMA_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  344. [VA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  345. [VA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  346. };
  347. static struct dev_config usb_rx_cfg = {
  348. .sample_rate = SAMPLING_RATE_48KHZ,
  349. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  350. .channels = 2,
  351. };
  352. static struct dev_config usb_tx_cfg = {
  353. .sample_rate = SAMPLING_RATE_48KHZ,
  354. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  355. .channels = 1,
  356. };
  357. static struct dev_config proxy_rx_cfg = {
  358. .sample_rate = SAMPLING_RATE_48KHZ,
  359. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  360. .channels = 2,
  361. };
  362. /* Default configuration of MI2S channels */
  363. static struct dev_config mi2s_rx_cfg[] = {
  364. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  365. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  366. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  367. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  368. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  369. [SEN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  370. };
  371. /* Default configuration of SPDIF channels */
  372. static struct dev_config spdif_rx_cfg[] = {
  373. [PRIM_SPDIF_RX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  374. [SEC_SPDIF_RX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  375. };
  376. static struct dev_config spdif_tx_cfg[] = {
  377. [PRIM_SPDIF_TX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  378. [SEC_SPDIF_TX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  379. };
  380. static struct dev_config mi2s_tx_cfg[] = {
  381. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  382. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  383. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  384. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  385. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  386. [SEN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  387. };
  388. static struct dev_config aux_pcm_rx_cfg[] = {
  389. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  390. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  391. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  392. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  393. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  394. [SEN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  395. };
  396. static struct dev_config aux_pcm_tx_cfg[] = {
  397. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  398. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  399. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  400. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  401. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  402. [SEN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  403. };
  404. static int msm_vi_feed_tx_ch = 2;
  405. static const char *const slim_rx_ch_text[] = {"One", "Two"};
  406. static const char *const slim_tx_ch_text[] = {"One", "Two", "Three", "Four",
  407. "Five", "Six", "Seven",
  408. "Eight"};
  409. static const char *const vi_feed_ch_text[] = {"One", "Two"};
  410. static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
  411. "S32_LE"};
  412. static char const *slim_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  413. "KHZ_32", "KHZ_44P1", "KHZ_48",
  414. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  415. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  416. static char const *bt_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  417. "KHZ_44P1", "KHZ_48",
  418. "KHZ_88P2", "KHZ_96"};
  419. static const char *const usb_ch_text[] = {"One", "Two", "Three", "Four",
  420. "Five", "Six", "Seven",
  421. "Eight"};
  422. static char const *ch_text[] = {"Two", "Three", "Four", "Five",
  423. "Six", "Seven", "Eight"};
  424. static char const *usb_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  425. "KHZ_16", "KHZ_22P05",
  426. "KHZ_32", "KHZ_44P1", "KHZ_48",
  427. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  428. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  429. static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four",
  430. "Five", "Six", "Seven", "Eight"};
  431. static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"};
  432. static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32",
  433. "KHZ_48", "KHZ_176P4",
  434. "KHZ_352P8"};
  435. static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"};
  436. static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_11P025", "KHZ_16",
  437. "KHZ_22P05", "KHZ_32", "KHZ_44P1",
  438. "KHZ_48", "KHZ_96", "KHZ_192", "KHZ_384"};
  439. static const char *const mi2s_ch_text[] = {
  440. "One", "Two", "Three", "Four", "Five", "Six", "Seven",
  441. "Eight", "Nine", "Ten", "Eleven", "Twelve", "Thirteen",
  442. "Fourteen", "Fifteen", "Sixteen"
  443. };
  444. static const char *const qos_text[] = {"Disable", "Enable"};
  445. static const char *const cdc_dma_rx_ch_text[] = {"One", "Two"};
  446. static const char *const cdc_dma_tx_ch_text[] = {"One", "Two", "Three", "Four",
  447. "Five", "Six", "Seven",
  448. "Eight"};
  449. static char const *cdc_dma_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  450. "KHZ_16", "KHZ_22P05",
  451. "KHZ_32", "KHZ_44P1", "KHZ_48",
  452. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  453. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  454. static const char *spdif_rate_text[] = {"KHZ_32", "KHZ_44P1", "KHZ_48",
  455. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  456. "KHZ_192"};
  457. static const char *spdif_ch_text[] = {"One", "Two"};
  458. static const char *spdif_bit_format_text[] = {"S16_LE", "S24_LE"};
  459. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_chs, slim_rx_ch_text);
  460. static SOC_ENUM_SINGLE_EXT_DECL(slim_2_rx_chs, slim_rx_ch_text);
  461. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_chs, slim_tx_ch_text);
  462. static SOC_ENUM_SINGLE_EXT_DECL(slim_1_tx_chs, slim_tx_ch_text);
  463. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_chs, slim_rx_ch_text);
  464. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_chs, slim_rx_ch_text);
  465. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_chs, usb_ch_text);
  466. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_chs, usb_ch_text);
  467. static SOC_ENUM_SINGLE_EXT_DECL(vi_feed_tx_chs, vi_feed_ch_text);
  468. static SOC_ENUM_SINGLE_EXT_DECL(proxy_rx_chs, ch_text);
  469. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_format, bit_format_text);
  470. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_format, bit_format_text);
  471. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_format, bit_format_text);
  472. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_format, bit_format_text);
  473. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_format, bit_format_text);
  474. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_format, bit_format_text);
  475. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_sample_rate, slim_sample_rate_text);
  476. static SOC_ENUM_SINGLE_EXT_DECL(slim_2_rx_sample_rate, slim_sample_rate_text);
  477. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_sample_rate, slim_sample_rate_text);
  478. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_sample_rate, slim_sample_rate_text);
  479. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_sample_rate, slim_sample_rate_text);
  480. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate, bt_sample_rate_text);
  481. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_sample_rate, usb_sample_rate_text);
  482. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_sample_rate, usb_sample_rate_text);
  483. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_chs, tdm_ch_text);
  484. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_format, tdm_bit_format_text);
  485. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text);
  486. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text);
  487. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text);
  488. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text);
  489. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  490. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  491. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  492. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  493. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  494. static SOC_ENUM_SINGLE_EXT_DECL(sen_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  495. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  496. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  497. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  498. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  499. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  500. static SOC_ENUM_SINGLE_EXT_DECL(sen_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  501. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_sample_rate, mi2s_rate_text);
  502. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_sample_rate, mi2s_rate_text);
  503. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_sample_rate, mi2s_rate_text);
  504. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_sample_rate, mi2s_rate_text);
  505. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_sample_rate, mi2s_rate_text);
  506. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_rx_sample_rate, mi2s_rate_text);
  507. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_sample_rate, mi2s_rate_text);
  508. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_sample_rate, mi2s_rate_text);
  509. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_sample_rate, mi2s_rate_text);
  510. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_sample_rate, mi2s_rate_text);
  511. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_sample_rate, mi2s_rate_text);
  512. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_tx_sample_rate, mi2s_rate_text);
  513. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_chs, mi2s_ch_text);
  514. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_chs, mi2s_ch_text);
  515. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_chs, mi2s_ch_text);
  516. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_chs, mi2s_ch_text);
  517. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_chs, mi2s_ch_text);
  518. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_chs, mi2s_ch_text);
  519. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_chs, mi2s_ch_text);
  520. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_chs, mi2s_ch_text);
  521. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_chs, mi2s_ch_text);
  522. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_chs, mi2s_ch_text);
  523. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_rx_chs, mi2s_ch_text);
  524. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_tx_chs, mi2s_ch_text);
  525. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_rx_format, bit_format_text);
  526. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_tx_format, bit_format_text);
  527. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_rx_format, bit_format_text);
  528. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_tx_format, bit_format_text);
  529. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_chs, cdc_dma_rx_ch_text);
  530. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_chs, cdc_dma_rx_ch_text);
  531. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  532. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  533. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_chs, cdc_dma_tx_ch_text);
  534. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  535. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  536. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_format, bit_format_text);
  537. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_format, bit_format_text);
  538. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_format, bit_format_text);
  539. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_format, bit_format_text);
  540. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_format, bit_format_text);
  541. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_format, bit_format_text);
  542. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_sample_rate,
  543. cdc_dma_sample_rate_text);
  544. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_sample_rate,
  545. cdc_dma_sample_rate_text);
  546. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_sample_rate,
  547. cdc_dma_sample_rate_text);
  548. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_sample_rate,
  549. cdc_dma_sample_rate_text);
  550. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_sample_rate,
  551. cdc_dma_sample_rate_text);
  552. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_sample_rate,
  553. cdc_dma_sample_rate_text);
  554. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_sample_rate,
  555. cdc_dma_sample_rate_text);
  556. static SOC_ENUM_SINGLE_EXT_DECL(spdif_rx_sample_rate, spdif_rate_text);
  557. static SOC_ENUM_SINGLE_EXT_DECL(spdif_tx_sample_rate, spdif_rate_text);
  558. static SOC_ENUM_SINGLE_EXT_DECL(spdif_rx_chs, spdif_ch_text);
  559. static SOC_ENUM_SINGLE_EXT_DECL(spdif_tx_chs, spdif_ch_text);
  560. static SOC_ENUM_SINGLE_EXT_DECL(spdif_rx_format, spdif_bit_format_text);
  561. static SOC_ENUM_SINGLE_EXT_DECL(spdif_tx_format, spdif_bit_format_text);
  562. static struct platform_device *spdev;
  563. static bool is_initial_boot;
  564. static bool codec_reg_done;
  565. static struct snd_soc_aux_dev *msm_aux_dev;
  566. static struct snd_soc_codec_conf *msm_codec_conf;
  567. static struct msm_asoc_wcd93xx_codec msm_codec_fn;
  568. static int msm_snd_enable_codec_ext_clk(struct snd_soc_codec *codec,
  569. int enable, bool dapm);
  570. static int msm_wsa881x_init(struct snd_soc_component *component);
  571. static int msm_snd_vad_cfg_put(struct snd_kcontrol *kcontrol,
  572. struct snd_ctl_elem_value *ucontrol);
  573. static struct snd_soc_dapm_route wcd_audio_paths[] = {
  574. {"MIC BIAS1", NULL, "MCLK TX"},
  575. {"MIC BIAS2", NULL, "MCLK TX"},
  576. {"MIC BIAS3", NULL, "MCLK TX"},
  577. {"MIC BIAS4", NULL, "MCLK TX"},
  578. };
  579. static struct afe_clk_set mi2s_clk[MI2S_MAX] = {
  580. {
  581. AFE_API_VERSION_I2S_CONFIG,
  582. Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
  583. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  584. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  585. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  586. 0,
  587. },
  588. {
  589. AFE_API_VERSION_I2S_CONFIG,
  590. Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
  591. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  592. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  593. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  594. 0,
  595. },
  596. {
  597. AFE_API_VERSION_I2S_CONFIG,
  598. Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
  599. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  600. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  601. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  602. 0,
  603. },
  604. {
  605. AFE_API_VERSION_I2S_CONFIG,
  606. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT,
  607. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  608. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  609. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  610. 0,
  611. },
  612. {
  613. AFE_API_VERSION_I2S_CONFIG,
  614. Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT,
  615. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  616. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  617. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  618. 0,
  619. },
  620. {
  621. AFE_API_VERSION_I2S_CONFIG,
  622. Q6AFE_LPASS_CLK_ID_SEN_MI2S_IBIT,
  623. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  624. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  625. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  626. 0,
  627. }
  628. };
  629. static struct mi2s_conf mi2s_intf_conf[MI2S_MAX];
  630. static int slim_get_sample_rate_val(int sample_rate)
  631. {
  632. int sample_rate_val = 0;
  633. switch (sample_rate) {
  634. case SAMPLING_RATE_8KHZ:
  635. sample_rate_val = 0;
  636. break;
  637. case SAMPLING_RATE_16KHZ:
  638. sample_rate_val = 1;
  639. break;
  640. case SAMPLING_RATE_32KHZ:
  641. sample_rate_val = 2;
  642. break;
  643. case SAMPLING_RATE_44P1KHZ:
  644. sample_rate_val = 3;
  645. break;
  646. case SAMPLING_RATE_48KHZ:
  647. sample_rate_val = 4;
  648. break;
  649. case SAMPLING_RATE_88P2KHZ:
  650. sample_rate_val = 5;
  651. break;
  652. case SAMPLING_RATE_96KHZ:
  653. sample_rate_val = 6;
  654. break;
  655. case SAMPLING_RATE_176P4KHZ:
  656. sample_rate_val = 7;
  657. break;
  658. case SAMPLING_RATE_192KHZ:
  659. sample_rate_val = 8;
  660. break;
  661. case SAMPLING_RATE_352P8KHZ:
  662. sample_rate_val = 9;
  663. break;
  664. case SAMPLING_RATE_384KHZ:
  665. sample_rate_val = 10;
  666. break;
  667. default:
  668. sample_rate_val = 4;
  669. break;
  670. }
  671. return sample_rate_val;
  672. }
  673. static int slim_get_sample_rate(int value)
  674. {
  675. int sample_rate = 0;
  676. switch (value) {
  677. case 0:
  678. sample_rate = SAMPLING_RATE_8KHZ;
  679. break;
  680. case 1:
  681. sample_rate = SAMPLING_RATE_16KHZ;
  682. break;
  683. case 2:
  684. sample_rate = SAMPLING_RATE_32KHZ;
  685. break;
  686. case 3:
  687. sample_rate = SAMPLING_RATE_44P1KHZ;
  688. break;
  689. case 4:
  690. sample_rate = SAMPLING_RATE_48KHZ;
  691. break;
  692. case 5:
  693. sample_rate = SAMPLING_RATE_88P2KHZ;
  694. break;
  695. case 6:
  696. sample_rate = SAMPLING_RATE_96KHZ;
  697. break;
  698. case 7:
  699. sample_rate = SAMPLING_RATE_176P4KHZ;
  700. break;
  701. case 8:
  702. sample_rate = SAMPLING_RATE_192KHZ;
  703. break;
  704. case 9:
  705. sample_rate = SAMPLING_RATE_352P8KHZ;
  706. break;
  707. case 10:
  708. sample_rate = SAMPLING_RATE_384KHZ;
  709. break;
  710. default:
  711. sample_rate = SAMPLING_RATE_48KHZ;
  712. break;
  713. }
  714. return sample_rate;
  715. }
  716. static int slim_get_bit_format_val(int bit_format)
  717. {
  718. int val = 0;
  719. switch (bit_format) {
  720. case SNDRV_PCM_FORMAT_S32_LE:
  721. val = 3;
  722. break;
  723. case SNDRV_PCM_FORMAT_S24_3LE:
  724. val = 2;
  725. break;
  726. case SNDRV_PCM_FORMAT_S24_LE:
  727. val = 1;
  728. break;
  729. case SNDRV_PCM_FORMAT_S16_LE:
  730. default:
  731. val = 0;
  732. break;
  733. }
  734. return val;
  735. }
  736. static int slim_get_bit_format(int val)
  737. {
  738. int bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  739. switch (val) {
  740. case 0:
  741. bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  742. break;
  743. case 1:
  744. bit_fmt = SNDRV_PCM_FORMAT_S24_LE;
  745. break;
  746. case 2:
  747. bit_fmt = SNDRV_PCM_FORMAT_S24_3LE;
  748. break;
  749. case 3:
  750. bit_fmt = SNDRV_PCM_FORMAT_S32_LE;
  751. break;
  752. default:
  753. bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  754. break;
  755. }
  756. return bit_fmt;
  757. }
  758. static int slim_get_port_idx(struct snd_kcontrol *kcontrol)
  759. {
  760. int port_id = 0;
  761. if (strnstr(kcontrol->id.name, "SLIM_0_RX", sizeof("SLIM_0_RX"))) {
  762. port_id = SLIM_RX_0;
  763. } else if (strnstr(kcontrol->id.name,
  764. "SLIM_2_RX", sizeof("SLIM_2_RX"))) {
  765. port_id = SLIM_RX_2;
  766. } else if (strnstr(kcontrol->id.name,
  767. "SLIM_5_RX", sizeof("SLIM_5_RX"))) {
  768. port_id = SLIM_RX_5;
  769. } else if (strnstr(kcontrol->id.name,
  770. "SLIM_6_RX", sizeof("SLIM_6_RX"))) {
  771. port_id = SLIM_RX_6;
  772. } else if (strnstr(kcontrol->id.name,
  773. "SLIM_0_TX", sizeof("SLIM_0_TX"))) {
  774. port_id = SLIM_TX_0;
  775. } else if (strnstr(kcontrol->id.name,
  776. "SLIM_1_TX", sizeof("SLIM_1_TX"))) {
  777. port_id = SLIM_TX_1;
  778. } else {
  779. pr_err("%s: unsupported channel: %s",
  780. __func__, kcontrol->id.name);
  781. return -EINVAL;
  782. }
  783. return port_id;
  784. }
  785. static int slim_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  786. struct snd_ctl_elem_value *ucontrol)
  787. {
  788. int ch_num = slim_get_port_idx(kcontrol);
  789. if (ch_num < 0)
  790. return ch_num;
  791. ucontrol->value.enumerated.item[0] =
  792. slim_get_sample_rate_val(slim_rx_cfg[ch_num].sample_rate);
  793. pr_debug("%s: slim[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  794. ch_num, slim_rx_cfg[ch_num].sample_rate,
  795. ucontrol->value.enumerated.item[0]);
  796. return 0;
  797. }
  798. static int slim_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  799. struct snd_ctl_elem_value *ucontrol)
  800. {
  801. int ch_num = slim_get_port_idx(kcontrol);
  802. if (ch_num < 0)
  803. return ch_num;
  804. slim_rx_cfg[ch_num].sample_rate =
  805. slim_get_sample_rate(ucontrol->value.enumerated.item[0]);
  806. pr_debug("%s: slim[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  807. ch_num, slim_rx_cfg[ch_num].sample_rate,
  808. ucontrol->value.enumerated.item[0]);
  809. return 0;
  810. }
  811. static int slim_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  812. struct snd_ctl_elem_value *ucontrol)
  813. {
  814. int ch_num = slim_get_port_idx(kcontrol);
  815. if (ch_num < 0)
  816. return ch_num;
  817. ucontrol->value.enumerated.item[0] =
  818. slim_get_sample_rate_val(slim_tx_cfg[ch_num].sample_rate);
  819. pr_debug("%s: slim[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  820. ch_num, slim_tx_cfg[ch_num].sample_rate,
  821. ucontrol->value.enumerated.item[0]);
  822. return 0;
  823. }
  824. static int slim_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  825. struct snd_ctl_elem_value *ucontrol)
  826. {
  827. int sample_rate = 0;
  828. int ch_num = slim_get_port_idx(kcontrol);
  829. if (ch_num < 0)
  830. return ch_num;
  831. sample_rate = slim_get_sample_rate(ucontrol->value.enumerated.item[0]);
  832. if (sample_rate == SAMPLING_RATE_44P1KHZ) {
  833. pr_err("%s: Unsupported sample rate %d: for Tx path\n",
  834. __func__, sample_rate);
  835. return -EINVAL;
  836. }
  837. slim_tx_cfg[ch_num].sample_rate = sample_rate;
  838. pr_debug("%s: slim[%d]_tx_sample_rate = %d, value = %d\n", __func__,
  839. ch_num, slim_tx_cfg[ch_num].sample_rate,
  840. ucontrol->value.enumerated.item[0]);
  841. return 0;
  842. }
  843. static int slim_rx_bit_format_get(struct snd_kcontrol *kcontrol,
  844. struct snd_ctl_elem_value *ucontrol)
  845. {
  846. int ch_num = slim_get_port_idx(kcontrol);
  847. if (ch_num < 0)
  848. return ch_num;
  849. ucontrol->value.enumerated.item[0] =
  850. slim_get_bit_format_val(slim_rx_cfg[ch_num].bit_format);
  851. pr_debug("%s: slim[%d]_rx_bit_format = %d, ucontrol value = %d\n",
  852. __func__, ch_num, slim_rx_cfg[ch_num].bit_format,
  853. ucontrol->value.enumerated.item[0]);
  854. return 0;
  855. }
  856. static int slim_rx_bit_format_put(struct snd_kcontrol *kcontrol,
  857. struct snd_ctl_elem_value *ucontrol)
  858. {
  859. int ch_num = slim_get_port_idx(kcontrol);
  860. if (ch_num < 0)
  861. return ch_num;
  862. slim_rx_cfg[ch_num].bit_format =
  863. slim_get_bit_format(ucontrol->value.enumerated.item[0]);
  864. pr_debug("%s: slim[%d]_rx_bit_format = %d, ucontrol value = %d\n",
  865. __func__, ch_num, slim_rx_cfg[ch_num].bit_format,
  866. ucontrol->value.enumerated.item[0]);
  867. return 0;
  868. }
  869. static int slim_tx_bit_format_get(struct snd_kcontrol *kcontrol,
  870. struct snd_ctl_elem_value *ucontrol)
  871. {
  872. int ch_num = slim_get_port_idx(kcontrol);
  873. if (ch_num < 0)
  874. return ch_num;
  875. ucontrol->value.enumerated.item[0] =
  876. slim_get_bit_format_val(slim_tx_cfg[ch_num].bit_format);
  877. pr_debug("%s: slim[%d]_tx_bit_format = %d, ucontrol value = %d\n",
  878. __func__, ch_num, slim_tx_cfg[ch_num].bit_format,
  879. ucontrol->value.enumerated.item[0]);
  880. return 0;
  881. }
  882. static int slim_tx_bit_format_put(struct snd_kcontrol *kcontrol,
  883. struct snd_ctl_elem_value *ucontrol)
  884. {
  885. int ch_num = slim_get_port_idx(kcontrol);
  886. if (ch_num < 0)
  887. return ch_num;
  888. slim_tx_cfg[ch_num].bit_format =
  889. slim_get_bit_format(ucontrol->value.enumerated.item[0]);
  890. pr_debug("%s: slim[%d]_tx_bit_format = %d, ucontrol value = %d\n",
  891. __func__, ch_num, slim_tx_cfg[ch_num].bit_format,
  892. ucontrol->value.enumerated.item[0]);
  893. return 0;
  894. }
  895. static int slim_rx_ch_get(struct snd_kcontrol *kcontrol,
  896. struct snd_ctl_elem_value *ucontrol)
  897. {
  898. int ch_num = slim_get_port_idx(kcontrol);
  899. if (ch_num < 0)
  900. return ch_num;
  901. pr_debug("%s: msm_slim_[%d]_rx_ch = %d\n", __func__,
  902. ch_num, slim_rx_cfg[ch_num].channels);
  903. ucontrol->value.enumerated.item[0] = slim_rx_cfg[ch_num].channels - 1;
  904. return 0;
  905. }
  906. static int slim_rx_ch_put(struct snd_kcontrol *kcontrol,
  907. struct snd_ctl_elem_value *ucontrol)
  908. {
  909. int ch_num = slim_get_port_idx(kcontrol);
  910. if (ch_num < 0)
  911. return ch_num;
  912. slim_rx_cfg[ch_num].channels = ucontrol->value.enumerated.item[0] + 1;
  913. pr_debug("%s: msm_slim_[%d]_rx_ch = %d\n", __func__,
  914. ch_num, slim_rx_cfg[ch_num].channels);
  915. return 1;
  916. }
  917. static int slim_tx_ch_get(struct snd_kcontrol *kcontrol,
  918. struct snd_ctl_elem_value *ucontrol)
  919. {
  920. int ch_num = slim_get_port_idx(kcontrol);
  921. if (ch_num < 0)
  922. return ch_num;
  923. pr_debug("%s: msm_slim_[%d]_tx_ch = %d\n", __func__,
  924. ch_num, slim_tx_cfg[ch_num].channels);
  925. ucontrol->value.enumerated.item[0] = slim_tx_cfg[ch_num].channels - 1;
  926. return 0;
  927. }
  928. static int slim_tx_ch_put(struct snd_kcontrol *kcontrol,
  929. struct snd_ctl_elem_value *ucontrol)
  930. {
  931. int ch_num = slim_get_port_idx(kcontrol);
  932. if (ch_num < 0)
  933. return ch_num;
  934. slim_tx_cfg[ch_num].channels = ucontrol->value.enumerated.item[0] + 1;
  935. pr_debug("%s: msm_slim_[%d]_tx_ch = %d\n", __func__,
  936. ch_num, slim_tx_cfg[ch_num].channels);
  937. return 1;
  938. }
  939. static int msm_vi_feed_tx_ch_get(struct snd_kcontrol *kcontrol,
  940. struct snd_ctl_elem_value *ucontrol)
  941. {
  942. ucontrol->value.integer.value[0] = msm_vi_feed_tx_ch - 1;
  943. pr_debug("%s: msm_vi_feed_tx_ch = %ld\n", __func__,
  944. ucontrol->value.integer.value[0]);
  945. return 0;
  946. }
  947. static int msm_vi_feed_tx_ch_put(struct snd_kcontrol *kcontrol,
  948. struct snd_ctl_elem_value *ucontrol)
  949. {
  950. msm_vi_feed_tx_ch = ucontrol->value.integer.value[0] + 1;
  951. pr_debug("%s: msm_vi_feed_tx_ch = %d\n", __func__, msm_vi_feed_tx_ch);
  952. return 1;
  953. }
  954. static int msm_bt_sample_rate_get(struct snd_kcontrol *kcontrol,
  955. struct snd_ctl_elem_value *ucontrol)
  956. {
  957. /*
  958. * Slimbus_7_Rx/Tx sample rate values should always be in sync (same)
  959. * when used for BT_SCO use case. Return either Rx or Tx sample rate
  960. * value.
  961. */
  962. switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
  963. case SAMPLING_RATE_96KHZ:
  964. ucontrol->value.integer.value[0] = 5;
  965. break;
  966. case SAMPLING_RATE_88P2KHZ:
  967. ucontrol->value.integer.value[0] = 4;
  968. break;
  969. case SAMPLING_RATE_48KHZ:
  970. ucontrol->value.integer.value[0] = 3;
  971. break;
  972. case SAMPLING_RATE_44P1KHZ:
  973. ucontrol->value.integer.value[0] = 2;
  974. break;
  975. case SAMPLING_RATE_16KHZ:
  976. ucontrol->value.integer.value[0] = 1;
  977. break;
  978. case SAMPLING_RATE_8KHZ:
  979. default:
  980. ucontrol->value.integer.value[0] = 0;
  981. break;
  982. }
  983. pr_debug("%s: sample rate = %d", __func__,
  984. slim_rx_cfg[SLIM_RX_7].sample_rate);
  985. return 0;
  986. }
  987. static int msm_bt_sample_rate_put(struct snd_kcontrol *kcontrol,
  988. struct snd_ctl_elem_value *ucontrol)
  989. {
  990. switch (ucontrol->value.integer.value[0]) {
  991. case 1:
  992. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
  993. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
  994. break;
  995. case 2:
  996. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  997. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  998. break;
  999. case 3:
  1000. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
  1001. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
  1002. break;
  1003. case 4:
  1004. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  1005. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  1006. break;
  1007. case 5:
  1008. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
  1009. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
  1010. break;
  1011. case 0:
  1012. default:
  1013. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
  1014. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
  1015. break;
  1016. }
  1017. pr_debug("%s: sample rates: slim7_rx = %d, slim7_tx = %d, value = %d\n",
  1018. __func__,
  1019. slim_rx_cfg[SLIM_RX_7].sample_rate,
  1020. slim_tx_cfg[SLIM_TX_7].sample_rate,
  1021. ucontrol->value.enumerated.item[0]);
  1022. return 0;
  1023. }
  1024. static int cdc_dma_get_port_idx(struct snd_kcontrol *kcontrol)
  1025. {
  1026. int idx = 0;
  1027. if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_0",
  1028. sizeof("WSA_CDC_DMA_RX_0")))
  1029. idx = WSA_CDC_DMA_RX_0;
  1030. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_1",
  1031. sizeof("WSA_CDC_DMA_RX_0")))
  1032. idx = WSA_CDC_DMA_RX_1;
  1033. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_0",
  1034. sizeof("WSA_CDC_DMA_TX_0")))
  1035. idx = WSA_CDC_DMA_TX_0;
  1036. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_1",
  1037. sizeof("WSA_CDC_DMA_TX_1")))
  1038. idx = WSA_CDC_DMA_TX_1;
  1039. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_2",
  1040. sizeof("WSA_CDC_DMA_TX_2")))
  1041. idx = WSA_CDC_DMA_TX_2;
  1042. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_0",
  1043. sizeof("VA_CDC_DMA_TX_0")))
  1044. idx = VA_CDC_DMA_TX_0;
  1045. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_1",
  1046. sizeof("VA_CDC_DMA_TX_1")))
  1047. idx = VA_CDC_DMA_TX_1;
  1048. else {
  1049. pr_err("%s: unsupported port: %s\n",
  1050. __func__, kcontrol->id.name);
  1051. return -EINVAL;
  1052. }
  1053. return idx;
  1054. }
  1055. static int cdc_dma_rx_ch_get(struct snd_kcontrol *kcontrol,
  1056. struct snd_ctl_elem_value *ucontrol)
  1057. {
  1058. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1059. if (ch_num < 0)
  1060. return ch_num;
  1061. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  1062. cdc_dma_rx_cfg[ch_num].channels - 1);
  1063. ucontrol->value.integer.value[0] = cdc_dma_rx_cfg[ch_num].channels - 1;
  1064. return 0;
  1065. }
  1066. static int cdc_dma_rx_ch_put(struct snd_kcontrol *kcontrol,
  1067. struct snd_ctl_elem_value *ucontrol)
  1068. {
  1069. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1070. if (ch_num < 0)
  1071. return ch_num;
  1072. cdc_dma_rx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  1073. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  1074. cdc_dma_rx_cfg[ch_num].channels);
  1075. return 1;
  1076. }
  1077. static int cdc_dma_rx_format_get(struct snd_kcontrol *kcontrol,
  1078. struct snd_ctl_elem_value *ucontrol)
  1079. {
  1080. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1081. switch (cdc_dma_rx_cfg[ch_num].bit_format) {
  1082. case SNDRV_PCM_FORMAT_S32_LE:
  1083. ucontrol->value.integer.value[0] = 3;
  1084. break;
  1085. case SNDRV_PCM_FORMAT_S24_3LE:
  1086. ucontrol->value.integer.value[0] = 2;
  1087. break;
  1088. case SNDRV_PCM_FORMAT_S24_LE:
  1089. ucontrol->value.integer.value[0] = 1;
  1090. break;
  1091. case SNDRV_PCM_FORMAT_S16_LE:
  1092. default:
  1093. ucontrol->value.integer.value[0] = 0;
  1094. break;
  1095. }
  1096. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  1097. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  1098. ucontrol->value.integer.value[0]);
  1099. return 0;
  1100. }
  1101. static int cdc_dma_rx_format_put(struct snd_kcontrol *kcontrol,
  1102. struct snd_ctl_elem_value *ucontrol)
  1103. {
  1104. int rc = 0;
  1105. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1106. switch (ucontrol->value.integer.value[0]) {
  1107. case 3:
  1108. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1109. break;
  1110. case 2:
  1111. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1112. break;
  1113. case 1:
  1114. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1115. break;
  1116. case 0:
  1117. default:
  1118. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1119. break;
  1120. }
  1121. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  1122. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  1123. ucontrol->value.integer.value[0]);
  1124. return rc;
  1125. }
  1126. static int cdc_dma_get_sample_rate_val(int sample_rate)
  1127. {
  1128. int sample_rate_val = 0;
  1129. switch (sample_rate) {
  1130. case SAMPLING_RATE_8KHZ:
  1131. sample_rate_val = 0;
  1132. break;
  1133. case SAMPLING_RATE_11P025KHZ:
  1134. sample_rate_val = 1;
  1135. break;
  1136. case SAMPLING_RATE_16KHZ:
  1137. sample_rate_val = 2;
  1138. break;
  1139. case SAMPLING_RATE_22P05KHZ:
  1140. sample_rate_val = 3;
  1141. break;
  1142. case SAMPLING_RATE_32KHZ:
  1143. sample_rate_val = 4;
  1144. break;
  1145. case SAMPLING_RATE_44P1KHZ:
  1146. sample_rate_val = 5;
  1147. break;
  1148. case SAMPLING_RATE_48KHZ:
  1149. sample_rate_val = 6;
  1150. break;
  1151. case SAMPLING_RATE_88P2KHZ:
  1152. sample_rate_val = 7;
  1153. break;
  1154. case SAMPLING_RATE_96KHZ:
  1155. sample_rate_val = 8;
  1156. break;
  1157. case SAMPLING_RATE_176P4KHZ:
  1158. sample_rate_val = 9;
  1159. break;
  1160. case SAMPLING_RATE_192KHZ:
  1161. sample_rate_val = 10;
  1162. break;
  1163. case SAMPLING_RATE_352P8KHZ:
  1164. sample_rate_val = 11;
  1165. break;
  1166. case SAMPLING_RATE_384KHZ:
  1167. sample_rate_val = 12;
  1168. break;
  1169. default:
  1170. sample_rate_val = 6;
  1171. break;
  1172. }
  1173. return sample_rate_val;
  1174. }
  1175. static int cdc_dma_get_sample_rate(int value)
  1176. {
  1177. int sample_rate = 0;
  1178. switch (value) {
  1179. case 0:
  1180. sample_rate = SAMPLING_RATE_8KHZ;
  1181. break;
  1182. case 1:
  1183. sample_rate = SAMPLING_RATE_11P025KHZ;
  1184. break;
  1185. case 2:
  1186. sample_rate = SAMPLING_RATE_16KHZ;
  1187. break;
  1188. case 3:
  1189. sample_rate = SAMPLING_RATE_22P05KHZ;
  1190. break;
  1191. case 4:
  1192. sample_rate = SAMPLING_RATE_32KHZ;
  1193. break;
  1194. case 5:
  1195. sample_rate = SAMPLING_RATE_44P1KHZ;
  1196. break;
  1197. case 6:
  1198. sample_rate = SAMPLING_RATE_48KHZ;
  1199. break;
  1200. case 7:
  1201. sample_rate = SAMPLING_RATE_88P2KHZ;
  1202. break;
  1203. case 8:
  1204. sample_rate = SAMPLING_RATE_96KHZ;
  1205. break;
  1206. case 9:
  1207. sample_rate = SAMPLING_RATE_176P4KHZ;
  1208. break;
  1209. case 10:
  1210. sample_rate = SAMPLING_RATE_192KHZ;
  1211. break;
  1212. case 11:
  1213. sample_rate = SAMPLING_RATE_352P8KHZ;
  1214. break;
  1215. case 12:
  1216. sample_rate = SAMPLING_RATE_384KHZ;
  1217. break;
  1218. default:
  1219. sample_rate = SAMPLING_RATE_48KHZ;
  1220. break;
  1221. }
  1222. return sample_rate;
  1223. }
  1224. static int cdc_dma_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1225. struct snd_ctl_elem_value *ucontrol)
  1226. {
  1227. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1228. if (ch_num < 0)
  1229. return ch_num;
  1230. ucontrol->value.enumerated.item[0] =
  1231. cdc_dma_get_sample_rate_val(cdc_dma_rx_cfg[ch_num].sample_rate);
  1232. pr_debug("%s: cdc_dma_rx_sample_rate = %d\n", __func__,
  1233. cdc_dma_rx_cfg[ch_num].sample_rate);
  1234. return 0;
  1235. }
  1236. static int cdc_dma_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1237. struct snd_ctl_elem_value *ucontrol)
  1238. {
  1239. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1240. if (ch_num < 0)
  1241. return ch_num;
  1242. cdc_dma_rx_cfg[ch_num].sample_rate =
  1243. cdc_dma_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1244. pr_debug("%s: control value = %d, cdc_dma_rx_sample_rate = %d\n",
  1245. __func__, ucontrol->value.enumerated.item[0],
  1246. cdc_dma_rx_cfg[ch_num].sample_rate);
  1247. return 0;
  1248. }
  1249. static int cdc_dma_tx_ch_get(struct snd_kcontrol *kcontrol,
  1250. struct snd_ctl_elem_value *ucontrol)
  1251. {
  1252. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1253. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  1254. cdc_dma_tx_cfg[ch_num].channels);
  1255. ucontrol->value.integer.value[0] = cdc_dma_tx_cfg[ch_num].channels - 1;
  1256. return 0;
  1257. }
  1258. static int cdc_dma_tx_ch_put(struct snd_kcontrol *kcontrol,
  1259. struct snd_ctl_elem_value *ucontrol)
  1260. {
  1261. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1262. cdc_dma_tx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  1263. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  1264. cdc_dma_tx_cfg[ch_num].channels);
  1265. return 1;
  1266. }
  1267. static int cdc_dma_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1268. struct snd_ctl_elem_value *ucontrol)
  1269. {
  1270. int sample_rate_val;
  1271. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1272. switch (cdc_dma_tx_cfg[ch_num].sample_rate) {
  1273. case SAMPLING_RATE_384KHZ:
  1274. sample_rate_val = 12;
  1275. break;
  1276. case SAMPLING_RATE_352P8KHZ:
  1277. sample_rate_val = 11;
  1278. break;
  1279. case SAMPLING_RATE_192KHZ:
  1280. sample_rate_val = 10;
  1281. break;
  1282. case SAMPLING_RATE_176P4KHZ:
  1283. sample_rate_val = 9;
  1284. break;
  1285. case SAMPLING_RATE_96KHZ:
  1286. sample_rate_val = 8;
  1287. break;
  1288. case SAMPLING_RATE_88P2KHZ:
  1289. sample_rate_val = 7;
  1290. break;
  1291. case SAMPLING_RATE_48KHZ:
  1292. sample_rate_val = 6;
  1293. break;
  1294. case SAMPLING_RATE_44P1KHZ:
  1295. sample_rate_val = 5;
  1296. break;
  1297. case SAMPLING_RATE_32KHZ:
  1298. sample_rate_val = 4;
  1299. break;
  1300. case SAMPLING_RATE_22P05KHZ:
  1301. sample_rate_val = 3;
  1302. break;
  1303. case SAMPLING_RATE_16KHZ:
  1304. sample_rate_val = 2;
  1305. break;
  1306. case SAMPLING_RATE_11P025KHZ:
  1307. sample_rate_val = 1;
  1308. break;
  1309. case SAMPLING_RATE_8KHZ:
  1310. sample_rate_val = 0;
  1311. break;
  1312. default:
  1313. sample_rate_val = 6;
  1314. break;
  1315. }
  1316. ucontrol->value.integer.value[0] = sample_rate_val;
  1317. pr_debug("%s: cdc_dma_tx_sample_rate = %d\n", __func__,
  1318. cdc_dma_tx_cfg[ch_num].sample_rate);
  1319. return 0;
  1320. }
  1321. static int cdc_dma_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1322. struct snd_ctl_elem_value *ucontrol)
  1323. {
  1324. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1325. switch (ucontrol->value.integer.value[0]) {
  1326. case 12:
  1327. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_384KHZ;
  1328. break;
  1329. case 11:
  1330. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_352P8KHZ;
  1331. break;
  1332. case 10:
  1333. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_192KHZ;
  1334. break;
  1335. case 9:
  1336. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_176P4KHZ;
  1337. break;
  1338. case 8:
  1339. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_96KHZ;
  1340. break;
  1341. case 7:
  1342. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_88P2KHZ;
  1343. break;
  1344. case 6:
  1345. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  1346. break;
  1347. case 5:
  1348. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_44P1KHZ;
  1349. break;
  1350. case 4:
  1351. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_32KHZ;
  1352. break;
  1353. case 3:
  1354. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_22P05KHZ;
  1355. break;
  1356. case 2:
  1357. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_16KHZ;
  1358. break;
  1359. case 1:
  1360. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_11P025KHZ;
  1361. break;
  1362. case 0:
  1363. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_8KHZ;
  1364. break;
  1365. default:
  1366. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  1367. break;
  1368. }
  1369. pr_debug("%s: control value = %ld, cdc_dma_tx_sample_rate = %d\n",
  1370. __func__, ucontrol->value.integer.value[0],
  1371. cdc_dma_tx_cfg[ch_num].sample_rate);
  1372. return 0;
  1373. }
  1374. static int cdc_dma_tx_format_get(struct snd_kcontrol *kcontrol,
  1375. struct snd_ctl_elem_value *ucontrol)
  1376. {
  1377. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1378. switch (cdc_dma_tx_cfg[ch_num].bit_format) {
  1379. case SNDRV_PCM_FORMAT_S32_LE:
  1380. ucontrol->value.integer.value[0] = 3;
  1381. break;
  1382. case SNDRV_PCM_FORMAT_S24_3LE:
  1383. ucontrol->value.integer.value[0] = 2;
  1384. break;
  1385. case SNDRV_PCM_FORMAT_S24_LE:
  1386. ucontrol->value.integer.value[0] = 1;
  1387. break;
  1388. case SNDRV_PCM_FORMAT_S16_LE:
  1389. default:
  1390. ucontrol->value.integer.value[0] = 0;
  1391. break;
  1392. }
  1393. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  1394. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  1395. ucontrol->value.integer.value[0]);
  1396. return 0;
  1397. }
  1398. static int cdc_dma_tx_format_put(struct snd_kcontrol *kcontrol,
  1399. struct snd_ctl_elem_value *ucontrol)
  1400. {
  1401. int rc = 0;
  1402. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1403. switch (ucontrol->value.integer.value[0]) {
  1404. case 3:
  1405. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1406. break;
  1407. case 2:
  1408. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1409. break;
  1410. case 1:
  1411. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1412. break;
  1413. case 0:
  1414. default:
  1415. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1416. break;
  1417. }
  1418. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  1419. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  1420. ucontrol->value.integer.value[0]);
  1421. return rc;
  1422. }
  1423. static int usb_audio_rx_ch_get(struct snd_kcontrol *kcontrol,
  1424. struct snd_ctl_elem_value *ucontrol)
  1425. {
  1426. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__,
  1427. usb_rx_cfg.channels);
  1428. ucontrol->value.integer.value[0] = usb_rx_cfg.channels - 1;
  1429. return 0;
  1430. }
  1431. static int usb_audio_rx_ch_put(struct snd_kcontrol *kcontrol,
  1432. struct snd_ctl_elem_value *ucontrol)
  1433. {
  1434. usb_rx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1435. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, usb_rx_cfg.channels);
  1436. return 1;
  1437. }
  1438. static int usb_audio_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1439. struct snd_ctl_elem_value *ucontrol)
  1440. {
  1441. int sample_rate_val;
  1442. switch (usb_rx_cfg.sample_rate) {
  1443. case SAMPLING_RATE_384KHZ:
  1444. sample_rate_val = 12;
  1445. break;
  1446. case SAMPLING_RATE_352P8KHZ:
  1447. sample_rate_val = 11;
  1448. break;
  1449. case SAMPLING_RATE_192KHZ:
  1450. sample_rate_val = 10;
  1451. break;
  1452. case SAMPLING_RATE_176P4KHZ:
  1453. sample_rate_val = 9;
  1454. break;
  1455. case SAMPLING_RATE_96KHZ:
  1456. sample_rate_val = 8;
  1457. break;
  1458. case SAMPLING_RATE_88P2KHZ:
  1459. sample_rate_val = 7;
  1460. break;
  1461. case SAMPLING_RATE_48KHZ:
  1462. sample_rate_val = 6;
  1463. break;
  1464. case SAMPLING_RATE_44P1KHZ:
  1465. sample_rate_val = 5;
  1466. break;
  1467. case SAMPLING_RATE_32KHZ:
  1468. sample_rate_val = 4;
  1469. break;
  1470. case SAMPLING_RATE_22P05KHZ:
  1471. sample_rate_val = 3;
  1472. break;
  1473. case SAMPLING_RATE_16KHZ:
  1474. sample_rate_val = 2;
  1475. break;
  1476. case SAMPLING_RATE_11P025KHZ:
  1477. sample_rate_val = 1;
  1478. break;
  1479. case SAMPLING_RATE_8KHZ:
  1480. default:
  1481. sample_rate_val = 0;
  1482. break;
  1483. }
  1484. ucontrol->value.integer.value[0] = sample_rate_val;
  1485. pr_debug("%s: usb_audio_rx_sample_rate = %d\n", __func__,
  1486. usb_rx_cfg.sample_rate);
  1487. return 0;
  1488. }
  1489. static int usb_audio_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1490. struct snd_ctl_elem_value *ucontrol)
  1491. {
  1492. switch (ucontrol->value.integer.value[0]) {
  1493. case 12:
  1494. usb_rx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1495. break;
  1496. case 11:
  1497. usb_rx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  1498. break;
  1499. case 10:
  1500. usb_rx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1501. break;
  1502. case 9:
  1503. usb_rx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  1504. break;
  1505. case 8:
  1506. usb_rx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1507. break;
  1508. case 7:
  1509. usb_rx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  1510. break;
  1511. case 6:
  1512. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1513. break;
  1514. case 5:
  1515. usb_rx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1516. break;
  1517. case 4:
  1518. usb_rx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1519. break;
  1520. case 3:
  1521. usb_rx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1522. break;
  1523. case 2:
  1524. usb_rx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1525. break;
  1526. case 1:
  1527. usb_rx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1528. break;
  1529. case 0:
  1530. usb_rx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1531. break;
  1532. default:
  1533. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1534. break;
  1535. }
  1536. pr_debug("%s: control value = %ld, usb_audio_rx_sample_rate = %d\n",
  1537. __func__, ucontrol->value.integer.value[0],
  1538. usb_rx_cfg.sample_rate);
  1539. return 0;
  1540. }
  1541. static int usb_audio_rx_format_get(struct snd_kcontrol *kcontrol,
  1542. struct snd_ctl_elem_value *ucontrol)
  1543. {
  1544. switch (usb_rx_cfg.bit_format) {
  1545. case SNDRV_PCM_FORMAT_S32_LE:
  1546. ucontrol->value.integer.value[0] = 3;
  1547. break;
  1548. case SNDRV_PCM_FORMAT_S24_3LE:
  1549. ucontrol->value.integer.value[0] = 2;
  1550. break;
  1551. case SNDRV_PCM_FORMAT_S24_LE:
  1552. ucontrol->value.integer.value[0] = 1;
  1553. break;
  1554. case SNDRV_PCM_FORMAT_S16_LE:
  1555. default:
  1556. ucontrol->value.integer.value[0] = 0;
  1557. break;
  1558. }
  1559. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1560. __func__, usb_rx_cfg.bit_format,
  1561. ucontrol->value.integer.value[0]);
  1562. return 0;
  1563. }
  1564. static int usb_audio_rx_format_put(struct snd_kcontrol *kcontrol,
  1565. struct snd_ctl_elem_value *ucontrol)
  1566. {
  1567. int rc = 0;
  1568. switch (ucontrol->value.integer.value[0]) {
  1569. case 3:
  1570. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1571. break;
  1572. case 2:
  1573. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1574. break;
  1575. case 1:
  1576. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1577. break;
  1578. case 0:
  1579. default:
  1580. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1581. break;
  1582. }
  1583. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1584. __func__, usb_rx_cfg.bit_format,
  1585. ucontrol->value.integer.value[0]);
  1586. return rc;
  1587. }
  1588. static int usb_audio_tx_ch_get(struct snd_kcontrol *kcontrol,
  1589. struct snd_ctl_elem_value *ucontrol)
  1590. {
  1591. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__,
  1592. usb_tx_cfg.channels);
  1593. ucontrol->value.integer.value[0] = usb_tx_cfg.channels - 1;
  1594. return 0;
  1595. }
  1596. static int usb_audio_tx_ch_put(struct snd_kcontrol *kcontrol,
  1597. struct snd_ctl_elem_value *ucontrol)
  1598. {
  1599. usb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1600. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, usb_tx_cfg.channels);
  1601. return 1;
  1602. }
  1603. static int usb_audio_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1604. struct snd_ctl_elem_value *ucontrol)
  1605. {
  1606. int sample_rate_val;
  1607. switch (usb_tx_cfg.sample_rate) {
  1608. case SAMPLING_RATE_384KHZ:
  1609. sample_rate_val = 12;
  1610. break;
  1611. case SAMPLING_RATE_352P8KHZ:
  1612. sample_rate_val = 11;
  1613. break;
  1614. case SAMPLING_RATE_192KHZ:
  1615. sample_rate_val = 10;
  1616. break;
  1617. case SAMPLING_RATE_176P4KHZ:
  1618. sample_rate_val = 9;
  1619. break;
  1620. case SAMPLING_RATE_96KHZ:
  1621. sample_rate_val = 8;
  1622. break;
  1623. case SAMPLING_RATE_88P2KHZ:
  1624. sample_rate_val = 7;
  1625. break;
  1626. case SAMPLING_RATE_48KHZ:
  1627. sample_rate_val = 6;
  1628. break;
  1629. case SAMPLING_RATE_44P1KHZ:
  1630. sample_rate_val = 5;
  1631. break;
  1632. case SAMPLING_RATE_32KHZ:
  1633. sample_rate_val = 4;
  1634. break;
  1635. case SAMPLING_RATE_22P05KHZ:
  1636. sample_rate_val = 3;
  1637. break;
  1638. case SAMPLING_RATE_16KHZ:
  1639. sample_rate_val = 2;
  1640. break;
  1641. case SAMPLING_RATE_11P025KHZ:
  1642. sample_rate_val = 1;
  1643. break;
  1644. case SAMPLING_RATE_8KHZ:
  1645. sample_rate_val = 0;
  1646. break;
  1647. default:
  1648. sample_rate_val = 6;
  1649. break;
  1650. }
  1651. ucontrol->value.integer.value[0] = sample_rate_val;
  1652. pr_debug("%s: usb_audio_tx_sample_rate = %d\n", __func__,
  1653. usb_tx_cfg.sample_rate);
  1654. return 0;
  1655. }
  1656. static int usb_audio_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1657. struct snd_ctl_elem_value *ucontrol)
  1658. {
  1659. switch (ucontrol->value.integer.value[0]) {
  1660. case 12:
  1661. usb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1662. break;
  1663. case 11:
  1664. usb_tx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  1665. break;
  1666. case 10:
  1667. usb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1668. break;
  1669. case 9:
  1670. usb_tx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  1671. break;
  1672. case 8:
  1673. usb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1674. break;
  1675. case 7:
  1676. usb_tx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  1677. break;
  1678. case 6:
  1679. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1680. break;
  1681. case 5:
  1682. usb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1683. break;
  1684. case 4:
  1685. usb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1686. break;
  1687. case 3:
  1688. usb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1689. break;
  1690. case 2:
  1691. usb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1692. break;
  1693. case 1:
  1694. usb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1695. break;
  1696. case 0:
  1697. usb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1698. break;
  1699. default:
  1700. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1701. break;
  1702. }
  1703. pr_debug("%s: control value = %ld, usb_audio_tx_sample_rate = %d\n",
  1704. __func__, ucontrol->value.integer.value[0],
  1705. usb_tx_cfg.sample_rate);
  1706. return 0;
  1707. }
  1708. static int usb_audio_tx_format_get(struct snd_kcontrol *kcontrol,
  1709. struct snd_ctl_elem_value *ucontrol)
  1710. {
  1711. switch (usb_tx_cfg.bit_format) {
  1712. case SNDRV_PCM_FORMAT_S32_LE:
  1713. ucontrol->value.integer.value[0] = 3;
  1714. break;
  1715. case SNDRV_PCM_FORMAT_S24_3LE:
  1716. ucontrol->value.integer.value[0] = 2;
  1717. break;
  1718. case SNDRV_PCM_FORMAT_S24_LE:
  1719. ucontrol->value.integer.value[0] = 1;
  1720. break;
  1721. case SNDRV_PCM_FORMAT_S16_LE:
  1722. default:
  1723. ucontrol->value.integer.value[0] = 0;
  1724. break;
  1725. }
  1726. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1727. __func__, usb_tx_cfg.bit_format,
  1728. ucontrol->value.integer.value[0]);
  1729. return 0;
  1730. }
  1731. static int usb_audio_tx_format_put(struct snd_kcontrol *kcontrol,
  1732. struct snd_ctl_elem_value *ucontrol)
  1733. {
  1734. int rc = 0;
  1735. switch (ucontrol->value.integer.value[0]) {
  1736. case 3:
  1737. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1738. break;
  1739. case 2:
  1740. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1741. break;
  1742. case 1:
  1743. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1744. break;
  1745. case 0:
  1746. default:
  1747. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1748. break;
  1749. }
  1750. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1751. __func__, usb_tx_cfg.bit_format,
  1752. ucontrol->value.integer.value[0]);
  1753. return rc;
  1754. }
  1755. static int proxy_rx_ch_get(struct snd_kcontrol *kcontrol,
  1756. struct snd_ctl_elem_value *ucontrol)
  1757. {
  1758. pr_debug("%s: proxy_rx channels = %d\n",
  1759. __func__, proxy_rx_cfg.channels);
  1760. ucontrol->value.integer.value[0] = proxy_rx_cfg.channels - 2;
  1761. return 0;
  1762. }
  1763. static int proxy_rx_ch_put(struct snd_kcontrol *kcontrol,
  1764. struct snd_ctl_elem_value *ucontrol)
  1765. {
  1766. proxy_rx_cfg.channels = ucontrol->value.integer.value[0] + 2;
  1767. pr_debug("%s: proxy_rx channels = %d\n",
  1768. __func__, proxy_rx_cfg.channels);
  1769. return 1;
  1770. }
  1771. static int tdm_get_sample_rate(int value)
  1772. {
  1773. int sample_rate = 0;
  1774. switch (value) {
  1775. case 0:
  1776. sample_rate = SAMPLING_RATE_8KHZ;
  1777. break;
  1778. case 1:
  1779. sample_rate = SAMPLING_RATE_16KHZ;
  1780. break;
  1781. case 2:
  1782. sample_rate = SAMPLING_RATE_32KHZ;
  1783. break;
  1784. case 3:
  1785. sample_rate = SAMPLING_RATE_48KHZ;
  1786. break;
  1787. case 4:
  1788. sample_rate = SAMPLING_RATE_176P4KHZ;
  1789. break;
  1790. case 5:
  1791. sample_rate = SAMPLING_RATE_352P8KHZ;
  1792. break;
  1793. default:
  1794. sample_rate = SAMPLING_RATE_48KHZ;
  1795. break;
  1796. }
  1797. return sample_rate;
  1798. }
  1799. static int aux_pcm_get_sample_rate(int value)
  1800. {
  1801. int sample_rate;
  1802. switch (value) {
  1803. case 1:
  1804. sample_rate = SAMPLING_RATE_16KHZ;
  1805. break;
  1806. case 0:
  1807. default:
  1808. sample_rate = SAMPLING_RATE_8KHZ;
  1809. break;
  1810. }
  1811. return sample_rate;
  1812. }
  1813. static int tdm_get_sample_rate_val(int sample_rate)
  1814. {
  1815. int sample_rate_val = 0;
  1816. switch (sample_rate) {
  1817. case SAMPLING_RATE_8KHZ:
  1818. sample_rate_val = 0;
  1819. break;
  1820. case SAMPLING_RATE_16KHZ:
  1821. sample_rate_val = 1;
  1822. break;
  1823. case SAMPLING_RATE_32KHZ:
  1824. sample_rate_val = 2;
  1825. break;
  1826. case SAMPLING_RATE_48KHZ:
  1827. sample_rate_val = 3;
  1828. break;
  1829. case SAMPLING_RATE_176P4KHZ:
  1830. sample_rate_val = 4;
  1831. break;
  1832. case SAMPLING_RATE_352P8KHZ:
  1833. sample_rate_val = 5;
  1834. break;
  1835. default:
  1836. sample_rate_val = 3;
  1837. break;
  1838. }
  1839. return sample_rate_val;
  1840. }
  1841. static int aux_pcm_get_sample_rate_val(int sample_rate)
  1842. {
  1843. int sample_rate_val;
  1844. switch (sample_rate) {
  1845. case SAMPLING_RATE_16KHZ:
  1846. sample_rate_val = 1;
  1847. break;
  1848. case SAMPLING_RATE_8KHZ:
  1849. default:
  1850. sample_rate_val = 0;
  1851. break;
  1852. }
  1853. return sample_rate_val;
  1854. }
  1855. static int tdm_get_port_idx(struct snd_kcontrol *kcontrol,
  1856. struct tdm_port *port)
  1857. {
  1858. if (port) {
  1859. if (strnstr(kcontrol->id.name, "PRI",
  1860. sizeof(kcontrol->id.name))) {
  1861. port->mode = TDM_PRI;
  1862. } else if (strnstr(kcontrol->id.name, "SEC",
  1863. sizeof(kcontrol->id.name))) {
  1864. port->mode = TDM_SEC;
  1865. } else if (strnstr(kcontrol->id.name, "TERT",
  1866. sizeof(kcontrol->id.name))) {
  1867. port->mode = TDM_TERT;
  1868. } else if (strnstr(kcontrol->id.name, "QUAT",
  1869. sizeof(kcontrol->id.name))) {
  1870. port->mode = TDM_QUAT;
  1871. } else if (strnstr(kcontrol->id.name, "QUIN",
  1872. sizeof(kcontrol->id.name))) {
  1873. port->mode = TDM_QUIN;
  1874. } else {
  1875. pr_err("%s: unsupported mode in: %s",
  1876. __func__, kcontrol->id.name);
  1877. return -EINVAL;
  1878. }
  1879. if (strnstr(kcontrol->id.name, "RX_0",
  1880. sizeof(kcontrol->id.name)) ||
  1881. strnstr(kcontrol->id.name, "TX_0",
  1882. sizeof(kcontrol->id.name))) {
  1883. port->channel = TDM_0;
  1884. } else if (strnstr(kcontrol->id.name, "RX_1",
  1885. sizeof(kcontrol->id.name)) ||
  1886. strnstr(kcontrol->id.name, "TX_1",
  1887. sizeof(kcontrol->id.name))) {
  1888. port->channel = TDM_1;
  1889. } else if (strnstr(kcontrol->id.name, "RX_2",
  1890. sizeof(kcontrol->id.name)) ||
  1891. strnstr(kcontrol->id.name, "TX_2",
  1892. sizeof(kcontrol->id.name))) {
  1893. port->channel = TDM_2;
  1894. } else if (strnstr(kcontrol->id.name, "RX_3",
  1895. sizeof(kcontrol->id.name)) ||
  1896. strnstr(kcontrol->id.name, "TX_3",
  1897. sizeof(kcontrol->id.name))) {
  1898. port->channel = TDM_3;
  1899. } else if (strnstr(kcontrol->id.name, "RX_4",
  1900. sizeof(kcontrol->id.name)) ||
  1901. strnstr(kcontrol->id.name, "TX_4",
  1902. sizeof(kcontrol->id.name))) {
  1903. port->channel = TDM_4;
  1904. } else if (strnstr(kcontrol->id.name, "RX_5",
  1905. sizeof(kcontrol->id.name)) ||
  1906. strnstr(kcontrol->id.name, "TX_5",
  1907. sizeof(kcontrol->id.name))) {
  1908. port->channel = TDM_5;
  1909. } else if (strnstr(kcontrol->id.name, "RX_6",
  1910. sizeof(kcontrol->id.name)) ||
  1911. strnstr(kcontrol->id.name, "TX_6",
  1912. sizeof(kcontrol->id.name))) {
  1913. port->channel = TDM_6;
  1914. } else if (strnstr(kcontrol->id.name, "RX_7",
  1915. sizeof(kcontrol->id.name)) ||
  1916. strnstr(kcontrol->id.name, "TX_7",
  1917. sizeof(kcontrol->id.name))) {
  1918. port->channel = TDM_7;
  1919. } else {
  1920. pr_err("%s: unsupported channel in: %s",
  1921. __func__, kcontrol->id.name);
  1922. return -EINVAL;
  1923. }
  1924. } else
  1925. return -EINVAL;
  1926. return 0;
  1927. }
  1928. static int tdm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1929. struct snd_ctl_elem_value *ucontrol)
  1930. {
  1931. struct tdm_port port;
  1932. int ret = tdm_get_port_idx(kcontrol, &port);
  1933. if (ret) {
  1934. pr_err("%s: unsupported control: %s",
  1935. __func__, kcontrol->id.name);
  1936. } else {
  1937. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1938. tdm_rx_cfg[port.mode][port.channel].sample_rate);
  1939. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1940. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1941. ucontrol->value.enumerated.item[0]);
  1942. }
  1943. return ret;
  1944. }
  1945. static int tdm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1946. struct snd_ctl_elem_value *ucontrol)
  1947. {
  1948. struct tdm_port port;
  1949. int ret = tdm_get_port_idx(kcontrol, &port);
  1950. if (ret) {
  1951. pr_err("%s: unsupported control: %s",
  1952. __func__, kcontrol->id.name);
  1953. } else {
  1954. tdm_rx_cfg[port.mode][port.channel].sample_rate =
  1955. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1956. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1957. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1958. ucontrol->value.enumerated.item[0]);
  1959. }
  1960. return ret;
  1961. }
  1962. static int tdm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1963. struct snd_ctl_elem_value *ucontrol)
  1964. {
  1965. struct tdm_port port;
  1966. int ret = tdm_get_port_idx(kcontrol, &port);
  1967. if (ret) {
  1968. pr_err("%s: unsupported control: %s",
  1969. __func__, kcontrol->id.name);
  1970. } else {
  1971. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1972. tdm_tx_cfg[port.mode][port.channel].sample_rate);
  1973. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1974. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1975. ucontrol->value.enumerated.item[0]);
  1976. }
  1977. return ret;
  1978. }
  1979. static int tdm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1980. struct snd_ctl_elem_value *ucontrol)
  1981. {
  1982. struct tdm_port port;
  1983. int ret = tdm_get_port_idx(kcontrol, &port);
  1984. if (ret) {
  1985. pr_err("%s: unsupported control: %s",
  1986. __func__, kcontrol->id.name);
  1987. } else {
  1988. tdm_tx_cfg[port.mode][port.channel].sample_rate =
  1989. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1990. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1991. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1992. ucontrol->value.enumerated.item[0]);
  1993. }
  1994. return ret;
  1995. }
  1996. static int tdm_get_format(int value)
  1997. {
  1998. int format = 0;
  1999. switch (value) {
  2000. case 0:
  2001. format = SNDRV_PCM_FORMAT_S16_LE;
  2002. break;
  2003. case 1:
  2004. format = SNDRV_PCM_FORMAT_S24_LE;
  2005. break;
  2006. case 2:
  2007. format = SNDRV_PCM_FORMAT_S32_LE;
  2008. break;
  2009. default:
  2010. format = SNDRV_PCM_FORMAT_S16_LE;
  2011. break;
  2012. }
  2013. return format;
  2014. }
  2015. static int tdm_get_format_val(int format)
  2016. {
  2017. int value = 0;
  2018. switch (format) {
  2019. case SNDRV_PCM_FORMAT_S16_LE:
  2020. value = 0;
  2021. break;
  2022. case SNDRV_PCM_FORMAT_S24_LE:
  2023. value = 1;
  2024. break;
  2025. case SNDRV_PCM_FORMAT_S32_LE:
  2026. value = 2;
  2027. break;
  2028. default:
  2029. value = 0;
  2030. break;
  2031. }
  2032. return value;
  2033. }
  2034. static int tdm_rx_format_get(struct snd_kcontrol *kcontrol,
  2035. struct snd_ctl_elem_value *ucontrol)
  2036. {
  2037. struct tdm_port port;
  2038. int ret = tdm_get_port_idx(kcontrol, &port);
  2039. if (ret) {
  2040. pr_err("%s: unsupported control: %s",
  2041. __func__, kcontrol->id.name);
  2042. } else {
  2043. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  2044. tdm_rx_cfg[port.mode][port.channel].bit_format);
  2045. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  2046. tdm_rx_cfg[port.mode][port.channel].bit_format,
  2047. ucontrol->value.enumerated.item[0]);
  2048. }
  2049. return ret;
  2050. }
  2051. static int tdm_rx_format_put(struct snd_kcontrol *kcontrol,
  2052. struct snd_ctl_elem_value *ucontrol)
  2053. {
  2054. struct tdm_port port;
  2055. int ret = tdm_get_port_idx(kcontrol, &port);
  2056. if (ret) {
  2057. pr_err("%s: unsupported control: %s",
  2058. __func__, kcontrol->id.name);
  2059. } else {
  2060. tdm_rx_cfg[port.mode][port.channel].bit_format =
  2061. tdm_get_format(ucontrol->value.enumerated.item[0]);
  2062. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  2063. tdm_rx_cfg[port.mode][port.channel].bit_format,
  2064. ucontrol->value.enumerated.item[0]);
  2065. }
  2066. return ret;
  2067. }
  2068. static int tdm_tx_format_get(struct snd_kcontrol *kcontrol,
  2069. struct snd_ctl_elem_value *ucontrol)
  2070. {
  2071. struct tdm_port port;
  2072. int ret = tdm_get_port_idx(kcontrol, &port);
  2073. if (ret) {
  2074. pr_err("%s: unsupported control: %s",
  2075. __func__, kcontrol->id.name);
  2076. } else {
  2077. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  2078. tdm_tx_cfg[port.mode][port.channel].bit_format);
  2079. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  2080. tdm_tx_cfg[port.mode][port.channel].bit_format,
  2081. ucontrol->value.enumerated.item[0]);
  2082. }
  2083. return ret;
  2084. }
  2085. static int tdm_tx_format_put(struct snd_kcontrol *kcontrol,
  2086. struct snd_ctl_elem_value *ucontrol)
  2087. {
  2088. struct tdm_port port;
  2089. int ret = tdm_get_port_idx(kcontrol, &port);
  2090. if (ret) {
  2091. pr_err("%s: unsupported control: %s",
  2092. __func__, kcontrol->id.name);
  2093. } else {
  2094. tdm_tx_cfg[port.mode][port.channel].bit_format =
  2095. tdm_get_format(ucontrol->value.enumerated.item[0]);
  2096. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  2097. tdm_tx_cfg[port.mode][port.channel].bit_format,
  2098. ucontrol->value.enumerated.item[0]);
  2099. }
  2100. return ret;
  2101. }
  2102. static int tdm_rx_ch_get(struct snd_kcontrol *kcontrol,
  2103. struct snd_ctl_elem_value *ucontrol)
  2104. {
  2105. struct tdm_port port;
  2106. int ret = tdm_get_port_idx(kcontrol, &port);
  2107. if (ret) {
  2108. pr_err("%s: unsupported control: %s",
  2109. __func__, kcontrol->id.name);
  2110. } else {
  2111. ucontrol->value.enumerated.item[0] =
  2112. tdm_rx_cfg[port.mode][port.channel].channels - 1;
  2113. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  2114. tdm_rx_cfg[port.mode][port.channel].channels - 1,
  2115. ucontrol->value.enumerated.item[0]);
  2116. }
  2117. return ret;
  2118. }
  2119. static int tdm_rx_ch_put(struct snd_kcontrol *kcontrol,
  2120. struct snd_ctl_elem_value *ucontrol)
  2121. {
  2122. struct tdm_port port;
  2123. int ret = tdm_get_port_idx(kcontrol, &port);
  2124. if (ret) {
  2125. pr_err("%s: unsupported control: %s",
  2126. __func__, kcontrol->id.name);
  2127. } else {
  2128. tdm_rx_cfg[port.mode][port.channel].channels =
  2129. ucontrol->value.enumerated.item[0] + 1;
  2130. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  2131. tdm_rx_cfg[port.mode][port.channel].channels,
  2132. ucontrol->value.enumerated.item[0] + 1);
  2133. }
  2134. return ret;
  2135. }
  2136. static int tdm_tx_ch_get(struct snd_kcontrol *kcontrol,
  2137. struct snd_ctl_elem_value *ucontrol)
  2138. {
  2139. struct tdm_port port;
  2140. int ret = tdm_get_port_idx(kcontrol, &port);
  2141. if (ret) {
  2142. pr_err("%s: unsupported control: %s",
  2143. __func__, kcontrol->id.name);
  2144. } else {
  2145. ucontrol->value.enumerated.item[0] =
  2146. tdm_tx_cfg[port.mode][port.channel].channels - 1;
  2147. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  2148. tdm_tx_cfg[port.mode][port.channel].channels - 1,
  2149. ucontrol->value.enumerated.item[0]);
  2150. }
  2151. return ret;
  2152. }
  2153. static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol,
  2154. struct snd_ctl_elem_value *ucontrol)
  2155. {
  2156. struct tdm_port port;
  2157. int ret = tdm_get_port_idx(kcontrol, &port);
  2158. if (ret) {
  2159. pr_err("%s: unsupported control: %s",
  2160. __func__, kcontrol->id.name);
  2161. } else {
  2162. tdm_tx_cfg[port.mode][port.channel].channels =
  2163. ucontrol->value.enumerated.item[0] + 1;
  2164. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  2165. tdm_tx_cfg[port.mode][port.channel].channels,
  2166. ucontrol->value.enumerated.item[0] + 1);
  2167. }
  2168. return ret;
  2169. }
  2170. static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol)
  2171. {
  2172. int idx;
  2173. if (strnstr(kcontrol->id.name, "PRIM_AUX_PCM",
  2174. sizeof("PRIM_AUX_PCM")))
  2175. idx = PRIM_AUX_PCM;
  2176. else if (strnstr(kcontrol->id.name, "SEC_AUX_PCM",
  2177. sizeof("SEC_AUX_PCM")))
  2178. idx = SEC_AUX_PCM;
  2179. else if (strnstr(kcontrol->id.name, "TERT_AUX_PCM",
  2180. sizeof("TERT_AUX_PCM")))
  2181. idx = TERT_AUX_PCM;
  2182. else if (strnstr(kcontrol->id.name, "QUAT_AUX_PCM",
  2183. sizeof("QUAT_AUX_PCM")))
  2184. idx = QUAT_AUX_PCM;
  2185. else if (strnstr(kcontrol->id.name, "QUIN_AUX_PCM",
  2186. sizeof("QUIN_AUX_PCM")))
  2187. idx = QUIN_AUX_PCM;
  2188. else if (strnstr(kcontrol->id.name, "SEN_AUX_PCM",
  2189. sizeof("SENN_AUX_PCM")))
  2190. idx = SEN_AUX_PCM;
  2191. else {
  2192. pr_err("%s: unsupported port: %s",
  2193. __func__, kcontrol->id.name);
  2194. idx = -EINVAL;
  2195. }
  2196. return idx;
  2197. }
  2198. static int aux_pcm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2199. struct snd_ctl_elem_value *ucontrol)
  2200. {
  2201. int idx = aux_pcm_get_port_idx(kcontrol);
  2202. if (idx < 0)
  2203. return idx;
  2204. aux_pcm_rx_cfg[idx].sample_rate =
  2205. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2206. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2207. idx, aux_pcm_rx_cfg[idx].sample_rate,
  2208. ucontrol->value.enumerated.item[0]);
  2209. return 0;
  2210. }
  2211. static int aux_pcm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2212. struct snd_ctl_elem_value *ucontrol)
  2213. {
  2214. int idx = aux_pcm_get_port_idx(kcontrol);
  2215. if (idx < 0)
  2216. return idx;
  2217. ucontrol->value.enumerated.item[0] =
  2218. aux_pcm_get_sample_rate_val(aux_pcm_rx_cfg[idx].sample_rate);
  2219. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2220. idx, aux_pcm_rx_cfg[idx].sample_rate,
  2221. ucontrol->value.enumerated.item[0]);
  2222. return 0;
  2223. }
  2224. static int aux_pcm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2225. struct snd_ctl_elem_value *ucontrol)
  2226. {
  2227. int idx = aux_pcm_get_port_idx(kcontrol);
  2228. if (idx < 0)
  2229. return idx;
  2230. aux_pcm_tx_cfg[idx].sample_rate =
  2231. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2232. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2233. idx, aux_pcm_tx_cfg[idx].sample_rate,
  2234. ucontrol->value.enumerated.item[0]);
  2235. return 0;
  2236. }
  2237. static int aux_pcm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2238. struct snd_ctl_elem_value *ucontrol)
  2239. {
  2240. int idx = aux_pcm_get_port_idx(kcontrol);
  2241. if (idx < 0)
  2242. return idx;
  2243. ucontrol->value.enumerated.item[0] =
  2244. aux_pcm_get_sample_rate_val(aux_pcm_tx_cfg[idx].sample_rate);
  2245. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2246. idx, aux_pcm_tx_cfg[idx].sample_rate,
  2247. ucontrol->value.enumerated.item[0]);
  2248. return 0;
  2249. }
  2250. static int mi2s_get_port_idx(struct snd_kcontrol *kcontrol)
  2251. {
  2252. int idx;
  2253. if (strnstr(kcontrol->id.name, "PRIM_MI2S_RX",
  2254. sizeof("PRIM_MI2S_RX")))
  2255. idx = PRIM_MI2S;
  2256. else if (strnstr(kcontrol->id.name, "SEC_MI2S_RX",
  2257. sizeof("SEC_MI2S_RX")))
  2258. idx = SEC_MI2S;
  2259. else if (strnstr(kcontrol->id.name, "TERT_MI2S_RX",
  2260. sizeof("TERT_MI2S_RX")))
  2261. idx = TERT_MI2S;
  2262. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_RX",
  2263. sizeof("QUAT_MI2S_RX")))
  2264. idx = QUAT_MI2S;
  2265. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_RX",
  2266. sizeof("QUIN_MI2S_RX")))
  2267. idx = QUIN_MI2S;
  2268. else if (strnstr(kcontrol->id.name, "SEN_MI2S_RX",
  2269. sizeof("SEN_MI2S_RX")))
  2270. idx = SEN_MI2S;
  2271. else if (strnstr(kcontrol->id.name, "PRIM_MI2S_TX",
  2272. sizeof("PRIM_MI2S_TX")))
  2273. idx = PRIM_MI2S;
  2274. else if (strnstr(kcontrol->id.name, "SEC_MI2S_TX",
  2275. sizeof("SEC_MI2S_TX")))
  2276. idx = SEC_MI2S;
  2277. else if (strnstr(kcontrol->id.name, "TERT_MI2S_TX",
  2278. sizeof("TERT_MI2S_TX")))
  2279. idx = TERT_MI2S;
  2280. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_TX",
  2281. sizeof("QUAT_MI2S_TX")))
  2282. idx = QUAT_MI2S;
  2283. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_TX",
  2284. sizeof("QUIN_MI2S_TX")))
  2285. idx = QUIN_MI2S;
  2286. else if (strnstr(kcontrol->id.name, "SEN_MI2S_TX",
  2287. sizeof("SEN_MI2S_TX")))
  2288. idx = SEN_MI2S;
  2289. else {
  2290. pr_err("%s: unsupported channel: %s",
  2291. __func__, kcontrol->id.name);
  2292. idx = -EINVAL;
  2293. }
  2294. return idx;
  2295. }
  2296. static int mi2s_get_sample_rate_val(int sample_rate)
  2297. {
  2298. int sample_rate_val;
  2299. switch (sample_rate) {
  2300. case SAMPLING_RATE_8KHZ:
  2301. sample_rate_val = 0;
  2302. break;
  2303. case SAMPLING_RATE_11P025KHZ:
  2304. sample_rate_val = 1;
  2305. break;
  2306. case SAMPLING_RATE_16KHZ:
  2307. sample_rate_val = 2;
  2308. break;
  2309. case SAMPLING_RATE_22P05KHZ:
  2310. sample_rate_val = 3;
  2311. break;
  2312. case SAMPLING_RATE_32KHZ:
  2313. sample_rate_val = 4;
  2314. break;
  2315. case SAMPLING_RATE_44P1KHZ:
  2316. sample_rate_val = 5;
  2317. break;
  2318. case SAMPLING_RATE_48KHZ:
  2319. sample_rate_val = 6;
  2320. break;
  2321. case SAMPLING_RATE_96KHZ:
  2322. sample_rate_val = 7;
  2323. break;
  2324. case SAMPLING_RATE_192KHZ:
  2325. sample_rate_val = 8;
  2326. break;
  2327. case SAMPLING_RATE_384KHZ:
  2328. sample_rate_val = 9;
  2329. break;
  2330. default:
  2331. sample_rate_val = 6;
  2332. break;
  2333. }
  2334. return sample_rate_val;
  2335. }
  2336. static int mi2s_get_sample_rate(int value)
  2337. {
  2338. int sample_rate;
  2339. switch (value) {
  2340. case 0:
  2341. sample_rate = SAMPLING_RATE_8KHZ;
  2342. break;
  2343. case 1:
  2344. sample_rate = SAMPLING_RATE_11P025KHZ;
  2345. break;
  2346. case 2:
  2347. sample_rate = SAMPLING_RATE_16KHZ;
  2348. break;
  2349. case 3:
  2350. sample_rate = SAMPLING_RATE_22P05KHZ;
  2351. break;
  2352. case 4:
  2353. sample_rate = SAMPLING_RATE_32KHZ;
  2354. break;
  2355. case 5:
  2356. sample_rate = SAMPLING_RATE_44P1KHZ;
  2357. break;
  2358. case 6:
  2359. sample_rate = SAMPLING_RATE_48KHZ;
  2360. break;
  2361. case 7:
  2362. sample_rate = SAMPLING_RATE_96KHZ;
  2363. break;
  2364. case 8:
  2365. sample_rate = SAMPLING_RATE_192KHZ;
  2366. break;
  2367. case 9:
  2368. sample_rate = SAMPLING_RATE_384KHZ;
  2369. break;
  2370. default:
  2371. sample_rate = SAMPLING_RATE_48KHZ;
  2372. break;
  2373. }
  2374. return sample_rate;
  2375. }
  2376. static int mi2s_auxpcm_get_format(int value)
  2377. {
  2378. int format;
  2379. switch (value) {
  2380. case 0:
  2381. format = SNDRV_PCM_FORMAT_S16_LE;
  2382. break;
  2383. case 1:
  2384. format = SNDRV_PCM_FORMAT_S24_LE;
  2385. break;
  2386. case 2:
  2387. format = SNDRV_PCM_FORMAT_S24_3LE;
  2388. break;
  2389. case 3:
  2390. format = SNDRV_PCM_FORMAT_S32_LE;
  2391. break;
  2392. default:
  2393. format = SNDRV_PCM_FORMAT_S16_LE;
  2394. break;
  2395. }
  2396. return format;
  2397. }
  2398. static int mi2s_auxpcm_get_format_value(int format)
  2399. {
  2400. int value;
  2401. switch (format) {
  2402. case SNDRV_PCM_FORMAT_S16_LE:
  2403. value = 0;
  2404. break;
  2405. case SNDRV_PCM_FORMAT_S24_LE:
  2406. value = 1;
  2407. break;
  2408. case SNDRV_PCM_FORMAT_S24_3LE:
  2409. value = 2;
  2410. break;
  2411. case SNDRV_PCM_FORMAT_S32_LE:
  2412. value = 3;
  2413. break;
  2414. default:
  2415. value = 0;
  2416. break;
  2417. }
  2418. return value;
  2419. }
  2420. static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2421. struct snd_ctl_elem_value *ucontrol)
  2422. {
  2423. int idx = mi2s_get_port_idx(kcontrol);
  2424. if (idx < 0)
  2425. return idx;
  2426. mi2s_rx_cfg[idx].sample_rate =
  2427. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2428. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2429. idx, mi2s_rx_cfg[idx].sample_rate,
  2430. ucontrol->value.enumerated.item[0]);
  2431. return 0;
  2432. }
  2433. static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2434. struct snd_ctl_elem_value *ucontrol)
  2435. {
  2436. int idx = mi2s_get_port_idx(kcontrol);
  2437. if (idx < 0)
  2438. return idx;
  2439. ucontrol->value.enumerated.item[0] =
  2440. mi2s_get_sample_rate_val(mi2s_rx_cfg[idx].sample_rate);
  2441. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2442. idx, mi2s_rx_cfg[idx].sample_rate,
  2443. ucontrol->value.enumerated.item[0]);
  2444. return 0;
  2445. }
  2446. static int mi2s_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2447. struct snd_ctl_elem_value *ucontrol)
  2448. {
  2449. int idx = mi2s_get_port_idx(kcontrol);
  2450. if (idx < 0)
  2451. return idx;
  2452. mi2s_tx_cfg[idx].sample_rate =
  2453. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2454. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2455. idx, mi2s_tx_cfg[idx].sample_rate,
  2456. ucontrol->value.enumerated.item[0]);
  2457. return 0;
  2458. }
  2459. static int mi2s_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2460. struct snd_ctl_elem_value *ucontrol)
  2461. {
  2462. int idx = mi2s_get_port_idx(kcontrol);
  2463. if (idx < 0)
  2464. return idx;
  2465. ucontrol->value.enumerated.item[0] =
  2466. mi2s_get_sample_rate_val(mi2s_tx_cfg[idx].sample_rate);
  2467. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2468. idx, mi2s_tx_cfg[idx].sample_rate,
  2469. ucontrol->value.enumerated.item[0]);
  2470. return 0;
  2471. }
  2472. static int msm_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
  2473. struct snd_ctl_elem_value *ucontrol)
  2474. {
  2475. int idx = mi2s_get_port_idx(kcontrol);
  2476. if (idx < 0)
  2477. return idx;
  2478. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2479. idx, mi2s_rx_cfg[idx].channels);
  2480. ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].channels - 1;
  2481. return 0;
  2482. }
  2483. static int msm_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
  2484. struct snd_ctl_elem_value *ucontrol)
  2485. {
  2486. int idx = mi2s_get_port_idx(kcontrol);
  2487. if (idx < 0)
  2488. return idx;
  2489. mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2490. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2491. idx, mi2s_rx_cfg[idx].channels);
  2492. return 1;
  2493. }
  2494. static int msm_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol,
  2495. struct snd_ctl_elem_value *ucontrol)
  2496. {
  2497. int idx = mi2s_get_port_idx(kcontrol);
  2498. if (idx < 0)
  2499. return idx;
  2500. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2501. idx, mi2s_tx_cfg[idx].channels);
  2502. ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].channels - 1;
  2503. return 0;
  2504. }
  2505. static int msm_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol,
  2506. struct snd_ctl_elem_value *ucontrol)
  2507. {
  2508. int idx = mi2s_get_port_idx(kcontrol);
  2509. if (idx < 0)
  2510. return idx;
  2511. mi2s_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2512. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2513. idx, mi2s_tx_cfg[idx].channels);
  2514. return 1;
  2515. }
  2516. static int msm_mi2s_rx_format_get(struct snd_kcontrol *kcontrol,
  2517. struct snd_ctl_elem_value *ucontrol)
  2518. {
  2519. int idx = mi2s_get_port_idx(kcontrol);
  2520. if (idx < 0)
  2521. return idx;
  2522. ucontrol->value.enumerated.item[0] =
  2523. mi2s_auxpcm_get_format_value(mi2s_rx_cfg[idx].bit_format);
  2524. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2525. idx, mi2s_rx_cfg[idx].bit_format,
  2526. ucontrol->value.enumerated.item[0]);
  2527. return 0;
  2528. }
  2529. static int msm_mi2s_rx_format_put(struct snd_kcontrol *kcontrol,
  2530. struct snd_ctl_elem_value *ucontrol)
  2531. {
  2532. struct msm_asoc_mach_data *pdata = NULL;
  2533. struct snd_soc_component *component = NULL;
  2534. struct snd_soc_card *card = NULL;
  2535. int idx = mi2s_get_port_idx(kcontrol);
  2536. component = snd_soc_kcontrol_component(kcontrol);
  2537. card = kcontrol->private_data;
  2538. pdata = snd_soc_card_get_drvdata(card);
  2539. if (idx < 0)
  2540. return idx;
  2541. /* check for PRIM_MI2S and CSRAx config to allow 24bit BE config only */
  2542. if ((PRIM_MI2S == idx) && (true==pdata->codec_is_csra))
  2543. {
  2544. mi2s_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  2545. pr_debug("%s: Keeping default format idx[%d]_rx_format = %d, item = %d\n",
  2546. __func__, idx, mi2s_rx_cfg[idx].bit_format,
  2547. ucontrol->value.enumerated.item[0]);
  2548. } else {
  2549. mi2s_rx_cfg[idx].bit_format =
  2550. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2551. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2552. idx, mi2s_rx_cfg[idx].bit_format,
  2553. ucontrol->value.enumerated.item[0]);
  2554. }
  2555. return 0;
  2556. }
  2557. static int msm_mi2s_tx_format_get(struct snd_kcontrol *kcontrol,
  2558. struct snd_ctl_elem_value *ucontrol)
  2559. {
  2560. int idx = mi2s_get_port_idx(kcontrol);
  2561. if (idx < 0)
  2562. return idx;
  2563. ucontrol->value.enumerated.item[0] =
  2564. mi2s_auxpcm_get_format_value(mi2s_tx_cfg[idx].bit_format);
  2565. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2566. idx, mi2s_tx_cfg[idx].bit_format,
  2567. ucontrol->value.enumerated.item[0]);
  2568. return 0;
  2569. }
  2570. static int msm_mi2s_tx_format_put(struct snd_kcontrol *kcontrol,
  2571. struct snd_ctl_elem_value *ucontrol)
  2572. {
  2573. int idx = mi2s_get_port_idx(kcontrol);
  2574. if (idx < 0)
  2575. return idx;
  2576. mi2s_tx_cfg[idx].bit_format =
  2577. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2578. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2579. idx, mi2s_tx_cfg[idx].bit_format,
  2580. ucontrol->value.enumerated.item[0]);
  2581. return 0;
  2582. }
  2583. static int msm_aux_pcm_rx_format_get(struct snd_kcontrol *kcontrol,
  2584. struct snd_ctl_elem_value *ucontrol)
  2585. {
  2586. int idx = aux_pcm_get_port_idx(kcontrol);
  2587. if (idx < 0)
  2588. return idx;
  2589. ucontrol->value.enumerated.item[0] =
  2590. mi2s_auxpcm_get_format_value(aux_pcm_rx_cfg[idx].bit_format);
  2591. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2592. idx, aux_pcm_rx_cfg[idx].bit_format,
  2593. ucontrol->value.enumerated.item[0]);
  2594. return 0;
  2595. }
  2596. static int msm_aux_pcm_rx_format_put(struct snd_kcontrol *kcontrol,
  2597. struct snd_ctl_elem_value *ucontrol)
  2598. {
  2599. int idx = aux_pcm_get_port_idx(kcontrol);
  2600. if (idx < 0)
  2601. return idx;
  2602. aux_pcm_rx_cfg[idx].bit_format =
  2603. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2604. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2605. idx, aux_pcm_rx_cfg[idx].bit_format,
  2606. ucontrol->value.enumerated.item[0]);
  2607. return 0;
  2608. }
  2609. static int msm_aux_pcm_tx_format_get(struct snd_kcontrol *kcontrol,
  2610. struct snd_ctl_elem_value *ucontrol)
  2611. {
  2612. int idx = aux_pcm_get_port_idx(kcontrol);
  2613. if (idx < 0)
  2614. return idx;
  2615. ucontrol->value.enumerated.item[0] =
  2616. mi2s_auxpcm_get_format_value(aux_pcm_tx_cfg[idx].bit_format);
  2617. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2618. idx, aux_pcm_tx_cfg[idx].bit_format,
  2619. ucontrol->value.enumerated.item[0]);
  2620. return 0;
  2621. }
  2622. static int msm_aux_pcm_tx_format_put(struct snd_kcontrol *kcontrol,
  2623. struct snd_ctl_elem_value *ucontrol)
  2624. {
  2625. int idx = aux_pcm_get_port_idx(kcontrol);
  2626. if (idx < 0)
  2627. return idx;
  2628. aux_pcm_tx_cfg[idx].bit_format =
  2629. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2630. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2631. idx, aux_pcm_tx_cfg[idx].bit_format,
  2632. ucontrol->value.enumerated.item[0]);
  2633. return 0;
  2634. }
  2635. static int spdif_get_port_idx(struct snd_kcontrol *kcontrol)
  2636. {
  2637. int idx;
  2638. if (strnstr(kcontrol->id.name, "PRIM_SPDIF_RX",
  2639. sizeof("PRIM_SPDIF_RX")))
  2640. idx = PRIM_SPDIF_RX;
  2641. else if (strnstr(kcontrol->id.name, "SEC_SPDIF_RX",
  2642. sizeof("SEC_SPDIF_RX")))
  2643. idx = SEC_SPDIF_RX;
  2644. else if (strnstr(kcontrol->id.name, "PRIM_SPDIF_TX",
  2645. sizeof("PRIM_SPDIF_TX")))
  2646. idx = PRIM_SPDIF_TX;
  2647. else if (strnstr(kcontrol->id.name, "SEC_SPDIF_TX",
  2648. sizeof("SEC_SPDIF_TX")))
  2649. idx = SEC_SPDIF_TX;
  2650. else {
  2651. pr_err("%s: unsupported channel: %s",
  2652. __func__, kcontrol->id.name);
  2653. idx = -EINVAL;
  2654. }
  2655. return idx;
  2656. }
  2657. static int spdif_get_sample_rate_val(int sample_rate)
  2658. {
  2659. int sample_rate_val;
  2660. switch (sample_rate) {
  2661. case SAMPLING_RATE_32KHZ:
  2662. sample_rate_val = 0;
  2663. break;
  2664. case SAMPLING_RATE_44P1KHZ:
  2665. sample_rate_val = 1;
  2666. break;
  2667. case SAMPLING_RATE_48KHZ:
  2668. sample_rate_val = 2;
  2669. break;
  2670. case SAMPLING_RATE_88P2KHZ:
  2671. sample_rate_val = 3;
  2672. break;
  2673. case SAMPLING_RATE_96KHZ:
  2674. sample_rate_val = 4;
  2675. break;
  2676. case SAMPLING_RATE_176P4KHZ:
  2677. sample_rate_val = 5;
  2678. break;
  2679. case SAMPLING_RATE_192KHZ:
  2680. sample_rate_val = 6;
  2681. break;
  2682. default:
  2683. sample_rate_val = 2;
  2684. break;
  2685. }
  2686. return sample_rate_val;
  2687. }
  2688. static int spdif_get_sample_rate(int value)
  2689. {
  2690. int sample_rate;
  2691. switch (value) {
  2692. case 0:
  2693. sample_rate = SAMPLING_RATE_32KHZ;
  2694. break;
  2695. case 1:
  2696. sample_rate = SAMPLING_RATE_44P1KHZ;
  2697. break;
  2698. case 2:
  2699. sample_rate = SAMPLING_RATE_48KHZ;
  2700. break;
  2701. case 3:
  2702. sample_rate = SAMPLING_RATE_88P2KHZ;
  2703. break;
  2704. case 4:
  2705. sample_rate = SAMPLING_RATE_96KHZ;
  2706. break;
  2707. case 5:
  2708. sample_rate = SAMPLING_RATE_176P4KHZ;
  2709. break;
  2710. case 6:
  2711. sample_rate = SAMPLING_RATE_192KHZ;
  2712. break;
  2713. default:
  2714. sample_rate = SAMPLING_RATE_48KHZ;
  2715. break;
  2716. }
  2717. return sample_rate;
  2718. }
  2719. static int spdif_get_format(int value)
  2720. {
  2721. int format;
  2722. switch (value) {
  2723. case 0:
  2724. format = SNDRV_PCM_FORMAT_S16_LE;
  2725. break;
  2726. case 1:
  2727. format = SNDRV_PCM_FORMAT_S24_LE;
  2728. break;
  2729. default:
  2730. format = SNDRV_PCM_FORMAT_S16_LE;
  2731. break;
  2732. }
  2733. return format;
  2734. }
  2735. static int spdif_get_format_value(int format)
  2736. {
  2737. int value;
  2738. switch (format) {
  2739. case SNDRV_PCM_FORMAT_S16_LE:
  2740. value = 0;
  2741. break;
  2742. case SNDRV_PCM_FORMAT_S24_LE:
  2743. value = 1;
  2744. break;
  2745. default:
  2746. value = 0;
  2747. break;
  2748. }
  2749. return value;
  2750. }
  2751. static int msm_spdif_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2752. struct snd_ctl_elem_value *ucontrol)
  2753. {
  2754. int idx = spdif_get_port_idx(kcontrol);
  2755. if (idx < 0)
  2756. return idx;
  2757. spdif_rx_cfg[idx].sample_rate =
  2758. spdif_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2759. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2760. idx, spdif_rx_cfg[idx].sample_rate,
  2761. ucontrol->value.enumerated.item[0]);
  2762. return 0;
  2763. }
  2764. static int msm_spdif_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2765. struct snd_ctl_elem_value *ucontrol)
  2766. {
  2767. int idx = spdif_get_port_idx(kcontrol);
  2768. if (idx < 0)
  2769. return idx;
  2770. ucontrol->value.enumerated.item[0] =
  2771. spdif_get_sample_rate_val(spdif_rx_cfg[idx].sample_rate);
  2772. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2773. idx, spdif_rx_cfg[idx].sample_rate,
  2774. ucontrol->value.enumerated.item[0]);
  2775. return 0;
  2776. }
  2777. static int msm_spdif_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2778. struct snd_ctl_elem_value *ucontrol)
  2779. {
  2780. int idx = spdif_get_port_idx(kcontrol);
  2781. if (idx < 0)
  2782. return idx;
  2783. spdif_tx_cfg[idx].sample_rate =
  2784. spdif_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2785. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2786. idx, spdif_tx_cfg[idx].sample_rate,
  2787. ucontrol->value.enumerated.item[0]);
  2788. return 0;
  2789. }
  2790. static int msm_spdif_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2791. struct snd_ctl_elem_value *ucontrol)
  2792. {
  2793. int idx = spdif_get_port_idx(kcontrol);
  2794. if (idx < 0)
  2795. return idx;
  2796. ucontrol->value.enumerated.item[0] =
  2797. spdif_get_sample_rate_val(spdif_tx_cfg[idx].sample_rate);
  2798. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2799. idx, spdif_tx_cfg[idx].sample_rate,
  2800. ucontrol->value.enumerated.item[0]);
  2801. return 0;
  2802. }
  2803. static int msm_spdif_rx_ch_get(struct snd_kcontrol *kcontrol,
  2804. struct snd_ctl_elem_value *ucontrol)
  2805. {
  2806. int idx = spdif_get_port_idx(kcontrol);
  2807. if (idx < 0)
  2808. return idx;
  2809. pr_debug("%s: msm_spdif_[%d]_rx_ch = %d\n", __func__,
  2810. idx, spdif_rx_cfg[idx].channels);
  2811. ucontrol->value.enumerated.item[0] = spdif_rx_cfg[idx].channels - 1;
  2812. return 0;
  2813. }
  2814. static int msm_spdif_rx_ch_put(struct snd_kcontrol *kcontrol,
  2815. struct snd_ctl_elem_value *ucontrol)
  2816. {
  2817. int idx = spdif_get_port_idx(kcontrol);
  2818. if (idx < 0)
  2819. return idx;
  2820. spdif_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2821. pr_debug("%s: msm_spdif_[%d]_rx_ch = %d\n", __func__,
  2822. idx, spdif_rx_cfg[idx].channels);
  2823. return 1;
  2824. }
  2825. static int msm_spdif_tx_ch_get(struct snd_kcontrol *kcontrol,
  2826. struct snd_ctl_elem_value *ucontrol)
  2827. {
  2828. int idx = spdif_get_port_idx(kcontrol);
  2829. if (idx < 0)
  2830. return idx;
  2831. pr_debug("%s: msm_spdif_[%d]_tx_ch = %d\n", __func__,
  2832. idx, spdif_tx_cfg[idx].channels);
  2833. ucontrol->value.enumerated.item[0] = spdif_tx_cfg[idx].channels - 1;
  2834. return 0;
  2835. }
  2836. static int msm_spdif_tx_ch_put(struct snd_kcontrol *kcontrol,
  2837. struct snd_ctl_elem_value *ucontrol)
  2838. {
  2839. int idx = spdif_get_port_idx(kcontrol);
  2840. if (idx < 0)
  2841. return idx;
  2842. spdif_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2843. pr_debug("%s: msm_spdif_[%d]_tx_ch = %d\n", __func__,
  2844. idx, spdif_tx_cfg[idx].channels);
  2845. return 1;
  2846. }
  2847. static int msm_spdif_rx_format_get(struct snd_kcontrol *kcontrol,
  2848. struct snd_ctl_elem_value *ucontrol)
  2849. {
  2850. int idx = spdif_get_port_idx(kcontrol);
  2851. if (idx < 0)
  2852. return idx;
  2853. ucontrol->value.enumerated.item[0] =
  2854. spdif_get_format_value(spdif_rx_cfg[idx].bit_format);
  2855. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2856. idx, spdif_rx_cfg[idx].bit_format,
  2857. ucontrol->value.enumerated.item[0]);
  2858. return 0;
  2859. }
  2860. static int msm_spdif_rx_format_put(struct snd_kcontrol *kcontrol,
  2861. struct snd_ctl_elem_value *ucontrol)
  2862. {
  2863. int idx = spdif_get_port_idx(kcontrol);
  2864. if (idx < 0)
  2865. return idx;
  2866. spdif_rx_cfg[idx].bit_format =
  2867. spdif_get_format(ucontrol->value.enumerated.item[0]);
  2868. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2869. idx, spdif_rx_cfg[idx].bit_format,
  2870. ucontrol->value.enumerated.item[0]);
  2871. return 0;
  2872. }
  2873. static int msm_spdif_tx_format_get(struct snd_kcontrol *kcontrol,
  2874. struct snd_ctl_elem_value *ucontrol)
  2875. {
  2876. int idx = spdif_get_port_idx(kcontrol);
  2877. if (idx < 0)
  2878. return idx;
  2879. ucontrol->value.enumerated.item[0] =
  2880. spdif_get_format_value(spdif_tx_cfg[idx].bit_format);
  2881. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2882. idx, spdif_tx_cfg[idx].bit_format,
  2883. ucontrol->value.enumerated.item[0]);
  2884. return 0;
  2885. }
  2886. static int msm_spdif_tx_format_put(struct snd_kcontrol *kcontrol,
  2887. struct snd_ctl_elem_value *ucontrol)
  2888. {
  2889. int idx = spdif_get_port_idx(kcontrol);
  2890. if (idx < 0)
  2891. return idx;
  2892. spdif_tx_cfg[idx].bit_format =
  2893. spdif_get_format(ucontrol->value.enumerated.item[0]);
  2894. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2895. idx, spdif_tx_cfg[idx].bit_format,
  2896. ucontrol->value.enumerated.item[0]);
  2897. return 0;
  2898. }
  2899. static const struct snd_kcontrol_new msm_snd_sb_controls[] = {
  2900. SOC_ENUM_EXT("SLIM_0_RX Channels", slim_0_rx_chs,
  2901. slim_rx_ch_get, slim_rx_ch_put),
  2902. SOC_ENUM_EXT("SLIM_2_RX Channels", slim_2_rx_chs,
  2903. slim_rx_ch_get, slim_rx_ch_put),
  2904. SOC_ENUM_EXT("SLIM_0_TX Channels", slim_0_tx_chs,
  2905. slim_tx_ch_get, slim_tx_ch_put),
  2906. SOC_ENUM_EXT("SLIM_1_TX Channels", slim_1_tx_chs,
  2907. slim_tx_ch_get, slim_tx_ch_put),
  2908. SOC_ENUM_EXT("SLIM_5_RX Channels", slim_5_rx_chs,
  2909. slim_rx_ch_get, slim_rx_ch_put),
  2910. SOC_ENUM_EXT("SLIM_6_RX Channels", slim_6_rx_chs,
  2911. slim_rx_ch_get, slim_rx_ch_put),
  2912. SOC_ENUM_EXT("SLIM_0_RX Format", slim_0_rx_format,
  2913. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2914. SOC_ENUM_EXT("SLIM_5_RX Format", slim_5_rx_format,
  2915. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2916. SOC_ENUM_EXT("SLIM_6_RX Format", slim_6_rx_format,
  2917. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2918. SOC_ENUM_EXT("SLIM_0_TX Format", slim_0_tx_format,
  2919. slim_tx_bit_format_get, slim_tx_bit_format_put),
  2920. SOC_ENUM_EXT("SLIM_0_RX SampleRate", slim_0_rx_sample_rate,
  2921. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2922. SOC_ENUM_EXT("SLIM_2_RX SampleRate", slim_2_rx_sample_rate,
  2923. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2924. SOC_ENUM_EXT("SLIM_0_TX SampleRate", slim_0_tx_sample_rate,
  2925. slim_tx_sample_rate_get, slim_tx_sample_rate_put),
  2926. SOC_ENUM_EXT("SLIM_5_RX SampleRate", slim_5_rx_sample_rate,
  2927. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2928. SOC_ENUM_EXT("SLIM_6_RX SampleRate", slim_6_rx_sample_rate,
  2929. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2930. };
  2931. static const struct snd_kcontrol_new msm_snd_va_controls[] = {
  2932. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Channels", va_cdc_dma_tx_0_chs,
  2933. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2934. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Channels", va_cdc_dma_tx_1_chs,
  2935. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2936. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Format", va_cdc_dma_tx_0_format,
  2937. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2938. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Format", va_cdc_dma_tx_1_format,
  2939. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2940. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 SampleRate",
  2941. va_cdc_dma_tx_0_sample_rate,
  2942. cdc_dma_tx_sample_rate_get,
  2943. cdc_dma_tx_sample_rate_put),
  2944. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 SampleRate",
  2945. va_cdc_dma_tx_1_sample_rate,
  2946. cdc_dma_tx_sample_rate_get,
  2947. cdc_dma_tx_sample_rate_put),
  2948. };
  2949. static const struct snd_kcontrol_new msm_snd_wsa_controls[] = {
  2950. SOC_ENUM_EXT("VI_FEED_TX Channels", vi_feed_tx_chs,
  2951. msm_vi_feed_tx_ch_get, msm_vi_feed_tx_ch_put),
  2952. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Channels", wsa_cdc_dma_rx_0_chs,
  2953. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2954. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Channels", wsa_cdc_dma_rx_1_chs,
  2955. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2956. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 Channels", wsa_cdc_dma_tx_0_chs,
  2957. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2958. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Channels", wsa_cdc_dma_tx_1_chs,
  2959. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2960. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Channels", wsa_cdc_dma_tx_2_chs,
  2961. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2962. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Format", wsa_cdc_dma_rx_0_format,
  2963. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2964. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Format", wsa_cdc_dma_rx_1_format,
  2965. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2966. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Format", wsa_cdc_dma_tx_1_format,
  2967. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2968. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Format", wsa_cdc_dma_tx_2_format,
  2969. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2970. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 SampleRate",
  2971. wsa_cdc_dma_rx_0_sample_rate,
  2972. cdc_dma_rx_sample_rate_get,
  2973. cdc_dma_rx_sample_rate_put),
  2974. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 SampleRate",
  2975. wsa_cdc_dma_rx_1_sample_rate,
  2976. cdc_dma_rx_sample_rate_get,
  2977. cdc_dma_rx_sample_rate_put),
  2978. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 SampleRate",
  2979. wsa_cdc_dma_tx_0_sample_rate,
  2980. cdc_dma_tx_sample_rate_get,
  2981. cdc_dma_tx_sample_rate_put),
  2982. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 SampleRate",
  2983. wsa_cdc_dma_tx_1_sample_rate,
  2984. cdc_dma_tx_sample_rate_get,
  2985. cdc_dma_tx_sample_rate_put),
  2986. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 SampleRate",
  2987. wsa_cdc_dma_tx_2_sample_rate,
  2988. cdc_dma_tx_sample_rate_get,
  2989. cdc_dma_tx_sample_rate_put),
  2990. };
  2991. static const struct snd_kcontrol_new msm_snd_controls[] = {
  2992. SOC_ENUM_EXT("USB_AUDIO_RX Channels", usb_rx_chs,
  2993. usb_audio_rx_ch_get, usb_audio_rx_ch_put),
  2994. SOC_ENUM_EXT("USB_AUDIO_TX Channels", usb_tx_chs,
  2995. usb_audio_tx_ch_get, usb_audio_tx_ch_put),
  2996. SOC_ENUM_EXT("PROXY_RX Channels", proxy_rx_chs,
  2997. proxy_rx_ch_get, proxy_rx_ch_put),
  2998. SOC_ENUM_EXT("USB_AUDIO_RX Format", usb_rx_format,
  2999. usb_audio_rx_format_get, usb_audio_rx_format_put),
  3000. SOC_ENUM_EXT("USB_AUDIO_TX Format", usb_tx_format,
  3001. usb_audio_tx_format_get, usb_audio_tx_format_put),
  3002. SOC_ENUM_EXT("BT SampleRate", bt_sample_rate,
  3003. msm_bt_sample_rate_get,
  3004. msm_bt_sample_rate_put),
  3005. SOC_ENUM_EXT("USB_AUDIO_RX SampleRate", usb_rx_sample_rate,
  3006. usb_audio_rx_sample_rate_get,
  3007. usb_audio_rx_sample_rate_put),
  3008. SOC_ENUM_EXT("USB_AUDIO_TX SampleRate", usb_tx_sample_rate,
  3009. usb_audio_tx_sample_rate_get,
  3010. usb_audio_tx_sample_rate_put),
  3011. SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3012. tdm_rx_sample_rate_get,
  3013. tdm_rx_sample_rate_put),
  3014. SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3015. tdm_tx_sample_rate_get,
  3016. tdm_tx_sample_rate_put),
  3017. SOC_ENUM_EXT("PRI_TDM_RX_0 Format", tdm_rx_format,
  3018. tdm_rx_format_get,
  3019. tdm_rx_format_put),
  3020. SOC_ENUM_EXT("PRI_TDM_TX_0 Format", tdm_tx_format,
  3021. tdm_tx_format_get,
  3022. tdm_tx_format_put),
  3023. SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", tdm_rx_chs,
  3024. tdm_rx_ch_get,
  3025. tdm_rx_ch_put),
  3026. SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", tdm_tx_chs,
  3027. tdm_tx_ch_get,
  3028. tdm_tx_ch_put),
  3029. SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3030. tdm_rx_sample_rate_get,
  3031. tdm_rx_sample_rate_put),
  3032. SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3033. tdm_tx_sample_rate_get,
  3034. tdm_tx_sample_rate_put),
  3035. SOC_ENUM_EXT("SEC_TDM_RX_0 Format", tdm_rx_format,
  3036. tdm_rx_format_get,
  3037. tdm_rx_format_put),
  3038. SOC_ENUM_EXT("SEC_TDM_TX_0 Format", tdm_tx_format,
  3039. tdm_tx_format_get,
  3040. tdm_tx_format_put),
  3041. SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", tdm_rx_chs,
  3042. tdm_rx_ch_get,
  3043. tdm_rx_ch_put),
  3044. SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", tdm_tx_chs,
  3045. tdm_tx_ch_get,
  3046. tdm_tx_ch_put),
  3047. SOC_ENUM_EXT("TERT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3048. tdm_rx_sample_rate_get,
  3049. tdm_rx_sample_rate_put),
  3050. SOC_ENUM_EXT("TERT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3051. tdm_tx_sample_rate_get,
  3052. tdm_tx_sample_rate_put),
  3053. SOC_ENUM_EXT("TERT_TDM_RX_0 Format", tdm_rx_format,
  3054. tdm_rx_format_get,
  3055. tdm_rx_format_put),
  3056. SOC_ENUM_EXT("TERT_TDM_TX_0 Format", tdm_tx_format,
  3057. tdm_tx_format_get,
  3058. tdm_tx_format_put),
  3059. SOC_ENUM_EXT("TERT_TDM_RX_0 Channels", tdm_rx_chs,
  3060. tdm_rx_ch_get,
  3061. tdm_rx_ch_put),
  3062. SOC_ENUM_EXT("TERT_TDM_TX_0 Channels", tdm_tx_chs,
  3063. tdm_tx_ch_get,
  3064. tdm_tx_ch_put),
  3065. SOC_ENUM_EXT("QUAT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3066. tdm_rx_sample_rate_get,
  3067. tdm_rx_sample_rate_put),
  3068. SOC_ENUM_EXT("QUAT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3069. tdm_tx_sample_rate_get,
  3070. tdm_tx_sample_rate_put),
  3071. SOC_ENUM_EXT("QUAT_TDM_RX_0 Format", tdm_rx_format,
  3072. tdm_rx_format_get,
  3073. tdm_rx_format_put),
  3074. SOC_ENUM_EXT("QUAT_TDM_TX_0 Format", tdm_tx_format,
  3075. tdm_tx_format_get,
  3076. tdm_tx_format_put),
  3077. SOC_ENUM_EXT("QUAT_TDM_RX_0 Channels", tdm_rx_chs,
  3078. tdm_rx_ch_get,
  3079. tdm_rx_ch_put),
  3080. SOC_ENUM_EXT("QUAT_TDM_TX_0 Channels", tdm_tx_chs,
  3081. tdm_tx_ch_get,
  3082. tdm_tx_ch_put),
  3083. SOC_ENUM_EXT("QUIN_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3084. tdm_rx_sample_rate_get,
  3085. tdm_rx_sample_rate_put),
  3086. SOC_ENUM_EXT("QUIN_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3087. tdm_tx_sample_rate_get,
  3088. tdm_tx_sample_rate_put),
  3089. SOC_ENUM_EXT("QUIN_TDM_RX_0 Format", tdm_rx_format,
  3090. tdm_rx_format_get,
  3091. tdm_rx_format_put),
  3092. SOC_ENUM_EXT("QUIN_TDM_TX_0 Format", tdm_tx_format,
  3093. tdm_tx_format_get,
  3094. tdm_tx_format_put),
  3095. SOC_ENUM_EXT("QUIN_TDM_RX_0 Channels", tdm_rx_chs,
  3096. tdm_rx_ch_get,
  3097. tdm_rx_ch_put),
  3098. SOC_ENUM_EXT("QUIN_TDM_TX_0 Channels", tdm_tx_chs,
  3099. tdm_tx_ch_get,
  3100. tdm_tx_ch_put),
  3101. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  3102. aux_pcm_rx_sample_rate_get,
  3103. aux_pcm_rx_sample_rate_put),
  3104. SOC_ENUM_EXT("SEC_AUX_PCM_RX SampleRate", sec_aux_pcm_rx_sample_rate,
  3105. aux_pcm_rx_sample_rate_get,
  3106. aux_pcm_rx_sample_rate_put),
  3107. SOC_ENUM_EXT("TERT_AUX_PCM_RX SampleRate", tert_aux_pcm_rx_sample_rate,
  3108. aux_pcm_rx_sample_rate_get,
  3109. aux_pcm_rx_sample_rate_put),
  3110. SOC_ENUM_EXT("QUAT_AUX_PCM_RX SampleRate", quat_aux_pcm_rx_sample_rate,
  3111. aux_pcm_rx_sample_rate_get,
  3112. aux_pcm_rx_sample_rate_put),
  3113. SOC_ENUM_EXT("QUIN_AUX_PCM_RX SampleRate", quin_aux_pcm_rx_sample_rate,
  3114. aux_pcm_rx_sample_rate_get,
  3115. aux_pcm_rx_sample_rate_put),
  3116. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  3117. aux_pcm_tx_sample_rate_get,
  3118. aux_pcm_tx_sample_rate_put),
  3119. SOC_ENUM_EXT("SEC_AUX_PCM_TX SampleRate", sec_aux_pcm_tx_sample_rate,
  3120. aux_pcm_tx_sample_rate_get,
  3121. aux_pcm_tx_sample_rate_put),
  3122. SOC_ENUM_EXT("TERT_AUX_PCM_TX SampleRate", tert_aux_pcm_tx_sample_rate,
  3123. aux_pcm_tx_sample_rate_get,
  3124. aux_pcm_tx_sample_rate_put),
  3125. SOC_ENUM_EXT("QUAT_AUX_PCM_TX SampleRate", quat_aux_pcm_tx_sample_rate,
  3126. aux_pcm_tx_sample_rate_get,
  3127. aux_pcm_tx_sample_rate_put),
  3128. SOC_ENUM_EXT("QUIN_AUX_PCM_TX SampleRate", quin_aux_pcm_tx_sample_rate,
  3129. aux_pcm_tx_sample_rate_get,
  3130. aux_pcm_tx_sample_rate_put),
  3131. SOC_ENUM_EXT("SEN_AUX_PCM_TX SampleRate", sen_aux_pcm_tx_sample_rate,
  3132. aux_pcm_tx_sample_rate_get,
  3133. aux_pcm_tx_sample_rate_put),
  3134. SOC_ENUM_EXT("PRIM_MI2S_RX SampleRate", prim_mi2s_rx_sample_rate,
  3135. mi2s_rx_sample_rate_get,
  3136. mi2s_rx_sample_rate_put),
  3137. SOC_ENUM_EXT("SEC_MI2S_RX SampleRate", sec_mi2s_rx_sample_rate,
  3138. mi2s_rx_sample_rate_get,
  3139. mi2s_rx_sample_rate_put),
  3140. SOC_ENUM_EXT("TERT_MI2S_RX SampleRate", tert_mi2s_rx_sample_rate,
  3141. mi2s_rx_sample_rate_get,
  3142. mi2s_rx_sample_rate_put),
  3143. SOC_ENUM_EXT("QUAT_MI2S_RX SampleRate", quat_mi2s_rx_sample_rate,
  3144. mi2s_rx_sample_rate_get,
  3145. mi2s_rx_sample_rate_put),
  3146. SOC_ENUM_EXT("QUIN_MI2S_RX SampleRate", quin_mi2s_rx_sample_rate,
  3147. mi2s_rx_sample_rate_get,
  3148. mi2s_rx_sample_rate_put),
  3149. SOC_ENUM_EXT("SEN_MI2S_RX SampleRate", sen_mi2s_rx_sample_rate,
  3150. mi2s_rx_sample_rate_get,
  3151. mi2s_rx_sample_rate_put),
  3152. SOC_ENUM_EXT("PRIM_MI2S_TX SampleRate", prim_mi2s_tx_sample_rate,
  3153. mi2s_tx_sample_rate_get,
  3154. mi2s_tx_sample_rate_put),
  3155. SOC_ENUM_EXT("SEC_MI2S_TX SampleRate", sec_mi2s_tx_sample_rate,
  3156. mi2s_tx_sample_rate_get,
  3157. mi2s_tx_sample_rate_put),
  3158. SOC_ENUM_EXT("TERT_MI2S_TX SampleRate", tert_mi2s_tx_sample_rate,
  3159. mi2s_tx_sample_rate_get,
  3160. mi2s_tx_sample_rate_put),
  3161. SOC_ENUM_EXT("QUAT_MI2S_TX SampleRate", quat_mi2s_tx_sample_rate,
  3162. mi2s_tx_sample_rate_get,
  3163. mi2s_tx_sample_rate_put),
  3164. SOC_ENUM_EXT("QUIN_MI2S_TX SampleRate", quin_mi2s_tx_sample_rate,
  3165. mi2s_tx_sample_rate_get,
  3166. mi2s_tx_sample_rate_put),
  3167. SOC_ENUM_EXT("SEN_MI2S_TX SampleRate", sen_mi2s_tx_sample_rate,
  3168. mi2s_tx_sample_rate_get,
  3169. mi2s_tx_sample_rate_put),
  3170. SOC_ENUM_EXT("PRIM_MI2S_RX Channels", prim_mi2s_rx_chs,
  3171. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3172. SOC_ENUM_EXT("PRIM_MI2S_TX Channels", prim_mi2s_tx_chs,
  3173. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3174. SOC_ENUM_EXT("SEC_MI2S_RX Channels", sec_mi2s_rx_chs,
  3175. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3176. SOC_ENUM_EXT("SEC_MI2S_TX Channels", sec_mi2s_tx_chs,
  3177. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3178. SOC_ENUM_EXT("TERT_MI2S_RX Channels", tert_mi2s_rx_chs,
  3179. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3180. SOC_ENUM_EXT("TERT_MI2S_TX Channels", tert_mi2s_tx_chs,
  3181. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3182. SOC_ENUM_EXT("QUAT_MI2S_RX Channels", quat_mi2s_rx_chs,
  3183. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3184. SOC_ENUM_EXT("QUAT_MI2S_TX Channels", quat_mi2s_tx_chs,
  3185. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3186. SOC_ENUM_EXT("QUIN_MI2S_RX Channels", quin_mi2s_rx_chs,
  3187. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3188. SOC_ENUM_EXT("QUIN_MI2S_TX Channels", quin_mi2s_tx_chs,
  3189. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3190. SOC_ENUM_EXT("SEN_MI2S_RX Channels", sen_mi2s_rx_chs,
  3191. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3192. SOC_ENUM_EXT("SEN_MI2S_TX Channels", sen_mi2s_tx_chs,
  3193. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3194. SOC_ENUM_EXT("PRIM_MI2S_RX Format", mi2s_rx_format,
  3195. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3196. SOC_ENUM_EXT("PRIM_MI2S_TX Format", mi2s_tx_format,
  3197. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3198. SOC_ENUM_EXT("SEC_MI2S_RX Format", mi2s_rx_format,
  3199. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3200. SOC_ENUM_EXT("SEC_MI2S_TX Format", mi2s_tx_format,
  3201. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3202. SOC_ENUM_EXT("TERT_MI2S_RX Format", mi2s_rx_format,
  3203. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3204. SOC_ENUM_EXT("TERT_MI2S_TX Format", mi2s_tx_format,
  3205. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3206. SOC_ENUM_EXT("QUAT_MI2S_RX Format", mi2s_rx_format,
  3207. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3208. SOC_ENUM_EXT("QUAT_MI2S_TX Format", mi2s_tx_format,
  3209. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3210. SOC_ENUM_EXT("QUIN_MI2S_RX Format", mi2s_rx_format,
  3211. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3212. SOC_ENUM_EXT("QUIN_MI2S_TX Format", mi2s_tx_format,
  3213. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3214. SOC_ENUM_EXT("SEN_MI2S_RX Format", mi2s_rx_format,
  3215. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3216. SOC_ENUM_EXT("SEN_MI2S_TX Format", mi2s_tx_format,
  3217. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3218. SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
  3219. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3220. SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
  3221. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3222. SOC_ENUM_EXT("SEC_AUX_PCM_RX Format", aux_pcm_rx_format,
  3223. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3224. SOC_ENUM_EXT("SEC_AUX_PCM_TX Format", aux_pcm_tx_format,
  3225. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3226. SOC_ENUM_EXT("TERT_AUX_PCM_RX Format", aux_pcm_rx_format,
  3227. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3228. SOC_ENUM_EXT("TERT_AUX_PCM_TX Format", aux_pcm_tx_format,
  3229. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3230. SOC_ENUM_EXT("QUAT_AUX_PCM_RX Format", aux_pcm_rx_format,
  3231. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3232. SOC_ENUM_EXT("QUAT_AUX_PCM_TX Format", aux_pcm_tx_format,
  3233. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3234. SOC_ENUM_EXT("QUIN_AUX_PCM_RX Format", aux_pcm_rx_format,
  3235. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3236. SOC_ENUM_EXT("QUIN_AUX_PCM_TX Format", aux_pcm_tx_format,
  3237. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3238. SOC_ENUM_EXT("SEN_AUX_PCM_RX Format", aux_pcm_rx_format,
  3239. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3240. SOC_ENUM_EXT("SEN_AUX_PCM_TX Format", aux_pcm_tx_format,
  3241. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3242. SOC_SINGLE_MULTI_EXT("VAD CFG", SND_SOC_NOPM, 0, 1000, 0, 3, NULL,
  3243. msm_snd_vad_cfg_put),
  3244. SOC_ENUM_EXT("PRIM_SPDIF_RX SampleRate", spdif_rx_sample_rate,
  3245. msm_spdif_rx_sample_rate_get,
  3246. msm_spdif_rx_sample_rate_put),
  3247. SOC_ENUM_EXT("PRIM_SPDIF_TX SampleRate", spdif_tx_sample_rate,
  3248. msm_spdif_tx_sample_rate_get,
  3249. msm_spdif_tx_sample_rate_put),
  3250. SOC_ENUM_EXT("SEC_SPDIF_RX SampleRate", spdif_rx_sample_rate,
  3251. msm_spdif_rx_sample_rate_get,
  3252. msm_spdif_rx_sample_rate_put),
  3253. SOC_ENUM_EXT("SEC_SPDIF_TX SampleRate", spdif_tx_sample_rate,
  3254. msm_spdif_tx_sample_rate_get,
  3255. msm_spdif_tx_sample_rate_put),
  3256. SOC_ENUM_EXT("PRIM_SPDIF_RX Channels", spdif_rx_chs,
  3257. msm_spdif_rx_ch_get, msm_spdif_rx_ch_put),
  3258. SOC_ENUM_EXT("PRIM_SPDIF_TX Channels", spdif_tx_chs,
  3259. msm_spdif_tx_ch_get, msm_spdif_tx_ch_put),
  3260. SOC_ENUM_EXT("SEC_SPDIF_RX Channels", spdif_rx_chs,
  3261. msm_spdif_rx_ch_get, msm_spdif_rx_ch_put),
  3262. SOC_ENUM_EXT("SEC_SPDIF_TX Channels", spdif_tx_chs,
  3263. msm_spdif_tx_ch_get, msm_spdif_tx_ch_put),
  3264. SOC_ENUM_EXT("PRIM_SPDIF_RX Format", spdif_rx_format,
  3265. msm_spdif_rx_format_get, msm_spdif_rx_format_put),
  3266. SOC_ENUM_EXT("PRIM_SPDIF_TX Format", spdif_tx_format,
  3267. msm_spdif_tx_format_get, msm_spdif_tx_format_put),
  3268. SOC_ENUM_EXT("SEC_SPDIF_RX Format", spdif_rx_format,
  3269. msm_spdif_rx_format_get, msm_spdif_rx_format_put),
  3270. SOC_ENUM_EXT("SEC_SPDIF_TX Format", spdif_tx_format,
  3271. msm_spdif_tx_format_get, msm_spdif_tx_format_put),
  3272. };
  3273. static int msm_snd_enable_codec_ext_clk(struct snd_soc_codec *codec,
  3274. int enable, bool dapm)
  3275. {
  3276. int ret = 0;
  3277. if (!strcmp(dev_name(codec->dev), "tasha_codec")) {
  3278. ret = tasha_cdc_mclk_enable(codec, enable, dapm);
  3279. } else {
  3280. dev_err(codec->dev, "%s: unknown codec to enable ext clk\n",
  3281. __func__);
  3282. ret = -EINVAL;
  3283. }
  3284. return ret;
  3285. }
  3286. static int msm_snd_enable_codec_ext_tx_clk(struct snd_soc_codec *codec,
  3287. int enable, bool dapm)
  3288. {
  3289. int ret = 0;
  3290. if (!strcmp(dev_name(codec->dev), "tasha_codec")) {
  3291. ret = tasha_cdc_mclk_tx_enable(codec, enable, dapm);
  3292. } else {
  3293. dev_err(codec->dev, "%s: unknown codec to enable TX ext clk\n",
  3294. __func__);
  3295. ret = -EINVAL;
  3296. }
  3297. return ret;
  3298. }
  3299. static int msm_mclk_tx_event(struct snd_soc_dapm_widget *w,
  3300. struct snd_kcontrol *kcontrol, int event)
  3301. {
  3302. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  3303. pr_debug("%s: event = %d\n", __func__, event);
  3304. switch (event) {
  3305. case SND_SOC_DAPM_PRE_PMU:
  3306. return msm_snd_enable_codec_ext_tx_clk(codec, 1, true);
  3307. case SND_SOC_DAPM_POST_PMD:
  3308. return msm_snd_enable_codec_ext_tx_clk(codec, 0, true);
  3309. }
  3310. return 0;
  3311. }
  3312. static int msm_mclk_event(struct snd_soc_dapm_widget *w,
  3313. struct snd_kcontrol *kcontrol, int event)
  3314. {
  3315. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  3316. pr_debug("%s: event = %d\n", __func__, event);
  3317. switch (event) {
  3318. case SND_SOC_DAPM_PRE_PMU:
  3319. return msm_snd_enable_codec_ext_clk(codec, 1, true);
  3320. case SND_SOC_DAPM_POST_PMD:
  3321. return msm_snd_enable_codec_ext_clk(codec, 0, true);
  3322. }
  3323. return 0;
  3324. }
  3325. static const struct snd_soc_dapm_widget msm_dapm_widgets[] = {
  3326. SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0,
  3327. msm_mclk_event,
  3328. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3329. SND_SOC_DAPM_SUPPLY("MCLK TX", SND_SOC_NOPM, 0, 0,
  3330. msm_mclk_tx_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3331. SND_SOC_DAPM_MIC("Analog Mic3", NULL),
  3332. SND_SOC_DAPM_MIC("Analog Mic4", NULL),
  3333. };
  3334. static int msm_dmic_event(struct snd_soc_dapm_widget *w,
  3335. struct snd_kcontrol *kcontrol, int event)
  3336. {
  3337. struct msm_asoc_mach_data *pdata = NULL;
  3338. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  3339. int ret = 0;
  3340. uint32_t dmic_idx;
  3341. int *dmic_gpio_cnt;
  3342. struct device_node *dmic_gpio;
  3343. char *wname;
  3344. wname = strpbrk(w->name, "01234567");
  3345. if (!wname) {
  3346. dev_err(codec->dev, "%s: widget not found\n", __func__);
  3347. return -EINVAL;
  3348. }
  3349. ret = kstrtouint(wname, 10, &dmic_idx);
  3350. if (ret < 0) {
  3351. dev_err(codec->dev, "%s: Invalid DMIC line on the codec\n",
  3352. __func__);
  3353. return -EINVAL;
  3354. }
  3355. pdata = snd_soc_card_get_drvdata(codec->component.card);
  3356. switch (dmic_idx) {
  3357. case 0:
  3358. case 1:
  3359. dmic_gpio_cnt = &pdata->dmic_01_gpio_cnt;
  3360. dmic_gpio = pdata->dmic_01_gpio_p;
  3361. break;
  3362. case 2:
  3363. case 3:
  3364. dmic_gpio_cnt = &pdata->dmic_23_gpio_cnt;
  3365. dmic_gpio = pdata->dmic_23_gpio_p;
  3366. break;
  3367. case 4:
  3368. case 5:
  3369. dmic_gpio_cnt = &pdata->dmic_45_gpio_cnt;
  3370. dmic_gpio = pdata->dmic_45_gpio_p;
  3371. break;
  3372. case 6:
  3373. case 7:
  3374. dmic_gpio_cnt = &pdata->dmic_67_gpio_cnt;
  3375. dmic_gpio = pdata->dmic_67_gpio_p;
  3376. break;
  3377. default:
  3378. dev_err(codec->dev, "%s: Invalid DMIC Selection\n",
  3379. __func__);
  3380. return -EINVAL;
  3381. }
  3382. dev_dbg(codec->dev, "%s: event %d DMIC%d dmic_gpio_cnt %d\n",
  3383. __func__, event, dmic_idx, *dmic_gpio_cnt);
  3384. switch (event) {
  3385. case SND_SOC_DAPM_PRE_PMU:
  3386. (*dmic_gpio_cnt)++;
  3387. if (*dmic_gpio_cnt == 1) {
  3388. ret = msm_cdc_pinctrl_select_active_state(
  3389. dmic_gpio);
  3390. if (ret < 0) {
  3391. dev_err(codec->dev, "%s: gpio set cannot be activated %sd\n",
  3392. __func__, "dmic_gpio");
  3393. return ret;
  3394. }
  3395. }
  3396. break;
  3397. case SND_SOC_DAPM_POST_PMD:
  3398. (*dmic_gpio_cnt)--;
  3399. if (*dmic_gpio_cnt == 0) {
  3400. ret = msm_cdc_pinctrl_select_sleep_state(
  3401. dmic_gpio);
  3402. if (ret < 0) {
  3403. dev_err(codec->dev, "%s: gpio set cannot be de-activated %sd\n",
  3404. __func__, "dmic_gpio");
  3405. return ret;
  3406. }
  3407. }
  3408. break;
  3409. default:
  3410. dev_err(codec->dev, "%s: invalid DAPM event %d\n",
  3411. __func__, event);
  3412. return -EINVAL;
  3413. }
  3414. return 0;
  3415. }
  3416. static const struct snd_soc_dapm_widget msm_va_dapm_widgets[] = {
  3417. SND_SOC_DAPM_MIC("Digital Mic0", msm_dmic_event),
  3418. SND_SOC_DAPM_MIC("Digital Mic1", msm_dmic_event),
  3419. SND_SOC_DAPM_MIC("Digital Mic2", msm_dmic_event),
  3420. SND_SOC_DAPM_MIC("Digital Mic3", msm_dmic_event),
  3421. SND_SOC_DAPM_MIC("Digital Mic4", msm_dmic_event),
  3422. SND_SOC_DAPM_MIC("Digital Mic5", msm_dmic_event),
  3423. SND_SOC_DAPM_MIC("Digital Mic6", msm_dmic_event),
  3424. SND_SOC_DAPM_MIC("Digital Mic7", msm_dmic_event),
  3425. };
  3426. static const struct snd_soc_dapm_widget msm_wsa_dapm_widgets[] = {
  3427. };
  3428. static inline int param_is_mask(int p)
  3429. {
  3430. return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) &&
  3431. (p <= SNDRV_PCM_HW_PARAM_LAST_MASK);
  3432. }
  3433. static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p,
  3434. int n)
  3435. {
  3436. return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]);
  3437. }
  3438. static void param_set_mask(struct snd_pcm_hw_params *p, int n,
  3439. unsigned int bit)
  3440. {
  3441. if (bit >= SNDRV_MASK_MAX)
  3442. return;
  3443. if (param_is_mask(n)) {
  3444. struct snd_mask *m = param_to_mask(p, n);
  3445. m->bits[0] = 0;
  3446. m->bits[1] = 0;
  3447. m->bits[bit >> 5] |= (1 << (bit & 31));
  3448. }
  3449. }
  3450. static int msm_slim_get_ch_from_beid(int32_t be_id)
  3451. {
  3452. int ch_id = 0;
  3453. switch (be_id) {
  3454. case MSM_BACKEND_DAI_SLIMBUS_0_RX:
  3455. ch_id = SLIM_RX_0;
  3456. break;
  3457. case MSM_BACKEND_DAI_SLIMBUS_1_RX:
  3458. ch_id = SLIM_RX_1;
  3459. break;
  3460. case MSM_BACKEND_DAI_SLIMBUS_2_RX:
  3461. ch_id = SLIM_RX_2;
  3462. break;
  3463. case MSM_BACKEND_DAI_SLIMBUS_3_RX:
  3464. ch_id = SLIM_RX_3;
  3465. break;
  3466. case MSM_BACKEND_DAI_SLIMBUS_4_RX:
  3467. ch_id = SLIM_RX_4;
  3468. break;
  3469. case MSM_BACKEND_DAI_SLIMBUS_6_RX:
  3470. ch_id = SLIM_RX_6;
  3471. break;
  3472. case MSM_BACKEND_DAI_SLIMBUS_0_TX:
  3473. ch_id = SLIM_TX_0;
  3474. break;
  3475. case MSM_BACKEND_DAI_SLIMBUS_3_TX:
  3476. ch_id = SLIM_TX_3;
  3477. break;
  3478. default:
  3479. ch_id = SLIM_RX_0;
  3480. break;
  3481. }
  3482. return ch_id;
  3483. }
  3484. static int msm_vad_get_portid_from_beid(int32_t be_id, int *port_id)
  3485. {
  3486. *port_id = 0xFFFF;
  3487. switch (be_id) {
  3488. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3489. *port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_0;
  3490. break;
  3491. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  3492. *port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  3493. break;
  3494. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  3495. *port_id = AFE_PORT_ID_QUINARY_TDM_TX;
  3496. break;
  3497. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  3498. *port_id = AFE_PORT_ID_QUINARY_PCM_TX;
  3499. break;
  3500. default:
  3501. return -EINVAL;
  3502. }
  3503. return 0;
  3504. }
  3505. static int msm_cdc_dma_get_idx_from_beid(int32_t be_id)
  3506. {
  3507. int idx = 0;
  3508. switch (be_id) {
  3509. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3510. idx = WSA_CDC_DMA_RX_0;
  3511. break;
  3512. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3513. idx = WSA_CDC_DMA_TX_0;
  3514. break;
  3515. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3516. idx = WSA_CDC_DMA_RX_1;
  3517. break;
  3518. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3519. idx = WSA_CDC_DMA_TX_1;
  3520. break;
  3521. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3522. idx = WSA_CDC_DMA_TX_2;
  3523. break;
  3524. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3525. idx = VA_CDC_DMA_TX_0;
  3526. break;
  3527. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3528. idx = VA_CDC_DMA_TX_1;
  3529. break;
  3530. default:
  3531. idx = VA_CDC_DMA_TX_0;
  3532. break;
  3533. }
  3534. return idx;
  3535. }
  3536. static int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  3537. struct snd_pcm_hw_params *params)
  3538. {
  3539. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3540. struct snd_interval *rate = hw_param_interval(params,
  3541. SNDRV_PCM_HW_PARAM_RATE);
  3542. struct snd_interval *channels = hw_param_interval(params,
  3543. SNDRV_PCM_HW_PARAM_CHANNELS);
  3544. int rc = 0;
  3545. int idx;
  3546. void *config = NULL;
  3547. struct snd_soc_codec *codec = NULL;
  3548. pr_debug("%s: format = %d, rate = %d\n",
  3549. __func__, params_format(params), params_rate(params));
  3550. switch (dai_link->id) {
  3551. case MSM_BACKEND_DAI_SLIMBUS_0_RX:
  3552. case MSM_BACKEND_DAI_SLIMBUS_1_RX:
  3553. case MSM_BACKEND_DAI_SLIMBUS_2_RX:
  3554. case MSM_BACKEND_DAI_SLIMBUS_3_RX:
  3555. case MSM_BACKEND_DAI_SLIMBUS_4_RX:
  3556. case MSM_BACKEND_DAI_SLIMBUS_6_RX:
  3557. idx = msm_slim_get_ch_from_beid(dai_link->id);
  3558. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3559. slim_rx_cfg[idx].bit_format);
  3560. rate->min = rate->max = slim_rx_cfg[idx].sample_rate;
  3561. channels->min = channels->max = slim_rx_cfg[idx].channels;
  3562. break;
  3563. case MSM_BACKEND_DAI_SLIMBUS_0_TX:
  3564. case MSM_BACKEND_DAI_SLIMBUS_3_TX:
  3565. idx = msm_slim_get_ch_from_beid(dai_link->id);
  3566. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3567. slim_tx_cfg[idx].bit_format);
  3568. rate->min = rate->max = slim_tx_cfg[idx].sample_rate;
  3569. channels->min = channels->max = slim_tx_cfg[idx].channels;
  3570. break;
  3571. case MSM_BACKEND_DAI_SLIMBUS_1_TX:
  3572. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3573. slim_tx_cfg[1].bit_format);
  3574. rate->min = rate->max = slim_tx_cfg[1].sample_rate;
  3575. channels->min = channels->max = slim_tx_cfg[1].channels;
  3576. break;
  3577. case MSM_BACKEND_DAI_SLIMBUS_4_TX:
  3578. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3579. SNDRV_PCM_FORMAT_S32_LE);
  3580. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  3581. channels->min = channels->max = msm_vi_feed_tx_ch;
  3582. break;
  3583. case MSM_BACKEND_DAI_SLIMBUS_5_RX:
  3584. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3585. slim_rx_cfg[5].bit_format);
  3586. rate->min = rate->max = slim_rx_cfg[5].sample_rate;
  3587. channels->min = channels->max = slim_rx_cfg[5].channels;
  3588. break;
  3589. case MSM_BACKEND_DAI_SLIMBUS_5_TX:
  3590. codec = rtd->codec;
  3591. rate->min = rate->max = SAMPLING_RATE_16KHZ;
  3592. channels->min = channels->max = 1;
  3593. config = msm_codec_fn.get_afe_config_fn(codec,
  3594. AFE_SLIMBUS_SLAVE_PORT_CONFIG);
  3595. if (config) {
  3596. rc = afe_set_config(AFE_SLIMBUS_SLAVE_PORT_CONFIG,
  3597. config, SLIMBUS_5_TX);
  3598. if (rc)
  3599. pr_err("%s: Failed to set slimbus slave port config %d\n",
  3600. __func__, rc);
  3601. }
  3602. break;
  3603. case MSM_BACKEND_DAI_SLIMBUS_7_RX:
  3604. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3605. slim_rx_cfg[SLIM_RX_7].bit_format);
  3606. rate->min = rate->max = slim_rx_cfg[SLIM_RX_7].sample_rate;
  3607. channels->min = channels->max =
  3608. slim_rx_cfg[SLIM_RX_7].channels;
  3609. break;
  3610. case MSM_BACKEND_DAI_SLIMBUS_7_TX:
  3611. rate->min = rate->max = slim_tx_cfg[SLIM_TX_7].sample_rate;
  3612. channels->min = channels->max =
  3613. slim_tx_cfg[SLIM_TX_7].channels;
  3614. break;
  3615. case MSM_BACKEND_DAI_SLIMBUS_8_TX:
  3616. rate->min = rate->max = slim_tx_cfg[SLIM_TX_8].sample_rate;
  3617. channels->min = channels->max =
  3618. slim_tx_cfg[SLIM_TX_8].channels;
  3619. break;
  3620. case MSM_BACKEND_DAI_USB_RX:
  3621. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3622. usb_rx_cfg.bit_format);
  3623. rate->min = rate->max = usb_rx_cfg.sample_rate;
  3624. channels->min = channels->max = usb_rx_cfg.channels;
  3625. break;
  3626. case MSM_BACKEND_DAI_USB_TX:
  3627. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3628. usb_tx_cfg.bit_format);
  3629. rate->min = rate->max = usb_tx_cfg.sample_rate;
  3630. channels->min = channels->max = usb_tx_cfg.channels;
  3631. break;
  3632. case MSM_BACKEND_DAI_AFE_PCM_RX:
  3633. channels->min = channels->max = proxy_rx_cfg.channels;
  3634. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3635. break;
  3636. case MSM_BACKEND_DAI_PRI_TDM_RX_0:
  3637. channels->min = channels->max =
  3638. tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  3639. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3640. tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
  3641. rate->min = rate->max = tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
  3642. break;
  3643. case MSM_BACKEND_DAI_PRI_TDM_TX_0:
  3644. channels->min = channels->max =
  3645. tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  3646. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3647. tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
  3648. rate->min = rate->max = tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
  3649. break;
  3650. case MSM_BACKEND_DAI_SEC_TDM_RX_0:
  3651. channels->min = channels->max =
  3652. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  3653. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3654. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  3655. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  3656. break;
  3657. case MSM_BACKEND_DAI_SEC_TDM_TX_0:
  3658. channels->min = channels->max =
  3659. tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  3660. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3661. tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
  3662. rate->min = rate->max = tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
  3663. break;
  3664. case MSM_BACKEND_DAI_TERT_TDM_RX_0:
  3665. channels->min = channels->max =
  3666. tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  3667. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3668. tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
  3669. rate->min = rate->max = tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
  3670. break;
  3671. case MSM_BACKEND_DAI_TERT_TDM_TX_0:
  3672. channels->min = channels->max =
  3673. tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  3674. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3675. tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
  3676. rate->min = rate->max = tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
  3677. break;
  3678. case MSM_BACKEND_DAI_QUAT_TDM_RX_0:
  3679. channels->min = channels->max =
  3680. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  3681. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3682. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  3683. rate->min = rate->max = tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3684. break;
  3685. case MSM_BACKEND_DAI_QUAT_TDM_TX_0:
  3686. channels->min = channels->max =
  3687. tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  3688. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3689. tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
  3690. rate->min = rate->max = tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3691. break;
  3692. case MSM_BACKEND_DAI_QUIN_TDM_RX_0:
  3693. channels->min = channels->max =
  3694. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  3695. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3696. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  3697. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  3698. break;
  3699. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  3700. channels->min = channels->max =
  3701. tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  3702. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3703. tdm_tx_cfg[TDM_QUIN][TDM_0].bit_format);
  3704. rate->min = rate->max = tdm_tx_cfg[TDM_QUIN][TDM_0].sample_rate;
  3705. break;
  3706. case MSM_BACKEND_DAI_AUXPCM_RX:
  3707. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3708. aux_pcm_rx_cfg[PRIM_AUX_PCM].bit_format);
  3709. rate->min = rate->max =
  3710. aux_pcm_rx_cfg[PRIM_AUX_PCM].sample_rate;
  3711. channels->min = channels->max =
  3712. aux_pcm_rx_cfg[PRIM_AUX_PCM].channels;
  3713. break;
  3714. case MSM_BACKEND_DAI_AUXPCM_TX:
  3715. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3716. aux_pcm_tx_cfg[PRIM_AUX_PCM].bit_format);
  3717. rate->min = rate->max =
  3718. aux_pcm_tx_cfg[PRIM_AUX_PCM].sample_rate;
  3719. channels->min = channels->max =
  3720. aux_pcm_tx_cfg[PRIM_AUX_PCM].channels;
  3721. break;
  3722. case MSM_BACKEND_DAI_SEC_AUXPCM_RX:
  3723. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3724. aux_pcm_rx_cfg[SEC_AUX_PCM].bit_format);
  3725. rate->min = rate->max =
  3726. aux_pcm_rx_cfg[SEC_AUX_PCM].sample_rate;
  3727. channels->min = channels->max =
  3728. aux_pcm_rx_cfg[SEC_AUX_PCM].channels;
  3729. break;
  3730. case MSM_BACKEND_DAI_SEC_AUXPCM_TX:
  3731. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3732. aux_pcm_tx_cfg[SEC_AUX_PCM].bit_format);
  3733. rate->min = rate->max =
  3734. aux_pcm_tx_cfg[SEC_AUX_PCM].sample_rate;
  3735. channels->min = channels->max =
  3736. aux_pcm_tx_cfg[SEC_AUX_PCM].channels;
  3737. break;
  3738. case MSM_BACKEND_DAI_TERT_AUXPCM_RX:
  3739. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3740. aux_pcm_rx_cfg[TERT_AUX_PCM].bit_format);
  3741. rate->min = rate->max =
  3742. aux_pcm_rx_cfg[TERT_AUX_PCM].sample_rate;
  3743. channels->min = channels->max =
  3744. aux_pcm_rx_cfg[TERT_AUX_PCM].channels;
  3745. break;
  3746. case MSM_BACKEND_DAI_TERT_AUXPCM_TX:
  3747. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3748. aux_pcm_tx_cfg[TERT_AUX_PCM].bit_format);
  3749. rate->min = rate->max =
  3750. aux_pcm_tx_cfg[TERT_AUX_PCM].sample_rate;
  3751. channels->min = channels->max =
  3752. aux_pcm_tx_cfg[TERT_AUX_PCM].channels;
  3753. break;
  3754. case MSM_BACKEND_DAI_QUAT_AUXPCM_RX:
  3755. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3756. aux_pcm_rx_cfg[QUAT_AUX_PCM].bit_format);
  3757. rate->min = rate->max =
  3758. aux_pcm_rx_cfg[QUAT_AUX_PCM].sample_rate;
  3759. channels->min = channels->max =
  3760. aux_pcm_rx_cfg[QUAT_AUX_PCM].channels;
  3761. break;
  3762. case MSM_BACKEND_DAI_QUAT_AUXPCM_TX:
  3763. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3764. aux_pcm_tx_cfg[QUAT_AUX_PCM].bit_format);
  3765. rate->min = rate->max =
  3766. aux_pcm_tx_cfg[QUAT_AUX_PCM].sample_rate;
  3767. channels->min = channels->max =
  3768. aux_pcm_tx_cfg[QUAT_AUX_PCM].channels;
  3769. break;
  3770. case MSM_BACKEND_DAI_QUIN_AUXPCM_RX:
  3771. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3772. aux_pcm_rx_cfg[QUIN_AUX_PCM].bit_format);
  3773. rate->min = rate->max =
  3774. aux_pcm_rx_cfg[QUIN_AUX_PCM].sample_rate;
  3775. channels->min = channels->max =
  3776. aux_pcm_rx_cfg[QUIN_AUX_PCM].channels;
  3777. break;
  3778. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  3779. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3780. aux_pcm_tx_cfg[QUIN_AUX_PCM].bit_format);
  3781. rate->min = rate->max =
  3782. aux_pcm_tx_cfg[QUIN_AUX_PCM].sample_rate;
  3783. channels->min = channels->max =
  3784. aux_pcm_tx_cfg[QUIN_AUX_PCM].channels;
  3785. break;
  3786. case MSM_BACKEND_DAI_SEN_AUXPCM_RX:
  3787. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3788. aux_pcm_rx_cfg[SEN_AUX_PCM].bit_format);
  3789. rate->min = rate->max =
  3790. aux_pcm_rx_cfg[SEN_AUX_PCM].sample_rate;
  3791. channels->min = channels->max =
  3792. aux_pcm_rx_cfg[SEN_AUX_PCM].channels;
  3793. break;
  3794. case MSM_BACKEND_DAI_SEN_AUXPCM_TX:
  3795. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3796. aux_pcm_tx_cfg[SEN_AUX_PCM].bit_format);
  3797. rate->min = rate->max =
  3798. aux_pcm_tx_cfg[SEN_AUX_PCM].sample_rate;
  3799. channels->min = channels->max =
  3800. aux_pcm_tx_cfg[SEN_AUX_PCM].channels;
  3801. break;
  3802. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  3803. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3804. mi2s_rx_cfg[PRIM_MI2S].bit_format);
  3805. rate->min = rate->max = mi2s_rx_cfg[PRIM_MI2S].sample_rate;
  3806. channels->min = channels->max =
  3807. mi2s_rx_cfg[PRIM_MI2S].channels;
  3808. break;
  3809. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  3810. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3811. mi2s_tx_cfg[PRIM_MI2S].bit_format);
  3812. rate->min = rate->max = mi2s_tx_cfg[PRIM_MI2S].sample_rate;
  3813. channels->min = channels->max =
  3814. mi2s_tx_cfg[PRIM_MI2S].channels;
  3815. break;
  3816. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  3817. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3818. mi2s_rx_cfg[SEC_MI2S].bit_format);
  3819. rate->min = rate->max = mi2s_rx_cfg[SEC_MI2S].sample_rate;
  3820. channels->min = channels->max =
  3821. mi2s_rx_cfg[SEC_MI2S].channels;
  3822. break;
  3823. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  3824. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3825. mi2s_tx_cfg[SEC_MI2S].bit_format);
  3826. rate->min = rate->max = mi2s_tx_cfg[SEC_MI2S].sample_rate;
  3827. channels->min = channels->max =
  3828. mi2s_tx_cfg[SEC_MI2S].channels;
  3829. break;
  3830. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  3831. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3832. mi2s_rx_cfg[TERT_MI2S].bit_format);
  3833. rate->min = rate->max = mi2s_rx_cfg[TERT_MI2S].sample_rate;
  3834. channels->min = channels->max =
  3835. mi2s_rx_cfg[TERT_MI2S].channels;
  3836. break;
  3837. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  3838. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3839. mi2s_tx_cfg[TERT_MI2S].bit_format);
  3840. rate->min = rate->max = mi2s_tx_cfg[TERT_MI2S].sample_rate;
  3841. channels->min = channels->max =
  3842. mi2s_tx_cfg[TERT_MI2S].channels;
  3843. break;
  3844. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  3845. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3846. mi2s_rx_cfg[QUAT_MI2S].bit_format);
  3847. rate->min = rate->max = mi2s_rx_cfg[QUAT_MI2S].sample_rate;
  3848. channels->min = channels->max =
  3849. mi2s_rx_cfg[QUAT_MI2S].channels;
  3850. break;
  3851. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  3852. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3853. mi2s_tx_cfg[QUAT_MI2S].bit_format);
  3854. rate->min = rate->max = mi2s_tx_cfg[QUAT_MI2S].sample_rate;
  3855. channels->min = channels->max =
  3856. mi2s_tx_cfg[QUAT_MI2S].channels;
  3857. break;
  3858. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  3859. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3860. mi2s_rx_cfg[QUIN_MI2S].bit_format);
  3861. rate->min = rate->max = mi2s_rx_cfg[QUIN_MI2S].sample_rate;
  3862. channels->min = channels->max =
  3863. mi2s_rx_cfg[QUIN_MI2S].channels;
  3864. break;
  3865. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  3866. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3867. mi2s_tx_cfg[QUIN_MI2S].bit_format);
  3868. rate->min = rate->max = mi2s_tx_cfg[QUIN_MI2S].sample_rate;
  3869. channels->min = channels->max =
  3870. mi2s_tx_cfg[QUIN_MI2S].channels;
  3871. break;
  3872. case MSM_BACKEND_DAI_SENARY_MI2S_RX:
  3873. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3874. mi2s_rx_cfg[SEN_MI2S].bit_format);
  3875. rate->min = rate->max = mi2s_rx_cfg[SEN_MI2S].sample_rate;
  3876. channels->min = channels->max =
  3877. mi2s_rx_cfg[SEN_MI2S].channels;
  3878. break;
  3879. case MSM_BACKEND_DAI_SENARY_MI2S_TX:
  3880. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3881. mi2s_tx_cfg[SEN_MI2S].bit_format);
  3882. rate->min = rate->max = mi2s_tx_cfg[SEN_MI2S].sample_rate;
  3883. channels->min = channels->max =
  3884. mi2s_tx_cfg[SEN_MI2S].channels;
  3885. break;
  3886. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3887. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3888. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3889. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3890. cdc_dma_rx_cfg[idx].bit_format);
  3891. rate->min = rate->max = cdc_dma_rx_cfg[idx].sample_rate;
  3892. channels->min = channels->max = cdc_dma_rx_cfg[idx].channels;
  3893. break;
  3894. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3895. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3896. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3897. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3898. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3899. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3900. cdc_dma_tx_cfg[idx].bit_format);
  3901. rate->min = rate->max = cdc_dma_tx_cfg[idx].sample_rate;
  3902. channels->min = channels->max = cdc_dma_tx_cfg[idx].channels;
  3903. break;
  3904. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3905. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3906. SNDRV_PCM_FORMAT_S32_LE);
  3907. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  3908. channels->min = channels->max = msm_vi_feed_tx_ch;
  3909. break;
  3910. case MSM_BACKEND_DAI_PRI_SPDIF_RX:
  3911. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3912. spdif_rx_cfg[PRIM_SPDIF_RX].bit_format);
  3913. rate->min = rate->max =
  3914. spdif_rx_cfg[PRIM_SPDIF_RX].sample_rate;
  3915. channels->min = channels->max =
  3916. spdif_rx_cfg[PRIM_SPDIF_RX].channels;
  3917. break;
  3918. case MSM_BACKEND_DAI_PRI_SPDIF_TX:
  3919. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3920. spdif_tx_cfg[PRIM_SPDIF_TX].bit_format);
  3921. rate->min = rate->max =
  3922. spdif_tx_cfg[PRIM_SPDIF_TX].sample_rate;
  3923. channels->min = channels->max =
  3924. spdif_tx_cfg[PRIM_SPDIF_TX].channels;
  3925. break;
  3926. case MSM_BACKEND_DAI_SEC_SPDIF_RX:
  3927. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3928. spdif_rx_cfg[SEC_SPDIF_RX].bit_format);
  3929. rate->min = rate->max =
  3930. spdif_rx_cfg[SEC_SPDIF_RX].sample_rate;
  3931. channels->min = channels->max =
  3932. spdif_rx_cfg[SEC_SPDIF_RX].channels;
  3933. break;
  3934. case MSM_BACKEND_DAI_SEC_SPDIF_TX:
  3935. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3936. spdif_tx_cfg[SEC_SPDIF_TX].bit_format);
  3937. rate->min = rate->max =
  3938. spdif_tx_cfg[SEC_SPDIF_TX].sample_rate;
  3939. channels->min = channels->max =
  3940. spdif_tx_cfg[SEC_SPDIF_TX].channels;
  3941. break;
  3942. default:
  3943. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3944. break;
  3945. }
  3946. return rc;
  3947. }
  3948. static int msm_afe_set_config(struct snd_soc_codec *codec)
  3949. {
  3950. int ret = 0;
  3951. void *config_data = NULL;
  3952. if (!msm_codec_fn.get_afe_config_fn) {
  3953. dev_err(codec->dev, "%s: codec get afe config not init'ed\n",
  3954. __func__);
  3955. return -EINVAL;
  3956. }
  3957. config_data = msm_codec_fn.get_afe_config_fn(codec,
  3958. AFE_CDC_REGISTERS_CONFIG);
  3959. if (config_data) {
  3960. ret = afe_set_config(AFE_CDC_REGISTERS_CONFIG, config_data, 0);
  3961. if (ret) {
  3962. dev_err(codec->dev,
  3963. "%s: Failed to set codec registers config %d\n",
  3964. __func__, ret);
  3965. return ret;
  3966. }
  3967. }
  3968. config_data = msm_codec_fn.get_afe_config_fn(codec,
  3969. AFE_CDC_REGISTER_PAGE_CONFIG);
  3970. if (config_data) {
  3971. ret = afe_set_config(AFE_CDC_REGISTER_PAGE_CONFIG, config_data,
  3972. 0);
  3973. if (ret)
  3974. dev_err(codec->dev,
  3975. "%s: Failed to set cdc register page config\n",
  3976. __func__);
  3977. }
  3978. config_data = msm_codec_fn.get_afe_config_fn(codec,
  3979. AFE_SLIMBUS_SLAVE_CONFIG);
  3980. if (config_data) {
  3981. ret = afe_set_config(AFE_SLIMBUS_SLAVE_CONFIG, config_data, 0);
  3982. if (ret) {
  3983. dev_err(codec->dev,
  3984. "%s: Failed to set slimbus slave config %d\n",
  3985. __func__, ret);
  3986. return ret;
  3987. }
  3988. }
  3989. return 0;
  3990. }
  3991. static void msm_afe_clear_config(void)
  3992. {
  3993. afe_clear_config(AFE_CDC_REGISTERS_CONFIG);
  3994. afe_clear_config(AFE_SLIMBUS_SLAVE_CONFIG);
  3995. }
  3996. static int msm_adsp_power_up_config(struct snd_soc_codec *codec,
  3997. struct snd_card *card)
  3998. {
  3999. int ret = 0;
  4000. unsigned long timeout;
  4001. int adsp_ready = 0;
  4002. bool snd_card_online = 0;
  4003. timeout = jiffies +
  4004. msecs_to_jiffies(ADSP_STATE_READY_TIMEOUT_MS);
  4005. do {
  4006. if (!snd_card_online) {
  4007. snd_card_online = snd_card_is_online_state(card);
  4008. pr_debug("%s: Sound card is %s\n", __func__,
  4009. snd_card_online ? "Online" : "Offline");
  4010. }
  4011. if (!adsp_ready) {
  4012. adsp_ready = q6core_is_adsp_ready();
  4013. pr_debug("%s: ADSP Audio is %s\n", __func__,
  4014. adsp_ready ? "ready" : "not ready");
  4015. }
  4016. if (snd_card_online && adsp_ready)
  4017. break;
  4018. /*
  4019. * Sound card/ADSP will be coming up after subsystem restart and
  4020. * it might not be fully up when the control reaches
  4021. * here. So, wait for 50msec before checking ADSP state
  4022. */
  4023. msleep(50);
  4024. } while (time_after(timeout, jiffies));
  4025. if (!snd_card_online || !adsp_ready) {
  4026. pr_err("%s: Timeout. Sound card is %s, ADSP Audio is %s\n",
  4027. __func__,
  4028. snd_card_online ? "Online" : "Offline",
  4029. adsp_ready ? "ready" : "not ready");
  4030. ret = -ETIMEDOUT;
  4031. goto err;
  4032. }
  4033. ret = msm_afe_set_config(codec);
  4034. if (ret)
  4035. pr_err("%s: Failed to set AFE config. err %d\n",
  4036. __func__, ret);
  4037. return 0;
  4038. err:
  4039. return ret;
  4040. }
  4041. static int qcs405_notifier_service_cb(struct notifier_block *this,
  4042. unsigned long opcode, void *ptr)
  4043. {
  4044. int ret;
  4045. struct snd_soc_card *card = NULL;
  4046. const char *be_dl_name = LPASS_BE_SLIMBUS_0_RX;
  4047. struct snd_soc_pcm_runtime *rtd;
  4048. struct snd_soc_codec *codec;
  4049. pr_debug("%s: Service opcode 0x%lx\n", __func__, opcode);
  4050. switch (opcode) {
  4051. case AUDIO_NOTIFIER_SERVICE_DOWN:
  4052. /*
  4053. * Use flag to ignore initial boot notifications
  4054. * On initial boot msm_adsp_power_up_config is
  4055. * called on init. There is no need to clear
  4056. * and set the config again on initial boot.
  4057. */
  4058. if (is_initial_boot)
  4059. break;
  4060. msm_afe_clear_config();
  4061. break;
  4062. case AUDIO_NOTIFIER_SERVICE_UP:
  4063. if (is_initial_boot) {
  4064. is_initial_boot = false;
  4065. break;
  4066. }
  4067. if (!spdev)
  4068. return -EINVAL;
  4069. card = platform_get_drvdata(spdev);
  4070. rtd = snd_soc_get_pcm_runtime(card, be_dl_name);
  4071. if (!rtd) {
  4072. dev_err(card->dev,
  4073. "%s: snd_soc_get_pcm_runtime for %s failed!\n",
  4074. __func__, be_dl_name);
  4075. ret = -EINVAL;
  4076. goto err;
  4077. }
  4078. codec = rtd->codec;
  4079. ret = msm_adsp_power_up_config(codec, card->snd_card);
  4080. if (ret < 0) {
  4081. dev_err(card->dev,
  4082. "%s: msm_adsp_power_up_config failed ret = %d!\n",
  4083. __func__, ret);
  4084. goto err;
  4085. }
  4086. break;
  4087. default:
  4088. break;
  4089. }
  4090. err:
  4091. return NOTIFY_OK;
  4092. }
  4093. static struct notifier_block service_nb = {
  4094. .notifier_call = qcs405_notifier_service_cb,
  4095. .priority = -INT_MAX,
  4096. };
  4097. static int msm_audrx_init(struct snd_soc_pcm_runtime *rtd)
  4098. {
  4099. int ret = 0;
  4100. void *config_data;
  4101. struct snd_soc_codec *codec = rtd->codec;
  4102. struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
  4103. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4104. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4105. struct snd_card *card;
  4106. struct msm_asoc_mach_data *pdata =
  4107. snd_soc_card_get_drvdata(rtd->card);
  4108. /*
  4109. * Codec SLIMBUS configuration
  4110. * RX1, RX2, RX3, RX4, RX5, RX6, RX7, RX8
  4111. * TX1, TX2, TX3, TX4, TX5, TX6, TX7, TX8, TX9, TX10, TX11, TX12, TX13
  4112. * TX14, TX15, TX16
  4113. */
  4114. unsigned int rx_ch[TASHA_RX_MAX] = {144, 145, 146, 147, 148, 149, 150,
  4115. 151, 152, 153, 154, 155, 156};
  4116. unsigned int tx_ch[TASHA_TX_MAX] = {128, 129, 130, 131, 132, 133,
  4117. 134, 135, 136, 137, 138, 139,
  4118. 140, 141, 142, 143};
  4119. pr_info("%s: dev_name:%s\n", __func__, dev_name(cpu_dai->dev));
  4120. rtd->pmdown_time = 0;
  4121. ret = snd_soc_add_codec_controls(codec, msm_snd_sb_controls,
  4122. ARRAY_SIZE(msm_snd_sb_controls));
  4123. if (ret < 0) {
  4124. pr_err("%s: add_codec_controls failed, err %d\n",
  4125. __func__, ret);
  4126. return ret;
  4127. }
  4128. snd_soc_dapm_new_controls(dapm, msm_dapm_widgets,
  4129. ARRAY_SIZE(msm_dapm_widgets));
  4130. snd_soc_dapm_add_routes(dapm, wcd_audio_paths,
  4131. ARRAY_SIZE(wcd_audio_paths));
  4132. snd_soc_dapm_ignore_suspend(dapm, "LINEOUT1");
  4133. snd_soc_dapm_ignore_suspend(dapm, "LINEOUT2");
  4134. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic3");
  4135. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic4");
  4136. snd_soc_dapm_sync(dapm);
  4137. snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  4138. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  4139. msm_codec_fn.get_afe_config_fn = tasha_get_afe_config;
  4140. ret = msm_adsp_power_up_config(codec, rtd->card->snd_card);
  4141. if (ret) {
  4142. dev_err(codec->dev, "%s: Failed to set AFE config %d\n",
  4143. __func__, ret);
  4144. goto err;
  4145. }
  4146. config_data = msm_codec_fn.get_afe_config_fn(codec,
  4147. AFE_AANC_VERSION);
  4148. if (config_data) {
  4149. ret = afe_set_config(AFE_AANC_VERSION, config_data, 0);
  4150. if (ret) {
  4151. dev_err(codec->dev, "%s: Failed to set aanc version %d\n",
  4152. __func__, ret);
  4153. goto err;
  4154. }
  4155. }
  4156. card = rtd->card->snd_card;
  4157. if (!pdata->codec_root)
  4158. pdata->codec_root = snd_info_create_subdir(card->module,
  4159. "codecs", card->proc_root);
  4160. if (!pdata->codec_root) {
  4161. dev_dbg(codec->dev, "%s: Cannot create codecs module entry\n",
  4162. __func__);
  4163. ret = 0;
  4164. goto err;
  4165. }
  4166. tasha_codec_info_create_codec_entry(pdata->codec_root, codec);
  4167. codec_reg_done = true;
  4168. return 0;
  4169. err:
  4170. return ret;
  4171. }
  4172. static int msm_va_cdc_dma_init(struct snd_soc_pcm_runtime *rtd)
  4173. {
  4174. int ret = 0;
  4175. struct snd_soc_codec *codec = rtd->codec;
  4176. struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
  4177. struct snd_card *card;
  4178. struct msm_asoc_mach_data *pdata =
  4179. snd_soc_card_get_drvdata(rtd->card);
  4180. ret = snd_soc_add_codec_controls(codec, msm_snd_va_controls,
  4181. ARRAY_SIZE(msm_snd_va_controls));
  4182. if (ret < 0) {
  4183. dev_err(codec->dev, "%s: add_codec_controls for va failed, err %d\n",
  4184. __func__, ret);
  4185. return ret;
  4186. }
  4187. snd_soc_dapm_new_controls(dapm, msm_va_dapm_widgets,
  4188. ARRAY_SIZE(msm_va_dapm_widgets));
  4189. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic0");
  4190. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic1");
  4191. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic2");
  4192. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic3");
  4193. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic4");
  4194. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic5");
  4195. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic6");
  4196. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic7");
  4197. snd_soc_dapm_sync(dapm);
  4198. card = rtd->card->snd_card;
  4199. if (!pdata->codec_root)
  4200. pdata->codec_root = snd_info_create_subdir(card->module,
  4201. "codecs", card->proc_root);
  4202. if (!pdata->codec_root) {
  4203. dev_dbg(codec->dev, "%s: Cannot create codecs module entry\n",
  4204. __func__);
  4205. ret = 0;
  4206. goto done;
  4207. }
  4208. bolero_info_create_codec_entry(pdata->codec_root, codec);
  4209. done:
  4210. return ret;
  4211. }
  4212. static int msm_wsa_cdc_dma_init(struct snd_soc_pcm_runtime *rtd)
  4213. {
  4214. int ret = 0;
  4215. struct snd_soc_codec *codec = rtd->codec;
  4216. struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
  4217. struct snd_soc_component *aux_comp;
  4218. struct snd_card *card;
  4219. struct msm_asoc_mach_data *pdata =
  4220. snd_soc_card_get_drvdata(rtd->card);
  4221. ret = snd_soc_add_codec_controls(codec, msm_snd_wsa_controls,
  4222. ARRAY_SIZE(msm_snd_wsa_controls));
  4223. if (ret < 0) {
  4224. dev_err(codec->dev, "%s: add_codec_controls for wsa failed, err %d\n",
  4225. __func__, ret);
  4226. return ret;
  4227. }
  4228. snd_soc_dapm_new_controls(dapm, msm_wsa_dapm_widgets,
  4229. ARRAY_SIZE(msm_wsa_dapm_widgets));
  4230. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK1 OUT");
  4231. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK2 OUT");
  4232. snd_soc_dapm_ignore_suspend(dapm, "WSA AIF VI");
  4233. snd_soc_dapm_ignore_suspend(dapm, "VIINPUT_WSA");
  4234. snd_soc_dapm_sync(dapm);
  4235. /*
  4236. * Send speaker configuration only for WSA8810.
  4237. * Default configuration is for WSA8815.
  4238. */
  4239. dev_dbg(codec->dev, "%s: Number of aux devices: %d\n",
  4240. __func__, rtd->card->num_aux_devs);
  4241. if (rtd->card->num_aux_devs &&
  4242. !list_empty(&rtd->card->component_dev_list)) {
  4243. aux_comp = list_first_entry(
  4244. &rtd->card->component_dev_list,
  4245. struct snd_soc_component,
  4246. card_aux_list);
  4247. if (!strcmp(aux_comp->name, WSA8810_NAME_1) ||
  4248. !strcmp(aux_comp->name, WSA8810_NAME_2)) {
  4249. wsa_macro_set_spkr_mode(rtd->codec,
  4250. WSA_MACRO_SPKR_MODE_1);
  4251. wsa_macro_set_spkr_gain_offset(rtd->codec,
  4252. WSA_MACRO_GAIN_OFFSET_M1P5_DB);
  4253. }
  4254. }
  4255. card = rtd->card->snd_card;
  4256. if (!pdata->codec_root)
  4257. pdata->codec_root = snd_info_create_subdir(card->module,
  4258. "codecs", card->proc_root);
  4259. if (!pdata->codec_root) {
  4260. dev_dbg(codec->dev, "%s: Cannot create codecs module entry\n",
  4261. __func__);
  4262. ret = 0;
  4263. goto done;
  4264. }
  4265. bolero_info_create_codec_entry(pdata->codec_root, codec);
  4266. done:
  4267. return ret;
  4268. }
  4269. static int msm_wcn_init(struct snd_soc_pcm_runtime *rtd)
  4270. {
  4271. unsigned int rx_ch[WCN_CDC_SLIM_RX_CH_MAX] = {157, 158};
  4272. unsigned int tx_ch[WCN_CDC_SLIM_TX_CH_MAX] = {159, 160, 161};
  4273. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4274. return snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  4275. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  4276. }
  4277. static int msm_snd_hw_params(struct snd_pcm_substream *substream,
  4278. struct snd_pcm_hw_params *params)
  4279. {
  4280. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4281. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4282. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4283. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4284. int ret = 0;
  4285. u32 rx_ch[SLIM_MAX_RX_PORTS], tx_ch[SLIM_MAX_TX_PORTS];
  4286. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4287. u32 user_set_tx_ch = 0;
  4288. u32 rx_ch_count;
  4289. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4290. ret = snd_soc_dai_get_channel_map(codec_dai,
  4291. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4292. if (ret < 0) {
  4293. pr_err("%s: failed to get codec chan map, err:%d\n",
  4294. __func__, ret);
  4295. goto err;
  4296. }
  4297. if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_5_RX) {
  4298. pr_debug("%s: rx_5_ch=%d\n", __func__,
  4299. slim_rx_cfg[5].channels);
  4300. rx_ch_count = slim_rx_cfg[5].channels;
  4301. } else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_2_RX) {
  4302. pr_debug("%s: rx_2_ch=%d\n", __func__,
  4303. slim_rx_cfg[2].channels);
  4304. rx_ch_count = slim_rx_cfg[2].channels;
  4305. } else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_6_RX) {
  4306. pr_debug("%s: rx_6_ch=%d\n", __func__,
  4307. slim_rx_cfg[6].channels);
  4308. rx_ch_count = slim_rx_cfg[6].channels;
  4309. } else {
  4310. pr_debug("%s: rx_0_ch=%d\n", __func__,
  4311. slim_rx_cfg[0].channels);
  4312. rx_ch_count = slim_rx_cfg[0].channels;
  4313. }
  4314. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  4315. rx_ch_count, rx_ch);
  4316. if (ret < 0) {
  4317. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4318. __func__, ret);
  4319. goto err;
  4320. }
  4321. } else {
  4322. pr_debug("%s: %s_tx_dai_id_%d_ch=%d\n", __func__,
  4323. codec_dai->name, codec_dai->id, user_set_tx_ch);
  4324. ret = snd_soc_dai_get_channel_map(codec_dai,
  4325. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4326. if (ret < 0) {
  4327. pr_err("%s: failed to get tx codec chan map, err:%d\n",
  4328. __func__, ret);
  4329. goto err;
  4330. }
  4331. /* For <codec>_tx1 case */
  4332. if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_0_TX)
  4333. user_set_tx_ch = slim_tx_cfg[0].channels;
  4334. /* For <codec>_tx3 case */
  4335. else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_1_TX)
  4336. user_set_tx_ch = slim_tx_cfg[1].channels;
  4337. else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_4_TX)
  4338. user_set_tx_ch = msm_vi_feed_tx_ch;
  4339. else
  4340. user_set_tx_ch = tx_ch_cnt;
  4341. pr_debug("%s: msm_slim_0_tx_ch(%d) user_set_tx_ch(%d) tx_ch_cnt(%d), BE id (%d)\n",
  4342. __func__, slim_tx_cfg[0].channels, user_set_tx_ch,
  4343. tx_ch_cnt, dai_link->id);
  4344. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4345. user_set_tx_ch, tx_ch, 0, 0);
  4346. if (ret < 0)
  4347. pr_err("%s: failed to set tx cpu chan map, err:%d\n",
  4348. __func__, ret);
  4349. }
  4350. err:
  4351. return ret;
  4352. }
  4353. static int msm_snd_cdc_dma_hw_params(struct snd_pcm_substream *substream,
  4354. struct snd_pcm_hw_params *params)
  4355. {
  4356. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4357. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4358. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4359. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4360. int ret = 0;
  4361. u32 rx_ch_cdc_dma, tx_ch_cdc_dma;
  4362. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4363. u32 user_set_tx_ch = 0;
  4364. u32 user_set_rx_ch = 0;
  4365. u32 ch_id;
  4366. ret = snd_soc_dai_get_channel_map(codec_dai,
  4367. &tx_ch_cnt, &tx_ch_cdc_dma, &rx_ch_cnt,
  4368. &rx_ch_cdc_dma);
  4369. if (ret < 0) {
  4370. pr_err("%s: failed to get codec chan map, err:%d\n",
  4371. __func__, ret);
  4372. goto err;
  4373. }
  4374. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4375. switch (dai_link->id) {
  4376. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  4377. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  4378. {
  4379. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  4380. pr_debug("%s: id %d rx_ch=%d\n", __func__,
  4381. ch_id, cdc_dma_rx_cfg[ch_id].channels);
  4382. user_set_rx_ch = cdc_dma_rx_cfg[ch_id].channels;
  4383. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  4384. user_set_rx_ch, &rx_ch_cdc_dma);
  4385. if (ret < 0) {
  4386. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4387. __func__, ret);
  4388. goto err;
  4389. }
  4390. }
  4391. break;
  4392. }
  4393. } else {
  4394. switch (dai_link->id) {
  4395. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  4396. {
  4397. user_set_tx_ch = msm_vi_feed_tx_ch;
  4398. }
  4399. break;
  4400. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  4401. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  4402. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  4403. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  4404. {
  4405. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  4406. pr_debug("%s: id %d tx_ch=%d\n", __func__,
  4407. ch_id, cdc_dma_tx_cfg[ch_id].channels);
  4408. user_set_tx_ch = cdc_dma_tx_cfg[ch_id].channels;
  4409. }
  4410. break;
  4411. }
  4412. ret = snd_soc_dai_set_channel_map(cpu_dai, user_set_tx_ch,
  4413. &tx_ch_cdc_dma, 0, 0);
  4414. if (ret < 0) {
  4415. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4416. __func__, ret);
  4417. goto err;
  4418. }
  4419. }
  4420. err:
  4421. return ret;
  4422. }
  4423. static int msm_wcn_hw_params(struct snd_pcm_substream *substream,
  4424. struct snd_pcm_hw_params *params)
  4425. {
  4426. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4427. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4428. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4429. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4430. u32 rx_ch[WCN_CDC_SLIM_RX_CH_MAX], tx_ch[WCN_CDC_SLIM_TX_CH_MAX];
  4431. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4432. int ret;
  4433. dev_dbg(rtd->dev, "%s: %s_tx_dai_id_%d\n", __func__,
  4434. codec_dai->name, codec_dai->id);
  4435. ret = snd_soc_dai_get_channel_map(codec_dai,
  4436. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4437. if (ret) {
  4438. dev_err(rtd->dev,
  4439. "%s: failed to get BTFM codec chan map\n, err:%d\n",
  4440. __func__, ret);
  4441. goto err;
  4442. }
  4443. dev_dbg(rtd->dev, "%s: tx_ch_cnt(%d) BE id %d\n",
  4444. __func__, tx_ch_cnt, dai_link->id);
  4445. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4446. tx_ch_cnt, tx_ch, rx_ch_cnt, rx_ch);
  4447. if (ret)
  4448. dev_err(rtd->dev, "%s: failed to set cpu chan map, err:%d\n",
  4449. __func__, ret);
  4450. err:
  4451. return ret;
  4452. }
  4453. static int msm_get_port_id(int be_id)
  4454. {
  4455. int afe_port_id;
  4456. switch (be_id) {
  4457. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  4458. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX;
  4459. break;
  4460. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  4461. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX;
  4462. break;
  4463. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  4464. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_RX;
  4465. break;
  4466. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  4467. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX;
  4468. break;
  4469. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  4470. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_RX;
  4471. break;
  4472. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  4473. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX;
  4474. break;
  4475. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  4476. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_RX;
  4477. break;
  4478. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  4479. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_TX;
  4480. break;
  4481. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  4482. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_RX;
  4483. break;
  4484. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  4485. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  4486. break;
  4487. case MSM_BACKEND_DAI_SENARY_MI2S_RX:
  4488. afe_port_id = AFE_PORT_ID_SENARY_MI2S_RX;
  4489. break;
  4490. case MSM_BACKEND_DAI_SENARY_MI2S_TX:
  4491. afe_port_id = AFE_PORT_ID_SENARY_MI2S_TX;
  4492. break;
  4493. default:
  4494. pr_err("%s: Invalid BE id: %d\n", __func__, be_id);
  4495. afe_port_id = -EINVAL;
  4496. }
  4497. return afe_port_id;
  4498. }
  4499. static u32 get_mi2s_bits_per_sample(u32 bit_format)
  4500. {
  4501. u32 bit_per_sample;
  4502. switch (bit_format) {
  4503. case SNDRV_PCM_FORMAT_S32_LE:
  4504. case SNDRV_PCM_FORMAT_S24_3LE:
  4505. case SNDRV_PCM_FORMAT_S24_LE:
  4506. bit_per_sample = 32;
  4507. break;
  4508. case SNDRV_PCM_FORMAT_S16_LE:
  4509. default:
  4510. bit_per_sample = 16;
  4511. break;
  4512. }
  4513. return bit_per_sample;
  4514. }
  4515. static void update_mi2s_clk_val(int dai_id, int stream)
  4516. {
  4517. u32 bit_per_sample;
  4518. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4519. bit_per_sample =
  4520. get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format);
  4521. mi2s_clk[dai_id].clk_freq_in_hz =
  4522. mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  4523. } else {
  4524. bit_per_sample =
  4525. get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format);
  4526. mi2s_clk[dai_id].clk_freq_in_hz =
  4527. mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  4528. }
  4529. }
  4530. static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable)
  4531. {
  4532. int ret = 0;
  4533. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4534. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4535. int port_id = 0;
  4536. int index = cpu_dai->id;
  4537. port_id = msm_get_port_id(rtd->dai_link->id);
  4538. if (port_id < 0) {
  4539. dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__);
  4540. ret = port_id;
  4541. goto err;
  4542. }
  4543. if (enable) {
  4544. update_mi2s_clk_val(index, substream->stream);
  4545. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  4546. mi2s_clk[index].clk_freq_in_hz);
  4547. }
  4548. mi2s_clk[index].enable = enable;
  4549. ret = afe_set_lpass_clock_v2(port_id,
  4550. &mi2s_clk[index]);
  4551. if (ret < 0) {
  4552. dev_err(rtd->card->dev,
  4553. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  4554. __func__, port_id, ret);
  4555. goto err;
  4556. }
  4557. err:
  4558. return ret;
  4559. }
  4560. static int msm_tdm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  4561. struct snd_pcm_hw_params *params)
  4562. {
  4563. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4564. struct snd_interval *rate = hw_param_interval(params,
  4565. SNDRV_PCM_HW_PARAM_RATE);
  4566. struct snd_interval *channels = hw_param_interval(params,
  4567. SNDRV_PCM_HW_PARAM_CHANNELS);
  4568. if (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) {
  4569. channels->min = channels->max =
  4570. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  4571. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4572. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  4573. rate->min = rate->max =
  4574. tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  4575. } else if (cpu_dai->id == AFE_PORT_ID_SECONDARY_TDM_RX) {
  4576. channels->min = channels->max =
  4577. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  4578. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4579. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  4580. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  4581. } else if (cpu_dai->id == AFE_PORT_ID_QUINARY_TDM_RX) {
  4582. channels->min = channels->max =
  4583. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  4584. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4585. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  4586. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  4587. } else {
  4588. pr_err("%s: dai id 0x%x not supported\n",
  4589. __func__, cpu_dai->id);
  4590. return -EINVAL;
  4591. }
  4592. pr_debug("%s: dai id = 0x%x channels = %d rate = %d format = 0x%x\n",
  4593. __func__, cpu_dai->id, channels->max, rate->max,
  4594. params_format(params));
  4595. return 0;
  4596. }
  4597. static int qcs405_tdm_snd_hw_params(struct snd_pcm_substream *substream,
  4598. struct snd_pcm_hw_params *params)
  4599. {
  4600. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4601. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4602. int ret = 0;
  4603. int slot_width = 32;
  4604. int channels, slots = 8;
  4605. unsigned int slot_mask, rate, clk_freq;
  4606. unsigned int slot_offset[8] = {0, 4, 8, 12, 16, 20, 24, 28};
  4607. pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id);
  4608. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  4609. switch (cpu_dai->id) {
  4610. case AFE_PORT_ID_PRIMARY_TDM_RX:
  4611. channels = tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  4612. break;
  4613. case AFE_PORT_ID_SECONDARY_TDM_RX:
  4614. channels = tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  4615. break;
  4616. case AFE_PORT_ID_TERTIARY_TDM_RX:
  4617. channels = tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  4618. break;
  4619. case AFE_PORT_ID_QUATERNARY_TDM_RX:
  4620. channels = tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  4621. break;
  4622. case AFE_PORT_ID_QUINARY_TDM_RX:
  4623. channels = tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  4624. break;
  4625. case AFE_PORT_ID_PRIMARY_TDM_TX:
  4626. channels = tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  4627. break;
  4628. case AFE_PORT_ID_SECONDARY_TDM_TX:
  4629. channels = tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  4630. break;
  4631. case AFE_PORT_ID_TERTIARY_TDM_TX:
  4632. channels = tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  4633. break;
  4634. case AFE_PORT_ID_QUATERNARY_TDM_TX:
  4635. channels = tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  4636. break;
  4637. case AFE_PORT_ID_QUINARY_TDM_TX:
  4638. channels = tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  4639. break;
  4640. default:
  4641. pr_err("%s: dai id 0x%x not supported\n",
  4642. __func__, cpu_dai->id);
  4643. return -EINVAL;
  4644. }
  4645. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4646. /*2 slot config - bits 0 and 1 set for the first two slots */
  4647. slot_mask = 0x0000FFFF >> (16-channels);
  4648. pr_debug("%s: tdm rx slot_width %d slots %d\n",
  4649. __func__, slot_width, slots);
  4650. ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, slot_mask,
  4651. slots, slot_width);
  4652. if (ret < 0) {
  4653. pr_err("%s: failed to set tdm rx slot, err:%d\n",
  4654. __func__, ret);
  4655. goto end;
  4656. }
  4657. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4658. 0, NULL, channels, slot_offset);
  4659. if (ret < 0) {
  4660. pr_err("%s: failed to set tdm rx channel map, err:%d\n",
  4661. __func__, ret);
  4662. goto end;
  4663. }
  4664. } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  4665. /*2 slot config - bits 0 and 1 set for the first two slots */
  4666. slot_mask = 0x0000FFFF >> (16-channels);
  4667. pr_debug("%s: tdm tx slot_width %d slots %d\n",
  4668. __func__, slot_width, slots);
  4669. ret = snd_soc_dai_set_tdm_slot(cpu_dai, slot_mask, 0,
  4670. slots, slot_width);
  4671. if (ret < 0) {
  4672. pr_err("%s: failed to set tdm tx slot, err:%d\n",
  4673. __func__, ret);
  4674. goto end;
  4675. }
  4676. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4677. channels, slot_offset, 0, NULL);
  4678. if (ret < 0) {
  4679. pr_err("%s: failed to set tdm tx channel map, err:%d\n",
  4680. __func__, ret);
  4681. goto end;
  4682. }
  4683. } else {
  4684. ret = -EINVAL;
  4685. pr_err("%s: invalid use case, err:%d\n",
  4686. __func__, ret);
  4687. goto end;
  4688. }
  4689. rate = params_rate(params);
  4690. clk_freq = rate * slot_width * slots;
  4691. ret = snd_soc_dai_set_sysclk(cpu_dai, 0, clk_freq, SND_SOC_CLOCK_OUT);
  4692. if (ret < 0)
  4693. pr_err("%s: failed to set tdm clk, err:%d\n",
  4694. __func__, ret);
  4695. end:
  4696. return ret;
  4697. }
  4698. static int msm_get_tdm_mode(u32 port_id)
  4699. {
  4700. u32 tdm_mode;
  4701. switch (port_id) {
  4702. case AFE_PORT_ID_PRIMARY_TDM_RX:
  4703. case AFE_PORT_ID_PRIMARY_TDM_TX:
  4704. tdm_mode = TDM_PRI;
  4705. break;
  4706. case AFE_PORT_ID_SECONDARY_TDM_RX:
  4707. case AFE_PORT_ID_SECONDARY_TDM_TX:
  4708. tdm_mode = TDM_SEC;
  4709. break;
  4710. case AFE_PORT_ID_TERTIARY_TDM_RX:
  4711. case AFE_PORT_ID_TERTIARY_TDM_TX:
  4712. tdm_mode = TDM_TERT;
  4713. break;
  4714. case AFE_PORT_ID_QUATERNARY_TDM_RX:
  4715. case AFE_PORT_ID_QUATERNARY_TDM_TX:
  4716. tdm_mode = TDM_QUAT;
  4717. break;
  4718. case AFE_PORT_ID_QUINARY_TDM_RX:
  4719. case AFE_PORT_ID_QUINARY_TDM_TX:
  4720. tdm_mode = TDM_QUIN;
  4721. break;
  4722. default:
  4723. pr_err("%s: Invalid port id: %d\n", __func__, port_id);
  4724. tdm_mode = -EINVAL;
  4725. }
  4726. return tdm_mode;
  4727. }
  4728. static int qcs405_tdm_snd_startup(struct snd_pcm_substream *substream)
  4729. {
  4730. int ret = 0;
  4731. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4732. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4733. struct snd_soc_card *card = rtd->card;
  4734. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4735. u32 tdm_mode = msm_get_tdm_mode(cpu_dai->id);
  4736. if (tdm_mode >= TDM_INTERFACE_MAX) {
  4737. ret = -EINVAL;
  4738. pr_err("%s: Invalid TDM interface %d\n",
  4739. __func__, ret);
  4740. return ret;
  4741. }
  4742. if (pdata->mi2s_gpio_p[tdm_mode]) {
  4743. ret = msm_cdc_pinctrl_select_active_state(
  4744. pdata->mi2s_gpio_p[tdm_mode]);
  4745. if (ret)
  4746. pr_err("%s: TDM GPIO pinctrl set active failed with %d\n",
  4747. __func__, ret);
  4748. }
  4749. /* Enable Mic bias for TDM Mics */
  4750. if (cpu_dai->id == AFE_PORT_ID_QUINARY_TDM_TX) {
  4751. if (pdata->tdm_micb_supply) {
  4752. ret = regulator_set_voltage(pdata->tdm_micb_supply,
  4753. pdata->tdm_micb_voltage,
  4754. pdata->tdm_micb_voltage);
  4755. if (ret) {
  4756. pr_err("%s: Setting voltage failed, err = %d\n",
  4757. __func__, ret);
  4758. return ret;
  4759. }
  4760. ret = regulator_set_load(pdata->tdm_micb_supply,
  4761. pdata->tdm_micb_current);
  4762. if (ret) {
  4763. pr_err("%s: Setting current failed, err = %d\n",
  4764. __func__, ret);
  4765. return ret;
  4766. }
  4767. ret = regulator_enable(pdata->tdm_micb_supply);
  4768. if (ret) {
  4769. pr_err("%s: regulator enable failed, err = %d\n",
  4770. __func__, ret);
  4771. return ret;
  4772. }
  4773. }
  4774. }
  4775. return ret;
  4776. }
  4777. static void qcs405_tdm_snd_shutdown(struct snd_pcm_substream *substream)
  4778. {
  4779. int ret = 0;
  4780. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4781. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4782. struct snd_soc_card *card = rtd->card;
  4783. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4784. u32 tdm_mode = msm_get_tdm_mode(cpu_dai->id);
  4785. if (cpu_dai->id == AFE_PORT_ID_QUINARY_TDM_TX) {
  4786. if (pdata->tdm_micb_supply) {
  4787. ret = regulator_disable(pdata->tdm_micb_supply);
  4788. if (ret)
  4789. pr_err("%s: regulator disable failed, err = %d\n",
  4790. __func__, ret);
  4791. regulator_set_voltage(pdata->tdm_micb_supply, 0,
  4792. pdata->tdm_micb_voltage);
  4793. regulator_set_load(pdata->tdm_micb_supply, 0);
  4794. }
  4795. }
  4796. if (pdata->mi2s_gpio_p[tdm_mode]) {
  4797. ret = msm_cdc_pinctrl_select_sleep_state(
  4798. pdata->mi2s_gpio_p[tdm_mode]);
  4799. if (ret)
  4800. pr_err("%s: TDM GPIO pinctrl set sleep failed with %d\n",
  4801. __func__, ret);
  4802. }
  4803. }
  4804. static struct snd_soc_ops qcs405_tdm_be_ops = {
  4805. .hw_params = qcs405_tdm_snd_hw_params,
  4806. .startup = qcs405_tdm_snd_startup,
  4807. .shutdown = qcs405_tdm_snd_shutdown
  4808. };
  4809. static int msm_fe_qos_prepare(struct snd_pcm_substream *substream)
  4810. {
  4811. cpumask_t mask;
  4812. if (pm_qos_request_active(&substream->latency_pm_qos_req))
  4813. pm_qos_remove_request(&substream->latency_pm_qos_req);
  4814. cpumask_clear(&mask);
  4815. cpumask_set_cpu(1, &mask); /* affine to core 1 */
  4816. cpumask_set_cpu(2, &mask); /* affine to core 2 */
  4817. cpumask_copy(&substream->latency_pm_qos_req.cpus_affine, &mask);
  4818. substream->latency_pm_qos_req.type = PM_QOS_REQ_AFFINE_CORES;
  4819. pm_qos_add_request(&substream->latency_pm_qos_req,
  4820. PM_QOS_CPU_DMA_LATENCY,
  4821. MSM_LL_QOS_VALUE);
  4822. return 0;
  4823. }
  4824. static struct snd_soc_ops msm_fe_qos_ops = {
  4825. .prepare = msm_fe_qos_prepare,
  4826. };
  4827. static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
  4828. {
  4829. int ret = 0;
  4830. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4831. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4832. int index = cpu_dai->id;
  4833. unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
  4834. struct snd_soc_card *card = rtd->card;
  4835. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4836. dev_dbg(rtd->card->dev,
  4837. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  4838. __func__, substream->name, substream->stream,
  4839. cpu_dai->name, cpu_dai->id);
  4840. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  4841. ret = -EINVAL;
  4842. dev_err(rtd->card->dev,
  4843. "%s: CPU DAI id (%d) out of range\n",
  4844. __func__, cpu_dai->id);
  4845. goto err;
  4846. }
  4847. /*
  4848. * Mutex protection in case the same MI2S
  4849. * interface using for both TX and RX so
  4850. * that the same clock won't be enable twice.
  4851. */
  4852. mutex_lock(&mi2s_intf_conf[index].lock);
  4853. if (++mi2s_intf_conf[index].ref_cnt == 1) {
  4854. /* Check if msm needs to provide the clock to the interface */
  4855. if (!mi2s_intf_conf[index].msm_is_mi2s_master) {
  4856. mi2s_clk[index].clk_id = mi2s_ebit_clk[index];
  4857. fmt = SND_SOC_DAIFMT_CBM_CFM;
  4858. }
  4859. ret = msm_mi2s_set_sclk(substream, true);
  4860. if (ret < 0) {
  4861. dev_err(rtd->card->dev,
  4862. "%s: afe lpass clock failed to enable MI2S clock, err:%d\n",
  4863. __func__, ret);
  4864. goto clean_up;
  4865. }
  4866. ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
  4867. if (ret < 0) {
  4868. pr_err("%s: set fmt cpu dai failed for MI2S (%d), err:%d\n",
  4869. __func__, index, ret);
  4870. goto clk_off;
  4871. }
  4872. if (pdata->mi2s_gpio_p[index])
  4873. msm_cdc_pinctrl_select_active_state(
  4874. pdata->mi2s_gpio_p[index]);
  4875. }
  4876. clk_off:
  4877. if (ret < 0)
  4878. msm_mi2s_set_sclk(substream, false);
  4879. clean_up:
  4880. if (ret < 0)
  4881. mi2s_intf_conf[index].ref_cnt--;
  4882. mutex_unlock(&mi2s_intf_conf[index].lock);
  4883. err:
  4884. return ret;
  4885. }
  4886. static void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
  4887. {
  4888. int ret;
  4889. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4890. int index = rtd->cpu_dai->id;
  4891. struct snd_soc_card *card = rtd->card;
  4892. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4893. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  4894. substream->name, substream->stream);
  4895. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  4896. pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index);
  4897. return;
  4898. }
  4899. mutex_lock(&mi2s_intf_conf[index].lock);
  4900. if (--mi2s_intf_conf[index].ref_cnt == 0) {
  4901. if (pdata->mi2s_gpio_p[index])
  4902. msm_cdc_pinctrl_select_sleep_state(
  4903. pdata->mi2s_gpio_p[index]);
  4904. ret = msm_mi2s_set_sclk(substream, false);
  4905. if (ret < 0)
  4906. pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n",
  4907. __func__, index, ret);
  4908. }
  4909. mutex_unlock(&mi2s_intf_conf[index].lock);
  4910. }
  4911. static int msm_spdif_set_clk(struct snd_pcm_substream *substream, bool enable)
  4912. {
  4913. int ret = 0;
  4914. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4915. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4916. int port_id = cpu_dai->id;
  4917. struct afe_clk_set clk_cfg;
  4918. clk_cfg.clk_set_minor_version = Q6AFE_LPASS_CLK_CONFIG_API_VERSION;
  4919. clk_cfg.clk_attri = Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO;
  4920. clk_cfg.clk_root = Q6AFE_LPASS_CLK_ROOT_DEFAULT;
  4921. clk_cfg.enable = enable;
  4922. /* Set core clock (based on sample rate for RX, fixed for TX) */
  4923. switch (port_id) {
  4924. case AFE_PORT_ID_PRIMARY_SPDIF_RX:
  4925. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_OUTPUT_CORE;
  4926. /* rate x 2ch x 2_for_biphase_coding x 32_bits_per_sample */
  4927. clk_cfg.clk_freq_in_hz =
  4928. spdif_rx_cfg[PRIM_SPDIF_RX].sample_rate * 2 * 2 * 32;
  4929. break;
  4930. case AFE_PORT_ID_SECONDARY_SPDIF_RX:
  4931. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_OUTPUT_CORE;
  4932. clk_cfg.clk_freq_in_hz =
  4933. spdif_rx_cfg[SEC_SPDIF_RX].sample_rate * 2 * 2 * 32;
  4934. break;
  4935. case AFE_PORT_ID_PRIMARY_SPDIF_TX:
  4936. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_INPUT_CORE;
  4937. clk_cfg.clk_freq_in_hz = SPDIF_TX_CORE_CLK_163_P84_MHZ;
  4938. break;
  4939. case AFE_PORT_ID_SECONDARY_SPDIF_TX:
  4940. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_INPUT_CORE;
  4941. clk_cfg.clk_freq_in_hz = SPDIF_TX_CORE_CLK_163_P84_MHZ;
  4942. break;
  4943. }
  4944. ret = afe_set_lpass_clock_v2(port_id, &clk_cfg);
  4945. if (ret < 0) {
  4946. dev_err(rtd->card->dev,
  4947. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  4948. __func__, port_id, ret);
  4949. goto err;
  4950. }
  4951. /* Set NPL clock for RX in addition */
  4952. switch (port_id) {
  4953. case AFE_PORT_ID_PRIMARY_SPDIF_RX:
  4954. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_OUTPUT_NPL;
  4955. ret = afe_set_lpass_clock_v2(port_id, &clk_cfg);
  4956. if (ret < 0) {
  4957. dev_err(rtd->card->dev,
  4958. "%s: afe NPL failed port 0x%x, err:%d\n",
  4959. __func__, port_id, ret);
  4960. goto err;
  4961. }
  4962. break;
  4963. case AFE_PORT_ID_SECONDARY_SPDIF_RX:
  4964. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_OUTPUT_NPL;
  4965. ret = afe_set_lpass_clock_v2(port_id, &clk_cfg);
  4966. if (ret < 0) {
  4967. dev_err(rtd->card->dev,
  4968. "%s: afe NPL failed for port 0x%x, err:%d\n",
  4969. __func__, port_id, ret);
  4970. goto err;
  4971. }
  4972. break;
  4973. }
  4974. if (enable) {
  4975. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  4976. clk_cfg.clk_freq_in_hz);
  4977. }
  4978. err:
  4979. return ret;
  4980. }
  4981. static int msm_spdif_snd_startup(struct snd_pcm_substream *substream)
  4982. {
  4983. int ret = 0;
  4984. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4985. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4986. int port_id = cpu_dai->id;
  4987. dev_dbg(rtd->card->dev,
  4988. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  4989. __func__, substream->name, substream->stream,
  4990. cpu_dai->name, cpu_dai->id);
  4991. if (port_id < AFE_PORT_ID_PRIMARY_SPDIF_RX ||
  4992. port_id > AFE_PORT_ID_SECONDARY_SPDIF_TX) {
  4993. ret = -EINVAL;
  4994. dev_err(rtd->card->dev,
  4995. "%s: CPU DAI id (%d) out of range\n",
  4996. __func__, cpu_dai->id);
  4997. goto err;
  4998. }
  4999. ret = msm_spdif_set_clk(substream, true);
  5000. if (ret < 0) {
  5001. dev_err(rtd->card->dev,
  5002. "%s: afe lpass clock failed to enable (%d), err:%d\n",
  5003. __func__, port_id, ret);
  5004. }
  5005. err:
  5006. return ret;
  5007. }
  5008. static void msm_spdif_snd_shutdown(struct snd_pcm_substream *substream)
  5009. {
  5010. int ret;
  5011. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5012. int port_id = rtd->cpu_dai->id;
  5013. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  5014. substream->name, substream->stream);
  5015. if (port_id < AFE_PORT_ID_PRIMARY_SPDIF_RX ||
  5016. port_id > AFE_PORT_ID_SECONDARY_SPDIF_TX) {
  5017. pr_err("%s:invalid SPDIF DAI(%d)\n", __func__, port_id);
  5018. return;
  5019. }
  5020. ret = msm_spdif_set_clk(substream, false);
  5021. if (ret < 0)
  5022. pr_err("%s:clock disable failed for SPDIF (%d); ret=%d\n",
  5023. __func__, port_id, ret);
  5024. }
  5025. static struct snd_soc_ops msm_mi2s_be_ops = {
  5026. .startup = msm_mi2s_snd_startup,
  5027. .shutdown = msm_mi2s_snd_shutdown,
  5028. };
  5029. static struct snd_soc_ops msm_cdc_dma_be_ops = {
  5030. .hw_params = msm_snd_cdc_dma_hw_params,
  5031. };
  5032. static struct snd_soc_ops msm_be_ops = {
  5033. .hw_params = msm_snd_hw_params,
  5034. };
  5035. static struct snd_soc_ops msm_wcn_ops = {
  5036. .hw_params = msm_wcn_hw_params,
  5037. };
  5038. static struct snd_soc_ops msm_spdif_be_ops = {
  5039. .startup = msm_spdif_snd_startup,
  5040. .shutdown = msm_spdif_snd_shutdown,
  5041. };
  5042. /* Digital audio interface glue - connects codec <---> CPU */
  5043. static struct snd_soc_dai_link msm_common_dai_links[] = {
  5044. /* FrontEnd DAI Links */
  5045. {
  5046. .name = MSM_DAILINK_NAME(Media1),
  5047. .stream_name = "MultiMedia1",
  5048. .cpu_dai_name = "MultiMedia1",
  5049. .platform_name = "msm-pcm-dsp.0",
  5050. .dynamic = 1,
  5051. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  5052. .dpcm_playback = 1,
  5053. .dpcm_capture = 1,
  5054. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5055. SND_SOC_DPCM_TRIGGER_POST},
  5056. .codec_dai_name = "snd-soc-dummy-dai",
  5057. .codec_name = "snd-soc-dummy",
  5058. .ignore_suspend = 1,
  5059. /* this dainlink has playback support */
  5060. .ignore_pmdown_time = 1,
  5061. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  5062. },
  5063. {
  5064. .name = MSM_DAILINK_NAME(Media2),
  5065. .stream_name = "MultiMedia2",
  5066. .cpu_dai_name = "MultiMedia2",
  5067. .platform_name = "msm-pcm-dsp.0",
  5068. .dynamic = 1,
  5069. .dpcm_playback = 1,
  5070. .dpcm_capture = 1,
  5071. .codec_dai_name = "snd-soc-dummy-dai",
  5072. .codec_name = "snd-soc-dummy",
  5073. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5074. SND_SOC_DPCM_TRIGGER_POST},
  5075. .ignore_suspend = 1,
  5076. /* this dainlink has playback support */
  5077. .ignore_pmdown_time = 1,
  5078. .id = MSM_FRONTEND_DAI_MULTIMEDIA2,
  5079. },
  5080. {
  5081. .name = "VoiceMMode1",
  5082. .stream_name = "VoiceMMode1",
  5083. .cpu_dai_name = "VoiceMMode1",
  5084. .platform_name = "msm-pcm-voice",
  5085. .dynamic = 1,
  5086. .dpcm_playback = 1,
  5087. .dpcm_capture = 1,
  5088. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5089. SND_SOC_DPCM_TRIGGER_POST},
  5090. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5091. .ignore_suspend = 1,
  5092. .ignore_pmdown_time = 1,
  5093. .codec_dai_name = "snd-soc-dummy-dai",
  5094. .codec_name = "snd-soc-dummy",
  5095. .id = MSM_FRONTEND_DAI_VOICEMMODE1,
  5096. },
  5097. {
  5098. .name = "MSM VoIP",
  5099. .stream_name = "VoIP",
  5100. .cpu_dai_name = "VoIP",
  5101. .platform_name = "msm-voip-dsp",
  5102. .dynamic = 1,
  5103. .dpcm_playback = 1,
  5104. .dpcm_capture = 1,
  5105. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5106. SND_SOC_DPCM_TRIGGER_POST},
  5107. .codec_dai_name = "snd-soc-dummy-dai",
  5108. .codec_name = "snd-soc-dummy",
  5109. .ignore_suspend = 1,
  5110. /* this dainlink has playback support */
  5111. .ignore_pmdown_time = 1,
  5112. .id = MSM_FRONTEND_DAI_VOIP,
  5113. },
  5114. {
  5115. .name = MSM_DAILINK_NAME(ULL),
  5116. .stream_name = "MultiMedia3",
  5117. .cpu_dai_name = "MultiMedia3",
  5118. .platform_name = "msm-pcm-dsp.2",
  5119. .dynamic = 1,
  5120. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  5121. .dpcm_playback = 1,
  5122. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5123. SND_SOC_DPCM_TRIGGER_POST},
  5124. .codec_dai_name = "snd-soc-dummy-dai",
  5125. .codec_name = "snd-soc-dummy",
  5126. .ignore_suspend = 1,
  5127. /* this dainlink has playback support */
  5128. .ignore_pmdown_time = 1,
  5129. .id = MSM_FRONTEND_DAI_MULTIMEDIA3,
  5130. },
  5131. /* Hostless PCM purpose */
  5132. {
  5133. .name = "SLIMBUS_0 Hostless",
  5134. .stream_name = "SLIMBUS_0 Hostless",
  5135. .cpu_dai_name = "SLIMBUS0_HOSTLESS",
  5136. .platform_name = "msm-pcm-hostless",
  5137. .dynamic = 1,
  5138. .dpcm_playback = 1,
  5139. .dpcm_capture = 1,
  5140. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5141. SND_SOC_DPCM_TRIGGER_POST},
  5142. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5143. .ignore_suspend = 1,
  5144. /* this dailink has playback support */
  5145. .ignore_pmdown_time = 1,
  5146. .codec_dai_name = "snd-soc-dummy-dai",
  5147. .codec_name = "snd-soc-dummy",
  5148. },
  5149. {
  5150. .name = "MSM AFE-PCM RX",
  5151. .stream_name = "AFE-PROXY RX",
  5152. .cpu_dai_name = "msm-dai-q6-dev.241",
  5153. .codec_name = "msm-stub-codec.1",
  5154. .codec_dai_name = "msm-stub-rx",
  5155. .platform_name = "msm-pcm-afe",
  5156. .dpcm_playback = 1,
  5157. .ignore_suspend = 1,
  5158. /* this dainlink has playback support */
  5159. .ignore_pmdown_time = 1,
  5160. },
  5161. {
  5162. .name = "MSM AFE-PCM TX",
  5163. .stream_name = "AFE-PROXY TX",
  5164. .cpu_dai_name = "msm-dai-q6-dev.240",
  5165. .codec_name = "msm-stub-codec.1",
  5166. .codec_dai_name = "msm-stub-tx",
  5167. .platform_name = "msm-pcm-afe",
  5168. .dpcm_capture = 1,
  5169. .ignore_suspend = 1,
  5170. },
  5171. {
  5172. .name = MSM_DAILINK_NAME(Compress1),
  5173. .stream_name = "Compress1",
  5174. .cpu_dai_name = "MultiMedia4",
  5175. .platform_name = "msm-compress-dsp",
  5176. .dynamic = 1,
  5177. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  5178. .dpcm_playback = 1,
  5179. .dpcm_capture = 1,
  5180. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5181. SND_SOC_DPCM_TRIGGER_POST},
  5182. .codec_dai_name = "snd-soc-dummy-dai",
  5183. .codec_name = "snd-soc-dummy",
  5184. .ignore_suspend = 1,
  5185. .ignore_pmdown_time = 1,
  5186. /* this dainlink has playback support */
  5187. .id = MSM_FRONTEND_DAI_MULTIMEDIA4,
  5188. },
  5189. {
  5190. .name = "AUXPCM Hostless",
  5191. .stream_name = "AUXPCM Hostless",
  5192. .cpu_dai_name = "AUXPCM_HOSTLESS",
  5193. .platform_name = "msm-pcm-hostless",
  5194. .dynamic = 1,
  5195. .dpcm_playback = 1,
  5196. .dpcm_capture = 1,
  5197. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5198. SND_SOC_DPCM_TRIGGER_POST},
  5199. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5200. .ignore_suspend = 1,
  5201. /* this dainlink has playback support */
  5202. .ignore_pmdown_time = 1,
  5203. .codec_dai_name = "snd-soc-dummy-dai",
  5204. .codec_name = "snd-soc-dummy",
  5205. },
  5206. {
  5207. .name = "SLIMBUS_1 Hostless",
  5208. .stream_name = "SLIMBUS_1 Hostless",
  5209. .cpu_dai_name = "SLIMBUS1_HOSTLESS",
  5210. .platform_name = "msm-pcm-hostless",
  5211. .dynamic = 1,
  5212. .dpcm_playback = 1,
  5213. .dpcm_capture = 1,
  5214. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5215. SND_SOC_DPCM_TRIGGER_POST},
  5216. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5217. .ignore_suspend = 1,
  5218. /* this dailink has playback support */
  5219. .ignore_pmdown_time = 1,
  5220. .codec_dai_name = "snd-soc-dummy-dai",
  5221. .codec_name = "snd-soc-dummy",
  5222. },
  5223. {
  5224. .name = "SLIMBUS_3 Hostless",
  5225. .stream_name = "SLIMBUS_3 Hostless",
  5226. .cpu_dai_name = "SLIMBUS3_HOSTLESS",
  5227. .platform_name = "msm-pcm-hostless",
  5228. .dynamic = 1,
  5229. .dpcm_playback = 1,
  5230. .dpcm_capture = 1,
  5231. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5232. SND_SOC_DPCM_TRIGGER_POST},
  5233. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5234. .ignore_suspend = 1,
  5235. /* this dailink has playback support */
  5236. .ignore_pmdown_time = 1,
  5237. .codec_dai_name = "snd-soc-dummy-dai",
  5238. .codec_name = "snd-soc-dummy",
  5239. },
  5240. {
  5241. .name = "SLIMBUS_4 Hostless",
  5242. .stream_name = "SLIMBUS_4 Hostless",
  5243. .cpu_dai_name = "SLIMBUS4_HOSTLESS",
  5244. .platform_name = "msm-pcm-hostless",
  5245. .dynamic = 1,
  5246. .dpcm_playback = 1,
  5247. .dpcm_capture = 1,
  5248. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5249. SND_SOC_DPCM_TRIGGER_POST},
  5250. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5251. .ignore_suspend = 1,
  5252. /* this dailink has playback support */
  5253. .ignore_pmdown_time = 1,
  5254. .codec_dai_name = "snd-soc-dummy-dai",
  5255. .codec_name = "snd-soc-dummy",
  5256. },
  5257. {
  5258. .name = MSM_DAILINK_NAME(LowLatency),
  5259. .stream_name = "MultiMedia5",
  5260. .cpu_dai_name = "MultiMedia5",
  5261. .platform_name = "msm-pcm-dsp.1",
  5262. .dynamic = 1,
  5263. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  5264. .dpcm_playback = 1,
  5265. .dpcm_capture = 1,
  5266. .codec_dai_name = "snd-soc-dummy-dai",
  5267. .codec_name = "snd-soc-dummy",
  5268. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5269. SND_SOC_DPCM_TRIGGER_POST},
  5270. .ignore_suspend = 1,
  5271. /* this dainlink has playback support */
  5272. .ignore_pmdown_time = 1,
  5273. .id = MSM_FRONTEND_DAI_MULTIMEDIA5,
  5274. .ops = &msm_fe_qos_ops,
  5275. },
  5276. {
  5277. .name = "Listen 1 Audio Service",
  5278. .stream_name = "Listen 1 Audio Service",
  5279. .cpu_dai_name = "LSM1",
  5280. .platform_name = "msm-lsm-client",
  5281. .dynamic = 1,
  5282. .dpcm_capture = 1,
  5283. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5284. SND_SOC_DPCM_TRIGGER_POST },
  5285. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5286. .ignore_suspend = 1,
  5287. .codec_dai_name = "snd-soc-dummy-dai",
  5288. .codec_name = "snd-soc-dummy",
  5289. .id = MSM_FRONTEND_DAI_LSM1,
  5290. },
  5291. /* Multiple Tunnel instances */
  5292. {
  5293. .name = MSM_DAILINK_NAME(Compress2),
  5294. .stream_name = "Compress2",
  5295. .cpu_dai_name = "MultiMedia7",
  5296. .platform_name = "msm-compress-dsp",
  5297. .dynamic = 1,
  5298. .dpcm_playback = 1,
  5299. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5300. SND_SOC_DPCM_TRIGGER_POST},
  5301. .codec_dai_name = "snd-soc-dummy-dai",
  5302. .codec_name = "snd-soc-dummy",
  5303. .ignore_suspend = 1,
  5304. .ignore_pmdown_time = 1,
  5305. /* this dainlink has playback support */
  5306. .id = MSM_FRONTEND_DAI_MULTIMEDIA7,
  5307. },
  5308. {
  5309. .name = MSM_DAILINK_NAME(MultiMedia10),
  5310. .stream_name = "MultiMedia10",
  5311. .cpu_dai_name = "MultiMedia10",
  5312. .platform_name = "msm-pcm-dsp.1",
  5313. .dynamic = 1,
  5314. .dpcm_playback = 1,
  5315. .dpcm_capture = 1,
  5316. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5317. SND_SOC_DPCM_TRIGGER_POST},
  5318. .codec_dai_name = "snd-soc-dummy-dai",
  5319. .codec_name = "snd-soc-dummy",
  5320. .ignore_suspend = 1,
  5321. .ignore_pmdown_time = 1,
  5322. /* this dainlink has playback support */
  5323. .id = MSM_FRONTEND_DAI_MULTIMEDIA10,
  5324. },
  5325. {
  5326. .name = MSM_DAILINK_NAME(ULL_NOIRQ),
  5327. .stream_name = "MM_NOIRQ",
  5328. .cpu_dai_name = "MultiMedia8",
  5329. .platform_name = "msm-pcm-dsp-noirq",
  5330. .dynamic = 1,
  5331. .dpcm_playback = 1,
  5332. .dpcm_capture = 1,
  5333. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5334. SND_SOC_DPCM_TRIGGER_POST},
  5335. .codec_dai_name = "snd-soc-dummy-dai",
  5336. .codec_name = "snd-soc-dummy",
  5337. .ignore_suspend = 1,
  5338. .ignore_pmdown_time = 1,
  5339. /* this dainlink has playback support */
  5340. .id = MSM_FRONTEND_DAI_MULTIMEDIA8,
  5341. .ops = &msm_fe_qos_ops,
  5342. },
  5343. /* HDMI Hostless */
  5344. {
  5345. .name = "HDMI_RX_HOSTLESS",
  5346. .stream_name = "HDMI_RX_HOSTLESS",
  5347. .cpu_dai_name = "HDMI_HOSTLESS",
  5348. .platform_name = "msm-pcm-hostless",
  5349. .dynamic = 1,
  5350. .dpcm_playback = 1,
  5351. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5352. SND_SOC_DPCM_TRIGGER_POST},
  5353. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5354. .ignore_suspend = 1,
  5355. .ignore_pmdown_time = 1,
  5356. .codec_dai_name = "snd-soc-dummy-dai",
  5357. .codec_name = "snd-soc-dummy",
  5358. },
  5359. {
  5360. .name = "VoiceMMode2",
  5361. .stream_name = "VoiceMMode2",
  5362. .cpu_dai_name = "VoiceMMode2",
  5363. .platform_name = "msm-pcm-voice",
  5364. .dynamic = 1,
  5365. .dpcm_playback = 1,
  5366. .dpcm_capture = 1,
  5367. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5368. SND_SOC_DPCM_TRIGGER_POST},
  5369. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5370. .ignore_suspend = 1,
  5371. .ignore_pmdown_time = 1,
  5372. .codec_dai_name = "snd-soc-dummy-dai",
  5373. .codec_name = "snd-soc-dummy",
  5374. .id = MSM_FRONTEND_DAI_VOICEMMODE2,
  5375. },
  5376. /* LSM FE */
  5377. {
  5378. .name = "Listen 2 Audio Service",
  5379. .stream_name = "Listen 2 Audio Service",
  5380. .cpu_dai_name = "LSM2",
  5381. .platform_name = "msm-lsm-client",
  5382. .dynamic = 1,
  5383. .dpcm_capture = 1,
  5384. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5385. SND_SOC_DPCM_TRIGGER_POST },
  5386. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5387. .ignore_suspend = 1,
  5388. .codec_dai_name = "snd-soc-dummy-dai",
  5389. .codec_name = "snd-soc-dummy",
  5390. .id = MSM_FRONTEND_DAI_LSM2,
  5391. },
  5392. {
  5393. .name = "Listen 3 Audio Service",
  5394. .stream_name = "Listen 3 Audio Service",
  5395. .cpu_dai_name = "LSM3",
  5396. .platform_name = "msm-lsm-client",
  5397. .dynamic = 1,
  5398. .dpcm_capture = 1,
  5399. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5400. SND_SOC_DPCM_TRIGGER_POST },
  5401. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5402. .ignore_suspend = 1,
  5403. .codec_dai_name = "snd-soc-dummy-dai",
  5404. .codec_name = "snd-soc-dummy",
  5405. .id = MSM_FRONTEND_DAI_LSM3,
  5406. },
  5407. {
  5408. .name = "Listen 4 Audio Service",
  5409. .stream_name = "Listen 4 Audio Service",
  5410. .cpu_dai_name = "LSM4",
  5411. .platform_name = "msm-lsm-client",
  5412. .dynamic = 1,
  5413. .dpcm_capture = 1,
  5414. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5415. SND_SOC_DPCM_TRIGGER_POST },
  5416. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5417. .ignore_suspend = 1,
  5418. .codec_dai_name = "snd-soc-dummy-dai",
  5419. .codec_name = "snd-soc-dummy",
  5420. .id = MSM_FRONTEND_DAI_LSM4,
  5421. },
  5422. {
  5423. .name = "Listen 5 Audio Service",
  5424. .stream_name = "Listen 5 Audio Service",
  5425. .cpu_dai_name = "LSM5",
  5426. .platform_name = "msm-lsm-client",
  5427. .dynamic = 1,
  5428. .dpcm_capture = 1,
  5429. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5430. SND_SOC_DPCM_TRIGGER_POST },
  5431. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5432. .ignore_suspend = 1,
  5433. .codec_dai_name = "snd-soc-dummy-dai",
  5434. .codec_name = "snd-soc-dummy",
  5435. .id = MSM_FRONTEND_DAI_LSM5,
  5436. },
  5437. {
  5438. .name = "Listen 6 Audio Service",
  5439. .stream_name = "Listen 6 Audio Service",
  5440. .cpu_dai_name = "LSM6",
  5441. .platform_name = "msm-lsm-client",
  5442. .dynamic = 1,
  5443. .dpcm_capture = 1,
  5444. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5445. SND_SOC_DPCM_TRIGGER_POST },
  5446. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5447. .ignore_suspend = 1,
  5448. .codec_dai_name = "snd-soc-dummy-dai",
  5449. .codec_name = "snd-soc-dummy",
  5450. .id = MSM_FRONTEND_DAI_LSM6,
  5451. },
  5452. {
  5453. .name = "Listen 7 Audio Service",
  5454. .stream_name = "Listen 7 Audio Service",
  5455. .cpu_dai_name = "LSM7",
  5456. .platform_name = "msm-lsm-client",
  5457. .dynamic = 1,
  5458. .dpcm_capture = 1,
  5459. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5460. SND_SOC_DPCM_TRIGGER_POST },
  5461. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5462. .ignore_suspend = 1,
  5463. .codec_dai_name = "snd-soc-dummy-dai",
  5464. .codec_name = "snd-soc-dummy",
  5465. .id = MSM_FRONTEND_DAI_LSM7,
  5466. },
  5467. {
  5468. .name = "Listen 8 Audio Service",
  5469. .stream_name = "Listen 8 Audio Service",
  5470. .cpu_dai_name = "LSM8",
  5471. .platform_name = "msm-lsm-client",
  5472. .dynamic = 1,
  5473. .dpcm_capture = 1,
  5474. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5475. SND_SOC_DPCM_TRIGGER_POST },
  5476. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5477. .ignore_suspend = 1,
  5478. .codec_dai_name = "snd-soc-dummy-dai",
  5479. .codec_name = "snd-soc-dummy",
  5480. .id = MSM_FRONTEND_DAI_LSM8,
  5481. },
  5482. {
  5483. .name = MSM_DAILINK_NAME(Media9),
  5484. .stream_name = "MultiMedia9",
  5485. .cpu_dai_name = "MultiMedia9",
  5486. .platform_name = "msm-pcm-dsp.0",
  5487. .dynamic = 1,
  5488. .dpcm_playback = 1,
  5489. .dpcm_capture = 1,
  5490. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5491. SND_SOC_DPCM_TRIGGER_POST},
  5492. .codec_dai_name = "snd-soc-dummy-dai",
  5493. .codec_name = "snd-soc-dummy",
  5494. .ignore_suspend = 1,
  5495. /* this dainlink has playback support */
  5496. .ignore_pmdown_time = 1,
  5497. .id = MSM_FRONTEND_DAI_MULTIMEDIA9,
  5498. },
  5499. {
  5500. .name = MSM_DAILINK_NAME(Compress4),
  5501. .stream_name = "Compress4",
  5502. .cpu_dai_name = "MultiMedia11",
  5503. .platform_name = "msm-compress-dsp",
  5504. .dynamic = 1,
  5505. .dpcm_playback = 1,
  5506. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5507. SND_SOC_DPCM_TRIGGER_POST},
  5508. .codec_dai_name = "snd-soc-dummy-dai",
  5509. .codec_name = "snd-soc-dummy",
  5510. .ignore_suspend = 1,
  5511. .ignore_pmdown_time = 1,
  5512. /* this dainlink has playback support */
  5513. .id = MSM_FRONTEND_DAI_MULTIMEDIA11,
  5514. },
  5515. {
  5516. .name = MSM_DAILINK_NAME(Compress5),
  5517. .stream_name = "Compress5",
  5518. .cpu_dai_name = "MultiMedia12",
  5519. .platform_name = "msm-compress-dsp",
  5520. .dynamic = 1,
  5521. .dpcm_playback = 1,
  5522. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5523. SND_SOC_DPCM_TRIGGER_POST},
  5524. .codec_dai_name = "snd-soc-dummy-dai",
  5525. .codec_name = "snd-soc-dummy",
  5526. .ignore_suspend = 1,
  5527. .ignore_pmdown_time = 1,
  5528. /* this dainlink has playback support */
  5529. .id = MSM_FRONTEND_DAI_MULTIMEDIA12,
  5530. },
  5531. {
  5532. .name = MSM_DAILINK_NAME(Compress6),
  5533. .stream_name = "Compress6",
  5534. .cpu_dai_name = "MultiMedia13",
  5535. .platform_name = "msm-compress-dsp",
  5536. .dynamic = 1,
  5537. .dpcm_playback = 1,
  5538. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5539. SND_SOC_DPCM_TRIGGER_POST},
  5540. .codec_dai_name = "snd-soc-dummy-dai",
  5541. .codec_name = "snd-soc-dummy",
  5542. .ignore_suspend = 1,
  5543. .ignore_pmdown_time = 1,
  5544. /* this dainlink has playback support */
  5545. .id = MSM_FRONTEND_DAI_MULTIMEDIA13,
  5546. },
  5547. {
  5548. .name = MSM_DAILINK_NAME(Compress7),
  5549. .stream_name = "Compress7",
  5550. .cpu_dai_name = "MultiMedia14",
  5551. .platform_name = "msm-compress-dsp",
  5552. .dynamic = 1,
  5553. .dpcm_playback = 1,
  5554. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5555. SND_SOC_DPCM_TRIGGER_POST},
  5556. .codec_dai_name = "snd-soc-dummy-dai",
  5557. .codec_name = "snd-soc-dummy",
  5558. .ignore_suspend = 1,
  5559. .ignore_pmdown_time = 1,
  5560. /* this dainlink has playback support */
  5561. .id = MSM_FRONTEND_DAI_MULTIMEDIA14,
  5562. },
  5563. {
  5564. .name = MSM_DAILINK_NAME(Compress8),
  5565. .stream_name = "Compress8",
  5566. .cpu_dai_name = "MultiMedia15",
  5567. .platform_name = "msm-compress-dsp",
  5568. .dynamic = 1,
  5569. .dpcm_playback = 1,
  5570. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5571. SND_SOC_DPCM_TRIGGER_POST},
  5572. .codec_dai_name = "snd-soc-dummy-dai",
  5573. .codec_name = "snd-soc-dummy",
  5574. .ignore_suspend = 1,
  5575. .ignore_pmdown_time = 1,
  5576. /* this dainlink has playback support */
  5577. .id = MSM_FRONTEND_DAI_MULTIMEDIA15,
  5578. },
  5579. {
  5580. .name = MSM_DAILINK_NAME(ULL_NOIRQ_2),
  5581. .stream_name = "MM_NOIRQ_2",
  5582. .cpu_dai_name = "MultiMedia16",
  5583. .platform_name = "msm-pcm-dsp-noirq",
  5584. .dynamic = 1,
  5585. .dpcm_playback = 1,
  5586. .dpcm_capture = 1,
  5587. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5588. SND_SOC_DPCM_TRIGGER_POST},
  5589. .codec_dai_name = "snd-soc-dummy-dai",
  5590. .codec_name = "snd-soc-dummy",
  5591. .ignore_suspend = 1,
  5592. .ignore_pmdown_time = 1,
  5593. /* this dainlink has playback support */
  5594. .id = MSM_FRONTEND_DAI_MULTIMEDIA16,
  5595. },
  5596. {
  5597. .name = "SLIMBUS_8 Hostless",
  5598. .stream_name = "SLIMBUS8_HOSTLESS Capture",
  5599. .cpu_dai_name = "SLIMBUS8_HOSTLESS",
  5600. .platform_name = "msm-pcm-hostless",
  5601. .dynamic = 1,
  5602. .dpcm_capture = 1,
  5603. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5604. SND_SOC_DPCM_TRIGGER_POST},
  5605. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5606. .ignore_suspend = 1,
  5607. .codec_dai_name = "snd-soc-dummy-dai",
  5608. .codec_name = "snd-soc-dummy",
  5609. },
  5610. /* Hostless PCM purpose */
  5611. {
  5612. .name = "CDC_DMA Hostless",
  5613. .stream_name = "CDC_DMA Hostless",
  5614. .cpu_dai_name = "CDC_DMA_HOSTLESS",
  5615. .platform_name = "msm-pcm-hostless",
  5616. .dynamic = 1,
  5617. .dpcm_playback = 1,
  5618. .dpcm_capture = 1,
  5619. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5620. SND_SOC_DPCM_TRIGGER_POST},
  5621. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5622. .ignore_suspend = 1,
  5623. /* this dailink has playback support */
  5624. .ignore_pmdown_time = 1,
  5625. .codec_dai_name = "snd-soc-dummy-dai",
  5626. .codec_name = "snd-soc-dummy",
  5627. },
  5628. };
  5629. static struct snd_soc_dai_link msm_bolero_fe_dai_links[] = {
  5630. {
  5631. .name = LPASS_BE_WSA_CDC_DMA_TX_0,
  5632. .stream_name = "WSA CDC DMA0 Capture",
  5633. .cpu_dai_name = "msm-dai-cdc-dma-dev.45057",
  5634. .platform_name = "msm-pcm-hostless",
  5635. .codec_name = "bolero_codec",
  5636. .codec_dai_name = "wsa_macro_vifeedback",
  5637. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0,
  5638. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5639. .ignore_suspend = 1,
  5640. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5641. .ops = &msm_cdc_dma_be_ops,
  5642. },
  5643. };
  5644. static struct snd_soc_dai_link msm_common_misc_fe_dai_links[] = {
  5645. {
  5646. .name = MSM_DAILINK_NAME(ASM Loopback),
  5647. .stream_name = "MultiMedia6",
  5648. .cpu_dai_name = "MultiMedia6",
  5649. .platform_name = "msm-pcm-loopback",
  5650. .dynamic = 1,
  5651. .dpcm_playback = 1,
  5652. .dpcm_capture = 1,
  5653. .codec_dai_name = "snd-soc-dummy-dai",
  5654. .codec_name = "snd-soc-dummy",
  5655. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5656. SND_SOC_DPCM_TRIGGER_POST},
  5657. .ignore_suspend = 1,
  5658. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5659. .ignore_pmdown_time = 1,
  5660. .id = MSM_FRONTEND_DAI_MULTIMEDIA6,
  5661. },
  5662. {
  5663. .name = "USB Audio Hostless",
  5664. .stream_name = "USB Audio Hostless",
  5665. .cpu_dai_name = "USBAUDIO_HOSTLESS",
  5666. .platform_name = "msm-pcm-hostless",
  5667. .dynamic = 1,
  5668. .dpcm_playback = 1,
  5669. .dpcm_capture = 1,
  5670. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5671. SND_SOC_DPCM_TRIGGER_POST},
  5672. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5673. .ignore_suspend = 1,
  5674. .ignore_pmdown_time = 1,
  5675. .codec_dai_name = "snd-soc-dummy-dai",
  5676. .codec_name = "snd-soc-dummy",
  5677. },
  5678. {
  5679. .name = "SLIMBUS_7 Hostless",
  5680. .stream_name = "SLIMBUS_7 Hostless",
  5681. .cpu_dai_name = "SLIMBUS7_HOSTLESS",
  5682. .platform_name = "msm-pcm-hostless",
  5683. .dynamic = 1,
  5684. .dpcm_capture = 1,
  5685. .dpcm_playback = 1,
  5686. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5687. SND_SOC_DPCM_TRIGGER_POST},
  5688. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5689. .ignore_suspend = 1,
  5690. .ignore_pmdown_time = 1,
  5691. .codec_dai_name = "snd-soc-dummy-dai",
  5692. .codec_name = "snd-soc-dummy",
  5693. },
  5694. {
  5695. .name = MSM_DAILINK_NAME(Compr Capture),
  5696. .stream_name = "Compr Capture",
  5697. .cpu_dai_name = "MultiMedia18",
  5698. .platform_name = "msm-compress-dsp",
  5699. .dynamic = 1,
  5700. .dpcm_capture = 1,
  5701. .codec_dai_name = "snd-soc-dummy-dai",
  5702. .codec_name = "snd-soc-dummy",
  5703. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5704. SND_SOC_DPCM_TRIGGER_POST},
  5705. .ignore_pmdown_time = 1,
  5706. .id = MSM_FRONTEND_DAI_MULTIMEDIA18,
  5707. },
  5708. {
  5709. .name = MSM_DAILINK_NAME(Transcode Loopback Playback),
  5710. .stream_name = "Transcode Loopback Playback",
  5711. .cpu_dai_name = "MultiMedia26",
  5712. .platform_name = "msm-transcode-loopback",
  5713. .dynamic = 1,
  5714. .dpcm_playback = 1,
  5715. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5716. SND_SOC_DPCM_TRIGGER_POST},
  5717. .codec_dai_name = "snd-soc-dummy-dai",
  5718. .codec_name = "snd-soc-dummy",
  5719. .ignore_suspend = 1,
  5720. .ignore_pmdown_time = 1,
  5721. /* this dailink has playback support */
  5722. .id = MSM_FRONTEND_DAI_MULTIMEDIA26,
  5723. },
  5724. {
  5725. .name = MSM_DAILINK_NAME(Transcode Loopback Capture),
  5726. .stream_name = "Transcode Loopback Capture",
  5727. .cpu_dai_name = "MultiMedia27",
  5728. .platform_name = "msm-transcode-loopback",
  5729. .dynamic = 1,
  5730. .dpcm_capture = 1,
  5731. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5732. SND_SOC_DPCM_TRIGGER_POST},
  5733. .codec_dai_name = "snd-soc-dummy-dai",
  5734. .codec_name = "snd-soc-dummy",
  5735. .ignore_suspend = 1,
  5736. .ignore_pmdown_time = 1,
  5737. .id = MSM_FRONTEND_DAI_MULTIMEDIA27,
  5738. },
  5739. };
  5740. static struct snd_soc_dai_link msm_common_be_dai_links[] = {
  5741. /* Backend AFE DAI Links */
  5742. {
  5743. .name = LPASS_BE_AFE_PCM_RX,
  5744. .stream_name = "AFE Playback",
  5745. .cpu_dai_name = "msm-dai-q6-dev.224",
  5746. .platform_name = "msm-pcm-routing",
  5747. .codec_name = "msm-stub-codec.1",
  5748. .codec_dai_name = "msm-stub-rx",
  5749. .no_pcm = 1,
  5750. .dpcm_playback = 1,
  5751. .id = MSM_BACKEND_DAI_AFE_PCM_RX,
  5752. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5753. /* this dainlink has playback support */
  5754. .ignore_pmdown_time = 1,
  5755. .ignore_suspend = 1,
  5756. },
  5757. {
  5758. .name = LPASS_BE_AFE_PCM_TX,
  5759. .stream_name = "AFE Capture",
  5760. .cpu_dai_name = "msm-dai-q6-dev.225",
  5761. .platform_name = "msm-pcm-routing",
  5762. .codec_name = "msm-stub-codec.1",
  5763. .codec_dai_name = "msm-stub-tx",
  5764. .no_pcm = 1,
  5765. .dpcm_capture = 1,
  5766. .id = MSM_BACKEND_DAI_AFE_PCM_TX,
  5767. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5768. .ignore_suspend = 1,
  5769. },
  5770. /* Incall Record Uplink BACK END DAI Link */
  5771. {
  5772. .name = LPASS_BE_INCALL_RECORD_TX,
  5773. .stream_name = "Voice Uplink Capture",
  5774. .cpu_dai_name = "msm-dai-q6-dev.32772",
  5775. .platform_name = "msm-pcm-routing",
  5776. .codec_name = "msm-stub-codec.1",
  5777. .codec_dai_name = "msm-stub-tx",
  5778. .no_pcm = 1,
  5779. .dpcm_capture = 1,
  5780. .id = MSM_BACKEND_DAI_INCALL_RECORD_TX,
  5781. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5782. .ignore_suspend = 1,
  5783. },
  5784. /* Incall Record Downlink BACK END DAI Link */
  5785. {
  5786. .name = LPASS_BE_INCALL_RECORD_RX,
  5787. .stream_name = "Voice Downlink Capture",
  5788. .cpu_dai_name = "msm-dai-q6-dev.32771",
  5789. .platform_name = "msm-pcm-routing",
  5790. .codec_name = "msm-stub-codec.1",
  5791. .codec_dai_name = "msm-stub-tx",
  5792. .no_pcm = 1,
  5793. .dpcm_capture = 1,
  5794. .id = MSM_BACKEND_DAI_INCALL_RECORD_RX,
  5795. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5796. .ignore_suspend = 1,
  5797. },
  5798. /* Incall Music BACK END DAI Link */
  5799. {
  5800. .name = LPASS_BE_VOICE_PLAYBACK_TX,
  5801. .stream_name = "Voice Farend Playback",
  5802. .cpu_dai_name = "msm-dai-q6-dev.32773",
  5803. .platform_name = "msm-pcm-routing",
  5804. .codec_name = "msm-stub-codec.1",
  5805. .codec_dai_name = "msm-stub-rx",
  5806. .no_pcm = 1,
  5807. .dpcm_playback = 1,
  5808. .id = MSM_BACKEND_DAI_VOICE_PLAYBACK_TX,
  5809. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5810. .ignore_suspend = 1,
  5811. .ignore_pmdown_time = 1,
  5812. },
  5813. /* Incall Music 2 BACK END DAI Link */
  5814. {
  5815. .name = LPASS_BE_VOICE2_PLAYBACK_TX,
  5816. .stream_name = "Voice2 Farend Playback",
  5817. .cpu_dai_name = "msm-dai-q6-dev.32770",
  5818. .platform_name = "msm-pcm-routing",
  5819. .codec_name = "msm-stub-codec.1",
  5820. .codec_dai_name = "msm-stub-rx",
  5821. .no_pcm = 1,
  5822. .dpcm_playback = 1,
  5823. .id = MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX,
  5824. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5825. .ignore_suspend = 1,
  5826. .ignore_pmdown_time = 1,
  5827. },
  5828. {
  5829. .name = LPASS_BE_USB_AUDIO_RX,
  5830. .stream_name = "USB Audio Playback",
  5831. .cpu_dai_name = "msm-dai-q6-dev.28672",
  5832. .platform_name = "msm-pcm-routing",
  5833. .codec_name = "msm-stub-codec.1",
  5834. .codec_dai_name = "msm-stub-rx",
  5835. .no_pcm = 1,
  5836. .dpcm_playback = 1,
  5837. .id = MSM_BACKEND_DAI_USB_RX,
  5838. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5839. .ignore_pmdown_time = 1,
  5840. .ignore_suspend = 1,
  5841. },
  5842. {
  5843. .name = LPASS_BE_USB_AUDIO_TX,
  5844. .stream_name = "USB Audio Capture",
  5845. .cpu_dai_name = "msm-dai-q6-dev.28673",
  5846. .platform_name = "msm-pcm-routing",
  5847. .codec_name = "msm-stub-codec.1",
  5848. .codec_dai_name = "msm-stub-tx",
  5849. .no_pcm = 1,
  5850. .dpcm_capture = 1,
  5851. .id = MSM_BACKEND_DAI_USB_TX,
  5852. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5853. .ignore_suspend = 1,
  5854. },
  5855. {
  5856. .name = LPASS_BE_PRI_TDM_RX_0,
  5857. .stream_name = "Primary TDM0 Playback",
  5858. .cpu_dai_name = "msm-dai-q6-tdm.36864",
  5859. .platform_name = "msm-pcm-routing",
  5860. .codec_name = "msm-stub-codec.1",
  5861. .codec_dai_name = "msm-stub-rx",
  5862. .no_pcm = 1,
  5863. .dpcm_playback = 1,
  5864. .id = MSM_BACKEND_DAI_PRI_TDM_RX_0,
  5865. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5866. .ops = &qcs405_tdm_be_ops,
  5867. .ignore_suspend = 1,
  5868. .ignore_pmdown_time = 1,
  5869. },
  5870. {
  5871. .name = LPASS_BE_PRI_TDM_TX_0,
  5872. .stream_name = "Primary TDM0 Capture",
  5873. .cpu_dai_name = "msm-dai-q6-tdm.36865",
  5874. .platform_name = "msm-pcm-routing",
  5875. .codec_name = "msm-stub-codec.1",
  5876. .codec_dai_name = "msm-stub-tx",
  5877. .no_pcm = 1,
  5878. .dpcm_capture = 1,
  5879. .id = MSM_BACKEND_DAI_PRI_TDM_TX_0,
  5880. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5881. .ops = &qcs405_tdm_be_ops,
  5882. .ignore_suspend = 1,
  5883. },
  5884. {
  5885. .name = LPASS_BE_SEC_TDM_RX_0,
  5886. .stream_name = "Secondary TDM0 Playback",
  5887. .cpu_dai_name = "msm-dai-q6-tdm.36880",
  5888. .platform_name = "msm-pcm-routing",
  5889. .codec_name = "msm-stub-codec.1",
  5890. .codec_dai_name = "msm-stub-rx",
  5891. .no_pcm = 1,
  5892. .dpcm_playback = 1,
  5893. .id = MSM_BACKEND_DAI_SEC_TDM_RX_0,
  5894. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5895. .ops = &qcs405_tdm_be_ops,
  5896. .ignore_suspend = 1,
  5897. .ignore_pmdown_time = 1,
  5898. },
  5899. {
  5900. .name = LPASS_BE_SEC_TDM_TX_0,
  5901. .stream_name = "Secondary TDM0 Capture",
  5902. .cpu_dai_name = "msm-dai-q6-tdm.36881",
  5903. .platform_name = "msm-pcm-routing",
  5904. .codec_name = "msm-stub-codec.1",
  5905. .codec_dai_name = "msm-stub-tx",
  5906. .no_pcm = 1,
  5907. .dpcm_capture = 1,
  5908. .id = MSM_BACKEND_DAI_SEC_TDM_TX_0,
  5909. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5910. .ops = &qcs405_tdm_be_ops,
  5911. .ignore_suspend = 1,
  5912. },
  5913. {
  5914. .name = LPASS_BE_TERT_TDM_RX_0,
  5915. .stream_name = "Tertiary TDM0 Playback",
  5916. .cpu_dai_name = "msm-dai-q6-tdm.36896",
  5917. .platform_name = "msm-pcm-routing",
  5918. .codec_name = "msm-stub-codec.1",
  5919. .codec_dai_name = "msm-stub-rx",
  5920. .no_pcm = 1,
  5921. .dpcm_playback = 1,
  5922. .id = MSM_BACKEND_DAI_TERT_TDM_RX_0,
  5923. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5924. .ops = &qcs405_tdm_be_ops,
  5925. .ignore_suspend = 1,
  5926. .ignore_pmdown_time = 1,
  5927. },
  5928. {
  5929. .name = LPASS_BE_TERT_TDM_TX_0,
  5930. .stream_name = "Tertiary TDM0 Capture",
  5931. .cpu_dai_name = "msm-dai-q6-tdm.36897",
  5932. .platform_name = "msm-pcm-routing",
  5933. .codec_name = "msm-stub-codec.1",
  5934. .codec_dai_name = "msm-stub-tx",
  5935. .no_pcm = 1,
  5936. .dpcm_capture = 1,
  5937. .id = MSM_BACKEND_DAI_TERT_TDM_TX_0,
  5938. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5939. .ops = &qcs405_tdm_be_ops,
  5940. .ignore_suspend = 1,
  5941. },
  5942. {
  5943. .name = LPASS_BE_QUAT_TDM_RX_0,
  5944. .stream_name = "Quaternary TDM0 Playback",
  5945. .cpu_dai_name = "msm-dai-q6-tdm.36912",
  5946. .platform_name = "msm-pcm-routing",
  5947. .codec_name = "msm-stub-codec.1",
  5948. .codec_dai_name = "msm-stub-rx",
  5949. .no_pcm = 1,
  5950. .dpcm_playback = 1,
  5951. .id = MSM_BACKEND_DAI_QUAT_TDM_RX_0,
  5952. .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
  5953. .ops = &qcs405_tdm_be_ops,
  5954. .ignore_suspend = 1,
  5955. .ignore_pmdown_time = 1,
  5956. },
  5957. {
  5958. .name = LPASS_BE_QUAT_TDM_TX_0,
  5959. .stream_name = "Quaternary TDM0 Capture",
  5960. .cpu_dai_name = "msm-dai-q6-tdm.36913",
  5961. .platform_name = "msm-pcm-routing",
  5962. .codec_name = "msm-stub-codec.1",
  5963. .codec_dai_name = "msm-stub-tx",
  5964. .no_pcm = 1,
  5965. .dpcm_capture = 1,
  5966. .id = MSM_BACKEND_DAI_QUAT_TDM_TX_0,
  5967. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5968. .ops = &qcs405_tdm_be_ops,
  5969. .ignore_suspend = 1,
  5970. },
  5971. {
  5972. .name = LPASS_BE_QUIN_TDM_RX_0,
  5973. .stream_name = "Quinary TDM0 Playback",
  5974. .cpu_dai_name = "msm-dai-q6-tdm.36928",
  5975. .platform_name = "msm-pcm-routing",
  5976. .codec_name = "msm-stub-codec.1",
  5977. .codec_dai_name = "msm-stub-rx",
  5978. .no_pcm = 1,
  5979. .dpcm_playback = 1,
  5980. .id = MSM_BACKEND_DAI_QUIN_TDM_RX_0,
  5981. .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
  5982. .ops = &qcs405_tdm_be_ops,
  5983. .ignore_suspend = 1,
  5984. .ignore_pmdown_time = 1,
  5985. },
  5986. {
  5987. .name = LPASS_BE_QUIN_TDM_TX_0,
  5988. .stream_name = "Quinary TDM0 Capture",
  5989. .cpu_dai_name = "msm-dai-q6-tdm.36929",
  5990. .platform_name = "msm-pcm-routing",
  5991. .codec_name = "msm-stub-codec.1",
  5992. .codec_dai_name = "msm-stub-tx",
  5993. .no_pcm = 1,
  5994. .dpcm_capture = 1,
  5995. .id = MSM_BACKEND_DAI_QUIN_TDM_TX_0,
  5996. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5997. .ops = &qcs405_tdm_be_ops,
  5998. .ignore_suspend = 1,
  5999. },
  6000. };
  6001. static struct snd_soc_dai_link msm_tasha_be_dai_links[] = {
  6002. {
  6003. .name = LPASS_BE_SLIMBUS_0_RX,
  6004. .stream_name = "Slimbus Playback",
  6005. .cpu_dai_name = "msm-dai-q6-dev.16384",
  6006. .platform_name = "msm-pcm-routing",
  6007. .codec_name = "tasha_codec",
  6008. .codec_dai_name = "tasha_mix_rx1",
  6009. .no_pcm = 1,
  6010. .dpcm_playback = 1,
  6011. .id = MSM_BACKEND_DAI_SLIMBUS_0_RX,
  6012. .init = &msm_audrx_init,
  6013. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6014. /* this dainlink has playback support */
  6015. .ignore_pmdown_time = 1,
  6016. .ignore_suspend = 1,
  6017. .ops = &msm_be_ops,
  6018. },
  6019. {
  6020. .name = LPASS_BE_SLIMBUS_0_TX,
  6021. .stream_name = "Slimbus Capture",
  6022. .cpu_dai_name = "msm-dai-q6-dev.16385",
  6023. .platform_name = "msm-pcm-routing",
  6024. .codec_name = "tasha_codec",
  6025. .codec_dai_name = "tasha_tx1",
  6026. .no_pcm = 1,
  6027. .dpcm_capture = 1,
  6028. .id = MSM_BACKEND_DAI_SLIMBUS_0_TX,
  6029. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6030. .ignore_suspend = 1,
  6031. .ops = &msm_be_ops,
  6032. },
  6033. {
  6034. .name = LPASS_BE_SLIMBUS_1_RX,
  6035. .stream_name = "Slimbus1 Playback",
  6036. .cpu_dai_name = "msm-dai-q6-dev.16386",
  6037. .platform_name = "msm-pcm-routing",
  6038. .codec_name = "tasha_codec",
  6039. .codec_dai_name = "tasha_mix_rx1",
  6040. .no_pcm = 1,
  6041. .dpcm_playback = 1,
  6042. .id = MSM_BACKEND_DAI_SLIMBUS_1_RX,
  6043. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6044. .ops = &msm_be_ops,
  6045. /* dai link has playback support */
  6046. .ignore_pmdown_time = 1,
  6047. .ignore_suspend = 1,
  6048. },
  6049. {
  6050. .name = LPASS_BE_SLIMBUS_1_TX,
  6051. .stream_name = "Slimbus1 Capture",
  6052. .cpu_dai_name = "msm-dai-q6-dev.16387",
  6053. .platform_name = "msm-pcm-routing",
  6054. .codec_name = "tasha_codec",
  6055. .codec_dai_name = "tasha_tx3",
  6056. .no_pcm = 1,
  6057. .dpcm_capture = 1,
  6058. .id = MSM_BACKEND_DAI_SLIMBUS_1_TX,
  6059. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6060. .ops = &msm_be_ops,
  6061. .ignore_suspend = 1,
  6062. },
  6063. {
  6064. .name = LPASS_BE_SLIMBUS_2_RX,
  6065. .stream_name = "Slimbus2 Playback",
  6066. .cpu_dai_name = "msm-dai-q6-dev.16388",
  6067. .platform_name = "msm-pcm-routing",
  6068. .codec_name = "tasha_codec",
  6069. .codec_dai_name = "tasha_rx2",
  6070. .no_pcm = 1,
  6071. .dpcm_playback = 1,
  6072. .id = MSM_BACKEND_DAI_SLIMBUS_2_RX,
  6073. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6074. .ops = &msm_be_ops,
  6075. .ignore_pmdown_time = 1,
  6076. .ignore_suspend = 1,
  6077. },
  6078. {
  6079. .name = LPASS_BE_SLIMBUS_3_RX,
  6080. .stream_name = "Slimbus3 Playback",
  6081. .cpu_dai_name = "msm-dai-q6-dev.16390",
  6082. .platform_name = "msm-pcm-routing",
  6083. .codec_name = "tasha_codec",
  6084. .codec_dai_name = "tasha_mix_rx1",
  6085. .no_pcm = 1,
  6086. .dpcm_playback = 1,
  6087. .id = MSM_BACKEND_DAI_SLIMBUS_3_RX,
  6088. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6089. .ops = &msm_be_ops,
  6090. /* dai link has playback support */
  6091. .ignore_pmdown_time = 1,
  6092. .ignore_suspend = 1,
  6093. },
  6094. {
  6095. .name = LPASS_BE_SLIMBUS_3_TX,
  6096. .stream_name = "Slimbus3 Capture",
  6097. .cpu_dai_name = "msm-dai-q6-dev.16391",
  6098. .platform_name = "msm-pcm-routing",
  6099. .codec_name = "tasha_codec",
  6100. .codec_dai_name = "tasha_tx1",
  6101. .no_pcm = 1,
  6102. .dpcm_capture = 1,
  6103. .id = MSM_BACKEND_DAI_SLIMBUS_3_TX,
  6104. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6105. .ops = &msm_be_ops,
  6106. .ignore_suspend = 1,
  6107. },
  6108. {
  6109. .name = LPASS_BE_SLIMBUS_4_RX,
  6110. .stream_name = "Slimbus4 Playback",
  6111. .cpu_dai_name = "msm-dai-q6-dev.16392",
  6112. .platform_name = "msm-pcm-routing",
  6113. .codec_name = "tasha_codec",
  6114. .codec_dai_name = "tasha_mix_rx1",
  6115. .no_pcm = 1,
  6116. .dpcm_playback = 1,
  6117. .id = MSM_BACKEND_DAI_SLIMBUS_4_RX,
  6118. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6119. .ops = &msm_be_ops,
  6120. /* dai link has playback support */
  6121. .ignore_pmdown_time = 1,
  6122. .ignore_suspend = 1,
  6123. },
  6124. {
  6125. .name = LPASS_BE_SLIMBUS_5_RX,
  6126. .stream_name = "Slimbus5 Playback",
  6127. .cpu_dai_name = "msm-dai-q6-dev.16394",
  6128. .platform_name = "msm-pcm-routing",
  6129. .codec_name = "tasha_codec",
  6130. .codec_dai_name = "tasha_rx3",
  6131. .no_pcm = 1,
  6132. .dpcm_playback = 1,
  6133. .id = MSM_BACKEND_DAI_SLIMBUS_5_RX,
  6134. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6135. .ops = &msm_be_ops,
  6136. /* dai link has playback support */
  6137. .ignore_pmdown_time = 1,
  6138. .ignore_suspend = 1,
  6139. },
  6140. {
  6141. .name = LPASS_BE_SLIMBUS_6_RX,
  6142. .stream_name = "Slimbus6 Playback",
  6143. .cpu_dai_name = "msm-dai-q6-dev.16396",
  6144. .platform_name = "msm-pcm-routing",
  6145. .codec_name = "tasha_codec",
  6146. .codec_dai_name = "tasha_rx4",
  6147. .no_pcm = 1,
  6148. .dpcm_playback = 1,
  6149. .id = MSM_BACKEND_DAI_SLIMBUS_6_RX,
  6150. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6151. .ops = &msm_be_ops,
  6152. /* dai link has playback support */
  6153. .ignore_pmdown_time = 1,
  6154. .ignore_suspend = 1,
  6155. },
  6156. /* Slimbus VI Recording */
  6157. {
  6158. .name = LPASS_BE_SLIMBUS_TX_VI,
  6159. .stream_name = "Slimbus4 Capture",
  6160. .cpu_dai_name = "msm-dai-q6-dev.16393",
  6161. .platform_name = "msm-pcm-routing",
  6162. .codec_name = "tasha_codec",
  6163. .codec_dai_name = "tasha_vifeedback",
  6164. .id = MSM_BACKEND_DAI_SLIMBUS_4_TX,
  6165. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6166. .ops = &msm_be_ops,
  6167. .ignore_suspend = 1,
  6168. .no_pcm = 1,
  6169. .dpcm_capture = 1,
  6170. .ignore_pmdown_time = 1,
  6171. },
  6172. };
  6173. static struct snd_soc_dai_link msm_wcn_be_dai_links[] = {
  6174. {
  6175. .name = LPASS_BE_SLIMBUS_7_RX,
  6176. .stream_name = "Slimbus7 Playback",
  6177. .cpu_dai_name = "msm-dai-q6-dev.16398",
  6178. .platform_name = "msm-pcm-routing",
  6179. .codec_name = "btfmslim_slave",
  6180. /* BT codec driver determines capabilities based on
  6181. * dai name, bt codecdai name should always contains
  6182. * supported usecase information
  6183. */
  6184. .codec_dai_name = "btfm_bt_sco_a2dp_slim_rx",
  6185. .no_pcm = 1,
  6186. .dpcm_playback = 1,
  6187. .id = MSM_BACKEND_DAI_SLIMBUS_7_RX,
  6188. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6189. .ops = &msm_wcn_ops,
  6190. /* dai link has playback support */
  6191. .ignore_pmdown_time = 1,
  6192. .ignore_suspend = 1,
  6193. },
  6194. {
  6195. .name = LPASS_BE_SLIMBUS_7_TX,
  6196. .stream_name = "Slimbus7 Capture",
  6197. .cpu_dai_name = "msm-dai-q6-dev.16399",
  6198. .platform_name = "msm-pcm-routing",
  6199. .codec_name = "btfmslim_slave",
  6200. .codec_dai_name = "btfm_bt_sco_slim_tx",
  6201. .no_pcm = 1,
  6202. .dpcm_capture = 1,
  6203. .id = MSM_BACKEND_DAI_SLIMBUS_7_TX,
  6204. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6205. .ops = &msm_wcn_ops,
  6206. .ignore_suspend = 1,
  6207. },
  6208. {
  6209. .name = LPASS_BE_SLIMBUS_8_TX,
  6210. .stream_name = "Slimbus8 Capture",
  6211. .cpu_dai_name = "msm-dai-q6-dev.16401",
  6212. .platform_name = "msm-pcm-routing",
  6213. .codec_name = "btfmslim_slave",
  6214. .codec_dai_name = "btfm_fm_slim_tx",
  6215. .no_pcm = 1,
  6216. .dpcm_capture = 1,
  6217. .id = MSM_BACKEND_DAI_SLIMBUS_8_TX,
  6218. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6219. .init = &msm_wcn_init,
  6220. .ops = &msm_wcn_ops,
  6221. .ignore_suspend = 1,
  6222. },
  6223. };
  6224. static struct snd_soc_dai_link msm_mi2s_be_dai_links[] = {
  6225. {
  6226. .name = LPASS_BE_PRI_MI2S_RX,
  6227. .stream_name = "Primary MI2S Playback",
  6228. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  6229. .platform_name = "msm-pcm-routing",
  6230. .codec_name = "msm-stub-codec.1",
  6231. .codec_dai_name = "msm-stub-rx",
  6232. .no_pcm = 1,
  6233. .dpcm_playback = 1,
  6234. .id = MSM_BACKEND_DAI_PRI_MI2S_RX,
  6235. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6236. .ops = &msm_mi2s_be_ops,
  6237. .ignore_suspend = 1,
  6238. .ignore_pmdown_time = 1,
  6239. },
  6240. {
  6241. .name = LPASS_BE_PRI_MI2S_TX,
  6242. .stream_name = "Primary MI2S Capture",
  6243. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  6244. .platform_name = "msm-pcm-routing",
  6245. .codec_name = "msm-stub-codec.1",
  6246. .codec_dai_name = "msm-stub-tx",
  6247. .no_pcm = 1,
  6248. .dpcm_capture = 1,
  6249. .id = MSM_BACKEND_DAI_PRI_MI2S_TX,
  6250. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6251. .ops = &msm_mi2s_be_ops,
  6252. .ignore_suspend = 1,
  6253. },
  6254. {
  6255. .name = LPASS_BE_SEC_MI2S_RX,
  6256. .stream_name = "Secondary MI2S Playback",
  6257. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  6258. .platform_name = "msm-pcm-routing",
  6259. .codec_name = "msm-stub-codec.1",
  6260. .codec_dai_name = "msm-stub-rx",
  6261. .no_pcm = 1,
  6262. .dpcm_playback = 1,
  6263. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX,
  6264. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6265. .ops = &msm_mi2s_be_ops,
  6266. .ignore_suspend = 1,
  6267. .ignore_pmdown_time = 1,
  6268. },
  6269. {
  6270. .name = LPASS_BE_SEC_MI2S_TX,
  6271. .stream_name = "Secondary MI2S Capture",
  6272. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  6273. .platform_name = "msm-pcm-routing",
  6274. .codec_name = "msm-stub-codec.1",
  6275. .codec_dai_name = "msm-stub-tx",
  6276. .no_pcm = 1,
  6277. .dpcm_capture = 1,
  6278. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_TX,
  6279. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6280. .ops = &msm_mi2s_be_ops,
  6281. .ignore_suspend = 1,
  6282. },
  6283. {
  6284. .name = LPASS_BE_TERT_MI2S_RX,
  6285. .stream_name = "Tertiary MI2S Playback",
  6286. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  6287. .platform_name = "msm-pcm-routing",
  6288. .codec_name = "msm-stub-codec.1",
  6289. .codec_dai_name = "msm-stub-rx",
  6290. .no_pcm = 1,
  6291. .dpcm_playback = 1,
  6292. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_RX,
  6293. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6294. .ops = &msm_mi2s_be_ops,
  6295. .ignore_suspend = 1,
  6296. .ignore_pmdown_time = 1,
  6297. },
  6298. {
  6299. .name = LPASS_BE_TERT_MI2S_TX,
  6300. .stream_name = "Tertiary MI2S Capture",
  6301. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  6302. .platform_name = "msm-pcm-routing",
  6303. .codec_name = "msm-stub-codec.1",
  6304. .codec_dai_name = "msm-stub-tx",
  6305. .no_pcm = 1,
  6306. .dpcm_capture = 1,
  6307. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX,
  6308. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6309. .ops = &msm_mi2s_be_ops,
  6310. .ignore_suspend = 1,
  6311. },
  6312. {
  6313. .name = LPASS_BE_QUAT_MI2S_RX,
  6314. .stream_name = "Quaternary MI2S Playback",
  6315. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  6316. .platform_name = "msm-pcm-routing",
  6317. .codec_name = "msm-stub-codec.1",
  6318. .codec_dai_name = "msm-stub-rx",
  6319. .no_pcm = 1,
  6320. .dpcm_playback = 1,
  6321. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX,
  6322. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6323. .ops = &msm_mi2s_be_ops,
  6324. .ignore_suspend = 1,
  6325. .ignore_pmdown_time = 1,
  6326. },
  6327. {
  6328. .name = LPASS_BE_QUAT_MI2S_TX,
  6329. .stream_name = "Quaternary MI2S Capture",
  6330. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  6331. .platform_name = "msm-pcm-routing",
  6332. .codec_name = "msm-stub-codec.1",
  6333. .codec_dai_name = "msm-stub-tx",
  6334. .no_pcm = 1,
  6335. .dpcm_capture = 1,
  6336. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX,
  6337. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6338. .ops = &msm_mi2s_be_ops,
  6339. .ignore_suspend = 1,
  6340. },
  6341. {
  6342. .name = LPASS_BE_QUIN_MI2S_RX,
  6343. .stream_name = "Quinary MI2S Playback",
  6344. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  6345. .platform_name = "msm-pcm-routing",
  6346. .codec_name = "msm-stub-codec.1",
  6347. .codec_dai_name = "msm-stub-rx",
  6348. .no_pcm = 1,
  6349. .dpcm_playback = 1,
  6350. .id = MSM_BACKEND_DAI_QUINARY_MI2S_RX,
  6351. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6352. .ops = &msm_mi2s_be_ops,
  6353. .ignore_suspend = 1,
  6354. .ignore_pmdown_time = 1,
  6355. },
  6356. {
  6357. .name = LPASS_BE_QUIN_MI2S_TX,
  6358. .stream_name = "Quinary MI2S Capture",
  6359. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  6360. .platform_name = "msm-pcm-routing",
  6361. .codec_name = "msm-stub-codec.1",
  6362. .codec_dai_name = "msm-stub-tx",
  6363. .no_pcm = 1,
  6364. .dpcm_capture = 1,
  6365. .id = MSM_BACKEND_DAI_QUINARY_MI2S_TX,
  6366. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6367. .ops = &msm_mi2s_be_ops,
  6368. .ignore_suspend = 1,
  6369. },
  6370. };
  6371. static struct snd_soc_dai_link msm_auxpcm_be_dai_links[] = {
  6372. /* Primary AUX PCM Backend DAI Links */
  6373. {
  6374. .name = LPASS_BE_AUXPCM_RX,
  6375. .stream_name = "AUX PCM Playback",
  6376. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  6377. .platform_name = "msm-pcm-routing",
  6378. .codec_name = "msm-stub-codec.1",
  6379. .codec_dai_name = "msm-stub-rx",
  6380. .no_pcm = 1,
  6381. .dpcm_playback = 1,
  6382. .id = MSM_BACKEND_DAI_AUXPCM_RX,
  6383. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6384. .ignore_pmdown_time = 1,
  6385. .ignore_suspend = 1,
  6386. },
  6387. {
  6388. .name = LPASS_BE_AUXPCM_TX,
  6389. .stream_name = "AUX PCM Capture",
  6390. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  6391. .platform_name = "msm-pcm-routing",
  6392. .codec_name = "msm-stub-codec.1",
  6393. .codec_dai_name = "msm-stub-tx",
  6394. .no_pcm = 1,
  6395. .dpcm_capture = 1,
  6396. .id = MSM_BACKEND_DAI_AUXPCM_TX,
  6397. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6398. .ignore_suspend = 1,
  6399. },
  6400. /* Secondary AUX PCM Backend DAI Links */
  6401. {
  6402. .name = LPASS_BE_SEC_AUXPCM_RX,
  6403. .stream_name = "Sec AUX PCM Playback",
  6404. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  6405. .platform_name = "msm-pcm-routing",
  6406. .codec_name = "msm-stub-codec.1",
  6407. .codec_dai_name = "msm-stub-rx",
  6408. .no_pcm = 1,
  6409. .dpcm_playback = 1,
  6410. .id = MSM_BACKEND_DAI_SEC_AUXPCM_RX,
  6411. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6412. .ignore_pmdown_time = 1,
  6413. .ignore_suspend = 1,
  6414. },
  6415. {
  6416. .name = LPASS_BE_SEC_AUXPCM_TX,
  6417. .stream_name = "Sec AUX PCM Capture",
  6418. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  6419. .platform_name = "msm-pcm-routing",
  6420. .codec_name = "msm-stub-codec.1",
  6421. .codec_dai_name = "msm-stub-tx",
  6422. .no_pcm = 1,
  6423. .dpcm_capture = 1,
  6424. .id = MSM_BACKEND_DAI_SEC_AUXPCM_TX,
  6425. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6426. .ignore_suspend = 1,
  6427. },
  6428. /* Tertiary AUX PCM Backend DAI Links */
  6429. {
  6430. .name = LPASS_BE_TERT_AUXPCM_RX,
  6431. .stream_name = "Tert AUX PCM Playback",
  6432. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  6433. .platform_name = "msm-pcm-routing",
  6434. .codec_name = "msm-stub-codec.1",
  6435. .codec_dai_name = "msm-stub-rx",
  6436. .no_pcm = 1,
  6437. .dpcm_playback = 1,
  6438. .id = MSM_BACKEND_DAI_TERT_AUXPCM_RX,
  6439. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6440. .ignore_suspend = 1,
  6441. },
  6442. {
  6443. .name = LPASS_BE_TERT_AUXPCM_TX,
  6444. .stream_name = "Tert AUX PCM Capture",
  6445. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  6446. .platform_name = "msm-pcm-routing",
  6447. .codec_name = "msm-stub-codec.1",
  6448. .codec_dai_name = "msm-stub-tx",
  6449. .no_pcm = 1,
  6450. .dpcm_capture = 1,
  6451. .id = MSM_BACKEND_DAI_TERT_AUXPCM_TX,
  6452. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6453. .ignore_suspend = 1,
  6454. },
  6455. /* Quaternary AUX PCM Backend DAI Links */
  6456. {
  6457. .name = LPASS_BE_QUAT_AUXPCM_RX,
  6458. .stream_name = "Quat AUX PCM Playback",
  6459. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  6460. .platform_name = "msm-pcm-routing",
  6461. .codec_name = "msm-stub-codec.1",
  6462. .codec_dai_name = "msm-stub-rx",
  6463. .no_pcm = 1,
  6464. .dpcm_playback = 1,
  6465. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_RX,
  6466. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6467. .ignore_pmdown_time = 1,
  6468. .ignore_suspend = 1,
  6469. },
  6470. {
  6471. .name = LPASS_BE_QUAT_AUXPCM_TX,
  6472. .stream_name = "Quat AUX PCM Capture",
  6473. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  6474. .platform_name = "msm-pcm-routing",
  6475. .codec_name = "msm-stub-codec.1",
  6476. .codec_dai_name = "msm-stub-tx",
  6477. .no_pcm = 1,
  6478. .dpcm_capture = 1,
  6479. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_TX,
  6480. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6481. .ignore_suspend = 1,
  6482. },
  6483. /* Quinary AUX PCM Backend DAI Links */
  6484. {
  6485. .name = LPASS_BE_QUIN_AUXPCM_RX,
  6486. .stream_name = "Quin AUX PCM Playback",
  6487. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  6488. .platform_name = "msm-pcm-routing",
  6489. .codec_name = "msm-stub-codec.1",
  6490. .codec_dai_name = "msm-stub-rx",
  6491. .no_pcm = 1,
  6492. .dpcm_playback = 1,
  6493. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_RX,
  6494. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6495. .ignore_pmdown_time = 1,
  6496. .ignore_suspend = 1,
  6497. },
  6498. {
  6499. .name = LPASS_BE_QUIN_AUXPCM_TX,
  6500. .stream_name = "Quin AUX PCM Capture",
  6501. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  6502. .platform_name = "msm-pcm-routing",
  6503. .codec_name = "msm-stub-codec.1",
  6504. .codec_dai_name = "msm-stub-tx",
  6505. .no_pcm = 1,
  6506. .dpcm_capture = 1,
  6507. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_TX,
  6508. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6509. .ignore_suspend = 1,
  6510. },
  6511. };
  6512. static struct snd_soc_dai_link msm_wsa_cdc_dma_be_dai_links[] = {
  6513. /* WSA CDC DMA Backend DAI Links */
  6514. {
  6515. .name = LPASS_BE_WSA_CDC_DMA_RX_0,
  6516. .stream_name = "WSA CDC DMA0 Playback",
  6517. .cpu_dai_name = "msm-dai-cdc-dma-dev.45056",
  6518. .platform_name = "msm-pcm-routing",
  6519. .codec_name = "bolero_codec",
  6520. .codec_dai_name = "wsa_macro_rx1",
  6521. .no_pcm = 1,
  6522. .dpcm_playback = 1,
  6523. .init = &msm_wsa_cdc_dma_init,
  6524. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0,
  6525. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6526. .ignore_pmdown_time = 1,
  6527. .ignore_suspend = 1,
  6528. .ops = &msm_cdc_dma_be_ops,
  6529. },
  6530. {
  6531. .name = LPASS_BE_WSA_CDC_DMA_RX_1,
  6532. .stream_name = "WSA CDC DMA1 Playback",
  6533. .cpu_dai_name = "msm-dai-cdc-dma-dev.45058",
  6534. .platform_name = "msm-pcm-routing",
  6535. .codec_name = "bolero_codec",
  6536. .codec_dai_name = "wsa_macro_rx_mix",
  6537. .no_pcm = 1,
  6538. .dpcm_playback = 1,
  6539. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1,
  6540. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6541. .ignore_pmdown_time = 1,
  6542. .ignore_suspend = 1,
  6543. .ops = &msm_cdc_dma_be_ops,
  6544. },
  6545. {
  6546. .name = LPASS_BE_WSA_CDC_DMA_TX_1,
  6547. .stream_name = "WSA CDC DMA1 Capture",
  6548. .cpu_dai_name = "msm-dai-cdc-dma-dev.45059",
  6549. .platform_name = "msm-pcm-routing",
  6550. .codec_name = "bolero_codec",
  6551. .codec_dai_name = "wsa_macro_echo",
  6552. .no_pcm = 1,
  6553. .dpcm_capture = 1,
  6554. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1,
  6555. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6556. .ignore_suspend = 1,
  6557. .ops = &msm_cdc_dma_be_ops,
  6558. },
  6559. };
  6560. static struct snd_soc_dai_link msm_va_cdc_dma_be_dai_links[] = {
  6561. {
  6562. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  6563. .stream_name = "VA CDC DMA0 Capture",
  6564. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  6565. .platform_name = "msm-pcm-routing",
  6566. .codec_name = "bolero_codec",
  6567. .codec_dai_name = "va_macro_tx1",
  6568. .no_pcm = 1,
  6569. .dpcm_capture = 1,
  6570. .init = &msm_va_cdc_dma_init,
  6571. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  6572. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6573. .ignore_suspend = 1,
  6574. .ops = &msm_cdc_dma_be_ops,
  6575. },
  6576. {
  6577. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  6578. .stream_name = "VA CDC DMA1 Capture",
  6579. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  6580. .platform_name = "msm-pcm-routing",
  6581. .codec_name = "bolero_codec",
  6582. .codec_dai_name = "va_macro_tx2",
  6583. .no_pcm = 1,
  6584. .dpcm_capture = 1,
  6585. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  6586. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6587. .ignore_suspend = 1,
  6588. .ops = &msm_cdc_dma_be_ops,
  6589. },
  6590. };
  6591. static struct snd_soc_dai_link msm_spdif_be_dai_links[] = {
  6592. {
  6593. .name = LPASS_BE_PRI_SPDIF_RX,
  6594. .stream_name = "Primary SPDIF Playback",
  6595. .cpu_dai_name = "msm-dai-q6-spdif.20480",
  6596. .platform_name = "msm-pcm-routing",
  6597. .codec_name = "msm-stub-codec.1",
  6598. .codec_dai_name = "msm-stub-rx",
  6599. .no_pcm = 1,
  6600. .dpcm_playback = 1,
  6601. .id = MSM_BACKEND_DAI_PRI_SPDIF_RX,
  6602. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6603. .ops = &msm_spdif_be_ops,
  6604. .ignore_suspend = 1,
  6605. .ignore_pmdown_time = 1,
  6606. },
  6607. {
  6608. .name = LPASS_BE_PRI_SPDIF_TX,
  6609. .stream_name = "Primary SPDIF Capture",
  6610. .cpu_dai_name = "msm-dai-q6-spdif.20481",
  6611. .platform_name = "msm-pcm-routing",
  6612. .codec_name = "msm-stub-codec.1",
  6613. .codec_dai_name = "msm-stub-tx",
  6614. .no_pcm = 1,
  6615. .dpcm_capture = 1,
  6616. .id = MSM_BACKEND_DAI_PRI_SPDIF_TX,
  6617. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6618. .ops = &msm_spdif_be_ops,
  6619. .ignore_suspend = 1,
  6620. },
  6621. {
  6622. .name = LPASS_BE_SEC_SPDIF_RX,
  6623. .stream_name = "Secondary SPDIF Playback",
  6624. .cpu_dai_name = "msm-dai-q6-spdif.20482",
  6625. .platform_name = "msm-pcm-routing",
  6626. .codec_name = "msm-stub-codec.1",
  6627. .codec_dai_name = "msm-stub-rx",
  6628. .no_pcm = 1,
  6629. .dpcm_playback = 1,
  6630. .id = MSM_BACKEND_DAI_SEC_SPDIF_RX,
  6631. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6632. .ops = &msm_spdif_be_ops,
  6633. .ignore_suspend = 1,
  6634. .ignore_pmdown_time = 1,
  6635. },
  6636. {
  6637. .name = LPASS_BE_SEC_SPDIF_TX,
  6638. .stream_name = "Secondary SPDIF Capture",
  6639. .cpu_dai_name = "msm-dai-q6-spdif.20483",
  6640. .platform_name = "msm-pcm-routing",
  6641. .codec_name = "msm-stub-codec.1",
  6642. .codec_dai_name = "msm-stub-tx",
  6643. .no_pcm = 1,
  6644. .dpcm_capture = 1,
  6645. .id = MSM_BACKEND_DAI_SEC_SPDIF_TX,
  6646. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6647. .ops = &msm_spdif_be_ops,
  6648. .ignore_suspend = 1,
  6649. },
  6650. };
  6651. static struct snd_soc_dai_link msm_qcs405_dai_links[
  6652. ARRAY_SIZE(msm_common_dai_links) +
  6653. ARRAY_SIZE(msm_common_misc_fe_dai_links) +
  6654. ARRAY_SIZE(msm_common_be_dai_links) +
  6655. ARRAY_SIZE(msm_tasha_be_dai_links) +
  6656. ARRAY_SIZE(msm_wcn_be_dai_links) +
  6657. ARRAY_SIZE(msm_mi2s_be_dai_links) +
  6658. ARRAY_SIZE(msm_auxpcm_be_dai_links) +
  6659. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links) +
  6660. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links) +
  6661. ARRAY_SIZE(msm_bolero_fe_dai_links) +
  6662. ARRAY_SIZE(msm_spdif_be_dai_links)];
  6663. static int msm_snd_card_tasha_late_probe(struct snd_soc_card *card)
  6664. {
  6665. int ret = 0;
  6666. ret = audio_notifier_register("qcs405", AUDIO_NOTIFIER_ADSP_DOMAIN,
  6667. &service_nb);
  6668. if (ret < 0)
  6669. pr_err("%s: Audio notifier register failed ret = %d\n",
  6670. __func__, ret);
  6671. return ret;
  6672. }
  6673. static int msm_snd_vad_cfg_put(struct snd_kcontrol *kcontrol,
  6674. struct snd_ctl_elem_value *ucontrol)
  6675. {
  6676. int ret = 0;
  6677. int port_id;
  6678. uint32_t vad_enable = ucontrol->value.integer.value[0];
  6679. uint32_t preroll_config = ucontrol->value.integer.value[1];
  6680. uint32_t vad_intf = ucontrol->value.integer.value[2];
  6681. if ((preroll_config < 0) || (preroll_config > 1000) ||
  6682. (vad_enable < 0) || (vad_enable > 1) ||
  6683. (vad_intf > MSM_BACKEND_DAI_MAX)) {
  6684. pr_err("%s: Invalid arguments\n", __func__);
  6685. ret = -EINVAL;
  6686. goto done;
  6687. }
  6688. pr_debug("%s: vad_enable=%d preroll_config=%d vad_intf=%d\n", __func__,
  6689. vad_enable, preroll_config, vad_intf);
  6690. ret = msm_vad_get_portid_from_beid(vad_intf, &port_id);
  6691. if (ret) {
  6692. pr_err("%s: Invalid vad interface\n", __func__);
  6693. goto done;
  6694. }
  6695. afe_set_vad_cfg(vad_enable, preroll_config, port_id);
  6696. done:
  6697. return ret;
  6698. }
  6699. static int msm_snd_card_codec_late_probe(struct snd_soc_card *card)
  6700. {
  6701. int ret = 0;
  6702. uint32_t tasha_codec = 0;
  6703. ret = afe_cal_init_hwdep(card);
  6704. if (ret) {
  6705. dev_err(card->dev, "afe cal hwdep init failed (%d)\n", ret);
  6706. ret = 0;
  6707. }
  6708. /* tasha late probe when it is present */
  6709. ret = of_property_read_u32(card->dev->of_node, "qcom,tasha-codec",
  6710. &tasha_codec);
  6711. if (ret) {
  6712. dev_err(card->dev, "%s: No DT match tasha codec\n", __func__);
  6713. ret = 0;
  6714. } else {
  6715. if (tasha_codec) {
  6716. ret = msm_snd_card_tasha_late_probe(card);
  6717. if (ret)
  6718. dev_err(card->dev, "%s: tasha late probe err\n",
  6719. __func__);
  6720. }
  6721. }
  6722. return ret;
  6723. }
  6724. struct snd_soc_card snd_soc_card_qcs405_msm = {
  6725. .name = "qcs405-snd-card",
  6726. .controls = msm_snd_controls,
  6727. .num_controls = ARRAY_SIZE(msm_snd_controls),
  6728. .late_probe = msm_snd_card_codec_late_probe,
  6729. };
  6730. static int msm_populate_dai_link_component_of_node(
  6731. struct snd_soc_card *card)
  6732. {
  6733. int i, index, ret = 0;
  6734. struct device *cdev = card->dev;
  6735. struct snd_soc_dai_link *dai_link = card->dai_link;
  6736. struct device_node *np;
  6737. if (!cdev) {
  6738. pr_err("%s: Sound card device memory NULL\n", __func__);
  6739. return -ENODEV;
  6740. }
  6741. for (i = 0; i < card->num_links; i++) {
  6742. if (dai_link[i].platform_of_node && dai_link[i].cpu_of_node)
  6743. continue;
  6744. /* populate platform_of_node for snd card dai links */
  6745. if (dai_link[i].platform_name &&
  6746. !dai_link[i].platform_of_node) {
  6747. index = of_property_match_string(cdev->of_node,
  6748. "asoc-platform-names",
  6749. dai_link[i].platform_name);
  6750. if (index < 0) {
  6751. pr_err("%s: No match found for platform name: %s\n",
  6752. __func__, dai_link[i].platform_name);
  6753. ret = index;
  6754. goto err;
  6755. }
  6756. np = of_parse_phandle(cdev->of_node, "asoc-platform",
  6757. index);
  6758. if (!np) {
  6759. pr_err("%s: retrieving phandle for platform %s, index %d failed\n",
  6760. __func__, dai_link[i].platform_name,
  6761. index);
  6762. ret = -ENODEV;
  6763. goto err;
  6764. }
  6765. dai_link[i].platform_of_node = np;
  6766. dai_link[i].platform_name = NULL;
  6767. }
  6768. /* populate cpu_of_node for snd card dai links */
  6769. if (dai_link[i].cpu_dai_name && !dai_link[i].cpu_of_node) {
  6770. index = of_property_match_string(cdev->of_node,
  6771. "asoc-cpu-names",
  6772. dai_link[i].cpu_dai_name);
  6773. if (index >= 0) {
  6774. np = of_parse_phandle(cdev->of_node, "asoc-cpu",
  6775. index);
  6776. if (!np) {
  6777. pr_err("%s: retrieving phandle for cpu dai %s failed\n",
  6778. __func__,
  6779. dai_link[i].cpu_dai_name);
  6780. ret = -ENODEV;
  6781. goto err;
  6782. }
  6783. dai_link[i].cpu_of_node = np;
  6784. dai_link[i].cpu_dai_name = NULL;
  6785. }
  6786. }
  6787. /* populate codec_of_node for snd card dai links */
  6788. if (dai_link[i].codec_name && !dai_link[i].codec_of_node) {
  6789. index = of_property_match_string(cdev->of_node,
  6790. "asoc-codec-names",
  6791. dai_link[i].codec_name);
  6792. if (index < 0)
  6793. continue;
  6794. np = of_parse_phandle(cdev->of_node, "asoc-codec",
  6795. index);
  6796. if (!np) {
  6797. pr_err("%s: retrieving phandle for codec %s failed\n",
  6798. __func__, dai_link[i].codec_name);
  6799. ret = -ENODEV;
  6800. goto err;
  6801. }
  6802. dai_link[i].codec_of_node = np;
  6803. dai_link[i].codec_name = NULL;
  6804. }
  6805. }
  6806. err:
  6807. return ret;
  6808. }
  6809. static struct snd_soc_dai_link msm_stub_fe_dai_links[] = {
  6810. /* FrontEnd DAI Links */
  6811. {
  6812. .name = "MSMSTUB Media1",
  6813. .stream_name = "MultiMedia1",
  6814. .cpu_dai_name = "MultiMedia1",
  6815. .platform_name = "msm-pcm-dsp.0",
  6816. .dynamic = 1,
  6817. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  6818. .dpcm_playback = 1,
  6819. .dpcm_capture = 1,
  6820. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6821. SND_SOC_DPCM_TRIGGER_POST},
  6822. .codec_dai_name = "snd-soc-dummy-dai",
  6823. .codec_name = "snd-soc-dummy",
  6824. .ignore_suspend = 1,
  6825. /* this dainlink has playback support */
  6826. .ignore_pmdown_time = 1,
  6827. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  6828. },
  6829. };
  6830. static struct snd_soc_dai_link msm_stub_be_dai_links[] = {
  6831. /* Backend DAI Links */
  6832. {
  6833. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  6834. .stream_name = "VA CDC DMA0 Capture",
  6835. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  6836. .platform_name = "msm-pcm-routing",
  6837. .codec_name = "bolero_codec",
  6838. .codec_dai_name = "va_macro_tx1",
  6839. .no_pcm = 1,
  6840. .dpcm_capture = 1,
  6841. .init = &msm_va_cdc_dma_init,
  6842. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  6843. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6844. .ignore_suspend = 1,
  6845. .ops = &msm_cdc_dma_be_ops,
  6846. },
  6847. {
  6848. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  6849. .stream_name = "VA CDC DMA1 Capture",
  6850. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  6851. .platform_name = "msm-pcm-routing",
  6852. .codec_name = "bolero_codec",
  6853. .codec_dai_name = "va_macro_tx2",
  6854. .no_pcm = 1,
  6855. .dpcm_capture = 1,
  6856. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  6857. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6858. .ignore_suspend = 1,
  6859. .ops = &msm_cdc_dma_be_ops,
  6860. },
  6861. };
  6862. static struct snd_soc_dai_link msm_stub_dai_links[
  6863. ARRAY_SIZE(msm_stub_fe_dai_links) +
  6864. ARRAY_SIZE(msm_stub_be_dai_links)];
  6865. struct snd_soc_card snd_soc_card_stub_msm = {
  6866. .name = "qcs405-stub-snd-card",
  6867. };
  6868. static const struct of_device_id qcs405_asoc_machine_of_match[] = {
  6869. { .compatible = "qcom,qcs405-asoc-snd",
  6870. .data = "codec"},
  6871. { .compatible = "qcom,qcs405-asoc-snd-stub",
  6872. .data = "stub_codec"},
  6873. {},
  6874. };
  6875. static struct snd_soc_card *populate_snd_card_dailinks(struct device *dev)
  6876. {
  6877. struct snd_soc_card *card = NULL;
  6878. struct snd_soc_dai_link *dailink;
  6879. int total_links = 0;
  6880. uint32_t tasha_codec = 0, auxpcm_audio_intf = 0;
  6881. uint32_t va_bolero_codec = 0, wsa_bolero_codec = 0, mi2s_audio_intf = 0;
  6882. uint32_t spdif_audio_intf = 0, wcn_audio_intf = 0;
  6883. const struct of_device_id *match;
  6884. char __iomem *spdif_cfg, *spdif_pin_ctl;
  6885. int rc = 0;
  6886. match = of_match_node(qcs405_asoc_machine_of_match, dev->of_node);
  6887. if (!match) {
  6888. dev_err(dev, "%s: No DT match found for sound card\n",
  6889. __func__);
  6890. return NULL;
  6891. }
  6892. if (!strcmp(match->data, "codec")) {
  6893. card = &snd_soc_card_qcs405_msm;
  6894. memcpy(msm_qcs405_dai_links + total_links,
  6895. msm_common_dai_links,
  6896. sizeof(msm_common_dai_links));
  6897. total_links += ARRAY_SIZE(msm_common_dai_links);
  6898. rc = of_property_read_u32(dev->of_node, "qcom,wsa-bolero-codec",
  6899. &wsa_bolero_codec);
  6900. if (rc) {
  6901. dev_dbg(dev, "%s: No DT match WSA Macro codec\n",
  6902. __func__);
  6903. } else {
  6904. if (wsa_bolero_codec) {
  6905. dev_dbg(dev, "%s(): WSA macro in bolero codec present\n",
  6906. __func__);
  6907. memcpy(msm_qcs405_dai_links + total_links,
  6908. msm_bolero_fe_dai_links,
  6909. sizeof(msm_bolero_fe_dai_links));
  6910. total_links +=
  6911. ARRAY_SIZE(msm_bolero_fe_dai_links);
  6912. }
  6913. }
  6914. memcpy(msm_qcs405_dai_links + total_links,
  6915. msm_common_misc_fe_dai_links,
  6916. sizeof(msm_common_misc_fe_dai_links));
  6917. total_links += ARRAY_SIZE(msm_common_misc_fe_dai_links);
  6918. memcpy(msm_qcs405_dai_links + total_links,
  6919. msm_common_be_dai_links,
  6920. sizeof(msm_common_be_dai_links));
  6921. total_links += ARRAY_SIZE(msm_common_be_dai_links);
  6922. rc = of_property_read_u32(dev->of_node, "qcom,tasha-codec",
  6923. &tasha_codec);
  6924. if (rc) {
  6925. dev_dbg(dev, "%s: No DT match tasha codec\n",
  6926. __func__);
  6927. } else {
  6928. if (tasha_codec) {
  6929. memcpy(msm_qcs405_dai_links + total_links,
  6930. msm_tasha_be_dai_links,
  6931. sizeof(msm_tasha_be_dai_links));
  6932. total_links +=
  6933. ARRAY_SIZE(msm_tasha_be_dai_links);
  6934. }
  6935. }
  6936. rc = of_property_read_u32(dev->of_node, "qcom,va-bolero-codec",
  6937. &va_bolero_codec);
  6938. if (rc) {
  6939. dev_dbg(dev, "%s: No DT match VA Macro codec\n",
  6940. __func__);
  6941. } else {
  6942. if (va_bolero_codec) {
  6943. dev_dbg(dev, "%s(): VA macro in bolero codec present\n",
  6944. __func__);
  6945. memcpy(msm_qcs405_dai_links + total_links,
  6946. msm_va_cdc_dma_be_dai_links,
  6947. sizeof(msm_va_cdc_dma_be_dai_links));
  6948. total_links +=
  6949. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links);
  6950. }
  6951. }
  6952. if (wsa_bolero_codec) {
  6953. dev_dbg(dev, "%s(): WSAmacro in bolero codec present\n",
  6954. __func__);
  6955. memcpy(msm_qcs405_dai_links + total_links,
  6956. msm_wsa_cdc_dma_be_dai_links,
  6957. sizeof(msm_wsa_cdc_dma_be_dai_links));
  6958. total_links +=
  6959. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links);
  6960. }
  6961. rc = of_property_read_u32(dev->of_node, "qcom,mi2s-audio-intf",
  6962. &mi2s_audio_intf);
  6963. if (rc) {
  6964. dev_dbg(dev, "%s: No DT match MI2S audio interface\n",
  6965. __func__);
  6966. } else {
  6967. if (mi2s_audio_intf) {
  6968. memcpy(msm_qcs405_dai_links + total_links,
  6969. msm_mi2s_be_dai_links,
  6970. sizeof(msm_mi2s_be_dai_links));
  6971. total_links +=
  6972. ARRAY_SIZE(msm_mi2s_be_dai_links);
  6973. }
  6974. }
  6975. rc = of_property_read_u32(dev->of_node,
  6976. "qcom,auxpcm-audio-intf",
  6977. &auxpcm_audio_intf);
  6978. if (rc) {
  6979. dev_dbg(dev, "%s: No DT match Aux PCM interface\n",
  6980. __func__);
  6981. } else {
  6982. if (auxpcm_audio_intf) {
  6983. memcpy(msm_qcs405_dai_links + total_links,
  6984. msm_auxpcm_be_dai_links,
  6985. sizeof(msm_auxpcm_be_dai_links));
  6986. total_links +=
  6987. ARRAY_SIZE(msm_auxpcm_be_dai_links);
  6988. }
  6989. }
  6990. rc = of_property_read_u32(dev->of_node, "qcom,spdif-audio-intf",
  6991. &spdif_audio_intf);
  6992. if (rc) {
  6993. dev_dbg(dev, "%s: No DT match SPDIF audio interface\n",
  6994. __func__);
  6995. } else {
  6996. if (spdif_audio_intf) {
  6997. memcpy(msm_qcs405_dai_links + total_links,
  6998. msm_spdif_be_dai_links,
  6999. sizeof(msm_spdif_be_dai_links));
  7000. total_links +=
  7001. ARRAY_SIZE(msm_spdif_be_dai_links);
  7002. /* enable spdif coax pins */
  7003. spdif_cfg = ioremap(TLMM_EAST_SPARE, 0x4);
  7004. spdif_pin_ctl =
  7005. ioremap(TLMM_SPDIF_HDMI_ARC_CTL, 0x4);
  7006. iowrite32(0xc0, spdif_cfg);
  7007. iowrite32(0x2220, spdif_pin_ctl);
  7008. }
  7009. }
  7010. rc = of_property_read_u32(dev->of_node, "qcom,wcn-btfm",
  7011. &wcn_audio_intf);
  7012. if (rc) {
  7013. dev_dbg(dev, "%s: No DT match WCN audio interface\n",
  7014. __func__);
  7015. } else {
  7016. if (wcn_audio_intf) {
  7017. memcpy(msm_qcs405_dai_links + total_links,
  7018. msm_wcn_be_dai_links,
  7019. sizeof(msm_wcn_be_dai_links));
  7020. total_links +=
  7021. ARRAY_SIZE(msm_wcn_be_dai_links);
  7022. }
  7023. }
  7024. dailink = msm_qcs405_dai_links;
  7025. } else if (!strcmp(match->data, "stub_codec")) {
  7026. card = &snd_soc_card_stub_msm;
  7027. memcpy(msm_stub_dai_links + total_links,
  7028. msm_stub_fe_dai_links,
  7029. sizeof(msm_stub_fe_dai_links));
  7030. total_links += ARRAY_SIZE(msm_stub_fe_dai_links);
  7031. memcpy(msm_stub_dai_links + total_links,
  7032. msm_stub_be_dai_links,
  7033. sizeof(msm_stub_be_dai_links));
  7034. total_links += ARRAY_SIZE(msm_stub_be_dai_links);
  7035. dailink = msm_stub_dai_links;
  7036. }
  7037. if (card) {
  7038. card->dai_link = dailink;
  7039. card->num_links = total_links;
  7040. }
  7041. return card;
  7042. }
  7043. static int msm_wsa881x_init(struct snd_soc_component *component)
  7044. {
  7045. u8 spkleft_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  7046. u8 spkright_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  7047. u8 spkleft_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_L, SPKR_L_COMP,
  7048. SPKR_L_BOOST, SPKR_L_VI};
  7049. u8 spkright_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_R, SPKR_R_COMP,
  7050. SPKR_R_BOOST, SPKR_R_VI};
  7051. unsigned int ch_rate[WSA881X_MAX_SWR_PORTS] = {2400, 600, 300, 1200};
  7052. unsigned int ch_mask[WSA881X_MAX_SWR_PORTS] = {0x1, 0xF, 0x3, 0x3};
  7053. struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
  7054. struct msm_asoc_mach_data *pdata;
  7055. struct snd_soc_dapm_context *dapm;
  7056. int ret = 0;
  7057. if (!codec) {
  7058. pr_err("%s codec is NULL\n", __func__);
  7059. return -EINVAL;
  7060. }
  7061. dapm = snd_soc_codec_get_dapm(codec);
  7062. if (!strcmp(component->name_prefix, "SpkrLeft")) {
  7063. dev_dbg(codec->dev, "%s: setting left ch map to codec %s\n",
  7064. __func__, codec->component.name);
  7065. wsa881x_set_channel_map(codec, &spkleft_ports[0],
  7066. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  7067. &ch_rate[0], &spkleft_port_types[0]);
  7068. if (dapm->component) {
  7069. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft IN");
  7070. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft SPKR");
  7071. }
  7072. } else if (!strcmp(component->name_prefix, "SpkrRight")) {
  7073. dev_dbg(codec->dev, "%s: setting right ch map to codec %s\n",
  7074. __func__, codec->component.name);
  7075. wsa881x_set_channel_map(codec, &spkright_ports[0],
  7076. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  7077. &ch_rate[0], &spkright_port_types[0]);
  7078. if (dapm->component) {
  7079. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight IN");
  7080. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight SPKR");
  7081. }
  7082. } else {
  7083. dev_err(codec->dev, "%s: wrong codec name %s\n", __func__,
  7084. codec->component.name);
  7085. ret = -EINVAL;
  7086. goto err;
  7087. }
  7088. pdata = snd_soc_card_get_drvdata(component->card);
  7089. if (pdata && pdata->codec_root)
  7090. wsa881x_codec_info_create_codec_entry(pdata->codec_root,
  7091. codec);
  7092. err:
  7093. return ret;
  7094. }
  7095. static int msm_init_wsa_dev(struct platform_device *pdev,
  7096. struct snd_soc_card *card)
  7097. {
  7098. struct device_node *wsa_of_node;
  7099. u32 wsa_max_devs;
  7100. u32 wsa_dev_cnt;
  7101. int i;
  7102. struct msm_wsa881x_dev_info *wsa881x_dev_info;
  7103. const char *wsa_auxdev_name_prefix[1];
  7104. char *dev_name_str = NULL;
  7105. int found = 0;
  7106. int ret = 0;
  7107. /* Get maximum WSA device count for this platform */
  7108. ret = of_property_read_u32(pdev->dev.of_node,
  7109. "qcom,wsa-max-devs", &wsa_max_devs);
  7110. if (ret) {
  7111. dev_info(&pdev->dev,
  7112. "%s: wsa-max-devs property missing in DT %s, ret = %d\n",
  7113. __func__, pdev->dev.of_node->full_name, ret);
  7114. card->num_aux_devs = 0;
  7115. return 0;
  7116. }
  7117. if (wsa_max_devs == 0) {
  7118. dev_warn(&pdev->dev,
  7119. "%s: Max WSA devices is 0 for this target?\n",
  7120. __func__);
  7121. card->num_aux_devs = 0;
  7122. return 0;
  7123. }
  7124. /* Get count of WSA device phandles for this platform */
  7125. wsa_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  7126. "qcom,wsa-devs", NULL);
  7127. if (wsa_dev_cnt == -ENOENT) {
  7128. dev_warn(&pdev->dev, "%s: No wsa device defined in DT.\n",
  7129. __func__);
  7130. goto err;
  7131. } else if (wsa_dev_cnt <= 0) {
  7132. dev_err(&pdev->dev,
  7133. "%s: Error reading wsa device from DT. wsa_dev_cnt = %d\n",
  7134. __func__, wsa_dev_cnt);
  7135. ret = -EINVAL;
  7136. goto err;
  7137. }
  7138. /*
  7139. * Expect total phandles count to be NOT less than maximum possible
  7140. * WSA count. However, if it is less, then assign same value to
  7141. * max count as well.
  7142. */
  7143. if (wsa_dev_cnt < wsa_max_devs) {
  7144. dev_dbg(&pdev->dev,
  7145. "%s: wsa_max_devs = %d cannot exceed wsa_dev_cnt = %d\n",
  7146. __func__, wsa_max_devs, wsa_dev_cnt);
  7147. wsa_max_devs = wsa_dev_cnt;
  7148. }
  7149. /* Make sure prefix string passed for each WSA device */
  7150. ret = of_property_count_strings(pdev->dev.of_node,
  7151. "qcom,wsa-aux-dev-prefix");
  7152. if (ret != wsa_dev_cnt) {
  7153. dev_err(&pdev->dev,
  7154. "%s: expecting %d wsa prefix. Defined only %d in DT\n",
  7155. __func__, wsa_dev_cnt, ret);
  7156. ret = -EINVAL;
  7157. goto err;
  7158. }
  7159. /*
  7160. * Alloc mem to store phandle and index info of WSA device, if already
  7161. * registered with ALSA core
  7162. */
  7163. wsa881x_dev_info = devm_kcalloc(&pdev->dev, wsa_max_devs,
  7164. sizeof(struct msm_wsa881x_dev_info),
  7165. GFP_KERNEL);
  7166. if (!wsa881x_dev_info) {
  7167. ret = -ENOMEM;
  7168. goto err;
  7169. }
  7170. /*
  7171. * search and check whether all WSA devices are already
  7172. * registered with ALSA core or not. If found a node, store
  7173. * the node and the index in a local array of struct for later
  7174. * use.
  7175. */
  7176. for (i = 0; i < wsa_dev_cnt; i++) {
  7177. wsa_of_node = of_parse_phandle(pdev->dev.of_node,
  7178. "qcom,wsa-devs", i);
  7179. if (unlikely(!wsa_of_node)) {
  7180. /* we should not be here */
  7181. dev_err(&pdev->dev,
  7182. "%s: wsa dev node is not present\n",
  7183. __func__);
  7184. ret = -EINVAL;
  7185. goto err_free_dev_info;
  7186. }
  7187. if (soc_find_component(wsa_of_node, NULL)) {
  7188. /* WSA device registered with ALSA core */
  7189. wsa881x_dev_info[found].of_node = wsa_of_node;
  7190. wsa881x_dev_info[found].index = i;
  7191. found++;
  7192. if (found == wsa_max_devs)
  7193. break;
  7194. }
  7195. }
  7196. if (found < wsa_max_devs) {
  7197. dev_err(&pdev->dev,
  7198. "%s: failed to find %d components. Found only %d\n",
  7199. __func__, wsa_max_devs, found);
  7200. return -EPROBE_DEFER;
  7201. }
  7202. dev_info(&pdev->dev,
  7203. "%s: found %d wsa881x devices registered with ALSA core\n",
  7204. __func__, found);
  7205. card->num_aux_devs = wsa_max_devs;
  7206. card->num_configs = wsa_max_devs;
  7207. /* Alloc array of AUX devs struct */
  7208. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7209. sizeof(struct snd_soc_aux_dev),
  7210. GFP_KERNEL);
  7211. if (!msm_aux_dev) {
  7212. ret = -ENOMEM;
  7213. goto err_free_dev_info;
  7214. }
  7215. /* Alloc array of codec conf struct */
  7216. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7217. sizeof(struct snd_soc_codec_conf),
  7218. GFP_KERNEL);
  7219. if (!msm_codec_conf) {
  7220. ret = -ENOMEM;
  7221. goto err_free_aux_dev;
  7222. }
  7223. for (i = 0; i < card->num_aux_devs; i++) {
  7224. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  7225. GFP_KERNEL);
  7226. if (!dev_name_str) {
  7227. ret = -ENOMEM;
  7228. goto err_free_cdc_conf;
  7229. }
  7230. ret = of_property_read_string_index(pdev->dev.of_node,
  7231. "qcom,wsa-aux-dev-prefix",
  7232. wsa881x_dev_info[i].index,
  7233. wsa_auxdev_name_prefix);
  7234. if (ret) {
  7235. dev_err(&pdev->dev,
  7236. "%s: failed to read wsa aux dev prefix, ret = %d\n",
  7237. __func__, ret);
  7238. ret = -EINVAL;
  7239. goto err_free_dev_name_str;
  7240. }
  7241. snprintf(dev_name_str, strlen("wsa881x.%d"), "wsa881x.%d", i);
  7242. msm_aux_dev[i].name = dev_name_str;
  7243. msm_aux_dev[i].codec_name = NULL;
  7244. msm_aux_dev[i].codec_of_node =
  7245. wsa881x_dev_info[i].of_node;
  7246. msm_aux_dev[i].init = msm_wsa881x_init;
  7247. msm_codec_conf[i].dev_name = NULL;
  7248. msm_codec_conf[i].name_prefix = wsa_auxdev_name_prefix[0];
  7249. msm_codec_conf[i].of_node =
  7250. wsa881x_dev_info[i].of_node;
  7251. }
  7252. card->codec_conf = msm_codec_conf;
  7253. card->aux_dev = msm_aux_dev;
  7254. return 0;
  7255. err_free_dev_name_str:
  7256. devm_kfree(&pdev->dev, dev_name_str);
  7257. err_free_cdc_conf:
  7258. devm_kfree(&pdev->dev, msm_codec_conf);
  7259. err_free_aux_dev:
  7260. devm_kfree(&pdev->dev, msm_aux_dev);
  7261. err_free_dev_info:
  7262. devm_kfree(&pdev->dev, wsa881x_dev_info);
  7263. err:
  7264. return ret;
  7265. }
  7266. static int msm_csra66x0_init(struct snd_soc_component *component)
  7267. {
  7268. struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
  7269. if (!codec) {
  7270. pr_err("%s codec is NULL\n", __func__);
  7271. return -EINVAL;
  7272. }
  7273. return 0;
  7274. }
  7275. static int msm_init_csra_dev(struct platform_device *pdev,
  7276. struct snd_soc_card *card)
  7277. {
  7278. struct device_node *csra_of_node;
  7279. u32 csra_max_devs;
  7280. u32 csra_dev_cnt;
  7281. char *dev_name_str = NULL;
  7282. struct msm_csra66x0_dev_info *csra66x0_dev_info;
  7283. const char *csra_auxdev_name_prefix[1];
  7284. int i;
  7285. int found = 0;
  7286. int ret = 0;
  7287. /* Get maximum CSRA device count for this platform */
  7288. ret = of_property_read_u32(pdev->dev.of_node,
  7289. "qcom,csra-max-devs", &csra_max_devs);
  7290. if (ret) {
  7291. dev_info(&pdev->dev,
  7292. "%s: csra-max-devs property missing in DT %s, ret = %d\n",
  7293. __func__, pdev->dev.of_node->full_name, ret);
  7294. card->num_aux_devs = 0;
  7295. return 0;
  7296. }
  7297. if (csra_max_devs == 0) {
  7298. dev_warn(&pdev->dev,
  7299. "%s: Max CSRA devices is 0 for this target?\n",
  7300. __func__);
  7301. return 0;
  7302. }
  7303. /* Get count of CSRA device phandles for this platform */
  7304. csra_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  7305. "qcom,csra-devs", NULL);
  7306. if (csra_dev_cnt == -ENOENT) {
  7307. dev_warn(&pdev->dev, "%s: No csra device defined in DT.\n",
  7308. __func__);
  7309. goto err;
  7310. } else if (csra_dev_cnt <= 0) {
  7311. dev_err(&pdev->dev,
  7312. "%s: Error reading csra device from DT. csra_dev_cnt = %d\n",
  7313. __func__, csra_dev_cnt);
  7314. ret = -EINVAL;
  7315. goto err;
  7316. }
  7317. /*
  7318. * Expect total phandles count to be NOT less than maximum possible
  7319. * CSRA count. However, if it is less, then assign same value to
  7320. * max count as well.
  7321. */
  7322. if (csra_dev_cnt < csra_max_devs) {
  7323. dev_dbg(&pdev->dev,
  7324. "%s: csra_max_devs = %d cannot exceed csra_dev_cnt = %d\n",
  7325. __func__, csra_max_devs, csra_dev_cnt);
  7326. csra_max_devs = csra_dev_cnt;
  7327. }
  7328. /* Make sure prefix string passed for each CSRA device */
  7329. ret = of_property_count_strings(pdev->dev.of_node,
  7330. "qcom,csra-aux-dev-prefix");
  7331. if (ret != csra_dev_cnt) {
  7332. dev_err(&pdev->dev,
  7333. "%s: expecting %d csra prefix. Defined only %d in DT\n",
  7334. __func__, csra_dev_cnt, ret);
  7335. ret = -EINVAL;
  7336. goto err;
  7337. }
  7338. /*
  7339. * Alloc mem to store phandle and index info of CSRA device, if already
  7340. * registered with ALSA core
  7341. */
  7342. csra66x0_dev_info = devm_kcalloc(&pdev->dev, csra_max_devs,
  7343. sizeof(struct msm_csra66x0_dev_info),
  7344. GFP_KERNEL);
  7345. if (!csra66x0_dev_info) {
  7346. ret = -ENOMEM;
  7347. goto err;
  7348. }
  7349. /*
  7350. * search and check whether all CSRA devices are already
  7351. * registered with ALSA core or not. If found a node, store
  7352. * the node and the index in a local array of struct for later
  7353. * use.
  7354. */
  7355. for (i = 0; i < csra_dev_cnt; i++) {
  7356. csra_of_node = of_parse_phandle(pdev->dev.of_node,
  7357. "qcom,csra-devs", i);
  7358. if (unlikely(!csra_of_node)) {
  7359. /* we should not be here */
  7360. dev_err(&pdev->dev,
  7361. "%s: csra dev node is not present\n",
  7362. __func__);
  7363. ret = -EINVAL;
  7364. goto err_free_dev_info;
  7365. }
  7366. if (soc_find_component(csra_of_node, NULL)) {
  7367. /* CSRA device registered with ALSA core */
  7368. csra66x0_dev_info[found].of_node = csra_of_node;
  7369. csra66x0_dev_info[found].index = i;
  7370. found++;
  7371. if (found == csra_max_devs)
  7372. break;
  7373. }
  7374. }
  7375. if (found < csra_max_devs) {
  7376. dev_dbg(&pdev->dev,
  7377. "%s: failed to find %d components. Found only %d\n",
  7378. __func__, csra_max_devs, found);
  7379. return -EPROBE_DEFER;
  7380. }
  7381. dev_info(&pdev->dev,
  7382. "%s: found %d csra66x0 devices registered with ALSA core\n",
  7383. __func__, found);
  7384. card->num_aux_devs = csra_max_devs;
  7385. card->num_configs = csra_max_devs;
  7386. /* Alloc array of AUX devs struct */
  7387. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7388. sizeof(struct snd_soc_aux_dev), GFP_KERNEL);
  7389. if (!msm_aux_dev) {
  7390. ret = -ENOMEM;
  7391. goto err_free_dev_info;
  7392. }
  7393. /* Alloc array of codec conf struct */
  7394. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7395. sizeof(struct snd_soc_codec_conf), GFP_KERNEL);
  7396. if (!msm_codec_conf) {
  7397. ret = -ENOMEM;
  7398. goto err_free_aux_dev;
  7399. }
  7400. for (i = 0; i < card->num_aux_devs; i++) {
  7401. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  7402. GFP_KERNEL);
  7403. if (!dev_name_str) {
  7404. ret = -ENOMEM;
  7405. goto err_free_cdc_conf;
  7406. }
  7407. ret = of_property_read_string_index(pdev->dev.of_node,
  7408. "qcom,csra-aux-dev-prefix",
  7409. csra66x0_dev_info[i].index,
  7410. csra_auxdev_name_prefix);
  7411. if (ret) {
  7412. dev_err(&pdev->dev,
  7413. "%s: failed to read csra aux dev prefix, ret = %d\n",
  7414. __func__, ret);
  7415. ret = -EINVAL;
  7416. goto err_free_dev_name_str;
  7417. }
  7418. snprintf(dev_name_str, strlen("csra66x0.%d"), "csra66x0.%d", i);
  7419. msm_aux_dev[i].name = dev_name_str;
  7420. msm_aux_dev[i].codec_name = NULL;
  7421. msm_aux_dev[i].codec_of_node =
  7422. csra66x0_dev_info[i].of_node;
  7423. msm_aux_dev[i].init = msm_csra66x0_init; /* codec specific init */
  7424. msm_codec_conf[i].dev_name = NULL;
  7425. msm_codec_conf[i].name_prefix = csra_auxdev_name_prefix[0];
  7426. msm_codec_conf[i].of_node = csra66x0_dev_info[i].of_node;
  7427. }
  7428. card->codec_conf = msm_codec_conf;
  7429. card->aux_dev = msm_aux_dev;
  7430. return 0;
  7431. err_free_dev_name_str:
  7432. devm_kfree(&pdev->dev, dev_name_str);
  7433. err_free_cdc_conf:
  7434. devm_kfree(&pdev->dev, msm_codec_conf);
  7435. err_free_aux_dev:
  7436. devm_kfree(&pdev->dev, msm_aux_dev);
  7437. err_free_dev_info:
  7438. devm_kfree(&pdev->dev, csra66x0_dev_info);
  7439. err:
  7440. return ret;
  7441. }
  7442. static void msm_i2s_auxpcm_init(struct platform_device *pdev)
  7443. {
  7444. int count;
  7445. u32 mi2s_master_slave[MI2S_MAX];
  7446. int ret;
  7447. for (count = 0; count < MI2S_MAX; count++) {
  7448. mutex_init(&mi2s_intf_conf[count].lock);
  7449. mi2s_intf_conf[count].ref_cnt = 0;
  7450. }
  7451. ret = of_property_read_u32_array(pdev->dev.of_node,
  7452. "qcom,msm-mi2s-master",
  7453. mi2s_master_slave, MI2S_MAX);
  7454. if (ret) {
  7455. dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-master in DT node\n",
  7456. __func__);
  7457. } else {
  7458. for (count = 0; count < MI2S_MAX; count++) {
  7459. mi2s_intf_conf[count].msm_is_mi2s_master =
  7460. mi2s_master_slave[count];
  7461. }
  7462. }
  7463. }
  7464. static void msm_i2s_auxpcm_deinit(void)
  7465. {
  7466. int count;
  7467. for (count = 0; count < MI2S_MAX; count++) {
  7468. mutex_destroy(&mi2s_intf_conf[count].lock);
  7469. mi2s_intf_conf[count].ref_cnt = 0;
  7470. mi2s_intf_conf[count].msm_is_mi2s_master = 0;
  7471. }
  7472. }
  7473. static int msm_scan_i2c_addr(struct platform_device *pdev,
  7474. uint32_t busnum, uint32_t addr)
  7475. {
  7476. struct i2c_adapter *adap;
  7477. u8 rbuf;
  7478. struct i2c_msg msg;
  7479. int status = 0;
  7480. adap = i2c_get_adapter(busnum);
  7481. if (!adap) {
  7482. dev_err(&pdev->dev, "%s: Cannot get I2C adapter %d\n",
  7483. __func__, busnum);
  7484. return -EBUSY;
  7485. }
  7486. /* to test presence, read one byte from device */
  7487. msg.addr = addr;
  7488. msg.flags = I2C_M_RD;
  7489. msg.len = 1;
  7490. msg.buf = &rbuf;
  7491. status = i2c_transfer(adap, &msg, 1);
  7492. i2c_put_adapter(adap);
  7493. if (status != 1) {
  7494. dev_dbg(&pdev->dev, "%s: I2C read from addr 0x%02x failed\n",
  7495. __func__, addr);
  7496. return -ENODEV;
  7497. }
  7498. dev_dbg(&pdev->dev, "%s: I2C read from addr 0x%02x successful\n",
  7499. __func__, addr);
  7500. return 0;
  7501. }
  7502. static int msm_detect_ep92_dev(struct platform_device *pdev,
  7503. struct snd_soc_card *card)
  7504. {
  7505. int i;
  7506. uint32_t ep92_busnum = 0;
  7507. uint32_t ep92_reg = 0;
  7508. const char *ep92_name = NULL;
  7509. struct snd_soc_dai_link *dai;
  7510. int rc = 0;
  7511. rc = of_property_read_u32(pdev->dev.of_node, "qcom,ep92-busnum",
  7512. &ep92_busnum);
  7513. if (rc) {
  7514. dev_info(&pdev->dev, "%s: No DT match ep92-reg\n", __func__);
  7515. return 0;
  7516. }
  7517. rc = of_property_read_u32(pdev->dev.of_node, "qcom,ep92-reg",
  7518. &ep92_reg);
  7519. if (rc) {
  7520. dev_info(&pdev->dev, "%s: No DT match ep92-busnum\n", __func__);
  7521. return 0;
  7522. }
  7523. rc = of_property_read_string(pdev->dev.of_node, "qcom,ep92-name",
  7524. &ep92_name);
  7525. if (rc) {
  7526. dev_info(&pdev->dev, "%s: No DT match ep92-name\n", __func__);
  7527. return 0;
  7528. }
  7529. /* check I2C bus for connected ep92 chip */
  7530. if (msm_scan_i2c_addr(pdev, ep92_busnum, ep92_reg) < 0) {
  7531. /* check a second time after a short delay */
  7532. msleep(20);
  7533. if (msm_scan_i2c_addr(pdev, ep92_busnum, ep92_reg) < 0) {
  7534. dev_info(&pdev->dev, "%s: No ep92 device found\n",
  7535. __func__);
  7536. /* continue with snd_card registration without ep92 */
  7537. return 0;
  7538. }
  7539. }
  7540. dev_info(&pdev->dev, "%s: ep92 device found\n", __func__);
  7541. /* update codec info in MI2S dai link */
  7542. dai = &msm_mi2s_be_dai_links[0];
  7543. for (i=0; i<ARRAY_SIZE(msm_mi2s_be_dai_links); i++) {
  7544. if (strcmp(dai->name, LPASS_BE_SEC_MI2S_TX) == 0) {
  7545. dev_dbg(&pdev->dev,
  7546. "%s: Set Sec MI2S dai to ep92 codec\n",
  7547. __func__);
  7548. dai->codec_name = ep92_name;
  7549. dai->codec_dai_name = "ep92-hdmi";
  7550. break;
  7551. }
  7552. dai++;
  7553. }
  7554. /* update codec info in SPDIF dai link */
  7555. dai = &msm_spdif_be_dai_links[0];
  7556. for (i=0; i<ARRAY_SIZE(msm_spdif_be_dai_links); i++) {
  7557. if (strcmp(dai->name, LPASS_BE_SEC_SPDIF_TX) == 0) {
  7558. dev_dbg(&pdev->dev,
  7559. "%s: Set Sec SPDIF dai to ep92 codec\n",
  7560. __func__);
  7561. dai->codec_name = ep92_name;
  7562. dai->codec_dai_name = "ep92-arc";
  7563. break;
  7564. }
  7565. dai++;
  7566. }
  7567. return 0;
  7568. }
  7569. static int msm_asoc_machine_probe(struct platform_device *pdev)
  7570. {
  7571. struct snd_soc_card *card;
  7572. struct msm_asoc_mach_data *pdata;
  7573. int ret;
  7574. u32 val;
  7575. const char *micb_supply_str = "tdm-vdd-micb-supply";
  7576. const char *micb_supply_str1 = "tdm-vdd-micb";
  7577. const char *micb_voltage_str = "qcom,tdm-vdd-micb-voltage";
  7578. const char *micb_current_str = "qcom,tdm-vdd-micb-current";
  7579. if (!pdev->dev.of_node) {
  7580. dev_err(&pdev->dev, "No platform supplied from device tree\n");
  7581. return -EINVAL;
  7582. }
  7583. pdata = devm_kzalloc(&pdev->dev,
  7584. sizeof(struct msm_asoc_mach_data), GFP_KERNEL);
  7585. if (!pdata)
  7586. return -ENOMEM;
  7587. /* test for ep92 HDMI bridge and update dai links accordingly */
  7588. ret = msm_detect_ep92_dev(pdev, card);
  7589. if (ret)
  7590. goto err;
  7591. card = populate_snd_card_dailinks(&pdev->dev);
  7592. if (!card) {
  7593. dev_err(&pdev->dev, "%s: Card uninitialized\n", __func__);
  7594. ret = -EINVAL;
  7595. goto err;
  7596. }
  7597. card->dev = &pdev->dev;
  7598. platform_set_drvdata(pdev, card);
  7599. snd_soc_card_set_drvdata(card, pdata);
  7600. ret = snd_soc_of_parse_card_name(card, "qcom,model");
  7601. if (ret) {
  7602. dev_err(&pdev->dev, "parse card name failed, err:%d\n",
  7603. ret);
  7604. goto err;
  7605. }
  7606. ret = snd_soc_of_parse_audio_routing(card, "qcom,audio-routing");
  7607. if (ret) {
  7608. dev_err(&pdev->dev, "parse audio routing failed, err:%d\n",
  7609. ret);
  7610. goto err;
  7611. }
  7612. ret = msm_populate_dai_link_component_of_node(card);
  7613. if (ret) {
  7614. ret = -EPROBE_DEFER;
  7615. goto err;
  7616. }
  7617. ret = of_property_read_u32(pdev->dev.of_node, "qcom,csra-codec", &val);
  7618. if (ret) {
  7619. dev_info(&pdev->dev, "no 'qcom,csra-codec' in DT\n");
  7620. val = 0;
  7621. }
  7622. if (val) {
  7623. pdata->codec_is_csra = true;
  7624. mi2s_rx_cfg[PRIM_MI2S].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  7625. ret = msm_init_csra_dev(pdev, card);
  7626. if (ret)
  7627. goto err;
  7628. } else {
  7629. pdata->codec_is_csra = false;
  7630. ret = msm_init_wsa_dev(pdev, card);
  7631. if (ret)
  7632. goto err;
  7633. }
  7634. pdata->dmic_01_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7635. "qcom,cdc-dmic01-gpios", 0);
  7636. pdata->dmic_23_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7637. "qcom,cdc-dmic23-gpios", 0);
  7638. pdata->dmic_45_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7639. "qcom,cdc-dmic45-gpios", 0);
  7640. pdata->dmic_67_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7641. "qcom,cdc-dmic67-gpios", 0);
  7642. pdata->mi2s_gpio_p[PRIM_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7643. "qcom,pri-mi2s-gpios", 0);
  7644. pdata->mi2s_gpio_p[SEC_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7645. "qcom,sec-mi2s-gpios", 0);
  7646. pdata->mi2s_gpio_p[TERT_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7647. "qcom,tert-mi2s-gpios", 0);
  7648. pdata->mi2s_gpio_p[QUAT_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7649. "qcom,quat-mi2s-gpios", 0);
  7650. pdata->mi2s_gpio_p[QUIN_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7651. "qcom,quin-mi2s-gpios", 0);
  7652. if (of_parse_phandle(pdev->dev.of_node, micb_supply_str, 0)) {
  7653. pdata->tdm_micb_supply = devm_regulator_get(&pdev->dev,
  7654. micb_supply_str1);
  7655. if (IS_ERR(pdata->tdm_micb_supply)) {
  7656. ret = PTR_ERR(pdata->tdm_micb_supply);
  7657. dev_err(&pdev->dev,
  7658. "%s:Failed to get micbias supply for TDM Mic %d\n",
  7659. __func__, ret);
  7660. }
  7661. ret = of_property_read_u32(pdev->dev.of_node,
  7662. micb_voltage_str,
  7663. &pdata->tdm_micb_voltage);
  7664. if (ret) {
  7665. dev_err(&pdev->dev,
  7666. "%s:Looking up %s property in node %s failed\n",
  7667. __func__, micb_voltage_str,
  7668. pdev->dev.of_node->full_name);
  7669. }
  7670. ret = of_property_read_u32(pdev->dev.of_node,
  7671. micb_current_str,
  7672. &pdata->tdm_micb_current);
  7673. if (ret) {
  7674. dev_err(&pdev->dev,
  7675. "%s:Looking up %s property in node %s failed\n",
  7676. __func__, micb_current_str,
  7677. pdev->dev.of_node->full_name);
  7678. }
  7679. }
  7680. ret = devm_snd_soc_register_card(&pdev->dev, card);
  7681. if (ret == -EPROBE_DEFER) {
  7682. if (codec_reg_done)
  7683. ret = -EINVAL;
  7684. goto err;
  7685. } else if (ret) {
  7686. dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
  7687. ret);
  7688. goto err;
  7689. }
  7690. dev_info(&pdev->dev, "Sound card %s registered\n", card->name);
  7691. spdev = pdev;
  7692. ret = msm_mdf_mem_init();
  7693. if (ret)
  7694. dev_err(&pdev->dev, "msm_mdf_mem_init failed (%d)\n",
  7695. ret);
  7696. msm_i2s_auxpcm_init(pdev);
  7697. is_initial_boot = true;
  7698. return 0;
  7699. err:
  7700. return ret;
  7701. }
  7702. static int msm_asoc_machine_remove(struct platform_device *pdev)
  7703. {
  7704. audio_notifier_deregister("qcs405");
  7705. msm_i2s_auxpcm_deinit();
  7706. msm_mdf_mem_deinit();
  7707. return 0;
  7708. }
  7709. static struct platform_driver qcs405_asoc_machine_driver = {
  7710. .driver = {
  7711. .name = DRV_NAME,
  7712. .owner = THIS_MODULE,
  7713. .pm = &snd_soc_pm_ops,
  7714. .of_match_table = qcs405_asoc_machine_of_match,
  7715. },
  7716. .probe = msm_asoc_machine_probe,
  7717. .remove = msm_asoc_machine_remove,
  7718. };
  7719. module_platform_driver(qcs405_asoc_machine_driver);
  7720. MODULE_DESCRIPTION("ALSA SoC QCS405 Machine driver");
  7721. MODULE_LICENSE("GPL v2");
  7722. MODULE_ALIAS("platform:" DRV_NAME);
  7723. MODULE_DEVICE_TABLE(of, qcs405_asoc_machine_of_match);