wcd937x.c 85 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/slab.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/device.h>
  9. #include <linux/delay.h>
  10. #include <linux/kernel.h>
  11. #include <linux/component.h>
  12. #include <linux/regmap.h>
  13. #include <linux/pm_runtime.h>
  14. #include <sound/soc.h>
  15. #include <sound/tlv.h>
  16. #include <soc/soundwire.h>
  17. #include <sound/soc.h>
  18. #include <sound/soc-dapm.h>
  19. #include "internal.h"
  20. #include "wcd937x.h"
  21. #include <asoc/wcdcal-hwdep.h>
  22. #include "wcd937x-registers.h"
  23. #include <asoc/msm-cdc-pinctrl.h>
  24. #include <dt-bindings/sound/audio-codec-port-types.h>
  25. #include <asoc/msm-cdc-supply.h>
  26. #define DRV_NAME "wcd937x_codec"
  27. #define WCD9370_VARIANT 0
  28. #define WCD9375_VARIANT 5
  29. #define WCD937X_VARIANT_ENTRY_SIZE 32
  30. #define NUM_SWRS_DT_PARAMS 5
  31. #define WCD937X_VERSION_1_0 1
  32. #define WCD937X_VERSION_ENTRY_SIZE 32
  33. #define EAR_RX_PATH_AUX 1
  34. enum {
  35. CODEC_TX = 0,
  36. CODEC_RX,
  37. };
  38. enum {
  39. ALLOW_BUCK_DISABLE,
  40. HPH_COMP_DELAY,
  41. HPH_PA_DELAY,
  42. AMIC2_BCS_ENABLE,
  43. };
  44. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  45. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  46. static int wcd937x_handle_post_irq(void *data);
  47. static int wcd937x_reset(struct device *dev);
  48. static int wcd937x_reset_low(struct device *dev);
  49. static const struct regmap_irq wcd937x_irqs[WCD937X_NUM_IRQS] = {
  50. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  51. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  52. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  53. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  54. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_SW_DET, 0, 0x10),
  55. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_OCP_INT, 0, 0x20),
  56. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_CNP_INT, 0, 0x40),
  57. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_OCP_INT, 0, 0x80),
  58. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_CNP_INT, 1, 0x01),
  59. REGMAP_IRQ_REG(WCD937X_IRQ_EAR_CNP_INT, 1, 0x02),
  60. REGMAP_IRQ_REG(WCD937X_IRQ_EAR_SCD_INT, 1, 0x04),
  61. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_CNP_INT, 1, 0x08),
  62. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_SCD_INT, 1, 0x10),
  63. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  64. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  65. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  66. REGMAP_IRQ_REG(WCD937X_IRQ_LDORT_SCD_INT, 2, 0x01),
  67. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  68. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  69. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  70. };
  71. static struct regmap_irq_chip wcd937x_regmap_irq_chip = {
  72. .name = "wcd937x",
  73. .irqs = wcd937x_irqs,
  74. .num_irqs = ARRAY_SIZE(wcd937x_irqs),
  75. .num_regs = 3,
  76. .status_base = WCD937X_DIGITAL_INTR_STATUS_0,
  77. .mask_base = WCD937X_DIGITAL_INTR_MASK_0,
  78. .ack_base = WCD937X_DIGITAL_INTR_CLEAR_0,
  79. .use_ack = 1,
  80. .clear_ack = 1,
  81. .type_base = WCD937X_DIGITAL_INTR_LEVEL_0,
  82. .runtime_pm = false,
  83. .handle_post_irq = wcd937x_handle_post_irq,
  84. .irq_drv_data = NULL,
  85. };
  86. static int wcd937x_handle_post_irq(void *data)
  87. {
  88. struct wcd937x_priv *wcd937x = data;
  89. u32 status1 = 0, status2 = 0, status3 = 0;
  90. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_0, &status1);
  91. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_1, &status2);
  92. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_2, &status3);
  93. wcd937x->tx_swr_dev->slave_irq_pending =
  94. ((status1 || status2 || status3) ? true : false);
  95. return IRQ_HANDLED;
  96. }
  97. static int wcd937x_init_reg(struct snd_soc_component *component)
  98. {
  99. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  100. 0x0E, 0x0E);
  101. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  102. 0x80, 0x80);
  103. usleep_range(1000, 1010);
  104. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  105. 0x40, 0x40);
  106. usleep_range(1000, 1010);
  107. snd_soc_component_update_bits(component, WCD937X_LDORXTX_CONFIG,
  108. 0x10, 0x00);
  109. snd_soc_component_update_bits(component, WCD937X_BIAS_VBG_FINE_ADJ,
  110. 0xF0, 0x80);
  111. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  112. 0x80, 0x80);
  113. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  114. 0x40, 0x40);
  115. usleep_range(10000, 10010);
  116. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  117. 0x40, 0x00);
  118. snd_soc_component_update_bits(component,
  119. WCD937X_HPH_SURGE_HPHLR_SURGE_EN,
  120. 0xFF, 0xD9);
  121. snd_soc_component_update_bits(component, WCD937X_MICB1_TEST_CTL_1,
  122. 0xFF, 0xFA);
  123. snd_soc_component_update_bits(component, WCD937X_MICB2_TEST_CTL_1,
  124. 0xFF, 0xFA);
  125. snd_soc_component_update_bits(component, WCD937X_MICB3_TEST_CTL_1,
  126. 0xFF, 0xFA);
  127. return 0;
  128. }
  129. static int wcd937x_set_port_params(struct snd_soc_component *component,
  130. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  131. u8 *ch_mask, u32 *ch_rate,
  132. u8 *port_type, u8 path)
  133. {
  134. int i, j;
  135. u8 num_ports = 0;
  136. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT] = NULL;
  137. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  138. switch (path) {
  139. case CODEC_RX:
  140. map = &wcd937x->rx_port_mapping;
  141. num_ports = wcd937x->num_rx_ports;
  142. break;
  143. case CODEC_TX:
  144. map = &wcd937x->tx_port_mapping;
  145. num_ports = wcd937x->num_tx_ports;
  146. break;
  147. }
  148. for (i = 0; i <= num_ports; i++) {
  149. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  150. if ((*map)[i][j].slave_port_type == slv_prt_type)
  151. goto found;
  152. }
  153. }
  154. found:
  155. if (i > num_ports || j == MAX_CH_PER_PORT) {
  156. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  157. __func__, slv_prt_type);
  158. return -EINVAL;
  159. }
  160. *port_id = i;
  161. *num_ch = (*map)[i][j].num_ch;
  162. *ch_mask = (*map)[i][j].ch_mask;
  163. *ch_rate = (*map)[i][j].ch_rate;
  164. *port_type = (*map)[i][j].master_port_type;
  165. return 0;
  166. }
  167. static int wcd937x_parse_port_mapping(struct device *dev,
  168. char *prop, u8 path)
  169. {
  170. u32 *dt_array, map_size, map_length;
  171. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  172. u32 slave_port_type, master_port_type;
  173. u32 i, ch_iter = 0;
  174. int ret = 0;
  175. u8 *num_ports = NULL;
  176. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT] = NULL;
  177. struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
  178. switch (path) {
  179. case CODEC_RX:
  180. map = &wcd937x->rx_port_mapping;
  181. num_ports = &wcd937x->num_rx_ports;
  182. break;
  183. case CODEC_TX:
  184. map = &wcd937x->tx_port_mapping;
  185. num_ports = &wcd937x->num_tx_ports;
  186. break;
  187. }
  188. if (!of_find_property(dev->of_node, prop,
  189. &map_size)) {
  190. dev_err(dev, "missing port mapping prop %s\n", prop);
  191. ret = -EINVAL;
  192. goto err;
  193. }
  194. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  195. dt_array = kzalloc(map_size, GFP_KERNEL);
  196. if (!dt_array) {
  197. ret = -ENOMEM;
  198. goto err;
  199. }
  200. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  201. NUM_SWRS_DT_PARAMS * map_length);
  202. if (ret) {
  203. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  204. __func__, prop);
  205. ret = -EINVAL;
  206. goto err_pdata_fail;
  207. }
  208. for (i = 0; i < map_length; i++) {
  209. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  210. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  211. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  212. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  213. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  214. if (port_num != old_port_num)
  215. ch_iter = 0;
  216. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  217. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  218. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  219. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  220. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  221. old_port_num = port_num;
  222. }
  223. *num_ports = port_num;
  224. kfree(dt_array);
  225. return 0;
  226. err_pdata_fail:
  227. kfree(dt_array);
  228. err:
  229. return ret;
  230. }
  231. static int wcd937x_tx_connect_port(struct snd_soc_component *component,
  232. u8 slv_port_type, u8 enable)
  233. {
  234. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  235. u8 port_id;
  236. u8 num_ch;
  237. u8 ch_mask;
  238. u32 ch_rate;
  239. u8 port_type;
  240. u8 num_port = 1;
  241. int ret = 0;
  242. ret = wcd937x_set_port_params(component, slv_port_type, &port_id,
  243. &num_ch, &ch_mask, &ch_rate,
  244. &port_type, CODEC_TX);
  245. if (ret)
  246. return ret;
  247. if (enable)
  248. ret = swr_connect_port(wcd937x->tx_swr_dev, &port_id,
  249. num_port, &ch_mask, &ch_rate,
  250. &num_ch, &port_type);
  251. else
  252. ret = swr_disconnect_port(wcd937x->tx_swr_dev, &port_id,
  253. num_port, &ch_mask, &port_type);
  254. return ret;
  255. }
  256. static int wcd937x_rx_connect_port(struct snd_soc_component *component,
  257. u8 slv_port_type, u8 enable)
  258. {
  259. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  260. u8 port_id;
  261. u8 num_ch;
  262. u8 ch_mask;
  263. u32 ch_rate;
  264. u8 port_type;
  265. u8 num_port = 1;
  266. int ret = 0;
  267. ret = wcd937x_set_port_params(component, slv_port_type, &port_id,
  268. &num_ch, &ch_mask, &ch_rate,
  269. &port_type, CODEC_RX);
  270. if (ret)
  271. return ret;
  272. if (enable)
  273. ret = swr_connect_port(wcd937x->rx_swr_dev, &port_id,
  274. num_port, &ch_mask, &ch_rate,
  275. &num_ch, &port_type);
  276. else
  277. ret = swr_disconnect_port(wcd937x->rx_swr_dev, &port_id,
  278. num_port, &ch_mask, &port_type);
  279. return ret;
  280. }
  281. static int wcd937x_rx_clk_enable(struct snd_soc_component *component)
  282. {
  283. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  284. if (wcd937x->rx_clk_cnt == 0) {
  285. snd_soc_component_update_bits(component,
  286. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x08, 0x08);
  287. snd_soc_component_update_bits(component,
  288. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
  289. snd_soc_component_update_bits(component,
  290. WCD937X_ANA_RX_SUPPLIES, 0x01, 0x01);
  291. snd_soc_component_update_bits(component,
  292. WCD937X_DIGITAL_CDC_RX0_CTL, 0x40, 0x00);
  293. snd_soc_component_update_bits(component,
  294. WCD937X_DIGITAL_CDC_RX1_CTL, 0x40, 0x00);
  295. snd_soc_component_update_bits(component,
  296. WCD937X_DIGITAL_CDC_RX2_CTL, 0x40, 0x00);
  297. snd_soc_component_update_bits(component,
  298. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
  299. }
  300. wcd937x->rx_clk_cnt++;
  301. return 0;
  302. }
  303. static int wcd937x_rx_clk_disable(struct snd_soc_component *component)
  304. {
  305. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  306. if (wcd937x->rx_clk_cnt == 0) {
  307. dev_dbg(wcd937x->dev, "%s:clk already disabled\n", __func__);
  308. return 0;
  309. }
  310. wcd937x->rx_clk_cnt--;
  311. if (wcd937x->rx_clk_cnt == 0) {
  312. snd_soc_component_update_bits(component,
  313. WCD937X_ANA_RX_SUPPLIES, 0x01, 0x00);
  314. snd_soc_component_update_bits(component,
  315. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  316. 0x02, 0x00);
  317. snd_soc_component_update_bits(component,
  318. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  319. 0x01, 0x00);
  320. }
  321. return 0;
  322. }
  323. /*
  324. * wcd937x_soc_get_mbhc: get wcd937x_mbhc handle of corresponding component
  325. * @component: handle to snd_soc_component *
  326. *
  327. * return wcd937x_mbhc handle or error code in case of failure
  328. */
  329. struct wcd937x_mbhc *wcd937x_soc_get_mbhc(struct snd_soc_component *component)
  330. {
  331. struct wcd937x_priv *wcd937x;
  332. if (!component) {
  333. pr_err("%s: Invalid params, NULL component\n", __func__);
  334. return NULL;
  335. }
  336. wcd937x = snd_soc_component_get_drvdata(component);
  337. if (!wcd937x) {
  338. pr_err("%s: Invalid params, NULL tavil\n", __func__);
  339. return NULL;
  340. }
  341. return wcd937x->mbhc;
  342. }
  343. EXPORT_SYMBOL(wcd937x_soc_get_mbhc);
  344. static int wcd937x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  345. struct snd_kcontrol *kcontrol,
  346. int event)
  347. {
  348. struct snd_soc_component *component =
  349. snd_soc_dapm_to_component(w->dapm);
  350. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  351. int hph_mode = wcd937x->hph_mode;
  352. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  353. w->name, event);
  354. switch (event) {
  355. case SND_SOC_DAPM_PRE_PMU:
  356. wcd937x_rx_clk_enable(component);
  357. snd_soc_component_update_bits(component,
  358. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  359. 0x01, 0x01);
  360. snd_soc_component_update_bits(component,
  361. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL,
  362. 0x04, 0x04);
  363. snd_soc_component_update_bits(component,
  364. WCD937X_HPH_RDAC_CLK_CTL1,
  365. 0x80, 0x00);
  366. set_bit(HPH_COMP_DELAY, &wcd937x->status_mask);
  367. break;
  368. case SND_SOC_DAPM_POST_PMU:
  369. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  370. snd_soc_component_update_bits(component,
  371. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  372. 0x0F, 0x02);
  373. else if (hph_mode == CLS_H_LOHIFI)
  374. snd_soc_component_update_bits(component,
  375. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  376. 0x0F, 0x06);
  377. if (wcd937x->comp1_enable) {
  378. snd_soc_component_update_bits(component,
  379. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  380. 0x02, 0x02);
  381. snd_soc_component_update_bits(component,
  382. WCD937X_HPH_L_EN, 0x20, 0x00);
  383. if (wcd937x->comp2_enable) {
  384. snd_soc_component_update_bits(component,
  385. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  386. 0x01, 0x01);
  387. snd_soc_component_update_bits(component,
  388. WCD937X_HPH_R_EN, 0x20, 0x00);
  389. }
  390. /*
  391. * 5ms sleep is required after COMP is enabled as per
  392. * HW requirement
  393. */
  394. if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) {
  395. usleep_range(5000, 5100);
  396. clear_bit(HPH_COMP_DELAY,
  397. &wcd937x->status_mask);
  398. }
  399. } else {
  400. snd_soc_component_update_bits(component,
  401. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  402. 0x02, 0x00);
  403. snd_soc_component_update_bits(component,
  404. WCD937X_HPH_L_EN, 0x20, 0x20);
  405. }
  406. snd_soc_component_update_bits(component,
  407. WCD937X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  408. break;
  409. case SND_SOC_DAPM_POST_PMD:
  410. snd_soc_component_update_bits(component,
  411. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  412. 0x0F, 0x01);
  413. break;
  414. }
  415. return 0;
  416. }
  417. static int wcd937x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  418. struct snd_kcontrol *kcontrol,
  419. int event)
  420. {
  421. struct snd_soc_component *component =
  422. snd_soc_dapm_to_component(w->dapm);
  423. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  424. int hph_mode = wcd937x->hph_mode;
  425. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  426. w->name, event);
  427. switch (event) {
  428. case SND_SOC_DAPM_PRE_PMU:
  429. wcd937x_rx_clk_enable(component);
  430. snd_soc_component_update_bits(component,
  431. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
  432. snd_soc_component_update_bits(component,
  433. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL, 0x08, 0x08);
  434. snd_soc_component_update_bits(component,
  435. WCD937X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  436. set_bit(HPH_COMP_DELAY, &wcd937x->status_mask);
  437. break;
  438. case SND_SOC_DAPM_POST_PMU:
  439. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  440. snd_soc_component_update_bits(component,
  441. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  442. 0x0F, 0x02);
  443. else if (hph_mode == CLS_H_LOHIFI)
  444. snd_soc_component_update_bits(component,
  445. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  446. 0x0F, 0x06);
  447. if (wcd937x->comp2_enable) {
  448. snd_soc_component_update_bits(component,
  449. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  450. 0x01, 0x01);
  451. snd_soc_component_update_bits(component,
  452. WCD937X_HPH_R_EN, 0x20, 0x00);
  453. if (wcd937x->comp1_enable) {
  454. snd_soc_component_update_bits(component,
  455. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  456. 0x02, 0x02);
  457. snd_soc_component_update_bits(component,
  458. WCD937X_HPH_L_EN, 0x20, 0x00);
  459. }
  460. /*
  461. * 5ms sleep is required after COMP is enabled as per
  462. * HW requirement
  463. */
  464. if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) {
  465. usleep_range(5000, 5100);
  466. clear_bit(HPH_COMP_DELAY,
  467. &wcd937x->status_mask);
  468. }
  469. } else {
  470. snd_soc_component_update_bits(component,
  471. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  472. 0x01, 0x00);
  473. snd_soc_component_update_bits(component,
  474. WCD937X_HPH_R_EN, 0x20, 0x20);
  475. }
  476. snd_soc_component_update_bits(component,
  477. WCD937X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  478. break;
  479. case SND_SOC_DAPM_POST_PMD:
  480. snd_soc_component_update_bits(component,
  481. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  482. 0x0F, 0x01);
  483. break;
  484. }
  485. return 0;
  486. }
  487. static int wcd937x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  488. struct snd_kcontrol *kcontrol,
  489. int event)
  490. {
  491. struct snd_soc_component *component =
  492. snd_soc_dapm_to_component(w->dapm);
  493. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  494. int hph_mode = wcd937x->hph_mode;
  495. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  496. w->name, event);
  497. switch (event) {
  498. case SND_SOC_DAPM_PRE_PMU:
  499. wcd937x_rx_clk_enable(component);
  500. snd_soc_component_update_bits(component,
  501. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL,
  502. 0x04, 0x04);
  503. snd_soc_component_update_bits(component,
  504. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  505. 0x01, 0x01);
  506. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  507. snd_soc_component_update_bits(component,
  508. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  509. 0x0F, 0x02);
  510. else if (hph_mode == CLS_H_LOHIFI)
  511. snd_soc_component_update_bits(component,
  512. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  513. 0x0F, 0x06);
  514. snd_soc_component_update_bits(component,
  515. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  516. 0x02, 0x02);
  517. usleep_range(5000, 5010);
  518. snd_soc_component_update_bits(component, WCD937X_FLYBACK_EN,
  519. 0x04, 0x00);
  520. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  521. WCD_CLSH_EVENT_PRE_DAC,
  522. WCD_CLSH_STATE_EAR,
  523. hph_mode);
  524. break;
  525. case SND_SOC_DAPM_POST_PMD:
  526. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_LOHIFI ||
  527. hph_mode == CLS_H_HIFI)
  528. snd_soc_component_update_bits(component,
  529. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  530. 0x0F, 0x01);
  531. break;
  532. };
  533. return 0;
  534. }
  535. static int wcd937x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  536. struct snd_kcontrol *kcontrol,
  537. int event)
  538. {
  539. struct snd_soc_component *component =
  540. snd_soc_dapm_to_component(w->dapm);
  541. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  542. int hph_mode = wcd937x->hph_mode;
  543. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  544. w->name, event);
  545. switch (event) {
  546. case SND_SOC_DAPM_PRE_PMU:
  547. wcd937x_rx_clk_enable(component);
  548. snd_soc_component_update_bits(component,
  549. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  550. 0x04, 0x04);
  551. snd_soc_component_update_bits(component,
  552. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  553. 0x04, 0x04);
  554. snd_soc_component_update_bits(component,
  555. WCD937X_DIGITAL_CDC_AUX_GAIN_CTL,
  556. 0x01, 0x01);
  557. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  558. WCD_CLSH_EVENT_PRE_DAC,
  559. WCD_CLSH_STATE_AUX,
  560. hph_mode);
  561. break;
  562. case SND_SOC_DAPM_POST_PMD:
  563. wcd937x_rx_clk_disable(component);
  564. snd_soc_component_update_bits(component,
  565. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  566. 0x04, 0x00);
  567. break;
  568. };
  569. return 0;
  570. }
  571. static int wcd937x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  572. struct snd_kcontrol *kcontrol,
  573. int event)
  574. {
  575. struct snd_soc_component *component =
  576. snd_soc_dapm_to_component(w->dapm);
  577. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  578. int ret = 0;
  579. int hph_mode = wcd937x->hph_mode;
  580. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  581. w->name, event);
  582. switch (event) {
  583. case SND_SOC_DAPM_PRE_PMU:
  584. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  585. wcd937x->rx_swr_dev->dev_num,
  586. true);
  587. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  588. WCD_CLSH_EVENT_PRE_DAC,
  589. WCD_CLSH_STATE_HPHR,
  590. hph_mode);
  591. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  592. 0x10, 0x10);
  593. usleep_range(100, 110);
  594. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  595. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  596. wcd937x->rx_swr_dev->dev_num,
  597. true);
  598. snd_soc_component_update_bits(component,
  599. WCD937X_DIGITAL_PDM_WD_CTL1, 0x17, 0x13);
  600. break;
  601. case SND_SOC_DAPM_POST_PMU:
  602. /*
  603. * 7ms sleep is required after PA is enabled as per
  604. * HW requirement. If compander is disabled, then
  605. * 20ms delay is required.
  606. */
  607. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  608. if (!wcd937x->comp2_enable)
  609. usleep_range(20000, 20100);
  610. else
  611. usleep_range(7000, 7100);
  612. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  613. }
  614. snd_soc_component_update_bits(component,
  615. WCD937X_HPH_NEW_INT_HPH_TIMER1,
  616. 0x02, 0x02);
  617. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  618. snd_soc_component_update_bits(component,
  619. WCD937X_ANA_RX_SUPPLIES,
  620. 0x02, 0x02);
  621. if (wcd937x->update_wcd_event)
  622. wcd937x->update_wcd_event(wcd937x->handle,
  623. WCD_BOLERO_EVT_RX_MUTE,
  624. (WCD_RX2 << 0x10));
  625. wcd_enable_irq(&wcd937x->irq_info,
  626. WCD937X_IRQ_HPHR_PDM_WD_INT);
  627. break;
  628. case SND_SOC_DAPM_PRE_PMD:
  629. wcd_disable_irq(&wcd937x->irq_info,
  630. WCD937X_IRQ_HPHR_PDM_WD_INT);
  631. if (wcd937x->update_wcd_event)
  632. wcd937x->update_wcd_event(wcd937x->handle,
  633. WCD_BOLERO_EVT_RX_MUTE,
  634. (WCD_RX2 << 0x10 | 0x1));
  635. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  636. WCD_EVENT_PRE_HPHR_PA_OFF,
  637. &wcd937x->mbhc->wcd_mbhc);
  638. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  639. break;
  640. case SND_SOC_DAPM_POST_PMD:
  641. /*
  642. * 7ms sleep is required after PA is disabled as per
  643. * HW requirement. If compander is disabled, then
  644. * 20ms delay is required.
  645. */
  646. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  647. if (!wcd937x->comp2_enable)
  648. usleep_range(20000, 20100);
  649. else
  650. usleep_range(7000, 7100);
  651. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  652. }
  653. snd_soc_component_update_bits(component,
  654. WCD937X_DIGITAL_PDM_WD_CTL1, 0x17, 0x00);
  655. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  656. WCD_EVENT_POST_HPHR_PA_OFF,
  657. &wcd937x->mbhc->wcd_mbhc);
  658. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  659. 0x10, 0x00);
  660. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  661. WCD_CLSH_EVENT_POST_PA,
  662. WCD_CLSH_STATE_HPHR,
  663. hph_mode);
  664. break;
  665. };
  666. return ret;
  667. }
  668. static int wcd937x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  669. struct snd_kcontrol *kcontrol,
  670. int event)
  671. {
  672. struct snd_soc_component *component =
  673. snd_soc_dapm_to_component(w->dapm);
  674. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  675. int ret = 0;
  676. int hph_mode = wcd937x->hph_mode;
  677. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  678. w->name, event);
  679. switch (event) {
  680. case SND_SOC_DAPM_PRE_PMU:
  681. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  682. wcd937x->rx_swr_dev->dev_num,
  683. true);
  684. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  685. WCD_CLSH_EVENT_PRE_DAC,
  686. WCD_CLSH_STATE_HPHL,
  687. hph_mode);
  688. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  689. 0x20, 0x20);
  690. usleep_range(100, 110);
  691. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  692. snd_soc_component_update_bits(component,
  693. WCD937X_DIGITAL_PDM_WD_CTL0, 0x17, 0x13);
  694. break;
  695. case SND_SOC_DAPM_POST_PMU:
  696. /*
  697. * 7ms sleep is required after PA is enabled as per
  698. * HW requirement. If compander is disabled, then
  699. * 20ms delay is required.
  700. */
  701. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  702. if (!wcd937x->comp1_enable)
  703. usleep_range(20000, 20100);
  704. else
  705. usleep_range(7000, 7100);
  706. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  707. }
  708. snd_soc_component_update_bits(component,
  709. WCD937X_HPH_NEW_INT_HPH_TIMER1,
  710. 0x02, 0x02);
  711. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  712. snd_soc_component_update_bits(component,
  713. WCD937X_ANA_RX_SUPPLIES,
  714. 0x02, 0x02);
  715. if (wcd937x->update_wcd_event)
  716. wcd937x->update_wcd_event(wcd937x->handle,
  717. WCD_BOLERO_EVT_RX_MUTE,
  718. (WCD_RX1 << 0x10));
  719. wcd_enable_irq(&wcd937x->irq_info,
  720. WCD937X_IRQ_HPHL_PDM_WD_INT);
  721. break;
  722. case SND_SOC_DAPM_PRE_PMD:
  723. wcd_disable_irq(&wcd937x->irq_info,
  724. WCD937X_IRQ_HPHL_PDM_WD_INT);
  725. if (wcd937x->update_wcd_event)
  726. wcd937x->update_wcd_event(wcd937x->handle,
  727. WCD_BOLERO_EVT_RX_MUTE,
  728. (WCD_RX1 << 0x10 | 0x1));
  729. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  730. WCD_EVENT_PRE_HPHL_PA_OFF,
  731. &wcd937x->mbhc->wcd_mbhc);
  732. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  733. break;
  734. case SND_SOC_DAPM_POST_PMD:
  735. /*
  736. * 7ms sleep is required after PA is disabled as per
  737. * HW requirement. If compander is disabled, then
  738. * 20ms delay is required.
  739. */
  740. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  741. if (!wcd937x->comp1_enable)
  742. usleep_range(20000, 20100);
  743. else
  744. usleep_range(7000, 7100);
  745. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  746. }
  747. snd_soc_component_update_bits(component,
  748. WCD937X_DIGITAL_PDM_WD_CTL0, 0x17, 0x00);
  749. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  750. WCD_EVENT_POST_HPHL_PA_OFF,
  751. &wcd937x->mbhc->wcd_mbhc);
  752. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  753. 0x20, 0x00);
  754. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  755. WCD_CLSH_EVENT_POST_PA,
  756. WCD_CLSH_STATE_HPHL,
  757. hph_mode);
  758. break;
  759. };
  760. return ret;
  761. }
  762. static int wcd937x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  763. struct snd_kcontrol *kcontrol,
  764. int event)
  765. {
  766. struct snd_soc_component *component =
  767. snd_soc_dapm_to_component(w->dapm);
  768. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  769. int hph_mode = wcd937x->hph_mode;
  770. int ret = 0;
  771. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  772. w->name, event);
  773. switch (event) {
  774. case SND_SOC_DAPM_PRE_PMU:
  775. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  776. wcd937x->rx_swr_dev->dev_num,
  777. true);
  778. snd_soc_component_update_bits(component,
  779. WCD937X_DIGITAL_PDM_WD_CTL2, 0x05, 0x05);
  780. break;
  781. case SND_SOC_DAPM_POST_PMU:
  782. usleep_range(1000, 1010);
  783. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  784. snd_soc_component_update_bits(component,
  785. WCD937X_ANA_RX_SUPPLIES,
  786. 0x02, 0x02);
  787. if (wcd937x->update_wcd_event)
  788. wcd937x->update_wcd_event(wcd937x->handle,
  789. WCD_BOLERO_EVT_RX_MUTE,
  790. (WCD_RX3 << 0x10));
  791. wcd_enable_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT);
  792. break;
  793. case SND_SOC_DAPM_PRE_PMD:
  794. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT);
  795. if (wcd937x->update_wcd_event)
  796. wcd937x->update_wcd_event(wcd937x->handle,
  797. WCD_BOLERO_EVT_RX_MUTE,
  798. (WCD_RX3 << 0x10 | 0x1));
  799. break;
  800. case SND_SOC_DAPM_POST_PMD:
  801. /* Add delay as per hw requirement */
  802. usleep_range(2000, 2010);
  803. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  804. WCD_CLSH_EVENT_POST_PA,
  805. WCD_CLSH_STATE_AUX,
  806. hph_mode);
  807. snd_soc_component_update_bits(component,
  808. WCD937X_DIGITAL_PDM_WD_CTL2, 0x05, 0x00);
  809. break;
  810. };
  811. return ret;
  812. }
  813. static int wcd937x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  814. struct snd_kcontrol *kcontrol,
  815. int event)
  816. {
  817. struct snd_soc_component *component =
  818. snd_soc_dapm_to_component(w->dapm);
  819. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  820. int hph_mode = wcd937x->hph_mode;
  821. int ret = 0;
  822. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  823. w->name, event);
  824. switch (event) {
  825. case SND_SOC_DAPM_PRE_PMU:
  826. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  827. wcd937x->rx_swr_dev->dev_num,
  828. true);
  829. /*
  830. * Enable watchdog interrupt for HPHL or AUX
  831. * depending on mux value
  832. */
  833. wcd937x->ear_rx_path =
  834. snd_soc_component_read32(
  835. component, WCD937X_DIGITAL_CDC_EAR_PATH_CTL);
  836. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  837. snd_soc_component_update_bits(component,
  838. WCD937X_DIGITAL_PDM_WD_CTL2,
  839. 0x05, 0x05);
  840. else
  841. snd_soc_component_update_bits(component,
  842. WCD937X_DIGITAL_PDM_WD_CTL0,
  843. 0x17, 0x13);
  844. if (!wcd937x->comp1_enable)
  845. snd_soc_component_update_bits(component,
  846. WCD937X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  847. break;
  848. case SND_SOC_DAPM_POST_PMU:
  849. usleep_range(6000, 6010);
  850. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  851. snd_soc_component_update_bits(component,
  852. WCD937X_ANA_RX_SUPPLIES,
  853. 0x02, 0x02);
  854. if (wcd937x->update_wcd_event)
  855. wcd937x->update_wcd_event(wcd937x->handle,
  856. WCD_BOLERO_EVT_RX_MUTE,
  857. (WCD_RX1 << 0x10));
  858. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  859. wcd_enable_irq(&wcd937x->irq_info,
  860. WCD937X_IRQ_AUX_PDM_WD_INT);
  861. else
  862. wcd_enable_irq(&wcd937x->irq_info,
  863. WCD937X_IRQ_HPHL_PDM_WD_INT);
  864. break;
  865. case SND_SOC_DAPM_PRE_PMD:
  866. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  867. wcd_disable_irq(&wcd937x->irq_info,
  868. WCD937X_IRQ_AUX_PDM_WD_INT);
  869. else
  870. wcd_disable_irq(&wcd937x->irq_info,
  871. WCD937X_IRQ_HPHL_PDM_WD_INT);
  872. if (wcd937x->update_wcd_event)
  873. wcd937x->update_wcd_event(wcd937x->handle,
  874. WCD_BOLERO_EVT_RX_MUTE,
  875. (WCD_RX1 << 0x10 | 0x1));
  876. break;
  877. case SND_SOC_DAPM_POST_PMD:
  878. if (!wcd937x->comp1_enable)
  879. snd_soc_component_update_bits(component,
  880. WCD937X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  881. usleep_range(7000, 7010);
  882. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  883. WCD_CLSH_EVENT_POST_PA,
  884. WCD_CLSH_STATE_EAR,
  885. hph_mode);
  886. snd_soc_component_update_bits(component, WCD937X_FLYBACK_EN,
  887. 0x04, 0x04);
  888. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  889. snd_soc_component_update_bits(component,
  890. WCD937X_DIGITAL_PDM_WD_CTL2,
  891. 0x05, 0x00);
  892. else
  893. snd_soc_component_update_bits(component,
  894. WCD937X_DIGITAL_PDM_WD_CTL0,
  895. 0x17, 0x00);
  896. break;
  897. };
  898. return ret;
  899. }
  900. static int wcd937x_enable_clsh(struct snd_soc_dapm_widget *w,
  901. struct snd_kcontrol *kcontrol,
  902. int event)
  903. {
  904. struct snd_soc_component *component =
  905. snd_soc_dapm_to_component(w->dapm);
  906. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  907. int mode = wcd937x->hph_mode;
  908. int ret = 0;
  909. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  910. w->name, event);
  911. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  912. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  913. wcd937x_rx_connect_port(component, CLSH,
  914. SND_SOC_DAPM_EVENT_ON(event));
  915. }
  916. if (SND_SOC_DAPM_EVENT_OFF(event))
  917. ret = swr_slvdev_datapath_control(
  918. wcd937x->rx_swr_dev,
  919. wcd937x->rx_swr_dev->dev_num,
  920. false);
  921. return ret;
  922. }
  923. static int wcd937x_enable_rx1(struct snd_soc_dapm_widget *w,
  924. struct snd_kcontrol *kcontrol,
  925. int event)
  926. {
  927. struct snd_soc_component *component =
  928. snd_soc_dapm_to_component(w->dapm);
  929. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  930. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  931. w->name, event);
  932. switch (event) {
  933. case SND_SOC_DAPM_PRE_PMU:
  934. wcd937x_rx_connect_port(component, HPH_L, true);
  935. if (wcd937x->comp1_enable)
  936. wcd937x_rx_connect_port(component, COMP_L, true);
  937. break;
  938. case SND_SOC_DAPM_POST_PMD:
  939. wcd937x_rx_connect_port(component, HPH_L, false);
  940. if (wcd937x->comp1_enable)
  941. wcd937x_rx_connect_port(component, COMP_L, false);
  942. wcd937x_rx_clk_disable(component);
  943. snd_soc_component_update_bits(component,
  944. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  945. 0x01, 0x00);
  946. break;
  947. };
  948. return 0;
  949. }
  950. static int wcd937x_enable_rx2(struct snd_soc_dapm_widget *w,
  951. struct snd_kcontrol *kcontrol, int event)
  952. {
  953. struct snd_soc_component *component =
  954. snd_soc_dapm_to_component(w->dapm);
  955. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  956. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  957. w->name, event);
  958. switch (event) {
  959. case SND_SOC_DAPM_PRE_PMU:
  960. wcd937x_rx_connect_port(component, HPH_R, true);
  961. if (wcd937x->comp2_enable)
  962. wcd937x_rx_connect_port(component, COMP_R, true);
  963. break;
  964. case SND_SOC_DAPM_POST_PMD:
  965. wcd937x_rx_connect_port(component, HPH_R, false);
  966. if (wcd937x->comp2_enable)
  967. wcd937x_rx_connect_port(component, COMP_R, false);
  968. wcd937x_rx_clk_disable(component);
  969. snd_soc_component_update_bits(component,
  970. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  971. 0x02, 0x00);
  972. break;
  973. };
  974. return 0;
  975. }
  976. static int wcd937x_enable_rx3(struct snd_soc_dapm_widget *w,
  977. struct snd_kcontrol *kcontrol,
  978. int event)
  979. {
  980. struct snd_soc_component *component =
  981. snd_soc_dapm_to_component(w->dapm);
  982. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  983. w->name, event);
  984. switch (event) {
  985. case SND_SOC_DAPM_PRE_PMU:
  986. wcd937x_rx_connect_port(component, LO, true);
  987. break;
  988. case SND_SOC_DAPM_POST_PMD:
  989. wcd937x_rx_connect_port(component, LO, false);
  990. usleep_range(6000, 6010);
  991. wcd937x_rx_clk_disable(component);
  992. snd_soc_component_update_bits(component,
  993. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  994. break;
  995. }
  996. return 0;
  997. }
  998. static int wcd937x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  999. struct snd_kcontrol *kcontrol,
  1000. int event)
  1001. {
  1002. struct snd_soc_component *component =
  1003. snd_soc_dapm_to_component(w->dapm);
  1004. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1005. u16 dmic_clk_reg;
  1006. s32 *dmic_clk_cnt;
  1007. unsigned int dmic;
  1008. char *wname;
  1009. int ret = 0;
  1010. wname = strpbrk(w->name, "012345");
  1011. if (!wname) {
  1012. dev_err(component->dev, "%s: widget not found\n", __func__);
  1013. return -EINVAL;
  1014. }
  1015. ret = kstrtouint(wname, 10, &dmic);
  1016. if (ret < 0) {
  1017. dev_err(component->dev, "%s: Invalid DMIC line on the codec\n",
  1018. __func__);
  1019. return -EINVAL;
  1020. }
  1021. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1022. w->name, event);
  1023. switch (dmic) {
  1024. case 0:
  1025. case 1:
  1026. dmic_clk_cnt = &(wcd937x->dmic_0_1_clk_cnt);
  1027. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC1_CTL;
  1028. break;
  1029. case 2:
  1030. case 3:
  1031. dmic_clk_cnt = &(wcd937x->dmic_2_3_clk_cnt);
  1032. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC2_CTL;
  1033. break;
  1034. case 4:
  1035. case 5:
  1036. dmic_clk_cnt = &(wcd937x->dmic_4_5_clk_cnt);
  1037. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC3_CTL;
  1038. break;
  1039. default:
  1040. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  1041. __func__);
  1042. return -EINVAL;
  1043. };
  1044. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  1045. __func__, event, dmic, *dmic_clk_cnt);
  1046. switch (event) {
  1047. case SND_SOC_DAPM_PRE_PMU:
  1048. snd_soc_component_update_bits(component,
  1049. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1050. snd_soc_component_update_bits(component,
  1051. dmic_clk_reg, 0x07, 0x02);
  1052. snd_soc_component_update_bits(component,
  1053. dmic_clk_reg, 0x08, 0x08);
  1054. snd_soc_component_update_bits(component,
  1055. dmic_clk_reg, 0x70, 0x20);
  1056. wcd937x_tx_connect_port(component, DMIC0 + (w->shift), true);
  1057. break;
  1058. case SND_SOC_DAPM_POST_PMD:
  1059. wcd937x_tx_connect_port(component, DMIC0 + (w->shift), false);
  1060. break;
  1061. };
  1062. return 0;
  1063. }
  1064. /*
  1065. * wcd937x_get_micb_vout_ctl_val: converts micbias from volts to register value
  1066. * @micb_mv: micbias in mv
  1067. *
  1068. * return register value converted
  1069. */
  1070. int wcd937x_get_micb_vout_ctl_val(u32 micb_mv)
  1071. {
  1072. /* min micbias voltage is 1V and maximum is 2.85V */
  1073. if (micb_mv < 1000 || micb_mv > 2850) {
  1074. pr_err("%s: unsupported micbias voltage\n", __func__);
  1075. return -EINVAL;
  1076. }
  1077. return (micb_mv - 1000) / 50;
  1078. }
  1079. EXPORT_SYMBOL(wcd937x_get_micb_vout_ctl_val);
  1080. /*
  1081. * wcd937x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  1082. * @component: handle to snd_soc_component *
  1083. * @req_volt: micbias voltage to be set
  1084. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  1085. *
  1086. * return 0 if adjustment is success or error code in case of failure
  1087. */
  1088. int wcd937x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  1089. int req_volt, int micb_num)
  1090. {
  1091. struct wcd937x_priv *wcd937x =
  1092. snd_soc_component_get_drvdata(component);
  1093. int cur_vout_ctl, req_vout_ctl;
  1094. int micb_reg, micb_val, micb_en;
  1095. int ret = 0;
  1096. switch (micb_num) {
  1097. case MIC_BIAS_1:
  1098. micb_reg = WCD937X_ANA_MICB1;
  1099. break;
  1100. case MIC_BIAS_2:
  1101. micb_reg = WCD937X_ANA_MICB2;
  1102. break;
  1103. case MIC_BIAS_3:
  1104. micb_reg = WCD937X_ANA_MICB3;
  1105. break;
  1106. default:
  1107. return -EINVAL;
  1108. }
  1109. mutex_lock(&wcd937x->micb_lock);
  1110. /*
  1111. * If requested micbias voltage is same as current micbias
  1112. * voltage, then just return. Otherwise, adjust voltage as
  1113. * per requested value. If micbias is already enabled, then
  1114. * to avoid slow micbias ramp-up or down enable pull-up
  1115. * momentarily, change the micbias value and then re-enable
  1116. * micbias.
  1117. */
  1118. micb_val = snd_soc_component_read32(component, micb_reg);
  1119. micb_en = (micb_val & 0xC0) >> 6;
  1120. cur_vout_ctl = micb_val & 0x3F;
  1121. req_vout_ctl = wcd937x_get_micb_vout_ctl_val(req_volt);
  1122. if (req_vout_ctl < 0) {
  1123. ret = -EINVAL;
  1124. goto exit;
  1125. }
  1126. if (cur_vout_ctl == req_vout_ctl) {
  1127. ret = 0;
  1128. goto exit;
  1129. }
  1130. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  1131. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  1132. req_volt, micb_en);
  1133. if (micb_en == 0x1)
  1134. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  1135. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  1136. if (micb_en == 0x1) {
  1137. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  1138. /*
  1139. * Add 2ms delay as per HW requirement after enabling
  1140. * micbias
  1141. */
  1142. usleep_range(2000, 2100);
  1143. }
  1144. exit:
  1145. mutex_unlock(&wcd937x->micb_lock);
  1146. return ret;
  1147. }
  1148. EXPORT_SYMBOL(wcd937x_mbhc_micb_adjust_voltage);
  1149. static int wcd937x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1150. struct snd_kcontrol *kcontrol,
  1151. int event)
  1152. {
  1153. struct snd_soc_component *component =
  1154. snd_soc_dapm_to_component(w->dapm);
  1155. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1156. int ret = 0;
  1157. switch (event) {
  1158. case SND_SOC_DAPM_PRE_PMU:
  1159. ret = swr_slvdev_datapath_control(wcd937x->tx_swr_dev,
  1160. wcd937x->tx_swr_dev->dev_num,
  1161. true);
  1162. break;
  1163. case SND_SOC_DAPM_POST_PMD:
  1164. ret = swr_slvdev_datapath_control(wcd937x->tx_swr_dev,
  1165. wcd937x->tx_swr_dev->dev_num,
  1166. false);
  1167. break;
  1168. };
  1169. return ret;
  1170. }
  1171. static int wcd937x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  1172. struct snd_kcontrol *kcontrol,
  1173. int event){
  1174. struct snd_soc_component *component =
  1175. snd_soc_dapm_to_component(w->dapm);
  1176. struct wcd937x_priv *wcd937x =
  1177. snd_soc_component_get_drvdata(component);
  1178. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1179. w->name, event);
  1180. switch (event) {
  1181. case SND_SOC_DAPM_PRE_PMU:
  1182. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1183. wcd937x->ana_clk_count++;
  1184. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1185. snd_soc_component_update_bits(component,
  1186. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1187. snd_soc_component_update_bits(component,
  1188. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x08);
  1189. snd_soc_component_update_bits(component,
  1190. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1191. /* Enable BCS for Headset mic */
  1192. if (w->shift == 1 && !(snd_soc_component_read32(component,
  1193. WCD937X_TX_NEW_TX_CH2_SEL) & 0x80)) {
  1194. wcd937x_tx_connect_port(codec, MBHC, true);
  1195. set_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask);
  1196. }
  1197. wcd937x_tx_connect_port(component, ADC1 + (w->shift), true);
  1198. break;
  1199. case SND_SOC_DAPM_POST_PMD:
  1200. wcd937x_tx_connect_port(component, ADC1 + (w->shift), false);
  1201. if (w->shift == 1 &&
  1202. test_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask)) {
  1203. wcd937x_tx_connect_port(codec, MBHC, false);
  1204. clear_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask);
  1205. }
  1206. snd_soc_component_update_bits(component,
  1207. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x00);
  1208. break;
  1209. };
  1210. return 0;
  1211. }
  1212. static int wcd937x_enable_req(struct snd_soc_dapm_widget *w,
  1213. struct snd_kcontrol *kcontrol, int event)
  1214. {
  1215. struct snd_soc_component *component =
  1216. snd_soc_dapm_to_component(w->dapm);
  1217. struct wcd937x_priv *wcd937x =
  1218. snd_soc_component_get_drvdata(component);
  1219. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1220. w->name, event);
  1221. switch (event) {
  1222. case SND_SOC_DAPM_PRE_PMU:
  1223. snd_soc_component_update_bits(component,
  1224. WCD937X_DIGITAL_CDC_REQ_CTL, 0x02, 0x02);
  1225. snd_soc_component_update_bits(component,
  1226. WCD937X_DIGITAL_CDC_REQ_CTL, 0x01, 0x00);
  1227. snd_soc_component_update_bits(component,
  1228. WCD937X_ANA_TX_CH2, 0x40, 0x40);
  1229. snd_soc_component_update_bits(component,
  1230. WCD937X_ANA_TX_CH3_HPF, 0x40, 0x40);
  1231. snd_soc_component_update_bits(component,
  1232. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x70, 0x70);
  1233. snd_soc_component_update_bits(component,
  1234. WCD937X_ANA_TX_CH1, 0x80, 0x80);
  1235. snd_soc_component_update_bits(component,
  1236. WCD937X_ANA_TX_CH2, 0x40, 0x00);
  1237. snd_soc_component_update_bits(component,
  1238. WCD937X_ANA_TX_CH2, 0x80, 0x80);
  1239. snd_soc_component_update_bits(component,
  1240. WCD937X_ANA_TX_CH3, 0x80, 0x80);
  1241. break;
  1242. case SND_SOC_DAPM_POST_PMD:
  1243. snd_soc_component_update_bits(component,
  1244. WCD937X_ANA_TX_CH1, 0x80, 0x00);
  1245. snd_soc_component_update_bits(component,
  1246. WCD937X_ANA_TX_CH2, 0x80, 0x00);
  1247. snd_soc_component_update_bits(component,
  1248. WCD937X_ANA_TX_CH3, 0x80, 0x00);
  1249. snd_soc_component_update_bits(component,
  1250. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x00);
  1251. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1252. wcd937x->ana_clk_count--;
  1253. if (wcd937x->ana_clk_count <= 0) {
  1254. snd_soc_component_update_bits(component,
  1255. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
  1256. wcd937x->ana_clk_count = 0;
  1257. }
  1258. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1259. snd_soc_component_update_bits(component,
  1260. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00);
  1261. break;
  1262. };
  1263. return 0;
  1264. }
  1265. int wcd937x_micbias_control(struct snd_soc_component *component,
  1266. int micb_num, int req, bool is_dapm)
  1267. {
  1268. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1269. int micb_index = micb_num - 1;
  1270. u16 micb_reg;
  1271. int pre_off_event = 0, post_off_event = 0;
  1272. int post_on_event = 0, post_dapm_off = 0;
  1273. int post_dapm_on = 0;
  1274. if ((micb_index < 0) || (micb_index > WCD937X_MAX_MICBIAS - 1)) {
  1275. dev_err(component->dev, "%s: Invalid micbias index, micb_ind:%d\n",
  1276. __func__, micb_index);
  1277. return -EINVAL;
  1278. }
  1279. switch (micb_num) {
  1280. case MIC_BIAS_1:
  1281. micb_reg = WCD937X_ANA_MICB1;
  1282. break;
  1283. case MIC_BIAS_2:
  1284. micb_reg = WCD937X_ANA_MICB2;
  1285. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1286. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1287. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1288. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1289. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1290. break;
  1291. case MIC_BIAS_3:
  1292. micb_reg = WCD937X_ANA_MICB3;
  1293. break;
  1294. default:
  1295. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1296. __func__, micb_num);
  1297. return -EINVAL;
  1298. };
  1299. mutex_lock(&wcd937x->micb_lock);
  1300. switch (req) {
  1301. case MICB_PULLUP_ENABLE:
  1302. wcd937x->pullup_ref[micb_index]++;
  1303. if ((wcd937x->pullup_ref[micb_index] == 1) &&
  1304. (wcd937x->micb_ref[micb_index] == 0))
  1305. snd_soc_component_update_bits(component, micb_reg,
  1306. 0xC0, 0x80);
  1307. break;
  1308. case MICB_PULLUP_DISABLE:
  1309. if (wcd937x->pullup_ref[micb_index] > 0)
  1310. wcd937x->pullup_ref[micb_index]--;
  1311. if ((wcd937x->pullup_ref[micb_index] == 0) &&
  1312. (wcd937x->micb_ref[micb_index] == 0))
  1313. snd_soc_component_update_bits(component, micb_reg,
  1314. 0xC0, 0x00);
  1315. break;
  1316. case MICB_ENABLE:
  1317. wcd937x->micb_ref[micb_index]++;
  1318. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1319. wcd937x->ana_clk_count++;
  1320. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1321. if (wcd937x->micb_ref[micb_index] == 1) {
  1322. snd_soc_component_update_bits(component,
  1323. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0xE0, 0xE0);
  1324. snd_soc_component_update_bits(component,
  1325. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1326. snd_soc_component_update_bits(component,
  1327. WCD937X_MICB1_TEST_CTL_2, 0x01, 0x01);
  1328. snd_soc_component_update_bits(component,
  1329. WCD937X_MICB2_TEST_CTL_2, 0x01, 0x01);
  1330. snd_soc_component_update_bits(component,
  1331. WCD937X_MICB3_TEST_CTL_2, 0x01, 0x01);
  1332. snd_soc_component_update_bits(component,
  1333. micb_reg, 0xC0, 0x40);
  1334. if (post_on_event)
  1335. blocking_notifier_call_chain(
  1336. &wcd937x->mbhc->notifier, post_on_event,
  1337. &wcd937x->mbhc->wcd_mbhc);
  1338. }
  1339. if (is_dapm && post_dapm_on && wcd937x->mbhc)
  1340. blocking_notifier_call_chain(
  1341. &wcd937x->mbhc->notifier, post_dapm_on,
  1342. &wcd937x->mbhc->wcd_mbhc);
  1343. break;
  1344. case MICB_DISABLE:
  1345. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1346. wcd937x->ana_clk_count--;
  1347. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1348. if (wcd937x->micb_ref[micb_index] > 0)
  1349. wcd937x->micb_ref[micb_index]--;
  1350. if ((wcd937x->micb_ref[micb_index] == 0) &&
  1351. (wcd937x->pullup_ref[micb_index] > 0))
  1352. snd_soc_component_update_bits(component, micb_reg,
  1353. 0xC0, 0x80);
  1354. else if ((wcd937x->micb_ref[micb_index] == 0) &&
  1355. (wcd937x->pullup_ref[micb_index] == 0)) {
  1356. if (pre_off_event && wcd937x->mbhc)
  1357. blocking_notifier_call_chain(
  1358. &wcd937x->mbhc->notifier, pre_off_event,
  1359. &wcd937x->mbhc->wcd_mbhc);
  1360. snd_soc_component_update_bits(component, micb_reg,
  1361. 0xC0, 0x00);
  1362. if (post_off_event && wcd937x->mbhc)
  1363. blocking_notifier_call_chain(
  1364. &wcd937x->mbhc->notifier,
  1365. post_off_event,
  1366. &wcd937x->mbhc->wcd_mbhc);
  1367. }
  1368. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1369. if (wcd937x->ana_clk_count <= 0) {
  1370. snd_soc_component_update_bits(component,
  1371. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  1372. 0x10, 0x00);
  1373. wcd937x->ana_clk_count = 0;
  1374. }
  1375. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1376. if (is_dapm && post_dapm_off && wcd937x->mbhc)
  1377. blocking_notifier_call_chain(
  1378. &wcd937x->mbhc->notifier, post_dapm_off,
  1379. &wcd937x->mbhc->wcd_mbhc);
  1380. break;
  1381. };
  1382. dev_dbg(component->dev, "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1383. __func__, micb_num, wcd937x->micb_ref[micb_index],
  1384. wcd937x->pullup_ref[micb_index]);
  1385. mutex_unlock(&wcd937x->micb_lock);
  1386. return 0;
  1387. }
  1388. EXPORT_SYMBOL(wcd937x_micbias_control);
  1389. static int wcd937x_get_logical_addr(struct swr_device *swr_dev)
  1390. {
  1391. int ret = 0;
  1392. uint8_t devnum = 0;
  1393. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1394. if (ret) {
  1395. dev_err(&swr_dev->dev,
  1396. "%s get devnum %d for dev addr %lx failed\n",
  1397. __func__, devnum, swr_dev->addr);
  1398. return ret;
  1399. }
  1400. swr_dev->dev_num = devnum;
  1401. return 0;
  1402. }
  1403. static int wcd937x_event_notify(struct notifier_block *block,
  1404. unsigned long val,
  1405. void *data)
  1406. {
  1407. u16 event = (val & 0xffff);
  1408. u16 amic = (val >> 0x10);
  1409. u16 mask = 0x40, reg = 0x0;
  1410. int ret = 0;
  1411. struct wcd937x_priv *wcd937x = dev_get_drvdata((struct device *)data);
  1412. struct snd_soc_component *component = wcd937x->component;
  1413. struct wcd_mbhc *mbhc;
  1414. switch (event) {
  1415. case BOLERO_WCD_EVT_TX_CH_HOLD_CLEAR:
  1416. if (amic == 0x1 || amic == 0x2)
  1417. reg = WCD937X_ANA_TX_CH2;
  1418. else if (amic == 0x3)
  1419. reg = WCD937X_ANA_TX_CH3_HPF;
  1420. else
  1421. return 0;
  1422. if (amic == 0x2)
  1423. mask = 0x20;
  1424. snd_soc_component_update_bits(component, reg, mask, 0x00);
  1425. break;
  1426. case BOLERO_WCD_EVT_PA_OFF_PRE_SSR:
  1427. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  1428. 0xC0, 0x00);
  1429. snd_soc_component_update_bits(component, WCD937X_ANA_EAR,
  1430. 0x80, 0x00);
  1431. snd_soc_component_update_bits(component, WCD937X_AUX_AUXPA,
  1432. 0x80, 0x00);
  1433. break;
  1434. case BOLERO_WCD_EVT_SSR_DOWN:
  1435. mbhc = &wcd937x->mbhc->wcd_mbhc;
  1436. wcd937x_mbhc_ssr_down(wcd937x->mbhc, component);
  1437. wcd937x_reset_low(wcd937x->dev);
  1438. break;
  1439. case BOLERO_WCD_EVT_SSR_UP:
  1440. wcd937x_reset(wcd937x->dev);
  1441. wcd937x_get_logical_addr(wcd937x->tx_swr_dev);
  1442. wcd937x_get_logical_addr(wcd937x->rx_swr_dev);
  1443. regcache_mark_dirty(wcd937x->regmap);
  1444. regcache_sync(wcd937x->regmap);
  1445. /* Enable surge protection */
  1446. snd_soc_component_update_bits(component,
  1447. WCD937X_HPH_SURGE_HPHLR_SURGE_EN,
  1448. 0xFF, 0xD9);
  1449. /* Initialize MBHC module */
  1450. mbhc = &wcd937x->mbhc->wcd_mbhc;
  1451. ret = wcd937x_mbhc_post_ssr_init(wcd937x->mbhc, component);
  1452. if (ret) {
  1453. dev_err(component->dev, "%s: mbhc initialization failed\n",
  1454. __func__);
  1455. } else {
  1456. wcd937x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  1457. }
  1458. break;
  1459. default:
  1460. dev_err(component->dev, "%s: invalid event %d\n", __func__,
  1461. event);
  1462. break;
  1463. }
  1464. return 0;
  1465. }
  1466. static int __wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1467. int event)
  1468. {
  1469. struct snd_soc_component *component =
  1470. snd_soc_dapm_to_component(w->dapm);
  1471. int micb_num;
  1472. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1473. __func__, w->name, event);
  1474. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  1475. micb_num = MIC_BIAS_1;
  1476. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  1477. micb_num = MIC_BIAS_2;
  1478. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  1479. micb_num = MIC_BIAS_3;
  1480. else
  1481. return -EINVAL;
  1482. switch (event) {
  1483. case SND_SOC_DAPM_PRE_PMU:
  1484. wcd937x_micbias_control(component, micb_num,
  1485. MICB_ENABLE, true);
  1486. break;
  1487. case SND_SOC_DAPM_POST_PMU:
  1488. usleep_range(1000, 1100);
  1489. break;
  1490. case SND_SOC_DAPM_POST_PMD:
  1491. wcd937x_micbias_control(component, micb_num,
  1492. MICB_DISABLE, true);
  1493. break;
  1494. };
  1495. return 0;
  1496. }
  1497. static int wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1498. struct snd_kcontrol *kcontrol,
  1499. int event)
  1500. {
  1501. return __wcd937x_codec_enable_micbias(w, event);
  1502. }
  1503. static int wcd937x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  1504. struct snd_ctl_elem_value *ucontrol)
  1505. {
  1506. struct snd_soc_component *component =
  1507. snd_soc_kcontrol_component(kcontrol);
  1508. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1509. ucontrol->value.integer.value[0] = wcd937x->hph_mode;
  1510. return 0;
  1511. }
  1512. static int wcd937x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  1513. struct snd_ctl_elem_value *ucontrol)
  1514. {
  1515. struct snd_soc_component *component =
  1516. snd_soc_kcontrol_component(kcontrol);
  1517. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1518. u32 mode_val;
  1519. mode_val = ucontrol->value.enumerated.item[0];
  1520. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  1521. if (mode_val == 0) {
  1522. dev_warn(component->dev, "%s:Invalid HPH Mode, default to class_AB\n",
  1523. __func__);
  1524. mode_val = 3; /* enum will be updated later */
  1525. }
  1526. wcd937x->hph_mode = mode_val;
  1527. return 0;
  1528. }
  1529. static int wcd937x_ear_pa_gain_get(struct snd_kcontrol *kcontrol,
  1530. struct snd_ctl_elem_value *ucontrol)
  1531. {
  1532. u8 ear_pa_gain = 0;
  1533. struct snd_soc_component *component =
  1534. snd_soc_kcontrol_component(kcontrol);
  1535. ear_pa_gain = snd_soc_component_read32(component,
  1536. WCD937X_ANA_EAR_COMPANDER_CTL);
  1537. ear_pa_gain = (ear_pa_gain & 0x7C) >> 2;
  1538. ucontrol->value.integer.value[0] = ear_pa_gain;
  1539. dev_dbg(component->dev, "%s: ear_pa_gain = 0x%x\n", __func__,
  1540. ear_pa_gain);
  1541. return 0;
  1542. }
  1543. static int wcd937x_ear_pa_gain_put(struct snd_kcontrol *kcontrol,
  1544. struct snd_ctl_elem_value *ucontrol)
  1545. {
  1546. u8 ear_pa_gain = 0;
  1547. struct snd_soc_component *component =
  1548. snd_soc_kcontrol_component(kcontrol);
  1549. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1550. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  1551. __func__, ucontrol->value.integer.value[0]);
  1552. ear_pa_gain = ucontrol->value.integer.value[0] << 2;
  1553. if (!wcd937x->comp1_enable) {
  1554. snd_soc_component_update_bits(component,
  1555. WCD937X_ANA_EAR_COMPANDER_CTL,
  1556. 0x7C, ear_pa_gain);
  1557. }
  1558. return 0;
  1559. }
  1560. static int wcd937x_get_compander(struct snd_kcontrol *kcontrol,
  1561. struct snd_ctl_elem_value *ucontrol)
  1562. {
  1563. struct snd_soc_component *component =
  1564. snd_soc_kcontrol_component(kcontrol);
  1565. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1566. bool hphr;
  1567. struct soc_multi_mixer_control *mc;
  1568. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1569. hphr = mc->shift;
  1570. ucontrol->value.integer.value[0] = hphr ? wcd937x->comp2_enable :
  1571. wcd937x->comp1_enable;
  1572. return 0;
  1573. }
  1574. static int wcd937x_set_compander(struct snd_kcontrol *kcontrol,
  1575. struct snd_ctl_elem_value *ucontrol)
  1576. {
  1577. struct snd_soc_component *component =
  1578. snd_soc_kcontrol_component(kcontrol);
  1579. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1580. int value = ucontrol->value.integer.value[0];
  1581. bool hphr;
  1582. struct soc_multi_mixer_control *mc;
  1583. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1584. hphr = mc->shift;
  1585. if (hphr)
  1586. wcd937x->comp2_enable = value;
  1587. else
  1588. wcd937x->comp1_enable = value;
  1589. return 0;
  1590. }
  1591. static int wcd937x_codec_enable_vdd_buck(struct snd_soc_dapm_widget *w,
  1592. struct snd_kcontrol *kcontrol,
  1593. int event)
  1594. {
  1595. struct snd_soc_component *component =
  1596. snd_soc_dapm_to_component(w->dapm);
  1597. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1598. struct wcd937x_pdata *pdata = NULL;
  1599. int ret = 0;
  1600. pdata = dev_get_platdata(wcd937x->dev);
  1601. if (!pdata) {
  1602. dev_err(component->dev, "%s: pdata is NULL\n", __func__);
  1603. return -EINVAL;
  1604. }
  1605. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1606. w->name, event);
  1607. switch (event) {
  1608. case SND_SOC_DAPM_PRE_PMU:
  1609. if (test_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask)) {
  1610. dev_dbg(component->dev,
  1611. "%s: buck already in enabled state\n",
  1612. __func__);
  1613. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1614. return 0;
  1615. }
  1616. ret = msm_cdc_enable_ondemand_supply(wcd937x->dev,
  1617. wcd937x->supplies,
  1618. pdata->regulator,
  1619. pdata->num_supplies,
  1620. "cdc-vdd-buck");
  1621. if (ret == -EINVAL) {
  1622. dev_err(component->dev, "%s: vdd buck is not enabled\n",
  1623. __func__);
  1624. return ret;
  1625. }
  1626. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1627. /*
  1628. * 200us sleep is required after LDO15 is enabled as per
  1629. * HW requirement
  1630. */
  1631. usleep_range(200, 250);
  1632. break;
  1633. case SND_SOC_DAPM_POST_PMD:
  1634. set_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1635. break;
  1636. }
  1637. return 0;
  1638. }
  1639. static const char * const rx_hph_mode_mux_text[] = {
  1640. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  1641. "CLS_H_ULP", "CLS_AB_HIFI",
  1642. };
  1643. static const char * const wcd937x_ear_pa_gain_text[] = {
  1644. "G_6_DB", "G_4P5_DB", "G_3_DB", "G_1P5_DB", "G_0_DB",
  1645. "G_M1P5_DB", "G_M3_DB", "G_M4P5_DB",
  1646. "G_M6_DB", "G_7P5_DB", "G_M9_DB",
  1647. "G_M10P5_DB", "G_M12_DB", "G_M13P5_DB",
  1648. "G_M15_DB", "G_M16P5_DB", "G_M18_DB",
  1649. };
  1650. static const struct soc_enum rx_hph_mode_mux_enum =
  1651. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  1652. rx_hph_mode_mux_text);
  1653. static SOC_ENUM_SINGLE_EXT_DECL(wcd937x_ear_pa_gain_enum,
  1654. wcd937x_ear_pa_gain_text);
  1655. static const struct snd_kcontrol_new wcd937x_snd_controls[] = {
  1656. SOC_ENUM_EXT("EAR PA GAIN", wcd937x_ear_pa_gain_enum,
  1657. wcd937x_ear_pa_gain_get, wcd937x_ear_pa_gain_put),
  1658. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  1659. wcd937x_rx_hph_mode_get, wcd937x_rx_hph_mode_put),
  1660. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  1661. wcd937x_get_compander, wcd937x_set_compander),
  1662. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  1663. wcd937x_get_compander, wcd937x_set_compander),
  1664. SOC_SINGLE_TLV("HPHL Volume", WCD937X_HPH_L_EN, 0, 20, 1, line_gain),
  1665. SOC_SINGLE_TLV("HPHR Volume", WCD937X_HPH_R_EN, 0, 20, 1, line_gain),
  1666. SOC_SINGLE_TLV("ADC1 Volume", WCD937X_ANA_TX_CH1, 0, 20, 0,
  1667. analog_gain),
  1668. SOC_SINGLE_TLV("ADC2 Volume", WCD937X_ANA_TX_CH2, 0, 20, 0,
  1669. analog_gain),
  1670. SOC_SINGLE_TLV("ADC3 Volume", WCD937X_ANA_TX_CH3, 0, 20, 0,
  1671. analog_gain),
  1672. };
  1673. static const struct snd_kcontrol_new adc1_switch[] = {
  1674. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1675. };
  1676. static const struct snd_kcontrol_new adc2_switch[] = {
  1677. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1678. };
  1679. static const struct snd_kcontrol_new adc3_switch[] = {
  1680. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1681. };
  1682. static const struct snd_kcontrol_new dmic1_switch[] = {
  1683. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1684. };
  1685. static const struct snd_kcontrol_new dmic2_switch[] = {
  1686. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1687. };
  1688. static const struct snd_kcontrol_new dmic3_switch[] = {
  1689. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1690. };
  1691. static const struct snd_kcontrol_new dmic4_switch[] = {
  1692. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1693. };
  1694. static const struct snd_kcontrol_new dmic5_switch[] = {
  1695. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1696. };
  1697. static const struct snd_kcontrol_new dmic6_switch[] = {
  1698. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1699. };
  1700. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  1701. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1702. };
  1703. static const struct snd_kcontrol_new aux_rdac_switch[] = {
  1704. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1705. };
  1706. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  1707. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1708. };
  1709. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  1710. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1711. };
  1712. static const char * const adc2_mux_text[] = {
  1713. "INP2", "INP3"
  1714. };
  1715. static const char * const rdac3_mux_text[] = {
  1716. "RX1", "RX3"
  1717. };
  1718. static const struct soc_enum adc2_enum =
  1719. SOC_ENUM_SINGLE(WCD937X_TX_NEW_TX_CH2_SEL, 7,
  1720. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  1721. static const struct soc_enum rdac3_enum =
  1722. SOC_ENUM_SINGLE(WCD937X_DIGITAL_CDC_EAR_PATH_CTL, 0,
  1723. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  1724. static const struct snd_kcontrol_new tx_adc2_mux =
  1725. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  1726. static const struct snd_kcontrol_new rx_rdac3_mux =
  1727. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  1728. static const struct snd_soc_dapm_widget wcd937x_dapm_widgets[] = {
  1729. /*input widgets*/
  1730. SND_SOC_DAPM_INPUT("AMIC1"),
  1731. SND_SOC_DAPM_INPUT("AMIC2"),
  1732. SND_SOC_DAPM_INPUT("AMIC3"),
  1733. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  1734. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  1735. SND_SOC_DAPM_INPUT("IN3_AUX"),
  1736. /*tx widgets*/
  1737. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  1738. wcd937x_codec_enable_adc,
  1739. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1740. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
  1741. wcd937x_codec_enable_adc,
  1742. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1743. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  1744. NULL, 0, wcd937x_enable_req,
  1745. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1746. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 0, 0,
  1747. NULL, 0, wcd937x_enable_req,
  1748. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1749. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  1750. &tx_adc2_mux),
  1751. /*tx mixers*/
  1752. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0,
  1753. adc1_switch, ARRAY_SIZE(adc1_switch),
  1754. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1755. SND_SOC_DAPM_POST_PMD),
  1756. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 0, 0,
  1757. adc2_switch, ARRAY_SIZE(adc2_switch),
  1758. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1759. SND_SOC_DAPM_POST_PMD),
  1760. /* micbias widgets*/
  1761. SND_SOC_DAPM_MICBIAS_E("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  1762. wcd937x_codec_enable_micbias,
  1763. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1764. SND_SOC_DAPM_POST_PMD),
  1765. SND_SOC_DAPM_MICBIAS_E("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  1766. wcd937x_codec_enable_micbias,
  1767. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1768. SND_SOC_DAPM_POST_PMD),
  1769. SND_SOC_DAPM_MICBIAS_E("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  1770. wcd937x_codec_enable_micbias,
  1771. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1772. SND_SOC_DAPM_POST_PMD),
  1773. SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0,
  1774. wcd937x_codec_enable_vdd_buck,
  1775. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1776. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  1777. wcd937x_enable_clsh,
  1778. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1779. /*rx widgets*/
  1780. SND_SOC_DAPM_PGA_E("EAR PGA", WCD937X_ANA_EAR, 7, 0, NULL, 0,
  1781. wcd937x_codec_enable_ear_pa,
  1782. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1783. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1784. SND_SOC_DAPM_PGA_E("AUX PGA", WCD937X_AUX_AUXPA, 7, 0, NULL, 0,
  1785. wcd937x_codec_enable_aux_pa,
  1786. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1787. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1788. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD937X_ANA_HPH, 7, 0, NULL, 0,
  1789. wcd937x_codec_enable_hphl_pa,
  1790. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1791. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1792. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD937X_ANA_HPH, 6, 0, NULL, 0,
  1793. wcd937x_codec_enable_hphr_pa,
  1794. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1795. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1796. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  1797. wcd937x_codec_hphl_dac_event,
  1798. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1799. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1800. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  1801. wcd937x_codec_hphr_dac_event,
  1802. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1803. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1804. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  1805. wcd937x_codec_ear_dac_event,
  1806. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1807. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1808. SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
  1809. wcd937x_codec_aux_dac_event,
  1810. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1811. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1812. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  1813. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  1814. wcd937x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  1815. SND_SOC_DAPM_POST_PMD),
  1816. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  1817. wcd937x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  1818. SND_SOC_DAPM_POST_PMD),
  1819. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  1820. wcd937x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  1821. SND_SOC_DAPM_POST_PMD),
  1822. /* rx mixer widgets*/
  1823. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  1824. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  1825. SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
  1826. aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
  1827. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  1828. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  1829. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  1830. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  1831. /*output widgets tx*/
  1832. SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
  1833. SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
  1834. /*output widgets rx*/
  1835. SND_SOC_DAPM_OUTPUT("EAR"),
  1836. SND_SOC_DAPM_OUTPUT("AUX"),
  1837. SND_SOC_DAPM_OUTPUT("HPHL"),
  1838. SND_SOC_DAPM_OUTPUT("HPHR"),
  1839. };
  1840. static const struct snd_soc_dapm_widget wcd9375_dapm_widgets[] = {
  1841. /*input widgets*/
  1842. SND_SOC_DAPM_INPUT("AMIC4"),
  1843. /*tx widgets*/
  1844. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
  1845. wcd937x_codec_enable_adc,
  1846. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1847. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 0, 0,
  1848. NULL, 0, wcd937x_enable_req,
  1849. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1850. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  1851. wcd937x_codec_enable_dmic,
  1852. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1853. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  1854. wcd937x_codec_enable_dmic,
  1855. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1856. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  1857. wcd937x_codec_enable_dmic,
  1858. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1859. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  1860. wcd937x_codec_enable_dmic,
  1861. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1862. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  1863. wcd937x_codec_enable_dmic,
  1864. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1865. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  1866. wcd937x_codec_enable_dmic,
  1867. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1868. /*tx mixer widgets*/
  1869. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0,
  1870. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  1871. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1872. SND_SOC_DAPM_POST_PMD),
  1873. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 0,
  1874. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  1875. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1876. SND_SOC_DAPM_POST_PMD),
  1877. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 0,
  1878. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  1879. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1880. SND_SOC_DAPM_POST_PMD),
  1881. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 0,
  1882. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  1883. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1884. SND_SOC_DAPM_POST_PMD),
  1885. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 0,
  1886. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  1887. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1888. SND_SOC_DAPM_POST_PMD),
  1889. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 0,
  1890. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  1891. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1892. SND_SOC_DAPM_POST_PMD),
  1893. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 0, 0, adc3_switch,
  1894. ARRAY_SIZE(adc3_switch), wcd937x_tx_swr_ctrl,
  1895. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1896. /*output widgets*/
  1897. SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
  1898. SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
  1899. SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
  1900. SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
  1901. SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
  1902. SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
  1903. SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
  1904. };
  1905. static const struct snd_soc_dapm_route wcd937x_audio_map[] = {
  1906. {"ADC1_OUTPUT", NULL, "ADC1_MIXER"},
  1907. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  1908. {"ADC1 REQ", NULL, "ADC1"},
  1909. {"ADC1", NULL, "AMIC1"},
  1910. {"ADC2_OUTPUT", NULL, "ADC2_MIXER"},
  1911. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  1912. {"ADC2 REQ", NULL, "ADC2"},
  1913. {"ADC2", NULL, "ADC2 MUX"},
  1914. {"ADC2 MUX", "INP3", "AMIC3"},
  1915. {"ADC2 MUX", "INP2", "AMIC2"},
  1916. {"IN1_HPHL", NULL, "VDD_BUCK"},
  1917. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  1918. {"RX1", NULL, "IN1_HPHL"},
  1919. {"RDAC1", NULL, "RX1"},
  1920. {"HPHL_RDAC", "Switch", "RDAC1"},
  1921. {"HPHL PGA", NULL, "HPHL_RDAC"},
  1922. {"HPHL", NULL, "HPHL PGA"},
  1923. {"IN2_HPHR", NULL, "VDD_BUCK"},
  1924. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  1925. {"RX2", NULL, "IN2_HPHR"},
  1926. {"RDAC2", NULL, "RX2"},
  1927. {"HPHR_RDAC", "Switch", "RDAC2"},
  1928. {"HPHR PGA", NULL, "HPHR_RDAC"},
  1929. {"HPHR", NULL, "HPHR PGA"},
  1930. {"IN3_AUX", NULL, "VDD_BUCK"},
  1931. {"IN3_AUX", NULL, "CLS_H_PORT"},
  1932. {"RX3", NULL, "IN3_AUX"},
  1933. {"RDAC4", NULL, "RX3"},
  1934. {"AUX_RDAC", "Switch", "RDAC4"},
  1935. {"AUX PGA", NULL, "AUX_RDAC"},
  1936. {"AUX", NULL, "AUX PGA"},
  1937. {"RDAC3_MUX", "RX3", "RX3"},
  1938. {"RDAC3_MUX", "RX1", "RX1"},
  1939. {"RDAC3", NULL, "RDAC3_MUX"},
  1940. {"EAR_RDAC", "Switch", "RDAC3"},
  1941. {"EAR PGA", NULL, "EAR_RDAC"},
  1942. {"EAR", NULL, "EAR PGA"},
  1943. };
  1944. static const struct snd_soc_dapm_route wcd9375_audio_map[] = {
  1945. {"ADC3_OUTPUT", NULL, "ADC3_MIXER"},
  1946. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  1947. {"ADC3 REQ", NULL, "ADC3"},
  1948. {"ADC3", NULL, "AMIC4"},
  1949. {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
  1950. {"DMIC1_MIXER", "Switch", "DMIC1"},
  1951. {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
  1952. {"DMIC2_MIXER", "Switch", "DMIC2"},
  1953. {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
  1954. {"DMIC3_MIXER", "Switch", "DMIC3"},
  1955. {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
  1956. {"DMIC4_MIXER", "Switch", "DMIC4"},
  1957. {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
  1958. {"DMIC5_MIXER", "Switch", "DMIC5"},
  1959. {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
  1960. {"DMIC6_MIXER", "Switch", "DMIC6"},
  1961. };
  1962. static ssize_t wcd937x_version_read(struct snd_info_entry *entry,
  1963. void *file_private_data,
  1964. struct file *file,
  1965. char __user *buf, size_t count,
  1966. loff_t pos)
  1967. {
  1968. struct wcd937x_priv *priv;
  1969. char buffer[WCD937X_VERSION_ENTRY_SIZE];
  1970. int len = 0;
  1971. priv = (struct wcd937x_priv *) entry->private_data;
  1972. if (!priv) {
  1973. pr_err("%s: wcd937x priv is null\n", __func__);
  1974. return -EINVAL;
  1975. }
  1976. switch (priv->version) {
  1977. case WCD937X_VERSION_1_0:
  1978. len = snprintf(buffer, sizeof(buffer), "WCD937X_1_0\n");
  1979. break;
  1980. default:
  1981. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  1982. }
  1983. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  1984. }
  1985. static struct snd_info_entry_ops wcd937x_info_ops = {
  1986. .read = wcd937x_version_read,
  1987. };
  1988. static ssize_t wcd937x_variant_read(struct snd_info_entry *entry,
  1989. void *file_private_data,
  1990. struct file *file,
  1991. char __user *buf, size_t count,
  1992. loff_t pos)
  1993. {
  1994. struct wcd937x_priv *priv;
  1995. char buffer[WCD937X_VARIANT_ENTRY_SIZE];
  1996. int len = 0;
  1997. priv = (struct wcd937x_priv *) entry->private_data;
  1998. if (!priv) {
  1999. pr_err("%s: wcd937x priv is null\n", __func__);
  2000. return -EINVAL;
  2001. }
  2002. switch (priv->variant) {
  2003. case WCD9370_VARIANT:
  2004. len = snprintf(buffer, sizeof(buffer), "WCD9370\n");
  2005. break;
  2006. case WCD9375_VARIANT:
  2007. len = snprintf(buffer, sizeof(buffer), "WCD9375\n");
  2008. break;
  2009. default:
  2010. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2011. }
  2012. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2013. }
  2014. static struct snd_info_entry_ops wcd937x_variant_ops = {
  2015. .read = wcd937x_variant_read,
  2016. };
  2017. /*
  2018. * wcd937x_info_create_codec_entry - creates wcd937x module
  2019. * @codec_root: The parent directory
  2020. * @component: component instance
  2021. *
  2022. * Creates wcd937x module, variant and version entry under the given
  2023. * parent directory.
  2024. *
  2025. * Return: 0 on success or negative error code on failure.
  2026. */
  2027. int wcd937x_info_create_codec_entry(struct snd_info_entry *codec_root,
  2028. struct snd_soc_component *component)
  2029. {
  2030. struct snd_info_entry *version_entry;
  2031. struct snd_info_entry *variant_entry;
  2032. struct wcd937x_priv *priv;
  2033. struct snd_soc_card *card;
  2034. if (!codec_root || !component)
  2035. return -EINVAL;
  2036. priv = snd_soc_component_get_drvdata(component);
  2037. if (priv->entry) {
  2038. dev_dbg(priv->dev,
  2039. "%s:wcd937x module already created\n", __func__);
  2040. return 0;
  2041. }
  2042. card = component->card;
  2043. priv->entry = snd_info_create_subdir(codec_root->module,
  2044. "wcd937x", codec_root);
  2045. if (!priv->entry) {
  2046. dev_dbg(component->dev, "%s: failed to create wcd937x entry\n",
  2047. __func__);
  2048. return -ENOMEM;
  2049. }
  2050. version_entry = snd_info_create_card_entry(card->snd_card,
  2051. "version",
  2052. priv->entry);
  2053. if (!version_entry) {
  2054. dev_dbg(component->dev, "%s: failed to create wcd937x version entry\n",
  2055. __func__);
  2056. return -ENOMEM;
  2057. }
  2058. version_entry->private_data = priv;
  2059. version_entry->size = WCD937X_VERSION_ENTRY_SIZE;
  2060. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  2061. version_entry->c.ops = &wcd937x_info_ops;
  2062. if (snd_info_register(version_entry) < 0) {
  2063. snd_info_free_entry(version_entry);
  2064. return -ENOMEM;
  2065. }
  2066. priv->version_entry = version_entry;
  2067. variant_entry = snd_info_create_card_entry(card->snd_card,
  2068. "variant",
  2069. priv->entry);
  2070. if (!variant_entry) {
  2071. dev_dbg(component->dev,
  2072. "%s: failed to create wcd937x variant entry\n",
  2073. __func__);
  2074. return -ENOMEM;
  2075. }
  2076. variant_entry->private_data = priv;
  2077. variant_entry->size = WCD937X_VARIANT_ENTRY_SIZE;
  2078. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  2079. variant_entry->c.ops = &wcd937x_variant_ops;
  2080. if (snd_info_register(variant_entry) < 0) {
  2081. snd_info_free_entry(variant_entry);
  2082. return -ENOMEM;
  2083. }
  2084. priv->variant_entry = variant_entry;
  2085. return 0;
  2086. }
  2087. EXPORT_SYMBOL(wcd937x_info_create_codec_entry);
  2088. static int wcd937x_set_micbias_data(struct wcd937x_priv *wcd937x,
  2089. struct wcd937x_pdata *pdata)
  2090. {
  2091. int vout_ctl_1 = 0, vout_ctl_2 = 0, vout_ctl_3 = 0;
  2092. int rc = 0;
  2093. if (!pdata) {
  2094. dev_err(wcd937x->dev, "%s: NULL pdata\n", __func__);
  2095. return -ENODEV;
  2096. }
  2097. /* set micbias voltage */
  2098. vout_ctl_1 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb1_mv);
  2099. vout_ctl_2 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb2_mv);
  2100. vout_ctl_3 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb3_mv);
  2101. if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0) {
  2102. rc = -EINVAL;
  2103. goto done;
  2104. }
  2105. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB1, 0x3F,
  2106. vout_ctl_1);
  2107. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB2, 0x3F,
  2108. vout_ctl_2);
  2109. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB3, 0x3F,
  2110. vout_ctl_3);
  2111. done:
  2112. return rc;
  2113. }
  2114. static int wcd937x_soc_codec_probe(struct snd_soc_component *component)
  2115. {
  2116. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  2117. struct snd_soc_dapm_context *dapm =
  2118. snd_soc_component_get_dapm(component);
  2119. int variant;
  2120. int ret = -EINVAL;
  2121. dev_info(component->dev, "%s()\n", __func__);
  2122. wcd937x = snd_soc_component_get_drvdata(component);
  2123. if (!wcd937x)
  2124. return -EINVAL;
  2125. wcd937x->component = component;
  2126. variant = (snd_soc_component_read32(
  2127. component, WCD937X_DIGITAL_EFUSE_REG_0) & 0x1E) >> 1;
  2128. wcd937x->variant = variant;
  2129. wcd937x->fw_data = devm_kzalloc(component->dev,
  2130. sizeof(*(wcd937x->fw_data)),
  2131. GFP_KERNEL);
  2132. if (!wcd937x->fw_data) {
  2133. dev_err(component->dev, "Failed to allocate fw_data\n");
  2134. ret = -ENOMEM;
  2135. goto err;
  2136. }
  2137. set_bit(WCD9XXX_MBHC_CAL, wcd937x->fw_data->cal_bit);
  2138. ret = wcd_cal_create_hwdep(wcd937x->fw_data,
  2139. WCD9XXX_CODEC_HWDEP_NODE, component);
  2140. if (ret < 0) {
  2141. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  2142. goto err_hwdep;
  2143. }
  2144. ret = wcd937x_mbhc_init(&wcd937x->mbhc, component, wcd937x->fw_data);
  2145. if (ret) {
  2146. pr_err("%s: mbhc initialization failed\n", __func__);
  2147. goto err_hwdep;
  2148. }
  2149. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  2150. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  2151. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  2152. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  2153. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  2154. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  2155. snd_soc_dapm_ignore_suspend(dapm, "ADC1_OUTPUT");
  2156. snd_soc_dapm_ignore_suspend(dapm, "ADC2_OUTPUT");
  2157. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  2158. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  2159. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  2160. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  2161. snd_soc_dapm_sync(dapm);
  2162. wcd_cls_h_init(&wcd937x->clsh_info);
  2163. wcd937x_init_reg(component);
  2164. if (wcd937x->variant == WCD9375_VARIANT) {
  2165. ret = snd_soc_dapm_new_controls(dapm, wcd9375_dapm_widgets,
  2166. ARRAY_SIZE(wcd9375_dapm_widgets));
  2167. if (ret < 0) {
  2168. dev_err(component->dev, "%s: Failed to add snd_ctls\n",
  2169. __func__);
  2170. goto err_hwdep;
  2171. }
  2172. ret = snd_soc_dapm_add_routes(dapm, wcd9375_audio_map,
  2173. ARRAY_SIZE(wcd9375_audio_map));
  2174. if (ret < 0) {
  2175. dev_err(component->dev, "%s: Failed to add routes\n",
  2176. __func__);
  2177. goto err_hwdep;
  2178. }
  2179. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  2180. snd_soc_dapm_ignore_suspend(dapm, "DMIC1_OUTPUT");
  2181. snd_soc_dapm_ignore_suspend(dapm, "DMIC2_OUTPUT");
  2182. snd_soc_dapm_ignore_suspend(dapm, "DMIC3_OUTPUT");
  2183. snd_soc_dapm_ignore_suspend(dapm, "DMIC4_OUTPUT");
  2184. snd_soc_dapm_ignore_suspend(dapm, "DMIC5_OUTPUT");
  2185. snd_soc_dapm_ignore_suspend(dapm, "DMIC6_OUTPUT");
  2186. snd_soc_dapm_ignore_suspend(dapm, "ADC3_OUTPUT");
  2187. snd_soc_dapm_sync(dapm);
  2188. }
  2189. wcd937x->version = WCD937X_VERSION_1_0;
  2190. /* Register event notifier */
  2191. wcd937x->nblock.notifier_call = wcd937x_event_notify;
  2192. if (wcd937x->register_notifier) {
  2193. ret = wcd937x->register_notifier(wcd937x->handle,
  2194. &wcd937x->nblock,
  2195. true);
  2196. if (ret) {
  2197. dev_err(component->dev,
  2198. "%s: Failed to register notifier %d\n",
  2199. __func__, ret);
  2200. return ret;
  2201. }
  2202. }
  2203. return ret;
  2204. err_hwdep:
  2205. wcd937x->fw_data = NULL;
  2206. err:
  2207. return ret;
  2208. }
  2209. static void wcd937x_soc_codec_remove(struct snd_soc_component *component)
  2210. {
  2211. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  2212. if (!wcd937x)
  2213. return;
  2214. if (wcd937x->register_notifier)
  2215. wcd937x->register_notifier(wcd937x->handle,
  2216. &wcd937x->nblock,
  2217. false);
  2218. return;
  2219. }
  2220. static const struct snd_soc_component_driver soc_codec_dev_wcd937x = {
  2221. .name = DRV_NAME,
  2222. .probe = wcd937x_soc_codec_probe,
  2223. .remove = wcd937x_soc_codec_remove,
  2224. .controls = wcd937x_snd_controls,
  2225. .num_controls = ARRAY_SIZE(wcd937x_snd_controls),
  2226. .dapm_widgets = wcd937x_dapm_widgets,
  2227. .num_dapm_widgets = ARRAY_SIZE(wcd937x_dapm_widgets),
  2228. .dapm_routes = wcd937x_audio_map,
  2229. .num_dapm_routes = ARRAY_SIZE(wcd937x_audio_map),
  2230. };
  2231. #ifdef CONFIG_PM_SLEEP
  2232. static int wcd937x_suspend(struct device *dev)
  2233. {
  2234. struct wcd937x_priv *wcd937x = NULL;
  2235. int ret = 0;
  2236. struct wcd937x_pdata *pdata = NULL;
  2237. if (!dev)
  2238. return -ENODEV;
  2239. wcd937x = dev_get_drvdata(dev);
  2240. if (!wcd937x)
  2241. return -EINVAL;
  2242. pdata = dev_get_platdata(wcd937x->dev);
  2243. if (!pdata) {
  2244. dev_err(dev, "%s: pdata is NULL\n", __func__);
  2245. return -EINVAL;
  2246. }
  2247. if (test_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask)) {
  2248. ret = msm_cdc_disable_ondemand_supply(wcd937x->dev,
  2249. wcd937x->supplies,
  2250. pdata->regulator,
  2251. pdata->num_supplies,
  2252. "cdc-vdd-buck");
  2253. if (ret == -EINVAL) {
  2254. dev_err(dev, "%s: vdd buck is not disabled\n",
  2255. __func__);
  2256. return 0;
  2257. }
  2258. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  2259. }
  2260. return 0;
  2261. }
  2262. static int wcd937x_resume(struct device *dev)
  2263. {
  2264. return 0;
  2265. }
  2266. #endif
  2267. static int wcd937x_reset(struct device *dev)
  2268. {
  2269. struct wcd937x_priv *wcd937x = NULL;
  2270. int rc = 0;
  2271. int value = 0;
  2272. if (!dev)
  2273. return -ENODEV;
  2274. wcd937x = dev_get_drvdata(dev);
  2275. if (!wcd937x)
  2276. return -EINVAL;
  2277. if (!wcd937x->rst_np) {
  2278. dev_err(dev, "%s: reset gpio device node not specified\n",
  2279. __func__);
  2280. return -EINVAL;
  2281. }
  2282. value = msm_cdc_pinctrl_get_state(wcd937x->rst_np);
  2283. if (value > 0)
  2284. return 0;
  2285. rc = msm_cdc_pinctrl_select_sleep_state(wcd937x->rst_np);
  2286. if (rc) {
  2287. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2288. __func__);
  2289. return rc;
  2290. }
  2291. /* 20ms sleep required after pulling the reset gpio to LOW */
  2292. usleep_range(20, 30);
  2293. rc = msm_cdc_pinctrl_select_active_state(wcd937x->rst_np);
  2294. if (rc) {
  2295. dev_err(dev, "%s: wcd active state request fail!\n",
  2296. __func__);
  2297. return rc;
  2298. }
  2299. /* 20ms sleep required after pulling the reset gpio to HIGH */
  2300. usleep_range(20, 30);
  2301. return rc;
  2302. }
  2303. static int wcd937x_read_of_property_u32(struct device *dev, const char *name,
  2304. u32 *val)
  2305. {
  2306. int rc = 0;
  2307. rc = of_property_read_u32(dev->of_node, name, val);
  2308. if (rc)
  2309. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2310. __func__, name, dev->of_node->full_name);
  2311. return rc;
  2312. }
  2313. static void wcd937x_dt_parse_micbias_info(struct device *dev,
  2314. struct wcd937x_micbias_setting *mb)
  2315. {
  2316. u32 prop_val = 0;
  2317. int rc = 0;
  2318. /* MB1 */
  2319. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  2320. NULL)) {
  2321. rc = wcd937x_read_of_property_u32(dev,
  2322. "qcom,cdc-micbias1-mv",
  2323. &prop_val);
  2324. if (!rc)
  2325. mb->micb1_mv = prop_val;
  2326. } else {
  2327. dev_info(dev, "%s: Micbias1 DT property not found\n",
  2328. __func__);
  2329. }
  2330. /* MB2 */
  2331. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  2332. NULL)) {
  2333. rc = wcd937x_read_of_property_u32(dev,
  2334. "qcom,cdc-micbias2-mv",
  2335. &prop_val);
  2336. if (!rc)
  2337. mb->micb2_mv = prop_val;
  2338. } else {
  2339. dev_info(dev, "%s: Micbias2 DT property not found\n",
  2340. __func__);
  2341. }
  2342. /* MB3 */
  2343. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  2344. NULL)) {
  2345. rc = wcd937x_read_of_property_u32(dev,
  2346. "qcom,cdc-micbias3-mv",
  2347. &prop_val);
  2348. if (!rc)
  2349. mb->micb3_mv = prop_val;
  2350. } else {
  2351. dev_info(dev, "%s: Micbias3 DT property not found\n",
  2352. __func__);
  2353. }
  2354. }
  2355. static int wcd937x_reset_low(struct device *dev)
  2356. {
  2357. struct wcd937x_priv *wcd937x = NULL;
  2358. int rc = 0;
  2359. if (!dev)
  2360. return -ENODEV;
  2361. wcd937x = dev_get_drvdata(dev);
  2362. if (!wcd937x)
  2363. return -EINVAL;
  2364. if (!wcd937x->rst_np) {
  2365. dev_err(dev, "%s: reset gpio device node not specified\n",
  2366. __func__);
  2367. return -EINVAL;
  2368. }
  2369. rc = msm_cdc_pinctrl_select_sleep_state(wcd937x->rst_np);
  2370. if (rc) {
  2371. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2372. __func__);
  2373. return rc;
  2374. }
  2375. /* 20ms sleep required after pulling the reset gpio to LOW */
  2376. usleep_range(20, 30);
  2377. return rc;
  2378. }
  2379. struct wcd937x_pdata *wcd937x_populate_dt_data(struct device *dev)
  2380. {
  2381. struct wcd937x_pdata *pdata = NULL;
  2382. pdata = kzalloc(sizeof(struct wcd937x_pdata),
  2383. GFP_KERNEL);
  2384. if (!pdata)
  2385. return NULL;
  2386. pdata->rst_np = of_parse_phandle(dev->of_node,
  2387. "qcom,wcd-rst-gpio-node", 0);
  2388. if (!pdata->rst_np) {
  2389. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2390. __func__, "qcom,wcd-rst-gpio-node",
  2391. dev->of_node->full_name);
  2392. return NULL;
  2393. }
  2394. /* Parse power supplies */
  2395. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  2396. &pdata->num_supplies);
  2397. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  2398. dev_err(dev, "%s: no power supplies defined for codec\n",
  2399. __func__);
  2400. return NULL;
  2401. }
  2402. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  2403. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  2404. wcd937x_dt_parse_micbias_info(dev, &pdata->micbias);
  2405. return pdata;
  2406. }
  2407. static int wcd937x_wakeup(void *handle, bool enable)
  2408. {
  2409. struct wcd937x_priv *priv;
  2410. if (!handle) {
  2411. pr_err("%s: NULL handle\n", __func__);
  2412. return -EINVAL;
  2413. }
  2414. priv = (struct wcd937x_priv *)handle;
  2415. if (!priv->tx_swr_dev) {
  2416. pr_err("%s: tx swr dev is NULL\n", __func__);
  2417. return -EINVAL;
  2418. }
  2419. if (enable)
  2420. return swr_device_wakeup_vote(priv->tx_swr_dev);
  2421. else
  2422. return swr_device_wakeup_unvote(priv->tx_swr_dev);
  2423. }
  2424. static irqreturn_t wcd937x_wd_handle_irq(int irq, void *data)
  2425. {
  2426. pr_err_ratelimited("%s: Watchdog interrupt for irq =%d triggered\n",
  2427. __func__, irq);
  2428. return IRQ_HANDLED;
  2429. }
  2430. static int wcd937x_bind(struct device *dev)
  2431. {
  2432. int ret = 0, i = 0;
  2433. struct wcd937x_priv *wcd937x = NULL;
  2434. struct wcd937x_pdata *pdata = NULL;
  2435. struct wcd_ctrl_platform_data *plat_data = NULL;
  2436. wcd937x = kzalloc(sizeof(struct wcd937x_priv), GFP_KERNEL);
  2437. if (!wcd937x)
  2438. return -ENOMEM;
  2439. dev_set_drvdata(dev, wcd937x);
  2440. pdata = wcd937x_populate_dt_data(dev);
  2441. if (!pdata) {
  2442. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  2443. return -EINVAL;
  2444. }
  2445. wcd937x->dev = dev;
  2446. wcd937x->dev->platform_data = pdata;
  2447. wcd937x->rst_np = pdata->rst_np;
  2448. ret = msm_cdc_init_supplies(dev, &wcd937x->supplies,
  2449. pdata->regulator, pdata->num_supplies);
  2450. if (!wcd937x->supplies) {
  2451. dev_err(dev, "%s: Cannot init wcd supplies\n",
  2452. __func__);
  2453. goto err_bind_all;
  2454. }
  2455. plat_data = dev_get_platdata(dev->parent);
  2456. if (!plat_data) {
  2457. dev_err(dev, "%s: platform data from parent is NULL\n",
  2458. __func__);
  2459. ret = -EINVAL;
  2460. goto err_bind_all;
  2461. }
  2462. wcd937x->handle = (void *)plat_data->handle;
  2463. if (!wcd937x->handle) {
  2464. dev_err(dev, "%s: handle is NULL\n", __func__);
  2465. ret = -EINVAL;
  2466. goto err_bind_all;
  2467. }
  2468. wcd937x->update_wcd_event = plat_data->update_wcd_event;
  2469. if (!wcd937x->update_wcd_event) {
  2470. dev_err(dev, "%s: update_wcd_event api is null!\n",
  2471. __func__);
  2472. ret = -EINVAL;
  2473. goto err_bind_all;
  2474. }
  2475. wcd937x->register_notifier = plat_data->register_notifier;
  2476. if (!wcd937x->register_notifier) {
  2477. dev_err(dev, "%s: register_notifier api is null!\n",
  2478. __func__);
  2479. ret = -EINVAL;
  2480. goto err_bind_all;
  2481. }
  2482. ret = msm_cdc_enable_static_supplies(dev, wcd937x->supplies,
  2483. pdata->regulator,
  2484. pdata->num_supplies);
  2485. if (ret) {
  2486. dev_err(dev, "%s: wcd static supply enable failed!\n",
  2487. __func__);
  2488. goto err_bind_all;
  2489. }
  2490. wcd937x_reset(dev);
  2491. /*
  2492. * Add 5msec delay to provide sufficient time for
  2493. * soundwire auto enumeration of slave devices as
  2494. * as per HW requirement.
  2495. */
  2496. usleep_range(5000, 5010);
  2497. wcd937x->wakeup = wcd937x_wakeup;
  2498. ret = component_bind_all(dev, wcd937x);
  2499. if (ret) {
  2500. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  2501. __func__, ret);
  2502. goto err_bind_all;
  2503. }
  2504. ret = wcd937x_parse_port_mapping(dev, "qcom,rx_swr_ch_map", CODEC_RX);
  2505. ret |= wcd937x_parse_port_mapping(dev, "qcom,tx_swr_ch_map", CODEC_TX);
  2506. if (ret) {
  2507. dev_err(dev, "Failed to read port mapping\n");
  2508. goto err;
  2509. }
  2510. wcd937x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  2511. if (!wcd937x->rx_swr_dev) {
  2512. dev_err(dev, "%s: Could not find RX swr slave device\n",
  2513. __func__);
  2514. ret = -ENODEV;
  2515. goto err;
  2516. }
  2517. wcd937x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  2518. if (!wcd937x->tx_swr_dev) {
  2519. dev_err(dev, "%s: Could not find TX swr slave device\n",
  2520. __func__);
  2521. ret = -ENODEV;
  2522. goto err;
  2523. }
  2524. wcd937x->regmap = devm_regmap_init_swr(wcd937x->tx_swr_dev,
  2525. &wcd937x_regmap_config);
  2526. if (!wcd937x->regmap) {
  2527. dev_err(dev, "%s: Regmap init failed\n",
  2528. __func__);
  2529. goto err;
  2530. }
  2531. /* Set all interupts as edge triggered */
  2532. for (i = 0; i < wcd937x_regmap_irq_chip.num_regs; i++)
  2533. regmap_write(wcd937x->regmap,
  2534. (WCD937X_DIGITAL_INTR_LEVEL_0 + i), 0);
  2535. wcd937x_regmap_irq_chip.irq_drv_data = wcd937x;
  2536. wcd937x->irq_info.wcd_regmap_irq_chip = &wcd937x_regmap_irq_chip;
  2537. wcd937x->irq_info.codec_name = "WCD937X";
  2538. wcd937x->irq_info.regmap = wcd937x->regmap;
  2539. wcd937x->irq_info.dev = dev;
  2540. ret = wcd_irq_init(&wcd937x->irq_info, &wcd937x->virq);
  2541. if (ret) {
  2542. dev_err(dev, "%s: IRQ init failed: %d\n",
  2543. __func__, ret);
  2544. goto err;
  2545. }
  2546. wcd937x->tx_swr_dev->slave_irq = wcd937x->virq;
  2547. ret = wcd937x_set_micbias_data(wcd937x, pdata);
  2548. if (ret < 0) {
  2549. dev_err(dev, "%s: bad micbias pdata\n", __func__);
  2550. goto err_irq;
  2551. }
  2552. mutex_init(&wcd937x->micb_lock);
  2553. mutex_init(&wcd937x->ana_tx_clk_lock);
  2554. /* Request for watchdog interrupt */
  2555. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHR_PDM_WD_INT,
  2556. "HPHR PDM WD INT", wcd937x_wd_handle_irq, NULL);
  2557. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHL_PDM_WD_INT,
  2558. "HPHL PDM WD INT", wcd937x_wd_handle_irq, NULL);
  2559. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT,
  2560. "AUX PDM WD INT", wcd937x_wd_handle_irq, NULL);
  2561. /* Disable watchdog interrupt for HPH and AUX */
  2562. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHR_PDM_WD_INT);
  2563. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHL_PDM_WD_INT);
  2564. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT);
  2565. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd937x,
  2566. NULL, 0);
  2567. if (ret) {
  2568. dev_err(dev, "%s: Codec registration failed\n",
  2569. __func__);
  2570. goto err_irq;
  2571. }
  2572. return ret;
  2573. err_irq:
  2574. wcd_irq_exit(&wcd937x->irq_info, wcd937x->virq);
  2575. err:
  2576. component_unbind_all(dev, wcd937x);
  2577. err_bind_all:
  2578. dev_set_drvdata(dev, NULL);
  2579. kfree(pdata);
  2580. kfree(wcd937x);
  2581. return ret;
  2582. }
  2583. static void wcd937x_unbind(struct device *dev)
  2584. {
  2585. struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
  2586. struct wcd937x_pdata *pdata = dev_get_platdata(wcd937x->dev);
  2587. wcd_irq_exit(&wcd937x->irq_info, wcd937x->virq);
  2588. snd_soc_unregister_component(dev);
  2589. component_unbind_all(dev, wcd937x);
  2590. mutex_destroy(&wcd937x->micb_lock);
  2591. mutex_destroy(&wcd937x->ana_tx_clk_lock);
  2592. dev_set_drvdata(dev, NULL);
  2593. kfree(pdata);
  2594. kfree(wcd937x);
  2595. }
  2596. static const struct of_device_id wcd937x_dt_match[] = {
  2597. { .compatible = "qcom,wcd937x-codec" },
  2598. {}
  2599. };
  2600. static const struct component_master_ops wcd937x_comp_ops = {
  2601. .bind = wcd937x_bind,
  2602. .unbind = wcd937x_unbind,
  2603. };
  2604. static int wcd937x_compare_of(struct device *dev, void *data)
  2605. {
  2606. return dev->of_node == data;
  2607. }
  2608. static void wcd937x_release_of(struct device *dev, void *data)
  2609. {
  2610. of_node_put(data);
  2611. }
  2612. static int wcd937x_add_slave_components(struct device *dev,
  2613. struct component_match **matchptr)
  2614. {
  2615. struct device_node *np, *rx_node, *tx_node;
  2616. np = dev->of_node;
  2617. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  2618. if (!rx_node) {
  2619. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  2620. return -ENODEV;
  2621. }
  2622. of_node_get(rx_node);
  2623. component_match_add_release(dev, matchptr,
  2624. wcd937x_release_of,
  2625. wcd937x_compare_of,
  2626. rx_node);
  2627. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  2628. if (!tx_node) {
  2629. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  2630. return -ENODEV;
  2631. }
  2632. of_node_get(tx_node);
  2633. component_match_add_release(dev, matchptr,
  2634. wcd937x_release_of,
  2635. wcd937x_compare_of,
  2636. tx_node);
  2637. return 0;
  2638. }
  2639. static int wcd937x_probe(struct platform_device *pdev)
  2640. {
  2641. struct component_match *match = NULL;
  2642. int ret;
  2643. ret = wcd937x_add_slave_components(&pdev->dev, &match);
  2644. if (ret)
  2645. return ret;
  2646. return component_master_add_with_match(&pdev->dev,
  2647. &wcd937x_comp_ops, match);
  2648. }
  2649. static int wcd937x_remove(struct platform_device *pdev)
  2650. {
  2651. component_master_del(&pdev->dev, &wcd937x_comp_ops);
  2652. dev_set_drvdata(&pdev->dev, NULL);
  2653. return 0;
  2654. }
  2655. #ifdef CONFIG_PM_SLEEP
  2656. static const struct dev_pm_ops wcd937x_dev_pm_ops = {
  2657. SET_SYSTEM_SLEEP_PM_OPS(
  2658. wcd937x_suspend,
  2659. wcd937x_resume
  2660. )
  2661. };
  2662. #endif
  2663. static struct platform_driver wcd937x_codec_driver = {
  2664. .probe = wcd937x_probe,
  2665. .remove = wcd937x_remove,
  2666. .driver = {
  2667. .name = "wcd937x_codec",
  2668. .owner = THIS_MODULE,
  2669. .of_match_table = of_match_ptr(wcd937x_dt_match),
  2670. #ifdef CONFIG_PM_SLEEP
  2671. .pm = &wcd937x_dev_pm_ops,
  2672. #endif
  2673. .suppress_bind_attrs = true,
  2674. },
  2675. };
  2676. module_platform_driver(wcd937x_codec_driver);
  2677. MODULE_DESCRIPTION("WCD937X Codec driver");
  2678. MODULE_LICENSE("GPL v2");