wcd938x.c 115 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/slab.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/device.h>
  9. #include <linux/delay.h>
  10. #include <linux/kernel.h>
  11. #include <linux/component.h>
  12. #include <sound/soc.h>
  13. #include <sound/tlv.h>
  14. #include <soc/soundwire.h>
  15. #include <linux/regmap.h>
  16. #include <sound/soc.h>
  17. #include <sound/soc-dapm.h>
  18. #include <asoc/wcdcal-hwdep.h>
  19. #include <asoc/msm-cdc-pinctrl.h>
  20. #include <asoc/msm-cdc-supply.h>
  21. #include <dt-bindings/sound/audio-codec-port-types.h>
  22. #include "wcd938x-registers.h"
  23. #include "wcd938x.h"
  24. #include "internal.h"
  25. #define WCD938X_DRV_NAME "wcd938x_codec"
  26. #define NUM_SWRS_DT_PARAMS 5
  27. #define WCD938X_VARIANT_ENTRY_SIZE 32
  28. #define WCD938X_VERSION_1_0 1
  29. #define WCD938X_VERSION_ENTRY_SIZE 32
  30. #define EAR_RX_PATH_AUX 1
  31. #define ADC_MODE_VAL_HIFI 0x01
  32. #define ADC_MODE_VAL_LO_HIF 0x02
  33. #define ADC_MODE_VAL_NORMAL 0x03
  34. #define ADC_MODE_VAL_LP 0x05
  35. #define ADC_MODE_VAL_ULP1 0x09
  36. #define ADC_MODE_VAL_ULP2 0x0B
  37. #define NUM_ATTEMPTS 5
  38. #define DAPM_MICBIAS1_STANDALONE "MIC BIAS1 Standalone"
  39. #define DAPM_MICBIAS2_STANDALONE "MIC BIAS2 Standalone"
  40. #define DAPM_MICBIAS3_STANDALONE "MIC BIAS3 Standalone"
  41. #define DAPM_MICBIAS4_STANDALONE "MIC BIAS4 Standalone"
  42. enum {
  43. CODEC_TX = 0,
  44. CODEC_RX,
  45. };
  46. enum {
  47. WCD_ADC1 = 0,
  48. WCD_ADC2,
  49. WCD_ADC3,
  50. WCD_ADC4,
  51. ALLOW_BUCK_DISABLE,
  52. HPH_COMP_DELAY,
  53. HPH_PA_DELAY,
  54. AMIC2_BCS_ENABLE,
  55. };
  56. enum {
  57. ADC_MODE_INVALID = 0,
  58. ADC_MODE_HIFI,
  59. ADC_MODE_LO_HIF,
  60. ADC_MODE_NORMAL,
  61. ADC_MODE_LP,
  62. ADC_MODE_ULP1,
  63. ADC_MODE_ULP2,
  64. };
  65. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  66. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  67. static int wcd938x_handle_post_irq(void *data);
  68. static int wcd938x_reset(struct device *dev);
  69. static int wcd938x_reset_low(struct device *dev);
  70. static const struct regmap_irq wcd938x_irqs[WCD938X_NUM_IRQS] = {
  71. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  72. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  73. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  74. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  75. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_SW_DET, 0, 0x10),
  76. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_OCP_INT, 0, 0x20),
  77. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_CNP_INT, 0, 0x40),
  78. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_OCP_INT, 0, 0x80),
  79. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_CNP_INT, 1, 0x01),
  80. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_CNP_INT, 1, 0x02),
  81. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_SCD_INT, 1, 0x04),
  82. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_CNP_INT, 1, 0x08),
  83. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_SCD_INT, 1, 0x10),
  84. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  85. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  86. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  87. REGMAP_IRQ_REG(WCD938X_IRQ_LDORT_SCD_INT, 2, 0x01),
  88. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  89. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  90. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  91. };
  92. static struct regmap_irq_chip wcd938x_regmap_irq_chip = {
  93. .name = "wcd938x",
  94. .irqs = wcd938x_irqs,
  95. .num_irqs = ARRAY_SIZE(wcd938x_irqs),
  96. .num_regs = 3,
  97. .status_base = WCD938X_DIGITAL_INTR_STATUS_0,
  98. .mask_base = WCD938X_DIGITAL_INTR_MASK_0,
  99. .type_base = WCD938X_DIGITAL_INTR_LEVEL_0,
  100. .ack_base = WCD938X_DIGITAL_INTR_CLEAR_0,
  101. .use_ack = 1,
  102. .runtime_pm = false,
  103. .handle_post_irq = wcd938x_handle_post_irq,
  104. .irq_drv_data = NULL,
  105. };
  106. static int wcd938x_handle_post_irq(void *data)
  107. {
  108. struct wcd938x_priv *wcd938x = data;
  109. u32 sts1 = 0, sts2 = 0, sts3 = 0;
  110. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_0, &sts1);
  111. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_1, &sts2);
  112. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_2, &sts3);
  113. wcd938x->tx_swr_dev->slave_irq_pending =
  114. ((sts1 || sts2 || sts3) ? true : false);
  115. return IRQ_HANDLED;
  116. }
  117. static int wcd938x_swr_slv_get_current_bank(struct swr_device *dev, u8 devnum)
  118. {
  119. int ret = 0;
  120. int bank = 0;
  121. ret = swr_read(dev, devnum, SWR_SCP_CONTROL, &bank, 1);
  122. if (ret)
  123. return -EINVAL;
  124. return ((bank & 0x40) ? 1: 0);
  125. }
  126. static int wcd938x_swr_slv_set_host_clk_div2(struct swr_device *dev,
  127. u8 devnum, int bank)
  128. {
  129. u8 val = (bank ? 1 : 0);
  130. return (swr_write(dev, devnum,
  131. (SWR_SCP_HOST_CLK_DIV2_CTL_BANK + (0x10 * bank)), &val));
  132. }
  133. static int wcd938x_set_swr_clk_rate(struct snd_soc_component *component,
  134. int mode, int bank)
  135. {
  136. u8 mask = (bank ? 0xF0 : 0x0F);
  137. u8 val = 0;
  138. if ((mode == ADC_MODE_ULP1) || (mode == ADC_MODE_ULP2))
  139. val = (bank ? 0x60 : 0x06);
  140. else
  141. val = 0x00;
  142. snd_soc_component_update_bits(component,
  143. WCD938X_DIGITAL_SWR_TX_CLK_RATE,
  144. mask, val);
  145. return 0;
  146. }
  147. static int wcd938x_init_reg(struct snd_soc_component *component)
  148. {
  149. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x0E, 0x0E);
  150. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x80, 0x80);
  151. /* 1 msec delay as per HW requirement */
  152. usleep_range(1000, 1010);
  153. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x40, 0x40);
  154. /* 1 msec delay as per HW requirement */
  155. usleep_range(1000, 1010);
  156. snd_soc_component_update_bits(component, WCD938X_LDORXTX_CONFIG,
  157. 0x10, 0x00);
  158. snd_soc_component_update_bits(component, WCD938X_BIAS_VBG_FINE_ADJ,
  159. 0xF0, 0x80);
  160. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x80, 0x80);
  161. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x40);
  162. /* 10 msec delay as per HW requirement */
  163. usleep_range(10000, 10010);
  164. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x00);
  165. snd_soc_component_update_bits(component,
  166. WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL,
  167. 0xF0, 0x00);
  168. snd_soc_component_update_bits(component,
  169. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW,
  170. 0x1F, 0x15);
  171. snd_soc_component_update_bits(component,
  172. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW,
  173. 0x1F, 0x15);
  174. snd_soc_component_update_bits(component, WCD938X_HPH_REFBUFF_UHQA_CTL,
  175. 0xC0, 0x80);
  176. snd_soc_component_update_bits(component, WCD938X_DIGITAL_CDC_DMIC_CTL,
  177. 0x02, 0x02);
  178. snd_soc_component_update_bits(component,
  179. WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP,
  180. 0xFF, 0x14);
  181. snd_soc_component_update_bits(component,
  182. WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP,
  183. 0x1F, 0x08);
  184. snd_soc_component_update_bits(component,
  185. WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0xFF, 0x55);
  186. snd_soc_component_update_bits(component,
  187. WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0xFF, 0x44);
  188. snd_soc_component_update_bits(component,
  189. WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0xFF, 0x11);
  190. snd_soc_component_update_bits(component,
  191. WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0xFF, 0x00);
  192. snd_soc_component_update_bits(component,
  193. WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0xFF, 0x00);
  194. snd_soc_component_update_bits(component,
  195. WCD938X_MICB1_TEST_CTL_1, 0xE0, 0xE0);
  196. snd_soc_component_update_bits(component,
  197. WCD938X_MICB2_TEST_CTL_1, 0xE0, 0xE0);
  198. snd_soc_component_update_bits(component,
  199. WCD938X_MICB3_TEST_CTL_1, 0xE0, 0xE0);
  200. snd_soc_component_update_bits(component,
  201. WCD938X_MICB4_TEST_CTL_1, 0xE0, 0xE0);
  202. snd_soc_component_update_bits(component,
  203. WCD938X_TX_3_4_TEST_BLK_EN2, 0x01, 0x00);
  204. return 0;
  205. }
  206. static int wcd938x_set_port_params(struct snd_soc_component *component,
  207. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  208. u8 *ch_mask, u32 *ch_rate,
  209. u8 *port_type, u8 path)
  210. {
  211. int i, j;
  212. u8 num_ports = 0;
  213. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  214. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  215. switch (path) {
  216. case CODEC_RX:
  217. map = &wcd938x->rx_port_mapping;
  218. num_ports = wcd938x->num_rx_ports;
  219. break;
  220. case CODEC_TX:
  221. map = &wcd938x->tx_port_mapping;
  222. num_ports = wcd938x->num_tx_ports;
  223. break;
  224. default:
  225. dev_err(component->dev, "%s Invalid path selected %u\n",
  226. __func__, path);
  227. return -EINVAL;
  228. }
  229. for (i = 0; i <= num_ports; i++) {
  230. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  231. if ((*map)[i][j].slave_port_type == slv_prt_type)
  232. goto found;
  233. }
  234. }
  235. found:
  236. if (i > num_ports || j == MAX_CH_PER_PORT) {
  237. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  238. __func__, slv_prt_type);
  239. return -EINVAL;
  240. }
  241. *port_id = i;
  242. *num_ch = (*map)[i][j].num_ch;
  243. *ch_mask = (*map)[i][j].ch_mask;
  244. *ch_rate = (*map)[i][j].ch_rate;
  245. *port_type = (*map)[i][j].master_port_type;
  246. return 0;
  247. }
  248. static int wcd938x_parse_port_mapping(struct device *dev,
  249. char *prop, u8 path)
  250. {
  251. u32 *dt_array, map_size, map_length;
  252. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  253. u32 slave_port_type, master_port_type;
  254. u32 i, ch_iter = 0;
  255. int ret = 0;
  256. u8 *num_ports = NULL;
  257. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  258. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  259. switch (path) {
  260. case CODEC_RX:
  261. map = &wcd938x->rx_port_mapping;
  262. num_ports = &wcd938x->num_rx_ports;
  263. break;
  264. case CODEC_TX:
  265. map = &wcd938x->tx_port_mapping;
  266. num_ports = &wcd938x->num_tx_ports;
  267. break;
  268. default:
  269. dev_err(dev, "%s Invalid path selected %u\n",
  270. __func__, path);
  271. return -EINVAL;
  272. }
  273. if (!of_find_property(dev->of_node, prop,
  274. &map_size)) {
  275. dev_err(dev, "missing port mapping prop %s\n", prop);
  276. ret = -EINVAL;
  277. goto err_port_map;
  278. }
  279. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  280. dt_array = kzalloc(map_size, GFP_KERNEL);
  281. if (!dt_array) {
  282. ret = -ENOMEM;
  283. goto err_alloc;
  284. }
  285. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  286. NUM_SWRS_DT_PARAMS * map_length);
  287. if (ret) {
  288. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  289. __func__, prop);
  290. goto err_pdata_fail;
  291. }
  292. for (i = 0; i < map_length; i++) {
  293. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  294. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  295. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  296. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  297. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  298. if (port_num != old_port_num)
  299. ch_iter = 0;
  300. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  301. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  302. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  303. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  304. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  305. old_port_num = port_num;
  306. }
  307. *num_ports = port_num;
  308. kfree(dt_array);
  309. return 0;
  310. err_pdata_fail:
  311. kfree(dt_array);
  312. err_alloc:
  313. err_port_map:
  314. return ret;
  315. }
  316. static int wcd938x_tx_connect_port(struct snd_soc_component *component,
  317. u8 slv_port_type, u8 enable)
  318. {
  319. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  320. u8 port_id, num_ch, ch_mask;
  321. u8 ch_type = 0;
  322. u32 ch_rate;
  323. int slave_ch_idx;
  324. u8 num_port = 1;
  325. int ret = 0;
  326. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  327. &num_ch, &ch_mask, &ch_rate,
  328. &ch_type, CODEC_TX);
  329. if (ret)
  330. return ret;
  331. slave_ch_idx = wcd938x_slave_get_slave_ch_val(slv_port_type);
  332. if (slave_ch_idx != -EINVAL)
  333. ch_type = wcd938x->tx_master_ch_map[slave_ch_idx];
  334. dev_dbg(component->dev, "%s slv_ch_idx: %d, mstr_ch_type: %d\n",
  335. __func__, slave_ch_idx, ch_type);
  336. if (enable)
  337. ret = swr_connect_port(wcd938x->tx_swr_dev, &port_id,
  338. num_port, &ch_mask, &ch_rate,
  339. &num_ch, &ch_type);
  340. else
  341. ret = swr_disconnect_port(wcd938x->tx_swr_dev, &port_id,
  342. num_port, &ch_mask, &ch_type);
  343. return ret;
  344. }
  345. static int wcd938x_rx_connect_port(struct snd_soc_component *component,
  346. u8 slv_port_type, u8 enable)
  347. {
  348. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  349. u8 port_id, num_ch, ch_mask, port_type;
  350. u32 ch_rate;
  351. u8 num_port = 1;
  352. int ret = 0;
  353. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  354. &num_ch, &ch_mask, &ch_rate,
  355. &port_type, CODEC_RX);
  356. if (ret)
  357. return ret;
  358. if (enable)
  359. ret = swr_connect_port(wcd938x->rx_swr_dev, &port_id,
  360. num_port, &ch_mask, &ch_rate,
  361. &num_ch, &port_type);
  362. else
  363. ret = swr_disconnect_port(wcd938x->rx_swr_dev, &port_id,
  364. num_port, &ch_mask, &port_type);
  365. return ret;
  366. }
  367. static int wcd938x_rx_clk_enable(struct snd_soc_component *component)
  368. {
  369. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  370. if (wcd938x->rx_clk_cnt == 0) {
  371. snd_soc_component_update_bits(component,
  372. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
  373. snd_soc_component_update_bits(component,
  374. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x01);
  375. snd_soc_component_update_bits(component,
  376. WCD938X_DIGITAL_CDC_RX0_CTL, 0x40, 0x00);
  377. snd_soc_component_update_bits(component,
  378. WCD938X_DIGITAL_CDC_RX1_CTL, 0x40, 0x00);
  379. snd_soc_component_update_bits(component,
  380. WCD938X_DIGITAL_CDC_RX2_CTL, 0x40, 0x00);
  381. snd_soc_component_update_bits(component,
  382. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
  383. snd_soc_component_update_bits(component,
  384. WCD938X_AUX_AUXPA, 0x10, 0x10);
  385. }
  386. wcd938x->rx_clk_cnt++;
  387. return 0;
  388. }
  389. static int wcd938x_rx_clk_disable(struct snd_soc_component *component)
  390. {
  391. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  392. wcd938x->rx_clk_cnt--;
  393. if (wcd938x->rx_clk_cnt == 0) {
  394. snd_soc_component_update_bits(component,
  395. WCD938X_ANA_RX_SUPPLIES, 0x40, 0x00);
  396. snd_soc_component_update_bits(component,
  397. WCD938X_ANA_RX_SUPPLIES, 0x80, 0x00);
  398. snd_soc_component_update_bits(component,
  399. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x00);
  400. snd_soc_component_update_bits(component,
  401. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x00);
  402. snd_soc_component_update_bits(component,
  403. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x00);
  404. }
  405. return 0;
  406. }
  407. /*
  408. * wcd938x_soc_get_mbhc: get wcd938x_mbhc handle of corresponding component
  409. * @component: handle to snd_soc_component *
  410. *
  411. * return wcd938x_mbhc handle or error code in case of failure
  412. */
  413. struct wcd938x_mbhc *wcd938x_soc_get_mbhc(struct snd_soc_component *component)
  414. {
  415. struct wcd938x_priv *wcd938x;
  416. if (!component) {
  417. pr_err("%s: Invalid params, NULL component\n", __func__);
  418. return NULL;
  419. }
  420. wcd938x = snd_soc_component_get_drvdata(component);
  421. if (!wcd938x) {
  422. pr_err("%s: wcd938x is NULL\n", __func__);
  423. return NULL;
  424. }
  425. return wcd938x->mbhc;
  426. }
  427. EXPORT_SYMBOL(wcd938x_soc_get_mbhc);
  428. static int wcd938x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  429. struct snd_kcontrol *kcontrol,
  430. int event)
  431. {
  432. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  433. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  434. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  435. w->name, event);
  436. switch (event) {
  437. case SND_SOC_DAPM_PRE_PMU:
  438. wcd938x_rx_clk_enable(component);
  439. snd_soc_component_update_bits(component,
  440. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  441. snd_soc_component_update_bits(component,
  442. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  443. snd_soc_component_update_bits(component,
  444. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  445. break;
  446. case SND_SOC_DAPM_POST_PMU:
  447. snd_soc_component_update_bits(component,
  448. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x0F, 0x02);
  449. if (wcd938x->comp1_enable) {
  450. snd_soc_component_update_bits(component,
  451. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x02);
  452. /* 5msec compander delay as per HW requirement */
  453. if (!wcd938x->comp2_enable ||
  454. (snd_soc_component_read32(component,
  455. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x01))
  456. usleep_range(5000, 5010);
  457. snd_soc_component_update_bits(component,
  458. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  459. } else {
  460. snd_soc_component_update_bits(component,
  461. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  462. 0x02, 0x00);
  463. snd_soc_component_update_bits(component,
  464. WCD938X_HPH_L_EN, 0x20, 0x20);
  465. }
  466. break;
  467. case SND_SOC_DAPM_POST_PMD:
  468. snd_soc_component_update_bits(component,
  469. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  470. 0x0F, 0x01);
  471. break;
  472. }
  473. return 0;
  474. }
  475. static int wcd938x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  476. struct snd_kcontrol *kcontrol,
  477. int event)
  478. {
  479. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  480. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  481. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  482. w->name, event);
  483. switch (event) {
  484. case SND_SOC_DAPM_PRE_PMU:
  485. wcd938x_rx_clk_enable(component);
  486. snd_soc_component_update_bits(component,
  487. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
  488. snd_soc_component_update_bits(component,
  489. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x08, 0x08);
  490. snd_soc_component_update_bits(component,
  491. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  492. break;
  493. case SND_SOC_DAPM_POST_PMU:
  494. snd_soc_component_update_bits(component,
  495. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x0F, 0x02);
  496. if (wcd938x->comp2_enable) {
  497. snd_soc_component_update_bits(component,
  498. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x01, 0x01);
  499. /* 5msec compander delay as per HW requirement */
  500. if (!wcd938x->comp1_enable ||
  501. (snd_soc_component_read32(component,
  502. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x02))
  503. usleep_range(5000, 5010);
  504. snd_soc_component_update_bits(component,
  505. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  506. } else {
  507. snd_soc_component_update_bits(component,
  508. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  509. 0x01, 0x00);
  510. snd_soc_component_update_bits(component,
  511. WCD938X_HPH_R_EN, 0x20, 0x20);
  512. }
  513. break;
  514. case SND_SOC_DAPM_POST_PMD:
  515. snd_soc_component_update_bits(component,
  516. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  517. 0x0F, 0x01);
  518. break;
  519. }
  520. return 0;
  521. }
  522. static int wcd938x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  523. struct snd_kcontrol *kcontrol,
  524. int event)
  525. {
  526. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  527. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  528. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  529. w->name, event);
  530. switch (event) {
  531. case SND_SOC_DAPM_PRE_PMU:
  532. wcd938x_rx_clk_enable(component);
  533. wcd938x->ear_rx_path =
  534. snd_soc_component_read32(
  535. component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
  536. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  537. snd_soc_component_update_bits(component,
  538. WCD938X_EAR_EAR_DAC_CON, 0x80, 0x00);
  539. snd_soc_component_update_bits(component,
  540. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x01);
  541. snd_soc_component_update_bits(component,
  542. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x04);
  543. snd_soc_component_update_bits(component,
  544. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  545. } else {
  546. snd_soc_component_update_bits(component,
  547. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  548. snd_soc_component_update_bits(component,
  549. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  550. snd_soc_component_update_bits(component,
  551. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x02);
  552. }
  553. /* 5 msec delay as per HW requirement */
  554. usleep_range(5000, 5010);
  555. if (wcd938x->flyback_cur_det_disable == 0)
  556. snd_soc_component_update_bits(component,
  557. WCD938X_FLYBACK_EN,
  558. 0x04, 0x00);
  559. wcd938x->flyback_cur_det_disable++;
  560. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  561. WCD_CLSH_EVENT_PRE_DAC,
  562. WCD_CLSH_STATE_EAR,
  563. wcd938x->hph_mode);
  564. break;
  565. case SND_SOC_DAPM_POST_PMD:
  566. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  567. snd_soc_component_update_bits(component,
  568. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x00);
  569. }
  570. snd_soc_component_update_bits(component,
  571. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  572. snd_soc_component_update_bits(component,
  573. WCD938X_EAR_EAR_DAC_CON, 0x80, 0x80);
  574. break;
  575. };
  576. return 0;
  577. }
  578. static int wcd938x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  579. struct snd_kcontrol *kcontrol,
  580. int event)
  581. {
  582. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  583. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  584. int ret = 0;
  585. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  586. w->name, event);
  587. switch (event) {
  588. case SND_SOC_DAPM_PRE_PMU:
  589. wcd938x_rx_clk_enable(component);
  590. snd_soc_component_update_bits(component,
  591. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x04);
  592. snd_soc_component_update_bits(component,
  593. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x04);
  594. snd_soc_component_update_bits(component,
  595. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x01);
  596. if (wcd938x->flyback_cur_det_disable == 0)
  597. snd_soc_component_update_bits(component,
  598. WCD938X_FLYBACK_EN,
  599. 0x04, 0x00);
  600. wcd938x->flyback_cur_det_disable++;
  601. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  602. WCD_CLSH_EVENT_PRE_DAC,
  603. WCD_CLSH_STATE_AUX,
  604. wcd938x->hph_mode);
  605. break;
  606. case SND_SOC_DAPM_POST_PMD:
  607. snd_soc_component_update_bits(component,
  608. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x00);
  609. break;
  610. };
  611. return ret;
  612. }
  613. static int wcd938x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  614. struct snd_kcontrol *kcontrol,
  615. int event)
  616. {
  617. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  618. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  619. int ret = 0;
  620. int hph_mode = wcd938x->hph_mode;
  621. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  622. w->name, event);
  623. switch (event) {
  624. case SND_SOC_DAPM_PRE_PMU:
  625. if (wcd938x->ldoh)
  626. snd_soc_component_update_bits(component,
  627. WCD938X_LDOH_MODE,
  628. 0x80, 0x80);
  629. if (wcd938x->update_wcd_event)
  630. wcd938x->update_wcd_event(wcd938x->handle,
  631. WCD_BOLERO_EVT_RX_MUTE,
  632. (WCD_RX2 << 0x10 | 0x1));
  633. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  634. wcd938x->rx_swr_dev->dev_num,
  635. true);
  636. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  637. WCD_CLSH_EVENT_PRE_DAC,
  638. WCD_CLSH_STATE_HPHR,
  639. hph_mode);
  640. wcd_clsh_set_hph_mode(component, CLS_H_HIFI);
  641. if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
  642. hph_mode == CLS_H_ULP) {
  643. snd_soc_component_update_bits(component,
  644. WCD938X_HPH_REFBUFF_LP_CTL, 0x01, 0x01);
  645. }
  646. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  647. 0x10, 0x10);
  648. wcd_clsh_set_hph_mode(component, hph_mode);
  649. /* 100 usec delay as per HW requirement */
  650. usleep_range(100, 110);
  651. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  652. snd_soc_component_update_bits(component,
  653. WCD938X_DIGITAL_PDM_WD_CTL1, 0x17, 0x13);
  654. break;
  655. case SND_SOC_DAPM_POST_PMU:
  656. /*
  657. * 7ms sleep is required if compander is enabled as per
  658. * HW requirement. If compander is disabled, then
  659. * 20ms delay is required.
  660. */
  661. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  662. if (!wcd938x->comp2_enable)
  663. usleep_range(20000, 20100);
  664. else
  665. usleep_range(7000, 7100);
  666. if (hph_mode == CLS_H_LP ||
  667. hph_mode == CLS_H_LOHIFI ||
  668. hph_mode == CLS_H_ULP)
  669. snd_soc_component_update_bits(component,
  670. WCD938X_HPH_REFBUFF_LP_CTL, 0x01,
  671. 0x00);
  672. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  673. }
  674. snd_soc_component_update_bits(component,
  675. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  676. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  677. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  678. snd_soc_component_update_bits(component,
  679. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  680. if (wcd938x->update_wcd_event)
  681. wcd938x->update_wcd_event(wcd938x->handle,
  682. WCD_BOLERO_EVT_RX_MUTE,
  683. (WCD_RX2 << 0x10));
  684. wcd_enable_irq(&wcd938x->irq_info,
  685. WCD938X_IRQ_HPHR_PDM_WD_INT);
  686. break;
  687. case SND_SOC_DAPM_PRE_PMD:
  688. if (wcd938x->update_wcd_event)
  689. wcd938x->update_wcd_event(wcd938x->handle,
  690. WCD_BOLERO_EVT_RX_MUTE,
  691. (WCD_RX2 << 0x10 | 0x1));
  692. wcd_disable_irq(&wcd938x->irq_info,
  693. WCD938X_IRQ_HPHR_PDM_WD_INT);
  694. if (wcd938x->update_wcd_event && wcd938x->comp2_enable)
  695. wcd938x->update_wcd_event(wcd938x->handle,
  696. WCD_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  697. (WCD_RX2 << 0x10));
  698. /*
  699. * 7ms sleep is required if compander is enabled as per
  700. * HW requirement. If compander is disabled, then
  701. * 20ms delay is required.
  702. */
  703. if (!wcd938x->comp2_enable)
  704. usleep_range(20000, 20100);
  705. else
  706. usleep_range(7000, 7100);
  707. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  708. 0x40, 0x00);
  709. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  710. WCD_EVENT_PRE_HPHR_PA_OFF,
  711. &wcd938x->mbhc->wcd_mbhc);
  712. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  713. break;
  714. case SND_SOC_DAPM_POST_PMD:
  715. /*
  716. * 7ms sleep is required if compander is enabled as per
  717. * HW requirement. If compander is disabled, then
  718. * 20ms delay is required.
  719. */
  720. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  721. if (!wcd938x->comp2_enable)
  722. usleep_range(20000, 20100);
  723. else
  724. usleep_range(7000, 7100);
  725. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  726. }
  727. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  728. WCD_EVENT_POST_HPHR_PA_OFF,
  729. &wcd938x->mbhc->wcd_mbhc);
  730. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  731. 0x10, 0x00);
  732. snd_soc_component_update_bits(component,
  733. WCD938X_DIGITAL_PDM_WD_CTL1, 0x17, 0x00);
  734. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  735. WCD_CLSH_EVENT_POST_PA,
  736. WCD_CLSH_STATE_HPHR,
  737. hph_mode);
  738. if (wcd938x->ldoh)
  739. snd_soc_component_update_bits(component,
  740. WCD938X_LDOH_MODE,
  741. 0x80, 0x00);
  742. break;
  743. };
  744. return ret;
  745. }
  746. static int wcd938x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  747. struct snd_kcontrol *kcontrol,
  748. int event)
  749. {
  750. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  751. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  752. int ret = 0;
  753. int hph_mode = wcd938x->hph_mode;
  754. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  755. w->name, event);
  756. switch (event) {
  757. case SND_SOC_DAPM_PRE_PMU:
  758. if (wcd938x->ldoh)
  759. snd_soc_component_update_bits(component,
  760. WCD938X_LDOH_MODE,
  761. 0x80, 0x80);
  762. if (wcd938x->update_wcd_event)
  763. wcd938x->update_wcd_event(wcd938x->handle,
  764. WCD_BOLERO_EVT_RX_MUTE,
  765. (WCD_RX1 << 0x10 | 0x01));
  766. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  767. wcd938x->rx_swr_dev->dev_num,
  768. true);
  769. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  770. WCD_CLSH_EVENT_PRE_DAC,
  771. WCD_CLSH_STATE_HPHL,
  772. hph_mode);
  773. wcd_clsh_set_hph_mode(component, CLS_H_HIFI);
  774. if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
  775. hph_mode == CLS_H_ULP) {
  776. snd_soc_component_update_bits(component,
  777. WCD938X_HPH_REFBUFF_LP_CTL, 0x01, 0x01);
  778. }
  779. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  780. 0x20, 0x20);
  781. wcd_clsh_set_hph_mode(component, hph_mode);
  782. /* 100 usec delay as per HW requirement */
  783. usleep_range(100, 110);
  784. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  785. snd_soc_component_update_bits(component,
  786. WCD938X_DIGITAL_PDM_WD_CTL0, 0x17, 0x13);
  787. break;
  788. case SND_SOC_DAPM_POST_PMU:
  789. /*
  790. * 7ms sleep is required if compander is enabled as per
  791. * HW requirement. If compander is disabled, then
  792. * 20ms delay is required.
  793. */
  794. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  795. if (!wcd938x->comp1_enable)
  796. usleep_range(20000, 20100);
  797. else
  798. usleep_range(7000, 7100);
  799. if (hph_mode == CLS_H_LP ||
  800. hph_mode == CLS_H_LOHIFI ||
  801. hph_mode == CLS_H_ULP)
  802. snd_soc_component_update_bits(component,
  803. WCD938X_HPH_REFBUFF_LP_CTL,
  804. 0x01, 0x00);
  805. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  806. }
  807. snd_soc_component_update_bits(component,
  808. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  809. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  810. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  811. snd_soc_component_update_bits(component,
  812. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  813. if (wcd938x->update_wcd_event)
  814. wcd938x->update_wcd_event(wcd938x->handle,
  815. WCD_BOLERO_EVT_RX_MUTE,
  816. (WCD_RX1 << 0x10));
  817. wcd_enable_irq(&wcd938x->irq_info,
  818. WCD938X_IRQ_HPHL_PDM_WD_INT);
  819. break;
  820. case SND_SOC_DAPM_PRE_PMD:
  821. if (wcd938x->update_wcd_event)
  822. wcd938x->update_wcd_event(wcd938x->handle,
  823. WCD_BOLERO_EVT_RX_MUTE,
  824. (WCD_RX1 << 0x10 | 0x1));
  825. wcd_disable_irq(&wcd938x->irq_info,
  826. WCD938X_IRQ_HPHL_PDM_WD_INT);
  827. if (wcd938x->update_wcd_event && wcd938x->comp1_enable)
  828. wcd938x->update_wcd_event(wcd938x->handle,
  829. WCD_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  830. (WCD_RX1 << 0x10));
  831. /*
  832. * 7ms sleep is required if compander is enabled as per
  833. * HW requirement. If compander is disabled, then
  834. * 20ms delay is required.
  835. */
  836. if (!wcd938x->comp1_enable)
  837. usleep_range(20000, 20100);
  838. else
  839. usleep_range(7000, 7100);
  840. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  841. 0x80, 0x00);
  842. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  843. WCD_EVENT_PRE_HPHL_PA_OFF,
  844. &wcd938x->mbhc->wcd_mbhc);
  845. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  846. break;
  847. case SND_SOC_DAPM_POST_PMD:
  848. /*
  849. * 7ms sleep is required if compander is enabled as per
  850. * HW requirement. If compander is disabled, then
  851. * 20ms delay is required.
  852. */
  853. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  854. if (!wcd938x->comp1_enable)
  855. usleep_range(21000, 21100);
  856. else
  857. usleep_range(7000, 7100);
  858. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  859. }
  860. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  861. WCD_EVENT_POST_HPHL_PA_OFF,
  862. &wcd938x->mbhc->wcd_mbhc);
  863. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  864. 0x20, 0x00);
  865. snd_soc_component_update_bits(component,
  866. WCD938X_DIGITAL_PDM_WD_CTL0, 0x17, 0x00);
  867. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  868. WCD_CLSH_EVENT_POST_PA,
  869. WCD_CLSH_STATE_HPHL,
  870. hph_mode);
  871. if (wcd938x->ldoh)
  872. snd_soc_component_update_bits(component,
  873. WCD938X_LDOH_MODE,
  874. 0x80, 0x00);
  875. break;
  876. };
  877. return ret;
  878. }
  879. static int wcd938x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  880. struct snd_kcontrol *kcontrol,
  881. int event)
  882. {
  883. struct snd_soc_component *component =
  884. snd_soc_dapm_to_component(w->dapm);
  885. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  886. int hph_mode = wcd938x->hph_mode;
  887. int ret = 0;
  888. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  889. w->name, event);
  890. switch (event) {
  891. case SND_SOC_DAPM_PRE_PMU:
  892. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  893. wcd938x->rx_swr_dev->dev_num,
  894. true);
  895. snd_soc_component_update_bits(component,
  896. WCD938X_DIGITAL_PDM_WD_CTL2, 0x05, 0x05);
  897. break;
  898. case SND_SOC_DAPM_POST_PMU:
  899. /* 1 msec delay as per HW requirement */
  900. usleep_range(1000, 1010);
  901. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  902. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  903. snd_soc_component_update_bits(component,
  904. WCD938X_ANA_RX_SUPPLIES,
  905. 0x02, 0x02);
  906. if (wcd938x->update_wcd_event)
  907. wcd938x->update_wcd_event(wcd938x->handle,
  908. WCD_BOLERO_EVT_RX_MUTE,
  909. (WCD_RX3 << 0x10));
  910. wcd_enable_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT);
  911. break;
  912. case SND_SOC_DAPM_PRE_PMD:
  913. wcd_disable_irq(&wcd938x->irq_info,
  914. WCD938X_IRQ_AUX_PDM_WD_INT);
  915. if (wcd938x->update_wcd_event)
  916. wcd938x->update_wcd_event(wcd938x->handle,
  917. WCD_BOLERO_EVT_RX_MUTE,
  918. (WCD_RX3 << 0x10 | 0x1));
  919. break;
  920. case SND_SOC_DAPM_POST_PMD:
  921. /* 1 msec delay as per HW requirement */
  922. usleep_range(1000, 1010);
  923. snd_soc_component_update_bits(component,
  924. WCD938X_DIGITAL_PDM_WD_CTL2, 0x05, 0x00);
  925. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  926. WCD_CLSH_EVENT_POST_PA,
  927. WCD_CLSH_STATE_AUX,
  928. hph_mode);
  929. wcd938x->flyback_cur_det_disable--;
  930. if (wcd938x->flyback_cur_det_disable == 0)
  931. snd_soc_component_update_bits(component,
  932. WCD938X_FLYBACK_EN,
  933. 0x04, 0x04);
  934. break;
  935. };
  936. return ret;
  937. }
  938. static int wcd938x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  939. struct snd_kcontrol *kcontrol,
  940. int event)
  941. {
  942. struct snd_soc_component *component =
  943. snd_soc_dapm_to_component(w->dapm);
  944. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  945. int hph_mode = wcd938x->hph_mode;
  946. int ret = 0;
  947. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  948. w->name, event);
  949. switch (event) {
  950. case SND_SOC_DAPM_PRE_PMU:
  951. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  952. wcd938x->rx_swr_dev->dev_num,
  953. true);
  954. /*
  955. * Enable watchdog interrupt for HPHL or AUX
  956. * depending on mux value
  957. */
  958. wcd938x->ear_rx_path =
  959. snd_soc_component_read32(
  960. component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
  961. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  962. snd_soc_component_update_bits(component,
  963. WCD938X_DIGITAL_PDM_WD_CTL2,
  964. 0x05, 0x05);
  965. else
  966. snd_soc_component_update_bits(component,
  967. WCD938X_DIGITAL_PDM_WD_CTL0,
  968. 0x17, 0x13);
  969. if (!wcd938x->comp1_enable)
  970. snd_soc_component_update_bits(component,
  971. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  972. break;
  973. case SND_SOC_DAPM_POST_PMU:
  974. /* 6 msec delay as per HW requirement */
  975. usleep_range(6000, 6010);
  976. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  977. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  978. snd_soc_component_update_bits(component,
  979. WCD938X_ANA_RX_SUPPLIES,
  980. 0x02, 0x02);
  981. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  982. if (wcd938x->update_wcd_event)
  983. wcd938x->update_wcd_event(wcd938x->handle,
  984. WCD_BOLERO_EVT_RX_MUTE,
  985. (WCD_RX3 << 0x10));
  986. wcd_enable_irq(&wcd938x->irq_info,
  987. WCD938X_IRQ_AUX_PDM_WD_INT);
  988. } else {
  989. if (wcd938x->update_wcd_event)
  990. wcd938x->update_wcd_event(wcd938x->handle,
  991. WCD_BOLERO_EVT_RX_MUTE,
  992. (WCD_RX1 << 0x10));
  993. wcd_enable_irq(&wcd938x->irq_info,
  994. WCD938X_IRQ_HPHL_PDM_WD_INT);
  995. }
  996. break;
  997. case SND_SOC_DAPM_PRE_PMD:
  998. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  999. wcd_disable_irq(&wcd938x->irq_info,
  1000. WCD938X_IRQ_AUX_PDM_WD_INT);
  1001. if (wcd938x->update_wcd_event)
  1002. wcd938x->update_wcd_event(wcd938x->handle,
  1003. WCD_BOLERO_EVT_RX_MUTE,
  1004. (WCD_RX3 << 0x10 | 0x1));
  1005. } else {
  1006. wcd_disable_irq(&wcd938x->irq_info,
  1007. WCD938X_IRQ_HPHL_PDM_WD_INT);
  1008. if (wcd938x->update_wcd_event)
  1009. wcd938x->update_wcd_event(wcd938x->handle,
  1010. WCD_BOLERO_EVT_RX_MUTE,
  1011. (WCD_RX1 << 0x10 | 0x1));
  1012. }
  1013. break;
  1014. case SND_SOC_DAPM_POST_PMD:
  1015. if (!wcd938x->comp1_enable)
  1016. snd_soc_component_update_bits(component,
  1017. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  1018. /* 7 msec delay as per HW requirement */
  1019. usleep_range(7000, 7010);
  1020. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  1021. snd_soc_component_update_bits(component,
  1022. WCD938X_DIGITAL_PDM_WD_CTL2,
  1023. 0x05, 0x00);
  1024. else
  1025. snd_soc_component_update_bits(component,
  1026. WCD938X_DIGITAL_PDM_WD_CTL0,
  1027. 0x17, 0x00);
  1028. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  1029. WCD_CLSH_EVENT_POST_PA,
  1030. WCD_CLSH_STATE_EAR,
  1031. hph_mode);
  1032. wcd938x->flyback_cur_det_disable--;
  1033. if (wcd938x->flyback_cur_det_disable == 0)
  1034. snd_soc_component_update_bits(component,
  1035. WCD938X_FLYBACK_EN,
  1036. 0x04, 0x04);
  1037. break;
  1038. };
  1039. return ret;
  1040. }
  1041. static int wcd938x_enable_clsh(struct snd_soc_dapm_widget *w,
  1042. struct snd_kcontrol *kcontrol,
  1043. int event)
  1044. {
  1045. struct snd_soc_component *component =
  1046. snd_soc_dapm_to_component(w->dapm);
  1047. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1048. int mode = wcd938x->hph_mode;
  1049. int ret = 0;
  1050. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1051. w->name, event);
  1052. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  1053. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  1054. wcd938x_rx_connect_port(component, CLSH,
  1055. SND_SOC_DAPM_EVENT_ON(event));
  1056. }
  1057. if (SND_SOC_DAPM_EVENT_OFF(event))
  1058. ret = swr_slvdev_datapath_control(
  1059. wcd938x->rx_swr_dev,
  1060. wcd938x->rx_swr_dev->dev_num,
  1061. false);
  1062. return ret;
  1063. }
  1064. static int wcd938x_enable_rx1(struct snd_soc_dapm_widget *w,
  1065. struct snd_kcontrol *kcontrol,
  1066. int event)
  1067. {
  1068. struct snd_soc_component *component =
  1069. snd_soc_dapm_to_component(w->dapm);
  1070. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1071. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1072. w->name, event);
  1073. switch (event) {
  1074. case SND_SOC_DAPM_PRE_PMU:
  1075. wcd938x_rx_connect_port(component, HPH_L, true);
  1076. if (wcd938x->comp1_enable)
  1077. wcd938x_rx_connect_port(component, COMP_L, true);
  1078. break;
  1079. case SND_SOC_DAPM_POST_PMD:
  1080. wcd938x_rx_connect_port(component, HPH_L, false);
  1081. if (wcd938x->comp1_enable)
  1082. wcd938x_rx_connect_port(component, COMP_L, false);
  1083. wcd938x_rx_clk_disable(component);
  1084. snd_soc_component_update_bits(component,
  1085. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  1086. 0x01, 0x00);
  1087. break;
  1088. };
  1089. return 0;
  1090. }
  1091. static int wcd938x_enable_rx2(struct snd_soc_dapm_widget *w,
  1092. struct snd_kcontrol *kcontrol, int event)
  1093. {
  1094. struct snd_soc_component *component =
  1095. snd_soc_dapm_to_component(w->dapm);
  1096. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1097. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1098. w->name, event);
  1099. switch (event) {
  1100. case SND_SOC_DAPM_PRE_PMU:
  1101. wcd938x_rx_connect_port(component, HPH_R, true);
  1102. if (wcd938x->comp2_enable)
  1103. wcd938x_rx_connect_port(component, COMP_R, true);
  1104. break;
  1105. case SND_SOC_DAPM_POST_PMD:
  1106. wcd938x_rx_connect_port(component, HPH_R, false);
  1107. if (wcd938x->comp2_enable)
  1108. wcd938x_rx_connect_port(component, COMP_R, false);
  1109. wcd938x_rx_clk_disable(component);
  1110. snd_soc_component_update_bits(component,
  1111. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  1112. 0x02, 0x00);
  1113. break;
  1114. };
  1115. return 0;
  1116. }
  1117. static int wcd938x_enable_rx3(struct snd_soc_dapm_widget *w,
  1118. struct snd_kcontrol *kcontrol,
  1119. int event)
  1120. {
  1121. struct snd_soc_component *component =
  1122. snd_soc_dapm_to_component(w->dapm);
  1123. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1124. w->name, event);
  1125. switch (event) {
  1126. case SND_SOC_DAPM_PRE_PMU:
  1127. wcd938x_rx_connect_port(component, LO, true);
  1128. break;
  1129. case SND_SOC_DAPM_POST_PMD:
  1130. wcd938x_rx_connect_port(component, LO, false);
  1131. /* 6 msec delay as per HW requirement */
  1132. usleep_range(6000, 6010);
  1133. wcd938x_rx_clk_disable(component);
  1134. snd_soc_component_update_bits(component,
  1135. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  1136. break;
  1137. }
  1138. return 0;
  1139. }
  1140. static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  1141. struct snd_kcontrol *kcontrol,
  1142. int event)
  1143. {
  1144. struct snd_soc_component *component =
  1145. snd_soc_dapm_to_component(w->dapm);
  1146. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1147. u16 dmic_clk_reg, dmic_clk_en_reg;
  1148. s32 *dmic_clk_cnt;
  1149. u8 dmic_ctl_shift = 0;
  1150. u8 dmic_clk_shift = 0;
  1151. u8 dmic_clk_mask = 0;
  1152. u16 dmic2_left_en = 0;
  1153. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1154. w->name, event);
  1155. switch (w->shift) {
  1156. case 0:
  1157. case 1:
  1158. dmic_clk_cnt = &(wcd938x->dmic_0_1_clk_cnt);
  1159. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
  1160. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC1_CTL;
  1161. dmic_clk_mask = 0x0F;
  1162. dmic_clk_shift = 0x00;
  1163. dmic_ctl_shift = 0x00;
  1164. break;
  1165. case 2:
  1166. dmic2_left_en = WCD938X_DIGITAL_CDC_DMIC2_CTL;
  1167. case 3:
  1168. dmic_clk_cnt = &(wcd938x->dmic_2_3_clk_cnt);
  1169. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
  1170. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC2_CTL;
  1171. dmic_clk_mask = 0xF0;
  1172. dmic_clk_shift = 0x04;
  1173. dmic_ctl_shift = 0x01;
  1174. break;
  1175. case 4:
  1176. case 5:
  1177. dmic_clk_cnt = &(wcd938x->dmic_4_5_clk_cnt);
  1178. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
  1179. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC3_CTL;
  1180. dmic_clk_mask = 0x0F;
  1181. dmic_clk_shift = 0x00;
  1182. dmic_ctl_shift = 0x02;
  1183. break;
  1184. case 6:
  1185. case 7:
  1186. dmic_clk_cnt = &(wcd938x->dmic_6_7_clk_cnt);
  1187. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
  1188. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC4_CTL;
  1189. dmic_clk_mask = 0xF0;
  1190. dmic_clk_shift = 0x04;
  1191. dmic_ctl_shift = 0x03;
  1192. break;
  1193. default:
  1194. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  1195. __func__);
  1196. return -EINVAL;
  1197. };
  1198. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  1199. __func__, event, (w->shift +1), *dmic_clk_cnt);
  1200. switch (event) {
  1201. case SND_SOC_DAPM_PRE_PMU:
  1202. snd_soc_component_update_bits(component,
  1203. WCD938X_DIGITAL_CDC_AMIC_CTL,
  1204. (0x01 << dmic_ctl_shift), 0x00);
  1205. /* 250us sleep as per HW requirement */
  1206. usleep_range(250, 260);
  1207. if (dmic2_left_en)
  1208. snd_soc_component_update_bits(component,
  1209. dmic2_left_en, 0x80, 0x80);
  1210. /* Setting DMIC clock rate to 2.4MHz */
  1211. snd_soc_component_update_bits(component,
  1212. dmic_clk_reg, dmic_clk_mask,
  1213. (0x03 << dmic_clk_shift));
  1214. snd_soc_component_update_bits(component,
  1215. dmic_clk_en_reg, 0x08, 0x08);
  1216. /* enable clock scaling */
  1217. snd_soc_component_update_bits(component,
  1218. WCD938X_DIGITAL_CDC_DMIC_CTL, 0x06, 0x06);
  1219. wcd938x_tx_connect_port(component, DMIC0 + (w->shift), true);
  1220. break;
  1221. case SND_SOC_DAPM_POST_PMD:
  1222. wcd938x_tx_connect_port(component, DMIC0 + (w->shift), false);
  1223. snd_soc_component_update_bits(component,
  1224. WCD938X_DIGITAL_CDC_AMIC_CTL,
  1225. (0x01 << dmic_ctl_shift),
  1226. (0x01 << dmic_ctl_shift));
  1227. if (dmic2_left_en)
  1228. snd_soc_component_update_bits(component,
  1229. dmic2_left_en, 0x80, 0x00);
  1230. snd_soc_component_update_bits(component,
  1231. dmic_clk_en_reg, 0x08, 0x00);
  1232. break;
  1233. };
  1234. return 0;
  1235. }
  1236. /*
  1237. * wcd938x_get_micb_vout_ctl_val: converts micbias from volts to register value
  1238. * @micb_mv: micbias in mv
  1239. *
  1240. * return register value converted
  1241. */
  1242. int wcd938x_get_micb_vout_ctl_val(u32 micb_mv)
  1243. {
  1244. /* min micbias voltage is 1V and maximum is 2.85V */
  1245. if (micb_mv < 1000 || micb_mv > 2850) {
  1246. pr_err("%s: unsupported micbias voltage\n", __func__);
  1247. return -EINVAL;
  1248. }
  1249. return (micb_mv - 1000) / 50;
  1250. }
  1251. EXPORT_SYMBOL(wcd938x_get_micb_vout_ctl_val);
  1252. /*
  1253. * wcd938x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  1254. * @component: handle to snd_soc_component *
  1255. * @req_volt: micbias voltage to be set
  1256. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  1257. *
  1258. * return 0 if adjustment is success or error code in case of failure
  1259. */
  1260. int wcd938x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  1261. int req_volt, int micb_num)
  1262. {
  1263. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1264. int cur_vout_ctl, req_vout_ctl;
  1265. int micb_reg, micb_val, micb_en;
  1266. int ret = 0;
  1267. switch (micb_num) {
  1268. case MIC_BIAS_1:
  1269. micb_reg = WCD938X_ANA_MICB1;
  1270. break;
  1271. case MIC_BIAS_2:
  1272. micb_reg = WCD938X_ANA_MICB2;
  1273. break;
  1274. case MIC_BIAS_3:
  1275. micb_reg = WCD938X_ANA_MICB3;
  1276. break;
  1277. case MIC_BIAS_4:
  1278. micb_reg = WCD938X_ANA_MICB4;
  1279. break;
  1280. default:
  1281. return -EINVAL;
  1282. }
  1283. mutex_lock(&wcd938x->micb_lock);
  1284. /*
  1285. * If requested micbias voltage is same as current micbias
  1286. * voltage, then just return. Otherwise, adjust voltage as
  1287. * per requested value. If micbias is already enabled, then
  1288. * to avoid slow micbias ramp-up or down enable pull-up
  1289. * momentarily, change the micbias value and then re-enable
  1290. * micbias.
  1291. */
  1292. micb_val = snd_soc_component_read32(component, micb_reg);
  1293. micb_en = (micb_val & 0xC0) >> 6;
  1294. cur_vout_ctl = micb_val & 0x3F;
  1295. req_vout_ctl = wcd938x_get_micb_vout_ctl_val(req_volt);
  1296. if (req_vout_ctl < 0) {
  1297. ret = -EINVAL;
  1298. goto exit;
  1299. }
  1300. if (cur_vout_ctl == req_vout_ctl) {
  1301. ret = 0;
  1302. goto exit;
  1303. }
  1304. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  1305. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  1306. req_volt, micb_en);
  1307. if (micb_en == 0x1)
  1308. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  1309. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  1310. if (micb_en == 0x1) {
  1311. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  1312. /*
  1313. * Add 2ms delay as per HW requirement after enabling
  1314. * micbias
  1315. */
  1316. usleep_range(2000, 2100);
  1317. }
  1318. exit:
  1319. mutex_unlock(&wcd938x->micb_lock);
  1320. return ret;
  1321. }
  1322. EXPORT_SYMBOL(wcd938x_mbhc_micb_adjust_voltage);
  1323. static int wcd938x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1324. struct snd_kcontrol *kcontrol,
  1325. int event)
  1326. {
  1327. struct snd_soc_component *component =
  1328. snd_soc_dapm_to_component(w->dapm);
  1329. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1330. int ret = 0;
  1331. int bank = 0;
  1332. int mode = 0;
  1333. bank = wcd938x_swr_slv_get_current_bank(wcd938x->tx_swr_dev,
  1334. wcd938x->tx_swr_dev->dev_num);
  1335. wcd938x_swr_slv_set_host_clk_div2(wcd938x->tx_swr_dev,
  1336. wcd938x->tx_swr_dev->dev_num, bank);
  1337. switch (event) {
  1338. case SND_SOC_DAPM_PRE_PMU:
  1339. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1340. wcd938x->tx_swr_dev->dev_num,
  1341. true);
  1342. if (test_bit(WCD_ADC1, &wcd938x->status_mask))
  1343. mode |= wcd938x->tx_mode[WCD_ADC1];
  1344. if (test_bit(WCD_ADC2, &wcd938x->status_mask))
  1345. mode |= wcd938x->tx_mode[WCD_ADC2];
  1346. if (test_bit(WCD_ADC3, &wcd938x->status_mask))
  1347. mode |= wcd938x->tx_mode[WCD_ADC3];
  1348. if (test_bit(WCD_ADC4, &wcd938x->status_mask))
  1349. mode |= wcd938x->tx_mode[WCD_ADC4];
  1350. wcd938x_set_swr_clk_rate(component, mode, bank);
  1351. break;
  1352. case SND_SOC_DAPM_POST_PMD:
  1353. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1354. wcd938x->tx_swr_dev->dev_num,
  1355. false);
  1356. wcd938x_set_swr_clk_rate(component, ADC_MODE_INVALID, bank);
  1357. break;
  1358. };
  1359. return ret;
  1360. }
  1361. static int wcd938x_get_adc_mode(int val)
  1362. {
  1363. int ret = 0;
  1364. switch (val) {
  1365. case ADC_MODE_INVALID:
  1366. ret = ADC_MODE_VAL_NORMAL;
  1367. break;
  1368. case ADC_MODE_HIFI:
  1369. ret = ADC_MODE_VAL_HIFI;
  1370. break;
  1371. case ADC_MODE_LO_HIF:
  1372. ret = ADC_MODE_VAL_LO_HIF;
  1373. break;
  1374. case ADC_MODE_NORMAL:
  1375. ret = ADC_MODE_VAL_NORMAL;
  1376. break;
  1377. case ADC_MODE_LP:
  1378. ret = ADC_MODE_VAL_LP;
  1379. break;
  1380. case ADC_MODE_ULP1:
  1381. ret = ADC_MODE_VAL_ULP1;
  1382. break;
  1383. case ADC_MODE_ULP2:
  1384. ret = ADC_MODE_VAL_ULP2;
  1385. break;
  1386. default:
  1387. ret = -EINVAL;
  1388. pr_err("%s: invalid ADC mode value %d\n", __func__, val);
  1389. break;
  1390. }
  1391. return ret;
  1392. }
  1393. static int wcd938x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  1394. struct snd_kcontrol *kcontrol,
  1395. int event){
  1396. struct snd_soc_component *component =
  1397. snd_soc_dapm_to_component(w->dapm);
  1398. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1399. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1400. w->name, event);
  1401. switch (event) {
  1402. case SND_SOC_DAPM_PRE_PMU:
  1403. snd_soc_component_update_bits(component,
  1404. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x08);
  1405. snd_soc_component_update_bits(component,
  1406. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1407. set_bit(w->shift, &wcd938x->status_mask);
  1408. /* Enable BCS for Headset mic */
  1409. if (w->shift == 1 && !(snd_soc_component_read32(component,
  1410. WCD938X_TX_NEW_AMIC_MUX_CFG) & 0x80)) {
  1411. wcd938x_tx_connect_port(component, MBHC, true);
  1412. set_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask);
  1413. }
  1414. wcd938x_tx_connect_port(component, ADC1 + (w->shift), true);
  1415. break;
  1416. case SND_SOC_DAPM_POST_PMD:
  1417. wcd938x_tx_connect_port(component, ADC1 + (w->shift), false);
  1418. if (w->shift == 1 &&
  1419. test_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask)) {
  1420. wcd938x_tx_connect_port(component, MBHC, false);
  1421. clear_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask);
  1422. }
  1423. snd_soc_component_update_bits(component,
  1424. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x00);
  1425. clear_bit(w->shift, &wcd938x->status_mask);
  1426. break;
  1427. };
  1428. return 0;
  1429. }
  1430. void wcd938x_disable_bcs_before_slow_insert(struct snd_soc_component *component,
  1431. bool bcs_disable)
  1432. {
  1433. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1434. if (wcd938x->update_wcd_event) {
  1435. if (bcs_disable)
  1436. wcd938x->update_wcd_event(wcd938x->handle,
  1437. WCD_BOLERO_EVT_BCS_CLK_OFF, 0);
  1438. else
  1439. wcd938x->update_wcd_event(wcd938x->handle,
  1440. WCD_BOLERO_EVT_BCS_CLK_OFF, 1);
  1441. }
  1442. }
  1443. int wcd938x_tx_channel_config(struct snd_soc_component *component,
  1444. int channel, int mode)
  1445. {
  1446. int reg = WCD938X_ANA_TX_CH2, mask = 0, val = 0;
  1447. int ret = 0;
  1448. switch (channel) {
  1449. case 0:
  1450. reg = WCD938X_ANA_TX_CH2;
  1451. mask = 0x40;
  1452. break;
  1453. case 1:
  1454. reg = WCD938X_ANA_TX_CH2;
  1455. mask = 0x20;
  1456. break;
  1457. case 2:
  1458. reg = WCD938X_ANA_TX_CH4;
  1459. mask = 0x40;
  1460. break;
  1461. case 3:
  1462. reg = WCD938X_ANA_TX_CH4;
  1463. mask = 0x20;
  1464. break;
  1465. default:
  1466. pr_err("%s: Invalid channel num %d\n", __func__, channel);
  1467. ret = -EINVAL;
  1468. break;
  1469. }
  1470. if (!mode)
  1471. val = 0x00;
  1472. else
  1473. val = mask;
  1474. if (!ret)
  1475. snd_soc_component_update_bits(component, reg, mask, val);
  1476. return ret;
  1477. }
  1478. static int wcd938x_enable_req(struct snd_soc_dapm_widget *w,
  1479. struct snd_kcontrol *kcontrol, int event)
  1480. {
  1481. struct snd_soc_component *component =
  1482. snd_soc_dapm_to_component(w->dapm);
  1483. int mode;
  1484. int ret = 0;
  1485. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1486. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1487. w->name, event);
  1488. switch (event) {
  1489. case SND_SOC_DAPM_PRE_PMU:
  1490. snd_soc_component_update_bits(component,
  1491. WCD938X_DIGITAL_CDC_REQ_CTL, 0x02, 0x02);
  1492. snd_soc_component_update_bits(component,
  1493. WCD938X_DIGITAL_CDC_REQ_CTL, 0x01, 0x00);
  1494. ret = wcd938x_tx_channel_config(component, w->shift, 1);
  1495. mode = wcd938x_get_adc_mode(wcd938x->tx_mode[w->shift]);
  1496. if (mode < 0) {
  1497. dev_info(component->dev,
  1498. "%s: invalid mode, setting to normal mode\n",
  1499. __func__);
  1500. mode = ADC_MODE_VAL_NORMAL;
  1501. }
  1502. switch (w->shift) {
  1503. case 0:
  1504. snd_soc_component_update_bits(component,
  1505. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x0F,
  1506. mode);
  1507. snd_soc_component_update_bits(component,
  1508. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x10);
  1509. break;
  1510. case 1:
  1511. snd_soc_component_update_bits(component,
  1512. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0xF0,
  1513. mode << 4);
  1514. snd_soc_component_update_bits(component,
  1515. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x20, 0x20);
  1516. break;
  1517. case 2:
  1518. snd_soc_component_update_bits(component,
  1519. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x0F,
  1520. mode);
  1521. snd_soc_component_update_bits(component,
  1522. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x40, 0x40);
  1523. break;
  1524. case 3:
  1525. snd_soc_component_update_bits(component,
  1526. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0xF0,
  1527. mode << 4);
  1528. snd_soc_component_update_bits(component,
  1529. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1530. break;
  1531. default:
  1532. break;
  1533. }
  1534. ret |= wcd938x_tx_channel_config(component, w->shift, 0);
  1535. break;
  1536. case SND_SOC_DAPM_POST_PMD:
  1537. switch (w->shift) {
  1538. case 0:
  1539. snd_soc_component_update_bits(component,
  1540. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x0F,
  1541. 0x00);
  1542. snd_soc_component_update_bits(component,
  1543. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x00);
  1544. break;
  1545. case 1:
  1546. snd_soc_component_update_bits(component,
  1547. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0xF0,
  1548. 0x00);
  1549. snd_soc_component_update_bits(component,
  1550. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x20, 0x00);
  1551. break;
  1552. case 2:
  1553. snd_soc_component_update_bits(component,
  1554. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x0F,
  1555. 0x00);
  1556. snd_soc_component_update_bits(component,
  1557. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x40, 0x00);
  1558. break;
  1559. case 3:
  1560. snd_soc_component_update_bits(component,
  1561. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0xF0,
  1562. 0x00);
  1563. snd_soc_component_update_bits(component,
  1564. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00);
  1565. break;
  1566. default:
  1567. break;
  1568. }
  1569. snd_soc_component_update_bits(component,
  1570. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
  1571. break;
  1572. };
  1573. return ret;
  1574. }
  1575. int wcd938x_micbias_control(struct snd_soc_component *component,
  1576. int micb_num, int req, bool is_dapm)
  1577. {
  1578. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1579. int micb_index = micb_num - 1;
  1580. u16 micb_reg;
  1581. int pre_off_event = 0, post_off_event = 0;
  1582. int post_on_event = 0, post_dapm_off = 0;
  1583. int post_dapm_on = 0;
  1584. int ret = 0;
  1585. if ((micb_index < 0) || (micb_index > WCD938X_MAX_MICBIAS - 1)) {
  1586. dev_err(component->dev,
  1587. "%s: Invalid micbias index, micb_ind:%d\n",
  1588. __func__, micb_index);
  1589. return -EINVAL;
  1590. }
  1591. if (NULL == wcd938x) {
  1592. dev_err(component->dev,
  1593. "%s: wcd938x private data is NULL\n", __func__);
  1594. return -EINVAL;
  1595. }
  1596. switch (micb_num) {
  1597. case MIC_BIAS_1:
  1598. micb_reg = WCD938X_ANA_MICB1;
  1599. break;
  1600. case MIC_BIAS_2:
  1601. micb_reg = WCD938X_ANA_MICB2;
  1602. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1603. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1604. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1605. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1606. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1607. break;
  1608. case MIC_BIAS_3:
  1609. micb_reg = WCD938X_ANA_MICB3;
  1610. break;
  1611. case MIC_BIAS_4:
  1612. micb_reg = WCD938X_ANA_MICB4;
  1613. break;
  1614. default:
  1615. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1616. __func__, micb_num);
  1617. return -EINVAL;
  1618. };
  1619. mutex_lock(&wcd938x->micb_lock);
  1620. switch (req) {
  1621. case MICB_PULLUP_ENABLE:
  1622. if (!wcd938x->dev_up) {
  1623. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1624. __func__, req);
  1625. ret = -ENODEV;
  1626. goto done;
  1627. }
  1628. wcd938x->pullup_ref[micb_index]++;
  1629. if ((wcd938x->pullup_ref[micb_index] == 1) &&
  1630. (wcd938x->micb_ref[micb_index] == 0))
  1631. snd_soc_component_update_bits(component, micb_reg,
  1632. 0xC0, 0x80);
  1633. break;
  1634. case MICB_PULLUP_DISABLE:
  1635. if (wcd938x->pullup_ref[micb_index] > 0)
  1636. wcd938x->pullup_ref[micb_index]--;
  1637. if (!wcd938x->dev_up) {
  1638. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1639. __func__, req);
  1640. ret = -ENODEV;
  1641. goto done;
  1642. }
  1643. if ((wcd938x->pullup_ref[micb_index] == 0) &&
  1644. (wcd938x->micb_ref[micb_index] == 0))
  1645. snd_soc_component_update_bits(component, micb_reg,
  1646. 0xC0, 0x00);
  1647. break;
  1648. case MICB_ENABLE:
  1649. if (!wcd938x->dev_up) {
  1650. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1651. __func__, req);
  1652. ret = -ENODEV;
  1653. goto done;
  1654. }
  1655. wcd938x->micb_ref[micb_index]++;
  1656. if (wcd938x->micb_ref[micb_index] == 1) {
  1657. snd_soc_component_update_bits(component,
  1658. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xE0, 0xE0);
  1659. snd_soc_component_update_bits(component,
  1660. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1661. snd_soc_component_update_bits(component,
  1662. WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x01, 0x01);
  1663. snd_soc_component_update_bits(component,
  1664. WCD938X_MICB1_TEST_CTL_2, 0x01, 0x01);
  1665. snd_soc_component_update_bits(component,
  1666. WCD938X_MICB2_TEST_CTL_2, 0x01, 0x01);
  1667. snd_soc_component_update_bits(component,
  1668. WCD938X_MICB3_TEST_CTL_2, 0x01, 0x01);
  1669. snd_soc_component_update_bits(component,
  1670. WCD938X_MICB4_TEST_CTL_2, 0x01, 0x01);
  1671. snd_soc_component_update_bits(component,
  1672. micb_reg, 0xC0, 0x40);
  1673. if (post_on_event)
  1674. blocking_notifier_call_chain(
  1675. &wcd938x->mbhc->notifier,
  1676. post_on_event,
  1677. &wcd938x->mbhc->wcd_mbhc);
  1678. }
  1679. if (is_dapm && post_dapm_on && wcd938x->mbhc)
  1680. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1681. post_dapm_on,
  1682. &wcd938x->mbhc->wcd_mbhc);
  1683. break;
  1684. case MICB_DISABLE:
  1685. if (wcd938x->micb_ref[micb_index] > 0)
  1686. wcd938x->micb_ref[micb_index]--;
  1687. if (!wcd938x->dev_up) {
  1688. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1689. __func__, req);
  1690. ret = -ENODEV;
  1691. goto done;
  1692. }
  1693. if ((wcd938x->micb_ref[micb_index] == 0) &&
  1694. (wcd938x->pullup_ref[micb_index] > 0))
  1695. snd_soc_component_update_bits(component, micb_reg,
  1696. 0xC0, 0x80);
  1697. else if ((wcd938x->micb_ref[micb_index] == 0) &&
  1698. (wcd938x->pullup_ref[micb_index] == 0)) {
  1699. if (pre_off_event && wcd938x->mbhc)
  1700. blocking_notifier_call_chain(
  1701. &wcd938x->mbhc->notifier,
  1702. pre_off_event,
  1703. &wcd938x->mbhc->wcd_mbhc);
  1704. snd_soc_component_update_bits(component, micb_reg,
  1705. 0xC0, 0x00);
  1706. if (post_off_event && wcd938x->mbhc)
  1707. blocking_notifier_call_chain(
  1708. &wcd938x->mbhc->notifier,
  1709. post_off_event,
  1710. &wcd938x->mbhc->wcd_mbhc);
  1711. }
  1712. if (is_dapm && post_dapm_off && wcd938x->mbhc)
  1713. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1714. post_dapm_off,
  1715. &wcd938x->mbhc->wcd_mbhc);
  1716. break;
  1717. };
  1718. dev_dbg(component->dev,
  1719. "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1720. __func__, micb_num, wcd938x->micb_ref[micb_index],
  1721. wcd938x->pullup_ref[micb_index]);
  1722. done:
  1723. mutex_unlock(&wcd938x->micb_lock);
  1724. return ret;
  1725. }
  1726. EXPORT_SYMBOL(wcd938x_micbias_control);
  1727. static int wcd938x_get_logical_addr(struct swr_device *swr_dev)
  1728. {
  1729. int ret = 0;
  1730. uint8_t devnum = 0;
  1731. int num_retry = NUM_ATTEMPTS;
  1732. do {
  1733. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1734. if (ret) {
  1735. dev_err(&swr_dev->dev,
  1736. "%s get devnum %d for dev addr %lx failed\n",
  1737. __func__, devnum, swr_dev->addr);
  1738. /* retry after 1ms */
  1739. usleep_range(1000, 1010);
  1740. }
  1741. } while (ret && --num_retry);
  1742. swr_dev->dev_num = devnum;
  1743. return 0;
  1744. }
  1745. static int wcd938x_event_notify(struct notifier_block *block,
  1746. unsigned long val,
  1747. void *data)
  1748. {
  1749. u16 event = (val & 0xffff);
  1750. int ret = 0;
  1751. struct wcd938x_priv *wcd938x = dev_get_drvdata((struct device *)data);
  1752. struct snd_soc_component *component = wcd938x->component;
  1753. struct wcd_mbhc *mbhc;
  1754. switch (event) {
  1755. case BOLERO_WCD_EVT_TX_CH_HOLD_CLEAR:
  1756. if (test_bit(WCD_ADC1, &wcd938x->status_mask)) {
  1757. snd_soc_component_update_bits(component,
  1758. WCD938X_ANA_TX_CH2, 0x40, 0x00);
  1759. clear_bit(WCD_ADC1, &wcd938x->status_mask);
  1760. }
  1761. if (test_bit(WCD_ADC2, &wcd938x->status_mask)) {
  1762. snd_soc_component_update_bits(component,
  1763. WCD938X_ANA_TX_CH2, 0x20, 0x00);
  1764. clear_bit(WCD_ADC2, &wcd938x->status_mask);
  1765. }
  1766. if (test_bit(WCD_ADC3, &wcd938x->status_mask)) {
  1767. snd_soc_component_update_bits(component,
  1768. WCD938X_ANA_TX_CH4, 0x40, 0x00);
  1769. clear_bit(WCD_ADC3, &wcd938x->status_mask);
  1770. }
  1771. if (test_bit(WCD_ADC4, &wcd938x->status_mask)) {
  1772. snd_soc_component_update_bits(component,
  1773. WCD938X_ANA_TX_CH4, 0x20, 0x00);
  1774. clear_bit(WCD_ADC4, &wcd938x->status_mask);
  1775. }
  1776. break;
  1777. case BOLERO_WCD_EVT_PA_OFF_PRE_SSR:
  1778. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  1779. 0xC0, 0x00);
  1780. snd_soc_component_update_bits(component, WCD938X_ANA_EAR,
  1781. 0x80, 0x00);
  1782. snd_soc_component_update_bits(component, WCD938X_AUX_AUXPA,
  1783. 0x80, 0x00);
  1784. break;
  1785. case BOLERO_WCD_EVT_SSR_DOWN:
  1786. wcd938x->dev_up = false;
  1787. mbhc = &wcd938x->mbhc->wcd_mbhc;
  1788. wcd938x_mbhc_ssr_down(wcd938x->mbhc, component);
  1789. wcd938x_reset_low(wcd938x->dev);
  1790. break;
  1791. case BOLERO_WCD_EVT_SSR_UP:
  1792. wcd938x_reset(wcd938x->dev);
  1793. /* allow reset to take effect */
  1794. usleep_range(10000, 10010);
  1795. wcd938x_get_logical_addr(wcd938x->tx_swr_dev);
  1796. wcd938x_get_logical_addr(wcd938x->rx_swr_dev);
  1797. wcd938x_init_reg(component);
  1798. regcache_mark_dirty(wcd938x->regmap);
  1799. regcache_sync(wcd938x->regmap);
  1800. /* Initialize MBHC module */
  1801. mbhc = &wcd938x->mbhc->wcd_mbhc;
  1802. ret = wcd938x_mbhc_post_ssr_init(wcd938x->mbhc, component);
  1803. if (ret) {
  1804. dev_err(component->dev, "%s: mbhc initialization failed\n",
  1805. __func__);
  1806. } else {
  1807. wcd938x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  1808. }
  1809. wcd938x->dev_up = true;
  1810. break;
  1811. case BOLERO_WCD_EVT_CLK_NOTIFY:
  1812. snd_soc_component_update_bits(component,
  1813. WCD938X_DIGITAL_TOP_CLK_CFG, 0x06,
  1814. ((val >> 0x10) << 0x01));
  1815. break;
  1816. default:
  1817. dev_dbg(component->dev, "%s: invalid event %d\n", __func__, event);
  1818. break;
  1819. }
  1820. return 0;
  1821. }
  1822. static int __wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1823. int event)
  1824. {
  1825. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1826. int micb_num;
  1827. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1828. __func__, w->name, event);
  1829. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  1830. micb_num = MIC_BIAS_1;
  1831. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  1832. micb_num = MIC_BIAS_2;
  1833. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  1834. micb_num = MIC_BIAS_3;
  1835. else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4")))
  1836. micb_num = MIC_BIAS_4;
  1837. else
  1838. return -EINVAL;
  1839. switch (event) {
  1840. case SND_SOC_DAPM_PRE_PMU:
  1841. wcd938x_micbias_control(component, micb_num,
  1842. MICB_ENABLE, true);
  1843. break;
  1844. case SND_SOC_DAPM_POST_PMU:
  1845. /* 1 msec delay as per HW requirement */
  1846. usleep_range(1000, 1100);
  1847. break;
  1848. case SND_SOC_DAPM_POST_PMD:
  1849. wcd938x_micbias_control(component, micb_num,
  1850. MICB_DISABLE, true);
  1851. break;
  1852. };
  1853. return 0;
  1854. }
  1855. static int wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1856. struct snd_kcontrol *kcontrol,
  1857. int event)
  1858. {
  1859. return __wcd938x_codec_enable_micbias(w, event);
  1860. }
  1861. static int __wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1862. int event)
  1863. {
  1864. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1865. int micb_num;
  1866. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1867. __func__, w->name, event);
  1868. if (strnstr(w->name, "VA MIC BIAS1", sizeof("VA MIC BIAS1")))
  1869. micb_num = MIC_BIAS_1;
  1870. else if (strnstr(w->name, "VA MIC BIAS2", sizeof("VA MIC BIAS2")))
  1871. micb_num = MIC_BIAS_2;
  1872. else if (strnstr(w->name, "VA MIC BIAS3", sizeof("VA MIC BIAS3")))
  1873. micb_num = MIC_BIAS_3;
  1874. else if (strnstr(w->name, "VA MIC BIAS4", sizeof("VA MIC BIAS4")))
  1875. micb_num = MIC_BIAS_4;
  1876. else
  1877. return -EINVAL;
  1878. switch (event) {
  1879. case SND_SOC_DAPM_PRE_PMU:
  1880. wcd938x_micbias_control(component, micb_num,
  1881. MICB_PULLUP_ENABLE, true);
  1882. break;
  1883. case SND_SOC_DAPM_POST_PMU:
  1884. /* 1 msec delay as per HW requirement */
  1885. usleep_range(1000, 1100);
  1886. break;
  1887. case SND_SOC_DAPM_POST_PMD:
  1888. wcd938x_micbias_control(component, micb_num,
  1889. MICB_PULLUP_DISABLE, true);
  1890. break;
  1891. };
  1892. return 0;
  1893. }
  1894. static int wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1895. struct snd_kcontrol *kcontrol,
  1896. int event)
  1897. {
  1898. return __wcd938x_codec_enable_micbias_pullup(w, event);
  1899. }
  1900. static int wcd938x_wakeup(void *handle, bool enable)
  1901. {
  1902. struct wcd938x_priv *priv;
  1903. int ret = 0;
  1904. if (!handle) {
  1905. pr_err("%s: NULL handle\n", __func__);
  1906. return -EINVAL;
  1907. }
  1908. priv = (struct wcd938x_priv *)handle;
  1909. if (!priv->tx_swr_dev) {
  1910. pr_err("%s: tx swr dev is NULL\n", __func__);
  1911. return -EINVAL;
  1912. }
  1913. mutex_lock(&priv->wakeup_lock);
  1914. if (enable)
  1915. ret = swr_device_wakeup_vote(priv->tx_swr_dev);
  1916. else
  1917. ret = swr_device_wakeup_unvote(priv->tx_swr_dev);
  1918. mutex_unlock(&priv->wakeup_lock);
  1919. return ret;
  1920. }
  1921. static int wcd938x_codec_force_enable_micbias(struct snd_soc_dapm_widget *w,
  1922. struct snd_kcontrol *kcontrol,
  1923. int event)
  1924. {
  1925. int ret = 0;
  1926. struct snd_soc_component *component =
  1927. snd_soc_dapm_to_component(w->dapm);
  1928. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1929. switch (event) {
  1930. case SND_SOC_DAPM_PRE_PMU:
  1931. wcd938x_wakeup(wcd938x, true);
  1932. ret = __wcd938x_codec_enable_micbias(w, SND_SOC_DAPM_PRE_PMU);
  1933. wcd938x_wakeup(wcd938x, false);
  1934. break;
  1935. case SND_SOC_DAPM_POST_PMD:
  1936. wcd938x_wakeup(wcd938x, true);
  1937. ret = __wcd938x_codec_enable_micbias(w, SND_SOC_DAPM_POST_PMD);
  1938. wcd938x_wakeup(wcd938x, false);
  1939. break;
  1940. }
  1941. return ret;
  1942. }
  1943. static int wcd938x_enable_micbias(struct wcd938x_priv *wcd938x,
  1944. int micb_num, int req)
  1945. {
  1946. int micb_index = micb_num - 1;
  1947. u16 micb_reg;
  1948. if (NULL == wcd938x) {
  1949. pr_err("%s: wcd938x private data is NULL\n", __func__);
  1950. return -EINVAL;
  1951. }
  1952. switch (micb_num) {
  1953. case MIC_BIAS_1:
  1954. micb_reg = WCD938X_ANA_MICB1;
  1955. break;
  1956. case MIC_BIAS_2:
  1957. micb_reg = WCD938X_ANA_MICB2;
  1958. break;
  1959. case MIC_BIAS_3:
  1960. micb_reg = WCD938X_ANA_MICB3;
  1961. break;
  1962. case MIC_BIAS_4:
  1963. micb_reg = WCD938X_ANA_MICB4;
  1964. break;
  1965. default:
  1966. pr_err("%s: Invalid micbias number: %d\n", __func__, micb_num);
  1967. return -EINVAL;
  1968. };
  1969. mutex_lock(&wcd938x->micb_lock);
  1970. switch (req) {
  1971. case MICB_ENABLE:
  1972. wcd938x->micb_ref[micb_index]++;
  1973. if (wcd938x->micb_ref[micb_index] == 1) {
  1974. regmap_update_bits(wcd938x->regmap,
  1975. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xE0, 0xE0);
  1976. regmap_update_bits(wcd938x->regmap,
  1977. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1978. regmap_update_bits(wcd938x->regmap,
  1979. WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x01, 0x01);
  1980. regmap_update_bits(wcd938x->regmap,
  1981. WCD938X_MICB1_TEST_CTL_2, 0x01, 0x01);
  1982. regmap_update_bits(wcd938x->regmap,
  1983. WCD938X_MICB2_TEST_CTL_2, 0x01, 0x01);
  1984. regmap_update_bits(wcd938x->regmap,
  1985. WCD938X_MICB3_TEST_CTL_2, 0x01, 0x01);
  1986. regmap_update_bits(wcd938x->regmap,
  1987. WCD938X_MICB4_TEST_CTL_2, 0x01, 0x01);
  1988. regmap_update_bits(wcd938x->regmap,
  1989. micb_reg, 0xC0, 0x40);
  1990. regmap_update_bits(wcd938x->regmap, micb_reg, 0x3F, 0x10);
  1991. }
  1992. break;
  1993. case MICB_PULLUP_ENABLE:
  1994. wcd938x->pullup_ref[micb_index]++;
  1995. if ((wcd938x->pullup_ref[micb_index] == 1) &&
  1996. (wcd938x->micb_ref[micb_index] == 0))
  1997. regmap_update_bits(wcd938x->regmap, micb_reg,
  1998. 0xC0, 0x80);
  1999. break;
  2000. case MICB_PULLUP_DISABLE:
  2001. if (wcd938x->pullup_ref[micb_index] > 0)
  2002. wcd938x->pullup_ref[micb_index]--;
  2003. if ((wcd938x->pullup_ref[micb_index] == 0) &&
  2004. (wcd938x->micb_ref[micb_index] == 0))
  2005. regmap_update_bits(wcd938x->regmap, micb_reg,
  2006. 0xC0, 0x00);
  2007. break;
  2008. case MICB_DISABLE:
  2009. if (wcd938x->micb_ref[micb_index] > 0)
  2010. wcd938x->micb_ref[micb_index]--;
  2011. if ((wcd938x->micb_ref[micb_index] == 0) &&
  2012. (wcd938x->pullup_ref[micb_index] > 0))
  2013. regmap_update_bits(wcd938x->regmap, micb_reg,
  2014. 0xC0, 0x80);
  2015. else if ((wcd938x->micb_ref[micb_index] == 0) &&
  2016. (wcd938x->pullup_ref[micb_index] == 0))
  2017. regmap_update_bits(wcd938x->regmap, micb_reg,
  2018. 0xC0, 0x00);
  2019. break;
  2020. };
  2021. mutex_unlock(&wcd938x->micb_lock);
  2022. return 0;
  2023. }
  2024. int wcd938x_codec_force_enable_micbias_v2(struct snd_soc_component *component,
  2025. int event, int micb_num)
  2026. {
  2027. struct wcd938x_priv *wcd938x_priv = NULL;
  2028. if(NULL == component) {
  2029. pr_err("%s: wcd938x component is NULL\n", __func__);
  2030. return -EINVAL;
  2031. }
  2032. if(event != SND_SOC_DAPM_PRE_PMU && event != SND_SOC_DAPM_POST_PMD) {
  2033. pr_err("%s: invalid event: %d\n", __func__, event);
  2034. return -EINVAL;
  2035. }
  2036. if(micb_num < MIC_BIAS_1 || micb_num > MIC_BIAS_4) {
  2037. pr_err("%s: invalid mic bias num: %d\n", __func__, micb_num);
  2038. return -EINVAL;
  2039. }
  2040. wcd938x_priv = snd_soc_component_get_drvdata(component);
  2041. switch (event) {
  2042. case SND_SOC_DAPM_PRE_PMU:
  2043. wcd938x_wakeup(wcd938x_priv, true);
  2044. wcd938x_enable_micbias(wcd938x_priv, micb_num, MICB_PULLUP_ENABLE);
  2045. wcd938x_wakeup(wcd938x_priv, false);
  2046. break;
  2047. case SND_SOC_DAPM_POST_PMD:
  2048. wcd938x_wakeup(wcd938x_priv, true);
  2049. wcd938x_enable_micbias(wcd938x_priv, micb_num, MICB_PULLUP_DISABLE);
  2050. wcd938x_wakeup(wcd938x_priv, false);
  2051. break;
  2052. }
  2053. return 0;
  2054. }
  2055. EXPORT_SYMBOL(wcd938x_codec_force_enable_micbias_v2);
  2056. static inline int wcd938x_tx_path_get(const char *wname,
  2057. unsigned int *path_num)
  2058. {
  2059. int ret = 0;
  2060. char *widget_name = NULL;
  2061. char *w_name = NULL;
  2062. char *path_num_char = NULL;
  2063. char *path_name = NULL;
  2064. widget_name = kstrndup(wname, 9, GFP_KERNEL);
  2065. if (!widget_name)
  2066. return -EINVAL;
  2067. w_name = widget_name;
  2068. path_name = strsep(&widget_name, " ");
  2069. if (!path_name) {
  2070. pr_err("%s: Invalid widget name = %s\n",
  2071. __func__, widget_name);
  2072. ret = -EINVAL;
  2073. goto err;
  2074. }
  2075. path_num_char = strpbrk(path_name, "0123");
  2076. if (!path_num_char) {
  2077. pr_err("%s: tx path index not found\n",
  2078. __func__);
  2079. ret = -EINVAL;
  2080. goto err;
  2081. }
  2082. ret = kstrtouint(path_num_char, 10, path_num);
  2083. if (ret < 0)
  2084. pr_err("%s: Invalid tx path = %s\n",
  2085. __func__, w_name);
  2086. err:
  2087. kfree(w_name);
  2088. return ret;
  2089. }
  2090. static int wcd938x_tx_mode_get(struct snd_kcontrol *kcontrol,
  2091. struct snd_ctl_elem_value *ucontrol)
  2092. {
  2093. struct snd_soc_component *component =
  2094. snd_soc_kcontrol_component(kcontrol);
  2095. struct wcd938x_priv *wcd938x = NULL;
  2096. int ret = 0;
  2097. unsigned int path = 0;
  2098. if (!component)
  2099. return -EINVAL;
  2100. wcd938x = snd_soc_component_get_drvdata(component);
  2101. if (!wcd938x)
  2102. return -EINVAL;
  2103. ret = wcd938x_tx_path_get(kcontrol->id.name, &path);
  2104. if (ret < 0)
  2105. return ret;
  2106. ucontrol->value.integer.value[0] = wcd938x->tx_mode[path];
  2107. return 0;
  2108. }
  2109. static int wcd938x_tx_mode_put(struct snd_kcontrol *kcontrol,
  2110. struct snd_ctl_elem_value *ucontrol)
  2111. {
  2112. struct snd_soc_component *component =
  2113. snd_soc_kcontrol_component(kcontrol);
  2114. struct wcd938x_priv *wcd938x = NULL;
  2115. u32 mode_val;
  2116. unsigned int path = 0;
  2117. int ret = 0;
  2118. if (!component)
  2119. return -EINVAL;
  2120. wcd938x = snd_soc_component_get_drvdata(component);
  2121. if (!wcd938x)
  2122. return -EINVAL;
  2123. ret = wcd938x_tx_path_get(kcontrol->id.name, &path);
  2124. if (ret)
  2125. return ret;
  2126. mode_val = ucontrol->value.enumerated.item[0];
  2127. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  2128. wcd938x->tx_mode[path] = mode_val;
  2129. return 0;
  2130. }
  2131. static int wcd938x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  2132. struct snd_ctl_elem_value *ucontrol)
  2133. {
  2134. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2135. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2136. ucontrol->value.integer.value[0] = wcd938x->hph_mode;
  2137. return 0;
  2138. }
  2139. static int wcd938x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  2140. struct snd_ctl_elem_value *ucontrol)
  2141. {
  2142. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2143. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2144. u32 mode_val;
  2145. mode_val = ucontrol->value.enumerated.item[0];
  2146. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  2147. if (wcd938x->variant == WCD9380) {
  2148. if (mode_val == CLS_H_HIFI || mode_val == CLS_AB_HIFI) {
  2149. dev_info(component->dev,
  2150. "%s:Invalid HPH Mode, default to CLS_H_ULP\n",
  2151. __func__);
  2152. mode_val = CLS_H_ULP;
  2153. }
  2154. }
  2155. if (mode_val == CLS_H_NORMAL) {
  2156. dev_info(component->dev,
  2157. "%s:Invalid HPH Mode, default to class_AB\n",
  2158. __func__);
  2159. mode_val = CLS_H_ULP;
  2160. }
  2161. wcd938x->hph_mode = mode_val;
  2162. return 0;
  2163. }
  2164. static int wcd938x_ear_pa_gain_get(struct snd_kcontrol *kcontrol,
  2165. struct snd_ctl_elem_value *ucontrol)
  2166. {
  2167. u8 ear_pa_gain = 0;
  2168. struct snd_soc_component *component =
  2169. snd_soc_kcontrol_component(kcontrol);
  2170. ear_pa_gain = snd_soc_component_read32(component,
  2171. WCD938X_ANA_EAR_COMPANDER_CTL);
  2172. ear_pa_gain = (ear_pa_gain & 0x7C) >> 2;
  2173. ucontrol->value.integer.value[0] = ear_pa_gain;
  2174. dev_dbg(component->dev, "%s: ear_pa_gain = 0x%x\n", __func__,
  2175. ear_pa_gain);
  2176. return 0;
  2177. }
  2178. static int wcd938x_ear_pa_gain_put(struct snd_kcontrol *kcontrol,
  2179. struct snd_ctl_elem_value *ucontrol)
  2180. {
  2181. u8 ear_pa_gain = 0;
  2182. struct snd_soc_component *component =
  2183. snd_soc_kcontrol_component(kcontrol);
  2184. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2185. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  2186. __func__, ucontrol->value.integer.value[0]);
  2187. ear_pa_gain = ucontrol->value.integer.value[0] << 2;
  2188. if (!wcd938x->comp1_enable) {
  2189. snd_soc_component_update_bits(component,
  2190. WCD938X_ANA_EAR_COMPANDER_CTL,
  2191. 0x7C, ear_pa_gain);
  2192. }
  2193. return 0;
  2194. }
  2195. static int wcd938x_get_compander(struct snd_kcontrol *kcontrol,
  2196. struct snd_ctl_elem_value *ucontrol)
  2197. {
  2198. struct snd_soc_component *component =
  2199. snd_soc_kcontrol_component(kcontrol);
  2200. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2201. bool hphr;
  2202. struct soc_multi_mixer_control *mc;
  2203. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2204. hphr = mc->shift;
  2205. ucontrol->value.integer.value[0] = hphr ? wcd938x->comp2_enable :
  2206. wcd938x->comp1_enable;
  2207. return 0;
  2208. }
  2209. static int wcd938x_set_compander(struct snd_kcontrol *kcontrol,
  2210. struct snd_ctl_elem_value *ucontrol)
  2211. {
  2212. struct snd_soc_component *component =
  2213. snd_soc_kcontrol_component(kcontrol);
  2214. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2215. int value = ucontrol->value.integer.value[0];
  2216. bool hphr;
  2217. struct soc_multi_mixer_control *mc;
  2218. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2219. hphr = mc->shift;
  2220. if (hphr)
  2221. wcd938x->comp2_enable = value;
  2222. else
  2223. wcd938x->comp1_enable = value;
  2224. return 0;
  2225. }
  2226. static int wcd938x_ldoh_get(struct snd_kcontrol *kcontrol,
  2227. struct snd_ctl_elem_value *ucontrol)
  2228. {
  2229. struct snd_soc_component *component =
  2230. snd_soc_kcontrol_component(kcontrol);
  2231. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2232. ucontrol->value.integer.value[0] = wcd938x->ldoh;
  2233. return 0;
  2234. }
  2235. static int wcd938x_ldoh_put(struct snd_kcontrol *kcontrol,
  2236. struct snd_ctl_elem_value *ucontrol)
  2237. {
  2238. struct snd_soc_component *component =
  2239. snd_soc_kcontrol_component(kcontrol);
  2240. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2241. wcd938x->ldoh = ucontrol->value.integer.value[0];
  2242. return 0;
  2243. }
  2244. const char * const tx_master_ch_text[] = {
  2245. "ZERO", "SWRM_TX1_CH1", "SWRM_TX1_CH2", "SWRM_TX1_CH3", "SWRM_TX1_CH4",
  2246. "SWRM_TX2_CH1", "SWRM_TX2_CH2", "SWRM_TX2_CH3", "SWRM_TX2_CH4",
  2247. "SWRM_TX3_CH1", "SWRM_TX3_CH2", "SWRM_TX3_CH3", "SWRM_TX3_CH4",
  2248. "SWRM_PCM_IN",
  2249. };
  2250. const struct soc_enum tx_master_ch_enum =
  2251. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_master_ch_text),
  2252. tx_master_ch_text);
  2253. static void wcd938x_tx_get_slave_ch_type_idx(const char *wname, int *ch_idx)
  2254. {
  2255. u8 ch_type = 0;
  2256. if (strnstr(wname, "ADC1", sizeof("ADC1")))
  2257. ch_type = ADC1;
  2258. else if (strnstr(wname, "ADC2", sizeof("ADC2")))
  2259. ch_type = ADC2;
  2260. else if (strnstr(wname, "ADC3", sizeof("ADC3")))
  2261. ch_type = ADC3;
  2262. else if (strnstr(wname, "ADC4", sizeof("ADC4")))
  2263. ch_type = ADC4;
  2264. else if (strnstr(wname, "DMIC0", sizeof("DMIC0")))
  2265. ch_type = DMIC0;
  2266. else if (strnstr(wname, "DMIC1", sizeof("DMIC1")))
  2267. ch_type = DMIC1;
  2268. else if (strnstr(wname, "MBHC", sizeof("MBHC")))
  2269. ch_type = MBHC;
  2270. else if (strnstr(wname, "DMIC2", sizeof("DMIC2")))
  2271. ch_type = DMIC2;
  2272. else if (strnstr(wname, "DMIC3", sizeof("DMIC3")))
  2273. ch_type = DMIC3;
  2274. else if (strnstr(wname, "DMIC4", sizeof("DMIC4")))
  2275. ch_type = DMIC4;
  2276. else if (strnstr(wname, "DMIC5", sizeof("DMIC5")))
  2277. ch_type = DMIC5;
  2278. else if (strnstr(wname, "DMIC6", sizeof("DMIC6")))
  2279. ch_type = DMIC6;
  2280. else if (strnstr(wname, "DMIC7", sizeof("DMIC7")))
  2281. ch_type = DMIC7;
  2282. else
  2283. pr_err("%s: port name: %s is not listed\n", __func__, wname);
  2284. if (ch_type)
  2285. *ch_idx = wcd938x_slave_get_slave_ch_val(ch_type);
  2286. else
  2287. *ch_idx = -EINVAL;
  2288. }
  2289. static int wcd938x_tx_master_ch_get(struct snd_kcontrol *kcontrol,
  2290. struct snd_ctl_elem_value *ucontrol)
  2291. {
  2292. struct snd_soc_component *component =
  2293. snd_soc_kcontrol_component(kcontrol);
  2294. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2295. int slave_ch_idx;
  2296. wcd938x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2297. if (slave_ch_idx != -EINVAL)
  2298. ucontrol->value.integer.value[0] =
  2299. wcd938x_slave_get_master_ch_val(
  2300. wcd938x->tx_master_ch_map[slave_ch_idx]);
  2301. return 0;
  2302. }
  2303. static int wcd938x_tx_master_ch_put(struct snd_kcontrol *kcontrol,
  2304. struct snd_ctl_elem_value *ucontrol)
  2305. {
  2306. struct snd_soc_component *component =
  2307. snd_soc_kcontrol_component(kcontrol);
  2308. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2309. int slave_ch_idx;
  2310. wcd938x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2311. dev_dbg(component->dev, "%s: slave_ch_idx: %d", __func__, slave_ch_idx);
  2312. dev_dbg(component->dev, "%s: ucontrol->value.enumerated.item[0] = %ld\n",
  2313. __func__, ucontrol->value.enumerated.item[0]);
  2314. if (slave_ch_idx != -EINVAL)
  2315. wcd938x->tx_master_ch_map[slave_ch_idx] =
  2316. wcd938x_slave_get_master_ch(
  2317. ucontrol->value.enumerated.item[0]);
  2318. return 0;
  2319. }
  2320. static const char * const tx_mode_mux_text_wcd9380[] = {
  2321. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  2322. };
  2323. static const struct soc_enum tx_mode_mux_enum_wcd9380 =
  2324. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text_wcd9380),
  2325. tx_mode_mux_text_wcd9380);
  2326. static const char * const tx_mode_mux_text[] = {
  2327. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  2328. "ADC_ULP1", "ADC_ULP2",
  2329. };
  2330. static const struct soc_enum tx_mode_mux_enum =
  2331. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text),
  2332. tx_mode_mux_text);
  2333. static const char * const rx_hph_mode_mux_text_wcd9380[] = {
  2334. "CLS_H_INVALID", "CLS_H_INVALID_1", "CLS_H_LP", "CLS_AB",
  2335. "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_H_INVALID_2", "CLS_AB_LP",
  2336. "CLS_AB_LOHIFI",
  2337. };
  2338. static const char * const wcd938x_ear_pa_gain_text[] = {
  2339. "G_6_DB", "G_4P5_DB", "G_3_DB", "G_1P5_DB", "G_0_DB",
  2340. "G_M1P5_DB", "G_M3_DB", "G_M4P5_DB",
  2341. "G_M6_DB", "G_7P5_DB", "G_M9_DB",
  2342. "G_M10P5_DB", "G_M12_DB", "G_M13P5_DB",
  2343. "G_M15_DB", "G_M16P5_DB", "G_M18_DB",
  2344. };
  2345. static const struct soc_enum rx_hph_mode_mux_enum_wcd9380 =
  2346. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text_wcd9380),
  2347. rx_hph_mode_mux_text_wcd9380);
  2348. static SOC_ENUM_SINGLE_EXT_DECL(wcd938x_ear_pa_gain_enum,
  2349. wcd938x_ear_pa_gain_text);
  2350. static const char * const rx_hph_mode_mux_text[] = {
  2351. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  2352. "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI",
  2353. };
  2354. static const struct soc_enum rx_hph_mode_mux_enum =
  2355. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  2356. rx_hph_mode_mux_text);
  2357. static const struct snd_kcontrol_new wcd9380_snd_controls[] = {
  2358. SOC_ENUM_EXT("EAR PA GAIN", wcd938x_ear_pa_gain_enum,
  2359. wcd938x_ear_pa_gain_get, wcd938x_ear_pa_gain_put),
  2360. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum_wcd9380,
  2361. wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
  2362. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum_wcd9380,
  2363. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2364. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum_wcd9380,
  2365. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2366. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum_wcd9380,
  2367. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2368. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum_wcd9380,
  2369. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2370. };
  2371. static const struct snd_kcontrol_new wcd9385_snd_controls[] = {
  2372. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  2373. wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
  2374. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum,
  2375. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2376. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum,
  2377. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2378. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum,
  2379. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2380. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum,
  2381. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2382. };
  2383. static const struct snd_kcontrol_new wcd938x_snd_controls[] = {
  2384. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  2385. wcd938x_get_compander, wcd938x_set_compander),
  2386. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  2387. wcd938x_get_compander, wcd938x_set_compander),
  2388. SOC_SINGLE_EXT("LDOH Enable", SND_SOC_NOPM, 0, 1, 0,
  2389. wcd938x_ldoh_get, wcd938x_ldoh_put),
  2390. SOC_SINGLE_TLV("HPHL Volume", WCD938X_HPH_L_EN, 0, 20, 1, line_gain),
  2391. SOC_SINGLE_TLV("HPHR Volume", WCD938X_HPH_R_EN, 0, 20, 1, line_gain),
  2392. SOC_SINGLE_TLV("ADC1 Volume", WCD938X_ANA_TX_CH1, 0, 20, 0,
  2393. analog_gain),
  2394. SOC_SINGLE_TLV("ADC2 Volume", WCD938X_ANA_TX_CH2, 0, 20, 0,
  2395. analog_gain),
  2396. SOC_SINGLE_TLV("ADC3 Volume", WCD938X_ANA_TX_CH3, 0, 20, 0,
  2397. analog_gain),
  2398. SOC_SINGLE_TLV("ADC4 Volume", WCD938X_ANA_TX_CH4, 0, 20, 0,
  2399. analog_gain),
  2400. SOC_ENUM_EXT("ADC1 ChMap", tx_master_ch_enum,
  2401. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2402. SOC_ENUM_EXT("ADC2 ChMap", tx_master_ch_enum,
  2403. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2404. SOC_ENUM_EXT("ADC3 ChMap", tx_master_ch_enum,
  2405. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2406. SOC_ENUM_EXT("ADC4 ChMap", tx_master_ch_enum,
  2407. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2408. SOC_ENUM_EXT("DMIC0 ChMap", tx_master_ch_enum,
  2409. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2410. SOC_ENUM_EXT("DMIC1 ChMap", tx_master_ch_enum,
  2411. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2412. SOC_ENUM_EXT("MBHC ChMap", tx_master_ch_enum,
  2413. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2414. SOC_ENUM_EXT("DMIC2 ChMap", tx_master_ch_enum,
  2415. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2416. SOC_ENUM_EXT("DMIC3 ChMap", tx_master_ch_enum,
  2417. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2418. SOC_ENUM_EXT("DMIC4 ChMap", tx_master_ch_enum,
  2419. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2420. SOC_ENUM_EXT("DMIC5 ChMap", tx_master_ch_enum,
  2421. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2422. SOC_ENUM_EXT("DMIC6 ChMap", tx_master_ch_enum,
  2423. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2424. SOC_ENUM_EXT("DMIC7 ChMap", tx_master_ch_enum,
  2425. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2426. };
  2427. static const struct snd_kcontrol_new adc1_switch[] = {
  2428. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2429. };
  2430. static const struct snd_kcontrol_new adc2_switch[] = {
  2431. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2432. };
  2433. static const struct snd_kcontrol_new adc3_switch[] = {
  2434. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2435. };
  2436. static const struct snd_kcontrol_new adc4_switch[] = {
  2437. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2438. };
  2439. static const struct snd_kcontrol_new dmic1_switch[] = {
  2440. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2441. };
  2442. static const struct snd_kcontrol_new dmic2_switch[] = {
  2443. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2444. };
  2445. static const struct snd_kcontrol_new dmic3_switch[] = {
  2446. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2447. };
  2448. static const struct snd_kcontrol_new dmic4_switch[] = {
  2449. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2450. };
  2451. static const struct snd_kcontrol_new dmic5_switch[] = {
  2452. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2453. };
  2454. static const struct snd_kcontrol_new dmic6_switch[] = {
  2455. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2456. };
  2457. static const struct snd_kcontrol_new dmic7_switch[] = {
  2458. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2459. };
  2460. static const struct snd_kcontrol_new dmic8_switch[] = {
  2461. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2462. };
  2463. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  2464. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2465. };
  2466. static const struct snd_kcontrol_new aux_rdac_switch[] = {
  2467. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2468. };
  2469. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  2470. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2471. };
  2472. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  2473. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2474. };
  2475. static const char * const adc2_mux_text[] = {
  2476. "INP2", "INP3"
  2477. };
  2478. static const struct soc_enum adc2_enum =
  2479. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 7,
  2480. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  2481. static const struct snd_kcontrol_new tx_adc2_mux =
  2482. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  2483. static const char * const adc3_mux_text[] = {
  2484. "INP4", "INP6"
  2485. };
  2486. static const struct soc_enum adc3_enum =
  2487. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 6,
  2488. ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
  2489. static const struct snd_kcontrol_new tx_adc3_mux =
  2490. SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
  2491. static const char * const adc4_mux_text[] = {
  2492. "INP5", "INP7"
  2493. };
  2494. static const struct soc_enum adc4_enum =
  2495. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 5,
  2496. ARRAY_SIZE(adc4_mux_text), adc4_mux_text);
  2497. static const struct snd_kcontrol_new tx_adc4_mux =
  2498. SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum);
  2499. static const char * const rdac3_mux_text[] = {
  2500. "RX1", "RX3"
  2501. };
  2502. static const char * const hdr12_mux_text[] = {
  2503. "NO_HDR12", "HDR12"
  2504. };
  2505. static const struct soc_enum hdr12_enum =
  2506. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 4,
  2507. ARRAY_SIZE(hdr12_mux_text), hdr12_mux_text);
  2508. static const struct snd_kcontrol_new tx_hdr12_mux =
  2509. SOC_DAPM_ENUM("HDR12 MUX Mux", hdr12_enum);
  2510. static const char * const hdr34_mux_text[] = {
  2511. "NO_HDR34", "HDR34"
  2512. };
  2513. static const struct soc_enum hdr34_enum =
  2514. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 3,
  2515. ARRAY_SIZE(hdr34_mux_text), hdr34_mux_text);
  2516. static const struct snd_kcontrol_new tx_hdr34_mux =
  2517. SOC_DAPM_ENUM("HDR34 MUX Mux", hdr34_enum);
  2518. static const struct soc_enum rdac3_enum =
  2519. SOC_ENUM_SINGLE(WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0,
  2520. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  2521. static const struct snd_kcontrol_new rx_rdac3_mux =
  2522. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  2523. static const struct snd_soc_dapm_widget wcd938x_dapm_widgets[] = {
  2524. /*input widgets*/
  2525. SND_SOC_DAPM_INPUT("AMIC1"),
  2526. SND_SOC_DAPM_INPUT("AMIC2"),
  2527. SND_SOC_DAPM_INPUT("AMIC3"),
  2528. SND_SOC_DAPM_INPUT("AMIC4"),
  2529. SND_SOC_DAPM_INPUT("AMIC5"),
  2530. SND_SOC_DAPM_INPUT("AMIC6"),
  2531. SND_SOC_DAPM_INPUT("AMIC7"),
  2532. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  2533. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  2534. SND_SOC_DAPM_INPUT("IN3_AUX"),
  2535. /*tx widgets*/
  2536. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  2537. wcd938x_codec_enable_adc,
  2538. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2539. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
  2540. wcd938x_codec_enable_adc,
  2541. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2542. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
  2543. wcd938x_codec_enable_adc,
  2544. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2545. SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0,
  2546. wcd938x_codec_enable_adc,
  2547. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2548. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  2549. wcd938x_codec_enable_dmic,
  2550. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2551. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  2552. wcd938x_codec_enable_dmic,
  2553. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2554. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  2555. wcd938x_codec_enable_dmic,
  2556. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2557. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  2558. wcd938x_codec_enable_dmic,
  2559. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2560. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  2561. wcd938x_codec_enable_dmic,
  2562. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2563. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  2564. wcd938x_codec_enable_dmic,
  2565. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2566. SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0,
  2567. wcd938x_codec_enable_dmic,
  2568. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2569. SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0,
  2570. wcd938x_codec_enable_dmic,
  2571. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2572. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  2573. NULL, 0, wcd938x_enable_req,
  2574. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2575. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0,
  2576. NULL, 0, wcd938x_enable_req,
  2577. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2578. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0,
  2579. NULL, 0, wcd938x_enable_req,
  2580. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2581. SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0,
  2582. NULL, 0, wcd938x_enable_req,
  2583. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2584. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  2585. &tx_adc2_mux),
  2586. SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0,
  2587. &tx_adc3_mux),
  2588. SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0,
  2589. &tx_adc4_mux),
  2590. SND_SOC_DAPM_MUX("HDR12 MUX", SND_SOC_NOPM, 0, 0,
  2591. &tx_hdr12_mux),
  2592. SND_SOC_DAPM_MUX("HDR34 MUX", SND_SOC_NOPM, 0, 0,
  2593. &tx_hdr34_mux),
  2594. /*tx mixers*/
  2595. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0,
  2596. adc1_switch, ARRAY_SIZE(adc1_switch),
  2597. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2598. SND_SOC_DAPM_POST_PMD),
  2599. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 0, 0,
  2600. adc2_switch, ARRAY_SIZE(adc2_switch),
  2601. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2602. SND_SOC_DAPM_POST_PMD),
  2603. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 0, 0, adc3_switch,
  2604. ARRAY_SIZE(adc3_switch), wcd938x_tx_swr_ctrl,
  2605. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2606. SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, 0, 0, adc4_switch,
  2607. ARRAY_SIZE(adc4_switch), wcd938x_tx_swr_ctrl,
  2608. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2609. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0,
  2610. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  2611. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2612. SND_SOC_DAPM_POST_PMD),
  2613. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 0,
  2614. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  2615. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2616. SND_SOC_DAPM_POST_PMD),
  2617. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 0,
  2618. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  2619. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2620. SND_SOC_DAPM_POST_PMD),
  2621. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 0,
  2622. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  2623. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2624. SND_SOC_DAPM_POST_PMD),
  2625. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 0,
  2626. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  2627. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2628. SND_SOC_DAPM_POST_PMD),
  2629. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 0,
  2630. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  2631. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2632. SND_SOC_DAPM_POST_PMD),
  2633. SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, 0,
  2634. 0, dmic7_switch, ARRAY_SIZE(dmic7_switch),
  2635. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2636. SND_SOC_DAPM_POST_PMD),
  2637. SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, 0,
  2638. 0, dmic8_switch, ARRAY_SIZE(dmic8_switch),
  2639. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2640. SND_SOC_DAPM_POST_PMD),
  2641. /* micbias widgets*/
  2642. SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2643. wcd938x_codec_enable_micbias,
  2644. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2645. SND_SOC_DAPM_POST_PMD),
  2646. SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2647. wcd938x_codec_enable_micbias,
  2648. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2649. SND_SOC_DAPM_POST_PMD),
  2650. SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2651. wcd938x_codec_enable_micbias,
  2652. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2653. SND_SOC_DAPM_POST_PMD),
  2654. SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, 0, 0,
  2655. wcd938x_codec_enable_micbias,
  2656. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2657. SND_SOC_DAPM_POST_PMD),
  2658. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS1_STANDALONE, SND_SOC_NOPM, 0, 0,
  2659. wcd938x_codec_force_enable_micbias,
  2660. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2661. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS2_STANDALONE, SND_SOC_NOPM, 0, 0,
  2662. wcd938x_codec_force_enable_micbias,
  2663. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2664. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS3_STANDALONE, SND_SOC_NOPM, 0, 0,
  2665. wcd938x_codec_force_enable_micbias,
  2666. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2667. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS4_STANDALONE, SND_SOC_NOPM, 0, 0,
  2668. wcd938x_codec_force_enable_micbias,
  2669. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2670. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  2671. wcd938x_enable_clsh,
  2672. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2673. /*rx widgets*/
  2674. SND_SOC_DAPM_PGA_E("EAR PGA", WCD938X_ANA_EAR, 7, 0, NULL, 0,
  2675. wcd938x_codec_enable_ear_pa,
  2676. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2677. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2678. SND_SOC_DAPM_PGA_E("AUX PGA", WCD938X_AUX_AUXPA, 7, 0, NULL, 0,
  2679. wcd938x_codec_enable_aux_pa,
  2680. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2681. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2682. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD938X_ANA_HPH, 7, 0, NULL, 0,
  2683. wcd938x_codec_enable_hphl_pa,
  2684. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2685. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2686. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD938X_ANA_HPH, 6, 0, NULL, 0,
  2687. wcd938x_codec_enable_hphr_pa,
  2688. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2689. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2690. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  2691. wcd938x_codec_hphl_dac_event,
  2692. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2693. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2694. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  2695. wcd938x_codec_hphr_dac_event,
  2696. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2697. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2698. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  2699. wcd938x_codec_ear_dac_event,
  2700. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2701. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2702. SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
  2703. wcd938x_codec_aux_dac_event,
  2704. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2705. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2706. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  2707. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  2708. wcd938x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  2709. SND_SOC_DAPM_POST_PMD),
  2710. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  2711. wcd938x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  2712. SND_SOC_DAPM_POST_PMD),
  2713. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  2714. wcd938x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  2715. SND_SOC_DAPM_POST_PMD),
  2716. /* rx mixer widgets*/
  2717. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  2718. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  2719. SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
  2720. aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
  2721. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  2722. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  2723. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  2724. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  2725. /*output widgets tx*/
  2726. SND_SOC_DAPM_OUTPUT("WCD_TX_OUTPUT"),
  2727. /*output widgets rx*/
  2728. SND_SOC_DAPM_OUTPUT("EAR"),
  2729. SND_SOC_DAPM_OUTPUT("AUX"),
  2730. SND_SOC_DAPM_OUTPUT("HPHL"),
  2731. SND_SOC_DAPM_OUTPUT("HPHR"),
  2732. /* micbias pull up widgets*/
  2733. SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2734. wcd938x_codec_enable_micbias_pullup,
  2735. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2736. SND_SOC_DAPM_POST_PMD),
  2737. SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2738. wcd938x_codec_enable_micbias_pullup,
  2739. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2740. SND_SOC_DAPM_POST_PMD),
  2741. SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2742. wcd938x_codec_enable_micbias_pullup,
  2743. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2744. SND_SOC_DAPM_POST_PMD),
  2745. SND_SOC_DAPM_SUPPLY("VA MIC BIAS4", SND_SOC_NOPM, 0, 0,
  2746. wcd938x_codec_enable_micbias_pullup,
  2747. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2748. SND_SOC_DAPM_POST_PMD),
  2749. };
  2750. static const struct snd_soc_dapm_route wcd938x_audio_map[] = {
  2751. {"WCD_TX_OUTPUT", NULL, "ADC1_MIXER"},
  2752. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  2753. {"ADC1 REQ", NULL, "ADC1"},
  2754. {"ADC1", NULL, "AMIC1"},
  2755. {"WCD_TX_OUTPUT", NULL, "ADC2_MIXER"},
  2756. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  2757. {"ADC2 REQ", NULL, "ADC2"},
  2758. {"ADC2", NULL, "HDR12 MUX"},
  2759. {"HDR12 MUX", "NO_HDR12", "ADC2 MUX"},
  2760. {"HDR12 MUX", "HDR12", "AMIC1"},
  2761. {"ADC2 MUX", "INP3", "AMIC3"},
  2762. {"ADC2 MUX", "INP2", "AMIC2"},
  2763. {"WCD_TX_OUTPUT", NULL, "ADC3_MIXER"},
  2764. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  2765. {"ADC3 REQ", NULL, "ADC3"},
  2766. {"ADC3", NULL, "HDR34 MUX"},
  2767. {"HDR34 MUX", "NO_HDR34", "ADC3 MUX"},
  2768. {"HDR34 MUX", "HDR34", "AMIC5"},
  2769. {"ADC3 MUX", "INP4", "AMIC4"},
  2770. {"ADC3 MUX", "INP6", "AMIC6"},
  2771. {"WCD_TX_OUTPUT", NULL, "ADC4_MIXER"},
  2772. {"ADC4_MIXER", "Switch", "ADC4 REQ"},
  2773. {"ADC4 REQ", NULL, "ADC4"},
  2774. {"ADC4", NULL, "ADC4 MUX"},
  2775. {"ADC4 MUX", "INP5", "AMIC5"},
  2776. {"ADC4 MUX", "INP7", "AMIC7"},
  2777. {"WCD_TX_OUTPUT", NULL, "DMIC1_MIXER"},
  2778. {"DMIC1_MIXER", "Switch", "DMIC1"},
  2779. {"WCD_TX_OUTPUT", NULL, "DMIC2_MIXER"},
  2780. {"DMIC2_MIXER", "Switch", "DMIC2"},
  2781. {"WCD_TX_OUTPUT", NULL, "DMIC3_MIXER"},
  2782. {"DMIC3_MIXER", "Switch", "DMIC3"},
  2783. {"WCD_TX_OUTPUT", NULL, "DMIC4_MIXER"},
  2784. {"DMIC4_MIXER", "Switch", "DMIC4"},
  2785. {"WCD_TX_OUTPUT", NULL, "DMIC5_MIXER"},
  2786. {"DMIC5_MIXER", "Switch", "DMIC5"},
  2787. {"WCD_TX_OUTPUT", NULL, "DMIC6_MIXER"},
  2788. {"DMIC6_MIXER", "Switch", "DMIC6"},
  2789. {"WCD_TX_OUTPUT", NULL, "DMIC7_MIXER"},
  2790. {"DMIC7_MIXER", "Switch", "DMIC7"},
  2791. {"WCD_TX_OUTPUT", NULL, "DMIC8_MIXER"},
  2792. {"DMIC8_MIXER", "Switch", "DMIC8"},
  2793. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  2794. {"RX1", NULL, "IN1_HPHL"},
  2795. {"RDAC1", NULL, "RX1"},
  2796. {"HPHL_RDAC", "Switch", "RDAC1"},
  2797. {"HPHL PGA", NULL, "HPHL_RDAC"},
  2798. {"HPHL", NULL, "HPHL PGA"},
  2799. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  2800. {"RX2", NULL, "IN2_HPHR"},
  2801. {"RDAC2", NULL, "RX2"},
  2802. {"HPHR_RDAC", "Switch", "RDAC2"},
  2803. {"HPHR PGA", NULL, "HPHR_RDAC"},
  2804. {"HPHR", NULL, "HPHR PGA"},
  2805. {"IN3_AUX", NULL, "CLS_H_PORT"},
  2806. {"RX3", NULL, "IN3_AUX"},
  2807. {"RDAC4", NULL, "RX3"},
  2808. {"AUX_RDAC", "Switch", "RDAC4"},
  2809. {"AUX PGA", NULL, "AUX_RDAC"},
  2810. {"AUX", NULL, "AUX PGA"},
  2811. {"RDAC3_MUX", "RX3", "RX3"},
  2812. {"RDAC3_MUX", "RX1", "RX1"},
  2813. {"RDAC3", NULL, "RDAC3_MUX"},
  2814. {"EAR_RDAC", "Switch", "RDAC3"},
  2815. {"EAR PGA", NULL, "EAR_RDAC"},
  2816. {"EAR", NULL, "EAR PGA"},
  2817. };
  2818. static ssize_t wcd938x_version_read(struct snd_info_entry *entry,
  2819. void *file_private_data,
  2820. struct file *file,
  2821. char __user *buf, size_t count,
  2822. loff_t pos)
  2823. {
  2824. struct wcd938x_priv *priv;
  2825. char buffer[WCD938X_VERSION_ENTRY_SIZE];
  2826. int len = 0;
  2827. priv = (struct wcd938x_priv *) entry->private_data;
  2828. if (!priv) {
  2829. pr_err("%s: wcd938x priv is null\n", __func__);
  2830. return -EINVAL;
  2831. }
  2832. switch (priv->version) {
  2833. case WCD938X_VERSION_1_0:
  2834. len = snprintf(buffer, sizeof(buffer), "WCD938X_1_0\n");
  2835. break;
  2836. default:
  2837. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2838. }
  2839. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2840. }
  2841. static struct snd_info_entry_ops wcd938x_info_ops = {
  2842. .read = wcd938x_version_read,
  2843. };
  2844. static ssize_t wcd938x_variant_read(struct snd_info_entry *entry,
  2845. void *file_private_data,
  2846. struct file *file,
  2847. char __user *buf, size_t count,
  2848. loff_t pos)
  2849. {
  2850. struct wcd938x_priv *priv;
  2851. char buffer[WCD938X_VARIANT_ENTRY_SIZE];
  2852. int len = 0;
  2853. priv = (struct wcd938x_priv *) entry->private_data;
  2854. if (!priv) {
  2855. pr_err("%s: wcd938x priv is null\n", __func__);
  2856. return -EINVAL;
  2857. }
  2858. switch (priv->variant) {
  2859. case WCD9380:
  2860. len = snprintf(buffer, sizeof(buffer), "WCD9380\n");
  2861. break;
  2862. case WCD9385:
  2863. len = snprintf(buffer, sizeof(buffer), "WCD9385\n");
  2864. break;
  2865. default:
  2866. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2867. }
  2868. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2869. }
  2870. static struct snd_info_entry_ops wcd938x_variant_ops = {
  2871. .read = wcd938x_variant_read,
  2872. };
  2873. /*
  2874. * wcd938x_get_codec_variant
  2875. * @component: component instance
  2876. *
  2877. * Return: codec variant or -EINVAL in error.
  2878. */
  2879. int wcd938x_get_codec_variant(struct snd_soc_component *component)
  2880. {
  2881. struct wcd938x_priv *priv = NULL;
  2882. if (!component)
  2883. return -EINVAL;
  2884. priv = snd_soc_component_get_drvdata(component);
  2885. if (!priv) {
  2886. dev_err(component->dev,
  2887. "%s:wcd938x not probed\n", __func__);
  2888. return 0;
  2889. }
  2890. return priv->variant;
  2891. }
  2892. EXPORT_SYMBOL(wcd938x_get_codec_variant);
  2893. /*
  2894. * wcd938x_info_create_codec_entry - creates wcd938x module
  2895. * @codec_root: The parent directory
  2896. * @component: component instance
  2897. *
  2898. * Creates wcd938x module, variant and version entry under the given
  2899. * parent directory.
  2900. *
  2901. * Return: 0 on success or negative error code on failure.
  2902. */
  2903. int wcd938x_info_create_codec_entry(struct snd_info_entry *codec_root,
  2904. struct snd_soc_component *component)
  2905. {
  2906. struct snd_info_entry *version_entry;
  2907. struct snd_info_entry *variant_entry;
  2908. struct wcd938x_priv *priv;
  2909. struct snd_soc_card *card;
  2910. if (!codec_root || !component)
  2911. return -EINVAL;
  2912. priv = snd_soc_component_get_drvdata(component);
  2913. if (priv->entry) {
  2914. dev_dbg(priv->dev,
  2915. "%s:wcd938x module already created\n", __func__);
  2916. return 0;
  2917. }
  2918. card = component->card;
  2919. priv->entry = snd_info_create_module_entry(codec_root->module,
  2920. "wcd938x", codec_root);
  2921. if (!priv->entry) {
  2922. dev_dbg(component->dev, "%s: failed to create wcd938x entry\n",
  2923. __func__);
  2924. return -ENOMEM;
  2925. }
  2926. priv->entry->mode = S_IFDIR | 0555;
  2927. if (snd_info_register(priv->entry) < 0) {
  2928. snd_info_free_entry(priv->entry);
  2929. return -ENOMEM;
  2930. }
  2931. version_entry = snd_info_create_card_entry(card->snd_card,
  2932. "version",
  2933. priv->entry);
  2934. if (!version_entry) {
  2935. dev_dbg(component->dev, "%s: failed to create wcd938x version entry\n",
  2936. __func__);
  2937. snd_info_free_entry(priv->entry);
  2938. return -ENOMEM;
  2939. }
  2940. version_entry->private_data = priv;
  2941. version_entry->size = WCD938X_VERSION_ENTRY_SIZE;
  2942. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  2943. version_entry->c.ops = &wcd938x_info_ops;
  2944. if (snd_info_register(version_entry) < 0) {
  2945. snd_info_free_entry(version_entry);
  2946. snd_info_free_entry(priv->entry);
  2947. return -ENOMEM;
  2948. }
  2949. priv->version_entry = version_entry;
  2950. variant_entry = snd_info_create_card_entry(card->snd_card,
  2951. "variant",
  2952. priv->entry);
  2953. if (!variant_entry) {
  2954. dev_dbg(component->dev, "%s: failed to create wcd938x variant entry\n",
  2955. __func__);
  2956. snd_info_free_entry(version_entry);
  2957. snd_info_free_entry(priv->entry);
  2958. return -ENOMEM;
  2959. }
  2960. variant_entry->private_data = priv;
  2961. variant_entry->size = WCD938X_VARIANT_ENTRY_SIZE;
  2962. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  2963. variant_entry->c.ops = &wcd938x_variant_ops;
  2964. if (snd_info_register(variant_entry) < 0) {
  2965. snd_info_free_entry(variant_entry);
  2966. snd_info_free_entry(version_entry);
  2967. snd_info_free_entry(priv->entry);
  2968. return -ENOMEM;
  2969. }
  2970. priv->variant_entry = variant_entry;
  2971. return 0;
  2972. }
  2973. EXPORT_SYMBOL(wcd938x_info_create_codec_entry);
  2974. static int wcd938x_set_micbias_data(struct wcd938x_priv *wcd938x,
  2975. struct wcd938x_pdata *pdata)
  2976. {
  2977. int vout_ctl_1 = 0, vout_ctl_2 = 0, vout_ctl_3 = 0, vout_ctl_4 = 0;
  2978. int rc = 0;
  2979. if (!pdata) {
  2980. dev_err(wcd938x->dev, "%s: NULL pdata\n", __func__);
  2981. return -ENODEV;
  2982. }
  2983. /* set micbias voltage */
  2984. vout_ctl_1 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb1_mv);
  2985. vout_ctl_2 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb2_mv);
  2986. vout_ctl_3 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb3_mv);
  2987. vout_ctl_4 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb4_mv);
  2988. if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0 ||
  2989. vout_ctl_4 < 0) {
  2990. rc = -EINVAL;
  2991. goto done;
  2992. }
  2993. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB1, 0x3F,
  2994. vout_ctl_1);
  2995. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB2, 0x3F,
  2996. vout_ctl_2);
  2997. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB3, 0x3F,
  2998. vout_ctl_3);
  2999. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB4, 0x3F,
  3000. vout_ctl_4);
  3001. done:
  3002. return rc;
  3003. }
  3004. static int wcd938x_soc_codec_probe(struct snd_soc_component *component)
  3005. {
  3006. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  3007. struct snd_soc_dapm_context *dapm =
  3008. snd_soc_component_get_dapm(component);
  3009. int variant;
  3010. int ret = -EINVAL;
  3011. dev_info(component->dev, "%s()\n", __func__);
  3012. wcd938x = snd_soc_component_get_drvdata(component);
  3013. if (!wcd938x)
  3014. return -EINVAL;
  3015. wcd938x->component = component;
  3016. snd_soc_component_init_regmap(component, wcd938x->regmap);
  3017. variant = (snd_soc_component_read32(component,
  3018. WCD938X_DIGITAL_EFUSE_REG_0) & 0x1E) >> 1;
  3019. wcd938x->variant = variant;
  3020. wcd938x->fw_data = devm_kzalloc(component->dev,
  3021. sizeof(*(wcd938x->fw_data)),
  3022. GFP_KERNEL);
  3023. if (!wcd938x->fw_data) {
  3024. dev_err(component->dev, "Failed to allocate fw_data\n");
  3025. ret = -ENOMEM;
  3026. goto err;
  3027. }
  3028. set_bit(WCD9XXX_MBHC_CAL, wcd938x->fw_data->cal_bit);
  3029. ret = wcd_cal_create_hwdep(wcd938x->fw_data,
  3030. WCD9XXX_CODEC_HWDEP_NODE, component);
  3031. if (ret < 0) {
  3032. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  3033. goto err_hwdep;
  3034. }
  3035. ret = wcd938x_mbhc_init(&wcd938x->mbhc, component, wcd938x->fw_data);
  3036. if (ret) {
  3037. pr_err("%s: mbhc initialization failed\n", __func__);
  3038. goto err_hwdep;
  3039. }
  3040. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  3041. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  3042. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  3043. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  3044. snd_soc_dapm_ignore_suspend(dapm, "AMIC5");
  3045. snd_soc_dapm_ignore_suspend(dapm, "AMIC6");
  3046. snd_soc_dapm_ignore_suspend(dapm, "AMIC7");
  3047. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_OUTPUT");
  3048. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  3049. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  3050. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  3051. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  3052. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  3053. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  3054. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  3055. snd_soc_dapm_sync(dapm);
  3056. wcd_cls_h_init(&wcd938x->clsh_info);
  3057. wcd938x_init_reg(component);
  3058. if (wcd938x->variant == WCD9380) {
  3059. ret = snd_soc_add_component_controls(component, wcd9380_snd_controls,
  3060. ARRAY_SIZE(wcd9380_snd_controls));
  3061. if (ret < 0) {
  3062. dev_err(component->dev,
  3063. "%s: Failed to add snd ctrls for variant: %d\n",
  3064. __func__, wcd938x->variant);
  3065. goto err_hwdep;
  3066. }
  3067. }
  3068. if (wcd938x->variant == WCD9385) {
  3069. ret = snd_soc_add_component_controls(component, wcd9385_snd_controls,
  3070. ARRAY_SIZE(wcd9385_snd_controls));
  3071. if (ret < 0) {
  3072. dev_err(component->dev,
  3073. "%s: Failed to add snd ctrls for variant: %d\n",
  3074. __func__, wcd938x->variant);
  3075. goto err_hwdep;
  3076. }
  3077. }
  3078. wcd938x->version = WCD938X_VERSION_1_0;
  3079. /* Register event notifier */
  3080. wcd938x->nblock.notifier_call = wcd938x_event_notify;
  3081. if (wcd938x->register_notifier) {
  3082. ret = wcd938x->register_notifier(wcd938x->handle,
  3083. &wcd938x->nblock,
  3084. true);
  3085. if (ret) {
  3086. dev_err(component->dev,
  3087. "%s: Failed to register notifier %d\n",
  3088. __func__, ret);
  3089. return ret;
  3090. }
  3091. }
  3092. wcd938x->dev_up = true;
  3093. return ret;
  3094. err_hwdep:
  3095. wcd938x->fw_data = NULL;
  3096. err:
  3097. return ret;
  3098. }
  3099. static void wcd938x_soc_codec_remove(struct snd_soc_component *component)
  3100. {
  3101. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  3102. if (!wcd938x) {
  3103. dev_err(component->dev, "%s: wcd938x is already NULL\n",
  3104. __func__);
  3105. return;
  3106. }
  3107. if (wcd938x->register_notifier)
  3108. wcd938x->register_notifier(wcd938x->handle,
  3109. &wcd938x->nblock,
  3110. false);
  3111. }
  3112. static struct snd_soc_component_driver soc_codec_dev_wcd938x = {
  3113. .name = WCD938X_DRV_NAME,
  3114. .probe = wcd938x_soc_codec_probe,
  3115. .remove = wcd938x_soc_codec_remove,
  3116. .controls = wcd938x_snd_controls,
  3117. .num_controls = ARRAY_SIZE(wcd938x_snd_controls),
  3118. .dapm_widgets = wcd938x_dapm_widgets,
  3119. .num_dapm_widgets = ARRAY_SIZE(wcd938x_dapm_widgets),
  3120. .dapm_routes = wcd938x_audio_map,
  3121. .num_dapm_routes = ARRAY_SIZE(wcd938x_audio_map),
  3122. };
  3123. static int wcd938x_reset(struct device *dev)
  3124. {
  3125. struct wcd938x_priv *wcd938x = NULL;
  3126. int rc = 0;
  3127. int value = 0;
  3128. if (!dev)
  3129. return -ENODEV;
  3130. wcd938x = dev_get_drvdata(dev);
  3131. if (!wcd938x)
  3132. return -EINVAL;
  3133. if (!wcd938x->rst_np) {
  3134. dev_err(dev, "%s: reset gpio device node not specified\n",
  3135. __func__);
  3136. return -EINVAL;
  3137. }
  3138. value = msm_cdc_pinctrl_get_state(wcd938x->rst_np);
  3139. if (value > 0)
  3140. return 0;
  3141. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  3142. if (rc) {
  3143. dev_err(dev, "%s: wcd sleep state request fail!\n",
  3144. __func__);
  3145. return rc;
  3146. }
  3147. /* 20us sleep required after pulling the reset gpio to LOW */
  3148. usleep_range(20, 30);
  3149. rc = msm_cdc_pinctrl_select_active_state(wcd938x->rst_np);
  3150. if (rc) {
  3151. dev_err(dev, "%s: wcd active state request fail!\n",
  3152. __func__);
  3153. return rc;
  3154. }
  3155. /* 20us sleep required after pulling the reset gpio to HIGH */
  3156. usleep_range(20, 30);
  3157. return rc;
  3158. }
  3159. static int wcd938x_read_of_property_u32(struct device *dev, const char *name,
  3160. u32 *val)
  3161. {
  3162. int rc = 0;
  3163. rc = of_property_read_u32(dev->of_node, name, val);
  3164. if (rc)
  3165. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  3166. __func__, name, dev->of_node->full_name);
  3167. return rc;
  3168. }
  3169. static void wcd938x_dt_parse_micbias_info(struct device *dev,
  3170. struct wcd938x_micbias_setting *mb)
  3171. {
  3172. u32 prop_val = 0;
  3173. int rc = 0;
  3174. /* MB1 */
  3175. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  3176. NULL)) {
  3177. rc = wcd938x_read_of_property_u32(dev,
  3178. "qcom,cdc-micbias1-mv",
  3179. &prop_val);
  3180. if (!rc)
  3181. mb->micb1_mv = prop_val;
  3182. } else {
  3183. dev_info(dev, "%s: Micbias1 DT property not found\n",
  3184. __func__);
  3185. }
  3186. /* MB2 */
  3187. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  3188. NULL)) {
  3189. rc = wcd938x_read_of_property_u32(dev,
  3190. "qcom,cdc-micbias2-mv",
  3191. &prop_val);
  3192. if (!rc)
  3193. mb->micb2_mv = prop_val;
  3194. } else {
  3195. dev_info(dev, "%s: Micbias2 DT property not found\n",
  3196. __func__);
  3197. }
  3198. /* MB3 */
  3199. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  3200. NULL)) {
  3201. rc = wcd938x_read_of_property_u32(dev,
  3202. "qcom,cdc-micbias3-mv",
  3203. &prop_val);
  3204. if (!rc)
  3205. mb->micb3_mv = prop_val;
  3206. } else {
  3207. dev_info(dev, "%s: Micbias3 DT property not found\n",
  3208. __func__);
  3209. }
  3210. /* MB4 */
  3211. if (of_find_property(dev->of_node, "qcom,cdc-micbias4-mv",
  3212. NULL)) {
  3213. rc = wcd938x_read_of_property_u32(dev,
  3214. "qcom,cdc-micbias4-mv",
  3215. &prop_val);
  3216. if (!rc)
  3217. mb->micb4_mv = prop_val;
  3218. } else {
  3219. dev_info(dev, "%s: Micbias4 DT property not found\n",
  3220. __func__);
  3221. }
  3222. }
  3223. static int wcd938x_reset_low(struct device *dev)
  3224. {
  3225. struct wcd938x_priv *wcd938x = NULL;
  3226. int rc = 0;
  3227. if (!dev)
  3228. return -ENODEV;
  3229. wcd938x = dev_get_drvdata(dev);
  3230. if (!wcd938x)
  3231. return -EINVAL;
  3232. if (!wcd938x->rst_np) {
  3233. dev_err(dev, "%s: reset gpio device node not specified\n",
  3234. __func__);
  3235. return -EINVAL;
  3236. }
  3237. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  3238. if (rc) {
  3239. dev_err(dev, "%s: wcd sleep state request fail!\n",
  3240. __func__);
  3241. return rc;
  3242. }
  3243. /* 20us sleep required after pulling the reset gpio to LOW */
  3244. usleep_range(20, 30);
  3245. return rc;
  3246. }
  3247. struct wcd938x_pdata *wcd938x_populate_dt_data(struct device *dev)
  3248. {
  3249. struct wcd938x_pdata *pdata = NULL;
  3250. pdata = devm_kzalloc(dev, sizeof(struct wcd938x_pdata),
  3251. GFP_KERNEL);
  3252. if (!pdata)
  3253. return NULL;
  3254. pdata->rst_np = of_parse_phandle(dev->of_node,
  3255. "qcom,wcd-rst-gpio-node", 0);
  3256. if (!pdata->rst_np) {
  3257. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  3258. __func__, "qcom,wcd-rst-gpio-node",
  3259. dev->of_node->full_name);
  3260. return NULL;
  3261. }
  3262. /* Parse power supplies */
  3263. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  3264. &pdata->num_supplies);
  3265. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  3266. dev_err(dev, "%s: no power supplies defined for codec\n",
  3267. __func__);
  3268. return NULL;
  3269. }
  3270. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  3271. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  3272. wcd938x_dt_parse_micbias_info(dev, &pdata->micbias);
  3273. return pdata;
  3274. }
  3275. static irqreturn_t wcd938x_wd_handle_irq(int irq, void *data)
  3276. {
  3277. pr_err_ratelimited("%s: Watchdog interrupt for irq =%d triggered\n",
  3278. __func__, irq);
  3279. return IRQ_HANDLED;
  3280. }
  3281. static int wcd938x_bind(struct device *dev)
  3282. {
  3283. int ret = 0, i = 0;
  3284. struct wcd938x_pdata *pdata = dev_get_platdata(dev);
  3285. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  3286. /*
  3287. * Add 5msec delay to provide sufficient time for
  3288. * soundwire auto enumeration of slave devices as
  3289. * as per HW requirement.
  3290. */
  3291. usleep_range(5000, 5010);
  3292. ret = component_bind_all(dev, wcd938x);
  3293. if (ret) {
  3294. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  3295. __func__, ret);
  3296. return ret;
  3297. }
  3298. wcd938x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  3299. if (!wcd938x->rx_swr_dev) {
  3300. dev_err(dev, "%s: Could not find RX swr slave device\n",
  3301. __func__);
  3302. ret = -ENODEV;
  3303. goto err;
  3304. }
  3305. wcd938x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  3306. if (!wcd938x->tx_swr_dev) {
  3307. dev_err(dev, "%s: Could not find TX swr slave device\n",
  3308. __func__);
  3309. ret = -ENODEV;
  3310. goto err;
  3311. }
  3312. wcd938x->regmap = devm_regmap_init_swr(wcd938x->tx_swr_dev,
  3313. &wcd938x_regmap_config);
  3314. if (!wcd938x->regmap) {
  3315. dev_err(dev, "%s: Regmap init failed\n",
  3316. __func__);
  3317. goto err;
  3318. }
  3319. /* Set all interupts as edge triggered */
  3320. for (i = 0; i < wcd938x_regmap_irq_chip.num_regs; i++)
  3321. regmap_write(wcd938x->regmap,
  3322. (WCD938X_DIGITAL_INTR_LEVEL_0 + i), 0);
  3323. wcd938x_regmap_irq_chip.irq_drv_data = wcd938x;
  3324. wcd938x->irq_info.wcd_regmap_irq_chip = &wcd938x_regmap_irq_chip;
  3325. wcd938x->irq_info.codec_name = "WCD938X";
  3326. wcd938x->irq_info.regmap = wcd938x->regmap;
  3327. wcd938x->irq_info.dev = dev;
  3328. ret = wcd_irq_init(&wcd938x->irq_info, &wcd938x->virq);
  3329. if (ret) {
  3330. dev_err(wcd938x->dev, "%s: IRQ init failed: %d\n",
  3331. __func__, ret);
  3332. goto err;
  3333. }
  3334. wcd938x->tx_swr_dev->slave_irq = wcd938x->virq;
  3335. ret = wcd938x_set_micbias_data(wcd938x, pdata);
  3336. if (ret < 0) {
  3337. dev_err(dev, "%s: bad micbias pdata\n", __func__);
  3338. goto err_irq;
  3339. }
  3340. /* Request for watchdog interrupt */
  3341. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT,
  3342. "HPHR PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3343. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT,
  3344. "HPHL PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3345. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT,
  3346. "AUX PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3347. /* Disable watchdog interrupt for HPH and AUX */
  3348. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT);
  3349. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT);
  3350. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT);
  3351. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd938x,
  3352. NULL, 0);
  3353. if (ret) {
  3354. dev_err(dev, "%s: Codec registration failed\n",
  3355. __func__);
  3356. goto err_irq;
  3357. }
  3358. return ret;
  3359. err_irq:
  3360. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  3361. err:
  3362. component_unbind_all(dev, wcd938x);
  3363. return ret;
  3364. }
  3365. static void wcd938x_unbind(struct device *dev)
  3366. {
  3367. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  3368. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT, NULL);
  3369. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT, NULL);
  3370. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT, NULL);
  3371. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  3372. snd_soc_unregister_component(dev);
  3373. component_unbind_all(dev, wcd938x);
  3374. }
  3375. static const struct of_device_id wcd938x_dt_match[] = {
  3376. { .compatible = "qcom,wcd938x-codec" },
  3377. {}
  3378. };
  3379. static const struct component_master_ops wcd938x_comp_ops = {
  3380. .bind = wcd938x_bind,
  3381. .unbind = wcd938x_unbind,
  3382. };
  3383. static int wcd938x_compare_of(struct device *dev, void *data)
  3384. {
  3385. return dev->of_node == data;
  3386. }
  3387. static void wcd938x_release_of(struct device *dev, void *data)
  3388. {
  3389. of_node_put(data);
  3390. }
  3391. static int wcd938x_add_slave_components(struct device *dev,
  3392. struct component_match **matchptr)
  3393. {
  3394. struct device_node *np, *rx_node, *tx_node;
  3395. np = dev->of_node;
  3396. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  3397. if (!rx_node) {
  3398. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  3399. return -ENODEV;
  3400. }
  3401. of_node_get(rx_node);
  3402. component_match_add_release(dev, matchptr,
  3403. wcd938x_release_of,
  3404. wcd938x_compare_of,
  3405. rx_node);
  3406. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  3407. if (!tx_node) {
  3408. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  3409. return -ENODEV;
  3410. }
  3411. of_node_get(tx_node);
  3412. component_match_add_release(dev, matchptr,
  3413. wcd938x_release_of,
  3414. wcd938x_compare_of,
  3415. tx_node);
  3416. return 0;
  3417. }
  3418. static int wcd938x_probe(struct platform_device *pdev)
  3419. {
  3420. struct component_match *match = NULL;
  3421. struct wcd938x_priv *wcd938x = NULL;
  3422. struct wcd938x_pdata *pdata = NULL;
  3423. struct wcd_ctrl_platform_data *plat_data = NULL;
  3424. struct device *dev = &pdev->dev;
  3425. int ret;
  3426. wcd938x = devm_kzalloc(dev, sizeof(struct wcd938x_priv),
  3427. GFP_KERNEL);
  3428. if (!wcd938x)
  3429. return -ENOMEM;
  3430. dev_set_drvdata(dev, wcd938x);
  3431. wcd938x->dev = dev;
  3432. pdata = wcd938x_populate_dt_data(dev);
  3433. if (!pdata) {
  3434. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  3435. return -EINVAL;
  3436. }
  3437. dev->platform_data = pdata;
  3438. wcd938x->rst_np = pdata->rst_np;
  3439. ret = msm_cdc_init_supplies(dev, &wcd938x->supplies,
  3440. pdata->regulator, pdata->num_supplies);
  3441. if (!wcd938x->supplies) {
  3442. dev_err(dev, "%s: Cannot init wcd supplies\n",
  3443. __func__);
  3444. return ret;
  3445. }
  3446. plat_data = dev_get_platdata(dev->parent);
  3447. if (!plat_data) {
  3448. dev_err(dev, "%s: platform data from parent is NULL\n",
  3449. __func__);
  3450. return -EINVAL;
  3451. }
  3452. wcd938x->handle = (void *)plat_data->handle;
  3453. if (!wcd938x->handle) {
  3454. dev_err(dev, "%s: handle is NULL\n", __func__);
  3455. return -EINVAL;
  3456. }
  3457. wcd938x->update_wcd_event = plat_data->update_wcd_event;
  3458. if (!wcd938x->update_wcd_event) {
  3459. dev_err(dev, "%s: update_wcd_event api is null!\n",
  3460. __func__);
  3461. return -EINVAL;
  3462. }
  3463. wcd938x->register_notifier = plat_data->register_notifier;
  3464. if (!wcd938x->register_notifier) {
  3465. dev_err(dev, "%s: register_notifier api is null!\n",
  3466. __func__);
  3467. return -EINVAL;
  3468. }
  3469. ret = msm_cdc_enable_static_supplies(&pdev->dev, wcd938x->supplies,
  3470. pdata->regulator,
  3471. pdata->num_supplies);
  3472. if (ret) {
  3473. dev_err(dev, "%s: wcd static supply enable failed!\n",
  3474. __func__);
  3475. return ret;
  3476. }
  3477. ret = wcd938x_parse_port_mapping(dev, "qcom,rx_swr_ch_map",
  3478. CODEC_RX);
  3479. ret |= wcd938x_parse_port_mapping(dev, "qcom,tx_swr_ch_map",
  3480. CODEC_TX);
  3481. if (ret) {
  3482. dev_err(dev, "Failed to read port mapping\n");
  3483. goto err;
  3484. }
  3485. mutex_init(&wcd938x->wakeup_lock);
  3486. mutex_init(&wcd938x->micb_lock);
  3487. ret = wcd938x_add_slave_components(dev, &match);
  3488. if (ret)
  3489. goto err_lock_init;
  3490. wcd938x_reset(dev);
  3491. wcd938x->wakeup = wcd938x_wakeup;
  3492. return component_master_add_with_match(dev,
  3493. &wcd938x_comp_ops, match);
  3494. err_lock_init:
  3495. mutex_destroy(&wcd938x->micb_lock);
  3496. mutex_destroy(&wcd938x->wakeup_lock);
  3497. err:
  3498. return ret;
  3499. }
  3500. static int wcd938x_remove(struct platform_device *pdev)
  3501. {
  3502. struct wcd938x_priv *wcd938x = NULL;
  3503. wcd938x = platform_get_drvdata(pdev);
  3504. component_master_del(&pdev->dev, &wcd938x_comp_ops);
  3505. mutex_destroy(&wcd938x->micb_lock);
  3506. mutex_destroy(&wcd938x->wakeup_lock);
  3507. dev_set_drvdata(&pdev->dev, NULL);
  3508. return 0;
  3509. }
  3510. #ifdef CONFIG_PM_SLEEP
  3511. static int wcd938x_suspend(struct device *dev)
  3512. {
  3513. return 0;
  3514. }
  3515. static int wcd938x_resume(struct device *dev)
  3516. {
  3517. return 0;
  3518. }
  3519. static const struct dev_pm_ops wcd938x_dev_pm_ops = {
  3520. SET_SYSTEM_SLEEP_PM_OPS(
  3521. wcd938x_suspend,
  3522. wcd938x_resume
  3523. )
  3524. };
  3525. #endif
  3526. static struct platform_driver wcd938x_codec_driver = {
  3527. .probe = wcd938x_probe,
  3528. .remove = wcd938x_remove,
  3529. .driver = {
  3530. .name = "wcd938x_codec",
  3531. .owner = THIS_MODULE,
  3532. .of_match_table = of_match_ptr(wcd938x_dt_match),
  3533. #ifdef CONFIG_PM_SLEEP
  3534. .pm = &wcd938x_dev_pm_ops,
  3535. #endif
  3536. .suppress_bind_attrs = true,
  3537. },
  3538. };
  3539. module_platform_driver(wcd938x_codec_driver);
  3540. MODULE_DESCRIPTION("WCD938X Codec driver");
  3541. MODULE_LICENSE("GPL v2");