wcd938x.c 87 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/slab.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/device.h>
  9. #include <linux/delay.h>
  10. #include <linux/kernel.h>
  11. #include <linux/component.h>
  12. #include <sound/soc.h>
  13. #include <sound/tlv.h>
  14. #include <soc/soundwire.h>
  15. #include <linux/regmap.h>
  16. #include <sound/soc.h>
  17. #include <sound/soc-dapm.h>
  18. #include <asoc/wcdcal-hwdep.h>
  19. #include <asoc/msm-cdc-pinctrl.h>
  20. #include <asoc/msm-cdc-supply.h>
  21. #include <dt-bindings/sound/audio-codec-port-types.h>
  22. #include "internal.h"
  23. #include "wcd938x-registers.h"
  24. #define WCD938X_DRV_NAME "wcd938x_codec"
  25. #define NUM_SWRS_DT_PARAMS 5
  26. #define WCD938X_VERSION_1_0 1
  27. #define WCD938X_VERSION_ENTRY_SIZE 32
  28. #define EAR_RX_PATH_AUX 1
  29. #define ADC_MODE_VAL_HIFI 0x01
  30. #define ADC_MODE_VAL_LO_HIF 0x02
  31. #define ADC_MODE_VAL_NORMAL 0x03
  32. #define ADC_MODE_VAL_LP 0x05
  33. #define ADC_MODE_VAL_ULP1 0x09
  34. #define ADC_MODE_VAL_ULP2 0x0B
  35. enum {
  36. WCD9380 = 0,
  37. WCD9385 = 5,
  38. };
  39. enum {
  40. CODEC_TX = 0,
  41. CODEC_RX,
  42. };
  43. enum {
  44. WCD_ADC1 = 0,
  45. WCD_ADC2,
  46. WCD_ADC3,
  47. WCD_ADC4,
  48. ALLOW_BUCK_DISABLE,
  49. HPH_COMP_DELAY,
  50. HPH_PA_DELAY,
  51. };
  52. enum {
  53. ADC_MODE_INVALID = 0,
  54. ADC_MODE_HIFI,
  55. ADC_MODE_LO_HIF,
  56. ADC_MODE_NORMAL,
  57. ADC_MODE_LP,
  58. ADC_MODE_ULP1,
  59. ADC_MODE_ULP2,
  60. };
  61. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  62. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  63. static int wcd938x_handle_post_irq(void *data);
  64. static int wcd938x_reset(struct device *dev);
  65. static int wcd938x_reset_low(struct device *dev);
  66. static const struct regmap_irq wcd938x_irqs[WCD938X_NUM_IRQS] = {
  67. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  68. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  69. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  70. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  71. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_SW_DET, 0, 0x10),
  72. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_OCP_INT, 0, 0x20),
  73. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_CNP_INT, 0, 0x40),
  74. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_OCP_INT, 0, 0x80),
  75. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_CNP_INT, 1, 0x01),
  76. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_CNP_INT, 1, 0x02),
  77. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_SCD_INT, 1, 0x04),
  78. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_CNP_INT, 1, 0x08),
  79. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_SCD_INT, 1, 0x10),
  80. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  81. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  82. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  83. REGMAP_IRQ_REG(WCD938X_IRQ_LDORT_SCD_INT, 2, 0x01),
  84. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  85. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  86. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  87. };
  88. static struct regmap_irq_chip wcd938x_regmap_irq_chip = {
  89. .name = "wcd938x",
  90. .irqs = wcd938x_irqs,
  91. .num_irqs = ARRAY_SIZE(wcd938x_irqs),
  92. .num_regs = 3,
  93. .status_base = WCD938X_DIGITAL_INTR_STATUS_0,
  94. .mask_base = WCD938X_DIGITAL_INTR_MASK_0,
  95. .type_base = WCD938X_DIGITAL_INTR_LEVEL_0,
  96. .ack_base = WCD938X_DIGITAL_INTR_CLEAR_0,
  97. .use_ack = 1,
  98. .runtime_pm = false,
  99. .handle_post_irq = wcd938x_handle_post_irq,
  100. .irq_drv_data = NULL,
  101. };
  102. static int wcd938x_handle_post_irq(void *data)
  103. {
  104. struct wcd938x_priv *wcd938x = data;
  105. u32 sts1 = 0, sts2 = 0, sts3 = 0;
  106. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_0, &sts1);
  107. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_1, &sts2);
  108. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_2, &sts3);
  109. wcd938x->tx_swr_dev->slave_irq_pending =
  110. ((sts1 || sts2 || sts3) ? true : false);
  111. return IRQ_HANDLED;
  112. }
  113. static int wcd938x_init_reg(struct snd_soc_component *component)
  114. {
  115. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x0E, 0x0E);
  116. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x80, 0x80);
  117. /* 1 msec delay as per HW requirement */
  118. usleep_range(1000, 1010);
  119. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x40, 0x40);
  120. /* 1 msec delay as per HW requirement */
  121. usleep_range(1000, 1010);
  122. snd_soc_component_update_bits(component, WCD938X_LDORXTX_CONFIG,
  123. 0x10, 0x00);
  124. snd_soc_component_update_bits(component, WCD938X_BIAS_VBG_FINE_ADJ,
  125. 0xF0, 0x80);
  126. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x80, 0x80);
  127. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x40);
  128. /* 10 msec delay as per HW requirement */
  129. usleep_range(10000, 10010);
  130. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x00);
  131. snd_soc_component_update_bits(component, WCD938X_HPH_OCP_CTL,
  132. 0xFF, 0x3A);
  133. snd_soc_component_update_bits(component, WCD938X_RX_OCP_CTL,
  134. 0x0F, 0x02);
  135. snd_soc_component_update_bits(component, WCD938X_HPH_R_TEST,
  136. 0x01, 0x01);
  137. snd_soc_component_update_bits(component, WCD938X_HPH_L_TEST,
  138. 0x01, 0x01);
  139. snd_soc_component_update_bits(component,
  140. WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL,
  141. 0xF0, 0x00);
  142. snd_soc_component_update_bits(component,
  143. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW,
  144. 0x1F, 0x15);
  145. snd_soc_component_update_bits(component,
  146. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW,
  147. 0x1F, 0x15);
  148. snd_soc_component_update_bits(component, WCD938X_HPH_REFBUFF_UHQA_CTL,
  149. 0xC0, 0x80);
  150. snd_soc_component_update_bits(component, WCD938X_DIGITAL_CDC_DMIC_CTL,
  151. 0x02, 0x02);
  152. snd_soc_component_update_bits(component,
  153. WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP,
  154. 0xFF, 0x14);
  155. snd_soc_component_update_bits(component,
  156. WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP,
  157. 0x1F, 0x08);
  158. return 0;
  159. }
  160. static int wcd938x_set_port_params(struct snd_soc_component *component,
  161. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  162. u8 *ch_mask, u32 *ch_rate,
  163. u8 *port_type, u8 path)
  164. {
  165. int i, j;
  166. u8 num_ports = 0;
  167. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  168. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  169. switch (path) {
  170. case CODEC_RX:
  171. map = &wcd938x->rx_port_mapping;
  172. num_ports = wcd938x->num_rx_ports;
  173. break;
  174. case CODEC_TX:
  175. map = &wcd938x->tx_port_mapping;
  176. num_ports = wcd938x->num_tx_ports;
  177. break;
  178. default:
  179. dev_err(component->dev, "%s Invalid path selected %u\n",
  180. __func__, path);
  181. return -EINVAL;
  182. }
  183. for (i = 0; i <= num_ports; i++) {
  184. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  185. if ((*map)[i][j].slave_port_type == slv_prt_type)
  186. goto found;
  187. }
  188. }
  189. found:
  190. if (i > num_ports || j == MAX_CH_PER_PORT) {
  191. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  192. __func__, slv_prt_type);
  193. return -EINVAL;
  194. }
  195. *port_id = i;
  196. *num_ch = (*map)[i][j].num_ch;
  197. *ch_mask = (*map)[i][j].ch_mask;
  198. *ch_rate = (*map)[i][j].ch_rate;
  199. *port_type = (*map)[i][j].master_port_type;
  200. return 0;
  201. }
  202. static int wcd938x_parse_port_mapping(struct device *dev,
  203. char *prop, u8 path)
  204. {
  205. u32 *dt_array, map_size, map_length;
  206. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  207. u32 slave_port_type, master_port_type;
  208. u32 i, ch_iter = 0;
  209. int ret = 0;
  210. u8 *num_ports = NULL;
  211. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  212. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  213. switch (path) {
  214. case CODEC_RX:
  215. map = &wcd938x->rx_port_mapping;
  216. num_ports = &wcd938x->num_rx_ports;
  217. break;
  218. case CODEC_TX:
  219. map = &wcd938x->tx_port_mapping;
  220. num_ports = &wcd938x->num_tx_ports;
  221. break;
  222. default:
  223. dev_err(dev, "%s Invalid path selected %u\n",
  224. __func__, path);
  225. return -EINVAL;
  226. }
  227. if (!of_find_property(dev->of_node, prop,
  228. &map_size)) {
  229. dev_err(dev, "missing port mapping prop %s\n", prop);
  230. ret = -EINVAL;
  231. goto err_port_map;
  232. }
  233. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  234. dt_array = kzalloc(map_size, GFP_KERNEL);
  235. if (!dt_array) {
  236. ret = -ENOMEM;
  237. goto err_alloc;
  238. }
  239. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  240. NUM_SWRS_DT_PARAMS * map_length);
  241. if (ret) {
  242. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  243. __func__, prop);
  244. goto err_pdata_fail;
  245. }
  246. for (i = 0; i < map_length; i++) {
  247. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  248. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  249. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  250. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  251. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  252. if (port_num != old_port_num)
  253. ch_iter = 0;
  254. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  255. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  256. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  257. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  258. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  259. old_port_num = port_num;
  260. }
  261. *num_ports = port_num;
  262. kfree(dt_array);
  263. return 0;
  264. err_pdata_fail:
  265. kfree(dt_array);
  266. err_alloc:
  267. err_port_map:
  268. return ret;
  269. }
  270. static int wcd938x_tx_connect_port(struct snd_soc_component *component,
  271. u8 slv_port_type, u8 enable)
  272. {
  273. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  274. u8 port_id, num_ch, ch_mask, port_type;
  275. u32 ch_rate;
  276. u8 num_port = 1;
  277. int ret = 0;
  278. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  279. &num_ch, &ch_mask, &ch_rate,
  280. &port_type, CODEC_TX);
  281. if (ret)
  282. return ret;
  283. if (enable)
  284. ret = swr_connect_port(wcd938x->tx_swr_dev, &port_id,
  285. num_port, &ch_mask, &ch_rate,
  286. &num_ch, &port_type);
  287. else
  288. ret = swr_disconnect_port(wcd938x->tx_swr_dev, &port_id,
  289. num_port, &ch_mask, &port_type);
  290. return ret;
  291. }
  292. static int wcd938x_rx_connect_port(struct snd_soc_component *component,
  293. u8 slv_port_type, u8 enable)
  294. {
  295. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  296. u8 port_id, num_ch, ch_mask, port_type;
  297. u32 ch_rate;
  298. u8 num_port = 1;
  299. int ret = 0;
  300. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  301. &num_ch, &ch_mask, &ch_rate,
  302. &port_type, CODEC_RX);
  303. if (ret)
  304. return ret;
  305. if (enable)
  306. ret = swr_connect_port(wcd938x->rx_swr_dev, &port_id,
  307. num_port, &ch_mask, &ch_rate,
  308. &num_ch, &port_type);
  309. else
  310. ret = swr_disconnect_port(wcd938x->rx_swr_dev, &port_id,
  311. num_port, &ch_mask, &port_type);
  312. return ret;
  313. }
  314. static int wcd938x_rx_clk_enable(struct snd_soc_component *component)
  315. {
  316. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  317. if (wcd938x->rx_clk_cnt == 0) {
  318. snd_soc_component_update_bits(component,
  319. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
  320. snd_soc_component_update_bits(component,
  321. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x01);
  322. snd_soc_component_update_bits(component,
  323. WCD938X_DIGITAL_CDC_RX0_CTL, 0x40, 0x00);
  324. snd_soc_component_update_bits(component,
  325. WCD938X_DIGITAL_CDC_RX1_CTL, 0x40, 0x00);
  326. snd_soc_component_update_bits(component,
  327. WCD938X_DIGITAL_CDC_RX2_CTL, 0x40, 0x00);
  328. snd_soc_component_update_bits(component,
  329. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
  330. snd_soc_component_update_bits(component,
  331. WCD938X_AUX_AUXPA, 0x10, 0x10);
  332. }
  333. wcd938x->rx_clk_cnt++;
  334. return 0;
  335. }
  336. static int wcd938x_rx_clk_disable(struct snd_soc_component *component)
  337. {
  338. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  339. wcd938x->rx_clk_cnt--;
  340. if (wcd938x->rx_clk_cnt == 0) {
  341. snd_soc_component_update_bits(component,
  342. WCD938X_ANA_RX_SUPPLIES, 0x40, 0x00);
  343. snd_soc_component_update_bits(component,
  344. WCD938X_ANA_RX_SUPPLIES, 0x80, 0x00);
  345. snd_soc_component_update_bits(component,
  346. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x00);
  347. snd_soc_component_update_bits(component,
  348. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x00);
  349. snd_soc_component_update_bits(component,
  350. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x00);
  351. }
  352. return 0;
  353. }
  354. /*
  355. * wcd938x_soc_get_mbhc: get wcd938x_mbhc handle of corresponding component
  356. * @component: handle to snd_soc_component *
  357. *
  358. * return wcd938x_mbhc handle or error code in case of failure
  359. */
  360. struct wcd938x_mbhc *wcd938x_soc_get_mbhc(struct snd_soc_component *component)
  361. {
  362. struct wcd938x_priv *wcd938x;
  363. if (!component) {
  364. pr_err("%s: Invalid params, NULL component\n", __func__);
  365. return NULL;
  366. }
  367. wcd938x = snd_soc_component_get_drvdata(component);
  368. if (!wcd938x) {
  369. pr_err("%s: wcd938x is NULL\n", __func__);
  370. return NULL;
  371. }
  372. return wcd938x->mbhc;
  373. }
  374. EXPORT_SYMBOL(wcd938x_soc_get_mbhc);
  375. static int wcd938x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  376. struct snd_kcontrol *kcontrol,
  377. int event)
  378. {
  379. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  380. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  381. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  382. w->name, event);
  383. switch (event) {
  384. case SND_SOC_DAPM_PRE_PMU:
  385. wcd938x_rx_clk_enable(component);
  386. snd_soc_component_update_bits(component,
  387. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  388. snd_soc_component_update_bits(component,
  389. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  390. snd_soc_component_update_bits(component,
  391. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  392. break;
  393. case SND_SOC_DAPM_POST_PMU:
  394. snd_soc_component_update_bits(component,
  395. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x0F, 0x02);
  396. if (wcd938x->comp1_enable) {
  397. snd_soc_component_update_bits(component,
  398. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x02);
  399. /* 5msec compander delay as per HW requirement */
  400. if (!wcd938x->comp2_enable ||
  401. (snd_soc_component_read32(component,
  402. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x01))
  403. usleep_range(5000, 5010);
  404. snd_soc_component_update_bits(component,
  405. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  406. } else {
  407. snd_soc_component_update_bits(component,
  408. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  409. 0x02, 0x00);
  410. snd_soc_component_update_bits(component,
  411. WCD938X_HPH_L_EN, 0x20, 0x20);
  412. }
  413. break;
  414. case SND_SOC_DAPM_POST_PMD:
  415. snd_soc_component_update_bits(component,
  416. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  417. 0x0F, 0x01);
  418. break;
  419. }
  420. return 0;
  421. }
  422. static int wcd938x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  423. struct snd_kcontrol *kcontrol,
  424. int event)
  425. {
  426. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  427. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  428. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  429. w->name, event);
  430. switch (event) {
  431. case SND_SOC_DAPM_PRE_PMU:
  432. wcd938x_rx_clk_enable(component);
  433. snd_soc_component_update_bits(component,
  434. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
  435. snd_soc_component_update_bits(component,
  436. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x08, 0x08);
  437. snd_soc_component_update_bits(component,
  438. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  439. break;
  440. case SND_SOC_DAPM_POST_PMU:
  441. snd_soc_component_update_bits(component,
  442. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x0F, 0x02);
  443. if (wcd938x->comp2_enable) {
  444. snd_soc_component_update_bits(component,
  445. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x01, 0x01);
  446. /* 5msec compander delay as per HW requirement */
  447. if (!wcd938x->comp1_enable ||
  448. (snd_soc_component_read32(component,
  449. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x02))
  450. usleep_range(5000, 5010);
  451. snd_soc_component_update_bits(component,
  452. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  453. } else {
  454. snd_soc_component_update_bits(component,
  455. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  456. 0x01, 0x00);
  457. snd_soc_component_update_bits(component,
  458. WCD938X_HPH_R_EN, 0x20, 0x20);
  459. }
  460. break;
  461. case SND_SOC_DAPM_POST_PMD:
  462. snd_soc_component_update_bits(component,
  463. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  464. 0x0F, 0x01);
  465. break;
  466. }
  467. return 0;
  468. }
  469. static int wcd938x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  470. struct snd_kcontrol *kcontrol,
  471. int event)
  472. {
  473. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  474. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  475. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  476. w->name, event);
  477. switch (event) {
  478. case SND_SOC_DAPM_PRE_PMU:
  479. wcd938x_rx_clk_enable(component);
  480. snd_soc_component_update_bits(component,
  481. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  482. snd_soc_component_update_bits(component,
  483. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  484. snd_soc_component_update_bits(component,
  485. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x02);
  486. /* 5 msec delay as per HW requirement */
  487. usleep_range(5000, 5010);
  488. if (wcd938x->flyback_cur_det_disable == 0)
  489. snd_soc_component_update_bits(component,
  490. WCD938X_FLYBACK_EN,
  491. 0x04, 0x00);
  492. wcd938x->flyback_cur_det_disable++;
  493. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  494. WCD_CLSH_EVENT_PRE_DAC,
  495. WCD_CLSH_STATE_EAR,
  496. wcd938x->hph_mode);
  497. break;
  498. case SND_SOC_DAPM_POST_PMD:
  499. break;
  500. };
  501. return 0;
  502. }
  503. static int wcd938x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  504. struct snd_kcontrol *kcontrol,
  505. int event)
  506. {
  507. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  508. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  509. int ret = 0;
  510. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  511. w->name, event);
  512. switch (event) {
  513. case SND_SOC_DAPM_PRE_PMU:
  514. wcd938x_rx_clk_enable(component);
  515. snd_soc_component_update_bits(component,
  516. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x04);
  517. snd_soc_component_update_bits(component,
  518. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x04);
  519. snd_soc_component_update_bits(component,
  520. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x01);
  521. if (wcd938x->flyback_cur_det_disable == 0)
  522. snd_soc_component_update_bits(component,
  523. WCD938X_FLYBACK_EN,
  524. 0x04, 0x00);
  525. wcd938x->flyback_cur_det_disable++;
  526. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  527. WCD_CLSH_EVENT_PRE_DAC,
  528. WCD_CLSH_STATE_AUX,
  529. wcd938x->hph_mode);
  530. break;
  531. case SND_SOC_DAPM_POST_PMD:
  532. snd_soc_component_update_bits(component,
  533. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x00);
  534. break;
  535. };
  536. return ret;
  537. }
  538. static int wcd938x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  539. struct snd_kcontrol *kcontrol,
  540. int event)
  541. {
  542. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  543. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  544. int ret = 0;
  545. int hph_mode = wcd938x->hph_mode;
  546. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  547. w->name, event);
  548. switch (event) {
  549. case SND_SOC_DAPM_PRE_PMU:
  550. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  551. wcd938x->rx_swr_dev->dev_num,
  552. true);
  553. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  554. WCD_CLSH_EVENT_PRE_DAC,
  555. WCD_CLSH_STATE_HPHR,
  556. hph_mode);
  557. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  558. 0x10, 0x10);
  559. /* 100 usec delay as per HW requirement */
  560. usleep_range(100, 110);
  561. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  562. snd_soc_component_update_bits(component,
  563. WCD938X_DIGITAL_PDM_WD_CTL1, 0x17, 0x13);
  564. break;
  565. case SND_SOC_DAPM_POST_PMU:
  566. /*
  567. * 7ms sleep is required if compander is enabled as per
  568. * HW requirement. If compander is disabled, then
  569. * 20ms delay is required.
  570. */
  571. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  572. if (!wcd938x->comp2_enable)
  573. usleep_range(20000, 20100);
  574. else
  575. usleep_range(7000, 7100);
  576. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  577. }
  578. snd_soc_component_update_bits(component,
  579. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  580. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  581. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  582. snd_soc_component_update_bits(component,
  583. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  584. if (wcd938x->update_wcd_event)
  585. wcd938x->update_wcd_event(wcd938x->handle,
  586. WCD_BOLERO_EVT_RX_MUTE,
  587. (WCD_RX2 << 0x10));
  588. break;
  589. case SND_SOC_DAPM_PRE_PMD:
  590. if (wcd938x->update_wcd_event)
  591. wcd938x->update_wcd_event(wcd938x->handle,
  592. WCD_BOLERO_EVT_RX_MUTE,
  593. (WCD_RX2 << 0x10 | 0x1));
  594. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  595. WCD_EVENT_PRE_HPHR_PA_OFF,
  596. &wcd938x->mbhc->wcd_mbhc);
  597. break;
  598. case SND_SOC_DAPM_POST_PMD:
  599. /* 7 msec delay as per HW requirement */
  600. usleep_range(7000, 7010);
  601. snd_soc_component_update_bits(component,
  602. WCD938X_DIGITAL_PDM_WD_CTL1, 0x17, 0x00);
  603. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  604. WCD_EVENT_POST_HPHR_PA_OFF,
  605. &wcd938x->mbhc->wcd_mbhc);
  606. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  607. 0x10, 0x00);
  608. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  609. WCD_CLSH_EVENT_POST_PA,
  610. WCD_CLSH_STATE_HPHR,
  611. hph_mode);
  612. break;
  613. };
  614. return ret;
  615. }
  616. static int wcd938x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  617. struct snd_kcontrol *kcontrol,
  618. int event)
  619. {
  620. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  621. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  622. int ret = 0;
  623. int hph_mode = wcd938x->hph_mode;
  624. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  625. w->name, event);
  626. switch (event) {
  627. case SND_SOC_DAPM_PRE_PMU:
  628. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  629. wcd938x->rx_swr_dev->dev_num,
  630. true);
  631. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  632. WCD_CLSH_EVENT_PRE_DAC,
  633. WCD_CLSH_STATE_HPHL,
  634. hph_mode);
  635. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  636. 0x20, 0x20);
  637. /* 100 usec delay as per HW requirement */
  638. usleep_range(100, 110);
  639. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  640. snd_soc_component_update_bits(component,
  641. WCD938X_DIGITAL_PDM_WD_CTL0, 0x17, 0x13);
  642. break;
  643. case SND_SOC_DAPM_POST_PMU:
  644. /*
  645. * 7ms sleep is required if compander is enabled as per
  646. * HW requirement. If compander is disabled, then
  647. * 20ms delay is required.
  648. */
  649. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  650. if (!wcd938x->comp1_enable)
  651. usleep_range(20000, 20100);
  652. else
  653. usleep_range(7000, 7100);
  654. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  655. }
  656. snd_soc_component_update_bits(component,
  657. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  658. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  659. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  660. snd_soc_component_update_bits(component,
  661. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  662. if (wcd938x->update_wcd_event)
  663. wcd938x->update_wcd_event(wcd938x->handle,
  664. WCD_BOLERO_EVT_RX_MUTE,
  665. (WCD_RX1 << 0x10));
  666. break;
  667. case SND_SOC_DAPM_PRE_PMD:
  668. if (wcd938x->update_wcd_event)
  669. wcd938x->update_wcd_event(wcd938x->handle,
  670. WCD_BOLERO_EVT_RX_MUTE,
  671. (WCD_RX1 << 0x10 | 0x1));
  672. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  673. WCD_EVENT_PRE_HPHL_PA_OFF,
  674. &wcd938x->mbhc->wcd_mbhc);
  675. break;
  676. case SND_SOC_DAPM_POST_PMD:
  677. /* 7 msec delay as per HW requirement */
  678. usleep_range(7000, 7010);
  679. snd_soc_component_update_bits(component,
  680. WCD938X_DIGITAL_PDM_WD_CTL0, 0x17, 0x00);
  681. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  682. WCD_EVENT_POST_HPHL_PA_OFF,
  683. &wcd938x->mbhc->wcd_mbhc);
  684. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  685. 0x20, 0x00);
  686. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  687. WCD_CLSH_EVENT_POST_PA,
  688. WCD_CLSH_STATE_HPHL,
  689. hph_mode);
  690. break;
  691. };
  692. return ret;
  693. }
  694. static int wcd938x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  695. struct snd_kcontrol *kcontrol,
  696. int event)
  697. {
  698. struct snd_soc_component *component =
  699. snd_soc_dapm_to_component(w->dapm);
  700. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  701. int hph_mode = wcd938x->hph_mode;
  702. int ret = 0;
  703. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  704. w->name, event);
  705. switch (event) {
  706. case SND_SOC_DAPM_PRE_PMU:
  707. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  708. wcd938x->rx_swr_dev->dev_num,
  709. true);
  710. snd_soc_component_update_bits(component,
  711. WCD938X_DIGITAL_PDM_WD_CTL2, 0x05, 0x05);
  712. break;
  713. case SND_SOC_DAPM_POST_PMU:
  714. /* 1 msec delay as per HW requirement */
  715. usleep_range(1000, 1010);
  716. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  717. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  718. snd_soc_component_update_bits(component,
  719. WCD938X_ANA_RX_SUPPLIES,
  720. 0x02, 0x02);
  721. if (wcd938x->update_wcd_event)
  722. wcd938x->update_wcd_event(wcd938x->handle,
  723. WCD_BOLERO_EVT_RX_MUTE,
  724. (WCD_RX3 << 0x10));
  725. break;
  726. case SND_SOC_DAPM_PRE_PMD:
  727. if (wcd938x->update_wcd_event)
  728. wcd938x->update_wcd_event(wcd938x->handle,
  729. WCD_BOLERO_EVT_RX_MUTE,
  730. (WCD_RX3 << 0x10 | 0x1));
  731. break;
  732. case SND_SOC_DAPM_POST_PMD:
  733. /* 1 msec delay as per HW requirement */
  734. usleep_range(1000, 1010);
  735. snd_soc_component_update_bits(component,
  736. WCD938X_DIGITAL_PDM_WD_CTL2, 0x05, 0x00);
  737. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  738. WCD_CLSH_EVENT_POST_PA,
  739. WCD_CLSH_STATE_AUX,
  740. hph_mode);
  741. wcd938x->flyback_cur_det_disable--;
  742. if (wcd938x->flyback_cur_det_disable == 0)
  743. snd_soc_component_update_bits(component,
  744. WCD938X_FLYBACK_EN,
  745. 0x04, 0x04);
  746. break;
  747. };
  748. return ret;
  749. }
  750. static int wcd938x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  751. struct snd_kcontrol *kcontrol,
  752. int event)
  753. {
  754. struct snd_soc_component *component =
  755. snd_soc_dapm_to_component(w->dapm);
  756. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  757. int hph_mode = wcd938x->hph_mode;
  758. int ret = 0;
  759. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  760. w->name, event);
  761. switch (event) {
  762. case SND_SOC_DAPM_PRE_PMU:
  763. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  764. wcd938x->rx_swr_dev->dev_num,
  765. true);
  766. /*
  767. * Enable watchdog interrupt for HPHL or AUX
  768. * depending on mux value
  769. */
  770. wcd938x->ear_rx_path =
  771. snd_soc_component_read32(
  772. component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
  773. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  774. snd_soc_component_update_bits(component,
  775. WCD938X_DIGITAL_PDM_WD_CTL2,
  776. 0x05, 0x05);
  777. else
  778. snd_soc_component_update_bits(component,
  779. WCD938X_DIGITAL_PDM_WD_CTL0,
  780. 0x17, 0x13);
  781. break;
  782. case SND_SOC_DAPM_POST_PMU:
  783. /* 6 msec delay as per HW requirement */
  784. usleep_range(6000, 6010);
  785. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  786. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  787. snd_soc_component_update_bits(component,
  788. WCD938X_ANA_RX_SUPPLIES,
  789. 0x02, 0x02);
  790. if (wcd938x->update_wcd_event)
  791. wcd938x->update_wcd_event(wcd938x->handle,
  792. WCD_BOLERO_EVT_RX_MUTE,
  793. (WCD_RX1 << 0x10));
  794. break;
  795. case SND_SOC_DAPM_PRE_PMD:
  796. if (wcd938x->update_wcd_event)
  797. wcd938x->update_wcd_event(wcd938x->handle,
  798. WCD_BOLERO_EVT_RX_MUTE,
  799. (WCD_RX1 << 0x10 | 0x1));
  800. break;
  801. case SND_SOC_DAPM_POST_PMD:
  802. /* 7 msec delay as per HW requirement */
  803. usleep_range(7000, 7010);
  804. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  805. snd_soc_component_update_bits(component,
  806. WCD938X_DIGITAL_PDM_WD_CTL2,
  807. 0x05, 0x00);
  808. else
  809. snd_soc_component_update_bits(component,
  810. WCD938X_DIGITAL_PDM_WD_CTL0,
  811. 0x17, 0x00);
  812. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  813. WCD_CLSH_EVENT_POST_PA,
  814. WCD_CLSH_STATE_EAR,
  815. hph_mode);
  816. wcd938x->flyback_cur_det_disable--;
  817. if (wcd938x->flyback_cur_det_disable == 0)
  818. snd_soc_component_update_bits(component,
  819. WCD938X_FLYBACK_EN,
  820. 0x04, 0x04);
  821. break;
  822. };
  823. return ret;
  824. }
  825. static int wcd938x_enable_clsh(struct snd_soc_dapm_widget *w,
  826. struct snd_kcontrol *kcontrol,
  827. int event)
  828. {
  829. struct snd_soc_component *component =
  830. snd_soc_dapm_to_component(w->dapm);
  831. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  832. int mode = wcd938x->hph_mode;
  833. int ret = 0;
  834. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  835. w->name, event);
  836. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  837. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  838. wcd938x_rx_connect_port(component, CLSH,
  839. SND_SOC_DAPM_EVENT_ON(event));
  840. }
  841. if (SND_SOC_DAPM_EVENT_OFF(event))
  842. ret = swr_slvdev_datapath_control(
  843. wcd938x->rx_swr_dev,
  844. wcd938x->rx_swr_dev->dev_num,
  845. false);
  846. return ret;
  847. }
  848. static int wcd938x_enable_rx1(struct snd_soc_dapm_widget *w,
  849. struct snd_kcontrol *kcontrol,
  850. int event)
  851. {
  852. struct snd_soc_component *component =
  853. snd_soc_dapm_to_component(w->dapm);
  854. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  855. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  856. w->name, event);
  857. switch (event) {
  858. case SND_SOC_DAPM_PRE_PMU:
  859. wcd938x_rx_connect_port(component, HPH_L, true);
  860. if (wcd938x->comp1_enable)
  861. wcd938x_rx_connect_port(component, COMP_L, true);
  862. break;
  863. case SND_SOC_DAPM_POST_PMD:
  864. wcd938x_rx_connect_port(component, HPH_L, false);
  865. if (wcd938x->comp1_enable)
  866. wcd938x_rx_connect_port(component, COMP_L, false);
  867. wcd938x_rx_clk_disable(component);
  868. snd_soc_component_update_bits(component,
  869. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  870. 0x01, 0x00);
  871. break;
  872. };
  873. return 0;
  874. }
  875. static int wcd938x_enable_rx2(struct snd_soc_dapm_widget *w,
  876. struct snd_kcontrol *kcontrol, int event)
  877. {
  878. struct snd_soc_component *component =
  879. snd_soc_dapm_to_component(w->dapm);
  880. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  881. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  882. w->name, event);
  883. switch (event) {
  884. case SND_SOC_DAPM_PRE_PMU:
  885. wcd938x_rx_connect_port(component, HPH_R, true);
  886. if (wcd938x->comp2_enable)
  887. wcd938x_rx_connect_port(component, COMP_R, true);
  888. break;
  889. case SND_SOC_DAPM_POST_PMD:
  890. wcd938x_rx_connect_port(component, HPH_R, false);
  891. if (wcd938x->comp2_enable)
  892. wcd938x_rx_connect_port(component, COMP_R, false);
  893. wcd938x_rx_clk_disable(component);
  894. snd_soc_component_update_bits(component,
  895. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  896. 0x02, 0x00);
  897. break;
  898. };
  899. return 0;
  900. }
  901. static int wcd938x_enable_rx3(struct snd_soc_dapm_widget *w,
  902. struct snd_kcontrol *kcontrol,
  903. int event)
  904. {
  905. struct snd_soc_component *component =
  906. snd_soc_dapm_to_component(w->dapm);
  907. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  908. w->name, event);
  909. switch (event) {
  910. case SND_SOC_DAPM_PRE_PMU:
  911. wcd938x_rx_connect_port(component, LO, true);
  912. break;
  913. case SND_SOC_DAPM_POST_PMD:
  914. wcd938x_rx_connect_port(component, LO, false);
  915. /* 6 msec delay as per HW requirement */
  916. usleep_range(6000, 6010);
  917. wcd938x_rx_clk_disable(component);
  918. snd_soc_component_update_bits(component,
  919. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  920. break;
  921. }
  922. return 0;
  923. }
  924. static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  925. struct snd_kcontrol *kcontrol,
  926. int event)
  927. {
  928. struct snd_soc_component *component =
  929. snd_soc_dapm_to_component(w->dapm);
  930. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  931. u16 dmic_clk_reg;
  932. s32 *dmic_clk_cnt;
  933. unsigned int dmic;
  934. char *wname;
  935. int ret = 0;
  936. wname = strpbrk(w->name, "012345");
  937. if (!wname) {
  938. dev_err(component->dev, "%s: widget not found\n", __func__);
  939. return -EINVAL;
  940. }
  941. ret = kstrtouint(wname, 10, &dmic);
  942. if (ret < 0) {
  943. dev_err(component->dev, "%s: Invalid DMIC line on the codec\n",
  944. __func__);
  945. return -EINVAL;
  946. }
  947. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  948. w->name, event);
  949. switch (dmic) {
  950. case 0:
  951. case 1:
  952. dmic_clk_cnt = &(wcd938x->dmic_0_1_clk_cnt);
  953. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC1_CTL;
  954. break;
  955. case 2:
  956. case 3:
  957. dmic_clk_cnt = &(wcd938x->dmic_2_3_clk_cnt);
  958. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC2_CTL;
  959. break;
  960. case 4:
  961. case 5:
  962. dmic_clk_cnt = &(wcd938x->dmic_4_5_clk_cnt);
  963. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC3_CTL;
  964. break;
  965. case 6:
  966. case 7:
  967. dmic_clk_cnt = &(wcd938x->dmic_6_7_clk_cnt);
  968. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC4_CTL;
  969. break;
  970. default:
  971. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  972. __func__);
  973. return -EINVAL;
  974. };
  975. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  976. __func__, event, dmic, *dmic_clk_cnt);
  977. switch (event) {
  978. case SND_SOC_DAPM_PRE_PMU:
  979. snd_soc_component_update_bits(component,
  980. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  981. /* enable clock scaling */
  982. snd_soc_component_update_bits(component,
  983. WCD938X_DIGITAL_CDC_DMIC_CTL, 0x06, 0x06);
  984. snd_soc_component_update_bits(component,
  985. dmic_clk_reg, 0x07, 0x02);
  986. snd_soc_component_update_bits(component,
  987. dmic_clk_reg, 0x08, 0x08);
  988. snd_soc_component_update_bits(component,
  989. dmic_clk_reg, 0x70, 0x20);
  990. wcd938x_tx_connect_port(component, DMIC0 + (w->shift), true);
  991. break;
  992. case SND_SOC_DAPM_POST_PMD:
  993. wcd938x_tx_connect_port(component, DMIC0 + (w->shift), false);
  994. break;
  995. };
  996. return 0;
  997. }
  998. /*
  999. * wcd938x_get_micb_vout_ctl_val: converts micbias from volts to register value
  1000. * @micb_mv: micbias in mv
  1001. *
  1002. * return register value converted
  1003. */
  1004. int wcd938x_get_micb_vout_ctl_val(u32 micb_mv)
  1005. {
  1006. /* min micbias voltage is 1V and maximum is 2.85V */
  1007. if (micb_mv < 1000 || micb_mv > 2850) {
  1008. pr_err("%s: unsupported micbias voltage\n", __func__);
  1009. return -EINVAL;
  1010. }
  1011. return (micb_mv - 1000) / 50;
  1012. }
  1013. EXPORT_SYMBOL(wcd938x_get_micb_vout_ctl_val);
  1014. /*
  1015. * wcd938x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  1016. * @component: handle to snd_soc_component *
  1017. * @req_volt: micbias voltage to be set
  1018. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  1019. *
  1020. * return 0 if adjustment is success or error code in case of failure
  1021. */
  1022. int wcd938x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  1023. int req_volt, int micb_num)
  1024. {
  1025. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1026. int cur_vout_ctl, req_vout_ctl;
  1027. int micb_reg, micb_val, micb_en;
  1028. int ret = 0;
  1029. switch (micb_num) {
  1030. case MIC_BIAS_1:
  1031. micb_reg = WCD938X_ANA_MICB1;
  1032. break;
  1033. case MIC_BIAS_2:
  1034. micb_reg = WCD938X_ANA_MICB2;
  1035. break;
  1036. case MIC_BIAS_3:
  1037. micb_reg = WCD938X_ANA_MICB3;
  1038. break;
  1039. case MIC_BIAS_4:
  1040. micb_reg = WCD938X_ANA_MICB4;
  1041. break;
  1042. default:
  1043. return -EINVAL;
  1044. }
  1045. mutex_lock(&wcd938x->micb_lock);
  1046. /*
  1047. * If requested micbias voltage is same as current micbias
  1048. * voltage, then just return. Otherwise, adjust voltage as
  1049. * per requested value. If micbias is already enabled, then
  1050. * to avoid slow micbias ramp-up or down enable pull-up
  1051. * momentarily, change the micbias value and then re-enable
  1052. * micbias.
  1053. */
  1054. micb_val = snd_soc_component_read32(component, micb_reg);
  1055. micb_en = (micb_val & 0xC0) >> 6;
  1056. cur_vout_ctl = micb_val & 0x3F;
  1057. req_vout_ctl = wcd938x_get_micb_vout_ctl_val(req_volt);
  1058. if (req_vout_ctl < 0) {
  1059. ret = -EINVAL;
  1060. goto exit;
  1061. }
  1062. if (cur_vout_ctl == req_vout_ctl) {
  1063. ret = 0;
  1064. goto exit;
  1065. }
  1066. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  1067. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  1068. req_volt, micb_en);
  1069. if (micb_en == 0x1)
  1070. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  1071. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  1072. if (micb_en == 0x1) {
  1073. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  1074. /*
  1075. * Add 2ms delay as per HW requirement after enabling
  1076. * micbias
  1077. */
  1078. usleep_range(2000, 2100);
  1079. }
  1080. exit:
  1081. mutex_unlock(&wcd938x->micb_lock);
  1082. return ret;
  1083. }
  1084. EXPORT_SYMBOL(wcd938x_mbhc_micb_adjust_voltage);
  1085. static int wcd938x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1086. struct snd_kcontrol *kcontrol,
  1087. int event)
  1088. {
  1089. struct snd_soc_component *component =
  1090. snd_soc_dapm_to_component(w->dapm);
  1091. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1092. int ret = 0;
  1093. switch (event) {
  1094. case SND_SOC_DAPM_PRE_PMU:
  1095. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1096. wcd938x->tx_swr_dev->dev_num,
  1097. true);
  1098. break;
  1099. case SND_SOC_DAPM_POST_PMD:
  1100. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1101. wcd938x->tx_swr_dev->dev_num,
  1102. false);
  1103. break;
  1104. };
  1105. return ret;
  1106. }
  1107. static int wcd938x_get_adc_mode(int val)
  1108. {
  1109. int ret = 0;
  1110. switch (val) {
  1111. case ADC_MODE_INVALID:
  1112. ret = ADC_MODE_VAL_NORMAL;
  1113. break;
  1114. case ADC_MODE_HIFI:
  1115. ret = ADC_MODE_VAL_HIFI;
  1116. break;
  1117. case ADC_MODE_LO_HIF:
  1118. ret = ADC_MODE_VAL_LO_HIF;
  1119. break;
  1120. case ADC_MODE_NORMAL:
  1121. ret = ADC_MODE_VAL_NORMAL;
  1122. break;
  1123. case ADC_MODE_LP:
  1124. ret = ADC_MODE_VAL_LP;
  1125. break;
  1126. case ADC_MODE_ULP1:
  1127. ret = ADC_MODE_VAL_ULP1;
  1128. break;
  1129. case ADC_MODE_ULP2:
  1130. ret = ADC_MODE_VAL_ULP2;
  1131. break;
  1132. default:
  1133. ret = -EINVAL;
  1134. pr_err("%s: invalid ADC mode value %d\n", __func__, val);
  1135. break;
  1136. }
  1137. return ret;
  1138. }
  1139. static int wcd938x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  1140. struct snd_kcontrol *kcontrol,
  1141. int event){
  1142. int mode;
  1143. struct snd_soc_component *component =
  1144. snd_soc_dapm_to_component(w->dapm);
  1145. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1146. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1147. w->name, event);
  1148. switch (event) {
  1149. case SND_SOC_DAPM_PRE_PMU:
  1150. mode = wcd938x_get_adc_mode(wcd938x->tx_mode[w->shift]);
  1151. if (mode < 0) {
  1152. dev_info(component->dev,
  1153. "%s: invalid mode, setting to normal mode\n",
  1154. __func__);
  1155. mode = ADC_MODE_VAL_NORMAL;
  1156. }
  1157. snd_soc_component_update_bits(component,
  1158. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1159. snd_soc_component_update_bits(component,
  1160. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x08);
  1161. snd_soc_component_update_bits(component,
  1162. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1163. switch (w->shift) {
  1164. case 0:
  1165. snd_soc_component_update_bits(component,
  1166. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x0F,
  1167. mode);
  1168. break;
  1169. case 1:
  1170. snd_soc_component_update_bits(component,
  1171. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0xF0,
  1172. mode << 4);
  1173. break;
  1174. case 2:
  1175. snd_soc_component_update_bits(component,
  1176. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x0F,
  1177. mode);
  1178. break;
  1179. case 3:
  1180. snd_soc_component_update_bits(component,
  1181. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0xF0,
  1182. mode << 4);
  1183. break;
  1184. default:
  1185. break;
  1186. }
  1187. set_bit(w->shift, &wcd938x->status_mask);
  1188. wcd938x_tx_connect_port(component, ADC1 + (w->shift), true);
  1189. break;
  1190. case SND_SOC_DAPM_POST_PMD:
  1191. wcd938x_tx_connect_port(component, ADC1 + (w->shift), false);
  1192. snd_soc_component_update_bits(component,
  1193. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x00);
  1194. clear_bit(w->shift, &wcd938x->status_mask);
  1195. break;
  1196. };
  1197. return 0;
  1198. }
  1199. int wcd938x_tx_channel_config(struct snd_soc_component *component,
  1200. int channel, int mode)
  1201. {
  1202. int reg = WCD938X_ANA_TX_CH2, mask = 0, val = 0;
  1203. int ret = 0;
  1204. switch (channel) {
  1205. case 0:
  1206. reg = WCD938X_ANA_TX_CH2;
  1207. mask = 0x40;
  1208. break;
  1209. case 1:
  1210. reg = WCD938X_ANA_TX_CH2;
  1211. mask = 0x20;
  1212. break;
  1213. case 2:
  1214. reg = WCD938X_ANA_TX_CH4;
  1215. mask = 0x40;
  1216. break;
  1217. case 3:
  1218. reg = WCD938X_ANA_TX_CH4;
  1219. mask = 0x20;
  1220. break;
  1221. default:
  1222. pr_err("%s: Invalid channel num %d\n", __func__, channel);
  1223. ret = -EINVAL;
  1224. break;
  1225. }
  1226. if (!mode)
  1227. val = 0x00;
  1228. else
  1229. val = mask;
  1230. if (!ret)
  1231. snd_soc_component_update_bits(component, reg, mask, val);
  1232. return ret;
  1233. }
  1234. static int wcd938x_enable_req(struct snd_soc_dapm_widget *w,
  1235. struct snd_kcontrol *kcontrol, int event)
  1236. {
  1237. struct snd_soc_component *component =
  1238. snd_soc_dapm_to_component(w->dapm);
  1239. int ret = 0;
  1240. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1241. w->name, event);
  1242. switch (event) {
  1243. case SND_SOC_DAPM_PRE_PMU:
  1244. snd_soc_component_update_bits(component,
  1245. WCD938X_DIGITAL_CDC_REQ_CTL, 0x02, 0x02);
  1246. snd_soc_component_update_bits(component,
  1247. WCD938X_DIGITAL_CDC_REQ_CTL, 0x01, 0x00);
  1248. ret = wcd938x_tx_channel_config(component, w->shift, 1);
  1249. snd_soc_component_update_bits(component,
  1250. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x30, 0x30);
  1251. snd_soc_component_update_bits(component,
  1252. WCD938X_ANA_TX_CH1, 0x80, 0x80);
  1253. snd_soc_component_update_bits(component,
  1254. WCD938X_ANA_TX_CH2, 0x80, 0x80);
  1255. ret |= wcd938x_tx_channel_config(component, w->shift, 0);
  1256. break;
  1257. case SND_SOC_DAPM_POST_PMD:
  1258. snd_soc_component_update_bits(component,
  1259. WCD938X_ANA_TX_CH1, 0x80, 0x00);
  1260. snd_soc_component_update_bits(component,
  1261. WCD938X_ANA_TX_CH2, 0x80, 0x00);
  1262. snd_soc_component_update_bits(component,
  1263. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x00);
  1264. snd_soc_component_update_bits(component,
  1265. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
  1266. snd_soc_component_update_bits(component,
  1267. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00);
  1268. break;
  1269. };
  1270. return ret;
  1271. }
  1272. int wcd938x_micbias_control(struct snd_soc_component *component,
  1273. int micb_num, int req, bool is_dapm)
  1274. {
  1275. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1276. int micb_index = micb_num - 1;
  1277. u16 micb_reg;
  1278. int pre_off_event = 0, post_off_event = 0;
  1279. int post_on_event = 0, post_dapm_off = 0;
  1280. int post_dapm_on = 0;
  1281. if ((micb_index < 0) || (micb_index > WCD938X_MAX_MICBIAS - 1)) {
  1282. dev_err(component->dev,
  1283. "%s: Invalid micbias index, micb_ind:%d\n",
  1284. __func__, micb_index);
  1285. return -EINVAL;
  1286. }
  1287. if (NULL == wcd938x) {
  1288. dev_err(component->dev,
  1289. "%s: wcd938x private data is NULL\n", __func__);
  1290. return -EINVAL;
  1291. }
  1292. switch (micb_num) {
  1293. case MIC_BIAS_1:
  1294. micb_reg = WCD938X_ANA_MICB1;
  1295. break;
  1296. case MIC_BIAS_2:
  1297. micb_reg = WCD938X_ANA_MICB2;
  1298. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1299. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1300. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1301. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1302. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1303. break;
  1304. case MIC_BIAS_3:
  1305. micb_reg = WCD938X_ANA_MICB3;
  1306. break;
  1307. case MIC_BIAS_4:
  1308. micb_reg = WCD938X_ANA_MICB4;
  1309. break;
  1310. default:
  1311. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1312. __func__, micb_num);
  1313. return -EINVAL;
  1314. };
  1315. mutex_lock(&wcd938x->micb_lock);
  1316. switch (req) {
  1317. case MICB_PULLUP_ENABLE:
  1318. wcd938x->pullup_ref[micb_index]++;
  1319. if ((wcd938x->pullup_ref[micb_index] == 1) &&
  1320. (wcd938x->micb_ref[micb_index] == 0))
  1321. snd_soc_component_update_bits(component, micb_reg,
  1322. 0xC0, 0x80);
  1323. break;
  1324. case MICB_PULLUP_DISABLE:
  1325. if (wcd938x->pullup_ref[micb_index] > 0)
  1326. wcd938x->pullup_ref[micb_index]--;
  1327. if ((wcd938x->pullup_ref[micb_index] == 0) &&
  1328. (wcd938x->micb_ref[micb_index] == 0))
  1329. snd_soc_component_update_bits(component, micb_reg,
  1330. 0xC0, 0x00);
  1331. break;
  1332. case MICB_ENABLE:
  1333. wcd938x->micb_ref[micb_index]++;
  1334. if (wcd938x->micb_ref[micb_index] == 1) {
  1335. snd_soc_component_update_bits(component,
  1336. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xE0, 0xE0);
  1337. snd_soc_component_update_bits(component,
  1338. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1339. snd_soc_component_update_bits(component,
  1340. WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x01, 0x01);
  1341. snd_soc_component_update_bits(component,
  1342. WCD938X_MICB1_TEST_CTL_2, 0x01, 0x01);
  1343. snd_soc_component_update_bits(component,
  1344. WCD938X_MICB2_TEST_CTL_2, 0x01, 0x01);
  1345. snd_soc_component_update_bits(component,
  1346. WCD938X_MICB3_TEST_CTL_2, 0x01, 0x01);
  1347. snd_soc_component_update_bits(component,
  1348. WCD938X_MICB4_TEST_CTL_2, 0x01, 0x01);
  1349. snd_soc_component_update_bits(component,
  1350. micb_reg, 0xC0, 0x40);
  1351. if (post_on_event)
  1352. blocking_notifier_call_chain(
  1353. &wcd938x->mbhc->notifier,
  1354. post_on_event,
  1355. &wcd938x->mbhc->wcd_mbhc);
  1356. }
  1357. if (is_dapm && post_dapm_on && wcd938x->mbhc)
  1358. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1359. post_dapm_on,
  1360. &wcd938x->mbhc->wcd_mbhc);
  1361. break;
  1362. case MICB_DISABLE:
  1363. if (wcd938x->micb_ref[micb_index] > 0)
  1364. wcd938x->micb_ref[micb_index]--;
  1365. if ((wcd938x->micb_ref[micb_index] == 0) &&
  1366. (wcd938x->pullup_ref[micb_index] > 0))
  1367. snd_soc_component_update_bits(component, micb_reg,
  1368. 0xC0, 0x80);
  1369. else if ((wcd938x->micb_ref[micb_index] == 0) &&
  1370. (wcd938x->pullup_ref[micb_index] == 0)) {
  1371. if (pre_off_event && wcd938x->mbhc)
  1372. blocking_notifier_call_chain(
  1373. &wcd938x->mbhc->notifier,
  1374. pre_off_event,
  1375. &wcd938x->mbhc->wcd_mbhc);
  1376. snd_soc_component_update_bits(component, micb_reg,
  1377. 0xC0, 0x00);
  1378. if (post_off_event && wcd938x->mbhc)
  1379. blocking_notifier_call_chain(
  1380. &wcd938x->mbhc->notifier,
  1381. post_off_event,
  1382. &wcd938x->mbhc->wcd_mbhc);
  1383. }
  1384. if (is_dapm && post_dapm_off && wcd938x->mbhc)
  1385. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1386. post_dapm_off,
  1387. &wcd938x->mbhc->wcd_mbhc);
  1388. break;
  1389. };
  1390. dev_dbg(component->dev,
  1391. "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1392. __func__, micb_num, wcd938x->micb_ref[micb_index],
  1393. wcd938x->pullup_ref[micb_index]);
  1394. mutex_unlock(&wcd938x->micb_lock);
  1395. return 0;
  1396. }
  1397. EXPORT_SYMBOL(wcd938x_micbias_control);
  1398. static int wcd938x_get_logical_addr(struct swr_device *swr_dev)
  1399. {
  1400. int ret = 0;
  1401. uint8_t devnum = 0;
  1402. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1403. if (ret) {
  1404. dev_err(&swr_dev->dev,
  1405. "%s get devnum %d for dev addr %lx failed\n",
  1406. __func__, devnum, swr_dev->addr);
  1407. swr_remove_device(swr_dev);
  1408. return ret;
  1409. }
  1410. swr_dev->dev_num = devnum;
  1411. return 0;
  1412. }
  1413. static int wcd938x_event_notify(struct notifier_block *block,
  1414. unsigned long val,
  1415. void *data)
  1416. {
  1417. u16 event = (val & 0xffff);
  1418. int ret = 0;
  1419. struct wcd938x_priv *wcd938x = dev_get_drvdata((struct device *)data);
  1420. struct snd_soc_component *component = wcd938x->component;
  1421. struct wcd_mbhc *mbhc;
  1422. switch (event) {
  1423. case BOLERO_WCD_EVT_TX_CH_HOLD_CLEAR:
  1424. if (test_bit(WCD_ADC1, &wcd938x->status_mask)) {
  1425. snd_soc_component_update_bits(component,
  1426. WCD938X_ANA_TX_CH2, 0x40, 0x00);
  1427. clear_bit(WCD_ADC1, &wcd938x->status_mask);
  1428. }
  1429. if (test_bit(WCD_ADC2, &wcd938x->status_mask)) {
  1430. snd_soc_component_update_bits(component,
  1431. WCD938X_ANA_TX_CH2, 0x20, 0x00);
  1432. clear_bit(WCD_ADC2, &wcd938x->status_mask);
  1433. }
  1434. if (test_bit(WCD_ADC3, &wcd938x->status_mask)) {
  1435. snd_soc_component_update_bits(component,
  1436. WCD938X_ANA_TX_CH4, 0x40, 0x00);
  1437. clear_bit(WCD_ADC3, &wcd938x->status_mask);
  1438. }
  1439. if (test_bit(WCD_ADC4, &wcd938x->status_mask)) {
  1440. snd_soc_component_update_bits(component,
  1441. WCD938X_ANA_TX_CH4, 0x20, 0x00);
  1442. clear_bit(WCD_ADC4, &wcd938x->status_mask);
  1443. }
  1444. break;
  1445. case BOLERO_WCD_EVT_PA_OFF_PRE_SSR:
  1446. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  1447. 0xC0, 0x00);
  1448. snd_soc_component_update_bits(component, WCD938X_ANA_EAR,
  1449. 0x80, 0x00);
  1450. snd_soc_component_update_bits(component, WCD938X_AUX_AUXPA,
  1451. 0x80, 0x00);
  1452. break;
  1453. case BOLERO_WCD_EVT_SSR_DOWN:
  1454. mbhc = &wcd938x->mbhc->wcd_mbhc;
  1455. wcd938x_mbhc_ssr_down(wcd938x->mbhc, component);
  1456. wcd938x_reset_low(wcd938x->dev);
  1457. break;
  1458. case BOLERO_WCD_EVT_SSR_UP:
  1459. wcd938x_reset(wcd938x->dev);
  1460. wcd938x_get_logical_addr(wcd938x->tx_swr_dev);
  1461. wcd938x_get_logical_addr(wcd938x->rx_swr_dev);
  1462. wcd938x_init_reg(component);
  1463. regcache_mark_dirty(wcd938x->regmap);
  1464. regcache_sync(wcd938x->regmap);
  1465. /* Initialize MBHC module */
  1466. mbhc = &wcd938x->mbhc->wcd_mbhc;
  1467. ret = wcd938x_mbhc_post_ssr_init(wcd938x->mbhc, component);
  1468. if (ret) {
  1469. dev_err(component->dev, "%s: mbhc initialization failed\n",
  1470. __func__);
  1471. } else {
  1472. wcd938x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  1473. }
  1474. break;
  1475. case BOLERO_WCD_EVT_CLK_NOTIFY:
  1476. snd_soc_component_update_bits(component,
  1477. WCD938X_DIGITAL_TOP_CLK_CFG, 0x06,
  1478. ((val >> 0x10) << 0x01));
  1479. break;
  1480. default:
  1481. dev_dbg(component->dev, "%s: invalid event %d\n", __func__, event);
  1482. break;
  1483. }
  1484. return 0;
  1485. }
  1486. static int __wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1487. int event)
  1488. {
  1489. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1490. int micb_num;
  1491. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1492. __func__, w->name, event);
  1493. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  1494. micb_num = MIC_BIAS_1;
  1495. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  1496. micb_num = MIC_BIAS_2;
  1497. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  1498. micb_num = MIC_BIAS_3;
  1499. else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4")))
  1500. micb_num = MIC_BIAS_4;
  1501. else
  1502. return -EINVAL;
  1503. switch (event) {
  1504. case SND_SOC_DAPM_PRE_PMU:
  1505. wcd938x_micbias_control(component, micb_num,
  1506. MICB_ENABLE, true);
  1507. break;
  1508. case SND_SOC_DAPM_POST_PMU:
  1509. /* 1 msec delay as per HW requirement */
  1510. usleep_range(1000, 1100);
  1511. break;
  1512. case SND_SOC_DAPM_POST_PMD:
  1513. wcd938x_micbias_control(component, micb_num,
  1514. MICB_DISABLE, true);
  1515. break;
  1516. };
  1517. return 0;
  1518. }
  1519. static int wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1520. struct snd_kcontrol *kcontrol,
  1521. int event)
  1522. {
  1523. return __wcd938x_codec_enable_micbias(w, event);
  1524. }
  1525. static inline int wcd938x_tx_path_get(const char *wname)
  1526. {
  1527. int ret = 0;
  1528. unsigned int path_num;
  1529. char *widget_name = NULL;
  1530. char *w_name = NULL;
  1531. char *path_num_char = NULL;
  1532. char *path_name = NULL;
  1533. widget_name = kstrndup(wname, 9, GFP_KERNEL);
  1534. if (!widget_name)
  1535. return -EINVAL;
  1536. w_name = widget_name;
  1537. path_name = strsep(&widget_name, " ");
  1538. if (!path_name) {
  1539. pr_err("%s: Invalid widget name = %s\n",
  1540. __func__, widget_name);
  1541. ret = -EINVAL;
  1542. goto err;
  1543. }
  1544. path_name = widget_name;
  1545. path_num_char = strpbrk(path_name, "0123");
  1546. if (!path_num_char) {
  1547. pr_err("%s: tx path index not found\n",
  1548. __func__);
  1549. ret = -EINVAL;
  1550. goto err;
  1551. }
  1552. ret = kstrtouint(path_num_char, 10, &path_num);
  1553. if (ret < 0)
  1554. pr_err("%s: Invalid tx path = %s\n",
  1555. __func__, w_name);
  1556. err:
  1557. kfree(w_name);
  1558. return ret;
  1559. }
  1560. static int wcd938x_tx_mode_get(struct snd_kcontrol *kcontrol,
  1561. struct snd_ctl_elem_value *ucontrol)
  1562. {
  1563. struct snd_soc_dapm_widget *widget =
  1564. snd_soc_dapm_kcontrol_widget(kcontrol);
  1565. struct snd_soc_component *component =
  1566. snd_soc_kcontrol_component(kcontrol);
  1567. struct wcd938x_priv *wcd938x = NULL;
  1568. int path = 0;
  1569. if (!component)
  1570. return -EINVAL;
  1571. wcd938x = snd_soc_component_get_drvdata(component);
  1572. if (!widget || !widget->name || !wcd938x)
  1573. return -EINVAL;
  1574. path = wcd938x_tx_path_get(widget->name);
  1575. if (path < 0 || path >= TX_ADC_MAX)
  1576. return -EINVAL;
  1577. ucontrol->value.integer.value[0] = wcd938x->tx_mode[path];
  1578. return 0;
  1579. }
  1580. static int wcd938x_tx_mode_put(struct snd_kcontrol *kcontrol,
  1581. struct snd_ctl_elem_value *ucontrol)
  1582. {
  1583. struct snd_soc_dapm_widget *widget =
  1584. snd_soc_dapm_kcontrol_widget(kcontrol);
  1585. struct snd_soc_component *component =
  1586. snd_soc_kcontrol_component(kcontrol);
  1587. struct wcd938x_priv *wcd938x = NULL;
  1588. u32 mode_val;
  1589. int path = 0;
  1590. if (!component)
  1591. return -EINVAL;
  1592. wcd938x = snd_soc_component_get_drvdata(component);
  1593. if (!widget || !widget->name || !wcd938x)
  1594. return -EINVAL;
  1595. path = wcd938x_tx_path_get(widget->name);
  1596. if (path < 0 || path >= TX_ADC_MAX)
  1597. return -EINVAL;
  1598. mode_val = ucontrol->value.enumerated.item[0];
  1599. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  1600. wcd938x->tx_mode[path] = mode_val;
  1601. return 0;
  1602. }
  1603. static int wcd938x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  1604. struct snd_ctl_elem_value *ucontrol)
  1605. {
  1606. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  1607. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1608. ucontrol->value.integer.value[0] = wcd938x->hph_mode;
  1609. return 0;
  1610. }
  1611. static int wcd938x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  1612. struct snd_ctl_elem_value *ucontrol)
  1613. {
  1614. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  1615. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1616. u32 mode_val;
  1617. mode_val = ucontrol->value.enumerated.item[0];
  1618. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  1619. if (mode_val == 0) {
  1620. dev_info(component->dev,
  1621. "%s:Invalid HPH Mode, default to class_AB\n",
  1622. __func__);
  1623. mode_val = 3; /* enum will be updated later */
  1624. }
  1625. wcd938x->hph_mode = mode_val;
  1626. return 0;
  1627. }
  1628. static int wcd938x_get_compander(struct snd_kcontrol *kcontrol,
  1629. struct snd_ctl_elem_value *ucontrol)
  1630. {
  1631. struct snd_soc_component *component =
  1632. snd_soc_kcontrol_component(kcontrol);
  1633. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1634. bool hphr;
  1635. struct soc_multi_mixer_control *mc;
  1636. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1637. hphr = mc->shift;
  1638. ucontrol->value.integer.value[0] = hphr ? wcd938x->comp2_enable :
  1639. wcd938x->comp1_enable;
  1640. return 0;
  1641. }
  1642. static int wcd938x_set_compander(struct snd_kcontrol *kcontrol,
  1643. struct snd_ctl_elem_value *ucontrol)
  1644. {
  1645. struct snd_soc_component *component =
  1646. snd_soc_kcontrol_component(kcontrol);
  1647. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1648. int value = ucontrol->value.integer.value[0];
  1649. bool hphr;
  1650. struct soc_multi_mixer_control *mc;
  1651. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1652. hphr = mc->shift;
  1653. if (hphr)
  1654. wcd938x->comp2_enable = value;
  1655. else
  1656. wcd938x->comp1_enable = value;
  1657. return 0;
  1658. }
  1659. static const char * const tx_mode_mux_text_wcd9380[] = {
  1660. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  1661. };
  1662. static const struct soc_enum tx_mode_mux_enum_wcd9380 =
  1663. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text_wcd9380),
  1664. tx_mode_mux_text_wcd9380);
  1665. static const char * const tx_mode_mux_text[] = {
  1666. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  1667. "ADC_ULP1", "ADC_ULP2",
  1668. };
  1669. static const struct soc_enum tx_mode_mux_enum =
  1670. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text),
  1671. tx_mode_mux_text);
  1672. static const char * const rx_hph_mode_mux_text[] = {
  1673. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  1674. "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI",
  1675. };
  1676. static const struct soc_enum rx_hph_mode_mux_enum =
  1677. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  1678. rx_hph_mode_mux_text);
  1679. static const struct snd_kcontrol_new wcd9380_snd_controls[] = {
  1680. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum_wcd9380,
  1681. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1682. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum_wcd9380,
  1683. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1684. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum_wcd9380,
  1685. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1686. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum_wcd9380,
  1687. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1688. };
  1689. static const struct snd_kcontrol_new wcd9385_snd_controls[] = {
  1690. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum,
  1691. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1692. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum,
  1693. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1694. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum,
  1695. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1696. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum,
  1697. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1698. };
  1699. static const struct snd_kcontrol_new wcd938x_snd_controls[] = {
  1700. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  1701. wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
  1702. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  1703. wcd938x_get_compander, wcd938x_set_compander),
  1704. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  1705. wcd938x_get_compander, wcd938x_set_compander),
  1706. SOC_SINGLE_TLV("HPHL Volume", WCD938X_HPH_L_EN, 0, 20, 1, line_gain),
  1707. SOC_SINGLE_TLV("HPHR Volume", WCD938X_HPH_R_EN, 0, 20, 1, line_gain),
  1708. SOC_SINGLE_TLV("ADC1 Volume", WCD938X_ANA_TX_CH1, 0, 20, 0,
  1709. analog_gain),
  1710. SOC_SINGLE_TLV("ADC2 Volume", WCD938X_ANA_TX_CH2, 0, 20, 0,
  1711. analog_gain),
  1712. SOC_SINGLE_TLV("ADC3 Volume", WCD938X_ANA_TX_CH3, 0, 20, 0,
  1713. analog_gain),
  1714. SOC_SINGLE_TLV("ADC4 Volume", WCD938X_ANA_TX_CH4, 0, 20, 0,
  1715. analog_gain),
  1716. };
  1717. static const struct snd_kcontrol_new adc1_switch[] = {
  1718. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1719. };
  1720. static const struct snd_kcontrol_new adc2_switch[] = {
  1721. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1722. };
  1723. static const struct snd_kcontrol_new adc3_switch[] = {
  1724. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1725. };
  1726. static const struct snd_kcontrol_new adc4_switch[] = {
  1727. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1728. };
  1729. static const struct snd_kcontrol_new dmic1_switch[] = {
  1730. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1731. };
  1732. static const struct snd_kcontrol_new dmic2_switch[] = {
  1733. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1734. };
  1735. static const struct snd_kcontrol_new dmic3_switch[] = {
  1736. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1737. };
  1738. static const struct snd_kcontrol_new dmic4_switch[] = {
  1739. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1740. };
  1741. static const struct snd_kcontrol_new dmic5_switch[] = {
  1742. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1743. };
  1744. static const struct snd_kcontrol_new dmic6_switch[] = {
  1745. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1746. };
  1747. static const struct snd_kcontrol_new dmic7_switch[] = {
  1748. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1749. };
  1750. static const struct snd_kcontrol_new dmic8_switch[] = {
  1751. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1752. };
  1753. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  1754. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1755. };
  1756. static const struct snd_kcontrol_new aux_rdac_switch[] = {
  1757. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1758. };
  1759. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  1760. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1761. };
  1762. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  1763. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1764. };
  1765. static const char * const adc2_mux_text[] = {
  1766. "INP2", "INP3"
  1767. };
  1768. static const struct soc_enum adc2_enum =
  1769. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 7,
  1770. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  1771. static const struct snd_kcontrol_new tx_adc2_mux =
  1772. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  1773. static const char * const adc3_mux_text[] = {
  1774. "INP4", "INP6"
  1775. };
  1776. static const struct soc_enum adc3_enum =
  1777. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 6,
  1778. ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
  1779. static const struct snd_kcontrol_new tx_adc3_mux =
  1780. SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
  1781. static const char * const adc4_mux_text[] = {
  1782. "INP5", "INP7"
  1783. };
  1784. static const struct soc_enum adc4_enum =
  1785. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 5,
  1786. ARRAY_SIZE(adc4_mux_text), adc4_mux_text);
  1787. static const struct snd_kcontrol_new tx_adc4_mux =
  1788. SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum);
  1789. static const char * const rdac3_mux_text[] = {
  1790. "RX1", "RX3"
  1791. };
  1792. static const char * const hdr12_mux_text[] = {
  1793. "NO_HDR12", "HDR12"
  1794. };
  1795. static const struct soc_enum hdr12_enum =
  1796. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 4,
  1797. ARRAY_SIZE(hdr12_mux_text), hdr12_mux_text);
  1798. static const struct snd_kcontrol_new tx_hdr12_mux =
  1799. SOC_DAPM_ENUM("HDR12 MUX Mux", hdr12_enum);
  1800. static const char * const hdr34_mux_text[] = {
  1801. "NO_HDR34", "HDR34"
  1802. };
  1803. static const struct soc_enum hdr34_enum =
  1804. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 3,
  1805. ARRAY_SIZE(hdr34_mux_text), hdr34_mux_text);
  1806. static const struct snd_kcontrol_new tx_hdr34_mux =
  1807. SOC_DAPM_ENUM("HDR34 MUX Mux", hdr34_enum);
  1808. static const struct soc_enum rdac3_enum =
  1809. SOC_ENUM_SINGLE(WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0,
  1810. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  1811. static const struct snd_kcontrol_new rx_rdac3_mux =
  1812. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  1813. static const struct snd_soc_dapm_widget wcd938x_dapm_widgets[] = {
  1814. /*input widgets*/
  1815. SND_SOC_DAPM_INPUT("AMIC1"),
  1816. SND_SOC_DAPM_INPUT("AMIC2"),
  1817. SND_SOC_DAPM_INPUT("AMIC3"),
  1818. SND_SOC_DAPM_INPUT("AMIC4"),
  1819. SND_SOC_DAPM_INPUT("AMIC5"),
  1820. SND_SOC_DAPM_INPUT("AMIC6"),
  1821. SND_SOC_DAPM_INPUT("AMIC7"),
  1822. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  1823. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  1824. SND_SOC_DAPM_INPUT("IN3_AUX"),
  1825. /*tx widgets*/
  1826. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  1827. wcd938x_codec_enable_adc,
  1828. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1829. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
  1830. wcd938x_codec_enable_adc,
  1831. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1832. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
  1833. wcd938x_codec_enable_adc,
  1834. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1835. SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0,
  1836. wcd938x_codec_enable_adc,
  1837. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1838. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  1839. wcd938x_codec_enable_dmic,
  1840. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1841. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  1842. wcd938x_codec_enable_dmic,
  1843. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1844. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  1845. wcd938x_codec_enable_dmic,
  1846. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1847. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  1848. wcd938x_codec_enable_dmic,
  1849. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1850. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  1851. wcd938x_codec_enable_dmic,
  1852. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1853. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  1854. wcd938x_codec_enable_dmic,
  1855. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1856. SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0,
  1857. wcd938x_codec_enable_dmic,
  1858. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1859. SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0,
  1860. wcd938x_codec_enable_dmic,
  1861. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1862. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  1863. NULL, 0, wcd938x_enable_req,
  1864. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1865. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0,
  1866. NULL, 0, wcd938x_enable_req,
  1867. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1868. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0,
  1869. NULL, 0, wcd938x_enable_req,
  1870. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1871. SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0,
  1872. NULL, 0, wcd938x_enable_req,
  1873. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1874. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  1875. &tx_adc2_mux),
  1876. SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0,
  1877. &tx_adc3_mux),
  1878. SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0,
  1879. &tx_adc4_mux),
  1880. SND_SOC_DAPM_MUX("HDR12 MUX", SND_SOC_NOPM, 0, 0,
  1881. &tx_hdr12_mux),
  1882. SND_SOC_DAPM_MUX("HDR34 MUX", SND_SOC_NOPM, 0, 0,
  1883. &tx_hdr34_mux),
  1884. /*tx mixers*/
  1885. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0,
  1886. adc1_switch, ARRAY_SIZE(adc1_switch),
  1887. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1888. SND_SOC_DAPM_POST_PMD),
  1889. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 0, 0,
  1890. adc2_switch, ARRAY_SIZE(adc2_switch),
  1891. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1892. SND_SOC_DAPM_POST_PMD),
  1893. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 0, 0, adc3_switch,
  1894. ARRAY_SIZE(adc3_switch), wcd938x_tx_swr_ctrl,
  1895. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1896. SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, 0, 0, adc4_switch,
  1897. ARRAY_SIZE(adc4_switch), wcd938x_tx_swr_ctrl,
  1898. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1899. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0,
  1900. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  1901. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1902. SND_SOC_DAPM_POST_PMD),
  1903. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 0,
  1904. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  1905. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1906. SND_SOC_DAPM_POST_PMD),
  1907. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 0,
  1908. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  1909. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1910. SND_SOC_DAPM_POST_PMD),
  1911. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 0,
  1912. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  1913. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1914. SND_SOC_DAPM_POST_PMD),
  1915. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 0,
  1916. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  1917. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1918. SND_SOC_DAPM_POST_PMD),
  1919. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 0,
  1920. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  1921. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1922. SND_SOC_DAPM_POST_PMD),
  1923. SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, 0,
  1924. 0, dmic7_switch, ARRAY_SIZE(dmic7_switch),
  1925. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1926. SND_SOC_DAPM_POST_PMD),
  1927. SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, 0,
  1928. 0, dmic8_switch, ARRAY_SIZE(dmic8_switch),
  1929. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1930. SND_SOC_DAPM_POST_PMD),
  1931. /* micbias widgets*/
  1932. SND_SOC_DAPM_MICBIAS_E("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  1933. wcd938x_codec_enable_micbias,
  1934. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1935. SND_SOC_DAPM_POST_PMD),
  1936. SND_SOC_DAPM_MICBIAS_E("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  1937. wcd938x_codec_enable_micbias,
  1938. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1939. SND_SOC_DAPM_POST_PMD),
  1940. SND_SOC_DAPM_MICBIAS_E("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  1941. wcd938x_codec_enable_micbias,
  1942. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1943. SND_SOC_DAPM_POST_PMD),
  1944. SND_SOC_DAPM_MICBIAS_E("MIC BIAS4", SND_SOC_NOPM, 0, 0,
  1945. wcd938x_codec_enable_micbias,
  1946. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1947. SND_SOC_DAPM_POST_PMD),
  1948. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  1949. wcd938x_enable_clsh,
  1950. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1951. /*rx widgets*/
  1952. SND_SOC_DAPM_PGA_E("EAR PGA", WCD938X_ANA_EAR, 7, 0, NULL, 0,
  1953. wcd938x_codec_enable_ear_pa,
  1954. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1955. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1956. SND_SOC_DAPM_PGA_E("AUX PGA", WCD938X_AUX_AUXPA, 7, 0, NULL, 0,
  1957. wcd938x_codec_enable_aux_pa,
  1958. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1959. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1960. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD938X_ANA_HPH, 7, 0, NULL, 0,
  1961. wcd938x_codec_enable_hphl_pa,
  1962. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1963. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1964. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD938X_ANA_HPH, 6, 0, NULL, 0,
  1965. wcd938x_codec_enable_hphr_pa,
  1966. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1967. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1968. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  1969. wcd938x_codec_hphl_dac_event,
  1970. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1971. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1972. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  1973. wcd938x_codec_hphr_dac_event,
  1974. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1975. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1976. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  1977. wcd938x_codec_ear_dac_event,
  1978. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1979. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1980. SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
  1981. wcd938x_codec_aux_dac_event,
  1982. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1983. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1984. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  1985. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  1986. wcd938x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  1987. SND_SOC_DAPM_POST_PMD),
  1988. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  1989. wcd938x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  1990. SND_SOC_DAPM_POST_PMD),
  1991. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  1992. wcd938x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  1993. SND_SOC_DAPM_POST_PMD),
  1994. /* rx mixer widgets*/
  1995. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  1996. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  1997. SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
  1998. aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
  1999. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  2000. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  2001. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  2002. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  2003. /*output widgets tx*/
  2004. SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
  2005. SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
  2006. SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
  2007. SND_SOC_DAPM_OUTPUT("ADC4_OUTPUT"),
  2008. SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
  2009. SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
  2010. SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
  2011. SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
  2012. SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
  2013. SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
  2014. SND_SOC_DAPM_OUTPUT("DMIC7_OUTPUT"),
  2015. SND_SOC_DAPM_OUTPUT("DMIC8_OUTPUT"),
  2016. /*output widgets rx*/
  2017. SND_SOC_DAPM_OUTPUT("EAR"),
  2018. SND_SOC_DAPM_OUTPUT("AUX"),
  2019. SND_SOC_DAPM_OUTPUT("HPHL"),
  2020. SND_SOC_DAPM_OUTPUT("HPHR"),
  2021. };
  2022. static const struct snd_soc_dapm_route wcd938x_audio_map[] = {
  2023. {"ADC1_OUTPUT", NULL, "ADC1_MIXER"},
  2024. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  2025. {"ADC1 REQ", NULL, "ADC1"},
  2026. {"ADC1", NULL, "AMIC1"},
  2027. {"ADC2_OUTPUT", NULL, "ADC2_MIXER"},
  2028. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  2029. {"ADC2 REQ", NULL, "ADC2"},
  2030. {"ADC2", NULL, "HDR12 MUX"},
  2031. {"HDR12 MUX", "NO_HDR12", "ADC2 MUX"},
  2032. {"HDR12 MUX", "HDR12", "AMIC1"},
  2033. {"ADC2 MUX", "INP3", "AMIC3"},
  2034. {"ADC2 MUX", "INP2", "AMIC2"},
  2035. {"ADC3_OUTPUT", NULL, "ADC3_MIXER"},
  2036. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  2037. {"ADC3 REQ", NULL, "ADC3"},
  2038. {"ADC3", NULL, "HDR34 MUX"},
  2039. {"HDR34 MUX", "NO_HDR34", "ADC3 MUX"},
  2040. {"HDR34 MUX", "HDR34", "AMIC5"},
  2041. {"ADC3 MUX", "INP4", "AMIC4"},
  2042. {"ADC3 MUX", "INP6", "AMIC6"},
  2043. {"ADC4_OUTPUT", NULL, "ADC4_MIXER"},
  2044. {"ADC4_MIXER", "Switch", "ADC4 REQ"},
  2045. {"ADC4 REQ", NULL, "ADC4"},
  2046. {"ADC4", NULL, "ADC4 MUX"},
  2047. {"ADC4 MUX", "INP5", "AMIC5"},
  2048. {"ADC4 MUX", "INP7", "AMIC7"},
  2049. {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
  2050. {"DMIC1_MIXER", "Switch", "DMIC1"},
  2051. {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
  2052. {"DMIC2_MIXER", "Switch", "DMIC2"},
  2053. {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
  2054. {"DMIC3_MIXER", "Switch", "DMIC3"},
  2055. {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
  2056. {"DMIC4_MIXER", "Switch", "DMIC4"},
  2057. {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
  2058. {"DMIC5_MIXER", "Switch", "DMIC5"},
  2059. {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
  2060. {"DMIC6_MIXER", "Switch", "DMIC6"},
  2061. {"DMIC7_OUTPUT", NULL, "DMIC7_MIXER"},
  2062. {"DMIC7_MIXER", "Switch", "DMIC7"},
  2063. {"DMIC8_OUTPUT", NULL, "DMIC8_MIXER"},
  2064. {"DMIC8_MIXER", "Switch", "DMIC8"},
  2065. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  2066. {"RX1", NULL, "IN1_HPHL"},
  2067. {"RDAC1", NULL, "RX1"},
  2068. {"HPHL_RDAC", "Switch", "RDAC1"},
  2069. {"HPHL PGA", NULL, "HPHL_RDAC"},
  2070. {"HPHL", NULL, "HPHL PGA"},
  2071. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  2072. {"RX2", NULL, "IN2_HPHR"},
  2073. {"RDAC2", NULL, "RX2"},
  2074. {"HPHR_RDAC", "Switch", "RDAC2"},
  2075. {"HPHR PGA", NULL, "HPHR_RDAC"},
  2076. {"HPHR", NULL, "HPHR PGA"},
  2077. {"IN3_AUX", NULL, "CLS_H_PORT"},
  2078. {"RX3", NULL, "IN3_AUX"},
  2079. {"RDAC4", NULL, "RX3"},
  2080. {"AUX_RDAC", "Switch", "RDAC4"},
  2081. {"AUX PGA", NULL, "AUX_RDAC"},
  2082. {"AUX", NULL, "AUX PGA"},
  2083. {"RDAC3_MUX", "RX3", "RX3"},
  2084. {"RDAC3_MUX", "RX1", "RX1"},
  2085. {"RDAC3", NULL, "RDAC3_MUX"},
  2086. {"EAR_RDAC", "Switch", "RDAC3"},
  2087. {"EAR PGA", NULL, "EAR_RDAC"},
  2088. {"EAR", NULL, "EAR PGA"},
  2089. };
  2090. static ssize_t wcd938x_version_read(struct snd_info_entry *entry,
  2091. void *file_private_data,
  2092. struct file *file,
  2093. char __user *buf, size_t count,
  2094. loff_t pos)
  2095. {
  2096. struct wcd938x_priv *priv;
  2097. char buffer[WCD938X_VERSION_ENTRY_SIZE];
  2098. int len = 0;
  2099. priv = (struct wcd938x_priv *) entry->private_data;
  2100. if (!priv) {
  2101. pr_err("%s: wcd938x priv is null\n", __func__);
  2102. return -EINVAL;
  2103. }
  2104. switch (priv->version) {
  2105. case WCD938X_VERSION_1_0:
  2106. len = snprintf(buffer, sizeof(buffer), "WCD938X_1_0\n");
  2107. break;
  2108. default:
  2109. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2110. }
  2111. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2112. }
  2113. static struct snd_info_entry_ops wcd938x_info_ops = {
  2114. .read = wcd938x_version_read,
  2115. };
  2116. /*
  2117. * wcd938x_info_create_codec_entry - creates wcd938x module
  2118. * @codec_root: The parent directory
  2119. * @component: component instance
  2120. *
  2121. * Creates wcd938x module and version entry under the given
  2122. * parent directory.
  2123. *
  2124. * Return: 0 on success or negative error code on failure.
  2125. */
  2126. int wcd938x_info_create_codec_entry(struct snd_info_entry *codec_root,
  2127. struct snd_soc_component *component)
  2128. {
  2129. struct snd_info_entry *version_entry;
  2130. struct wcd938x_priv *priv;
  2131. struct snd_soc_card *card;
  2132. if (!codec_root || !component)
  2133. return -EINVAL;
  2134. priv = snd_soc_component_get_drvdata(component);
  2135. if (priv->entry) {
  2136. dev_dbg(priv->dev,
  2137. "%s:wcd938x module already created\n", __func__);
  2138. return 0;
  2139. }
  2140. card = component->card;
  2141. priv->entry = snd_info_create_subdir(codec_root->module,
  2142. "wcd938x", codec_root);
  2143. if (!priv->entry) {
  2144. dev_dbg(component->dev, "%s: failed to create wcd938x entry\n",
  2145. __func__);
  2146. return -ENOMEM;
  2147. }
  2148. version_entry = snd_info_create_card_entry(card->snd_card,
  2149. "version",
  2150. priv->entry);
  2151. if (!version_entry) {
  2152. dev_dbg(component->dev, "%s: failed to create wcd938x version entry\n",
  2153. __func__);
  2154. return -ENOMEM;
  2155. }
  2156. version_entry->private_data = priv;
  2157. version_entry->size = WCD938X_VERSION_ENTRY_SIZE;
  2158. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  2159. version_entry->c.ops = &wcd938x_info_ops;
  2160. if (snd_info_register(version_entry) < 0) {
  2161. snd_info_free_entry(version_entry);
  2162. return -ENOMEM;
  2163. }
  2164. priv->version_entry = version_entry;
  2165. return 0;
  2166. }
  2167. EXPORT_SYMBOL(wcd938x_info_create_codec_entry);
  2168. static int wcd938x_soc_codec_probe(struct snd_soc_component *component)
  2169. {
  2170. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2171. struct snd_soc_dapm_context *dapm =
  2172. snd_soc_component_get_dapm(component);
  2173. int variant;
  2174. int ret = -EINVAL;
  2175. dev_info(component->dev, "%s()\n", __func__);
  2176. wcd938x = snd_soc_component_get_drvdata(component);
  2177. if (!wcd938x)
  2178. return -EINVAL;
  2179. wcd938x->component = component;
  2180. snd_soc_component_init_regmap(component, wcd938x->regmap);
  2181. variant = (snd_soc_component_read32(component,
  2182. WCD938X_DIGITAL_EFUSE_REG_0) & 0x1E) >> 1;
  2183. wcd938x->variant = variant;
  2184. wcd938x->fw_data = devm_kzalloc(component->dev,
  2185. sizeof(*(wcd938x->fw_data)),
  2186. GFP_KERNEL);
  2187. if (!wcd938x->fw_data) {
  2188. dev_err(component->dev, "Failed to allocate fw_data\n");
  2189. ret = -ENOMEM;
  2190. goto err;
  2191. }
  2192. set_bit(WCD9XXX_MBHC_CAL, wcd938x->fw_data->cal_bit);
  2193. ret = wcd_cal_create_hwdep(wcd938x->fw_data,
  2194. WCD9XXX_CODEC_HWDEP_NODE, component);
  2195. if (ret < 0) {
  2196. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  2197. goto err_hwdep;
  2198. }
  2199. ret = wcd938x_mbhc_init(&wcd938x->mbhc, component, wcd938x->fw_data);
  2200. if (ret) {
  2201. pr_err("%s: mbhc initialization failed\n", __func__);
  2202. goto err_hwdep;
  2203. }
  2204. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  2205. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  2206. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  2207. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  2208. snd_soc_dapm_ignore_suspend(dapm, "AMIC5");
  2209. snd_soc_dapm_ignore_suspend(dapm, "AMIC6");
  2210. snd_soc_dapm_ignore_suspend(dapm, "AMIC7");
  2211. snd_soc_dapm_ignore_suspend(dapm, "DMIC1_OUTPUT");
  2212. snd_soc_dapm_ignore_suspend(dapm, "DMIC2_OUTPUT");
  2213. snd_soc_dapm_ignore_suspend(dapm, "DMIC3_OUTPUT");
  2214. snd_soc_dapm_ignore_suspend(dapm, "DMIC4_OUTPUT");
  2215. snd_soc_dapm_ignore_suspend(dapm, "DMIC5_OUTPUT");
  2216. snd_soc_dapm_ignore_suspend(dapm, "DMIC6_OUTPUT");
  2217. snd_soc_dapm_ignore_suspend(dapm, "DMIC7_OUTPUT");
  2218. snd_soc_dapm_ignore_suspend(dapm, "DMIC8_OUTPUT");
  2219. snd_soc_dapm_ignore_suspend(dapm, "ADC1_OUTPUT");
  2220. snd_soc_dapm_ignore_suspend(dapm, "ADC2_OUTPUT");
  2221. snd_soc_dapm_ignore_suspend(dapm, "ADC3_OUTPUT");
  2222. snd_soc_dapm_ignore_suspend(dapm, "ADC4_OUTPUT");
  2223. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  2224. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  2225. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  2226. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  2227. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  2228. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  2229. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  2230. snd_soc_dapm_sync(dapm);
  2231. wcd_cls_h_init(&wcd938x->clsh_info);
  2232. wcd938x_init_reg(component);
  2233. if (wcd938x->variant == WCD9380) {
  2234. ret = snd_soc_add_component_controls(component, wcd9380_snd_controls,
  2235. ARRAY_SIZE(wcd9380_snd_controls));
  2236. if (ret < 0) {
  2237. dev_err(component->dev,
  2238. "%s: Failed to add snd ctrls for variant: %d\n",
  2239. __func__, wcd938x->variant);
  2240. goto err_hwdep;
  2241. }
  2242. }
  2243. if (wcd938x->variant == WCD9385) {
  2244. ret = snd_soc_add_component_controls(component, wcd9385_snd_controls,
  2245. ARRAY_SIZE(wcd9385_snd_controls));
  2246. if (ret < 0) {
  2247. dev_err(component->dev,
  2248. "%s: Failed to add snd ctrls for variant: %d\n",
  2249. __func__, wcd938x->variant);
  2250. goto err_hwdep;
  2251. }
  2252. }
  2253. wcd938x->version = WCD938X_VERSION_1_0;
  2254. /* Register event notifier */
  2255. wcd938x->nblock.notifier_call = wcd938x_event_notify;
  2256. if (wcd938x->register_notifier) {
  2257. ret = wcd938x->register_notifier(wcd938x->handle,
  2258. &wcd938x->nblock,
  2259. true);
  2260. if (ret) {
  2261. dev_err(component->dev,
  2262. "%s: Failed to register notifier %d\n",
  2263. __func__, ret);
  2264. return ret;
  2265. }
  2266. }
  2267. return ret;
  2268. err_hwdep:
  2269. wcd938x->fw_data = NULL;
  2270. err:
  2271. return ret;
  2272. }
  2273. static void wcd938x_soc_codec_remove(struct snd_soc_component *component)
  2274. {
  2275. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2276. if (!wcd938x) {
  2277. dev_err(component->dev, "%s: wcd938x is already NULL\n",
  2278. __func__);
  2279. return;
  2280. }
  2281. if (wcd938x->register_notifier)
  2282. wcd938x->register_notifier(wcd938x->handle,
  2283. &wcd938x->nblock,
  2284. false);
  2285. }
  2286. static struct snd_soc_component_driver soc_codec_dev_wcd938x = {
  2287. .name = WCD938X_DRV_NAME,
  2288. .probe = wcd938x_soc_codec_probe,
  2289. .remove = wcd938x_soc_codec_remove,
  2290. .controls = wcd938x_snd_controls,
  2291. .num_controls = ARRAY_SIZE(wcd938x_snd_controls),
  2292. .dapm_widgets = wcd938x_dapm_widgets,
  2293. .num_dapm_widgets = ARRAY_SIZE(wcd938x_dapm_widgets),
  2294. .dapm_routes = wcd938x_audio_map,
  2295. .num_dapm_routes = ARRAY_SIZE(wcd938x_audio_map),
  2296. };
  2297. static int wcd938x_reset(struct device *dev)
  2298. {
  2299. struct wcd938x_priv *wcd938x = NULL;
  2300. int rc = 0;
  2301. int value = 0;
  2302. if (!dev)
  2303. return -ENODEV;
  2304. wcd938x = dev_get_drvdata(dev);
  2305. if (!wcd938x)
  2306. return -EINVAL;
  2307. if (!wcd938x->rst_np) {
  2308. dev_err(dev, "%s: reset gpio device node not specified\n",
  2309. __func__);
  2310. return -EINVAL;
  2311. }
  2312. value = msm_cdc_pinctrl_get_state(wcd938x->rst_np);
  2313. if (value > 0)
  2314. return 0;
  2315. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  2316. if (rc) {
  2317. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2318. __func__);
  2319. return rc;
  2320. }
  2321. /* 20us sleep required after pulling the reset gpio to LOW */
  2322. usleep_range(20, 30);
  2323. rc = msm_cdc_pinctrl_select_active_state(wcd938x->rst_np);
  2324. if (rc) {
  2325. dev_err(dev, "%s: wcd active state request fail!\n",
  2326. __func__);
  2327. return rc;
  2328. }
  2329. /* 20us sleep required after pulling the reset gpio to HIGH */
  2330. usleep_range(20, 30);
  2331. return rc;
  2332. }
  2333. static int wcd938x_read_of_property_u32(struct device *dev, const char *name,
  2334. u32 *val)
  2335. {
  2336. int rc = 0;
  2337. rc = of_property_read_u32(dev->of_node, name, val);
  2338. if (rc)
  2339. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2340. __func__, name, dev->of_node->full_name);
  2341. return rc;
  2342. }
  2343. static void wcd938x_dt_parse_micbias_info(struct device *dev,
  2344. struct wcd938x_micbias_setting *mb)
  2345. {
  2346. u32 prop_val = 0;
  2347. int rc = 0;
  2348. /* MB1 */
  2349. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  2350. NULL)) {
  2351. rc = wcd938x_read_of_property_u32(dev,
  2352. "qcom,cdc-micbias1-mv",
  2353. &prop_val);
  2354. if (!rc)
  2355. mb->micb1_mv = prop_val;
  2356. } else {
  2357. dev_info(dev, "%s: Micbias1 DT property not found\n",
  2358. __func__);
  2359. }
  2360. /* MB2 */
  2361. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  2362. NULL)) {
  2363. rc = wcd938x_read_of_property_u32(dev,
  2364. "qcom,cdc-micbias2-mv",
  2365. &prop_val);
  2366. if (!rc)
  2367. mb->micb2_mv = prop_val;
  2368. } else {
  2369. dev_info(dev, "%s: Micbias2 DT property not found\n",
  2370. __func__);
  2371. }
  2372. /* MB3 */
  2373. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  2374. NULL)) {
  2375. rc = wcd938x_read_of_property_u32(dev,
  2376. "qcom,cdc-micbias3-mv",
  2377. &prop_val);
  2378. if (!rc)
  2379. mb->micb3_mv = prop_val;
  2380. } else {
  2381. dev_info(dev, "%s: Micbias3 DT property not found\n",
  2382. __func__);
  2383. }
  2384. }
  2385. static int wcd938x_reset_low(struct device *dev)
  2386. {
  2387. struct wcd938x_priv *wcd938x = NULL;
  2388. int rc = 0;
  2389. if (!dev)
  2390. return -ENODEV;
  2391. wcd938x = dev_get_drvdata(dev);
  2392. if (!wcd938x)
  2393. return -EINVAL;
  2394. if (!wcd938x->rst_np) {
  2395. dev_err(dev, "%s: reset gpio device node not specified\n",
  2396. __func__);
  2397. return -EINVAL;
  2398. }
  2399. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  2400. if (rc) {
  2401. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2402. __func__);
  2403. return rc;
  2404. }
  2405. /* 20us sleep required after pulling the reset gpio to LOW */
  2406. usleep_range(20, 30);
  2407. return rc;
  2408. }
  2409. struct wcd938x_pdata *wcd938x_populate_dt_data(struct device *dev)
  2410. {
  2411. struct wcd938x_pdata *pdata = NULL;
  2412. pdata = devm_kzalloc(dev, sizeof(struct wcd938x_pdata),
  2413. GFP_KERNEL);
  2414. if (!pdata)
  2415. return NULL;
  2416. pdata->rst_np = of_parse_phandle(dev->of_node,
  2417. "qcom,wcd-rst-gpio-node", 0);
  2418. if (!pdata->rst_np) {
  2419. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2420. __func__, "qcom,wcd-rst-gpio-node",
  2421. dev->of_node->full_name);
  2422. return NULL;
  2423. }
  2424. /* Parse power supplies */
  2425. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  2426. &pdata->num_supplies);
  2427. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  2428. dev_err(dev, "%s: no power supplies defined for codec\n",
  2429. __func__);
  2430. return NULL;
  2431. }
  2432. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  2433. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  2434. wcd938x_dt_parse_micbias_info(dev, &pdata->micbias);
  2435. return pdata;
  2436. }
  2437. static irqreturn_t wcd938x_wd_handle_irq(int irq, void *data)
  2438. {
  2439. pr_err_ratelimited("%s: Watchdog interrupt for irq =%d triggered\n",
  2440. __func__, irq);
  2441. return IRQ_HANDLED;
  2442. }
  2443. static int wcd938x_bind(struct device *dev)
  2444. {
  2445. int ret = 0, i = 0;
  2446. struct wcd938x_pdata *pdata = dev_get_platdata(dev);
  2447. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  2448. /*
  2449. * Add 5msec delay to provide sufficient time for
  2450. * soundwire auto enumeration of slave devices as
  2451. * as per HW requirement.
  2452. */
  2453. usleep_range(5000, 5010);
  2454. ret = component_bind_all(dev, wcd938x);
  2455. if (ret) {
  2456. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  2457. __func__, ret);
  2458. return ret;
  2459. }
  2460. wcd938x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  2461. if (!wcd938x->rx_swr_dev) {
  2462. dev_err(dev, "%s: Could not find RX swr slave device\n",
  2463. __func__);
  2464. ret = -ENODEV;
  2465. goto err;
  2466. }
  2467. wcd938x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  2468. if (!wcd938x->tx_swr_dev) {
  2469. dev_err(dev, "%s: Could not find TX swr slave device\n",
  2470. __func__);
  2471. ret = -ENODEV;
  2472. goto err;
  2473. }
  2474. wcd938x->regmap = devm_regmap_init_swr(wcd938x->tx_swr_dev,
  2475. &wcd938x_regmap_config);
  2476. if (!wcd938x->regmap) {
  2477. dev_err(dev, "%s: Regmap init failed\n",
  2478. __func__);
  2479. goto err;
  2480. }
  2481. /* Set all interupts as edge triggered */
  2482. for (i = 0; i < wcd938x_regmap_irq_chip.num_regs; i++)
  2483. regmap_write(wcd938x->regmap,
  2484. (WCD938X_DIGITAL_INTR_LEVEL_0 + i), 0);
  2485. wcd938x_regmap_irq_chip.irq_drv_data = wcd938x;
  2486. wcd938x->irq_info.wcd_regmap_irq_chip = &wcd938x_regmap_irq_chip;
  2487. wcd938x->irq_info.codec_name = "WCD938X";
  2488. wcd938x->irq_info.regmap = wcd938x->regmap;
  2489. wcd938x->irq_info.dev = dev;
  2490. ret = wcd_irq_init(&wcd938x->irq_info, &wcd938x->virq);
  2491. if (ret) {
  2492. dev_err(wcd938x->dev, "%s: IRQ init failed: %d\n",
  2493. __func__, ret);
  2494. goto err;
  2495. }
  2496. wcd938x->tx_swr_dev->slave_irq = wcd938x->virq;
  2497. /* Request for watchdog interrupt */
  2498. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT,
  2499. "HPHR PDM WD INT", wcd938x_wd_handle_irq, NULL);
  2500. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT,
  2501. "HPHL PDM WD INT", wcd938x_wd_handle_irq, NULL);
  2502. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT,
  2503. "AUX PDM WD INT", wcd938x_wd_handle_irq, NULL);
  2504. /* Enable watchdog interrupt for HPH and AUX */
  2505. wcd_enable_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT);
  2506. wcd_enable_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT);
  2507. wcd_enable_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT);
  2508. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd938x,
  2509. NULL, 0);
  2510. if (ret) {
  2511. dev_err(dev, "%s: Codec registration failed\n",
  2512. __func__);
  2513. goto err_irq;
  2514. }
  2515. return ret;
  2516. err_irq:
  2517. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  2518. err:
  2519. component_unbind_all(dev, wcd938x);
  2520. return ret;
  2521. }
  2522. static void wcd938x_unbind(struct device *dev)
  2523. {
  2524. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  2525. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  2526. snd_soc_unregister_component(dev);
  2527. component_unbind_all(dev, wcd938x);
  2528. }
  2529. static const struct of_device_id wcd938x_dt_match[] = {
  2530. { .compatible = "qcom,wcd938x-codec" },
  2531. {}
  2532. };
  2533. static const struct component_master_ops wcd938x_comp_ops = {
  2534. .bind = wcd938x_bind,
  2535. .unbind = wcd938x_unbind,
  2536. };
  2537. static int wcd938x_compare_of(struct device *dev, void *data)
  2538. {
  2539. return dev->of_node == data;
  2540. }
  2541. static void wcd938x_release_of(struct device *dev, void *data)
  2542. {
  2543. of_node_put(data);
  2544. }
  2545. static int wcd938x_add_slave_components(struct device *dev,
  2546. struct component_match **matchptr)
  2547. {
  2548. struct device_node *np, *rx_node, *tx_node;
  2549. np = dev->of_node;
  2550. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  2551. if (!rx_node) {
  2552. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  2553. return -ENODEV;
  2554. }
  2555. of_node_get(rx_node);
  2556. component_match_add_release(dev, matchptr,
  2557. wcd938x_release_of,
  2558. wcd938x_compare_of,
  2559. rx_node);
  2560. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  2561. if (!tx_node) {
  2562. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  2563. return -ENODEV;
  2564. }
  2565. of_node_get(tx_node);
  2566. component_match_add_release(dev, matchptr,
  2567. wcd938x_release_of,
  2568. wcd938x_compare_of,
  2569. tx_node);
  2570. return 0;
  2571. }
  2572. static int wcd938x_wakeup(void *handle, bool enable)
  2573. {
  2574. struct wcd938x_priv *priv;
  2575. if (!handle) {
  2576. pr_err("%s: NULL handle\n", __func__);
  2577. return -EINVAL;
  2578. }
  2579. priv = (struct wcd938x_priv *)handle;
  2580. if (!priv->tx_swr_dev) {
  2581. pr_err("%s: tx swr dev is NULL\n", __func__);
  2582. return -EINVAL;
  2583. }
  2584. if (enable)
  2585. return swr_device_wakeup_vote(priv->tx_swr_dev);
  2586. else
  2587. return swr_device_wakeup_unvote(priv->tx_swr_dev);
  2588. }
  2589. static int wcd938x_probe(struct platform_device *pdev)
  2590. {
  2591. struct component_match *match = NULL;
  2592. struct wcd938x_priv *wcd938x = NULL;
  2593. struct wcd938x_pdata *pdata = NULL;
  2594. struct wcd_ctrl_platform_data *plat_data = NULL;
  2595. struct device *dev = &pdev->dev;
  2596. int ret;
  2597. wcd938x = devm_kzalloc(dev, sizeof(struct wcd938x_priv),
  2598. GFP_KERNEL);
  2599. if (!wcd938x)
  2600. return -ENOMEM;
  2601. dev_set_drvdata(dev, wcd938x);
  2602. wcd938x->dev = dev;
  2603. pdata = wcd938x_populate_dt_data(dev);
  2604. if (!pdata) {
  2605. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  2606. return -EINVAL;
  2607. }
  2608. dev->platform_data = pdata;
  2609. wcd938x->rst_np = pdata->rst_np;
  2610. ret = msm_cdc_init_supplies(dev, &wcd938x->supplies,
  2611. pdata->regulator, pdata->num_supplies);
  2612. if (!wcd938x->supplies) {
  2613. dev_err(dev, "%s: Cannot init wcd supplies\n",
  2614. __func__);
  2615. return ret;
  2616. }
  2617. plat_data = dev_get_platdata(dev->parent);
  2618. if (!plat_data) {
  2619. dev_err(dev, "%s: platform data from parent is NULL\n",
  2620. __func__);
  2621. return -EINVAL;
  2622. }
  2623. wcd938x->handle = (void *)plat_data->handle;
  2624. if (!wcd938x->handle) {
  2625. dev_err(dev, "%s: handle is NULL\n", __func__);
  2626. return -EINVAL;
  2627. }
  2628. wcd938x->update_wcd_event = plat_data->update_wcd_event;
  2629. if (!wcd938x->update_wcd_event) {
  2630. dev_err(dev, "%s: update_wcd_event api is null!\n",
  2631. __func__);
  2632. return -EINVAL;
  2633. }
  2634. wcd938x->register_notifier = plat_data->register_notifier;
  2635. if (!wcd938x->register_notifier) {
  2636. dev_err(dev, "%s: register_notifier api is null!\n",
  2637. __func__);
  2638. return -EINVAL;
  2639. }
  2640. ret = msm_cdc_enable_static_supplies(&pdev->dev, wcd938x->supplies,
  2641. pdata->regulator,
  2642. pdata->num_supplies);
  2643. if (ret) {
  2644. dev_err(dev, "%s: wcd static supply enable failed!\n",
  2645. __func__);
  2646. return ret;
  2647. }
  2648. ret = wcd938x_parse_port_mapping(dev, "qcom,rx_swr_ch_map",
  2649. CODEC_RX);
  2650. ret |= wcd938x_parse_port_mapping(dev, "qcom,tx_swr_ch_map",
  2651. CODEC_TX);
  2652. if (ret) {
  2653. dev_err(dev, "Failed to read port mapping\n");
  2654. goto err;
  2655. }
  2656. ret = wcd938x_add_slave_components(dev, &match);
  2657. if (ret)
  2658. goto err;
  2659. wcd938x_reset(dev);
  2660. wcd938x->wakeup = wcd938x_wakeup;
  2661. return component_master_add_with_match(dev,
  2662. &wcd938x_comp_ops, match);
  2663. err:
  2664. return ret;
  2665. }
  2666. static int wcd938x_remove(struct platform_device *pdev)
  2667. {
  2668. component_master_del(&pdev->dev, &wcd938x_comp_ops);
  2669. dev_set_drvdata(&pdev->dev, NULL);
  2670. return 0;
  2671. }
  2672. #ifdef CONFIG_PM_SLEEP
  2673. static int wcd938x_suspend(struct device *dev)
  2674. {
  2675. return 0;
  2676. }
  2677. static int wcd938x_resume(struct device *dev)
  2678. {
  2679. return 0;
  2680. }
  2681. static const struct dev_pm_ops wcd938x_dev_pm_ops = {
  2682. SET_SYSTEM_SLEEP_PM_OPS(
  2683. wcd938x_suspend,
  2684. wcd938x_resume
  2685. )
  2686. };
  2687. #endif
  2688. static struct platform_driver wcd938x_codec_driver = {
  2689. .probe = wcd938x_probe,
  2690. .remove = wcd938x_remove,
  2691. .driver = {
  2692. .name = "wcd938x_codec",
  2693. .owner = THIS_MODULE,
  2694. .of_match_table = of_match_ptr(wcd938x_dt_match),
  2695. #ifdef CONFIG_PM_SLEEP
  2696. .pm = &wcd938x_dev_pm_ops,
  2697. #endif
  2698. .suppress_bind_attrs = true,
  2699. },
  2700. };
  2701. module_platform_driver(wcd938x_codec_driver);
  2702. MODULE_DESCRIPTION("WCD938X Codec driver");
  2703. MODULE_LICENSE("GPL v2");