wsa884x.c 71 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/module.h>
  7. #include <linux/init.h>
  8. #include <linux/slab.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/device.h>
  11. #include <linux/printk.h>
  12. #include <linux/bitops.h>
  13. #include <linux/regulator/consumer.h>
  14. #include <linux/pm_runtime.h>
  15. #include <linux/delay.h>
  16. #include <linux/kernel.h>
  17. #include <linux/gpio.h>
  18. #include <linux/of_gpio.h>
  19. #include <linux/of_platform.h>
  20. #include <linux/regmap.h>
  21. #include <linux/debugfs.h>
  22. #include <soc/soundwire.h>
  23. #include <sound/pcm.h>
  24. #include <sound/pcm_params.h>
  25. #include <sound/soc.h>
  26. #include <sound/soc-dapm.h>
  27. #include <sound/tlv.h>
  28. #include <asoc/msm-cdc-pinctrl.h>
  29. #include <asoc/msm-cdc-supply.h>
  30. #include "wsa884x-registers.h"
  31. #include "wsa884x.h"
  32. #include "internal.h"
  33. #include "asoc/bolero-slave-internal.h"
  34. #include <linux/qti-regmap-debugfs.h>
  35. #define T1_TEMP -10
  36. #define T2_TEMP 150
  37. #define LOW_TEMP_THRESHOLD 5
  38. #define HIGH_TEMP_THRESHOLD 45
  39. #define TEMP_INVALID 0xFFFF
  40. #define WSA884X_TEMP_RETRY 3
  41. #define WSA884X_IRQ_RETRY 2
  42. #define PBR_MAX_VOLTAGE 20
  43. #define PBR_MAX_CODE 255
  44. #define WSA884X_IDLE_DETECT_NG_BLOCK_MASK 0x38
  45. #define MAX_NAME_LEN 40
  46. #define WSA884X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  47. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  48. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
  49. SNDRV_PCM_RATE_384000)
  50. /* Fractional Rates */
  51. #define WSA884X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  52. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
  53. #define WSA884X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  54. SNDRV_PCM_FMTBIT_S24_LE |\
  55. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
  56. #define REG_FIELD_VALUE(register_name, field_name, value) \
  57. WSA884X_##register_name, FIELD_MASK(register_name, field_name), \
  58. value << FIELD_SHIFT(register_name, field_name)
  59. enum {
  60. IDLE_DETECT,
  61. NG1,
  62. NG2,
  63. NG3,
  64. };
  65. struct wsa_temp_register {
  66. u8 d1_msb;
  67. u8 d1_lsb;
  68. u8 d2_msb;
  69. u8 d2_lsb;
  70. u8 dmeas_msb;
  71. u8 dmeas_lsb;
  72. };
  73. enum {
  74. COMP_OFFSET0,
  75. COMP_OFFSET1,
  76. COMP_OFFSET2,
  77. COMP_OFFSET3,
  78. COMP_OFFSET4,
  79. };
  80. #define WSA884X_VTH_TO_REG(vth) \
  81. ((vth) != 0 ? (((vth) - 150) * PBR_MAX_CODE / (PBR_MAX_VOLTAGE * 100) + 1) : 0)
  82. struct wsa_reg_mask_val {
  83. u16 reg;
  84. u8 mask;
  85. u8 val;
  86. };
  87. static const struct wsa_reg_mask_val reg_init[] = {
  88. {REG_FIELD_VALUE(CKWD_CTL_1, VPP_SW_CTL, 0x00)},
  89. {REG_FIELD_VALUE(CDC_SPK_DSM_A2_0, COEF_A2, 0x0A)},
  90. {REG_FIELD_VALUE(CDC_SPK_DSM_A2_1, COEF_A2, 0x08)},
  91. {REG_FIELD_VALUE(CDC_SPK_DSM_A3_0, COEF_A3, 0xF3)},
  92. {REG_FIELD_VALUE(CDC_SPK_DSM_A3_1, COEF_A3, 0x07)},
  93. {REG_FIELD_VALUE(CDC_SPK_DSM_A4_0, COEF_A4, 0x79)},
  94. {REG_FIELD_VALUE(CDC_SPK_DSM_A5_0, COEF_A5, 0x0B)},
  95. {REG_FIELD_VALUE(CDC_SPK_DSM_A6_0, COEF_A6, 0x8A)},
  96. {REG_FIELD_VALUE(CDC_SPK_DSM_A7_0, COEF_A7, 0x9B)},
  97. {REG_FIELD_VALUE(CDC_SPK_DSM_C_0, COEF_C3, 0x06)},
  98. {REG_FIELD_VALUE(CDC_SPK_DSM_C_0, COEF_C2, 0x08)},
  99. {REG_FIELD_VALUE(CDC_SPK_DSM_C_2, COEF_C7, 0x0F)},
  100. {REG_FIELD_VALUE(CDC_SPK_DSM_C_3, COEF_C7, 0x20)},
  101. {REG_FIELD_VALUE(CDC_SPK_DSM_R1, SAT_LIMIT_R1, 0x83)},
  102. {REG_FIELD_VALUE(CDC_SPK_DSM_R2, SAT_LIMIT_R2, 0x7F)},
  103. {REG_FIELD_VALUE(CDC_SPK_DSM_R3, SAT_LIMIT_R3, 0x9D)},
  104. {REG_FIELD_VALUE(CDC_SPK_DSM_R4, SAT_LIMIT_R4, 0x82)},
  105. {REG_FIELD_VALUE(CDC_SPK_DSM_R5, SAT_LIMIT_R5, 0x8B)},
  106. {REG_FIELD_VALUE(CDC_SPK_DSM_R6, SAT_LIMIT_R6, 0x9B)},
  107. {REG_FIELD_VALUE(CDC_SPK_DSM_R7, SAT_LIMIT_R7, 0x3F)},
  108. {REG_FIELD_VALUE(BOP_DEGLITCH_CTL, BOP_DEGLITCH_SETTING, 0x08)},
  109. {REG_FIELD_VALUE(VBAT_THRM_FLT_CTL, VBAT_COEF_SEL, 0x04)},
  110. {REG_FIELD_VALUE(CLSH_CTL_0, DLY_CODE, 0x06)},
  111. {REG_FIELD_VALUE(CLSH_SOFT_MAX, SOFT_MAX, 0xFF)},
  112. {REG_FIELD_VALUE(OTP_REG_38, BOOST_ILIM_TUNE, 0x00)},
  113. {REG_FIELD_VALUE(OTP_REG_40, ISENSE_RESCAL, 0x08)},
  114. {REG_FIELD_VALUE(STB_CTRL1, SLOPE_COMP_CURRENT, 0x0D)},
  115. {REG_FIELD_VALUE(ILIM_CTRL1, ILIM_OFFSET_PB, 0x03)},
  116. {REG_FIELD_VALUE(CURRENT_LIMIT, CURRENT_LIMIT, 0x09)},
  117. {REG_FIELD_VALUE(CKWD_CTL_1, CKWD_VCOMP_VREF_SEL, 0x13)},
  118. {REG_FIELD_VALUE(BOP2_PROG, BOP2_VTH, 0x06)},
  119. {REG_FIELD_VALUE(BOP2_PROG, BOP2_HYST, 0x06)},
  120. {REG_FIELD_VALUE(VBAT_CAL_CTL, RESERVE, 0x02)},
  121. {REG_FIELD_VALUE(REF_CTRL, BG_RDY_SEL, 0x01)},
  122. {REG_FIELD_VALUE(ZX_CTRL1, ZX_DET_SW_SEL, 0x03)},
  123. };
  124. static const struct wsa_reg_mask_val reg_init_2S[] = {
  125. {REG_FIELD_VALUE(CLSH_CTL_1, SLR_MAX, 0x02)},
  126. {REG_FIELD_VALUE(CLSH_V_HD_PA, V_HD_PA, 0x13)},
  127. {REG_FIELD_VALUE(UVLO_PROG, UVLO1_VTH, 0x03)},
  128. {REG_FIELD_VALUE(UVLO_PROG, UVLO1_HYST, 0x03)},
  129. {REG_FIELD_VALUE(DAC_VCM_CTRL_REG2, DAC_VCM_SHIFT, 0x06)},
  130. {REG_FIELD_VALUE(DAC_VCM_CTRL_REG3, DAC_VCM_SHIFT, 0x14)},
  131. {REG_FIELD_VALUE(DAC_VCM_CTRL_REG4, DAC_VCM_SHIFT, 0x19)},
  132. {REG_FIELD_VALUE(DAC_VCM_CTRL_REG5, DAC_VCM_SHIFT, 0x1B)},
  133. {REG_FIELD_VALUE(DAC_VCM_CTRL_REG6, DAC_VCM_SHIFT, 0x1C)},
  134. {REG_FIELD_VALUE(DAC_VCM_CTRL_REG7, DAC_VCM_SHIFT_FINAL_OVERRIDE, 0x01)},
  135. };
  136. static int wsa884x_handle_post_irq(void *data);
  137. static int wsa884x_get_temperature(struct snd_soc_component *component,
  138. int *temp);
  139. enum {
  140. WSA8840 = 0,
  141. WSA8845 = 5,
  142. WSA8845H = 0xC,
  143. };
  144. enum {
  145. SPKR_STATUS = 0,
  146. WSA_SUPPLIES_LPM_MODE,
  147. SPKR_ADIE_LB,
  148. };
  149. enum {
  150. WSA884X_IRQ_INT_SAF2WAR = 0,
  151. WSA884X_IRQ_INT_WAR2SAF,
  152. WSA884X_IRQ_INT_DISABLE,
  153. WSA884X_IRQ_INT_OCP,
  154. WSA884X_IRQ_INT_CLIP,
  155. WSA884X_IRQ_INT_PDM_WD,
  156. WSA884X_IRQ_INT_CLK_WD,
  157. WSA884X_IRQ_INT_INTR_PIN,
  158. WSA884X_IRQ_INT_UVLO,
  159. WSA884X_IRQ_INT_PA_ON_ERR,
  160. WSA884X_NUM_IRQS,
  161. };
  162. static const struct regmap_irq wsa884x_irqs[WSA884X_NUM_IRQS] = {
  163. REGMAP_IRQ_REG(WSA884X_IRQ_INT_SAF2WAR, 0, 0x01),
  164. REGMAP_IRQ_REG(WSA884X_IRQ_INT_WAR2SAF, 0, 0x02),
  165. REGMAP_IRQ_REG(WSA884X_IRQ_INT_DISABLE, 0, 0x04),
  166. REGMAP_IRQ_REG(WSA884X_IRQ_INT_OCP, 0, 0x08),
  167. REGMAP_IRQ_REG(WSA884X_IRQ_INT_CLIP, 0, 0x10),
  168. REGMAP_IRQ_REG(WSA884X_IRQ_INT_PDM_WD, 0, 0x20),
  169. REGMAP_IRQ_REG(WSA884X_IRQ_INT_CLK_WD, 0, 0x40),
  170. REGMAP_IRQ_REG(WSA884X_IRQ_INT_INTR_PIN, 0, 0x80),
  171. REGMAP_IRQ_REG(WSA884X_IRQ_INT_UVLO, 1, 0x01),
  172. REGMAP_IRQ_REG(WSA884X_IRQ_INT_PA_ON_ERR, 1, 0x02),
  173. };
  174. static struct regmap_irq_chip wsa884x_regmap_irq_chip = {
  175. .name = "wsa884x",
  176. .irqs = wsa884x_irqs,
  177. .num_irqs = ARRAY_SIZE(wsa884x_irqs),
  178. .num_regs = 2,
  179. .status_base = WSA884X_INTR_STATUS0,
  180. .mask_base = WSA884X_INTR_MASK0,
  181. .type_base = WSA884X_INTR_LEVEL0,
  182. .ack_base = WSA884X_INTR_CLEAR0,
  183. .use_ack = 1,
  184. .runtime_pm = false,
  185. .handle_post_irq = wsa884x_handle_post_irq,
  186. .irq_drv_data = NULL,
  187. };
  188. static int wsa884x_handle_post_irq(void *data)
  189. {
  190. struct wsa884x_priv *wsa884x = data;
  191. u32 sts1 = 0, sts2 = 0;
  192. int retry = WSA884X_IRQ_RETRY;
  193. struct snd_soc_component *component = NULL;
  194. if (!wsa884x)
  195. return IRQ_NONE;
  196. component = wsa884x->component;
  197. if (!wsa884x->pa_mute) {
  198. do {
  199. wsa884x->pa_mute = 0;
  200. snd_soc_component_update_bits(component,
  201. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x01));
  202. usleep_range(1000, 1100);
  203. regmap_read(wsa884x->regmap, WSA884X_INTR_STATUS0, &sts1);
  204. regmap_read(wsa884x->regmap, WSA884X_INTR_STATUS1, &sts2);
  205. wsa884x->swr_slave->slave_irq_pending =
  206. ((sts1 || sts2) ? true : false);
  207. pr_debug("%s: IRQs Sts0: %x, Sts1: %x\n", __func__,
  208. sts1, sts2);
  209. if (wsa884x->swr_slave->slave_irq_pending) {
  210. pr_debug("%s: IRQ retries left: %0d\n",
  211. __func__, retry);
  212. snd_soc_component_update_bits(component,
  213. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x00));
  214. wsa884x->pa_mute = 1;
  215. if (retry--)
  216. usleep_range(1000, 1100);
  217. } else {
  218. break;
  219. }
  220. } while (retry);
  221. }
  222. return IRQ_HANDLED;
  223. }
  224. #ifdef CONFIG_DEBUG_FS
  225. static int codec_debug_open(struct inode *inode, struct file *file)
  226. {
  227. file->private_data = inode->i_private;
  228. return 0;
  229. }
  230. static int get_parameters(char *buf, u32 *param1, int num_of_par)
  231. {
  232. char *token;
  233. int base, cnt;
  234. token = strsep(&buf, " ");
  235. for (cnt = 0; cnt < num_of_par; cnt++) {
  236. if (token) {
  237. if ((token[1] == 'x') || (token[1] == 'X'))
  238. base = 16;
  239. else
  240. base = 10;
  241. if (kstrtou32(token, base, &param1[cnt]) != 0)
  242. return -EINVAL;
  243. token = strsep(&buf, " ");
  244. } else {
  245. return -EINVAL;
  246. }
  247. }
  248. return 0;
  249. }
  250. static bool is_swr_slave_reg_readable(int reg)
  251. {
  252. int ret = true;
  253. if (((reg > 0x46) && (reg < 0x4A)) ||
  254. ((reg > 0x4A) && (reg < 0x50)) ||
  255. ((reg > 0x55) && (reg < 0x60)) ||
  256. ((reg > 0x60) && (reg < 0x70)) ||
  257. ((reg > 0x70) && (reg < 0xC0)) ||
  258. ((reg > 0xC1) && (reg < 0xC8)) ||
  259. ((reg > 0xC8) && (reg < 0xD0)) ||
  260. ((reg > 0xD0) && (reg < 0xE0)) ||
  261. ((reg > 0xE0) && (reg < 0xF0)) ||
  262. ((reg > 0xF0) && (reg < 0x100)) ||
  263. ((reg > 0x105) && (reg < 0x120)) ||
  264. ((reg > 0x205) && (reg < 0x220)) ||
  265. ((reg > 0x305) && (reg < 0x320)) ||
  266. ((reg > 0x405) && (reg < 0x420)) ||
  267. ((reg > 0x505) && (reg < 0x520)) ||
  268. ((reg > 0x605) && (reg < 0x620)) ||
  269. ((reg > 0x127) && (reg < 0x130)) ||
  270. ((reg > 0x227) && (reg < 0x230)) ||
  271. ((reg > 0x327) && (reg < 0x330)) ||
  272. ((reg > 0x427) && (reg < 0x430)) ||
  273. ((reg > 0x527) && (reg < 0x530)) ||
  274. ((reg > 0x627) && (reg < 0x630)) ||
  275. ((reg > 0x137) && (reg < 0x200)) ||
  276. ((reg > 0x237) && (reg < 0x300)) ||
  277. ((reg > 0x337) && (reg < 0x400)) ||
  278. ((reg > 0x437) && (reg < 0x500)) ||
  279. ((reg > 0x537) && (reg < 0x600)) ||
  280. ((reg > 0x637) && (reg < 0xF00)) ||
  281. ((reg > 0xF05) && (reg < 0xF20)) ||
  282. ((reg > 0xF25) && (reg < 0xF30)) ||
  283. ((reg > 0xF35) && (reg < 0x2000)))
  284. ret = false;
  285. return ret;
  286. }
  287. static ssize_t swr_slave_reg_show(struct swr_device *pdev, char __user *ubuf,
  288. size_t count, loff_t *ppos)
  289. {
  290. int i, reg_val, len;
  291. ssize_t total = 0;
  292. char tmp_buf[SWR_SLV_MAX_BUF_LEN];
  293. if (!ubuf || !ppos)
  294. return 0;
  295. for (i = (((int) *ppos/BYTES_PER_LINE) + SWR_SLV_START_REG_ADDR);
  296. i <= SWR_SLV_MAX_REG_ADDR; i++) {
  297. if (!is_swr_slave_reg_readable(i))
  298. continue;
  299. swr_read(pdev, pdev->dev_num, i, &reg_val, 1);
  300. len = snprintf(tmp_buf, sizeof(tmp_buf), "0x%.3x: 0x%.2x\n", i,
  301. (reg_val & 0xFF));
  302. if (len < 0) {
  303. pr_err_ratelimited("%s: fail to fill the buffer\n", __func__);
  304. total = -EFAULT;
  305. goto copy_err;
  306. }
  307. if ((total + len) >= count - 1)
  308. break;
  309. if (copy_to_user((ubuf + total), tmp_buf, len)) {
  310. pr_err_ratelimited("%s: fail to copy reg dump\n", __func__);
  311. total = -EFAULT;
  312. goto copy_err;
  313. }
  314. total += len;
  315. *ppos += len;
  316. }
  317. copy_err:
  318. *ppos = SWR_SLV_MAX_REG_ADDR * BYTES_PER_LINE;
  319. return total;
  320. }
  321. static ssize_t codec_debug_dump(struct file *file, char __user *ubuf,
  322. size_t count, loff_t *ppos)
  323. {
  324. struct swr_device *pdev;
  325. if (!count || !file || !ppos || !ubuf)
  326. return -EINVAL;
  327. pdev = file->private_data;
  328. if (!pdev)
  329. return -EINVAL;
  330. if (*ppos < 0)
  331. return -EINVAL;
  332. return swr_slave_reg_show(pdev, ubuf, count, ppos);
  333. }
  334. static ssize_t codec_debug_read(struct file *file, char __user *ubuf,
  335. size_t count, loff_t *ppos)
  336. {
  337. char lbuf[SWR_SLV_RD_BUF_LEN];
  338. struct swr_device *pdev = NULL;
  339. struct wsa884x_priv *wsa884x = NULL;
  340. if (!count || !file || !ppos || !ubuf)
  341. return -EINVAL;
  342. pdev = file->private_data;
  343. if (!pdev)
  344. return -EINVAL;
  345. wsa884x = swr_get_dev_data(pdev);
  346. if (!wsa884x)
  347. return -EINVAL;
  348. if (*ppos < 0)
  349. return -EINVAL;
  350. snprintf(lbuf, sizeof(lbuf), "0x%x\n",
  351. (wsa884x->read_data & 0xFF));
  352. return simple_read_from_buffer(ubuf, count, ppos, lbuf,
  353. strnlen(lbuf, 7));
  354. }
  355. static ssize_t codec_debug_peek_write(struct file *file,
  356. const char __user *ubuf, size_t cnt, loff_t *ppos)
  357. {
  358. char lbuf[SWR_SLV_WR_BUF_LEN];
  359. int rc = 0;
  360. u32 param[5];
  361. struct swr_device *pdev = NULL;
  362. struct wsa884x_priv *wsa884x = NULL;
  363. if (!cnt || !file || !ppos || !ubuf)
  364. return -EINVAL;
  365. pdev = file->private_data;
  366. if (!pdev)
  367. return -EINVAL;
  368. wsa884x = swr_get_dev_data(pdev);
  369. if (!wsa884x)
  370. return -EINVAL;
  371. if (*ppos < 0)
  372. return -EINVAL;
  373. if (cnt > sizeof(lbuf) - 1)
  374. return -EINVAL;
  375. rc = copy_from_user(lbuf, ubuf, cnt);
  376. if (rc)
  377. return -EFAULT;
  378. lbuf[cnt] = '\0';
  379. rc = get_parameters(lbuf, param, 1);
  380. if (!((param[0] <= SWR_SLV_MAX_REG_ADDR) && (rc == 0)))
  381. return -EINVAL;
  382. swr_read(pdev, pdev->dev_num, param[0], &wsa884x->read_data, 1);
  383. if (rc == 0)
  384. rc = cnt;
  385. else
  386. pr_err_ratelimited("%s: rc = %d\n", __func__, rc);
  387. return rc;
  388. }
  389. static ssize_t codec_debug_write(struct file *file,
  390. const char __user *ubuf, size_t cnt, loff_t *ppos)
  391. {
  392. char lbuf[SWR_SLV_WR_BUF_LEN];
  393. int rc = 0;
  394. u32 param[5];
  395. struct swr_device *pdev;
  396. if (!file || !ppos || !ubuf)
  397. return -EINVAL;
  398. pdev = file->private_data;
  399. if (!pdev)
  400. return -EINVAL;
  401. if (cnt > sizeof(lbuf) - 1)
  402. return -EINVAL;
  403. rc = copy_from_user(lbuf, ubuf, cnt);
  404. if (rc)
  405. return -EFAULT;
  406. lbuf[cnt] = '\0';
  407. rc = get_parameters(lbuf, param, 2);
  408. if (!((param[0] <= SWR_SLV_MAX_REG_ADDR) &&
  409. (param[1] <= 0xFF) && (rc == 0)))
  410. return -EINVAL;
  411. swr_write(pdev, pdev->dev_num, param[0], &param[1]);
  412. if (rc == 0)
  413. rc = cnt;
  414. else
  415. pr_err_ratelimited("%s: rc = %d\n", __func__, rc);
  416. return rc;
  417. }
  418. static const struct file_operations codec_debug_write_ops = {
  419. .open = codec_debug_open,
  420. .write = codec_debug_write,
  421. };
  422. static const struct file_operations codec_debug_read_ops = {
  423. .open = codec_debug_open,
  424. .read = codec_debug_read,
  425. .write = codec_debug_peek_write,
  426. };
  427. static const struct file_operations codec_debug_dump_ops = {
  428. .open = codec_debug_open,
  429. .read = codec_debug_dump,
  430. };
  431. #endif
  432. static void wsa884x_regcache_sync(struct wsa884x_priv *wsa884x)
  433. {
  434. mutex_lock(&wsa884x->res_lock);
  435. regcache_mark_dirty(wsa884x->regmap);
  436. regcache_sync(wsa884x->regmap);
  437. mutex_unlock(&wsa884x->res_lock);
  438. }
  439. static irqreturn_t wsa884x_saf2war_handle_irq(int irq, void *data)
  440. {
  441. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  442. __func__, irq);
  443. return IRQ_HANDLED;
  444. }
  445. static irqreturn_t wsa884x_war2saf_handle_irq(int irq, void *data)
  446. {
  447. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  448. __func__, irq);
  449. return IRQ_HANDLED;
  450. }
  451. static irqreturn_t wsa884x_otp_handle_irq(int irq, void *data)
  452. {
  453. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  454. __func__, irq);
  455. return IRQ_HANDLED;
  456. }
  457. static irqreturn_t wsa884x_ocp_handle_irq(int irq, void *data)
  458. {
  459. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  460. __func__, irq);
  461. return IRQ_HANDLED;
  462. }
  463. static irqreturn_t wsa884x_clip_handle_irq(int irq, void *data)
  464. {
  465. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  466. __func__, irq);
  467. return IRQ_HANDLED;
  468. }
  469. static irqreturn_t wsa884x_pdm_wd_handle_irq(int irq, void *data)
  470. {
  471. struct wsa884x_priv *wsa884x = data;
  472. struct snd_soc_component *component = NULL;
  473. if (!wsa884x)
  474. return IRQ_NONE;
  475. component = wsa884x->component;
  476. snd_soc_component_update_bits(component,
  477. REG_FIELD_VALUE(PDM_WD_CTL, PDM_WD_EN, 0x00));
  478. snd_soc_component_update_bits(component,
  479. REG_FIELD_VALUE(PDM_WD_CTL, PDM_WD_EN, 0x01));
  480. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  481. __func__, irq);
  482. return IRQ_HANDLED;
  483. }
  484. static irqreturn_t wsa884x_clk_wd_handle_irq(int irq, void *data)
  485. {
  486. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  487. __func__, irq);
  488. return IRQ_HANDLED;
  489. }
  490. static irqreturn_t wsa884x_ext_int_handle_irq(int irq, void *data)
  491. {
  492. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  493. __func__, irq);
  494. return IRQ_HANDLED;
  495. }
  496. static irqreturn_t wsa884x_uvlo_handle_irq(int irq, void *data)
  497. {
  498. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  499. __func__, irq);
  500. return IRQ_HANDLED;
  501. }
  502. static irqreturn_t wsa884x_pa_on_err_handle_irq(int irq, void *data)
  503. {
  504. u8 pa_fsm_sta = 0, pa_fsm_err = 0;
  505. struct wsa884x_priv *wsa884x = data;
  506. struct snd_soc_component *component = NULL;
  507. if (!wsa884x)
  508. return IRQ_NONE;
  509. component = wsa884x->component;
  510. if (!component)
  511. return IRQ_NONE;
  512. snd_soc_component_update_bits(component,
  513. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x00));
  514. pa_fsm_sta = (snd_soc_component_read(component, WSA884X_PA_FSM_STA1)
  515. & 0x1F);
  516. if (pa_fsm_sta)
  517. pa_fsm_err = snd_soc_component_read(component,
  518. WSA884X_PA_FSM_ERR_COND0);
  519. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  520. __func__, irq);
  521. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL0,
  522. 0x10, 0x00);
  523. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL0,
  524. 0x10, 0x10);
  525. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL0,
  526. 0x10, 0x00);
  527. return IRQ_HANDLED;
  528. }
  529. static int wsa884x_set_gain_parameters(struct snd_soc_component *component)
  530. {
  531. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  532. u8 igain;
  533. u8 vgain;
  534. switch (wsa884x->bat_cfg) {
  535. case CONFIG_1S:
  536. case EXT_1S:
  537. switch (wsa884x->system_gain) {
  538. case G_21_DB:
  539. wsa884x->comp_offset = COMP_OFFSET0;
  540. wsa884x->min_gain = G_0_DB;
  541. wsa884x->pa_aux_gain = PA_AUX_0_DB;
  542. break;
  543. case G_19P5_DB:
  544. wsa884x->comp_offset = COMP_OFFSET1;
  545. wsa884x->min_gain = G_M1P5_DB;
  546. wsa884x->pa_aux_gain = PA_AUX_M1P5_DB;
  547. break;
  548. case G_18_DB:
  549. wsa884x->comp_offset = COMP_OFFSET2;
  550. wsa884x->min_gain = G_M3_DB;
  551. wsa884x->pa_aux_gain = PA_AUX_M3_DB;
  552. break;
  553. case G_16P5_DB:
  554. wsa884x->comp_offset = COMP_OFFSET3;
  555. wsa884x->min_gain = G_M4P5_DB;
  556. wsa884x->pa_aux_gain = PA_AUX_M4P5_DB;
  557. break;
  558. default:
  559. wsa884x->comp_offset = COMP_OFFSET4;
  560. wsa884x->min_gain = G_M6_DB;
  561. wsa884x->pa_aux_gain = PA_AUX_M6_DB;
  562. break;
  563. }
  564. break;
  565. case CONFIG_3S:
  566. case EXT_3S:
  567. wsa884x->comp_offset = COMP_OFFSET0;
  568. wsa884x->min_gain = G_7P5_DB;
  569. wsa884x->pa_aux_gain = PA_AUX_7P5_DB;
  570. break;
  571. case EXT_ABOVE_3S:
  572. wsa884x->comp_offset = COMP_OFFSET0;
  573. wsa884x->min_gain = G_12_DB;
  574. wsa884x->pa_aux_gain = PA_AUX_12_DB;
  575. break;
  576. default:
  577. wsa884x->comp_offset = COMP_OFFSET0;
  578. wsa884x->min_gain = G_0_DB;
  579. wsa884x->pa_aux_gain = PA_AUX_0_DB;
  580. break;
  581. }
  582. igain = isense_gain_data[wsa884x->system_gain][wsa884x->rload];
  583. vgain = vsense_gain_data[wsa884x->system_gain];
  584. snd_soc_component_update_bits(component,
  585. REG_FIELD_VALUE(ISENSE2, ISENSE_GAIN_CTL, igain));
  586. snd_soc_component_update_bits(component,
  587. REG_FIELD_VALUE(VSENSE1, GAIN_VSENSE_FE, vgain));
  588. snd_soc_component_update_bits(component,
  589. REG_FIELD_VALUE(GAIN_RAMPING_MIN, MIN_GAIN, wsa884x->min_gain));
  590. if (wsa884x->comp_enable) {
  591. snd_soc_component_update_bits(component,
  592. REG_FIELD_VALUE(DRE_CTL_0, OFFSET,
  593. wsa884x->comp_offset));
  594. snd_soc_component_update_bits(component,
  595. REG_FIELD_VALUE(DRE_CTL_1, CSR_GAIN_EN, 0x00));
  596. } else {
  597. wsa884x->pa_aux_gain = pa_aux_no_comp[wsa884x->pa_gain];
  598. snd_soc_component_update_bits(component,
  599. REG_FIELD_VALUE(DRE_CTL_1, CSR_GAIN_EN, 0x01));
  600. snd_soc_component_update_bits(component,
  601. REG_FIELD_VALUE(DRE_CTL_1, CSR_GAIN, wsa884x->pa_gain));
  602. }
  603. return 0;
  604. }
  605. static int wsa884x_set_pbr_parameters(struct snd_soc_component *component)
  606. {
  607. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  608. int vth1_reg_val;
  609. int vth2_reg_val;
  610. int vth3_reg_val;
  611. int vth4_reg_val;
  612. int vth5_reg_val;
  613. int vth6_reg_val;
  614. int vth7_reg_val;
  615. int vth8_reg_val;
  616. int vth9_reg_val;
  617. int vth10_reg_val;
  618. int vth11_reg_val;
  619. int vth12_reg_val;
  620. int vth13_reg_val;
  621. int vth14_reg_val;
  622. int vth15_reg_val;
  623. int vth1_val = pbr_vth1_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  624. int vth2_val = pbr_vth2_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  625. int vth3_val = pbr_vth3_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  626. int vth4_val = pbr_vth4_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  627. int vth5_val = pbr_vth5_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  628. int vth6_val = pbr_vth6_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  629. int vth7_val = pbr_vth7_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  630. int vth8_val = pbr_vth8_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  631. int vth9_val = pbr_vth9_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  632. int vth10_val = pbr_vth10_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  633. int vth11_val = pbr_vth11_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  634. int vth12_val = pbr_vth12_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  635. int vth13_val = pbr_vth13_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  636. int vth14_val = pbr_vth14_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  637. int vth15_val = pbr_vth15_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  638. vth1_reg_val = WSA884X_VTH_TO_REG(vth1_val);
  639. vth2_reg_val = WSA884X_VTH_TO_REG(vth2_val);
  640. vth3_reg_val = WSA884X_VTH_TO_REG(vth3_val);
  641. vth4_reg_val = WSA884X_VTH_TO_REG(vth4_val);
  642. vth5_reg_val = WSA884X_VTH_TO_REG(vth5_val);
  643. vth6_reg_val = WSA884X_VTH_TO_REG(vth6_val);
  644. vth7_reg_val = WSA884X_VTH_TO_REG(vth7_val);
  645. vth8_reg_val = WSA884X_VTH_TO_REG(vth8_val);
  646. vth9_reg_val = WSA884X_VTH_TO_REG(vth9_val);
  647. vth10_reg_val = WSA884X_VTH_TO_REG(vth10_val);
  648. vth11_reg_val = WSA884X_VTH_TO_REG(vth11_val);
  649. vth12_reg_val = WSA884X_VTH_TO_REG(vth12_val);
  650. vth13_reg_val = WSA884X_VTH_TO_REG(vth13_val);
  651. vth14_reg_val = WSA884X_VTH_TO_REG(vth14_val);
  652. vth15_reg_val = WSA884X_VTH_TO_REG(vth15_val);
  653. snd_soc_component_write(component, WSA884X_CLSH_VTH1, vth1_reg_val);
  654. snd_soc_component_write(component, WSA884X_CLSH_VTH2, vth2_reg_val);
  655. snd_soc_component_write(component, WSA884X_CLSH_VTH3, vth3_reg_val);
  656. snd_soc_component_write(component, WSA884X_CLSH_VTH4, vth4_reg_val);
  657. snd_soc_component_write(component, WSA884X_CLSH_VTH5, vth5_reg_val);
  658. snd_soc_component_write(component, WSA884X_CLSH_VTH6, vth6_reg_val);
  659. snd_soc_component_write(component, WSA884X_CLSH_VTH7, vth7_reg_val);
  660. snd_soc_component_write(component, WSA884X_CLSH_VTH8, vth8_reg_val);
  661. snd_soc_component_write(component, WSA884X_CLSH_VTH9, vth9_reg_val);
  662. snd_soc_component_write(component, WSA884X_CLSH_VTH10, vth10_reg_val);
  663. snd_soc_component_write(component, WSA884X_CLSH_VTH11, vth11_reg_val);
  664. snd_soc_component_write(component, WSA884X_CLSH_VTH12, vth12_reg_val);
  665. snd_soc_component_write(component, WSA884X_CLSH_VTH13, vth13_reg_val);
  666. snd_soc_component_write(component, WSA884X_CLSH_VTH14, vth14_reg_val);
  667. snd_soc_component_write(component, WSA884X_CLSH_VTH15, vth15_reg_val);
  668. return 0;
  669. }
  670. static void wsa_noise_gate_write(struct snd_soc_component *component,
  671. int imode)
  672. {
  673. switch (imode) {
  674. case NG1:
  675. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL1,
  676. WSA884X_IDLE_DETECT_NG_BLOCK_MASK, 0x30);
  677. break;
  678. case NG2:
  679. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL1,
  680. WSA884X_IDLE_DETECT_NG_BLOCK_MASK, 0x20);
  681. break;
  682. case NG3:
  683. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL1,
  684. WSA884X_IDLE_DETECT_NG_BLOCK_MASK, 0x10);
  685. break;
  686. default:
  687. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL1,
  688. WSA884X_IDLE_DETECT_NG_BLOCK_MASK, 0x8);
  689. break;
  690. }
  691. }
  692. static int wsa_dev_mode_get(struct snd_kcontrol *kcontrol,
  693. struct snd_ctl_elem_value *ucontrol)
  694. {
  695. struct snd_soc_component *component =
  696. snd_soc_kcontrol_component(kcontrol);
  697. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  698. ucontrol->value.integer.value[0] = wsa884x->dev_mode;
  699. dev_dbg(component->dev, "%s: mode = 0x%x\n", __func__,
  700. wsa884x->dev_mode);
  701. return 0;
  702. }
  703. static int wsa_dev_mode_put(struct snd_kcontrol *kcontrol,
  704. struct snd_ctl_elem_value *ucontrol)
  705. {
  706. struct snd_soc_component *component =
  707. snd_soc_kcontrol_component(kcontrol);
  708. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  709. int dev_mode;
  710. int wsa_dev_index;
  711. if ((ucontrol->value.integer.value[0] >= SPEAKER) &&
  712. (ucontrol->value.integer.value[0] < MAX_DEV_MODE))
  713. dev_mode = ucontrol->value.integer.value[0];
  714. else
  715. return -EINVAL;
  716. dev_dbg(component->dev, "%s: Dev Mode current: %d, new: %d\n",
  717. __func__, wsa884x->dev_mode, dev_mode);
  718. /* Check if input parameter is in range */
  719. wsa_dev_index = (wsa884x->dev_index - 1) % 2;
  720. if ((dev_mode + wsa_dev_index * 2) < (MAX_DEV_MODE * 2)) {
  721. wsa884x->dev_mode = dev_mode;
  722. wsa884x->system_gain = wsa884x->sys_gains[dev_mode + wsa_dev_index * 2];
  723. } else {
  724. return -EINVAL;
  725. }
  726. return 0;
  727. }
  728. static const char * const wsa_pa_gain_text[] = {
  729. "G_21_DB", "G_19P5_DB" "G_18_DB", "G_16P5_DB", "G_15_DB", "G_13P5_DB",
  730. "G_12_DB", "G_10P5_DB", "G_9_DB", "G_7P5_DB", "G_6_DB", "G_4P5_DB",
  731. "G_3_DB", "G_1P5_DB", "G_0_DB", "G_M1P5_DB", "G_M3_DB", "G_M4P5_DB"
  732. "G_M6_DB", "G_M7P5_DB", "G_M9_DB"
  733. };
  734. static const struct soc_enum wsa_pa_gain_enum =
  735. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(wsa_pa_gain_text), wsa_pa_gain_text);
  736. static int wsa_pa_gain_get(struct snd_kcontrol *kcontrol,
  737. struct snd_ctl_elem_value *ucontrol)
  738. {
  739. struct snd_soc_component *component =
  740. snd_soc_kcontrol_component(kcontrol);
  741. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  742. ucontrol->value.integer.value[0] = wsa884x->pa_gain;
  743. dev_dbg(component->dev, "%s: PA gain = 0x%x\n", __func__,
  744. wsa884x->pa_gain);
  745. return 0;
  746. }
  747. static int wsa_pa_gain_put(struct snd_kcontrol *kcontrol,
  748. struct snd_ctl_elem_value *ucontrol)
  749. {
  750. struct snd_soc_component *component =
  751. snd_soc_kcontrol_component(kcontrol);
  752. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  753. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  754. __func__, ucontrol->value.integer.value[0]);
  755. wsa884x->pa_gain = ucontrol->value.integer.value[0];
  756. return 0;
  757. }
  758. static int wsa_get_temp(struct snd_kcontrol *kcontrol,
  759. struct snd_ctl_elem_value *ucontrol)
  760. {
  761. struct snd_soc_component *component =
  762. snd_soc_kcontrol_component(kcontrol);
  763. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  764. int temp = 0;
  765. if (test_bit(SPKR_STATUS, &wsa884x->status_mask))
  766. temp = wsa884x->curr_temp;
  767. else
  768. wsa884x_get_temperature(component, &temp);
  769. ucontrol->value.integer.value[0] = temp;
  770. return 0;
  771. }
  772. static ssize_t wsa884x_codec_version_read(struct snd_info_entry *entry,
  773. void *file_private_data, struct file *file,
  774. char __user *buf, size_t count, loff_t pos)
  775. {
  776. struct wsa884x_priv *wsa884x;
  777. char buffer[WSA884X_VERSION_ENTRY_SIZE];
  778. int len = 0;
  779. wsa884x = (struct wsa884x_priv *) entry->private_data;
  780. if (!wsa884x) {
  781. pr_err_ratelimited("%s: wsa884x priv is null\n", __func__);
  782. return -EINVAL;
  783. }
  784. switch (wsa884x->version) {
  785. case WSA884X_VERSION_1_0:
  786. len = snprintf(buffer, sizeof(buffer), "WSA884X_1_0\n");
  787. break;
  788. default:
  789. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  790. break;
  791. }
  792. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  793. }
  794. static struct snd_info_entry_ops wsa884x_codec_info_ops = {
  795. .read = wsa884x_codec_version_read,
  796. };
  797. static ssize_t wsa884x_variant_read(struct snd_info_entry *entry,
  798. void *file_private_data,
  799. struct file *file,
  800. char __user *buf, size_t count,
  801. loff_t pos)
  802. {
  803. struct wsa884x_priv *wsa884x;
  804. char buffer[WSA884X_VARIANT_ENTRY_SIZE];
  805. int len = 0;
  806. wsa884x = (struct wsa884x_priv *) entry->private_data;
  807. if (!wsa884x) {
  808. pr_err_ratelimited("%s: wsa884x priv is null\n", __func__);
  809. return -EINVAL;
  810. }
  811. switch (wsa884x->variant) {
  812. case WSA8840:
  813. len = snprintf(buffer, sizeof(buffer), "WSA8840\n");
  814. break;
  815. case WSA8845:
  816. len = snprintf(buffer, sizeof(buffer), "WSA8845\n");
  817. break;
  818. case WSA8845H:
  819. len = snprintf(buffer, sizeof(buffer), "WSA8845H\n");
  820. break;
  821. default:
  822. len = snprintf(buffer, sizeof(buffer), "UNDEFINED\n");
  823. break;
  824. }
  825. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  826. }
  827. static struct snd_info_entry_ops wsa884x_variant_ops = {
  828. .read = wsa884x_variant_read,
  829. };
  830. /*
  831. * wsa884x_codec_info_create_codec_entry - creates wsa884x module
  832. * @codec_root: The parent directory
  833. * @component: Codec instance
  834. *
  835. * Creates wsa884x module and version entry under the given
  836. * parent directory.
  837. *
  838. * Return: 0 on success or negative error code on failure.
  839. */
  840. int wsa884x_codec_info_create_codec_entry(struct snd_info_entry *codec_root,
  841. struct snd_soc_component *component)
  842. {
  843. struct snd_info_entry *version_entry;
  844. struct snd_info_entry *variant_entry;
  845. struct wsa884x_priv *wsa884x;
  846. struct snd_soc_card *card;
  847. char name[80];
  848. if (!codec_root || !component)
  849. return -EINVAL;
  850. wsa884x = snd_soc_component_get_drvdata(component);
  851. if (wsa884x->entry) {
  852. dev_dbg(wsa884x->dev,
  853. "%s:wsa884x module already created\n", __func__);
  854. return 0;
  855. }
  856. card = component->card;
  857. snprintf(name, sizeof(name), "%s.%llx", "wsa884x",
  858. wsa884x->swr_slave->addr);
  859. wsa884x->entry = snd_info_create_module_entry(codec_root->module,
  860. (const char *)name,
  861. codec_root);
  862. if (!wsa884x->entry) {
  863. dev_dbg(component->dev, "%s: failed to create wsa884x entry\n",
  864. __func__);
  865. return -ENOMEM;
  866. }
  867. wsa884x->entry->mode = S_IFDIR | 0555;
  868. if (snd_info_register(wsa884x->entry) < 0) {
  869. snd_info_free_entry(wsa884x->entry);
  870. return -ENOMEM;
  871. }
  872. version_entry = snd_info_create_card_entry(card->snd_card,
  873. "version",
  874. wsa884x->entry);
  875. if (!version_entry) {
  876. dev_dbg(component->dev, "%s: failed to create wsa884x version entry\n",
  877. __func__);
  878. snd_info_free_entry(wsa884x->entry);
  879. return -ENOMEM;
  880. }
  881. version_entry->private_data = wsa884x;
  882. version_entry->size = WSA884X_VERSION_ENTRY_SIZE;
  883. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  884. version_entry->c.ops = &wsa884x_codec_info_ops;
  885. if (snd_info_register(version_entry) < 0) {
  886. snd_info_free_entry(version_entry);
  887. snd_info_free_entry(wsa884x->entry);
  888. return -ENOMEM;
  889. }
  890. wsa884x->version_entry = version_entry;
  891. variant_entry = snd_info_create_card_entry(card->snd_card,
  892. "variant",
  893. wsa884x->entry);
  894. if (!variant_entry) {
  895. dev_dbg(component->dev,
  896. "%s: failed to create wsa884x variant entry\n",
  897. __func__);
  898. snd_info_free_entry(version_entry);
  899. snd_info_free_entry(wsa884x->entry);
  900. return -ENOMEM;
  901. }
  902. variant_entry->private_data = wsa884x;
  903. variant_entry->size = WSA884X_VARIANT_ENTRY_SIZE;
  904. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  905. variant_entry->c.ops = &wsa884x_variant_ops;
  906. if (snd_info_register(variant_entry) < 0) {
  907. snd_info_free_entry(variant_entry);
  908. snd_info_free_entry(version_entry);
  909. snd_info_free_entry(wsa884x->entry);
  910. return -ENOMEM;
  911. }
  912. wsa884x->variant_entry = variant_entry;
  913. return 0;
  914. }
  915. EXPORT_SYMBOL(wsa884x_codec_info_create_codec_entry);
  916. /*
  917. * wsa884x_codec_get_dev_num - returns swr device number
  918. * @component: Codec instance
  919. *
  920. * Return: swr device number on success or negative error
  921. * code on failure.
  922. */
  923. int wsa884x_codec_get_dev_num(struct snd_soc_component *component)
  924. {
  925. struct wsa884x_priv *wsa884x;
  926. if (!component)
  927. return -EINVAL;
  928. wsa884x = snd_soc_component_get_drvdata(component);
  929. if (!wsa884x) {
  930. pr_err_ratelimited("%s: wsa884x component is NULL\n", __func__);
  931. return -EINVAL;
  932. }
  933. return wsa884x->swr_slave->dev_num;
  934. }
  935. EXPORT_SYMBOL(wsa884x_codec_get_dev_num);
  936. static int wsa884x_get_dev_num(struct snd_kcontrol *kcontrol,
  937. struct snd_ctl_elem_value *ucontrol)
  938. {
  939. struct snd_soc_component *component =
  940. snd_soc_kcontrol_component(kcontrol);
  941. struct wsa884x_priv *wsa884x;
  942. if (!component)
  943. return -EINVAL;
  944. wsa884x = snd_soc_component_get_drvdata(component);
  945. if (!wsa884x) {
  946. pr_err_ratelimited("%s: wsa884x component is NULL\n", __func__);
  947. return -EINVAL;
  948. }
  949. ucontrol->value.integer.value[0] = wsa884x->swr_slave->dev_num;
  950. return 0;
  951. }
  952. static int wsa884x_get_compander(struct snd_kcontrol *kcontrol,
  953. struct snd_ctl_elem_value *ucontrol)
  954. {
  955. struct snd_soc_component *component =
  956. snd_soc_kcontrol_component(kcontrol);
  957. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  958. ucontrol->value.integer.value[0] = wsa884x->comp_enable;
  959. return 0;
  960. }
  961. /*
  962. * wsa884x_validate_dt_configuration_params - returns 1 or 0
  963. * Return: 0 Valid configuration, 1 Invalid configuration
  964. */
  965. static bool wsa884x_validate_dt_configuration_params(struct snd_soc_component *component,
  966. u8 irload, u8 ibat_cfg_dts, u8 isystem_gain)
  967. {
  968. u8 bat_cfg_reg;
  969. bool is_invalid_flag = true;
  970. bat_cfg_reg = snd_soc_component_read(component, WSA884X_VPHX_SYS_EN_STATUS);
  971. if ((ibat_cfg_dts == EXT_1S) || (ibat_cfg_dts == EXT_2S) || (ibat_cfg_dts == EXT_3S))
  972. ibat_cfg_dts = EXT_ABOVE_3S;
  973. if ((WSA_4_OHMS <= irload && irload < WSA_MAX_OHMS) &&
  974. (G_21_DB <= isystem_gain && isystem_gain < G_MAX_DB) &&
  975. (EXT_ABOVE_3S <= ibat_cfg_dts && ibat_cfg_dts < CONFIG_MAX) &&
  976. (ibat_cfg_dts == bat_cfg_reg))
  977. is_invalid_flag = false;
  978. return is_invalid_flag;
  979. }
  980. static int wsa884x_set_compander(struct snd_kcontrol *kcontrol,
  981. struct snd_ctl_elem_value *ucontrol)
  982. {
  983. struct snd_soc_component *component =
  984. snd_soc_kcontrol_component(kcontrol);
  985. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  986. int value = ucontrol->value.integer.value[0];
  987. dev_dbg(component->dev, "%s: Compander enable current %d, new %d\n",
  988. __func__, wsa884x->comp_enable, value);
  989. wsa884x->comp_enable = value;
  990. return 0;
  991. }
  992. static int wsa884x_get_visense(struct snd_kcontrol *kcontrol,
  993. struct snd_ctl_elem_value *ucontrol)
  994. {
  995. struct snd_soc_component *component =
  996. snd_soc_kcontrol_component(kcontrol);
  997. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  998. ucontrol->value.integer.value[0] = wsa884x->visense_enable;
  999. return 0;
  1000. }
  1001. static int wsa884x_set_visense(struct snd_kcontrol *kcontrol,
  1002. struct snd_ctl_elem_value *ucontrol)
  1003. {
  1004. struct snd_soc_component *component =
  1005. snd_soc_kcontrol_component(kcontrol);
  1006. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1007. int value = ucontrol->value.integer.value[0];
  1008. dev_dbg(component->dev, "%s: VIsense enable current %d, new %d\n",
  1009. __func__, wsa884x->visense_enable, value);
  1010. wsa884x->visense_enable = value;
  1011. return 0;
  1012. }
  1013. static int wsa884x_get_pbr(struct snd_kcontrol *kcontrol,
  1014. struct snd_ctl_elem_value *ucontrol)
  1015. {
  1016. struct snd_soc_component *component =
  1017. snd_soc_kcontrol_component(kcontrol);
  1018. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1019. ucontrol->value.integer.value[0] = wsa884x->pbr_enable;
  1020. return 0;
  1021. }
  1022. static int wsa884x_set_pbr(struct snd_kcontrol *kcontrol,
  1023. struct snd_ctl_elem_value *ucontrol)
  1024. {
  1025. struct snd_soc_component *component =
  1026. snd_soc_kcontrol_component(kcontrol);
  1027. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1028. int value = ucontrol->value.integer.value[0];
  1029. dev_dbg(component->dev, "%s: PBR enable current %d, new %d\n",
  1030. __func__, wsa884x->pbr_enable, value);
  1031. wsa884x->pbr_enable = value;
  1032. return 0;
  1033. }
  1034. static int wsa884x_get_cps(struct snd_kcontrol *kcontrol,
  1035. struct snd_ctl_elem_value *ucontrol)
  1036. {
  1037. struct snd_soc_component *component =
  1038. snd_soc_kcontrol_component(kcontrol);
  1039. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1040. ucontrol->value.integer.value[0] = wsa884x->cps_enable;
  1041. return 0;
  1042. }
  1043. static int wsa884x_set_cps(struct snd_kcontrol *kcontrol,
  1044. struct snd_ctl_elem_value *ucontrol)
  1045. {
  1046. struct snd_soc_component *component =
  1047. snd_soc_kcontrol_component(kcontrol);
  1048. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1049. int value = ucontrol->value.integer.value[0];
  1050. dev_dbg(component->dev, "%s: CPS enable current %d, new %d\n",
  1051. __func__, wsa884x->cps_enable, value);
  1052. wsa884x->cps_enable = value;
  1053. return 0;
  1054. }
  1055. static const struct snd_kcontrol_new wsa884x_snd_controls[] = {
  1056. SOC_ENUM_EXT("WSA PA Gain", wsa_pa_gain_enum,
  1057. wsa_pa_gain_get, wsa_pa_gain_put),
  1058. SOC_SINGLE_EXT("WSA Temp", SND_SOC_NOPM, 0, UINT_MAX, 0,
  1059. wsa_get_temp, NULL),
  1060. SOC_SINGLE_EXT("WSA Get DevNum", SND_SOC_NOPM, 0, UINT_MAX, 0,
  1061. wsa884x_get_dev_num, NULL),
  1062. SOC_SINGLE_EXT("WSA MODE", SND_SOC_NOPM, 0, 1, 0,
  1063. wsa_dev_mode_get, wsa_dev_mode_put),
  1064. SOC_SINGLE_EXT("COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  1065. wsa884x_get_compander, wsa884x_set_compander),
  1066. SOC_SINGLE_EXT("VISENSE Switch", SND_SOC_NOPM, 0, 1, 0,
  1067. wsa884x_get_visense, wsa884x_set_visense),
  1068. SOC_SINGLE_EXT("PBR Switch", SND_SOC_NOPM, 0, 1, 0,
  1069. wsa884x_get_pbr, wsa884x_set_pbr),
  1070. SOC_SINGLE_EXT("CPS Switch", SND_SOC_NOPM, 0, 1, 0,
  1071. wsa884x_get_cps, wsa884x_set_cps),
  1072. };
  1073. static const struct snd_kcontrol_new swr_dac_port[] = {
  1074. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1075. };
  1076. static int wsa884x_set_port(struct snd_soc_component *component, int port_idx,
  1077. u8 *port_id, u8 *num_ch, u8 *ch_mask, u32 *ch_rate,
  1078. u8 *port_type)
  1079. {
  1080. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1081. *port_id = wsa884x->port[port_idx].port_id;
  1082. *num_ch = wsa884x->port[port_idx].num_ch;
  1083. *ch_mask = wsa884x->port[port_idx].ch_mask;
  1084. *ch_rate = wsa884x->port[port_idx].ch_rate;
  1085. *port_type = wsa884x->port[port_idx].port_type;
  1086. return 0;
  1087. }
  1088. static int wsa884x_enable_swr_dac_port(struct snd_soc_dapm_widget *w,
  1089. struct snd_kcontrol *kcontrol, int event)
  1090. {
  1091. struct snd_soc_component *component =
  1092. snd_soc_dapm_to_component(w->dapm);
  1093. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1094. u8 port_id[WSA884X_MAX_SWR_PORTS];
  1095. u8 num_ch[WSA884X_MAX_SWR_PORTS];
  1096. u8 ch_mask[WSA884X_MAX_SWR_PORTS];
  1097. u32 ch_rate[WSA884X_MAX_SWR_PORTS];
  1098. u8 port_type[WSA884X_MAX_SWR_PORTS];
  1099. u8 num_port = 0;
  1100. dev_dbg(component->dev, "%s: event %d name %s\n", __func__,
  1101. event, w->name);
  1102. if (wsa884x == NULL)
  1103. return -EINVAL;
  1104. switch (event) {
  1105. case SND_SOC_DAPM_PRE_PMU:
  1106. wsa884x_set_port(component, SWR_DAC_PORT,
  1107. &port_id[num_port], &num_ch[num_port],
  1108. &ch_mask[num_port], &ch_rate[num_port],
  1109. &port_type[num_port]);
  1110. if (wsa884x->dev_mode == RECEIVER)
  1111. ch_rate[num_port] = SWR_CLK_RATE_4P8MHZ;
  1112. ++num_port;
  1113. if (wsa884x->comp_enable) {
  1114. wsa884x_set_port(component, SWR_COMP_PORT,
  1115. &port_id[num_port], &num_ch[num_port],
  1116. &ch_mask[num_port], &ch_rate[num_port],
  1117. &port_type[num_port]);
  1118. ++num_port;
  1119. }
  1120. if (wsa884x->pbr_enable) {
  1121. wsa884x_set_port(component, SWR_PBR_PORT,
  1122. &port_id[num_port], &num_ch[num_port],
  1123. &ch_mask[num_port], &ch_rate[num_port],
  1124. &port_type[num_port]);
  1125. ++num_port;
  1126. }
  1127. if (wsa884x->visense_enable) {
  1128. wsa884x_set_port(component, SWR_VISENSE_PORT,
  1129. &port_id[num_port], &num_ch[num_port],
  1130. &ch_mask[num_port], &ch_rate[num_port],
  1131. &port_type[num_port]);
  1132. ++num_port;
  1133. }
  1134. if (wsa884x->cps_enable) {
  1135. wsa884x_set_port(component, SWR_CPS_PORT,
  1136. &port_id[num_port], &num_ch[num_port],
  1137. &ch_mask[num_port], &ch_rate[num_port],
  1138. &port_type[num_port]);
  1139. ++num_port;
  1140. }
  1141. swr_connect_port(wsa884x->swr_slave, &port_id[0], num_port,
  1142. &ch_mask[0], &ch_rate[0], &num_ch[0],
  1143. &port_type[0]);
  1144. break;
  1145. case SND_SOC_DAPM_POST_PMU:
  1146. set_bit(SPKR_STATUS, &wsa884x->status_mask);
  1147. break;
  1148. case SND_SOC_DAPM_PRE_PMD:
  1149. wsa884x_set_port(component, SWR_DAC_PORT,
  1150. &port_id[num_port], &num_ch[num_port],
  1151. &ch_mask[num_port], &ch_rate[num_port],
  1152. &port_type[num_port]);
  1153. ++num_port;
  1154. if (wsa884x->comp_enable) {
  1155. wsa884x_set_port(component, SWR_COMP_PORT,
  1156. &port_id[num_port], &num_ch[num_port],
  1157. &ch_mask[num_port], &ch_rate[num_port],
  1158. &port_type[num_port]);
  1159. ++num_port;
  1160. }
  1161. if (wsa884x->pbr_enable) {
  1162. wsa884x_set_port(component, SWR_PBR_PORT,
  1163. &port_id[num_port], &num_ch[num_port],
  1164. &ch_mask[num_port], &ch_rate[num_port],
  1165. &port_type[num_port]);
  1166. ++num_port;
  1167. }
  1168. if (wsa884x->visense_enable) {
  1169. wsa884x_set_port(component, SWR_VISENSE_PORT,
  1170. &port_id[num_port], &num_ch[num_port],
  1171. &ch_mask[num_port], &ch_rate[num_port],
  1172. &port_type[num_port]);
  1173. ++num_port;
  1174. }
  1175. if (wsa884x->cps_enable) {
  1176. wsa884x_set_port(component, SWR_CPS_PORT,
  1177. &port_id[num_port], &num_ch[num_port],
  1178. &ch_mask[num_port], &ch_rate[num_port],
  1179. &port_type[num_port]);
  1180. ++num_port;
  1181. }
  1182. swr_disconnect_port(wsa884x->swr_slave, &port_id[0], num_port,
  1183. &ch_mask[0], &port_type[0]);
  1184. break;
  1185. case SND_SOC_DAPM_POST_PMD:
  1186. if (swr_set_device_group(wsa884x->swr_slave, SWR_GROUP_NONE))
  1187. dev_err_ratelimited(component->dev,
  1188. "%s: set num ch failed\n", __func__);
  1189. swr_slvdev_datapath_control(wsa884x->swr_slave,
  1190. wsa884x->swr_slave->dev_num,
  1191. false);
  1192. break;
  1193. default:
  1194. break;
  1195. }
  1196. return 0;
  1197. }
  1198. static int wsa884x_spkr_event(struct snd_soc_dapm_widget *w,
  1199. struct snd_kcontrol *kcontrol, int event)
  1200. {
  1201. struct snd_soc_component *component =
  1202. snd_soc_dapm_to_component(w->dapm);
  1203. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1204. dev_dbg(component->dev, "%s: %s %d\n", __func__, w->name, event);
  1205. switch (event) {
  1206. case SND_SOC_DAPM_POST_PMU:
  1207. swr_slvdev_datapath_control(wsa884x->swr_slave,
  1208. wsa884x->swr_slave->dev_num,
  1209. true);
  1210. wsa884x_set_gain_parameters(component);
  1211. if (wsa884x->dev_mode == SPEAKER) {
  1212. snd_soc_component_update_bits(component,
  1213. REG_FIELD_VALUE(DRE_CTL_0, PROG_DELAY, 0x0F));
  1214. } else {
  1215. snd_soc_component_update_bits(component,
  1216. REG_FIELD_VALUE(DRE_CTL_0, PROG_DELAY, 0x03));
  1217. snd_soc_component_update_bits(component,
  1218. REG_FIELD_VALUE(CDC_PATH_MODE, RXD_MODE, 0x01));
  1219. snd_soc_component_update_bits(component,
  1220. REG_FIELD_VALUE(PWM_CLK_CTL,
  1221. PWM_CLK_FREQ_SEL, 0x01));
  1222. }
  1223. if (wsa884x->pbr_enable) {
  1224. snd_soc_component_update_bits(component,
  1225. REG_FIELD_VALUE(CURRENT_LIMIT,
  1226. CURRENT_LIMIT_OVRD_EN, 0x00));
  1227. switch (wsa884x->bat_cfg) {
  1228. case CONFIG_1S:
  1229. snd_soc_component_update_bits(component,
  1230. REG_FIELD_VALUE(CURRENT_LIMIT,
  1231. CURRENT_LIMIT, 0x15));
  1232. break;
  1233. case CONFIG_2S:
  1234. snd_soc_component_update_bits(component,
  1235. REG_FIELD_VALUE(CURRENT_LIMIT,
  1236. CURRENT_LIMIT, 0x11));
  1237. break;
  1238. case CONFIG_3S:
  1239. snd_soc_component_update_bits(component,
  1240. REG_FIELD_VALUE(CURRENT_LIMIT,
  1241. CURRENT_LIMIT, 0x0D));
  1242. break;
  1243. }
  1244. } else {
  1245. snd_soc_component_update_bits(component,
  1246. REG_FIELD_VALUE(CURRENT_LIMIT,
  1247. CURRENT_LIMIT_OVRD_EN, 0x01));
  1248. if (wsa884x->system_gain >= G_12_DB)
  1249. snd_soc_component_update_bits(component,
  1250. REG_FIELD_VALUE(CURRENT_LIMIT,
  1251. CURRENT_LIMIT, 0x15));
  1252. else
  1253. snd_soc_component_update_bits(component,
  1254. REG_FIELD_VALUE(CURRENT_LIMIT,
  1255. CURRENT_LIMIT, 0x09));
  1256. }
  1257. /* Force remove group */
  1258. swr_remove_from_group(wsa884x->swr_slave,
  1259. wsa884x->swr_slave->dev_num);
  1260. if (test_bit(SPKR_ADIE_LB, &wsa884x->status_mask) &&
  1261. !wsa884x->pa_mute)
  1262. snd_soc_component_update_bits(component,
  1263. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x01));
  1264. break;
  1265. case SND_SOC_DAPM_PRE_PMD:
  1266. snd_soc_component_update_bits(component,
  1267. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x00));
  1268. snd_soc_component_update_bits(component,
  1269. REG_FIELD_VALUE(PDM_WD_CTL, PDM_WD_EN, 0x00));
  1270. clear_bit(SPKR_STATUS, &wsa884x->status_mask);
  1271. clear_bit(SPKR_ADIE_LB, &wsa884x->status_mask);
  1272. wsa884x->pa_mute = 0;
  1273. break;
  1274. }
  1275. return 0;
  1276. }
  1277. static const struct snd_soc_dapm_widget wsa884x_dapm_widgets[] = {
  1278. SND_SOC_DAPM_INPUT("IN"),
  1279. SND_SOC_DAPM_MIXER_E("SWR DAC_Port", SND_SOC_NOPM, 0, 0, swr_dac_port,
  1280. ARRAY_SIZE(swr_dac_port), wsa884x_enable_swr_dac_port,
  1281. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1282. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1283. SND_SOC_DAPM_SPK("SPKR", wsa884x_spkr_event),
  1284. };
  1285. static const struct snd_soc_dapm_route wsa884x_audio_map[] = {
  1286. {"SWR DAC_Port", "Switch", "IN"},
  1287. {"SPKR", NULL, "SWR DAC_Port"},
  1288. };
  1289. int wsa884x_set_channel_map(struct snd_soc_component *component, u8 *port,
  1290. u8 num_port, unsigned int *ch_mask,
  1291. unsigned int *ch_rate, u8 *port_type)
  1292. {
  1293. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1294. int i;
  1295. if (!port || !ch_mask || !ch_rate ||
  1296. (num_port > WSA884X_MAX_SWR_PORTS)) {
  1297. dev_err_ratelimited(component->dev,
  1298. "%s: Invalid port=%pK, ch_mask=%pK, ch_rate=%pK\n",
  1299. __func__, port, ch_mask, ch_rate);
  1300. return -EINVAL;
  1301. }
  1302. for (i = 0; i < num_port; i++) {
  1303. wsa884x->port[i].port_id = port[i];
  1304. wsa884x->port[i].ch_mask = ch_mask[i];
  1305. wsa884x->port[i].ch_rate = ch_rate[i];
  1306. wsa884x->port[i].num_ch = __sw_hweight8(ch_mask[i]);
  1307. if (port_type)
  1308. wsa884x->port[i].port_type = port_type[i];
  1309. }
  1310. return 0;
  1311. }
  1312. EXPORT_SYMBOL(wsa884x_set_channel_map);
  1313. static void wsa884x_codec_init(struct snd_soc_component *component)
  1314. {
  1315. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1316. int i;
  1317. if (!wsa884x)
  1318. return;
  1319. for (i = 0; i < ARRAY_SIZE(reg_init); i++)
  1320. snd_soc_component_update_bits(component, reg_init[i].reg,
  1321. reg_init[i].mask, reg_init[i].val);
  1322. /* Register updates for 2S battery configuration */
  1323. if (wsa884x->bat_cfg == CONFIG_2S) {
  1324. for (i = 0; i < ARRAY_SIZE(reg_init_2S); i++)
  1325. snd_soc_component_update_bits(component, reg_init_2S[i].reg,
  1326. reg_init_2S[i].mask, reg_init_2S[i].val);
  1327. }
  1328. wsa_noise_gate_write(component, wsa884x->noise_gate_mode);
  1329. }
  1330. static int32_t wsa884x_temp_reg_read(struct snd_soc_component *component,
  1331. struct wsa_temp_register *wsa_temp_reg)
  1332. {
  1333. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1334. if (!wsa884x) {
  1335. dev_err_ratelimited(component->dev, "%s: wsa884x is NULL\n", __func__);
  1336. return -EINVAL;
  1337. }
  1338. mutex_lock(&wsa884x->res_lock);
  1339. snd_soc_component_update_bits(component,
  1340. REG_FIELD_VALUE(PA_FSM_BYP0, DC_CAL_EN, 0x01));
  1341. snd_soc_component_update_bits(component,
  1342. REG_FIELD_VALUE(PA_FSM_BYP0, BG_EN, 0x01));
  1343. snd_soc_component_update_bits(component,
  1344. REG_FIELD_VALUE(PA_FSM_BYP0, CLK_WD_EN, 0x01));
  1345. snd_soc_component_update_bits(component,
  1346. REG_FIELD_VALUE(PA_FSM_BYP0, TSADC_EN, 0x01));
  1347. snd_soc_component_update_bits(component,
  1348. REG_FIELD_VALUE(PA_FSM_BYP0, D_UNMUTE, 0x01));
  1349. snd_soc_component_update_bits(component,
  1350. REG_FIELD_VALUE(PA_FSM_BYP0, SPKR_PROT_EN, 0x01));
  1351. snd_soc_component_update_bits(component,
  1352. REG_FIELD_VALUE(TADC_VALUE_CTL, TEMP_VALUE_RD_EN, 0x00));
  1353. wsa_temp_reg->dmeas_msb = snd_soc_component_read(component,
  1354. WSA884X_TEMP_DIN_MSB);
  1355. wsa_temp_reg->dmeas_lsb = snd_soc_component_read(component,
  1356. WSA884X_TEMP_DIN_LSB);
  1357. snd_soc_component_update_bits(component,
  1358. REG_FIELD_VALUE(TADC_VALUE_CTL, TEMP_VALUE_RD_EN, 0x01));
  1359. wsa_temp_reg->d1_msb = snd_soc_component_read(component,
  1360. WSA884X_OTP_REG_1);
  1361. wsa_temp_reg->d1_lsb = snd_soc_component_read(component,
  1362. WSA884X_OTP_REG_2);
  1363. wsa_temp_reg->d2_msb = snd_soc_component_read(component,
  1364. WSA884X_OTP_REG_3);
  1365. wsa_temp_reg->d2_lsb = snd_soc_component_read(component,
  1366. WSA884X_OTP_REG_4);
  1367. snd_soc_component_update_bits(component,
  1368. WSA884X_PA_FSM_BYP0, 0xE7, 0x00);
  1369. mutex_unlock(&wsa884x->res_lock);
  1370. return 0;
  1371. }
  1372. static int wsa884x_get_temperature(struct snd_soc_component *component,
  1373. int *temp)
  1374. {
  1375. struct wsa_temp_register reg;
  1376. int dmeas, d1, d2;
  1377. int ret = 0;
  1378. int temp_val = 0;
  1379. int t1 = T1_TEMP;
  1380. int t2 = T2_TEMP;
  1381. u8 retry = WSA884X_TEMP_RETRY;
  1382. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1383. if (!wsa884x)
  1384. return -EINVAL;
  1385. do {
  1386. ret = wsa884x_temp_reg_read(component, &reg);
  1387. if (ret) {
  1388. pr_err_ratelimited("%s: temp read failed: %d, current temp: %d\n",
  1389. __func__, ret, wsa884x->curr_temp);
  1390. if (temp)
  1391. *temp = wsa884x->curr_temp;
  1392. return 0;
  1393. }
  1394. /*
  1395. * Temperature register values are expected to be in the
  1396. * following range.
  1397. * d1_msb = 68 - 92 and d1_lsb = 0, 64, 128, 192
  1398. * d2_msb = 185 -218 and d2_lsb = 0, 64, 128, 192
  1399. */
  1400. if ((reg.d1_msb < 68 || reg.d1_msb > 92) ||
  1401. (!(reg.d1_lsb == 0 || reg.d1_lsb == 64 || reg.d1_lsb == 128 ||
  1402. reg.d1_lsb == 192)) ||
  1403. (reg.d2_msb < 185 || reg.d2_msb > 218) ||
  1404. (!(reg.d2_lsb == 0 || reg.d2_lsb == 64 || reg.d2_lsb == 128 ||
  1405. reg.d2_lsb == 192))) {
  1406. printk_ratelimited("%s: Temperature registers[%d %d %d %d] are out of range\n",
  1407. __func__, reg.d1_msb, reg.d1_lsb, reg.d2_msb,
  1408. reg.d2_lsb);
  1409. }
  1410. dmeas = ((reg.dmeas_msb << 0x8) | reg.dmeas_lsb) >> 0x6;
  1411. d1 = ((reg.d1_msb << 0x8) | reg.d1_lsb) >> 0x6;
  1412. d2 = ((reg.d2_msb << 0x8) | reg.d2_lsb) >> 0x6;
  1413. if (d1 == d2)
  1414. temp_val = TEMP_INVALID;
  1415. else
  1416. temp_val = t1 + (((dmeas - d1) * (t2 - t1))/(d2 - d1));
  1417. if (temp_val <= LOW_TEMP_THRESHOLD ||
  1418. temp_val >= HIGH_TEMP_THRESHOLD) {
  1419. pr_debug("%s: T0: %d is out of range[%d, %d]\n", __func__,
  1420. temp_val, LOW_TEMP_THRESHOLD, HIGH_TEMP_THRESHOLD);
  1421. if (retry--)
  1422. msleep(10);
  1423. } else {
  1424. break;
  1425. }
  1426. } while (retry);
  1427. wsa884x->curr_temp = temp_val;
  1428. if (temp)
  1429. *temp = temp_val;
  1430. pr_debug("%s: t0 measured: %d dmeas = %d, d1 = %d, d2 = %d\n",
  1431. __func__, temp_val, dmeas, d1, d2);
  1432. return ret;
  1433. }
  1434. static int wsa884x_codec_probe(struct snd_soc_component *component)
  1435. {
  1436. char w_name[MAX_NAME_LEN];
  1437. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1438. struct swr_device *dev;
  1439. int variant = 0, version = 0;
  1440. struct snd_soc_dapm_context *dapm =
  1441. snd_soc_component_get_dapm(component);
  1442. if (!wsa884x)
  1443. return -EINVAL;
  1444. if (!component->name_prefix)
  1445. return -EINVAL;
  1446. snd_soc_component_init_regmap(component, wsa884x->regmap);
  1447. dev = wsa884x->swr_slave;
  1448. wsa884x->component = component;
  1449. variant = (snd_soc_component_read(component, WSA884X_OTP_REG_0)
  1450. & FIELD_MASK(OTP_REG_0, WSA884X_ID));
  1451. wsa884x->variant = variant;
  1452. version = (snd_soc_component_read(component, WSA884X_CHIP_ID0)
  1453. & FIELD_MASK(CHIP_ID0, BYTE_0));
  1454. wsa884x->version = version;
  1455. wsa884x->comp_offset = COMP_OFFSET2;
  1456. wsa884x_codec_init(component);
  1457. wsa884x->global_pa_cnt = 0;
  1458. memset(w_name, 0, sizeof(w_name));
  1459. strlcpy(w_name, wsa884x->dai_driver->playback.stream_name,
  1460. sizeof(w_name));
  1461. snd_soc_dapm_ignore_suspend(dapm, w_name);
  1462. memset(w_name, 0, sizeof(w_name));
  1463. strlcpy(w_name, "IN", sizeof(w_name));
  1464. snd_soc_dapm_ignore_suspend(dapm, w_name);
  1465. memset(w_name, 0, sizeof(w_name));
  1466. strlcpy(w_name, "SWR DAC_Port", sizeof(w_name));
  1467. snd_soc_dapm_ignore_suspend(dapm, w_name);
  1468. memset(w_name, 0, sizeof(w_name));
  1469. strlcpy(w_name, "SPKR", sizeof(w_name));
  1470. snd_soc_dapm_ignore_suspend(dapm, w_name);
  1471. snd_soc_dapm_sync(dapm);
  1472. return 0;
  1473. }
  1474. static void wsa884x_codec_remove(struct snd_soc_component *component)
  1475. {
  1476. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1477. if (!wsa884x)
  1478. return;
  1479. snd_soc_component_exit_regmap(component);
  1480. return;
  1481. }
  1482. static int wsa884x_soc_codec_suspend(struct snd_soc_component *component)
  1483. {
  1484. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1485. if (!wsa884x)
  1486. return 0;
  1487. wsa884x->dapm_bias_off = true;
  1488. return 0;
  1489. }
  1490. static int wsa884x_soc_codec_resume(struct snd_soc_component *component)
  1491. {
  1492. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1493. if (!wsa884x)
  1494. return 0;
  1495. wsa884x->dapm_bias_off = false;
  1496. return 0;
  1497. }
  1498. static const struct snd_soc_component_driver soc_codec_dev_wsa884x_wsa = {
  1499. .name = "",
  1500. .probe = wsa884x_codec_probe,
  1501. .remove = wsa884x_codec_remove,
  1502. .controls = wsa884x_snd_controls,
  1503. .num_controls = ARRAY_SIZE(wsa884x_snd_controls),
  1504. .dapm_widgets = wsa884x_dapm_widgets,
  1505. .num_dapm_widgets = ARRAY_SIZE(wsa884x_dapm_widgets),
  1506. .dapm_routes = wsa884x_audio_map,
  1507. .num_dapm_routes = ARRAY_SIZE(wsa884x_audio_map),
  1508. .suspend = wsa884x_soc_codec_suspend,
  1509. .resume = wsa884x_soc_codec_resume,
  1510. };
  1511. static int wsa884x_gpio_ctrl(struct wsa884x_priv *wsa884x, bool enable)
  1512. {
  1513. int ret = 0;
  1514. if (enable)
  1515. ret = msm_cdc_pinctrl_select_active_state(
  1516. wsa884x->wsa_rst_np);
  1517. else
  1518. ret = msm_cdc_pinctrl_select_sleep_state(
  1519. wsa884x->wsa_rst_np);
  1520. if (ret != 0)
  1521. dev_err_ratelimited(wsa884x->dev,
  1522. "%s: Failed to turn state %d; ret=%d\n",
  1523. __func__, enable, ret);
  1524. return ret;
  1525. }
  1526. static int wsa884x_swr_up(struct wsa884x_priv *wsa884x)
  1527. {
  1528. int ret;
  1529. ret = wsa884x_gpio_ctrl(wsa884x, true);
  1530. if (ret)
  1531. dev_err_ratelimited(wsa884x->dev, "%s: Failed to enable gpio\n", __func__);
  1532. return ret;
  1533. }
  1534. static int wsa884x_swr_down(struct wsa884x_priv *wsa884x)
  1535. {
  1536. int ret;
  1537. ret = wsa884x_gpio_ctrl(wsa884x, false);
  1538. if (ret)
  1539. dev_err_ratelimited(wsa884x->dev, "%s: Failed to disable gpio\n", __func__);
  1540. return ret;
  1541. }
  1542. static int wsa884x_swr_reset(struct wsa884x_priv *wsa884x)
  1543. {
  1544. u8 retry = WSA884X_NUM_RETRY;
  1545. u8 devnum = 0;
  1546. struct swr_device *pdev;
  1547. pdev = wsa884x->swr_slave;
  1548. while (swr_get_logical_dev_num(pdev, pdev->addr, &devnum) && retry--) {
  1549. /* Retry after 1 msec delay */
  1550. usleep_range(1000, 1100);
  1551. }
  1552. pdev->dev_num = devnum;
  1553. wsa884x_regcache_sync(wsa884x);
  1554. return 0;
  1555. }
  1556. static int wsa884x_event_notify(struct notifier_block *nb,
  1557. unsigned long val, void *ptr)
  1558. {
  1559. u16 event = (val & 0xffff);
  1560. struct wsa884x_priv *wsa884x = container_of(nb, struct wsa884x_priv,
  1561. parent_nblock);
  1562. if (!wsa884x)
  1563. return -EINVAL;
  1564. switch (event) {
  1565. case BOLERO_SLV_EVT_PA_OFF_PRE_SSR:
  1566. if (test_bit(SPKR_STATUS, &wsa884x->status_mask))
  1567. snd_soc_component_update_bits(wsa884x->component,
  1568. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x00));
  1569. wsa884x_swr_down(wsa884x);
  1570. break;
  1571. case BOLERO_SLV_EVT_SSR_UP:
  1572. wsa884x_swr_up(wsa884x);
  1573. /* Add delay to allow enumerate */
  1574. usleep_range(20000, 20010);
  1575. wsa884x_swr_reset(wsa884x);
  1576. dev_err(wsa884x->dev, "%s: BOLERO_SLV_EVT_SSR_UP Called", __func__);
  1577. swr_init_port_params(wsa884x->swr_slave, WSA884X_MAX_SWR_PORTS,
  1578. wsa884x->swr_wsa_port_params);
  1579. break;
  1580. case BOLERO_SLV_EVT_PA_ON_POST_FSCLK:
  1581. if (test_bit(SPKR_STATUS, &wsa884x->status_mask)) {
  1582. snd_soc_component_update_bits(wsa884x->component,
  1583. REG_FIELD_VALUE(PDM_WD_CTL, PDM_WD_EN, 0x01));
  1584. snd_soc_component_update_bits(wsa884x->component,
  1585. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x01));
  1586. }
  1587. break;
  1588. case BOLERO_SLV_EVT_PA_ON_POST_FSCLK_ADIE_LB:
  1589. if (test_bit(SPKR_STATUS, &wsa884x->status_mask))
  1590. set_bit(SPKR_ADIE_LB, &wsa884x->status_mask);
  1591. break;
  1592. default:
  1593. dev_dbg(wsa884x->dev, "%s: unknown event %d\n",
  1594. __func__, event);
  1595. break;
  1596. }
  1597. return 0;
  1598. }
  1599. static int wsa884x_parse_port_params(struct device *dev, char *prop)
  1600. {
  1601. u32 *dt_array, map_size, max_uc;
  1602. int ret = 0;
  1603. u32 cnt = 0;
  1604. u32 i, j;
  1605. struct swr_port_params (*map)[SWR_UC_MAX][WSA884X_MAX_SWR_PORTS];
  1606. struct swr_dev_frame_config (*map_uc)[SWR_UC_MAX];
  1607. struct wsa884x_priv *wsa884x = dev_get_drvdata(dev);
  1608. map = &wsa884x->wsa_port_params;
  1609. map_uc = &wsa884x->swr_wsa_port_params;
  1610. if (!of_find_property(dev->of_node, prop,
  1611. &map_size)) {
  1612. dev_err(dev, "missing port mapping prop %s\n", prop);
  1613. ret = -EINVAL;
  1614. goto err_port_map;
  1615. }
  1616. max_uc = map_size / (WSA884X_MAX_SWR_PORTS * SWR_PORT_PARAMS * sizeof(u32));
  1617. if (max_uc != SWR_UC_MAX) {
  1618. dev_err(dev, "%s: port params not provided for all usecases\n",
  1619. __func__);
  1620. ret = -EINVAL;
  1621. goto err_port_map;
  1622. }
  1623. dt_array = kzalloc(map_size, GFP_KERNEL);
  1624. if (!dt_array) {
  1625. ret = -ENOMEM;
  1626. goto err_port_map;
  1627. }
  1628. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  1629. WSA884X_MAX_SWR_PORTS * SWR_PORT_PARAMS * max_uc);
  1630. if (ret) {
  1631. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  1632. __func__, prop);
  1633. goto err_pdata_fail;
  1634. }
  1635. for (i = 0; i < max_uc; i++) {
  1636. for (j = 0; j < WSA884X_MAX_SWR_PORTS; j++) {
  1637. cnt = (i * WSA884X_MAX_SWR_PORTS + j) * SWR_PORT_PARAMS;
  1638. (*map)[i][j].offset1 = dt_array[cnt];
  1639. (*map)[i][j].lane_ctrl = dt_array[cnt + 1];
  1640. }
  1641. (*map_uc)[i].pp = &(*map)[i][0];
  1642. }
  1643. kfree(dt_array);
  1644. return 0;
  1645. err_pdata_fail:
  1646. kfree(dt_array);
  1647. err_port_map:
  1648. return ret;
  1649. }
  1650. static int wsa884x_enable_supplies(struct device *dev,
  1651. struct wsa884x_priv *priv)
  1652. {
  1653. int ret = 0;
  1654. /* Parse power supplies */
  1655. msm_cdc_get_power_supplies(dev, &priv->regulator,
  1656. &priv->num_supplies);
  1657. if (!priv->regulator || (priv->num_supplies <= 0)) {
  1658. dev_err(dev, "%s: no power supplies defined\n", __func__);
  1659. return -EINVAL;
  1660. }
  1661. ret = msm_cdc_init_supplies(dev, &priv->supplies,
  1662. priv->regulator, priv->num_supplies);
  1663. if (!priv->supplies) {
  1664. dev_err(dev, "%s: Cannot init wsa supplies\n",
  1665. __func__);
  1666. return ret;
  1667. }
  1668. ret = msm_cdc_enable_static_supplies(dev, priv->supplies,
  1669. priv->regulator,
  1670. priv->num_supplies);
  1671. if (ret)
  1672. dev_err(dev, "%s: wsa static supply enable failed!\n",
  1673. __func__);
  1674. return ret;
  1675. }
  1676. static struct snd_soc_dai_driver wsa_dai[] = {
  1677. {
  1678. .name = "",
  1679. .playback = {
  1680. .stream_name = "",
  1681. .rates = WSA884X_RATES | WSA884X_FRAC_RATES,
  1682. .formats = WSA884X_FORMATS,
  1683. .rate_max = 192000,
  1684. .rate_min = 8000,
  1685. .channels_min = 1,
  1686. .channels_max = 2,
  1687. },
  1688. },
  1689. };
  1690. static int wsa884x_swr_probe(struct swr_device *pdev)
  1691. {
  1692. int ret = 0;
  1693. struct wsa884x_priv *wsa884x;
  1694. u8 devnum = 0;
  1695. bool pin_state_current = false;
  1696. struct wsa_ctrl_platform_data *plat_data = NULL;
  1697. struct snd_soc_component *component;
  1698. u32 noise_gate_mode;
  1699. char buffer[MAX_NAME_LEN];
  1700. int dev_index = 0;
  1701. struct regmap_irq_chip *wsa884x_sub_regmap_irq_chip = NULL;
  1702. u8 wo0_val;
  1703. int sys_gain_size, sys_gain_length;
  1704. int wsa_dev_index;
  1705. wsa884x = devm_kzalloc(&pdev->dev, sizeof(struct wsa884x_priv),
  1706. GFP_KERNEL);
  1707. if (!wsa884x)
  1708. return -ENOMEM;
  1709. wsa884x_sub_regmap_irq_chip = devm_kzalloc(&pdev->dev, sizeof(struct regmap_irq_chip),
  1710. GFP_KERNEL);
  1711. if (!wsa884x_sub_regmap_irq_chip)
  1712. return -ENOMEM;
  1713. memcpy(wsa884x_sub_regmap_irq_chip, &wsa884x_regmap_irq_chip,
  1714. sizeof(struct regmap_irq_chip));
  1715. ret = wsa884x_enable_supplies(&pdev->dev, wsa884x);
  1716. if (ret) {
  1717. ret = -EPROBE_DEFER;
  1718. goto err;
  1719. }
  1720. wsa884x->wsa_rst_np = of_parse_phandle(pdev->dev.of_node,
  1721. "qcom,spkr-sd-n-node", 0);
  1722. if (!wsa884x->wsa_rst_np) {
  1723. dev_dbg(&pdev->dev, "%s: pinctrl not defined\n", __func__);
  1724. goto err_supply;
  1725. }
  1726. swr_set_dev_data(pdev, wsa884x);
  1727. wsa884x->swr_slave = pdev;
  1728. wsa884x->dev = &pdev->dev;
  1729. pin_state_current = msm_cdc_pinctrl_get_state(wsa884x->wsa_rst_np);
  1730. wsa884x_gpio_ctrl(wsa884x, true);
  1731. /*
  1732. * Add 5msec delay to provide sufficient time for
  1733. * soundwire auto enumeration of slave devices as
  1734. * per HW requirement.
  1735. */
  1736. usleep_range(5000, 5010);
  1737. ret = swr_get_logical_dev_num(pdev, pdev->addr, &devnum);
  1738. if (ret) {
  1739. dev_dbg(&pdev->dev,
  1740. "%s get devnum %d for dev addr %lx failed\n",
  1741. __func__, devnum, pdev->addr);
  1742. ret = -EPROBE_DEFER;
  1743. goto err_supply;
  1744. }
  1745. pdev->dev_num = devnum;
  1746. wsa884x->regmap = devm_regmap_init_swr(pdev,
  1747. &wsa884x_regmap_config);
  1748. if (IS_ERR(wsa884x->regmap)) {
  1749. ret = PTR_ERR(wsa884x->regmap);
  1750. dev_err(&pdev->dev, "%s: regmap_init failed %d\n",
  1751. __func__, ret);
  1752. goto dev_err;
  1753. }
  1754. devm_regmap_qti_debugfs_register(&pdev->dev, wsa884x->regmap);
  1755. wsa884x_sub_regmap_irq_chip->irq_drv_data = wsa884x;
  1756. wsa884x->irq_info.wcd_regmap_irq_chip = wsa884x_sub_regmap_irq_chip;
  1757. wsa884x->irq_info.codec_name = "WSA884X";
  1758. wsa884x->irq_info.regmap = wsa884x->regmap;
  1759. wsa884x->irq_info.dev = &pdev->dev;
  1760. ret = wcd_irq_init(&wsa884x->irq_info, &wsa884x->virq);
  1761. if (ret) {
  1762. dev_err(wsa884x->dev, "%s: IRQ init failed: %d\n",
  1763. __func__, ret);
  1764. goto dev_err;
  1765. }
  1766. wsa884x->swr_slave->slave_irq = wsa884x->virq;
  1767. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_SAF2WAR,
  1768. "WSA SAF2WAR", wsa884x_saf2war_handle_irq, wsa884x);
  1769. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_WAR2SAF,
  1770. "WSA WAR2SAF", wsa884x_war2saf_handle_irq, wsa884x);
  1771. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_DISABLE,
  1772. "WSA OTP", wsa884x_otp_handle_irq, wsa884x);
  1773. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_OCP,
  1774. "WSA OCP", wsa884x_ocp_handle_irq, wsa884x);
  1775. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLIP,
  1776. "WSA CLIP", wsa884x_clip_handle_irq, wsa884x);
  1777. wcd_disable_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLIP);
  1778. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_PDM_WD,
  1779. "WSA PDM WD", wsa884x_pdm_wd_handle_irq, wsa884x);
  1780. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLK_WD,
  1781. "WSA CLK WD", wsa884x_clk_wd_handle_irq, wsa884x);
  1782. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_INTR_PIN,
  1783. "WSA EXT INT", wsa884x_ext_int_handle_irq, wsa884x);
  1784. wcd_disable_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_INTR_PIN);
  1785. /* Under Voltage Lock out (UVLO) interrupt handle */
  1786. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_UVLO,
  1787. "WSA UVLO", wsa884x_uvlo_handle_irq, wsa884x);
  1788. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_PA_ON_ERR,
  1789. "WSA PA ERR", wsa884x_pa_on_err_handle_irq, wsa884x);
  1790. wsa884x->driver = devm_kzalloc(&pdev->dev,
  1791. sizeof(struct snd_soc_component_driver), GFP_KERNEL);
  1792. if (!wsa884x->driver) {
  1793. ret = -ENOMEM;
  1794. goto err_irq;
  1795. }
  1796. memcpy(wsa884x->driver, &soc_codec_dev_wsa884x_wsa,
  1797. sizeof(struct snd_soc_component_driver));
  1798. wsa884x->dai_driver = devm_kzalloc(&pdev->dev,
  1799. sizeof(struct snd_soc_dai_driver), GFP_KERNEL);
  1800. if (!wsa884x->dai_driver) {
  1801. ret = -ENOMEM;
  1802. goto err_mem;
  1803. }
  1804. memcpy(wsa884x->dai_driver, wsa_dai, sizeof(struct snd_soc_dai_driver));
  1805. /* Get last digit from HEX format */
  1806. dev_index = (int)((char)(pdev->addr & 0xF));
  1807. dev_index += 1;
  1808. if (of_device_is_compatible(pdev->dev.of_node, "qcom,wsa884x_2"))
  1809. dev_index += 2;
  1810. snprintf(buffer, sizeof(buffer), "wsa-codec.%d", dev_index);
  1811. wsa884x->driver->name = kstrndup(buffer, strlen(buffer), GFP_KERNEL);
  1812. snprintf(buffer, sizeof(buffer), "wsa_rx%d", dev_index);
  1813. wsa884x->dai_driver->name =
  1814. kstrndup(buffer, strlen(buffer), GFP_KERNEL);
  1815. snprintf(buffer, sizeof(buffer), "WSA884X_AIF%d Playback", dev_index);
  1816. wsa884x->dai_driver->playback.stream_name =
  1817. kstrndup(buffer, strlen(buffer), GFP_KERNEL);
  1818. /* Number of DAI's used is 1 */
  1819. ret = snd_soc_register_component(&pdev->dev,
  1820. wsa884x->driver, wsa884x->dai_driver, 1);
  1821. component = snd_soc_lookup_component(&pdev->dev, wsa884x->driver->name);
  1822. if (!component) {
  1823. dev_err(&pdev->dev, "%s: component is NULL\n", __func__);
  1824. ret = -EINVAL;
  1825. goto err_mem;
  1826. }
  1827. wsa884x->parent_np = of_parse_phandle(pdev->dev.of_node,
  1828. "qcom,bolero-handle", 0);
  1829. if (!wsa884x->parent_np)
  1830. wsa884x->parent_np = of_parse_phandle(pdev->dev.of_node,
  1831. "qcom,lpass-cdc-handle", 0);
  1832. if (wsa884x->parent_np) {
  1833. wsa884x->parent_dev =
  1834. of_find_device_by_node(wsa884x->parent_np);
  1835. if (wsa884x->parent_dev) {
  1836. plat_data = dev_get_platdata(&wsa884x->parent_dev->dev);
  1837. if (plat_data) {
  1838. wsa884x->parent_nblock.notifier_call =
  1839. wsa884x_event_notify;
  1840. if (plat_data->register_notifier)
  1841. plat_data->register_notifier(
  1842. plat_data->handle,
  1843. &wsa884x->parent_nblock,
  1844. true);
  1845. wsa884x->register_notifier =
  1846. plat_data->register_notifier;
  1847. wsa884x->handle = plat_data->handle;
  1848. } else {
  1849. dev_err(&pdev->dev, "%s: plat data not found\n",
  1850. __func__);
  1851. }
  1852. } else {
  1853. dev_err(&pdev->dev, "%s: parent dev not found\n",
  1854. __func__);
  1855. }
  1856. } else {
  1857. dev_info(&pdev->dev, "%s: parent node not found\n", __func__);
  1858. }
  1859. /* Start in speaker mode by default */
  1860. wsa884x->dev_mode = SPEAKER;
  1861. wsa884x->dev_index = dev_index;
  1862. /* wsa_dev_index is macro_agnostic index */
  1863. wsa_dev_index = (wsa884x->dev_index - 1) % 2;
  1864. wsa884x->macro_np = of_parse_phandle(pdev->dev.of_node,
  1865. "qcom,wsa-macro-handle", 0);
  1866. if (wsa884x->macro_np) {
  1867. wsa884x->macro_dev =
  1868. of_find_device_by_node(wsa884x->macro_np);
  1869. if (wsa884x->macro_dev) {
  1870. ret = of_property_read_u32_index(
  1871. wsa884x->macro_dev->dev.of_node,
  1872. "qcom,wsa-rloads",
  1873. wsa_dev_index,
  1874. &wsa884x->rload);
  1875. if (ret) {
  1876. dev_err(&pdev->dev,
  1877. "%s: Failed to read wsa rloads\n",
  1878. __func__);
  1879. goto err_mem;
  1880. }
  1881. ret = of_property_read_u32_index(
  1882. wsa884x->macro_dev->dev.of_node,
  1883. "qcom,wsa-bat-cfgs",
  1884. wsa_dev_index,
  1885. &wsa884x->bat_cfg);
  1886. if (ret) {
  1887. dev_err(&pdev->dev,
  1888. "%s: Failed to read wsa bat cfgs\n",
  1889. __func__);
  1890. goto err_mem;
  1891. }
  1892. ret = of_property_read_u32(wsa884x->macro_dev->dev.of_node,
  1893. "qcom,noise-gate-mode", &noise_gate_mode);
  1894. if (ret) {
  1895. dev_info(&pdev->dev,
  1896. "%s: Failed to read wsa noise gate mode\n",
  1897. __func__);
  1898. wsa884x->noise_gate_mode = IDLE_DETECT;
  1899. } else {
  1900. if (IDLE_DETECT <= noise_gate_mode && noise_gate_mode <= NG3)
  1901. wsa884x->noise_gate_mode = noise_gate_mode;
  1902. else
  1903. wsa884x->noise_gate_mode = IDLE_DETECT;
  1904. }
  1905. if (!of_find_property(wsa884x->macro_dev->dev.of_node,
  1906. "qcom,wsa-system-gains", &sys_gain_size)) {
  1907. dev_err(&pdev->dev,
  1908. "%s: missing wsa-system-gains\n",
  1909. __func__);
  1910. goto err_mem;
  1911. }
  1912. sys_gain_length = sys_gain_size / (2 * sizeof(u32));
  1913. ret = of_property_read_u32_array(
  1914. wsa884x->macro_dev->dev.of_node,
  1915. "qcom,wsa-system-gains", wsa884x->sys_gains,
  1916. sys_gain_length);
  1917. if (ret) {
  1918. dev_err(&pdev->dev,
  1919. "%s: Failed to read wsa system gains\n",
  1920. __func__);
  1921. goto err_mem;
  1922. }
  1923. wsa884x->system_gain = wsa884x->sys_gains[
  1924. wsa884x->dev_mode + wsa_dev_index * 2];
  1925. } else {
  1926. dev_err(&pdev->dev, "%s: parent dev not found\n",
  1927. __func__);
  1928. goto err_mem;
  1929. }
  1930. } else {
  1931. dev_err(&pdev->dev, "%s: parent node not found\n", __func__);
  1932. goto err_mem;
  1933. }
  1934. dev_dbg(component->dev,
  1935. "%s: Bat_cfg: 0x%x rload: 0x%x, sys_gain: 0x%x\n", __func__,
  1936. wsa884x->bat_cfg, wsa884x->rload, wsa884x->system_gain);
  1937. ret = wsa884x_validate_dt_configuration_params(component, wsa884x->rload,
  1938. wsa884x->bat_cfg, wsa884x->system_gain);
  1939. if (ret) {
  1940. dev_err(&pdev->dev,
  1941. "%s: invalid dt parameter: Bat_cfg: 0x%x rload: 0x%x, sys_gain: 0x%x\n",
  1942. __func__, wsa884x->bat_cfg, wsa884x->rload, wsa884x->system_gain);
  1943. ret = -EINVAL;
  1944. goto err_mem;
  1945. }
  1946. /* Assume that compander is enabled by default unless it is haptics sku */
  1947. if (wsa884x->variant == WSA8845H)
  1948. wsa884x->comp_enable = false;
  1949. else
  1950. wsa884x->comp_enable = true;
  1951. wsa884x_set_gain_parameters(component);
  1952. wsa884x_set_pbr_parameters(component);
  1953. /* Must write WO registers in a single write */
  1954. wo0_val = (0xC0 | (wsa884x->pa_aux_gain << 0x02) | !wsa884x->dev_mode);
  1955. snd_soc_component_write(component, WSA884X_ANA_WO_CTL_0, wo0_val);
  1956. snd_soc_component_write(component, WSA884X_ANA_WO_CTL_1, 0x0);
  1957. if (wsa884x->rload == WSA_4_OHMS || wsa884x->rload == WSA_6_OHMS)
  1958. snd_soc_component_update_bits(component,
  1959. REG_FIELD_VALUE(OCP_CTL, OCP_CURR_LIMIT, 0x07));
  1960. if (wsa884x->dev_mode == SPEAKER) {
  1961. snd_soc_component_update_bits(component,
  1962. REG_FIELD_VALUE(DRE_CTL_0, PROG_DELAY, 0x0F));
  1963. } else {
  1964. snd_soc_component_update_bits(component,
  1965. REG_FIELD_VALUE(DRE_CTL_0, PROG_DELAY, 0x03));
  1966. snd_soc_component_update_bits(component,
  1967. REG_FIELD_VALUE(CDC_PATH_MODE, RXD_MODE, 0x01));
  1968. snd_soc_component_update_bits(component,
  1969. REG_FIELD_VALUE(PWM_CLK_CTL,
  1970. PWM_CLK_FREQ_SEL, 0x01));
  1971. }
  1972. if (wsa884x->bat_cfg != CONFIG_1S && wsa884x->bat_cfg != EXT_1S)
  1973. snd_soc_component_update_bits(component,
  1974. REG_FIELD_VALUE(TOP_CTRL1,
  1975. OCP_LOWVBAT_ITH_SEL_EN, 0x00));
  1976. ret = wsa884x_parse_port_params(&pdev->dev, "qcom,swr-wsa-port-params");
  1977. if (ret) {
  1978. dev_err(&pdev->dev, "Failed to read port params\n");
  1979. goto err;
  1980. }
  1981. swr_init_port_params(wsa884x->swr_slave, WSA884X_MAX_SWR_PORTS,
  1982. wsa884x->swr_wsa_port_params);
  1983. mutex_init(&wsa884x->res_lock);
  1984. #ifdef CONFIG_DEBUG_FS
  1985. if (!wsa884x->debugfs_dent) {
  1986. wsa884x->debugfs_dent = debugfs_create_dir(
  1987. dev_name(&pdev->dev), 0);
  1988. if (!IS_ERR(wsa884x->debugfs_dent)) {
  1989. wsa884x->debugfs_peek =
  1990. debugfs_create_file("swrslave_peek",
  1991. S_IFREG | 0444,
  1992. wsa884x->debugfs_dent,
  1993. (void *) pdev,
  1994. &codec_debug_read_ops);
  1995. wsa884x->debugfs_poke =
  1996. debugfs_create_file("swrslave_poke",
  1997. S_IFREG | 0444,
  1998. wsa884x->debugfs_dent,
  1999. (void *) pdev,
  2000. &codec_debug_write_ops);
  2001. wsa884x->debugfs_reg_dump =
  2002. debugfs_create_file(
  2003. "swrslave_reg_dump",
  2004. S_IFREG | 0444,
  2005. wsa884x->debugfs_dent,
  2006. (void *) pdev,
  2007. &codec_debug_dump_ops);
  2008. }
  2009. }
  2010. #endif
  2011. return 0;
  2012. err_mem:
  2013. if (wsa884x->dai_driver) {
  2014. kfree(wsa884x->dai_driver->name);
  2015. kfree(wsa884x->dai_driver->playback.stream_name);
  2016. kfree(wsa884x->dai_driver);
  2017. }
  2018. if (wsa884x->driver) {
  2019. kfree(wsa884x->driver->name);
  2020. kfree(wsa884x->driver);
  2021. }
  2022. err_irq:
  2023. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_SAF2WAR, NULL);
  2024. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_WAR2SAF, NULL);
  2025. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_DISABLE, NULL);
  2026. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_OCP, NULL);
  2027. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLIP, NULL);
  2028. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_PDM_WD, NULL);
  2029. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLK_WD, NULL);
  2030. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_INTR_PIN, NULL);
  2031. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_UVLO, NULL);
  2032. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_PA_ON_ERR, NULL);
  2033. wcd_irq_exit(&wsa884x->irq_info, wsa884x->virq);
  2034. dev_err:
  2035. if (pin_state_current == false)
  2036. wsa884x_gpio_ctrl(wsa884x, false);
  2037. swr_remove_device(pdev);
  2038. err_supply:
  2039. msm_cdc_release_supplies(&pdev->dev, wsa884x->supplies,
  2040. wsa884x->regulator,
  2041. wsa884x->num_supplies);
  2042. err:
  2043. swr_set_dev_data(pdev, NULL);
  2044. return ret;
  2045. }
  2046. static int wsa884x_swr_remove(struct swr_device *pdev)
  2047. {
  2048. struct wsa884x_priv *wsa884x;
  2049. wsa884x = swr_get_dev_data(pdev);
  2050. if (!wsa884x) {
  2051. dev_err(&pdev->dev, "%s: wsa884x is NULL\n", __func__);
  2052. return -EINVAL;
  2053. }
  2054. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_SAF2WAR, NULL);
  2055. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_WAR2SAF, NULL);
  2056. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_DISABLE, NULL);
  2057. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_OCP, NULL);
  2058. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLIP, NULL);
  2059. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_PDM_WD, NULL);
  2060. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLK_WD, NULL);
  2061. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_INTR_PIN, NULL);
  2062. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_UVLO, NULL);
  2063. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_PA_ON_ERR, NULL);
  2064. if (wsa884x->register_notifier)
  2065. wsa884x->register_notifier(wsa884x->handle,
  2066. &wsa884x->parent_nblock, false);
  2067. #ifdef CONFIG_DEBUG_FS
  2068. debugfs_remove_recursive(wsa884x->debugfs_dent);
  2069. wsa884x->debugfs_dent = NULL;
  2070. #endif
  2071. mutex_destroy(&wsa884x->res_lock);
  2072. snd_soc_unregister_component(&pdev->dev);
  2073. if (wsa884x->dai_driver) {
  2074. kfree(wsa884x->dai_driver->name);
  2075. kfree(wsa884x->dai_driver->playback.stream_name);
  2076. kfree(wsa884x->dai_driver);
  2077. }
  2078. if (wsa884x->driver) {
  2079. kfree(wsa884x->driver->name);
  2080. kfree(wsa884x->driver);
  2081. }
  2082. msm_cdc_release_supplies(&pdev->dev, wsa884x->supplies,
  2083. wsa884x->regulator,
  2084. wsa884x->num_supplies);
  2085. swr_set_dev_data(pdev, NULL);
  2086. return 0;
  2087. }
  2088. #ifdef CONFIG_PM_SLEEP
  2089. static int wsa884x_swr_suspend(struct device *dev)
  2090. {
  2091. struct wsa884x_priv *wsa884x = swr_get_dev_data(to_swr_device(dev));
  2092. if (!wsa884x) {
  2093. dev_err_ratelimited(dev, "%s: wsa884x private data is NULL\n", __func__);
  2094. return -EINVAL;
  2095. }
  2096. dev_dbg(dev, "%s: system suspend\n", __func__);
  2097. if (wsa884x->dapm_bias_off ||
  2098. (snd_soc_component_get_bias_level(wsa884x->component) ==
  2099. SND_SOC_BIAS_OFF)) {
  2100. msm_cdc_set_supplies_lpm_mode(dev, wsa884x->supplies,
  2101. wsa884x->regulator,
  2102. wsa884x->num_supplies,
  2103. true);
  2104. set_bit(WSA_SUPPLIES_LPM_MODE, &wsa884x->status_mask);
  2105. }
  2106. return 0;
  2107. }
  2108. static int wsa884x_swr_resume(struct device *dev)
  2109. {
  2110. struct wsa884x_priv *wsa884x = swr_get_dev_data(to_swr_device(dev));
  2111. if (!wsa884x) {
  2112. dev_err(dev, "%s: wsa884x private data is NULL\n", __func__);
  2113. return -EINVAL;
  2114. }
  2115. if (test_bit(WSA_SUPPLIES_LPM_MODE, &wsa884x->status_mask)) {
  2116. msm_cdc_set_supplies_lpm_mode(dev, wsa884x->supplies,
  2117. wsa884x->regulator,
  2118. wsa884x->num_supplies,
  2119. false);
  2120. clear_bit(WSA_SUPPLIES_LPM_MODE, &wsa884x->status_mask);
  2121. }
  2122. dev_dbg(dev, "%s: system resume\n", __func__);
  2123. return 0;
  2124. }
  2125. #endif /* CONFIG_PM_SLEEP */
  2126. static const struct dev_pm_ops wsa884x_swr_pm_ops = {
  2127. .suspend_late = wsa884x_swr_suspend,
  2128. .resume_early = wsa884x_swr_resume,
  2129. };
  2130. static const struct swr_device_id wsa884x_swr_id[] = {
  2131. {"wsa884x", 0},
  2132. {"wsa884x_2", 0},
  2133. {}
  2134. };
  2135. static const struct of_device_id wsa884x_swr_dt_match[] = {
  2136. {
  2137. .compatible = "qcom,wsa884x",
  2138. },
  2139. {
  2140. .compatible = "qcom,wsa884x_2",
  2141. },
  2142. {}
  2143. };
  2144. static struct swr_driver wsa884x_swr_driver = {
  2145. .driver = {
  2146. .name = "wsa884x",
  2147. .owner = THIS_MODULE,
  2148. .pm = &wsa884x_swr_pm_ops,
  2149. .of_match_table = wsa884x_swr_dt_match,
  2150. },
  2151. .probe = wsa884x_swr_probe,
  2152. .remove = wsa884x_swr_remove,
  2153. .id_table = wsa884x_swr_id,
  2154. };
  2155. static int __init wsa884x_swr_init(void)
  2156. {
  2157. return swr_driver_register(&wsa884x_swr_driver);
  2158. }
  2159. static void __exit wsa884x_swr_exit(void)
  2160. {
  2161. swr_driver_unregister(&wsa884x_swr_driver);
  2162. }
  2163. module_init(wsa884x_swr_init);
  2164. module_exit(wsa884x_swr_exit);
  2165. MODULE_DESCRIPTION("WSA884x codec driver");
  2166. MODULE_LICENSE("GPL v2");