sde_hw_mdss.h 20 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  5. */
  6. #ifndef _SDE_HW_MDSS_H
  7. #define _SDE_HW_MDSS_H
  8. #include <linux/kernel.h>
  9. #include <linux/err.h>
  10. #include <drm/sde_drm.h>
  11. #include <drm/msm_drm_pp.h>
  12. #include "msm_drv.h"
  13. #define SDE_DBG_NAME "sde"
  14. #define SDE_NONE 0
  15. #ifndef SDE_CSC_MATRIX_COEFF_SIZE
  16. #define SDE_CSC_MATRIX_COEFF_SIZE 9
  17. #endif
  18. #ifndef SDE_CSC_CLAMP_SIZE
  19. #define SDE_CSC_CLAMP_SIZE 6
  20. #endif
  21. #ifndef SDE_CSC_BIAS_SIZE
  22. #define SDE_CSC_BIAS_SIZE 3
  23. #endif
  24. #ifndef SDE_MAX_PLANES
  25. #define SDE_MAX_PLANES 4
  26. #endif
  27. #define PIPES_PER_STAGE 2
  28. #ifndef SDE_MAX_DE_CURVES
  29. #define SDE_MAX_DE_CURVES 3
  30. #endif
  31. #define MAX_DSI_DISPLAYS 2
  32. #define MAX_DATA_PATH_PER_DSIPLAY 4
  33. enum sde_format_flags {
  34. SDE_FORMAT_FLAG_YUV_BIT,
  35. SDE_FORMAT_FLAG_DX_BIT,
  36. SDE_FORMAT_FLAG_COMPRESSED_BIT,
  37. SDE_FORMAT_FLAG_ALPHA_SWAP_BIT,
  38. SDE_FORMAT_FLAG_FP16_BIT,
  39. SDE_FORMAT_FLAG_BIT_MAX,
  40. };
  41. #define SDE_FORMAT_FLAG_YUV BIT(SDE_FORMAT_FLAG_YUV_BIT)
  42. #define SDE_FORMAT_FLAG_DX BIT(SDE_FORMAT_FLAG_DX_BIT)
  43. #define SDE_FORMAT_FLAG_COMPRESSED BIT(SDE_FORMAT_FLAG_COMPRESSED_BIT)
  44. #define SDE_FORMAT_FLAG_ALPHA_SWAP BIT(SDE_FORMAT_FLAG_ALPHA_SWAP_BIT)
  45. #define SDE_FORMAT_FLAG_FP16 BIT(SDE_FORMAT_FLAG_FP16_BIT)
  46. #define SDE_FORMAT_IS_YUV(X) \
  47. (test_bit(SDE_FORMAT_FLAG_YUV_BIT, (X)->flag))
  48. #define SDE_FORMAT_IS_DX(X) \
  49. (test_bit(SDE_FORMAT_FLAG_DX_BIT, (X)->flag))
  50. #define SDE_FORMAT_IS_LINEAR(X) ((X)->fetch_mode == SDE_FETCH_LINEAR)
  51. #define SDE_FORMAT_IS_TILE(X) \
  52. (((X)->fetch_mode == SDE_FETCH_UBWC) && \
  53. !test_bit(SDE_FORMAT_FLAG_COMPRESSED_BIT, (X)->flag))
  54. #define SDE_FORMAT_IS_UBWC(X) \
  55. (((X)->fetch_mode == SDE_FETCH_UBWC) && \
  56. test_bit(SDE_FORMAT_FLAG_COMPRESSED_BIT, (X)->flag))
  57. #define SDE_FORMAT_IS_ALPHA_SWAPPED(X) \
  58. (test_bit(SDE_FORMAT_FLAG_ALPHA_SWAP_BIT, (X)->flag))
  59. #define SDE_FORMAT_IS_FP16(X) \
  60. (test_bit(SDE_FORMAT_FLAG_FP16_BIT, (X)->flag))
  61. #define MDP_TICK_COUNT 16
  62. #define XO_CLK_RATE 19200
  63. #define MS_TICKS_IN_SEC 1000
  64. #define CALCULATE_WD_LOAD_VALUE(fps) \
  65. ((uint32_t)((MS_TICKS_IN_SEC * XO_CLK_RATE)/(MDP_TICK_COUNT * fps)))
  66. #define SDE_BLEND_FG_ALPHA_FG_CONST (0 << 0)
  67. #define SDE_BLEND_FG_ALPHA_BG_CONST (1 << 0)
  68. #define SDE_BLEND_FG_ALPHA_FG_PIXEL (2 << 0)
  69. #define SDE_BLEND_FG_ALPHA_BG_PIXEL (3 << 0)
  70. #define SDE_BLEND_FG_INV_ALPHA (1 << 2)
  71. #define SDE_BLEND_FG_MOD_ALPHA (1 << 3)
  72. #define SDE_BLEND_FG_INV_MOD_ALPHA (1 << 4)
  73. #define SDE_BLEND_FG_TRANSP_EN (1 << 5)
  74. #define SDE_BLEND_BG_ALPHA_FG_CONST (0 << 8)
  75. #define SDE_BLEND_BG_ALPHA_BG_CONST (1 << 8)
  76. #define SDE_BLEND_BG_ALPHA_FG_PIXEL (2 << 8)
  77. #define SDE_BLEND_BG_ALPHA_BG_PIXEL (3 << 8)
  78. #define SDE_BLEND_BG_INV_ALPHA (1 << 10)
  79. #define SDE_BLEND_BG_MOD_ALPHA (1 << 11)
  80. #define SDE_BLEND_BG_INV_MOD_ALPHA (1 << 12)
  81. #define SDE_BLEND_BG_TRANSP_EN (1 << 13)
  82. #define SDE_VSYNC0_SOURCE_GPIO 0
  83. #define SDE_VSYNC1_SOURCE_GPIO 1
  84. #define SDE_VSYNC2_SOURCE_GPIO 2
  85. #define SDE_VSYNC_SOURCE_INTF_0 3
  86. #define SDE_VSYNC_SOURCE_INTF_1 4
  87. #define SDE_VSYNC_SOURCE_INTF_2 5
  88. #define SDE_VSYNC_SOURCE_INTF_3 6
  89. #define SDE_VSYNC_SOURCE_WD_TIMER_4 11
  90. #define SDE_VSYNC_SOURCE_WD_TIMER_3 12
  91. #define SDE_VSYNC_SOURCE_WD_TIMER_2 13
  92. #define SDE_VSYNC_SOURCE_WD_TIMER_1 14
  93. #define SDE_VSYNC_SOURCE_WD_TIMER_0 15
  94. enum sde_hw_blk_type {
  95. SDE_HW_BLK_TOP = 0,
  96. SDE_HW_BLK_SSPP,
  97. SDE_HW_BLK_LM,
  98. SDE_HW_BLK_DSPP,
  99. SDE_HW_BLK_DS,
  100. SDE_HW_BLK_CTL,
  101. SDE_HW_BLK_CDM,
  102. SDE_HW_BLK_PINGPONG,
  103. SDE_HW_BLK_INTF,
  104. SDE_HW_BLK_WB,
  105. SDE_HW_BLK_DSC,
  106. SDE_HW_BLK_VDC,
  107. SDE_HW_BLK_MERGE_3D,
  108. SDE_HW_BLK_QDSS,
  109. SDE_HW_BLK_DNSC_BLUR,
  110. SDE_HW_BLK_MAX,
  111. };
  112. enum sde_uidle {
  113. UIDLE = 0x1,
  114. UIDLE_MAX,
  115. };
  116. enum sde_mdp {
  117. MDP_TOP = 0x1,
  118. MDP_MAX,
  119. };
  120. enum sde_sspp {
  121. SSPP_NONE,
  122. SSPP_VIG0,
  123. SSPP_VIG1,
  124. SSPP_VIG2,
  125. SSPP_VIG3,
  126. SSPP_VIG_MAX = SSPP_VIG3,
  127. SSPP_DMA0,
  128. SSPP_DMA1,
  129. SSPP_DMA2,
  130. SSPP_DMA3,
  131. SSPP_DMA4,
  132. SSPP_DMA5,
  133. SSPP_DMA_MAX = SSPP_DMA5,
  134. SSPP_MAX
  135. };
  136. #define SDE_SSPP_VALID(x) ((x) > SSPP_NONE && (x) < SSPP_MAX)
  137. #define SDE_SSPP_VALID_VIG(x) ((x) >= SSPP_VIG0 && (x) <= SSPP_VIG_MAX)
  138. #define SDE_SSPP_VALID_DMA(x) ((x) >= SSPP_DMA0 && (x) <= SSPP_DMA_MAX)
  139. enum sde_sspp_type {
  140. SSPP_TYPE_VIG,
  141. SSPP_TYPE_DMA,
  142. SSPP_TYPE_MAX
  143. };
  144. enum sde_sspp_rect {
  145. R0,
  146. R1,
  147. R_MAX
  148. };
  149. enum sde_lm {
  150. LM_0 = 1,
  151. LM_1,
  152. LM_2,
  153. LM_3,
  154. LM_4,
  155. LM_5,
  156. LM_DCWB_DUMMY_0,
  157. LM_DCWB_DUMMY_1,
  158. LM_6,
  159. LM_MAX
  160. };
  161. enum sde_stage {
  162. SDE_STAGE_BASE = 0,
  163. SDE_STAGE_0,
  164. SDE_STAGE_1,
  165. SDE_STAGE_2,
  166. SDE_STAGE_3,
  167. SDE_STAGE_4,
  168. SDE_STAGE_5,
  169. SDE_STAGE_6,
  170. SDE_STAGE_7,
  171. SDE_STAGE_8,
  172. SDE_STAGE_9,
  173. SDE_STAGE_10,
  174. SDE_STAGE_MAX
  175. };
  176. enum sde_dspp {
  177. DSPP_0 = 1,
  178. DSPP_1,
  179. DSPP_2,
  180. DSPP_3,
  181. DSPP_MAX
  182. };
  183. enum sde_ltm {
  184. LTM_0 = DSPP_0,
  185. LTM_1,
  186. LTM_2,
  187. LTM_3,
  188. LTM_MAX
  189. };
  190. enum sde_rc {
  191. RC_0 = DSPP_0,
  192. RC_1,
  193. RC_2,
  194. RC_3,
  195. RC_MAX
  196. };
  197. enum sde_ds {
  198. DS_TOP,
  199. DS_0,
  200. DS_1,
  201. DS_MAX
  202. };
  203. enum sde_ctl {
  204. CTL_0 = 1,
  205. CTL_1,
  206. CTL_2,
  207. CTL_3,
  208. CTL_4,
  209. CTL_5,
  210. CTL_MAX
  211. };
  212. enum sde_cdm {
  213. CDM_0 = 1,
  214. CDM_1,
  215. CDM_MAX
  216. };
  217. enum sde_dnsc_blur {
  218. DNSC_BLUR_0 = 1,
  219. DNSC_BLUR__MAX
  220. };
  221. enum sde_pingpong {
  222. PINGPONG_0 = 1,
  223. PINGPONG_1,
  224. PINGPONG_2,
  225. PINGPONG_3,
  226. PINGPONG_4,
  227. PINGPONG_5,
  228. PINGPONG_CWB_0,
  229. PINGPONG_CWB_1,
  230. PINGPONG_S0,
  231. PINGPONG_MAX
  232. };
  233. enum sde_dsc {
  234. DSC_NONE = 0,
  235. DSC_0,
  236. DSC_1,
  237. DSC_2,
  238. DSC_3,
  239. DSC_4,
  240. DSC_5,
  241. DSC_MAX
  242. };
  243. enum sde_vdc {
  244. VDC_NONE = 0,
  245. VDC_0,
  246. VDC_1,
  247. VDC_MAX
  248. };
  249. enum sde_intf {
  250. INTF_0 = 1,
  251. INTF_1,
  252. INTF_2,
  253. INTF_3,
  254. INTF_4,
  255. INTF_5,
  256. INTF_6,
  257. INTF_MAX
  258. };
  259. enum sde_intf_type {
  260. INTF_NONE = 0x0,
  261. INTF_DSI = 0x1,
  262. INTF_HDMI = 0x3,
  263. INTF_LCDC = 0x5,
  264. INTF_EDP = 0x9,
  265. INTF_DP = 0xa,
  266. INTF_TYPE_MAX,
  267. /* virtual interfaces */
  268. INTF_WB = 0x100,
  269. };
  270. enum sde_intf_mode {
  271. INTF_MODE_NONE = 0,
  272. INTF_MODE_CMD,
  273. INTF_MODE_VIDEO,
  274. INTF_MODE_WB_BLOCK,
  275. INTF_MODE_WB_LINE,
  276. INTF_MODE_MAX
  277. };
  278. enum sde_wb {
  279. WB_0 = 1,
  280. WB_1,
  281. WB_2,
  282. WB_3,
  283. WB_MAX
  284. };
  285. enum sde_ad {
  286. AD_0 = 0x1,
  287. AD_1,
  288. AD_MAX
  289. };
  290. enum sde_cwb {
  291. CWB_0 = 0x1,
  292. CWB_1,
  293. CWB_2,
  294. CWB_3,
  295. CWB_4,
  296. CWB_5,
  297. CWB_MAX
  298. };
  299. enum sde_dcwb {
  300. DCWB_0 = 0x1,
  301. DCWB_1,
  302. DCWB_MAX
  303. };
  304. enum sde_wd_timer {
  305. WD_TIMER_0 = 0x1,
  306. WD_TIMER_1,
  307. WD_TIMER_2,
  308. WD_TIMER_3,
  309. WD_TIMER_4,
  310. WD_TIMER_5,
  311. WD_TIMER_MAX
  312. };
  313. enum sde_vbif {
  314. VBIF_0,
  315. VBIF_1,
  316. VBIF_MAX,
  317. VBIF_RT = VBIF_0,
  318. VBIF_NRT = VBIF_1
  319. };
  320. enum sde_iommu_domain {
  321. SDE_IOMMU_DOMAIN_UNSECURE,
  322. SDE_IOMMU_DOMAIN_SECURE,
  323. SDE_IOMMU_DOMAIN_MAX
  324. };
  325. enum sde_rot {
  326. ROT_0 = 1,
  327. ROT_MAX
  328. };
  329. enum sde_merge_3d {
  330. MERGE_3D_0 = 1,
  331. MERGE_3D_1,
  332. MERGE_3D_2,
  333. MERGE_3D_CWB_0,
  334. MERGE_3D_MAX
  335. };
  336. enum sde_qdss {
  337. QDSS_0,
  338. QDSS_MAX
  339. };
  340. /**
  341. * SDE HW,Component order color map
  342. */
  343. enum {
  344. C0_G_Y = 0,
  345. C1_B_Cb = 1,
  346. C2_R_Cr = 2,
  347. C3_ALPHA = 3
  348. };
  349. /**
  350. * enum sde_plane_type - defines how the color component pixel packing
  351. * @SDE_PLANE_INTERLEAVED : Color components in single plane
  352. * @SDE_PLANE_PLANAR : Color component in separate planes
  353. * @SDE_PLANE_PSEUDO_PLANAR : Chroma components interleaved in separate plane
  354. */
  355. enum sde_plane_type {
  356. SDE_PLANE_INTERLEAVED,
  357. SDE_PLANE_PLANAR,
  358. SDE_PLANE_PSEUDO_PLANAR,
  359. };
  360. /**
  361. * enum sde_chroma_samp_type - chroma sub-samplng type
  362. * @SDE_CHROMA_RGB : No chroma subsampling
  363. * @SDE_CHROMA_H2V1 : Chroma pixels are horizontally subsampled
  364. * @SDE_CHROMA_H1V2 : Chroma pixels are vertically subsampled
  365. * @SDE_CHROMA_420 : 420 subsampling
  366. */
  367. enum sde_chroma_samp_type {
  368. SDE_CHROMA_RGB,
  369. SDE_CHROMA_H2V1,
  370. SDE_CHROMA_H1V2,
  371. SDE_CHROMA_420
  372. };
  373. /**
  374. * sde_fetch_type - Defines How SDE HW fetches data
  375. * @SDE_FETCH_LINEAR : fetch is line by line
  376. * @SDE_FETCH_TILE : fetches data in Z order from a tile
  377. * @SDE_FETCH_UBWC : fetch and decompress data
  378. */
  379. enum sde_fetch_type {
  380. SDE_FETCH_LINEAR,
  381. SDE_FETCH_TILE,
  382. SDE_FETCH_UBWC
  383. };
  384. /**
  385. * Value of enum chosen to fit the number of bits
  386. * expected by the HW programming.
  387. */
  388. enum {
  389. COLOR_ALPHA_1BIT = 0,
  390. COLOR_ALPHA_4BIT = 1,
  391. COLOR_4BIT = 0,
  392. COLOR_5BIT = 1, /* No 5-bit Alpha */
  393. COLOR_6BIT = 2, /* 6-Bit Alpha also = 2 */
  394. COLOR_8BIT = 3, /* 8-Bit Alpha also = 3 */
  395. COLOR_16BIT = 3,
  396. };
  397. /**
  398. * enum sde_3d_blend_mode
  399. * Desribes how the 3d data is blended
  400. * @BLEND_3D_NONE : 3d blending not enabled
  401. * @BLEND_3D_FRAME_INT : Frame interleaving
  402. * @BLEND_3D_H_ROW_INT : Horizontal row interleaving
  403. * @BLEND_3D_V_ROW_INT : vertical row interleaving
  404. * @BLEND_3D_COL_INT : column interleaving
  405. * @BLEND_3D_MAX :
  406. */
  407. enum sde_3d_blend_mode {
  408. BLEND_3D_NONE = 0,
  409. BLEND_3D_FRAME_INT,
  410. BLEND_3D_H_ROW_INT,
  411. BLEND_3D_V_ROW_INT,
  412. BLEND_3D_COL_INT,
  413. BLEND_3D_MAX
  414. };
  415. /**
  416. * enum sde_sys_cache_state: states of disp system cache
  417. * CACHE_STATE_DISABLED: sys cache has been disabled
  418. * CACHE_STATE_ENABLED: sys cache has been enabled
  419. * CACHE_STATE_NORMAL: sys cache is normal state
  420. * CACHE_STATE_PRE_CACHE: frame cache is being prepared
  421. * CACHE_STATE_FRAME_WRITE: sys cache is being written to
  422. * CACHE_STATE_FRAME_READ: sys cache is being read
  423. */
  424. enum sde_sys_cache_state {
  425. CACHE_STATE_DISABLED,
  426. CACHE_STATE_ENABLED,
  427. CACHE_STATE_NORMAL,
  428. CACHE_STATE_PRE_CACHE,
  429. CACHE_STATE_FRAME_WRITE,
  430. CACHE_STATE_FRAME_READ
  431. };
  432. /**
  433. * enum sde_wb_usage_type: Type of usage of the WB connector
  434. * WB_USAGE_WFD: WB connector used for WFD
  435. * WB_USAGE_CWB: WB connector used for concurrent writeback
  436. * WB_USAGE_OFFLINE_WB: WB connector used for 2-pass composition
  437. */
  438. enum sde_wb_usage_type {
  439. WB_USAGE_WFD,
  440. WB_USAGE_CWB,
  441. WB_USAGE_OFFLINE_WB,
  442. };
  443. /** struct sde_format - defines the format configuration which
  444. * allows SDE HW to correctly fetch and decode the format
  445. * @base: base msm_format struture containing fourcc code
  446. * @fetch_planes: how the color components are packed in pixel format
  447. * @element: element color ordering
  448. * @bits: element bit widths
  449. * @chroma_sample: chroma sub-samplng type
  450. * @unpack_align_msb: unpack aligned, 0 to LSB, 1 to MSB
  451. * @unpack_tight: 0 for loose, 1 for tight
  452. * @unpack_count: 0 = 1 component, 1 = 2 component
  453. * @bpp: bytes per pixel
  454. * @alpha_enable: whether the format has an alpha channel
  455. * @num_planes: number of planes (including meta data planes)
  456. * @fetch_mode: linear, tiled, or ubwc hw fetch behavior
  457. * @is_yuv: is format a yuv variant
  458. * @flag: usage bit flags
  459. * @tile_width: format tile width
  460. * @tile_height: format tile height
  461. */
  462. struct sde_format {
  463. struct msm_format base;
  464. enum sde_plane_type fetch_planes;
  465. u8 element[SDE_MAX_PLANES];
  466. u8 bits[SDE_MAX_PLANES];
  467. enum sde_chroma_samp_type chroma_sample;
  468. u8 unpack_align_msb;
  469. u8 unpack_tight;
  470. u8 unpack_count;
  471. u8 bpp;
  472. u8 alpha_enable;
  473. u8 num_planes;
  474. enum sde_fetch_type fetch_mode;
  475. DECLARE_BITMAP(flag, SDE_FORMAT_FLAG_BIT_MAX);
  476. u16 tile_width;
  477. u16 tile_height;
  478. };
  479. #define to_sde_format(x) container_of(x, struct sde_format, base)
  480. /**
  481. * struct sde_hw_fmt_layout - format information of the source pixel data
  482. * @format: pixel format parameters
  483. * @num_planes: number of planes (including meta data planes)
  484. * @width: image width
  485. * @height: image height
  486. * @total_size: total size in bytes
  487. * @plane_addr: address of each plane
  488. * @plane_size: length of each plane
  489. * @plane_pitch: pitch of each plane
  490. */
  491. struct sde_hw_fmt_layout {
  492. const struct sde_format *format;
  493. uint32_t num_planes;
  494. uint32_t width;
  495. uint32_t height;
  496. uint32_t total_size;
  497. uint32_t plane_addr[SDE_MAX_PLANES];
  498. uint32_t plane_size[SDE_MAX_PLANES];
  499. uint32_t plane_pitch[SDE_MAX_PLANES];
  500. };
  501. struct sde_rect {
  502. u16 x;
  503. u16 y;
  504. u16 w;
  505. u16 h;
  506. };
  507. struct sde_io_res {
  508. bool enabled;
  509. u32 src_w;
  510. u32 src_h;
  511. u32 dst_w;
  512. u32 dst_h;
  513. };
  514. struct sde_csc_cfg {
  515. /* matrix coefficients in S15.16 format */
  516. uint32_t csc_mv[SDE_CSC_MATRIX_COEFF_SIZE];
  517. uint32_t csc_pre_bv[SDE_CSC_BIAS_SIZE];
  518. uint32_t csc_post_bv[SDE_CSC_BIAS_SIZE];
  519. uint32_t csc_pre_lv[SDE_CSC_CLAMP_SIZE];
  520. uint32_t csc_post_lv[SDE_CSC_CLAMP_SIZE];
  521. };
  522. /**
  523. * struct sde_mdss_color - mdss color description
  524. * color 0 : green
  525. * color 1 : blue
  526. * color 2 : red
  527. * color 3 : alpha
  528. */
  529. struct sde_mdss_color {
  530. u32 color_0;
  531. u32 color_1;
  532. u32 color_2;
  533. u32 color_3;
  534. };
  535. /*
  536. * Define bit masks for h/w logging.
  537. */
  538. #define SDE_DBG_MASK_NONE (1 << 0)
  539. #define SDE_DBG_MASK_CDM (1 << 1)
  540. #define SDE_DBG_MASK_DSPP (1 << 2)
  541. #define SDE_DBG_MASK_INTF (1 << 3)
  542. #define SDE_DBG_MASK_LM (1 << 4)
  543. #define SDE_DBG_MASK_CTL (1 << 5)
  544. #define SDE_DBG_MASK_PINGPONG (1 << 6)
  545. #define SDE_DBG_MASK_SSPP (1 << 7)
  546. #define SDE_DBG_MASK_WB (1 << 8)
  547. #define SDE_DBG_MASK_TOP (1 << 9)
  548. #define SDE_DBG_MASK_VBIF (1 << 10)
  549. #define SDE_DBG_MASK_DSC (1 << 11)
  550. #define SDE_DBG_MASK_ROT (1 << 12)
  551. #define SDE_DBG_MASK_DS (1 << 13)
  552. #define SDE_DBG_MASK_REGDMA (1 << 14)
  553. #define SDE_DBG_MASK_UIDLE (1 << 15)
  554. #define SDE_DBG_MASK_SID (1 << 15)
  555. #define SDE_DBG_MASK_QDSS (1 << 16)
  556. #define SDE_DBG_MASK_VDC (1 << 17)
  557. #define SDE_DBG_MASK_DNSC_BLUR (1 << 18)
  558. /**
  559. * struct sde_hw_cp_cfg: hardware dspp/lm feature payload.
  560. * @payload: Feature specific payload.
  561. * @len: Length of the payload.
  562. * @ctl: control pointer associated with dspp/lm.
  563. * @last_feature: last feature that will be set.
  564. * @num_of_mixers: number of layer mixers for the display.
  565. * @mixer_info: mixer info pointer associated with lm.
  566. * @displayv: height of the display.
  567. * @displayh: width of the display.
  568. * @dspp[DSPP_MAX]: array of hw_dspp pointers associated with crtc.
  569. * @broadcast_disabled: flag indicating if broadcast should be avoided when
  570. * using LUTDMA
  571. * @panel_height: height of display panel in pixels.
  572. * @panel_width: width of display panel in pixels.
  573. * @valid_skip_blend_plane: true if skip plane params are valid
  574. * @skip_blend_plane: plane which has been skipped staging into layer mixer
  575. * @skip_blend_plane_w: skip plane width
  576. * @skip_blend_plane_h: skip plane height
  577. */
  578. struct sde_hw_cp_cfg {
  579. void *payload;
  580. u32 len;
  581. void *ctl;
  582. u32 last_feature;
  583. u32 num_of_mixers;
  584. void *mixer_info;
  585. u32 displayv;
  586. u32 displayh;
  587. struct sde_hw_dspp *dspp[DSPP_MAX];
  588. bool broadcast_disabled;
  589. u32 panel_height;
  590. u32 panel_width;
  591. bool valid_skip_blend_plane;
  592. enum sde_sspp skip_blend_plane;
  593. u32 skip_blend_plane_w;
  594. u32 skip_blend_plane_h;
  595. };
  596. /**
  597. * struct sde_hw_dim_layer: dim layer configs
  598. * @flags: Flag to represent INCLUSIVE/EXCLUSIVE
  599. * @stage: Blending stage of dim layer
  600. * @color_fill: Color fill to be used for the layer
  601. * @rect: Dim layer coordinates
  602. */
  603. struct sde_hw_dim_layer {
  604. uint32_t flags;
  605. uint32_t stage;
  606. struct sde_mdss_color color_fill;
  607. struct sde_rect rect;
  608. };
  609. /**
  610. * struct sde_splash_mem - Struct contains splah memory info
  611. * @splash_buf_size: Indicates the size of the memory region
  612. * @splash_buf_base: Address of specific splash memory region
  613. * @ramdump_size: Size of ramdump buffer region
  614. * @ramdump_base: Address of ramdump region reserved by bootloader
  615. * @ref_cnt: Tracks the map count to help in sharing splash memory
  616. */
  617. struct sde_splash_mem {
  618. u32 splash_buf_size;
  619. unsigned long splash_buf_base;
  620. u32 ramdump_size;
  621. unsigned long ramdump_base;
  622. u32 ref_cnt;
  623. };
  624. /**
  625. * struct sde_sspp_index_info - Struct informing which pipes are staged on
  626. * particular display
  627. * @pipes: bitmap, bit index is true if rect_0 of that pipe is staged,
  628. * else is false
  629. * @virt_pipes: bitmap, bit index is true if rect_1 of that pipe is staged,
  630. * else set to false
  631. * @bordercolor: True if border color is enabled
  632. */
  633. struct sde_sspp_index_info {
  634. DECLARE_BITMAP(pipes, SSPP_MAX);
  635. DECLARE_BITMAP(virt_pipes, SSPP_MAX);
  636. bool bordercolor;
  637. };
  638. /**
  639. * struct sde_splash_data - Struct contains details of resources and hw blocks
  640. * used in continuous splash on a specific display.
  641. * @cont_splash_enabled: Stores the cont_splash status (enabled/disabled)
  642. * @encoder: Pointer to the drm encoder object used for this display
  643. * @splash: Pointer to struct sde_splash_mem used for this display
  644. * @demura: Pointer to struct sde_splash_mem used for demura cont splash
  645. * @ctl_ids: Stores the valid MDSS ctl block ids for the current mode
  646. * @lm_ids: Stores the valid MDSS layer mixer block ids for the current mode
  647. * @dsc_ids: Stores the valid MDSS DSC block ids for the current mode
  648. * @vdc_ids: Stores the valid MDSS VDC block ids for the current mode
  649. * @pipes: Array of sspp info detected on this display
  650. * @ctl_cnt: Stores the active number of MDSS "top" blks of the current mode
  651. * @lm_cnt: Stores the active number of MDSS "LM" blks for the current mode
  652. * @dsc_cnt: Stores the active number of MDSS "dsc" blks for the current mode
  653. * @vdc_cnt: Stores the valid MDSS VDC block ids for the current mode
  654. */
  655. struct sde_splash_display {
  656. bool cont_splash_enabled;
  657. struct drm_encoder *encoder;
  658. struct sde_splash_mem *splash;
  659. struct sde_splash_mem *demura;
  660. u8 ctl_ids[MAX_DATA_PATH_PER_DSIPLAY];
  661. u8 lm_ids[MAX_DATA_PATH_PER_DSIPLAY];
  662. u8 dsc_ids[MAX_DATA_PATH_PER_DSIPLAY];
  663. u8 vdc_ids[MAX_DATA_PATH_PER_DSIPLAY];
  664. struct sde_sspp_index_info pipe_info;
  665. u8 ctl_cnt;
  666. u8 lm_cnt;
  667. u8 dsc_cnt;
  668. u8 vdc_cnt;
  669. };
  670. enum sde_handoff_type {
  671. SDE_SPLASH_HANDOFF,
  672. SDE_VM_HANDOFF,
  673. };
  674. /**
  675. * struct sde_splash_data - Struct contains details of continuous splash
  676. * for all the displays connected by probe time
  677. * @type: Indicates the type of handoff
  678. * @num_splash_regions: Indicates number of splash memory regions from dtsi
  679. * @num_splash_displays: Indicates count of active displays in continuous splash
  680. * @splash_mem: Array of all struct sde_splash_mem listed from dtsi
  681. * @demura_mem: Array of all demura memory regions listed from dtsi
  682. * @splash_display: Array of all struct sde_splash_display
  683. */
  684. struct sde_splash_data {
  685. enum sde_handoff_type type;
  686. u32 num_splash_regions;
  687. u32 num_splash_displays;
  688. struct sde_splash_mem splash_mem[MAX_DSI_DISPLAYS];
  689. struct sde_splash_mem demura_mem[MAX_DSI_DISPLAYS];
  690. struct sde_splash_display splash_display[MAX_DSI_DISPLAYS];
  691. };
  692. /**
  693. * struct sde_hw_tear_check - Struct contains parameters to configure
  694. * tear-effect module. This structure is used to configure tear-check
  695. * logic present either in ping-pong or in interface module.
  696. * @vsync_count: Ratio of MDP VSYNC clk freq(Hz) to refresh rate divided
  697. * by no of lines
  698. * @sync_cfg_height: Total vertical lines (display height - 1)
  699. * @vsync_init_val: Init value to which the read pointer gets loaded at
  700. * vsync edge
  701. * @sync_threshold_start: Read pointer threshold start ROI for write operation
  702. * @sync_threshold_continue: The minimum number of lines the write pointer
  703. * needs to be above the read pointer
  704. * @start_pos: The position from which the start_threshold value is added
  705. * @rd_ptr_irq: The read pointer line at which interrupt has to be generated
  706. * @wr_ptr_irq: The write pointer line at which interrupt has to be generated
  707. * @hw_vsync_mode: Sync with external frame sync input
  708. */
  709. struct sde_hw_tear_check {
  710. u32 vsync_count;
  711. u32 sync_cfg_height;
  712. u32 vsync_init_val;
  713. u32 sync_threshold_start;
  714. u32 sync_threshold_continue;
  715. u32 start_pos;
  716. u32 rd_ptr_irq;
  717. u32 wr_ptr_irq;
  718. u8 hw_vsync_mode;
  719. };
  720. /**
  721. * struct sde_hw_autorefresh - Struct contains parameters to configure
  722. * auto-refresh mode for command mode panels
  723. * @enable: Enalbe or disable the auto-refresh mode
  724. * @frame_count: Auto-refresh frame counter at which update occurs
  725. */
  726. struct sde_hw_autorefresh {
  727. bool enable;
  728. u32 frame_count;
  729. };
  730. /**
  731. * struct sde_hw_pp_vsync_info - Struct contains parameters to configure
  732. * read and write pointers for command mode panels
  733. * @pp_idx: Ping-pong block index
  734. * @intf_idx: Interface block index
  735. * @rd_ptr_init_val: Value of rd pointer at vsync edge
  736. * @rd_ptr_frame_count: num frames sent since enabling interface
  737. * @rd_ptr_line_count: current line on panel (rd ptr)
  738. * @wr_ptr_line_count: current line within pp fifo (wr ptr)
  739. * @intf_frame_count: num frames read from intf
  740. */
  741. struct sde_hw_pp_vsync_info {
  742. u32 pp_idx;
  743. u32 intf_idx;
  744. u32 rd_ptr_init_val;
  745. u32 rd_ptr_frame_count;
  746. u32 rd_ptr_line_count;
  747. u32 wr_ptr_line_count;
  748. u32 intf_frame_count;
  749. };
  750. /**
  751. * struct sde_hw_noise_layer_cfg: Payload to enable/disable noise blend
  752. * @flags: operation control flags, for future use
  753. * @noise_blend_stage: blend stage required for noise layer
  754. * @attn_blend_stage: blend stage required for attn layer
  755. * @attn_factor: factor in range of 1 to 255
  756. * @stength: strength in range of 0 to 6
  757. * @alpha_noise: factor in range of 1 to 255
  758. */
  759. struct sde_hw_noise_layer_cfg {
  760. u64 flags;
  761. u32 noise_blend_stage;
  762. u32 attn_blend_stage;
  763. u32 attn_factor;
  764. u32 strength;
  765. u32 alpha_noise;
  766. };
  767. #endif /* _SDE_HW_MDSS_H */