sde_hw_intf.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
  4. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  5. */
  6. #include <linux/iopoll.h>
  7. #include "sde_hwio.h"
  8. #include "sde_hw_catalog.h"
  9. #include "sde_hw_intf.h"
  10. #include "sde_dbg.h"
  11. #define INTF_TIMING_ENGINE_EN 0x000
  12. #define INTF_CONFIG 0x004
  13. #define INTF_HSYNC_CTL 0x008
  14. #define INTF_VSYNC_PERIOD_F0 0x00C
  15. #define INTF_VSYNC_PERIOD_F1 0x010
  16. #define INTF_VSYNC_PULSE_WIDTH_F0 0x014
  17. #define INTF_VSYNC_PULSE_WIDTH_F1 0x018
  18. #define INTF_DISPLAY_V_START_F0 0x01C
  19. #define INTF_DISPLAY_V_START_F1 0x020
  20. #define INTF_DISPLAY_V_END_F0 0x024
  21. #define INTF_DISPLAY_V_END_F1 0x028
  22. #define INTF_ACTIVE_V_START_F0 0x02C
  23. #define INTF_ACTIVE_V_START_F1 0x030
  24. #define INTF_ACTIVE_V_END_F0 0x034
  25. #define INTF_ACTIVE_V_END_F1 0x038
  26. #define INTF_DISPLAY_HCTL 0x03C
  27. #define INTF_ACTIVE_HCTL 0x040
  28. #define INTF_BORDER_COLOR 0x044
  29. #define INTF_UNDERFLOW_COLOR 0x048
  30. #define INTF_HSYNC_SKEW 0x04C
  31. #define INTF_POLARITY_CTL 0x050
  32. #define INTF_TEST_CTL 0x054
  33. #define INTF_TP_COLOR0 0x058
  34. #define INTF_TP_COLOR1 0x05C
  35. #define INTF_CONFIG2 0x060
  36. #define INTF_DISPLAY_DATA_HCTL 0x064
  37. #define INTF_ACTIVE_DATA_HCTL 0x068
  38. #define INTF_FRAME_LINE_COUNT_EN 0x0A8
  39. #define INTF_FRAME_COUNT 0x0AC
  40. #define INTF_LINE_COUNT 0x0B0
  41. #define INTF_DEFLICKER_CONFIG 0x0F0
  42. #define INTF_DEFLICKER_STRNG_COEFF 0x0F4
  43. #define INTF_DEFLICKER_WEAK_COEFF 0x0F8
  44. #define INTF_REG_SPLIT_LINK 0x080
  45. #define INTF_DSI_CMD_MODE_TRIGGER_EN 0x084
  46. #define INTF_PANEL_FORMAT 0x090
  47. #define INTF_TPG_ENABLE 0x100
  48. #define INTF_TPG_MAIN_CONTROL 0x104
  49. #define INTF_TPG_VIDEO_CONFIG 0x108
  50. #define INTF_TPG_COMPONENT_LIMITS 0x10C
  51. #define INTF_TPG_RECTANGLE 0x110
  52. #define INTF_TPG_INITIAL_VALUE 0x114
  53. #define INTF_TPG_BLK_WHITE_PATTERN_FRAMES 0x118
  54. #define INTF_TPG_RGB_MAPPING 0x11C
  55. #define INTF_PROG_FETCH_START 0x170
  56. #define INTF_PROG_ROT_START 0x174
  57. #define INTF_MISR_CTRL 0x180
  58. #define INTF_MISR_SIGNATURE 0x184
  59. #define INTF_VSYNC_TIMESTAMP_CTRL 0x210
  60. #define INTF_VSYNC_TIMESTAMP0 0x214
  61. #define INTF_VSYNC_TIMESTAMP1 0x218
  62. #define INTF_MDP_VSYNC_TIMESTAMP0 0x21C
  63. #define INTF_MDP_VSYNC_TIMESTAMP1 0x220
  64. #define INTF_WD_TIMER_0_CTL 0x230
  65. #define INTF_WD_TIMER_0_CTL2 0x234
  66. #define INTF_WD_TIMER_0_LOAD_VALUE 0x238
  67. #define INTF_MUX 0x25C
  68. #define INTF_UNDERRUN_COUNT 0x268
  69. #define INTF_STATUS 0x26C
  70. #define INTF_AVR_CONTROL 0x270
  71. #define INTF_AVR_MODE 0x274
  72. #define INTF_AVR_TRIGGER 0x278
  73. #define INTF_AVR_VTOTAL 0x27C
  74. #define INTF_TEAR_MDP_VSYNC_SEL 0x280
  75. #define INTF_TEAR_TEAR_CHECK_EN 0x284
  76. #define INTF_TEAR_SYNC_CONFIG_VSYNC 0x288
  77. #define INTF_TEAR_SYNC_CONFIG_HEIGHT 0x28C
  78. #define INTF_TEAR_SYNC_WRCOUNT 0x290
  79. #define INTF_TEAR_VSYNC_INIT_VAL 0x294
  80. #define INTF_TEAR_INT_COUNT_VAL 0x298
  81. #define INTF_TEAR_SYNC_THRESH 0x29C
  82. #define INTF_TEAR_START_POS 0x2A0
  83. #define INTF_TEAR_RD_PTR_IRQ 0x2A4
  84. #define INTF_TEAR_WR_PTR_IRQ 0x2A8
  85. #define INTF_TEAR_OUT_LINE_COUNT 0x2AC
  86. #define INTF_TEAR_LINE_COUNT 0x2B0
  87. #define INTF_TEAR_AUTOREFRESH_CONFIG 0x2B4
  88. #define INTF_TEAR_TEAR_DETECT_CTRL 0x2B8
  89. static struct sde_intf_cfg *_intf_offset(enum sde_intf intf,
  90. struct sde_mdss_cfg *m,
  91. void __iomem *addr,
  92. struct sde_hw_blk_reg_map *b)
  93. {
  94. int i;
  95. for (i = 0; i < m->intf_count; i++) {
  96. if ((intf == m->intf[i].id) &&
  97. (m->intf[i].type != INTF_NONE)) {
  98. b->base_off = addr;
  99. b->blk_off = m->intf[i].base;
  100. b->length = m->intf[i].len;
  101. b->hw_rev = m->hw_rev;
  102. b->log_mask = SDE_DBG_MASK_INTF;
  103. return &m->intf[i];
  104. }
  105. }
  106. return ERR_PTR(-EINVAL);
  107. }
  108. static void sde_hw_intf_avr_trigger(struct sde_hw_intf *ctx)
  109. {
  110. struct sde_hw_blk_reg_map *c;
  111. if (!ctx)
  112. return;
  113. c = &ctx->hw;
  114. SDE_REG_WRITE(c, INTF_AVR_TRIGGER, 0x1);
  115. SDE_DEBUG("AVR Triggered\n");
  116. }
  117. static int sde_hw_intf_avr_setup(struct sde_hw_intf *ctx,
  118. const struct intf_timing_params *params,
  119. const struct intf_avr_params *avr_params)
  120. {
  121. struct sde_hw_blk_reg_map *c;
  122. u32 hsync_period, vsync_period;
  123. u32 min_fps, default_fps, diff_fps;
  124. u32 vsync_period_slow;
  125. u32 avr_vtotal;
  126. u32 add_porches = 0;
  127. if (!ctx || !params || !avr_params) {
  128. SDE_ERROR("invalid input parameter(s)\n");
  129. return -EINVAL;
  130. }
  131. c = &ctx->hw;
  132. min_fps = avr_params->min_fps;
  133. default_fps = avr_params->default_fps;
  134. diff_fps = default_fps - min_fps;
  135. hsync_period = params->hsync_pulse_width +
  136. params->h_back_porch + params->width +
  137. params->h_front_porch;
  138. vsync_period = params->vsync_pulse_width +
  139. params->v_back_porch + params->height +
  140. params->v_front_porch;
  141. if (diff_fps)
  142. add_porches = mult_frac(vsync_period, diff_fps, min_fps);
  143. vsync_period_slow = vsync_period + add_porches;
  144. avr_vtotal = vsync_period_slow * hsync_period;
  145. SDE_REG_WRITE(c, INTF_AVR_VTOTAL, avr_vtotal);
  146. return 0;
  147. }
  148. static void sde_hw_intf_avr_ctrl(struct sde_hw_intf *ctx,
  149. const struct intf_avr_params *avr_params)
  150. {
  151. struct sde_hw_blk_reg_map *c;
  152. u32 avr_mode = 0;
  153. u32 avr_ctrl = 0;
  154. if (!ctx || !avr_params)
  155. return;
  156. c = &ctx->hw;
  157. if (avr_params->avr_mode) {
  158. avr_ctrl = BIT(0);
  159. avr_mode = (avr_params->avr_mode == SDE_RM_QSYNC_ONE_SHOT_MODE) ?
  160. (BIT(0) | BIT(8)) : 0x0;
  161. if (avr_params->avr_step_lines)
  162. avr_mode |= avr_params->avr_step_lines << 16;
  163. }
  164. SDE_REG_WRITE(c, INTF_AVR_CONTROL, avr_ctrl);
  165. SDE_REG_WRITE(c, INTF_AVR_MODE, avr_mode);
  166. }
  167. static u32 sde_hw_intf_get_avr_status(struct sde_hw_intf *ctx)
  168. {
  169. struct sde_hw_blk_reg_map *c;
  170. u32 avr_ctrl;
  171. if (!ctx)
  172. return false;
  173. c = &ctx->hw;
  174. avr_ctrl = SDE_REG_READ(c, INTF_AVR_CONTROL);
  175. return avr_ctrl >> 31;
  176. }
  177. static inline void _check_and_set_comp_bit(struct sde_hw_intf *ctx,
  178. bool dsc_4hs_merge, bool compression_en, u32 *intf_cfg2)
  179. {
  180. if (((SDE_HW_MAJOR(ctx->mdss->hw_rev) >= SDE_HW_MAJOR(SDE_HW_VER_700)) && compression_en)
  181. || (IS_SDE_MAJOR_SAME(ctx->mdss->hw_rev, SDE_HW_VER_600) && dsc_4hs_merge))
  182. (*intf_cfg2) |= BIT(12);
  183. else if (!compression_en)
  184. (*intf_cfg2) &= ~BIT(12);
  185. }
  186. static void sde_hw_intf_reset_counter(struct sde_hw_intf *ctx)
  187. {
  188. struct sde_hw_blk_reg_map *c = &ctx->hw;
  189. SDE_REG_WRITE(c, INTF_LINE_COUNT, BIT(31));
  190. }
  191. static u64 sde_hw_intf_get_vsync_timestamp(struct sde_hw_intf *ctx)
  192. {
  193. struct sde_hw_blk_reg_map *c = &ctx->hw;
  194. u32 timestamp_lo, timestamp_hi;
  195. u64 timestamp = 0;
  196. u32 reg_ts_0, reg_ts_1;
  197. if (ctx->cap->features & BIT(SDE_INTF_MDP_VSYNC_TS)) {
  198. reg_ts_0 = INTF_MDP_VSYNC_TIMESTAMP0;
  199. reg_ts_1 = INTF_MDP_VSYNC_TIMESTAMP1;
  200. } else {
  201. reg_ts_0 = INTF_VSYNC_TIMESTAMP0;
  202. reg_ts_1 = INTF_VSYNC_TIMESTAMP1;
  203. }
  204. timestamp_hi = SDE_REG_READ(c, reg_ts_1);
  205. timestamp_lo = SDE_REG_READ(c, reg_ts_0);
  206. timestamp = timestamp_hi;
  207. timestamp = (timestamp << 32) | timestamp_lo;
  208. return timestamp;
  209. }
  210. static void sde_hw_intf_setup_timing_engine(struct sde_hw_intf *ctx,
  211. const struct intf_timing_params *p,
  212. const struct sde_format *fmt)
  213. {
  214. struct sde_hw_blk_reg_map *c = &ctx->hw;
  215. u32 hsync_period, vsync_period;
  216. u32 display_v_start, display_v_end;
  217. u32 hsync_start_x, hsync_end_x;
  218. u32 hsync_data_start_x, hsync_data_end_x;
  219. u32 active_h_start, active_h_end;
  220. u32 active_v_start, active_v_end;
  221. u32 active_hctl, display_hctl, hsync_ctl;
  222. u32 polarity_ctl, den_polarity, hsync_polarity, vsync_polarity;
  223. u32 panel_format;
  224. u32 intf_cfg, intf_cfg2 = 0;
  225. u32 display_data_hctl = 0, active_data_hctl = 0;
  226. u32 data_width;
  227. bool dp_intf = false;
  228. /* read interface_cfg */
  229. intf_cfg = SDE_REG_READ(c, INTF_CONFIG);
  230. if (ctx->cap->type == INTF_EDP || ctx->cap->type == INTF_DP)
  231. dp_intf = true;
  232. hsync_period = p->hsync_pulse_width + p->h_back_porch + p->width +
  233. p->h_front_porch;
  234. vsync_period = p->vsync_pulse_width + p->v_back_porch + p->height +
  235. p->v_front_porch;
  236. display_v_start = ((p->vsync_pulse_width + p->v_back_porch) *
  237. hsync_period) + p->hsync_skew;
  238. display_v_end = ((vsync_period - p->v_front_porch) * hsync_period) +
  239. p->hsync_skew - 1;
  240. hsync_ctl = (hsync_period << 16) | p->hsync_pulse_width;
  241. hsync_start_x = p->h_back_porch + p->hsync_pulse_width;
  242. hsync_end_x = hsync_period - p->h_front_porch - 1;
  243. /*
  244. * DATA_HCTL_EN controls data timing which can be different from
  245. * video timing. It is recommended to enable it for all cases, except
  246. * if compression is enabled in 1 pixel per clock mode
  247. */
  248. if (!p->compression_en || p->wide_bus_en)
  249. intf_cfg2 |= BIT(4);
  250. if (p->wide_bus_en)
  251. intf_cfg2 |= BIT(0);
  252. /*
  253. * If widebus is disabled:
  254. * For uncompressed stream, the data is valid for the entire active
  255. * window period.
  256. * For compressed stream, data is valid for a shorter time period
  257. * inside the active window depending on the compression ratio.
  258. *
  259. * If widebus is enabled:
  260. * For uncompressed stream, data is valid for only half the active
  261. * window, since the data rate is doubled in this mode.
  262. * p->width holds the adjusted width for DP but unadjusted width for DSI
  263. * For compressed stream, data validity window needs to be adjusted for
  264. * compression ratio and then further halved.
  265. */
  266. data_width = p->width;
  267. if (p->compression_en) {
  268. data_width = DIV_ROUND_UP(p->dce_bytes_per_line, 3);
  269. if (p->wide_bus_en)
  270. data_width >>= 1;
  271. } else if (!dp_intf && p->wide_bus_en) {
  272. data_width = p->width >> 1;
  273. } else {
  274. data_width = p->width;
  275. }
  276. hsync_data_start_x = hsync_start_x;
  277. hsync_data_end_x = hsync_start_x + data_width - 1;
  278. display_hctl = (hsync_end_x << 16) | hsync_start_x;
  279. display_data_hctl = (hsync_data_end_x << 16) | hsync_data_start_x;
  280. if (dp_intf) {
  281. // DP timing adjustment
  282. display_v_start += p->hsync_pulse_width + p->h_back_porch;
  283. display_v_end -= p->h_front_porch;
  284. }
  285. intf_cfg |= BIT(29); /* ACTIVE_H_ENABLE */
  286. intf_cfg |= BIT(30); /* ACTIVE_V_ENABLE */
  287. active_h_start = hsync_start_x;
  288. active_h_end = active_h_start + p->xres - 1;
  289. active_v_start = display_v_start;
  290. active_v_end = active_v_start + (p->yres * hsync_period) - 1;
  291. active_hctl = (active_h_end << 16) | active_h_start;
  292. if (dp_intf) {
  293. display_hctl = active_hctl;
  294. if (p->compression_en) {
  295. active_data_hctl = (hsync_start_x +
  296. p->extra_dto_cycles) << 16;
  297. active_data_hctl += hsync_start_x;
  298. display_data_hctl = active_data_hctl;
  299. }
  300. }
  301. _check_and_set_comp_bit(ctx, p->dsc_4hs_merge, p->compression_en,
  302. &intf_cfg2);
  303. den_polarity = 0;
  304. if (ctx->cap->type == INTF_HDMI) {
  305. hsync_polarity = p->yres >= 720 ? 0 : 1;
  306. vsync_polarity = p->yres >= 720 ? 0 : 1;
  307. } else if (ctx->cap->type == INTF_DP) {
  308. hsync_polarity = p->hsync_polarity;
  309. vsync_polarity = p->vsync_polarity;
  310. } else {
  311. hsync_polarity = 0;
  312. vsync_polarity = 0;
  313. }
  314. polarity_ctl = (den_polarity << 2) | /* DEN Polarity */
  315. (vsync_polarity << 1) | /* VSYNC Polarity */
  316. (hsync_polarity << 0); /* HSYNC Polarity */
  317. if (!SDE_FORMAT_IS_YUV(fmt))
  318. panel_format = (fmt->bits[C0_G_Y] |
  319. (fmt->bits[C1_B_Cb] << 2) |
  320. (fmt->bits[C2_R_Cr] << 4) |
  321. (0x21 << 8));
  322. else
  323. /* Interface treats all the pixel data in RGB888 format */
  324. panel_format = (COLOR_8BIT |
  325. (COLOR_8BIT << 2) |
  326. (COLOR_8BIT << 4) |
  327. (0x21 << 8));
  328. if (p->wide_bus_en)
  329. intf_cfg2 |= BIT(0);
  330. /* Synchronize timing engine enable to TE */
  331. if ((ctx->cap->features & BIT(SDE_INTF_TE_ALIGN_VSYNC))
  332. && p->poms_align_vsync)
  333. intf_cfg2 |= BIT(16);
  334. if (ctx->cfg.split_link_en)
  335. SDE_REG_WRITE(c, INTF_REG_SPLIT_LINK, 0x3);
  336. SDE_REG_WRITE(c, INTF_HSYNC_CTL, hsync_ctl);
  337. SDE_REG_WRITE(c, INTF_VSYNC_PERIOD_F0, vsync_period * hsync_period);
  338. SDE_REG_WRITE(c, INTF_VSYNC_PULSE_WIDTH_F0,
  339. p->vsync_pulse_width * hsync_period);
  340. SDE_REG_WRITE(c, INTF_DISPLAY_HCTL, display_hctl);
  341. SDE_REG_WRITE(c, INTF_DISPLAY_V_START_F0, display_v_start);
  342. SDE_REG_WRITE(c, INTF_DISPLAY_V_END_F0, display_v_end);
  343. SDE_REG_WRITE(c, INTF_ACTIVE_HCTL, active_hctl);
  344. SDE_REG_WRITE(c, INTF_ACTIVE_V_START_F0, active_v_start);
  345. SDE_REG_WRITE(c, INTF_ACTIVE_V_END_F0, active_v_end);
  346. SDE_REG_WRITE(c, INTF_BORDER_COLOR, p->border_clr);
  347. SDE_REG_WRITE(c, INTF_UNDERFLOW_COLOR, p->underflow_clr);
  348. SDE_REG_WRITE(c, INTF_HSYNC_SKEW, p->hsync_skew);
  349. SDE_REG_WRITE(c, INTF_POLARITY_CTL, polarity_ctl);
  350. SDE_REG_WRITE(c, INTF_FRAME_LINE_COUNT_EN, 0x3);
  351. SDE_REG_WRITE(c, INTF_CONFIG, intf_cfg);
  352. SDE_REG_WRITE(c, INTF_PANEL_FORMAT, panel_format);
  353. SDE_REG_WRITE(c, INTF_CONFIG2, intf_cfg2);
  354. SDE_REG_WRITE(c, INTF_DISPLAY_DATA_HCTL, display_data_hctl);
  355. SDE_REG_WRITE(c, INTF_ACTIVE_DATA_HCTL, active_data_hctl);
  356. }
  357. static void sde_hw_intf_enable_timing_engine(
  358. struct sde_hw_intf *intf,
  359. u8 enable)
  360. {
  361. struct sde_hw_blk_reg_map *c = &intf->hw;
  362. /* Note: Display interface select is handled in top block hw layer */
  363. SDE_REG_WRITE(c, INTF_TIMING_ENGINE_EN, enable != 0);
  364. if (enable && (intf->cap->features & (BIT(SDE_INTF_PANEL_VSYNC_TS) | BIT(SDE_INTF_MDP_VSYNC_TS))))
  365. SDE_REG_WRITE(c, INTF_VSYNC_TIMESTAMP_CTRL, BIT(0));
  366. }
  367. static void sde_hw_intf_setup_prg_fetch(
  368. struct sde_hw_intf *intf,
  369. const struct intf_prog_fetch *fetch)
  370. {
  371. struct sde_hw_blk_reg_map *c = &intf->hw;
  372. int fetch_enable;
  373. /*
  374. * Fetch should always be outside the active lines. If the fetching
  375. * is programmed within active region, hardware behavior is unknown.
  376. */
  377. fetch_enable = SDE_REG_READ(c, INTF_CONFIG);
  378. if (fetch->enable) {
  379. fetch_enable |= BIT(31);
  380. SDE_REG_WRITE(c, INTF_PROG_FETCH_START,
  381. fetch->fetch_start);
  382. } else {
  383. fetch_enable &= ~BIT(31);
  384. }
  385. SDE_REG_WRITE(c, INTF_CONFIG, fetch_enable);
  386. }
  387. static void sde_hw_intf_setup_vsync_source(struct sde_hw_intf *intf,
  388. u32 frame_rate)
  389. {
  390. struct sde_hw_blk_reg_map *c;
  391. u32 reg;
  392. if (!intf)
  393. return;
  394. c = &intf->hw;
  395. SDE_REG_WRITE(c, INTF_WD_TIMER_0_LOAD_VALUE, CALCULATE_WD_LOAD_VALUE(frame_rate));
  396. SDE_REG_WRITE(c, INTF_WD_TIMER_0_CTL, BIT(0)); /* clear timer */
  397. reg = SDE_REG_READ(c, INTF_WD_TIMER_0_CTL2);
  398. reg |= BIT(8); /* enable heartbeat timer */
  399. reg |= BIT(0); /* enable WD timer */
  400. SDE_REG_WRITE(c, INTF_WD_TIMER_0_CTL2, reg);
  401. /* make sure that timers are enabled/disabled for vsync state */
  402. wmb();
  403. }
  404. static void sde_hw_intf_bind_pingpong_blk(
  405. struct sde_hw_intf *intf,
  406. bool enable,
  407. const enum sde_pingpong pp)
  408. {
  409. struct sde_hw_blk_reg_map *c;
  410. u32 mux_cfg;
  411. if (!intf)
  412. return;
  413. c = &intf->hw;
  414. if (enable) {
  415. mux_cfg = SDE_REG_READ(c, INTF_MUX);
  416. mux_cfg &= ~0x0f;
  417. mux_cfg |= (pp - PINGPONG_0) & 0x7;
  418. /* Splitlink case, pp0->sublink0, pp1->sublink1 */
  419. if (intf->cfg.split_link_en)
  420. mux_cfg = 0x10000;
  421. } else {
  422. mux_cfg = 0xf000f;
  423. }
  424. SDE_REG_WRITE(c, INTF_MUX, mux_cfg);
  425. }
  426. static void sde_hw_intf_get_status(
  427. struct sde_hw_intf *intf,
  428. struct intf_status *s)
  429. {
  430. struct sde_hw_blk_reg_map *c = &intf->hw;
  431. s->is_en = SDE_REG_READ(c, INTF_TIMING_ENGINE_EN);
  432. if (s->is_en) {
  433. s->frame_count = SDE_REG_READ(c, INTF_FRAME_COUNT);
  434. s->line_count = SDE_REG_READ(c, INTF_LINE_COUNT) & 0xffff;
  435. } else {
  436. s->line_count = 0;
  437. s->frame_count = 0;
  438. }
  439. }
  440. static void sde_hw_intf_v1_get_status(
  441. struct sde_hw_intf *intf,
  442. struct intf_status *s)
  443. {
  444. struct sde_hw_blk_reg_map *c = &intf->hw;
  445. s->is_en = SDE_REG_READ(c, INTF_STATUS) & BIT(0);
  446. s->is_prog_fetch_en = (SDE_REG_READ(c, INTF_CONFIG) & BIT(31));
  447. if (s->is_en) {
  448. s->frame_count = SDE_REG_READ(c, INTF_FRAME_COUNT);
  449. s->line_count = SDE_REG_READ(c, INTF_LINE_COUNT) & 0xffff;
  450. } else {
  451. s->line_count = 0;
  452. s->frame_count = 0;
  453. }
  454. }
  455. static void sde_hw_intf_setup_misr(struct sde_hw_intf *intf,
  456. bool enable, u32 frame_count)
  457. {
  458. struct sde_hw_blk_reg_map *c = &intf->hw;
  459. u32 config = 0;
  460. SDE_REG_WRITE(c, INTF_MISR_CTRL, MISR_CTRL_STATUS_CLEAR);
  461. /* clear misr data */
  462. wmb();
  463. if (enable)
  464. config = (frame_count & MISR_FRAME_COUNT_MASK) |
  465. MISR_CTRL_ENABLE |
  466. INTF_MISR_CTRL_FREE_RUN_MASK |
  467. INTF_MISR_CTRL_INPUT_SEL_DATA;
  468. SDE_REG_WRITE(c, INTF_MISR_CTRL, config);
  469. }
  470. static int sde_hw_intf_collect_misr(struct sde_hw_intf *intf, bool nonblock,
  471. u32 *misr_value)
  472. {
  473. struct sde_hw_blk_reg_map *c = &intf->hw;
  474. u32 ctrl = 0;
  475. if (!misr_value)
  476. return -EINVAL;
  477. ctrl = SDE_REG_READ(c, INTF_MISR_CTRL);
  478. if (!nonblock) {
  479. if (ctrl & MISR_CTRL_ENABLE) {
  480. int rc;
  481. rc = readl_poll_timeout(c->base_off + c->blk_off +
  482. INTF_MISR_CTRL, ctrl,
  483. (ctrl & MISR_CTRL_STATUS) > 0, 500,
  484. 84000);
  485. if (rc)
  486. return rc;
  487. } else {
  488. return -EINVAL;
  489. }
  490. }
  491. *misr_value = SDE_REG_READ(c, INTF_MISR_SIGNATURE);
  492. return 0;
  493. }
  494. static u32 sde_hw_intf_get_line_count(struct sde_hw_intf *intf)
  495. {
  496. struct sde_hw_blk_reg_map *c;
  497. if (!intf)
  498. return 0;
  499. c = &intf->hw;
  500. return SDE_REG_READ(c, INTF_LINE_COUNT) & 0xffff;
  501. }
  502. static u32 sde_hw_intf_get_underrun_line_count(struct sde_hw_intf *intf)
  503. {
  504. struct sde_hw_blk_reg_map *c;
  505. u32 hsync_period;
  506. if (!intf)
  507. return 0;
  508. c = &intf->hw;
  509. hsync_period = SDE_REG_READ(c, INTF_HSYNC_CTL);
  510. hsync_period = ((hsync_period & 0xffff0000) >> 16);
  511. return hsync_period ?
  512. SDE_REG_READ(c, INTF_UNDERRUN_COUNT) / hsync_period :
  513. 0xebadebad;
  514. }
  515. static u32 sde_hw_intf_get_intr_status(struct sde_hw_intf *intf)
  516. {
  517. if (!intf)
  518. return -EINVAL;
  519. return SDE_REG_READ(&intf->hw, INTF_INTR_STATUS);
  520. }
  521. static int sde_hw_intf_setup_te_config(struct sde_hw_intf *intf,
  522. struct sde_hw_tear_check *te)
  523. {
  524. struct sde_hw_blk_reg_map *c;
  525. u32 cfg = 0;
  526. if (!intf)
  527. return -EINVAL;
  528. c = &intf->hw;
  529. if (te->hw_vsync_mode)
  530. cfg |= BIT(20);
  531. cfg |= te->vsync_count;
  532. SDE_REG_WRITE(c, INTF_TEAR_SYNC_CONFIG_VSYNC, cfg);
  533. wmb(); /* disable vsync counter before updating single buffer registers */
  534. SDE_REG_WRITE(c, INTF_TEAR_SYNC_CONFIG_HEIGHT, te->sync_cfg_height);
  535. SDE_REG_WRITE(c, INTF_TEAR_VSYNC_INIT_VAL, te->vsync_init_val);
  536. SDE_REG_WRITE(c, INTF_TEAR_RD_PTR_IRQ, te->rd_ptr_irq);
  537. SDE_REG_WRITE(c, INTF_TEAR_WR_PTR_IRQ, te->wr_ptr_irq);
  538. SDE_REG_WRITE(c, INTF_TEAR_START_POS, te->start_pos);
  539. SDE_REG_WRITE(c, INTF_TEAR_SYNC_THRESH,
  540. ((te->sync_threshold_continue << 16) |
  541. te->sync_threshold_start));
  542. SDE_REG_WRITE(c, INTF_TEAR_SYNC_WRCOUNT,
  543. (te->start_pos + te->sync_threshold_start + 1));
  544. cfg |= BIT(19); /* VSYNC_COUNTER_EN */
  545. SDE_REG_WRITE(c, INTF_TEAR_SYNC_CONFIG_VSYNC, cfg);
  546. return 0;
  547. }
  548. static int sde_hw_intf_setup_autorefresh_config(struct sde_hw_intf *intf,
  549. struct sde_hw_autorefresh *cfg)
  550. {
  551. struct sde_hw_blk_reg_map *c;
  552. u32 refresh_cfg;
  553. if (!intf || !cfg)
  554. return -EINVAL;
  555. c = &intf->hw;
  556. refresh_cfg = SDE_REG_READ(c, INTF_TEAR_AUTOREFRESH_CONFIG);
  557. if (cfg->enable)
  558. refresh_cfg = BIT(31) | cfg->frame_count;
  559. else
  560. refresh_cfg &= ~BIT(31);
  561. SDE_REG_WRITE(c, INTF_TEAR_AUTOREFRESH_CONFIG, refresh_cfg);
  562. return 0;
  563. }
  564. static int sde_hw_intf_get_autorefresh_config(struct sde_hw_intf *intf,
  565. struct sde_hw_autorefresh *cfg)
  566. {
  567. struct sde_hw_blk_reg_map *c;
  568. u32 val;
  569. if (!intf || !cfg)
  570. return -EINVAL;
  571. c = &intf->hw;
  572. val = SDE_REG_READ(c, INTF_TEAR_AUTOREFRESH_CONFIG);
  573. cfg->enable = (val & BIT(31)) >> 31;
  574. cfg->frame_count = val & 0xffff;
  575. return 0;
  576. }
  577. static int sde_hw_intf_poll_timeout_wr_ptr(struct sde_hw_intf *intf,
  578. u32 timeout_us)
  579. {
  580. struct sde_hw_blk_reg_map *c;
  581. u32 val;
  582. int rc;
  583. if (!intf)
  584. return -EINVAL;
  585. c = &intf->hw;
  586. rc = readl_poll_timeout(c->base_off + c->blk_off + INTF_TEAR_LINE_COUNT,
  587. val, (val & 0xffff) >= 1, 10, timeout_us);
  588. return rc;
  589. }
  590. static int sde_hw_intf_enable_te(struct sde_hw_intf *intf, bool enable)
  591. {
  592. struct sde_hw_blk_reg_map *c;
  593. if (!intf)
  594. return -EINVAL;
  595. c = &intf->hw;
  596. SDE_REG_WRITE(c, INTF_TEAR_TEAR_CHECK_EN, enable);
  597. if (enable && (intf->cap->features & (BIT(SDE_INTF_PANEL_VSYNC_TS) | BIT(SDE_INTF_MDP_VSYNC_TS))))
  598. SDE_REG_WRITE(c, INTF_VSYNC_TIMESTAMP_CTRL, BIT(0));
  599. return 0;
  600. }
  601. static void sde_hw_intf_update_te(struct sde_hw_intf *intf,
  602. struct sde_hw_tear_check *te)
  603. {
  604. struct sde_hw_blk_reg_map *c;
  605. int cfg;
  606. if (!intf || !te)
  607. return;
  608. c = &intf->hw;
  609. cfg = SDE_REG_READ(c, INTF_TEAR_SYNC_THRESH);
  610. cfg &= ~0xFFFF;
  611. cfg |= te->sync_threshold_start;
  612. SDE_REG_WRITE(c, INTF_TEAR_SYNC_THRESH, cfg);
  613. }
  614. static int sde_hw_intf_connect_external_te(struct sde_hw_intf *intf,
  615. bool enable_external_te)
  616. {
  617. struct sde_hw_blk_reg_map *c = &intf->hw;
  618. u32 cfg;
  619. int orig;
  620. if (!intf)
  621. return -EINVAL;
  622. c = &intf->hw;
  623. cfg = SDE_REG_READ(c, INTF_TEAR_SYNC_CONFIG_VSYNC);
  624. orig = (bool)(cfg & BIT(20));
  625. if (enable_external_te)
  626. cfg |= BIT(20);
  627. else
  628. cfg &= ~BIT(20);
  629. SDE_REG_WRITE(c, INTF_TEAR_SYNC_CONFIG_VSYNC, cfg);
  630. return orig;
  631. }
  632. static int sde_hw_intf_get_vsync_info(struct sde_hw_intf *intf,
  633. struct sde_hw_pp_vsync_info *info)
  634. {
  635. struct sde_hw_blk_reg_map *c = &intf->hw;
  636. u32 val;
  637. if (!intf || !info)
  638. return -EINVAL;
  639. c = &intf->hw;
  640. val = SDE_REG_READ(c, INTF_TEAR_VSYNC_INIT_VAL);
  641. info->rd_ptr_init_val = val & 0xffff;
  642. val = SDE_REG_READ(c, INTF_TEAR_INT_COUNT_VAL);
  643. info->rd_ptr_frame_count = (val & 0xffff0000) >> 16;
  644. info->rd_ptr_line_count = val & 0xffff;
  645. val = SDE_REG_READ(c, INTF_TEAR_LINE_COUNT);
  646. info->wr_ptr_line_count = val & 0xffff;
  647. val = SDE_REG_READ(c, INTF_FRAME_COUNT);
  648. info->intf_frame_count = val;
  649. return 0;
  650. }
  651. static int sde_hw_intf_v1_check_and_reset_tearcheck(struct sde_hw_intf *intf,
  652. struct intf_tear_status *status)
  653. {
  654. struct sde_hw_blk_reg_map *c = &intf->hw;
  655. u32 start_pos;
  656. if (!intf || !status)
  657. return -EINVAL;
  658. c = &intf->hw;
  659. status->read_count = SDE_REG_READ(c, INTF_TEAR_INT_COUNT_VAL);
  660. start_pos = SDE_REG_READ(c, INTF_TEAR_START_POS);
  661. status->write_count = SDE_REG_READ(c, INTF_TEAR_SYNC_WRCOUNT);
  662. status->write_count &= 0xffff0000;
  663. status->write_count |= start_pos;
  664. SDE_REG_WRITE(c, INTF_TEAR_SYNC_WRCOUNT, status->write_count);
  665. return 0;
  666. }
  667. static void sde_hw_intf_vsync_sel(struct sde_hw_intf *intf,
  668. u32 vsync_source)
  669. {
  670. struct sde_hw_blk_reg_map *c;
  671. if (!intf)
  672. return;
  673. c = &intf->hw;
  674. SDE_REG_WRITE(c, INTF_TEAR_MDP_VSYNC_SEL, (vsync_source & 0xf));
  675. }
  676. static void sde_hw_intf_enable_compressed_input(struct sde_hw_intf *intf,
  677. bool compression_en, bool dsc_4hs_merge)
  678. {
  679. struct sde_hw_blk_reg_map *c;
  680. u32 intf_cfg2;
  681. if (!intf)
  682. return;
  683. /*
  684. * callers can either call this function to enable/disable the 64 bit
  685. * compressed input or this configuration can be applied along
  686. * with timing generation parameters
  687. */
  688. c = &intf->hw;
  689. intf_cfg2 = SDE_REG_READ(c, INTF_CONFIG2);
  690. _check_and_set_comp_bit(intf, dsc_4hs_merge, compression_en,
  691. &intf_cfg2);
  692. SDE_REG_WRITE(c, INTF_CONFIG2, intf_cfg2);
  693. }
  694. static void sde_hw_intf_enable_wide_bus(struct sde_hw_intf *intf,
  695. bool enable)
  696. {
  697. struct sde_hw_blk_reg_map *c;
  698. u32 intf_cfg2;
  699. if (!intf)
  700. return;
  701. c = &intf->hw;
  702. intf_cfg2 = SDE_REG_READ(c, INTF_CONFIG2);
  703. intf_cfg2 &= ~BIT(0);
  704. intf_cfg2 |= enable ? BIT(0) : 0;
  705. SDE_REG_WRITE(c, INTF_CONFIG2, intf_cfg2);
  706. }
  707. static void _setup_intf_ops(struct sde_hw_intf_ops *ops,
  708. unsigned long cap)
  709. {
  710. ops->setup_timing_gen = sde_hw_intf_setup_timing_engine;
  711. ops->setup_prg_fetch = sde_hw_intf_setup_prg_fetch;
  712. ops->enable_timing = sde_hw_intf_enable_timing_engine;
  713. ops->setup_misr = sde_hw_intf_setup_misr;
  714. ops->collect_misr = sde_hw_intf_collect_misr;
  715. ops->get_line_count = sde_hw_intf_get_line_count;
  716. ops->get_underrun_line_count = sde_hw_intf_get_underrun_line_count;
  717. ops->get_intr_status = sde_hw_intf_get_intr_status;
  718. ops->avr_setup = sde_hw_intf_avr_setup;
  719. ops->avr_trigger = sde_hw_intf_avr_trigger;
  720. ops->avr_ctrl = sde_hw_intf_avr_ctrl;
  721. ops->enable_compressed_input = sde_hw_intf_enable_compressed_input;
  722. ops->enable_wide_bus = sde_hw_intf_enable_wide_bus;
  723. if (cap & BIT(SDE_INTF_STATUS))
  724. ops->get_status = sde_hw_intf_v1_get_status;
  725. else
  726. ops->get_status = sde_hw_intf_get_status;
  727. if (cap & BIT(SDE_INTF_INPUT_CTRL))
  728. ops->bind_pingpong_blk = sde_hw_intf_bind_pingpong_blk;
  729. if (cap & BIT(SDE_INTF_WD_TIMER))
  730. ops->setup_vsync_source = sde_hw_intf_setup_vsync_source;
  731. if (cap & BIT(SDE_INTF_AVR_STATUS))
  732. ops->get_avr_status = sde_hw_intf_get_avr_status;
  733. if (cap & BIT(SDE_INTF_TE)) {
  734. ops->setup_tearcheck = sde_hw_intf_setup_te_config;
  735. ops->enable_tearcheck = sde_hw_intf_enable_te;
  736. ops->update_tearcheck = sde_hw_intf_update_te;
  737. ops->connect_external_te = sde_hw_intf_connect_external_te;
  738. ops->get_vsync_info = sde_hw_intf_get_vsync_info;
  739. ops->setup_autorefresh = sde_hw_intf_setup_autorefresh_config;
  740. ops->get_autorefresh = sde_hw_intf_get_autorefresh_config;
  741. ops->poll_timeout_wr_ptr = sde_hw_intf_poll_timeout_wr_ptr;
  742. ops->vsync_sel = sde_hw_intf_vsync_sel;
  743. ops->check_and_reset_tearcheck =
  744. sde_hw_intf_v1_check_and_reset_tearcheck;
  745. }
  746. if (cap & BIT(SDE_INTF_RESET_COUNTER))
  747. ops->reset_counter = sde_hw_intf_reset_counter;
  748. if (cap & (BIT(SDE_INTF_PANEL_VSYNC_TS) | BIT(SDE_INTF_MDP_VSYNC_TS)))
  749. ops->get_vsync_timestamp = sde_hw_intf_get_vsync_timestamp;
  750. }
  751. struct sde_hw_blk_reg_map *sde_hw_intf_init(enum sde_intf idx,
  752. void __iomem *addr,
  753. struct sde_mdss_cfg *m)
  754. {
  755. struct sde_hw_intf *c;
  756. struct sde_intf_cfg *cfg;
  757. c = kzalloc(sizeof(*c), GFP_KERNEL);
  758. if (!c)
  759. return ERR_PTR(-ENOMEM);
  760. cfg = _intf_offset(idx, m, addr, &c->hw);
  761. if (IS_ERR_OR_NULL(cfg)) {
  762. kfree(c);
  763. pr_err("failed to create sde_hw_intf %d\n", idx);
  764. return ERR_PTR(-EINVAL);
  765. }
  766. /*
  767. * Assign ops
  768. */
  769. c->idx = idx;
  770. c->cap = cfg;
  771. c->mdss = m;
  772. _setup_intf_ops(&c->ops, c->cap->features);
  773. sde_dbg_reg_register_dump_range(SDE_DBG_NAME, cfg->name, c->hw.blk_off,
  774. c->hw.blk_off + c->hw.length, c->hw.xin_id);
  775. return &c->hw;
  776. }
  777. void sde_hw_intf_destroy(struct sde_hw_blk_reg_map *hw)
  778. {
  779. if (hw)
  780. kfree(to_sde_hw_intf(hw));
  781. }