sde_hw_dnsc_blur.c 8.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2021, The Linux Foundation. All rights reserved.
  4. */
  5. #include "sde_hw_mdss.h"
  6. #include "sde_hwio.h"
  7. #include "sde_hw_catalog.h"
  8. #include "sde_hw_dnsc_blur.h"
  9. #include "sde_dbg.h"
  10. #include "sde_kms.h"
  11. #define DNSC_BLUR_OP_MODE 0x0
  12. #define DNSC_BLUR_BLUR_RATIO_H 0x4
  13. #define DNSC_BLUR_BLUR_RATIO_V 0x8
  14. #define DNSC_BLUR_PCMN_PHASE_INIT_H 0xC
  15. #define DNSC_BLUR_PCMN_PHASE_STEP_H 0x10
  16. #define DNSC_BLUR_PCMN_PHASE_INIT_V 0x14
  17. #define DNSC_BLUR_PCMN_PHASE_STEP_V 0x18
  18. #define DNSC_BLUR_OUT_IMG_SIZE 0x1C
  19. #define DNSC_BLUR_GAUS_COEF_LUT_SEL 0x20
  20. #define DNSC_BLUR_MUX 0x24
  21. #define DNSC_BLUR_SRC_IMG_SIZE 0x28
  22. #define DNSC_BLUR_GAUS_COEF_LUT_H0 0x0
  23. #define DNSC_BLUR_GAUS_COEF_LUT_V0 0x100
  24. #define DNSC_BLUR_GAUS_COEF_LUT_H1 0x200
  25. #define DNSC_BLUR_GAUS_COEF_LUT_V1 0x300
  26. #define DNSC_BLUR_DITHER_OP_MODE 0x0
  27. #define DNSC_BLUR_DITHER_BITDEPTH 0x4
  28. #define DNSC_BLUR_DITHER_MATRIX_ROW0 0x8
  29. /* DNSC_BLUR_OP_MODE bits */
  30. #define DNSC_BLUR_OPMODE_ENABLE BIT(0)
  31. #define DNSC_BLUR_OPMODE_DWNS_H_EN BIT(1)
  32. #define DNSC_BLUR_OPMODE_DWNS_V_EN BIT(2)
  33. #define DNSC_BLUR_OPMODE_PCMN_H BIT(8)
  34. #define DNSC_BLUR_OPMODE_PCMN_V BIT(12)
  35. #define DNSC_BLUR_OPMODE_OUT_RND_8B_EN BIT(16)
  36. static struct sde_dnsc_blur_cfg *_dnsc_blur_offset(enum sde_dnsc_blur idx,
  37. struct sde_mdss_cfg *m, void __iomem *addr, struct sde_hw_blk_reg_map *b)
  38. {
  39. int i;
  40. for (i = 0; i < m->dnsc_blur_count; i++) {
  41. if (idx == m->dnsc_blur[i].id) {
  42. b->base_off = addr;
  43. b->blk_off = m->dnsc_blur[i].base;
  44. b->length = m->dnsc_blur[i].len;
  45. b->hw_rev = m->hw_rev;
  46. b->log_mask = SDE_DBG_MASK_DNSC_BLUR;
  47. return &m->dnsc_blur[i];
  48. }
  49. }
  50. return ERR_PTR(-EINVAL);
  51. }
  52. static inline int _dnsc_blur_subblk_offset(struct sde_hw_dnsc_blur *hw_dnsc_blur,
  53. int s_id, u32 *base)
  54. {
  55. const struct sde_dnsc_blur_sub_blks *sblk;
  56. sblk = hw_dnsc_blur->caps->sblk;
  57. switch (s_id) {
  58. case SDE_DNSC_BLUR_GAUS_LUT:
  59. *base = sblk->gaus_lut.base;
  60. break;
  61. case SDE_DNSC_BLUR_DITHER:
  62. *base = sblk->dither.base;
  63. break;
  64. default:
  65. return -EINVAL;
  66. }
  67. return 0;
  68. }
  69. static void _sde_hw_dnsc_blur_gaus_lut_setup(struct sde_hw_dnsc_blur *hw_dnsc_blur,
  70. struct sde_drm_dnsc_blur_cfg *cfg, u32 lut_sel)
  71. {
  72. struct sde_hw_blk_reg_map *hw = &hw_dnsc_blur->hw;
  73. u32 lut_off, base;
  74. int i;
  75. if (_dnsc_blur_subblk_offset(hw_dnsc_blur, SDE_DNSC_BLUR_GAUS_LUT, &base))
  76. return;
  77. SDE_REG_WRITE(hw, DNSC_BLUR_GAUS_COEF_LUT_SEL, lut_sel);
  78. if (cfg->flags_h & DNSC_BLUR_GAUS_FILTER) {
  79. lut_off = lut_sel ? DNSC_BLUR_GAUS_COEF_LUT_H1 : DNSC_BLUR_GAUS_COEF_LUT_H0;
  80. for (i = 0; i < DNSC_BLUR_COEF_NUM; i++)
  81. SDE_REG_WRITE(hw, lut_off + (i * 0x4) + base, cfg->coef_hori[i]);
  82. }
  83. if (cfg->flags_v & DNSC_BLUR_GAUS_FILTER) {
  84. lut_off = lut_sel ? DNSC_BLUR_GAUS_COEF_LUT_V1 : DNSC_BLUR_GAUS_COEF_LUT_V0;
  85. for (i = 0; i < DNSC_BLUR_COEF_NUM; i++)
  86. SDE_REG_WRITE(hw, lut_off + (i * 0x4) + base, cfg->coef_vert[i]);
  87. }
  88. }
  89. static void _sde_hw_dnsc_blur_filter_setup(struct sde_hw_dnsc_blur *hw_dnsc_blur,
  90. struct sde_drm_dnsc_blur_cfg *cfg, u32 lut_sel)
  91. {
  92. struct sde_hw_blk_reg_map *hw = &hw_dnsc_blur->hw;
  93. u32 val;
  94. /* PCMN */
  95. if (cfg->flags_h & DNSC_BLUR_PCMN_FILTER) {
  96. SDE_REG_WRITE(hw, DNSC_BLUR_PCMN_PHASE_INIT_H, cfg->phase_init_h);
  97. SDE_REG_WRITE(hw, DNSC_BLUR_PCMN_PHASE_STEP_H, cfg->phase_step_h);
  98. }
  99. if (cfg->flags_v & DNSC_BLUR_PCMN_FILTER) {
  100. SDE_REG_WRITE(hw, DNSC_BLUR_PCMN_PHASE_INIT_V, cfg->phase_init_v);
  101. SDE_REG_WRITE(hw, DNSC_BLUR_PCMN_PHASE_STEP_V, cfg->phase_step_v);
  102. }
  103. /* Gaussian */
  104. if (cfg->flags_h & DNSC_BLUR_GAUS_FILTER) {
  105. val = (cfg->norm_h << 16) | cfg->ratio_h;
  106. SDE_REG_WRITE(hw, DNSC_BLUR_BLUR_RATIO_H, val);
  107. }
  108. if (cfg->flags_v & DNSC_BLUR_GAUS_FILTER) {
  109. val = (cfg->norm_v << 16) | cfg->ratio_v;
  110. SDE_REG_WRITE(hw, DNSC_BLUR_BLUR_RATIO_V, val);
  111. }
  112. if ((cfg->flags_v | cfg->flags_h) & DNSC_BLUR_GAUS_FILTER)
  113. _sde_hw_dnsc_blur_gaus_lut_setup(hw_dnsc_blur, cfg, lut_sel);
  114. }
  115. static void _sde_hw_dnsc_blur_setup(struct sde_hw_dnsc_blur *hw_dnsc_blur,
  116. struct sde_drm_dnsc_blur_cfg *cfg, u32 lut_sel)
  117. {
  118. struct sde_hw_blk_reg_map *hw = &hw_dnsc_blur->hw;
  119. u32 opmode = 0;
  120. /* disable, when no scaling involved */
  121. if (!cfg || !(cfg->flags & DNSC_BLUR_EN)) {
  122. SDE_REG_WRITE(hw, DNSC_BLUR_OP_MODE, 0x0);
  123. return;
  124. }
  125. opmode = DNSC_BLUR_OPMODE_ENABLE;
  126. opmode |= (cfg->flags & DNSC_BLUR_RND_8B_EN) ? DNSC_BLUR_OPMODE_OUT_RND_8B_EN : 0;
  127. if (cfg->flags_h) {
  128. opmode |= DNSC_BLUR_OPMODE_DWNS_H_EN;
  129. opmode |= (cfg->flags_h & DNSC_BLUR_PCMN_FILTER) ? DNSC_BLUR_OPMODE_PCMN_H : 0;
  130. }
  131. if (cfg->flags_v) {
  132. opmode |= DNSC_BLUR_OPMODE_DWNS_V_EN;
  133. opmode |= (cfg->flags_v & DNSC_BLUR_PCMN_FILTER) ? DNSC_BLUR_OPMODE_PCMN_V : 0;
  134. }
  135. _sde_hw_dnsc_blur_filter_setup(hw_dnsc_blur, cfg, lut_sel);
  136. SDE_REG_WRITE(hw, DNSC_BLUR_OP_MODE, opmode);
  137. SDE_REG_WRITE(hw, DNSC_BLUR_OUT_IMG_SIZE, (cfg->dst_height << 16) | cfg->dst_width);
  138. SDE_REG_WRITE(hw, DNSC_BLUR_SRC_IMG_SIZE, (cfg->src_height << 16) | cfg->src_width);
  139. }
  140. static void _sde_hw_dnsc_blur_dither_setup(struct sde_hw_dnsc_blur *hw_dnsc_blur,
  141. struct sde_drm_dnsc_blur_cfg *cfg)
  142. {
  143. struct sde_hw_blk_reg_map *hw = &hw_dnsc_blur->hw;
  144. int i;
  145. u32 base, data, offset;
  146. if (_dnsc_blur_subblk_offset(hw_dnsc_blur, SDE_DNSC_BLUR_DITHER, &base))
  147. return;
  148. /* disable case */
  149. if (!cfg || !(cfg->flags & DNSC_BLUR_DITHER_EN)) {
  150. SDE_REG_WRITE(hw, DNSC_BLUR_DITHER_OP_MODE + base, 0x0);
  151. return;
  152. }
  153. data = (dither_depth_map[cfg->c0_bitdepth] & REG_MASK(2)) |
  154. ((dither_depth_map[cfg->c1_bitdepth] & REG_MASK(2)) << 2) |
  155. ((dither_depth_map[cfg->c2_bitdepth] & REG_MASK(2)) << 4) |
  156. ((dither_depth_map[cfg->c3_bitdepth] & REG_MASK(2)) << 6) |
  157. ((cfg->temporal_en) ? (1 << 8) : 0);
  158. SDE_REG_WRITE(hw, DNSC_BLUR_DITHER_BITDEPTH + base, data);
  159. offset = DNSC_BLUR_DITHER_MATRIX_ROW0;
  160. for (i = 0; i < DNSC_BLUR_DITHER_MATRIX_SZ - 3; i += 4) {
  161. data = (cfg->dither_matrix[i] & REG_MASK(4)) |
  162. ((cfg->dither_matrix[i + 1] & REG_MASK(4)) << 4) |
  163. ((cfg->dither_matrix[i + 2] & REG_MASK(4)) << 8) |
  164. ((cfg->dither_matrix[i + 3] & REG_MASK(4)) << 12);
  165. SDE_REG_WRITE(hw, base + offset, data);
  166. offset += 4;
  167. }
  168. data = BIT(0);
  169. data |= (cfg->dither_flags & DNSC_BLUR_DITHER_LUMA_MODE) ? BIT(4) : 0;
  170. SDE_REG_WRITE(hw, DNSC_BLUR_DITHER_OP_MODE + base, data);
  171. }
  172. static void _sde_hw_dnsc_blur_bind_pingpong_blk(struct sde_hw_dnsc_blur *hw_dnsc_blur,
  173. bool enable, const enum sde_pingpong pp)
  174. {
  175. struct sde_hw_blk_reg_map *hw = &hw_dnsc_blur->hw;
  176. int mux_cfg;
  177. if (enable && (pp < PINGPONG_0 || pp >= PINGPONG_MAX))
  178. return;
  179. mux_cfg = enable ? (pp - PINGPONG_0) & 0x7 : 0xF;
  180. SDE_REG_WRITE(hw, DNSC_BLUR_MUX, mux_cfg);
  181. }
  182. static void _setup_dnsc_blur_ops(struct sde_hw_dnsc_blur_ops *ops, unsigned long features)
  183. {
  184. ops->setup_dnsc_blur = _sde_hw_dnsc_blur_setup;
  185. ops->setup_dither = _sde_hw_dnsc_blur_dither_setup;
  186. ops->bind_pingpong_blk = _sde_hw_dnsc_blur_bind_pingpong_blk;
  187. }
  188. struct sde_hw_blk_reg_map *sde_hw_dnsc_blur_init(enum sde_dnsc_blur idx,
  189. void __iomem *addr, struct sde_mdss_cfg *m)
  190. {
  191. struct sde_hw_dnsc_blur *c;
  192. struct sde_dnsc_blur_cfg *cfg;
  193. if (!addr || !m)
  194. return ERR_PTR(-EINVAL);
  195. c = kzalloc(sizeof(*c), GFP_KERNEL);
  196. if (!c)
  197. return ERR_PTR(-ENOMEM);
  198. cfg = _dnsc_blur_offset(idx, m, addr, &c->hw);
  199. if (IS_ERR_OR_NULL(cfg)) {
  200. kfree(c);
  201. return ERR_PTR(-EINVAL);
  202. }
  203. c->idx = idx;
  204. c->caps = cfg;
  205. _setup_dnsc_blur_ops(&c->ops, c->caps->features);
  206. sde_dbg_reg_register_dump_range(SDE_DBG_NAME, cfg->name, c->hw.blk_off,
  207. c->hw.blk_off + c->hw.length, c->hw.xin_id);
  208. if (cfg->sblk->gaus_lut.base && cfg->sblk->gaus_lut.len)
  209. sde_dbg_reg_register_dump_range(SDE_DBG_NAME, cfg->sblk->gaus_lut.name,
  210. c->hw.blk_off + cfg->sblk->gaus_lut.base,
  211. c->hw.blk_off + cfg->sblk->gaus_lut.base +
  212. cfg->sblk->gaus_lut.len, c->hw.xin_id);
  213. if (cfg->sblk->dither.base && cfg->sblk->dither.len)
  214. sde_dbg_reg_register_dump_range(SDE_DBG_NAME, cfg->sblk->dither.name,
  215. c->hw.blk_off + cfg->sblk->dither.base,
  216. c->hw.blk_off + cfg->sblk->dither.base +
  217. cfg->sblk->dither.len, c->hw.xin_id);
  218. return &c->hw;
  219. }
  220. void sde_hw_dnsc_blur_destroy(struct sde_hw_blk_reg_map *hw)
  221. {
  222. if (hw)
  223. kfree(to_sde_hw_dnsc_blur(hw));
  224. }