sde_hw_ctl.c 34 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  5. */
  6. #include <linux/delay.h>
  7. #include "sde_hwio.h"
  8. #include "sde_hw_ctl.h"
  9. #include "sde_dbg.h"
  10. #include "sde_kms.h"
  11. #include "sde_reg_dma.h"
  12. #define CTL_LAYER(lm) \
  13. (((lm) == LM_5) ? (0x024) : (((lm) - LM_0) * 0x004))
  14. #define CTL_LAYER_EXT(lm) \
  15. (0x40 + (((lm) - LM_0) * 0x004))
  16. #define CTL_LAYER_EXT2(lm) \
  17. (0x70 + (((lm) - LM_0) * 0x004))
  18. #define CTL_LAYER_EXT3(lm) \
  19. (0xA0 + (((lm) - LM_0) * 0x004))
  20. #define CTL_LAYER_EXT4(lm) \
  21. (0xB8 + (((lm) - LM_0) * 0x004))
  22. #define CTL_TOP 0x014
  23. #define CTL_FLUSH 0x018
  24. #define CTL_START 0x01C
  25. #define CTL_PREPARE 0x0d0
  26. #define CTL_SW_RESET 0x030
  27. #define CTL_SW_RESET_OVERRIDE 0x060
  28. #define CTL_STATUS 0x064
  29. #define CTL_LAYER_EXTN_OFFSET 0x40
  30. #define CTL_ROT_TOP 0x0C0
  31. #define CTL_ROT_FLUSH 0x0C4
  32. #define CTL_ROT_START 0x0CC
  33. #define CTL_MERGE_3D_ACTIVE 0x0E4
  34. #define CTL_DSC_ACTIVE 0x0E8
  35. #define CTL_WB_ACTIVE 0x0EC
  36. #define CTL_CWB_ACTIVE 0x0F0
  37. #define CTL_INTF_ACTIVE 0x0F4
  38. #define CTL_CDM_ACTIVE 0x0F8
  39. #define CTL_FETCH_PIPE_ACTIVE 0x0FC
  40. #define CTL_MERGE_3D_FLUSH 0x100
  41. #define CTL_DSC_FLUSH 0x104
  42. #define CTL_WB_FLUSH 0x108
  43. #define CTL_CWB_FLUSH 0x10C
  44. #define CTL_INTF_FLUSH 0x110
  45. #define CTL_CDM_FLUSH 0x114
  46. #define CTL_PERIPH_FLUSH 0x128
  47. #define CTL_DSPP_0_FLUSH 0x13c
  48. #define CTL_INTF_MASTER 0x134
  49. #define CTL_UIDLE_ACTIVE 0x138
  50. #define CTL_MIXER_BORDER_OUT BIT(24)
  51. #define CTL_FLUSH_MASK_ROT BIT(27)
  52. #define CTL_FLUSH_MASK_CTL BIT(17)
  53. #define CTL_NUM_EXT 5
  54. #define CTL_SSPP_MAX_RECTS 2
  55. #define SDE_REG_RESET_TIMEOUT_US 2000
  56. #define SDE_REG_WAIT_RESET_TIMEOUT_US 100000
  57. #define UPDATE_MASK(m, idx, en) \
  58. ((m) = (en) ? ((m) | BIT((idx))) : ((m) & ~BIT((idx))))
  59. #define CTL_INVALID_BIT 0xffff
  60. #define VDC_IDX(i) ((i) + 16)
  61. #define UPDATE_ACTIVE(r, idx, en) UPDATE_MASK((r), (idx), (en))
  62. #define DNSC_BLUR_IDX(i) (i + 16)
  63. /**
  64. * List of SSPP bits in CTL_FLUSH
  65. */
  66. static const u32 sspp_tbl[SSPP_MAX] = { SDE_NONE, 0, 1, 2, 18, 11, 12, 24, 25, 13, 14};
  67. /**
  68. * List of layer mixer bits in CTL_FLUSH
  69. */
  70. static const u32 mixer_tbl[LM_MAX] = {SDE_NONE, 6, 7, 8, 9, 10, 20,
  71. SDE_NONE};
  72. /**
  73. * List of DSPP bits in CTL_FLUSH
  74. */
  75. static const u32 dspp_tbl[DSPP_MAX] = {SDE_NONE, 13, 14, 15, 21};
  76. /**
  77. * List of DSPP PA LUT bits in CTL_FLUSH
  78. */
  79. static const u32 dspp_pav_tbl[DSPP_MAX] = {SDE_NONE, 3, 4, 5, 19};
  80. /**
  81. * List of CDM LUT bits in CTL_FLUSH
  82. */
  83. static const u32 cdm_tbl[CDM_MAX] = {SDE_NONE, 26};
  84. /**
  85. * List of WB bits in CTL_FLUSH
  86. */
  87. static const u32 wb_tbl[WB_MAX] = {SDE_NONE, SDE_NONE, SDE_NONE, 16};
  88. /**
  89. * List of ROT bits in CTL_FLUSH
  90. */
  91. static const u32 rot_tbl[ROT_MAX] = {SDE_NONE, 27};
  92. /**
  93. * List of INTF bits in CTL_FLUSH
  94. */
  95. static const u32 intf_tbl[INTF_MAX] = {SDE_NONE, 31, 30, 29, 28};
  96. /**
  97. * Below definitions are for CTL supporting SDE_CTL_ACTIVE_CFG,
  98. * certain blocks have the individual flush control as well,
  99. * for such blocks flush is done by flushing individual control and
  100. * top level control.
  101. */
  102. /**
  103. * List of SSPP bits in CTL_FETCH_PIPE_ACTIVE
  104. */
  105. static const u32 fetch_tbl[SSPP_MAX] = {CTL_INVALID_BIT, 16, 17, 18, 19, 0, 1, 2, 3, 4, 5};
  106. /**
  107. * list of WB bits in CTL_WB_FLUSH
  108. */
  109. static const u32 wb_flush_tbl[WB_MAX] = {SDE_NONE, SDE_NONE, 1, 2};
  110. /**
  111. * list of INTF bits in CTL_INTF_FLUSH
  112. */
  113. static const u32 intf_flush_tbl[INTF_MAX] = {SDE_NONE, 0, 1, 2, 3, 4, 5};
  114. /**
  115. * list of DSC bits in CTL_DSC_FLUSH
  116. */
  117. static const u32 dsc_flush_tbl[DSC_MAX] = {SDE_NONE, 0, 1, 2, 3, 4, 5};
  118. /**
  119. * list of VDC bits in CTL_DSC_FLUSH
  120. */
  121. static const u32 vdc_flush_tbl[DSC_MAX] = {SDE_NONE, 16, 17};
  122. /**
  123. * list of MERGE_3D bits in CTL_MERGE_3D_FLUSH
  124. */
  125. static const u32 merge_3d_tbl[MERGE_3D_MAX] = {SDE_NONE, 0, 1, 2};
  126. /**
  127. * list of CDM bits in CTL_CDM_FLUSH
  128. */
  129. static const u32 cdm_flush_tbl[CDM_MAX] = {SDE_NONE, 0};
  130. /**
  131. * list of CWB bits in CTL_CWB_FLUSH
  132. */
  133. static const u32 cwb_flush_tbl[CWB_MAX] = {SDE_NONE, SDE_NONE, 1, 2, 3,
  134. 4, 5};
  135. /**
  136. * list of CWB bits in CTL_CWB_FLUSH for dedicated cwb
  137. */
  138. static const u32 dcwb_flush_tbl[CWB_MAX] = {SDE_NONE, SDE_NONE, 0, 1};
  139. /**
  140. * list of DSPP sub-blk flush bits in CTL_DSPP_x_FLUSH
  141. */
  142. static const u32 dspp_sub_blk_flush_tbl[SDE_DSPP_MAX] = {
  143. [SDE_DSPP_IGC] = 2,
  144. [SDE_DSPP_PCC] = 4,
  145. [SDE_DSPP_GC] = 5,
  146. [SDE_DSPP_HSIC] = 0,
  147. [SDE_DSPP_MEMCOLOR] = 0,
  148. [SDE_DSPP_SIXZONE] = 0,
  149. [SDE_DSPP_GAMUT] = 3,
  150. [SDE_DSPP_DITHER] = 0,
  151. [SDE_DSPP_HIST] = 0,
  152. [SDE_DSPP_VLUT] = 1,
  153. [SDE_DSPP_AD] = 0,
  154. [SDE_DSPP_LTM] = 7,
  155. [SDE_DSPP_SPR] = 8,
  156. [SDE_DSPP_DEMURA] = 9,
  157. [SDE_DSPP_RC] = 10,
  158. [SDE_DSPP_SB] = 31,
  159. };
  160. /**
  161. * struct ctl_sspp_stage_reg_map: Describes bit layout for a sspp stage cfg
  162. * @ext: Index to indicate LAYER_x_EXT id for given sspp
  163. * @start: Start position of blend stage bits for given sspp
  164. * @bits: Number of bits from @start assigned for given sspp
  165. * @sec_bit_mask: Bitmask to add to LAYER_x_EXT1 for missing bit of sspp
  166. */
  167. struct ctl_sspp_stage_reg_map {
  168. u32 ext;
  169. u32 start;
  170. u32 bits;
  171. u32 sec_bit_mask;
  172. };
  173. /* list of ctl_sspp_stage_reg_map for all the sppp */
  174. static const struct ctl_sspp_stage_reg_map
  175. sspp_reg_cfg_tbl[SSPP_MAX][CTL_SSPP_MAX_RECTS] = {
  176. /* SSPP_NONE */{ {0, 0, 0, 0}, {0, 0, 0, 0} },
  177. /* SSPP_VIG0 */{ {0, 0, 3, BIT(0)}, {3, 0, 4, 0} },
  178. /* SSPP_VIG1 */{ {0, 3, 3, BIT(2)}, {3, 4, 4, 0} },
  179. /* SSPP_VIG2 */{ {0, 6, 3, BIT(4)}, {3, 8, 4, 0} },
  180. /* SSPP_VIG3 */{ {0, 26, 3, BIT(6)}, {3, 12, 4, 0} },
  181. /* SSPP_DMA0 */{ {0, 18, 3, BIT(16)}, {2, 8, 4, 0} },
  182. /* SSPP_DMA1 */{ {0, 21, 3, BIT(18)}, {2, 12, 4, 0} },
  183. /* SSPP_DMA2 */{ {2, 0, 4, 0}, {2, 16, 4, 0} },
  184. /* SSPP_DMA3 */{ {2, 4, 4, 0}, {2, 20, 4, 0} },
  185. /* SSPP_DMA4 */{ {4, 0, 4, 0}, {4, 8, 4, 0} },
  186. /* SSPP_DMA5 */{ {4, 4, 4, 0}, {4, 12, 4, 0} },
  187. };
  188. /**
  189. * Individual flush bit in CTL_FLUSH
  190. */
  191. #define WB_IDX 16
  192. #define DSC_IDX 22
  193. #define MERGE_3D_IDX 23
  194. #define CDM_IDX 26
  195. #define CWB_IDX 28
  196. #define DSPP_IDX 29
  197. #define PERIPH_IDX 30
  198. #define INTF_IDX 31
  199. /* struct ctl_hw_flush_cfg: Defines the active ctl hw flush config,
  200. * See enum ctl_hw_flush_type for types
  201. * @blk_max: Maximum hw idx
  202. * @flush_reg: Register with corresponding active ctl hw
  203. * @flush_idx: Corresponding index in ctl flush
  204. * @flush_mask_idx: Index of hw flush mask to use
  205. * @flush_tbl: Pointer to flush table
  206. */
  207. struct ctl_hw_flush_cfg {
  208. u32 blk_max;
  209. u32 flush_reg;
  210. u32 flush_idx;
  211. u32 flush_mask_idx;
  212. const u32 *flush_tbl;
  213. };
  214. static const struct ctl_hw_flush_cfg
  215. ctl_hw_flush_cfg_tbl_v1[SDE_HW_FLUSH_MAX] = {
  216. {WB_MAX, CTL_WB_FLUSH, WB_IDX, SDE_HW_FLUSH_WB,
  217. wb_flush_tbl}, /* SDE_HW_FLUSH_WB */
  218. {DSC_MAX, CTL_DSC_FLUSH, DSC_IDX, SDE_HW_FLUSH_DSC,
  219. dsc_flush_tbl}, /* SDE_HW_FLUSH_DSC */
  220. /* VDC is flushed to dsc, flush_reg = 0 so flush is done only once */
  221. {VDC_MAX, 0, DSC_IDX, SDE_HW_FLUSH_DSC,
  222. vdc_flush_tbl}, /* SDE_HW_FLUSH_VDC */
  223. {MERGE_3D_MAX, CTL_MERGE_3D_FLUSH, MERGE_3D_IDX, SDE_HW_FLUSH_MERGE_3D,
  224. merge_3d_tbl}, /* SDE_HW_FLUSH_MERGE_3D */
  225. {CDM_MAX, CTL_CDM_FLUSH, CDM_IDX, SDE_HW_FLUSH_CDM,
  226. cdm_flush_tbl}, /* SDE_HW_FLUSH_CDM */
  227. {CWB_MAX, CTL_CWB_FLUSH, CWB_IDX, SDE_HW_FLUSH_CWB,
  228. cwb_flush_tbl}, /* SDE_HW_FLUSH_CWB */
  229. {INTF_MAX, CTL_PERIPH_FLUSH, PERIPH_IDX, SDE_HW_FLUSH_PERIPH,
  230. intf_flush_tbl }, /* SDE_HW_FLUSH_PERIPH */
  231. {INTF_MAX, CTL_INTF_FLUSH, INTF_IDX, SDE_HW_FLUSH_INTF,
  232. intf_flush_tbl } /* SDE_HW_FLUSH_INTF */
  233. };
  234. static struct sde_ctl_cfg *_ctl_offset(enum sde_ctl ctl,
  235. struct sde_mdss_cfg *m,
  236. void __iomem *addr,
  237. struct sde_hw_blk_reg_map *b)
  238. {
  239. int i;
  240. for (i = 0; i < m->ctl_count; i++) {
  241. if (ctl == m->ctl[i].id) {
  242. b->base_off = addr;
  243. b->blk_off = m->ctl[i].base;
  244. b->length = m->ctl[i].len;
  245. b->hw_rev = m->hw_rev;
  246. b->log_mask = SDE_DBG_MASK_CTL;
  247. return &m->ctl[i];
  248. }
  249. }
  250. return ERR_PTR(-ENOMEM);
  251. }
  252. static int _mixer_stages(const struct sde_lm_cfg *mixer, int count,
  253. enum sde_lm lm)
  254. {
  255. int i;
  256. int stages = -EINVAL;
  257. for (i = 0; i < count; i++) {
  258. if (lm == mixer[i].id) {
  259. stages = mixer[i].sblk->maxblendstages;
  260. break;
  261. }
  262. }
  263. return stages;
  264. }
  265. static inline bool _is_dspp_flush_pending(struct sde_hw_ctl *ctx)
  266. {
  267. int i;
  268. for (i = 0; i < CTL_MAX_DSPP_COUNT; i++) {
  269. if (ctx->flush.pending_dspp_flush_masks[i])
  270. return true;
  271. }
  272. return false;
  273. }
  274. static inline int sde_hw_ctl_trigger_start(struct sde_hw_ctl *ctx)
  275. {
  276. if (!ctx)
  277. return -EINVAL;
  278. SDE_REG_WRITE(&ctx->hw, CTL_START, 0x1);
  279. return 0;
  280. }
  281. static inline int sde_hw_ctl_get_start_state(struct sde_hw_ctl *ctx)
  282. {
  283. if (!ctx)
  284. return -EINVAL;
  285. return SDE_REG_READ(&ctx->hw, CTL_START);
  286. }
  287. static inline int sde_hw_ctl_trigger_pending(struct sde_hw_ctl *ctx)
  288. {
  289. if (!ctx)
  290. return -EINVAL;
  291. SDE_REG_WRITE(&ctx->hw, CTL_PREPARE, 0x1);
  292. return 0;
  293. }
  294. static inline int sde_hw_ctl_clear_pending_flush(struct sde_hw_ctl *ctx)
  295. {
  296. if (!ctx)
  297. return -EINVAL;
  298. memset(&ctx->flush, 0, sizeof(ctx->flush));
  299. return 0;
  300. }
  301. static inline int sde_hw_ctl_update_pending_flush(struct sde_hw_ctl *ctx,
  302. struct sde_ctl_flush_cfg *cfg)
  303. {
  304. if (!ctx || !cfg)
  305. return -EINVAL;
  306. ctx->flush.pending_flush_mask |= cfg->pending_flush_mask;
  307. return 0;
  308. }
  309. static int sde_hw_ctl_get_pending_flush(struct sde_hw_ctl *ctx,
  310. struct sde_ctl_flush_cfg *cfg)
  311. {
  312. if (!ctx || !cfg)
  313. return -EINVAL;
  314. memcpy(cfg, &ctx->flush, sizeof(*cfg));
  315. return 0;
  316. }
  317. static inline int sde_hw_ctl_trigger_flush(struct sde_hw_ctl *ctx)
  318. {
  319. if (!ctx)
  320. return -EINVAL;
  321. SDE_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->flush.pending_flush_mask);
  322. return 0;
  323. }
  324. static inline u32 sde_hw_ctl_get_flush_register(struct sde_hw_ctl *ctx)
  325. {
  326. struct sde_hw_blk_reg_map *c;
  327. u32 rot_op_mode;
  328. if (!ctx)
  329. return 0;
  330. c = &ctx->hw;
  331. rot_op_mode = SDE_REG_READ(c, CTL_ROT_TOP) & 0x3;
  332. /* rotate flush bit is undefined if offline mode, so ignore it */
  333. if (rot_op_mode == SDE_CTL_ROT_OP_MODE_OFFLINE)
  334. return SDE_REG_READ(c, CTL_FLUSH) & ~CTL_FLUSH_MASK_ROT;
  335. return SDE_REG_READ(c, CTL_FLUSH);
  336. }
  337. static inline void sde_hw_ctl_uidle_enable(struct sde_hw_ctl *ctx, bool enable)
  338. {
  339. u32 val;
  340. if (!ctx)
  341. return;
  342. val = SDE_REG_READ(&ctx->hw, CTL_UIDLE_ACTIVE);
  343. val = (val & ~BIT(0)) | (enable ? BIT(0) : 0);
  344. SDE_REG_WRITE(&ctx->hw, CTL_UIDLE_ACTIVE, val);
  345. }
  346. static inline int sde_hw_ctl_update_bitmask_sspp(struct sde_hw_ctl *ctx,
  347. enum sde_sspp sspp,
  348. bool enable)
  349. {
  350. if (!ctx)
  351. return -EINVAL;
  352. if (!(sspp > SSPP_NONE) || !(sspp < SSPP_MAX)) {
  353. SDE_ERROR("Unsupported pipe %d\n", sspp);
  354. return -EINVAL;
  355. }
  356. UPDATE_MASK(ctx->flush.pending_flush_mask, sspp_tbl[sspp], enable);
  357. return 0;
  358. }
  359. static inline int sde_hw_ctl_update_bitmask_mixer(struct sde_hw_ctl *ctx,
  360. enum sde_lm lm,
  361. bool enable)
  362. {
  363. if (!ctx)
  364. return -EINVAL;
  365. if (!(lm > SDE_NONE) || !(lm < LM_MAX)) {
  366. SDE_ERROR("Unsupported mixer %d\n", lm);
  367. return -EINVAL;
  368. }
  369. UPDATE_MASK(ctx->flush.pending_flush_mask, mixer_tbl[lm], enable);
  370. ctx->flush.pending_flush_mask |= CTL_FLUSH_MASK_CTL;
  371. return 0;
  372. }
  373. static inline int sde_hw_ctl_update_bitmask_dspp(struct sde_hw_ctl *ctx,
  374. enum sde_dspp dspp,
  375. bool enable)
  376. {
  377. if (!ctx)
  378. return -EINVAL;
  379. if (!(dspp > SDE_NONE) || !(dspp < DSPP_MAX)) {
  380. SDE_ERROR("Unsupported dspp %d\n", dspp);
  381. return -EINVAL;
  382. }
  383. UPDATE_MASK(ctx->flush.pending_flush_mask, dspp_tbl[dspp], enable);
  384. return 0;
  385. }
  386. static inline int sde_hw_ctl_update_bitmask_dspp_pavlut(struct sde_hw_ctl *ctx,
  387. enum sde_dspp dspp, bool enable)
  388. {
  389. if (!ctx)
  390. return -EINVAL;
  391. if (!(dspp > SDE_NONE) || !(dspp < DSPP_MAX)) {
  392. SDE_ERROR("Unsupported dspp %d\n", dspp);
  393. return -EINVAL;
  394. }
  395. UPDATE_MASK(ctx->flush.pending_flush_mask, dspp_pav_tbl[dspp], enable);
  396. return 0;
  397. }
  398. static inline int sde_hw_ctl_update_bitmask_cdm(struct sde_hw_ctl *ctx,
  399. enum sde_cdm cdm,
  400. bool enable)
  401. {
  402. if (!ctx)
  403. return -EINVAL;
  404. if (!(cdm > SDE_NONE) || !(cdm < CDM_MAX) || (cdm == CDM_1)) {
  405. SDE_ERROR("Unsupported cdm %d\n", cdm);
  406. return -EINVAL;
  407. }
  408. UPDATE_MASK(ctx->flush.pending_flush_mask, cdm_tbl[cdm], enable);
  409. return 0;
  410. }
  411. static inline int sde_hw_ctl_update_bitmask_wb(struct sde_hw_ctl *ctx,
  412. enum sde_wb wb, bool enable)
  413. {
  414. if (!ctx)
  415. return -EINVAL;
  416. if (!(wb > SDE_NONE) || !(wb < WB_MAX) ||
  417. (wb == WB_0) || (wb == WB_1)) {
  418. SDE_ERROR("Unsupported wb %d\n", wb);
  419. return -EINVAL;
  420. }
  421. UPDATE_MASK(ctx->flush.pending_flush_mask, wb_tbl[wb], enable);
  422. return 0;
  423. }
  424. static inline int sde_hw_ctl_update_bitmask_intf(struct sde_hw_ctl *ctx,
  425. enum sde_intf intf, bool enable)
  426. {
  427. if (!ctx)
  428. return -EINVAL;
  429. if (!(intf > SDE_NONE) || !(intf < INTF_MAX) || (intf > INTF_4)) {
  430. SDE_ERROR("Unsupported intf %d\n", intf);
  431. return -EINVAL;
  432. }
  433. UPDATE_MASK(ctx->flush.pending_flush_mask, intf_tbl[intf], enable);
  434. return 0;
  435. }
  436. static inline int sde_hw_ctl_update_bitmask(struct sde_hw_ctl *ctx,
  437. enum ctl_hw_flush_type type, u32 blk_idx, bool enable)
  438. {
  439. int ret = 0;
  440. if (!ctx)
  441. return -EINVAL;
  442. switch (type) {
  443. case SDE_HW_FLUSH_CDM:
  444. ret = sde_hw_ctl_update_bitmask_cdm(ctx, blk_idx, enable);
  445. break;
  446. case SDE_HW_FLUSH_WB:
  447. ret = sde_hw_ctl_update_bitmask_wb(ctx, blk_idx, enable);
  448. break;
  449. case SDE_HW_FLUSH_INTF:
  450. ret = sde_hw_ctl_update_bitmask_intf(ctx, blk_idx, enable);
  451. break;
  452. default:
  453. break;
  454. }
  455. return ret;
  456. }
  457. static inline int sde_hw_ctl_update_bitmask_v1(struct sde_hw_ctl *ctx,
  458. enum ctl_hw_flush_type type, u32 blk_idx, bool enable)
  459. {
  460. const struct ctl_hw_flush_cfg *cfg;
  461. if (!ctx || !(type < SDE_HW_FLUSH_MAX))
  462. return -EINVAL;
  463. cfg = &ctl_hw_flush_cfg_tbl_v1[type];
  464. if ((blk_idx <= SDE_NONE) || (blk_idx >= cfg->blk_max)) {
  465. SDE_ERROR("Unsupported hw idx, type:%d, blk_idx:%d, blk_max:%d",
  466. type, blk_idx, cfg->blk_max);
  467. return -EINVAL;
  468. }
  469. UPDATE_MASK(ctx->flush.pending_hw_flush_mask[cfg->flush_mask_idx],
  470. cfg->flush_tbl[blk_idx], enable);
  471. if (ctx->flush.pending_hw_flush_mask[cfg->flush_mask_idx])
  472. UPDATE_MASK(ctx->flush.pending_flush_mask, cfg->flush_idx, 1);
  473. else
  474. UPDATE_MASK(ctx->flush.pending_flush_mask, cfg->flush_idx, 0);
  475. return 0;
  476. }
  477. static inline void sde_hw_ctl_update_dnsc_blur_bitmask(struct sde_hw_ctl *ctx,
  478. u32 blk_idx, bool enable)
  479. {
  480. if (enable)
  481. ctx->flush.pending_hw_flush_mask[SDE_HW_FLUSH_WB] |=
  482. BIT(DNSC_BLUR_IDX(blk_idx) - DNSC_BLUR_0);
  483. else
  484. ctx->flush.pending_hw_flush_mask[SDE_HW_FLUSH_WB] &=
  485. ~BIT(DNSC_BLUR_IDX(blk_idx) - DNSC_BLUR_0);
  486. }
  487. static inline int sde_hw_ctl_update_pending_flush_v1(
  488. struct sde_hw_ctl *ctx,
  489. struct sde_ctl_flush_cfg *cfg)
  490. {
  491. int i = 0;
  492. if (!ctx || !cfg)
  493. return -EINVAL;
  494. for (i = 0; i < SDE_HW_FLUSH_MAX; i++)
  495. ctx->flush.pending_hw_flush_mask[i] |=
  496. cfg->pending_hw_flush_mask[i];
  497. for (i = 0; i < CTL_MAX_DSPP_COUNT; i++)
  498. ctx->flush.pending_dspp_flush_masks[i] |=
  499. cfg->pending_dspp_flush_masks[i];
  500. ctx->flush.pending_flush_mask |= cfg->pending_flush_mask;
  501. return 0;
  502. }
  503. static inline int sde_hw_ctl_update_bitmask_dspp_subblk(struct sde_hw_ctl *ctx,
  504. enum sde_dspp dspp, u32 sub_blk, bool enable)
  505. {
  506. if (!ctx || dspp < DSPP_0 || dspp >= DSPP_MAX ||
  507. sub_blk < SDE_DSPP_IGC || sub_blk >= SDE_DSPP_MAX) {
  508. SDE_ERROR("invalid args - ctx %s, dspp %d sub_block %d\n",
  509. ctx ? "valid" : "invalid", dspp, sub_blk);
  510. return -EINVAL;
  511. }
  512. UPDATE_MASK(ctx->flush.pending_dspp_flush_masks[dspp - DSPP_0],
  513. dspp_sub_blk_flush_tbl[sub_blk], enable);
  514. if (_is_dspp_flush_pending(ctx))
  515. UPDATE_MASK(ctx->flush.pending_flush_mask, DSPP_IDX, 1);
  516. else
  517. UPDATE_MASK(ctx->flush.pending_flush_mask, DSPP_IDX, 0);
  518. return 0;
  519. }
  520. static void sde_hw_ctl_set_fetch_pipe_active(struct sde_hw_ctl *ctx,
  521. unsigned long *fetch_active)
  522. {
  523. int i;
  524. u32 val = 0;
  525. if (fetch_active) {
  526. for (i = 0; i < SSPP_MAX; i++) {
  527. if (test_bit(i, fetch_active) &&
  528. fetch_tbl[i] != CTL_INVALID_BIT)
  529. val |= BIT(fetch_tbl[i]);
  530. }
  531. }
  532. SDE_REG_WRITE(&ctx->hw, CTL_FETCH_PIPE_ACTIVE, val);
  533. }
  534. static u32 sde_hw_ctl_get_active_fetch_pipes(struct sde_hw_ctl *ctx)
  535. {
  536. int i;
  537. u32 fetch_info, fetch_active = 0;
  538. if (!ctx) {
  539. DRM_ERROR("invalid args - ctx invalid\n");
  540. return 0;
  541. }
  542. fetch_info = SDE_REG_READ(&ctx->hw, CTL_FETCH_PIPE_ACTIVE);
  543. for (i = SSPP_VIG0; i < SSPP_MAX; i++) {
  544. if (fetch_tbl[i] != CTL_INVALID_BIT &&
  545. fetch_info & BIT(fetch_tbl[i])) {
  546. fetch_active |= BIT(i);
  547. }
  548. }
  549. return fetch_active;
  550. }
  551. static inline void _sde_hw_ctl_write_dspp_flushes(struct sde_hw_ctl *ctx) {
  552. int i;
  553. bool has_dspp_flushes = ctx->caps->features &
  554. BIT(SDE_CTL_UNIFIED_DSPP_FLUSH);
  555. if (!has_dspp_flushes)
  556. return;
  557. for (i = 0; i < CTL_MAX_DSPP_COUNT; i++) {
  558. u32 pending = ctx->flush.pending_dspp_flush_masks[i];
  559. if (pending)
  560. SDE_REG_WRITE(&ctx->hw, CTL_DSPP_0_FLUSH + (i * 4),
  561. pending);
  562. }
  563. }
  564. static inline int sde_hw_ctl_trigger_flush_v1(struct sde_hw_ctl *ctx)
  565. {
  566. int i = 0;
  567. const struct ctl_hw_flush_cfg *cfg = &ctl_hw_flush_cfg_tbl_v1[0];
  568. if (!ctx)
  569. return -EINVAL;
  570. if (ctx->flush.pending_flush_mask & BIT(DSPP_IDX))
  571. _sde_hw_ctl_write_dspp_flushes(ctx);
  572. for (i = 0; i < SDE_HW_FLUSH_MAX; i++)
  573. if (cfg[i].flush_reg &&
  574. ctx->flush.pending_flush_mask &
  575. BIT(cfg[i].flush_idx))
  576. SDE_REG_WRITE(&ctx->hw,
  577. cfg[i].flush_reg,
  578. ctx->flush.pending_hw_flush_mask[i]);
  579. SDE_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->flush.pending_flush_mask);
  580. return 0;
  581. }
  582. static inline u32 sde_hw_ctl_get_intf_v1(struct sde_hw_ctl *ctx)
  583. {
  584. struct sde_hw_blk_reg_map *c;
  585. u32 intf_active;
  586. if (!ctx) {
  587. pr_err("Invalid input argument\n");
  588. return 0;
  589. }
  590. c = &ctx->hw;
  591. intf_active = SDE_REG_READ(c, CTL_INTF_ACTIVE);
  592. return intf_active;
  593. }
  594. static inline u32 sde_hw_ctl_get_intf(struct sde_hw_ctl *ctx)
  595. {
  596. struct sde_hw_blk_reg_map *c;
  597. u32 ctl_top;
  598. u32 intf_active = 0;
  599. if (!ctx) {
  600. pr_err("Invalid input argument\n");
  601. return 0;
  602. }
  603. c = &ctx->hw;
  604. ctl_top = SDE_REG_READ(c, CTL_TOP);
  605. intf_active = (ctl_top > 0) ?
  606. BIT(ctl_top - 1) : 0;
  607. return intf_active;
  608. }
  609. static u32 sde_hw_ctl_poll_reset_status(struct sde_hw_ctl *ctx, u32 timeout_us)
  610. {
  611. struct sde_hw_blk_reg_map *c;
  612. ktime_t timeout;
  613. u32 status;
  614. if (!ctx)
  615. return 0;
  616. c = &ctx->hw;
  617. timeout = ktime_add_us(ktime_get(), timeout_us);
  618. /*
  619. * it takes around 30us to have mdp finish resetting its ctl path
  620. * poll every 50us so that reset should be completed at 1st poll
  621. */
  622. do {
  623. status = SDE_REG_READ(c, CTL_SW_RESET);
  624. status &= 0x1;
  625. if (status)
  626. usleep_range(20, 50);
  627. } while (status && ktime_compare_safe(ktime_get(), timeout) < 0);
  628. return status;
  629. }
  630. static u32 sde_hw_ctl_get_reset_status(struct sde_hw_ctl *ctx)
  631. {
  632. if (!ctx)
  633. return 0;
  634. return (u32)SDE_REG_READ(&ctx->hw, CTL_SW_RESET);
  635. }
  636. static u32 sde_hw_ctl_get_scheduler_status(struct sde_hw_ctl *ctx)
  637. {
  638. if (!ctx)
  639. return INVALID_CTL_STATUS;
  640. return (u32)SDE_REG_READ(&ctx->hw, CTL_STATUS);
  641. }
  642. static int sde_hw_ctl_reset_control(struct sde_hw_ctl *ctx)
  643. {
  644. struct sde_hw_blk_reg_map *c;
  645. if (!ctx)
  646. return 0;
  647. c = &ctx->hw;
  648. pr_debug("issuing hw ctl reset for ctl:%d\n", ctx->idx);
  649. SDE_REG_WRITE(c, CTL_SW_RESET, 0x1);
  650. if (sde_hw_ctl_poll_reset_status(ctx, SDE_REG_RESET_TIMEOUT_US))
  651. return -EINVAL;
  652. return 0;
  653. }
  654. static void sde_hw_ctl_hard_reset(struct sde_hw_ctl *ctx, bool enable)
  655. {
  656. struct sde_hw_blk_reg_map *c;
  657. if (!ctx)
  658. return;
  659. c = &ctx->hw;
  660. pr_debug("hw ctl hard reset for ctl:%d, %d\n",
  661. ctx->idx - CTL_0, enable);
  662. SDE_REG_WRITE(c, CTL_SW_RESET_OVERRIDE, enable);
  663. }
  664. static int sde_hw_ctl_wait_reset_status(struct sde_hw_ctl *ctx)
  665. {
  666. struct sde_hw_blk_reg_map *c;
  667. u32 status;
  668. if (!ctx)
  669. return 0;
  670. c = &ctx->hw;
  671. status = SDE_REG_READ(c, CTL_SW_RESET);
  672. status &= 0x01;
  673. if (!status)
  674. return 0;
  675. pr_debug("hw ctl reset is set for ctl:%d\n", ctx->idx);
  676. if (sde_hw_ctl_poll_reset_status(ctx, SDE_REG_WAIT_RESET_TIMEOUT_US)) {
  677. pr_err("hw recovery is not complete for ctl:%d\n", ctx->idx);
  678. return -EINVAL;
  679. }
  680. return 0;
  681. }
  682. static void sde_hw_ctl_clear_all_blendstages(struct sde_hw_ctl *ctx)
  683. {
  684. struct sde_hw_blk_reg_map *c;
  685. int i;
  686. if (!ctx)
  687. return;
  688. c = &ctx->hw;
  689. for (i = 0; i < ctx->mixer_count; i++) {
  690. int mixer_id = ctx->mixer_hw_caps[i].id;
  691. SDE_REG_WRITE(c, CTL_LAYER(mixer_id), 0);
  692. SDE_REG_WRITE(c, CTL_LAYER_EXT(mixer_id), 0);
  693. SDE_REG_WRITE(c, CTL_LAYER_EXT2(mixer_id), 0);
  694. SDE_REG_WRITE(c, CTL_LAYER_EXT3(mixer_id), 0);
  695. SDE_REG_WRITE(c, CTL_LAYER_EXT4(mixer_id), 0);
  696. }
  697. SDE_REG_WRITE(c, CTL_FETCH_PIPE_ACTIVE, 0);
  698. }
  699. static void _sde_hw_ctl_get_mixer_cfg(struct sde_hw_ctl *ctx,
  700. struct sde_hw_stage_cfg *stage_cfg, int stages, u32 *cfg)
  701. {
  702. int i, j, pipes_per_stage;
  703. const struct ctl_sspp_stage_reg_map *reg_map;
  704. if (test_bit(SDE_MIXER_SOURCESPLIT, &ctx->mixer_hw_caps->features))
  705. pipes_per_stage = PIPES_PER_STAGE;
  706. else
  707. pipes_per_stage = 1;
  708. for (i = 0; i <= stages; i++) {
  709. /* overflow to ext register if 'i + 1 > 7' */
  710. for (j = 0 ; j < pipes_per_stage; j++) {
  711. enum sde_sspp pipe = stage_cfg->stage[i][j];
  712. enum sde_sspp_multirect_index rect_index =
  713. stage_cfg->multirect_index[i][j];
  714. u32 mixer_value;
  715. if (!pipe || pipe >= SSPP_MAX || rect_index >= SDE_SSPP_RECT_MAX)
  716. continue;
  717. /* Handle multi rect enums */
  718. if (rect_index == SDE_SSPP_RECT_SOLO)
  719. rect_index = SDE_SSPP_RECT_0;
  720. reg_map = &sspp_reg_cfg_tbl[pipe][rect_index-1];
  721. if (!reg_map->bits)
  722. continue;
  723. mixer_value = (i + 1) & (BIT(reg_map->bits) - 1);
  724. cfg[reg_map->ext] |= (mixer_value << reg_map->start);
  725. if ((i + 1) > mixer_value)
  726. cfg[1] |= reg_map->sec_bit_mask;
  727. }
  728. }
  729. }
  730. static void sde_hw_ctl_setup_blendstage(struct sde_hw_ctl *ctx,
  731. enum sde_lm lm, struct sde_hw_stage_cfg *stage_cfg,
  732. bool disable_border)
  733. {
  734. struct sde_hw_blk_reg_map *c;
  735. u32 cfg[CTL_NUM_EXT] = { 0 };
  736. int stages;
  737. bool null_commit;
  738. if (!ctx)
  739. return;
  740. stages = _mixer_stages(ctx->mixer_hw_caps, ctx->mixer_count, lm);
  741. if (stages < 0)
  742. return;
  743. c = &ctx->hw;
  744. if (stage_cfg)
  745. _sde_hw_ctl_get_mixer_cfg(ctx, stage_cfg, stages, cfg);
  746. null_commit = (!cfg[0] && !cfg[1] && !cfg[2] && !cfg[3] && !cfg[4]);
  747. if (!disable_border && (null_commit || (stage_cfg && !stage_cfg->stage[0][0])))
  748. cfg[0] |= CTL_MIXER_BORDER_OUT;
  749. SDE_REG_WRITE(c, CTL_LAYER(lm), cfg[0]);
  750. SDE_REG_WRITE(c, CTL_LAYER_EXT(lm), cfg[1]);
  751. SDE_REG_WRITE(c, CTL_LAYER_EXT2(lm), cfg[2]);
  752. SDE_REG_WRITE(c, CTL_LAYER_EXT3(lm), cfg[3]);
  753. SDE_REG_WRITE(c, CTL_LAYER_EXT4(lm), cfg[4]);
  754. }
  755. static u32 sde_hw_ctl_get_staged_sspp(struct sde_hw_ctl *ctx, enum sde_lm lm,
  756. struct sde_sspp_index_info *info)
  757. {
  758. int i, j;
  759. u32 count = 0;
  760. u32 mask = 0;
  761. bool staged;
  762. u32 mixercfg[CTL_NUM_EXT];
  763. struct sde_hw_blk_reg_map *c;
  764. const struct ctl_sspp_stage_reg_map *sspp_cfg;
  765. if (!ctx || (lm >= LM_DCWB_DUMMY_0) || !info)
  766. return 0;
  767. c = &ctx->hw;
  768. mixercfg[0] = SDE_REG_READ(c, CTL_LAYER(lm));
  769. mixercfg[1] = SDE_REG_READ(c, CTL_LAYER_EXT(lm));
  770. mixercfg[2] = SDE_REG_READ(c, CTL_LAYER_EXT2(lm));
  771. mixercfg[3] = SDE_REG_READ(c, CTL_LAYER_EXT3(lm));
  772. mixercfg[4] = SDE_REG_READ(c, CTL_LAYER_EXT4(lm));
  773. if (mixercfg[0] & CTL_MIXER_BORDER_OUT)
  774. info->bordercolor = true;
  775. for (i = SSPP_VIG0; i < SSPP_MAX; i++) {
  776. for (j = 0; j < CTL_SSPP_MAX_RECTS; j++) {
  777. sspp_cfg = &sspp_reg_cfg_tbl[i][j];
  778. if (!sspp_cfg->bits || sspp_cfg->ext >= CTL_NUM_EXT)
  779. continue;
  780. mask = ((0x1 << sspp_cfg->bits) - 1) << sspp_cfg->start;
  781. staged = mixercfg[sspp_cfg->ext] & mask;
  782. if (!staged)
  783. staged = mixercfg[1] & sspp_cfg->sec_bit_mask;
  784. if (staged) {
  785. if (j)
  786. set_bit(i, info->virt_pipes);
  787. else
  788. set_bit(i, info->pipes);
  789. count++;
  790. }
  791. }
  792. }
  793. return count;
  794. }
  795. static int sde_hw_ctl_intf_cfg_v1(struct sde_hw_ctl *ctx,
  796. struct sde_hw_intf_cfg_v1 *cfg)
  797. {
  798. struct sde_hw_blk_reg_map *c;
  799. u32 intf_active = 0;
  800. u32 wb_active = 0;
  801. u32 merge_3d_active = 0;
  802. u32 cwb_active = 0;
  803. u32 mode_sel = 0xf0000000;
  804. u32 cdm_active = 0;
  805. u32 intf_master = 0;
  806. u32 i;
  807. if (!ctx)
  808. return -EINVAL;
  809. c = &ctx->hw;
  810. for (i = 0; i < cfg->intf_count; i++) {
  811. if (cfg->intf[i])
  812. intf_active |= BIT(cfg->intf[i] - INTF_0);
  813. }
  814. if (cfg->intf_count > 1)
  815. intf_master = BIT(cfg->intf_master - INTF_0);
  816. for (i = 0; i < cfg->wb_count; i++) {
  817. if (cfg->wb[i])
  818. wb_active |= BIT(cfg->wb[i] - WB_0);
  819. }
  820. for (i = 0; i < cfg->dnsc_blur_count; i++) {
  821. if (cfg->dnsc_blur[i])
  822. wb_active |= BIT(DNSC_BLUR_IDX(cfg->dnsc_blur[i] - DNSC_BLUR_0));
  823. }
  824. for (i = 0; i < cfg->merge_3d_count; i++) {
  825. if (cfg->merge_3d[i])
  826. merge_3d_active |= BIT(cfg->merge_3d[i] - MERGE_3D_0);
  827. }
  828. for (i = 0; i < cfg->cwb_count; i++) {
  829. if (cfg->cwb[i])
  830. cwb_active |= BIT(cfg->cwb[i] - CWB_0);
  831. }
  832. for (i = 0; i < cfg->cdm_count; i++) {
  833. if (cfg->cdm[i])
  834. cdm_active |= BIT(cfg->cdm[i] - CDM_0);
  835. }
  836. if (cfg->intf_mode_sel == SDE_CTL_MODE_SEL_CMD)
  837. mode_sel |= BIT(17);
  838. SDE_REG_WRITE(c, CTL_TOP, mode_sel);
  839. SDE_REG_WRITE(c, CTL_WB_ACTIVE, wb_active);
  840. SDE_REG_WRITE(c, CTL_CWB_ACTIVE, cwb_active);
  841. SDE_REG_WRITE(c, CTL_INTF_ACTIVE, intf_active);
  842. SDE_REG_WRITE(c, CTL_CDM_ACTIVE, cdm_active);
  843. SDE_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, merge_3d_active);
  844. SDE_REG_WRITE(c, CTL_INTF_MASTER, intf_master);
  845. return 0;
  846. }
  847. static int sde_hw_ctl_reset_post_disable(struct sde_hw_ctl *ctx,
  848. struct sde_hw_intf_cfg_v1 *cfg, u32 merge_3d_idx)
  849. {
  850. struct sde_hw_blk_reg_map *c;
  851. u32 intf_active = 0, wb_active = 0, merge_3d_active = 0;
  852. u32 intf_flush = 0, wb_flush = 0;
  853. u32 i;
  854. if (!ctx || !cfg) {
  855. SDE_ERROR("invalid hw_ctl or hw_intf blk\n");
  856. return -EINVAL;
  857. }
  858. c = &ctx->hw;
  859. for (i = 0; i < cfg->intf_count; i++) {
  860. if (cfg->intf[i]) {
  861. intf_active &= ~BIT(cfg->intf[i] - INTF_0);
  862. intf_flush |= BIT(cfg->intf[i] - INTF_0);
  863. }
  864. }
  865. for (i = 0; i < cfg->wb_count; i++) {
  866. if (cfg->wb[i]) {
  867. wb_active &= ~BIT(cfg->wb[i] - WB_0);
  868. wb_flush |= BIT(cfg->wb[i] - WB_0);
  869. }
  870. }
  871. for (i = 0; i < cfg->dnsc_blur_count; i++) {
  872. if (cfg->dnsc_blur[i]) {
  873. wb_active &= ~BIT(DNSC_BLUR_IDX(cfg->dnsc_blur[i] - DNSC_BLUR_0));
  874. wb_flush |= BIT(DNSC_BLUR_IDX(cfg->dnsc_blur[i] - DNSC_BLUR_0));
  875. }
  876. }
  877. if (merge_3d_idx) {
  878. /* disable and flush merge3d_blk */
  879. merge_3d_active &= ~BIT(merge_3d_idx - MERGE_3D_0);
  880. ctx->flush.pending_hw_flush_mask[SDE_HW_FLUSH_MERGE_3D] =
  881. BIT(merge_3d_idx - MERGE_3D_0);
  882. UPDATE_MASK(ctx->flush.pending_flush_mask, MERGE_3D_IDX, 1);
  883. SDE_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, merge_3d_active);
  884. }
  885. sde_hw_ctl_clear_all_blendstages(ctx);
  886. if (cfg->intf_count) {
  887. ctx->flush.pending_hw_flush_mask[SDE_HW_FLUSH_INTF] =
  888. intf_flush;
  889. UPDATE_MASK(ctx->flush.pending_flush_mask, INTF_IDX, 1);
  890. SDE_REG_WRITE(c, CTL_INTF_ACTIVE, intf_active);
  891. }
  892. if (cfg->wb_count) {
  893. ctx->flush.pending_hw_flush_mask[SDE_HW_FLUSH_WB] = wb_flush;
  894. UPDATE_MASK(ctx->flush.pending_flush_mask, WB_IDX, 1);
  895. SDE_REG_WRITE(c, CTL_WB_ACTIVE, wb_active);
  896. }
  897. return 0;
  898. }
  899. static int sde_hw_ctl_update_intf_cfg(struct sde_hw_ctl *ctx,
  900. struct sde_hw_intf_cfg_v1 *cfg, bool enable)
  901. {
  902. int i;
  903. u32 cwb_active = 0;
  904. u32 merge_3d_active = 0;
  905. u32 wb_active = 0;
  906. u32 dsc_active = 0;
  907. u32 vdc_active = 0;
  908. struct sde_hw_blk_reg_map *c;
  909. if (!ctx)
  910. return -EINVAL;
  911. c = &ctx->hw;
  912. if (cfg->cwb_count) {
  913. cwb_active = SDE_REG_READ(c, CTL_CWB_ACTIVE);
  914. for (i = 0; i < cfg->cwb_count; i++) {
  915. if (cfg->cwb[i])
  916. UPDATE_ACTIVE(cwb_active,
  917. (cfg->cwb[i] - CWB_0),
  918. enable);
  919. }
  920. for (i = 0; i < cfg->wb_count; i++) {
  921. if (cfg->wb[i] && enable)
  922. wb_active |= BIT(cfg->wb[i] - WB_0);
  923. }
  924. SDE_REG_WRITE(c, CTL_CWB_ACTIVE, cwb_active);
  925. SDE_REG_WRITE(c, CTL_WB_ACTIVE, wb_active);
  926. }
  927. if (cfg->dnsc_blur_count) {
  928. wb_active = SDE_REG_READ(c, CTL_WB_ACTIVE);
  929. for (i = 0; i < cfg->dnsc_blur_count; i++) {
  930. if (cfg->dnsc_blur[i])
  931. UPDATE_ACTIVE(wb_active,
  932. DNSC_BLUR_IDX(cfg->dnsc_blur[i] - DNSC_BLUR_0),
  933. enable);
  934. }
  935. SDE_REG_WRITE(c, CTL_WB_ACTIVE, wb_active);
  936. }
  937. if (cfg->merge_3d_count) {
  938. merge_3d_active = SDE_REG_READ(c, CTL_MERGE_3D_ACTIVE);
  939. for (i = 0; i < cfg->merge_3d_count; i++) {
  940. if (cfg->merge_3d[i])
  941. UPDATE_ACTIVE(merge_3d_active,
  942. (cfg->merge_3d[i] - MERGE_3D_0),
  943. enable);
  944. }
  945. SDE_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, merge_3d_active);
  946. }
  947. if (cfg->dsc_count) {
  948. dsc_active = SDE_REG_READ(c, CTL_DSC_ACTIVE);
  949. for (i = 0; i < cfg->dsc_count; i++) {
  950. if (cfg->dsc[i])
  951. UPDATE_ACTIVE(dsc_active,
  952. (cfg->dsc[i] - DSC_0), enable);
  953. }
  954. SDE_REG_WRITE(c, CTL_DSC_ACTIVE, dsc_active);
  955. }
  956. if (cfg->vdc_count) {
  957. vdc_active = SDE_REG_READ(c, CTL_DSC_ACTIVE);
  958. for (i = 0; i < cfg->vdc_count; i++) {
  959. if (cfg->vdc[i])
  960. UPDATE_ACTIVE(vdc_active,
  961. VDC_IDX(cfg->vdc[i] - VDC_0), enable);
  962. }
  963. SDE_REG_WRITE(c, CTL_DSC_ACTIVE, vdc_active);
  964. }
  965. return 0;
  966. }
  967. static int sde_hw_ctl_intf_cfg(struct sde_hw_ctl *ctx,
  968. struct sde_hw_intf_cfg *cfg)
  969. {
  970. struct sde_hw_blk_reg_map *c;
  971. u32 intf_cfg = 0;
  972. if (!ctx)
  973. return -EINVAL;
  974. c = &ctx->hw;
  975. intf_cfg |= (cfg->intf & 0xF) << 4;
  976. if (cfg->wb)
  977. intf_cfg |= (cfg->wb & 0x3) + 2;
  978. if (cfg->mode_3d) {
  979. intf_cfg |= BIT(19);
  980. intf_cfg |= (cfg->mode_3d - 0x1) << 20;
  981. }
  982. switch (cfg->intf_mode_sel) {
  983. case SDE_CTL_MODE_SEL_VID:
  984. intf_cfg &= ~BIT(17);
  985. intf_cfg &= ~(0x3 << 15);
  986. break;
  987. case SDE_CTL_MODE_SEL_CMD:
  988. intf_cfg |= BIT(17);
  989. intf_cfg |= ((cfg->stream_sel & 0x3) << 15);
  990. break;
  991. default:
  992. pr_err("unknown interface type %d\n", cfg->intf_mode_sel);
  993. return -EINVAL;
  994. }
  995. SDE_REG_WRITE(c, CTL_TOP, intf_cfg);
  996. return 0;
  997. }
  998. static void sde_hw_ctl_update_wb_cfg(struct sde_hw_ctl *ctx,
  999. struct sde_hw_intf_cfg *cfg, bool enable)
  1000. {
  1001. struct sde_hw_blk_reg_map *c = &ctx->hw;
  1002. u32 intf_cfg = 0;
  1003. if (!cfg->wb)
  1004. return;
  1005. intf_cfg = SDE_REG_READ(c, CTL_TOP);
  1006. if (enable)
  1007. intf_cfg |= (cfg->wb & 0x3) + 2;
  1008. else
  1009. intf_cfg &= ~((cfg->wb & 0x3) + 2);
  1010. SDE_REG_WRITE(c, CTL_TOP, intf_cfg);
  1011. }
  1012. static inline u32 sde_hw_ctl_read_ctl_layers(struct sde_hw_ctl *ctx, int index)
  1013. {
  1014. struct sde_hw_blk_reg_map *c;
  1015. u32 ctl_top;
  1016. if (!ctx) {
  1017. pr_err("Invalid input argument\n");
  1018. return 0;
  1019. }
  1020. c = &ctx->hw;
  1021. ctl_top = SDE_REG_READ(c, CTL_LAYER(index));
  1022. pr_debug("Ctl_layer value = 0x%x\n", ctl_top);
  1023. return ctl_top;
  1024. }
  1025. static inline bool sde_hw_ctl_read_active_status(struct sde_hw_ctl *ctx,
  1026. enum sde_hw_blk_type blk, int index)
  1027. {
  1028. struct sde_hw_blk_reg_map *c;
  1029. if (!ctx) {
  1030. pr_err("Invalid input argument\n");
  1031. return 0;
  1032. }
  1033. c = &ctx->hw;
  1034. switch (blk) {
  1035. case SDE_HW_BLK_MERGE_3D:
  1036. return (SDE_REG_READ(c, CTL_MERGE_3D_ACTIVE) &
  1037. BIT(index - MERGE_3D_0)) ? true : false;
  1038. case SDE_HW_BLK_DSC:
  1039. return (SDE_REG_READ(c, CTL_DSC_ACTIVE) &
  1040. BIT(index - DSC_0)) ? true : false;
  1041. case SDE_HW_BLK_WB:
  1042. return (SDE_REG_READ(c, CTL_WB_ACTIVE) &
  1043. BIT(index - WB_0)) ? true : false;
  1044. case SDE_HW_BLK_CDM:
  1045. return (SDE_REG_READ(c, CTL_CDM_ACTIVE) &
  1046. BIT(index - CDM_0)) ? true : false;
  1047. case SDE_HW_BLK_INTF:
  1048. return (SDE_REG_READ(c, CTL_INTF_ACTIVE) &
  1049. BIT(index - INTF_0)) ? true : false;
  1050. default:
  1051. pr_err("unsupported blk %d\n", blk);
  1052. return false;
  1053. };
  1054. return false;
  1055. }
  1056. static int sde_hw_reg_dma_flush(struct sde_hw_ctl *ctx, bool blocking)
  1057. {
  1058. struct sde_hw_reg_dma_ops *ops = sde_reg_dma_get_ops();
  1059. if (!ctx)
  1060. return -EINVAL;
  1061. if (ops && ops->last_command)
  1062. return ops->last_command(ctx, DMA_CTL_QUEUE0,
  1063. (blocking ? REG_DMA_WAIT4_COMP : REG_DMA_NOWAIT));
  1064. return 0;
  1065. }
  1066. static void _setup_ctl_ops(struct sde_hw_ctl_ops *ops,
  1067. unsigned long cap)
  1068. {
  1069. if (cap & BIT(SDE_CTL_ACTIVE_CFG)) {
  1070. ops->update_pending_flush =
  1071. sde_hw_ctl_update_pending_flush_v1;
  1072. ops->trigger_flush = sde_hw_ctl_trigger_flush_v1;
  1073. ops->setup_intf_cfg_v1 = sde_hw_ctl_intf_cfg_v1;
  1074. ops->update_intf_cfg = sde_hw_ctl_update_intf_cfg;
  1075. ops->update_bitmask = sde_hw_ctl_update_bitmask_v1;
  1076. ops->update_dnsc_blur_bitmask = sde_hw_ctl_update_dnsc_blur_bitmask;
  1077. ops->get_ctl_intf = sde_hw_ctl_get_intf_v1;
  1078. ops->reset_post_disable = sde_hw_ctl_reset_post_disable;
  1079. ops->get_scheduler_status = sde_hw_ctl_get_scheduler_status;
  1080. ops->read_active_status = sde_hw_ctl_read_active_status;
  1081. ops->set_active_pipes = sde_hw_ctl_set_fetch_pipe_active;
  1082. ops->get_active_pipes = sde_hw_ctl_get_active_fetch_pipes;
  1083. } else {
  1084. ops->update_pending_flush = sde_hw_ctl_update_pending_flush;
  1085. ops->trigger_flush = sde_hw_ctl_trigger_flush;
  1086. ops->setup_intf_cfg = sde_hw_ctl_intf_cfg;
  1087. ops->update_bitmask = sde_hw_ctl_update_bitmask;
  1088. ops->get_ctl_intf = sde_hw_ctl_get_intf;
  1089. }
  1090. ops->clear_pending_flush = sde_hw_ctl_clear_pending_flush;
  1091. ops->get_pending_flush = sde_hw_ctl_get_pending_flush;
  1092. ops->get_flush_register = sde_hw_ctl_get_flush_register;
  1093. ops->trigger_start = sde_hw_ctl_trigger_start;
  1094. ops->trigger_pending = sde_hw_ctl_trigger_pending;
  1095. ops->read_ctl_layers = sde_hw_ctl_read_ctl_layers;
  1096. ops->update_wb_cfg = sde_hw_ctl_update_wb_cfg;
  1097. ops->reset = sde_hw_ctl_reset_control;
  1098. ops->get_reset = sde_hw_ctl_get_reset_status;
  1099. ops->hard_reset = sde_hw_ctl_hard_reset;
  1100. ops->wait_reset_status = sde_hw_ctl_wait_reset_status;
  1101. ops->clear_all_blendstages = sde_hw_ctl_clear_all_blendstages;
  1102. ops->setup_blendstage = sde_hw_ctl_setup_blendstage;
  1103. ops->get_staged_sspp = sde_hw_ctl_get_staged_sspp;
  1104. ops->update_bitmask_sspp = sde_hw_ctl_update_bitmask_sspp;
  1105. ops->update_bitmask_mixer = sde_hw_ctl_update_bitmask_mixer;
  1106. ops->reg_dma_flush = sde_hw_reg_dma_flush;
  1107. ops->get_start_state = sde_hw_ctl_get_start_state;
  1108. if (cap & BIT(SDE_CTL_UNIFIED_DSPP_FLUSH)) {
  1109. ops->update_bitmask_dspp_subblk =
  1110. sde_hw_ctl_update_bitmask_dspp_subblk;
  1111. } else {
  1112. ops->update_bitmask_dspp = sde_hw_ctl_update_bitmask_dspp;
  1113. ops->update_bitmask_dspp_pavlut =
  1114. sde_hw_ctl_update_bitmask_dspp_pavlut;
  1115. }
  1116. if (cap & BIT(SDE_CTL_UIDLE))
  1117. ops->uidle_enable = sde_hw_ctl_uidle_enable;
  1118. };
  1119. struct sde_hw_blk_reg_map *sde_hw_ctl_init(enum sde_ctl idx,
  1120. void __iomem *addr,
  1121. struct sde_mdss_cfg *m)
  1122. {
  1123. struct sde_hw_ctl *c;
  1124. struct sde_ctl_cfg *cfg;
  1125. c = kzalloc(sizeof(*c), GFP_KERNEL);
  1126. if (!c)
  1127. return ERR_PTR(-ENOMEM);
  1128. cfg = _ctl_offset(idx, m, addr, &c->hw);
  1129. if (IS_ERR_OR_NULL(cfg)) {
  1130. kfree(c);
  1131. pr_err("failed to create sde_hw_ctl %d\n", idx);
  1132. return ERR_PTR(-EINVAL);
  1133. }
  1134. c->caps = cfg;
  1135. _setup_ctl_ops(&c->ops, c->caps->features);
  1136. c->idx = idx;
  1137. c->mixer_count = m->mixer_count;
  1138. c->mixer_hw_caps = m->mixer;
  1139. sde_dbg_reg_register_dump_range(SDE_DBG_NAME, cfg->name, c->hw.blk_off,
  1140. c->hw.blk_off + c->hw.length, c->hw.xin_id);
  1141. return &c->hw;
  1142. }
  1143. void sde_hw_ctl_destroy(struct sde_hw_blk_reg_map *hw)
  1144. {
  1145. if (hw)
  1146. kfree(to_sde_hw_ctl(hw));
  1147. }