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swr-mstr-registers.h

swr-mstr-registers.h 7.3 KB
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  1. /* SPDX-License-Identifier: GPL-2.0-only */
    2. 

  2. /*
    3. 

  3.  * Copyright (c) 2015, 2018-2021 The Linux Foundation. All rights reserved.
    4. 

  4.  */
    5. 

  5. 

  6. #ifndef _SWRM_REGISTERS_H
    7. 

  7. #define _SWRM_REGISTERS_H
    8. 

  8. 

  9. #define SWRM_BASE                                 0x00
    10. 

  10. #define SWRM_COMP_HW_VERSION                      (SWRM_BASE+0x0000)
    11. 

  11. #define SWRM_COMP_CFG                             (SWRM_BASE+0x0004)
    12. 

  12. #define SWRM_COMP_SW_RESET                        (SWRM_BASE+0x0008)
    13. 

  13. #define SWRM_COMP_POWER_CFG                       (SWRM_BASE+0x000C)
    14. 

  14. #define SWRM_COMP_FEATURE_CFG                     (SWRM_BASE+0x0010)
    15. 

  15. #define SWRM_COMP_STATUS                          (SWRM_BASE+0x0014)
    16. 

  16. #define SWRM_LINK_MANAGER_EE                      (SWRM_BASE+0x0018)
    17. 

  17. #define SWRM_COMP_PARAMS                          (SWRM_BASE+0x0100)
    18. 

  18. #define SWRM_COMP_MASTER_ID                       (SWRM_BASE+0x0104)
    19. 

  19. #define MM_SYNC_CONFIG                            (SWRM_BASE+0x0108)
    20. 

  20. #define SWRM_COMP_NPL_PARAMS                      (SWRM_BASE+0x0120)
    21. 

  21. #define SWRM_INTERRUPT_STATUS                     (SWRM_BASE+0x0200)
    22. 

  22. #define SWRM_INTERRUPT_CLEAR                      (SWRM_BASE+0x0208)
    23. 

  23. #define SWRM_INTERRUPT_STATUS_1                   (SWRM_BASE+0x0220)
    24. 

  24. #define SWRM_INTERRUPT_CLEAR_1                    (SWRM_BASE+0x0228)
    25. 

  25. #define SWRM_CPU1_INTERRUPT_EN                    (SWRM_BASE+0x0210)
    26. 

  26. #define SWRM_CPU1_INTERRUPT_EN_1                  (SWRM_BASE+0x0230)
    27. 

  27. #define SWRM_CPU0_CMD_RESPONSE                    (SWRM_BASE+0x0250)
    28. 

  28. 

  29. #define SWRM_CPU1_CMD_FIFO_WR_CMD                 (SWRM_BASE+0x031C)
    30. 

  30. #define SWRM_CPU1_CMD_FIFO_RD_CMD                 (SWRM_BASE+0x0320)
    31. 

  31. #define SWRM_CPU1_CMD_FIFO_STATUS                 (SWRM_BASE+0x0328)
    32. 

  32. #define SWRM_CPU1_CMD_FIFO_RD_FIFO                (SWRM_BASE+0x0334)
    33. 

  33. 

  34. #ifdef CONFIG_SWRM_VER_1P7
    35. 

  35. #define SWRM_INTERRUPT_EN                    SWRM_CPU1_INTERRUPT_EN
    36. 

  36. #define SWRM_INTERRUPT_EN_1                  SWRM_CPU1_INTERRUPT_EN_1
    37. 

  37. #define SWRM_CMD_FIFO_WR_CMD                 SWRM_CPU1_CMD_FIFO_WR_CMD
    38. 

  38. #define SWRM_CMD_FIFO_RD_CMD                 SWRM_CPU1_CMD_FIFO_RD_CMD
    39. 

  39. #define SWRM_CMD_FIFO_STATUS                 SWRM_CPU1_CMD_FIFO_STATUS
    40. 

  40. #define SWRM_CMD_FIFO_RD_FIFO                SWRM_CPU1_CMD_FIFO_RD_FIFO
    41. 

  41. #else
    42. 

  42. #define SWRM_INTERRUPT_EN                         (SWRM_BASE+0x0204)
    43. 

  43. #define SWRM_INTERRUPT_EN_1                       (SWRM_BASE+0x0224)
    44. 

  44. #define SWRM_CMD_FIFO_WR_CMD                      (SWRM_BASE+0x0300)
    45. 

  45. #define SWRM_CMD_FIFO_RD_CMD                      (SWRM_BASE+0x0304)
    46. 

  46. #define SWRM_CMD_FIFO_STATUS                      (SWRM_BASE+0x030C)
    47. 

  47. #define SWRM_CMD_FIFO_RD_FIFO                     (SWRM_BASE+0x0318)
    48. 

  48. #endif /* CONFIG_SWRM_VER_1P7 */
    49. 

  49. 

  50. #define SWRM_CMD_FIFO_CMD                         (SWRM_BASE+0x0308)
    51. 

  51. #define SWRM_CMD_FIFO_CFG                         (SWRM_BASE+0x0314)
    52. 

  52. #define SWRM_CPU_NUM_ENTRIES_WR_CMD_FIFO          (SWRM_BASE+0x0370)
    53. 

  53. #define SWRM_CPU0_SW_INTERRUPT_SET                (SWRM_BASE+0x0374)
    54. 

  54. #define SWRM_CPU0_SW_MESSAGE0                     (SWRM_BASE+0x0384)
    55. 

  55. #define SWRM_CPU0_SW_MESSAGE1                     (SWRM_BASE+0x0394)
    56. 

  56. #define SWRM_ENUMERATOR_CFG                       (SWRM_BASE+0x0500)
    57. 

  57. #define SWRM_ENUMERATOR_STATUS                    (SWRM_BASE+0x0504)
    58. 

  58. #define SWRM_ENUMERATOR_PRE_ENUM_CFG              (SWRM_BASE+0x0530)
    59. 

  59. #define SWRM_ENUMERATOR_SLAVE_DEV_ID_1(m)         (SWRM_BASE+0x0530+0x8*m)
    60. 

  60. #define SWRM_ENUMERATOR_SLAVE_DEV_ID_2(m)         (SWRM_BASE+0x0534+0x8*m)
    61. 

  61. #define SWRM_CTRL_W_GEN_STATUS                    (SWRM_BASE+0x0600)
    62. 

  62. #define SWRM_SW_RESET_STATUS                      (SWRM_BASE+0x0700)
    63. 

  63. #define SWRM_FORCE_BANK_SWITCH_SUCCESS            (SWRM_BASE+0x0704)
    64. 

  64. #define SWRM_SILENCE_TONE_REPEAT_VALUE_THRESHOLD  (SWRM_BASE+0x0710)
    65. 

  65. #define SWRM_SELF_GENERATE_FRAME_SYNC             (SWRM_BASE+0x0714)
    66. 

  66. #define SWRM_MCP_FRAME_CTRL_BANK(m)               (SWRM_BASE+0x101C+0x40*m)
    67. 

  67. #define SWRM_MCP_BUS_CTRL                         (SWRM_BASE+0x1044)
    68. 

  68. #define SWRM_MCP_CFG                              (SWRM_BASE+0x1048)
    69. 

  69. #define SWRM_MCP_STATUS                           (SWRM_BASE+0x104C)
    70. 

  70. #define SWRM_MCP_SLV_STATUS                       (SWRM_BASE+0x1090)
    71. 

  71. 

  72. #define SWRM_DIN_DP_INT_STATUS(n)         (SWRM_BASE+0x1000+0x100*n)
    73. 

  73. #define SWRM_DIN_DP_INT_CLEAR(n)          (SWRM_BASE+0x1008+0x100*n)
    74. 

  74. 

  75. #define SWRM_DP_PORT_CONTROL(n)           (SWRM_BASE+0x1020+0x100*n)
    76. 

  76. #define SWRM_DP_PORT_CTRL_BANK(n, m)      (SWRM_BASE+0x1024+0x100*n+0x40*m)
    77. 

  77. #define SWRM_DP_PORT_CTRL_2_BANK(n, m)    (SWRM_BASE+0x1028+0x100*n+0x40*m)
    78. 

  78. #define SWRM_DP_BLOCK_CTRL_1(n)           (SWRM_BASE+0x102C+0x100*n)
    79. 

  79. #define SWRM_DP_BLOCK_CTRL2_BANK(n, m)    (SWRM_BASE+0x1030+0x100*n+0x40*m)
    80. 

  80. #define SWRM_DP_PORT_HCTRL_BANK(n, m)     (SWRM_BASE+0x1034+0x100*n+0x40*m)
    81. 

  81. #define SWRM_DP_BLOCK_CTRL3_BANK(n, m)    (SWRM_BASE+0x1038+0x100*n+0x40*m)
    82. 

  82. #define SWRM_DP_SAMPLECTRL2_BANK(n, m)    (SWRM_BASE+0x103C+0x100*n+0x40*m)
    83. 

  83. 

  84. #define SWRM_DIN_DP_FEATURES_EN(n)        (SWRM_BASE+0x104C+0x100*n)
    85. 

  85. #define SWRM_DIN_DP_PCM_PORT_CTRL(n)      (SWRM_BASE+0x1054+0x100*n)
    86. 

  86. 

  87. #define SWRM_DOUT_DP_INT_STATUS(n)          (SWRM_BASE+0x1000+0x100*n)
    88. 

  88. #define SWRM_DOUT_DP_INT_CLEAR(n)           (SWRM_BASE+0x1008+0x100*n)
    89. 

  89. #define SWRM_DOUT_DP_FEATURES_EN(n)         (SWRM_BASE+0x104C+0x100*n)
    90. 

  90. #define SWRM_DOUT_DP_SILENCE_TONE_CFG(n)    (SWRM_BASE+0x1050+0x100*n)
    91. 

  91. #define SWRM_DOUT_DP_PCM_PORT_CTRL(n)       (SWRM_BASE+0x1054+0x100*n)
    92. 

  92. #define SWRM_MAX_REGISTER SWRM_DIN_DP_PCM_PORT_CTRL(9)
    93. 

  93. 

  94. #define SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ                    0x1
    95. 

  95. #define SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED                0x2
    96. 

  96. #define SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS          0x4
    97. 

  97. #define SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET                  0x8
    98. 

  98. #define SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW                  0x10
    99. 

  99. #define SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW                 0x20
    100. 

  100. #define SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW              0x40
    101. 

  101. #define SWRM_INTERRUPT_STATUS_CMD_ERROR                         0x80
    102. 

  102. #define SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION               0x100
    103. 

  103. #define SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH         0x200
    104. 

  104. #define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED           0x400
    105. 

  105. 

  106. #ifdef CONFIG_SWRM_VER_1P1
    107. 

  107. #define SWRM_INTERRUPT_STATUS_NEW_SLAVE_AUTO_ENUM_FINISHED   0x800
    108. 

  108. #define SWRM_INTERRUPT_STATUS_AUTO_ENUM_FAILED               0x1000
    109. 

  109. #define SWRM_INTERRUPT_STATUS_AUTO_ENUM_TABLE_IS_FULL        0x2000
    110. 

  110. #define SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED             0x4000
    111. 

  111. #define SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED              0x8000
    112. 

  112. #define SWRM_INTERRUPT_STATUS_ERROR_PORT_TEST                0x10000
    113. 

  113. #else
    114. 

  114. #define SWRM_INTERRUPT_STATUS_AUTO_ENUM_FAILED               0x800
    115. 

  115. #define SWRM_INTERRUPT_STATUS_AUTO_ENUM_TABLE_IS_FULL        0x1000
    116. 

  116. #define SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED             0x2000
    117. 

  117. #define SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED              0x4000
    118. 

  118. #define SWRM_INTERRUPT_STATUS_ERROR_PORT_TEST                0x8000
    119. 

  119. #endif /* CONFIG_SWRM_VER_1P1 */
    120. 

  120. 

  121. #define SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP            0x10000
    122. 

  122. 

  123. #define SWRM_INTERRUPT_MAX    0x11
    124. 

  124. 

  125. #define SWRM_COMP_PARAMS_WR_FIFO_DEPTH		0x00007C00
    126. 

  126. #define SWRM_COMP_PARAMS_RD_FIFO_DEPTH		0x000F8000
    127. 

  127. 

  128. #define SWRM_COMP_FEATURE_CFG_DEFAULT_VAL	0x06
    129. 

  129. #define SWRM_COMP_FEATURE_CFG_DEFAULT_VAL_V1P7	0x406
    130. 

  130. #define SWRM_COMP_FEATURE_CFG_PCM_EN_MASK	0x18
    131. 

  131. 

  132. #define SWRM_COMP_PARAMS_AUTO_ENUM_SLAVES	0x00F00000
    133. 

  133. #endif /* _SWRM_REGISTERS_H */
    134.