1741a5b55c
when SSR is releasing core and some clients voting for bus. Change-Id: I8575d747c17f234bbce216c346843ab07ea6b340 Signed-off-by: George Shen <quic_sqiao@quicinc.com>
344 строки
8.7 KiB
C
344 строки
8.7 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only
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*
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* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
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*/
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#include "msm_cvp.h"
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#include "cvp_power.h"
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static inline int find_max(unsigned long *array, unsigned int num)
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{
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int i, max = 0;
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for (i = 0; i < num; i++)
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max = array[i] > max ? array[i] : max;
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return max;
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}
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static bool is_subblock_profile_existed(struct msm_cvp_inst *inst)
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{
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return (inst->prop.cycles[HFI_HW_OD] ||
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inst->prop.cycles[HFI_HW_MPU] ||
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inst->prop.cycles[HFI_HW_FDU] ||
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inst->prop.cycles[HFI_HW_ICA] ||
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inst->prop.cycles[HFI_HW_VADL] ||
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inst->prop.cycles[HFI_HW_TOF] ||
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inst->prop.cycles[HFI_HW_RGE] ||
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inst->prop.cycles[HFI_HW_XRA] ||
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inst->prop.cycles[HFI_HW_LSR]);
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}
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static char hw_names[HFI_MAX_HW_THREADS][8] = {{"FDU"}, {"OD"}, {"MPU"}, {"ICA"},
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{"VADL"}, {"TOF"}, {"RGE"}, {"XRA"},
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{"LSR"}};
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static void aggregate_power_update(struct msm_cvp_core *core,
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struct cvp_power_level *nrt_pwr,
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struct cvp_power_level *rt_pwr,
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unsigned int max_clk_rate)
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{
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struct msm_cvp_inst *inst;
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int i, j;
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unsigned long blocks_sum[2][HFI_MAX_HW_THREADS] = {0};
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unsigned long fw_sum[2] = {0}, max_cycle[2] = {0}, op_max_cycle[2] = {0};
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unsigned long op_blocks_max[2][HFI_MAX_HW_THREADS] = {0};
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unsigned long op_fw_max[2] = {0}, bw_sum[2] = {0}, op_bw_max[2] = {0};
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list_for_each_entry(inst, &core->instances, list) {
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if (inst->state == MSM_CVP_CORE_INVALID ||
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inst->state == MSM_CVP_CORE_UNINIT ||
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!is_subblock_profile_existed(inst))
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continue;
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if (inst->prop.priority <= CVP_RT_PRIO_THRESHOLD) {
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/* Non-realtime session use index 0 */
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i = 0;
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} else {
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i = 1;
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}
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for (j = 0; j < HFI_MAX_HW_THREADS; j++)
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if (inst->prop.cycles[j])
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dprintk(CVP_PWR, "pwrUpdate %s %u\n",
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hw_names[j], inst->prop.cycles[j]);
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for (j = 0; j < HFI_MAX_HW_THREADS; j++)
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if (inst->prop.op_cycles[j])
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dprintk(CVP_PWR, "pwrUpdate_OP %s %u\n",
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hw_names[j], inst->prop.op_cycles[j]);
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dprintk(CVP_PWR, " fw %u fw_o %u\n", inst->prop.fw_cycles,
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inst->prop.fw_op_cycles);
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for (j = 0; j < HFI_MAX_HW_THREADS; j++)
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blocks_sum[i][j] += inst->prop.cycles[j];
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fw_sum[i] += inst->prop.fw_cycles;
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for (j = 0; j < HFI_MAX_HW_THREADS; j++)
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op_blocks_max[i][j] =
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(op_blocks_max[i][j] >= inst->prop.op_cycles[j]) ?
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op_blocks_max[i][j] : inst->prop.op_cycles[j];
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op_fw_max[i] =
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(op_fw_max[i] >= inst->prop.fw_op_cycles) ?
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op_fw_max[i] : inst->prop.fw_op_cycles;
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bw_sum[i] += inst->prop.ddr_bw;
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op_bw_max[i] =
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(op_bw_max[i] >= inst->prop.ddr_op_bw) ?
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op_bw_max[i] : inst->prop.ddr_op_bw;
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for (j = 0; j < HFI_MAX_HW_THREADS; j++) {
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if (inst->prop.fps[j])
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dprintk(CVP_PWR, "fps %s %d ", hw_names[j],
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inst->prop.fps[j]);
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}
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}
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for (i = 0; i < 2; i++) {
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max_cycle[i] = find_max(&blocks_sum[i][0], HFI_MAX_HW_THREADS);
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op_max_cycle[i] = find_max(&op_blocks_max[i][0], HFI_MAX_HW_THREADS);
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op_max_cycle[i] =
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(op_max_cycle[i] > max_clk_rate) ?
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max_clk_rate : op_max_cycle[i];
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bw_sum[i] = (bw_sum[i] >= op_bw_max[i]) ?
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bw_sum[i] : op_bw_max[i];
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}
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nrt_pwr->core_sum += max_cycle[0];
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nrt_pwr->op_core_sum = (nrt_pwr->op_core_sum >= op_max_cycle[0]) ?
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nrt_pwr->op_core_sum : op_max_cycle[0];
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nrt_pwr->bw_sum += bw_sum[0];
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rt_pwr->core_sum += max_cycle[1];
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rt_pwr->op_core_sum = (rt_pwr->op_core_sum >= op_max_cycle[1]) ?
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rt_pwr->op_core_sum : op_max_cycle[1];
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rt_pwr->bw_sum += bw_sum[1];
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}
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/**
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* adjust_bw_freqs(): calculate CVP clock freq and bw required to sustain
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* required use case.
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* Bandwidth vote will be best-effort, not returning error if the request
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* b/w exceeds max limit.
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* Clock vote from non-realtime sessions will be best effort, not returning
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* error if the aggreated session clock request exceeds max limit.
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* Clock vote from realtime session will be hard request. If aggregated
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* session clock request exceeds max limit, the function will return
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* error.
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*
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* Ensure caller acquires clk_lock!
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*/
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static int adjust_bw_freqs(unsigned int max_bw, unsigned int min_bw)
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{
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struct msm_cvp_core *core;
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struct iris_hfi_device *hdev;
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struct allowed_clock_rates_table *tbl = NULL;
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unsigned int tbl_size;
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unsigned int cvp_min_rate, cvp_max_rate;
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struct cvp_power_level rt_pwr = {0}, nrt_pwr = {0};
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unsigned long tmp, core_sum, op_core_sum, bw_sum;
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int i;
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core = cvp_driver->cvp_core;
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hdev = core->device->hfi_device_data;
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tbl = core->resources.allowed_clks_tbl;
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tbl_size = core->resources.allowed_clks_tbl_size;
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cvp_min_rate = tbl[0].clock_rate;
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cvp_max_rate = tbl[tbl_size - 1].clock_rate;
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aggregate_power_update(core, &nrt_pwr, &rt_pwr, cvp_max_rate);
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dprintk(CVP_PWR, "PwrUpdate nrt %u %u rt %u %u\n",
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nrt_pwr.core_sum, nrt_pwr.op_core_sum,
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rt_pwr.core_sum, rt_pwr.op_core_sum);
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if (rt_pwr.core_sum > cvp_max_rate) {
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dprintk(CVP_WARN, "%s clk vote out of range %lld\n",
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__func__, rt_pwr.core_sum);
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return -ENOTSUPP;
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}
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core_sum = rt_pwr.core_sum + nrt_pwr.core_sum;
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op_core_sum = (rt_pwr.op_core_sum >= nrt_pwr.op_core_sum) ?
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rt_pwr.op_core_sum : nrt_pwr.op_core_sum;
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core_sum = (core_sum >= op_core_sum) ?
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core_sum : op_core_sum;
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if (core_sum > cvp_max_rate) {
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core_sum = cvp_max_rate;
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} else if (core_sum <= cvp_min_rate) {
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core_sum = cvp_min_rate;
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} else {
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for (i = 1; i < tbl_size; i++)
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if (core_sum <= tbl[i].clock_rate)
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break;
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core_sum = tbl[i].clock_rate;
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}
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bw_sum = rt_pwr.bw_sum + nrt_pwr.bw_sum;
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bw_sum = bw_sum >> 10;
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bw_sum = (bw_sum > max_bw) ? max_bw : bw_sum;
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bw_sum = (bw_sum < min_bw) ? min_bw : bw_sum;
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dprintk(CVP_PWR, "%s %lld %lld\n", __func__,
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core_sum, bw_sum);
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tmp = core->curr_freq;
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core->curr_freq = core_sum;
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core->orig_core_sum = tmp;
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hdev->clk_freq = core->curr_freq;
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core->bw_sum = bw_sum;
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return 0;
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}
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int msm_cvp_update_power(struct msm_cvp_inst *inst)
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{
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int rc = 0;
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struct msm_cvp_core *core;
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struct msm_cvp_inst *s;
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struct bus_info *bus = NULL;
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struct clock_set *clocks;
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struct clock_info *cl;
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int bus_count = 0;
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unsigned int max_bw = 0, min_bw = 0;
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if (!inst) {
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dprintk(CVP_ERR, "%s: invalid params\n", __func__);
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return -EINVAL;
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}
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s = cvp_get_inst_validate(inst->core, inst);
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if (!s)
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return -ECONNRESET;
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core = inst->core;
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if (!core || core->state == CVP_CORE_UNINIT) {
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rc = -ECONNRESET;
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goto adjust_exit;
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}
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clocks = &core->resources.clock_set;
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cl = &clocks->clock_tbl[clocks->count - 1];
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if (!cl->has_scaling) {
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dprintk(CVP_ERR, "Cannot scale CVP clock\n");
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rc = -EINVAL;
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goto adjust_exit;
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}
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for (bus_count = 0; bus_count < core->resources.bus_set.count; bus_count++) {
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if (!strcmp(core->resources.bus_set.bus_tbl[bus_count].name, "cvp-ddr")) {
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bus = &core->resources.bus_set.bus_tbl[bus_count];
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max_bw = bus->range[1];
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min_bw = max_bw/10;
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}
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}
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if (!bus) {
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dprintk(CVP_ERR, "bus node is NULL for cvp-ddr\n");
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rc = -EINVAL;
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goto adjust_exit;
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}
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mutex_lock(&core->clk_lock);
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rc = adjust_bw_freqs(max_bw, min_bw);
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mutex_unlock(&core->clk_lock);
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if (rc)
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goto adjust_exit;
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rc = msm_cvp_set_clocks(core);
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if (rc) {
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dprintk(CVP_ERR,
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"Failed to set clock rate %u %s: %d %s\n",
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core->curr_freq, cl->name, rc, __func__);
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core->curr_freq = core->orig_core_sum;
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goto adjust_exit;
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}
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rc = msm_cvp_set_bw(core, bus, core->bw_sum);
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adjust_exit:
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cvp_put_inst(s);
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return rc;
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}
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unsigned int msm_cvp_get_hw_aggregate_cycles(enum hfi_hw_thread hwblk)
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{
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struct msm_cvp_core *core;
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struct msm_cvp_inst *inst;
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unsigned long cycles_sum = 0;
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core = cvp_driver->cvp_core;
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if (!core) {
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dprintk(CVP_ERR, "%s: invalid core\n", __func__);
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return -EINVAL;
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}
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mutex_lock(&core->clk_lock);
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list_for_each_entry(inst, &core->instances, list) {
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if (inst->state == MSM_CVP_CORE_INVALID ||
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inst->state == MSM_CVP_CORE_UNINIT ||
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!is_subblock_profile_existed(inst))
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continue;
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switch (hwblk) {
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case HFI_HW_FDU:
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{
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cycles_sum += inst->prop.cycles[HFI_HW_FDU];
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break;
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}
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case HFI_HW_ICA:
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{
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cycles_sum += inst->prop.cycles[HFI_HW_ICA];
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break;
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}
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case HFI_HW_MPU:
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{
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cycles_sum += inst->prop.cycles[HFI_HW_MPU];
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break;
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}
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case HFI_HW_OD:
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{
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cycles_sum += inst->prop.cycles[HFI_HW_OD];
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break;
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}
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case HFI_HW_VADL:
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{
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cycles_sum += inst->prop.cycles[HFI_HW_VADL];
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break;
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}
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case HFI_HW_TOF:
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{
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cycles_sum += inst->prop.cycles[HFI_HW_TOF];
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break;
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}
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case HFI_HW_RGE:
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{
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cycles_sum += inst->prop.cycles[HFI_HW_RGE];
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break;
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}
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case HFI_HW_XRA:
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{
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cycles_sum += inst->prop.cycles[HFI_HW_XRA];
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break;
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}
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case HFI_HW_LSR:
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{
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cycles_sum += inst->prop.cycles[HFI_HW_LSR];
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break;
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}
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default:
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dprintk(CVP_ERR, "unrecognized hw block %d\n",
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hwblk);
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break;
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}
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}
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mutex_unlock(&core->clk_lock);
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cycles_sum = cycles_sum&0xFFFFFFFF;
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return (unsigned int)cycles_sum;
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}
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