hal_internal.h 45 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #ifndef _HAL_INTERNAL_H_
  20. #define _HAL_INTERNAL_H_
  21. #include "qdf_types.h"
  22. #include "qdf_atomic.h"
  23. #include "qdf_lock.h"
  24. #include "qdf_mem.h"
  25. #include "qdf_nbuf.h"
  26. #include "pld_common.h"
  27. #if defined(FEATURE_HAL_DELAYED_REG_WRITE)
  28. #include "qdf_defer.h"
  29. #include "qdf_timer.h"
  30. #endif
  31. #define hal_alert(params...) QDF_TRACE_FATAL(QDF_MODULE_ID_HAL, params)
  32. #define hal_err(params...) QDF_TRACE_ERROR(QDF_MODULE_ID_HAL, params)
  33. #define hal_warn(params...) QDF_TRACE_WARN(QDF_MODULE_ID_HAL, params)
  34. #define hal_info(params...) QDF_TRACE_INFO(QDF_MODULE_ID_HAL, params)
  35. #define hal_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_HAL, params)
  36. #define hal_alert_rl(params...) QDF_TRACE_FATAL_RL(QDF_MODULE_ID_HAL, params)
  37. #define hal_err_rl(params...) QDF_TRACE_ERROR_RL(QDF_MODULE_ID_HAL, params)
  38. #define hal_warn_rl(params...) QDF_TRACE_WARN_RL(QDF_MODULE_ID_HAL, params)
  39. #define hal_info_rl(params...) QDF_TRACE_INFO_RL(QDF_MODULE_ID_HAL, params)
  40. #define hal_debug_rl(params...) QDF_TRACE_DEBUG_RL(QDF_MODULE_ID_HAL, params)
  41. #ifdef ENABLE_VERBOSE_DEBUG
  42. extern bool is_hal_verbose_debug_enabled;
  43. #define hal_verbose_debug(params...) \
  44. if (unlikely(is_hal_verbose_debug_enabled)) \
  45. do {\
  46. QDF_TRACE_DEBUG(QDF_MODULE_ID_HAL, params); \
  47. } while (0)
  48. #define hal_verbose_hex_dump(params...) \
  49. if (unlikely(is_hal_verbose_debug_enabled)) \
  50. do {\
  51. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_HAL, \
  52. QDF_TRACE_LEVEL_DEBUG, \
  53. params); \
  54. } while (0)
  55. #else
  56. #define hal_verbose_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_HAL, params)
  57. #define hal_verbose_hex_dump(params...) \
  58. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_HAL, QDF_TRACE_LEVEL_DEBUG, \
  59. params)
  60. #endif
  61. /*
  62. * Given the offset of a field in bytes, returns uint8_t *
  63. */
  64. #define _OFFSET_TO_BYTE_PTR(_ptr, _off_in_bytes) \
  65. (((uint8_t *)(_ptr)) + (_off_in_bytes))
  66. /*
  67. * Given the offset of a field in bytes, returns uint32_t *
  68. */
  69. #define _OFFSET_TO_WORD_PTR(_ptr, _off_in_bytes) \
  70. (((uint32_t *)(_ptr)) + ((_off_in_bytes) >> 2))
  71. /*
  72. * Given the offset of a field in bytes, returns uint64_t *
  73. */
  74. #define _OFFSET_TO_QWORD_PTR(_ptr, _off_in_bytes) \
  75. (((uint64_t *)(_ptr)) + ((_off_in_bytes) >> 3))
  76. #define _HAL_MS(_word, _mask, _shift) \
  77. (((_word) & (_mask)) >> (_shift))
  78. /*
  79. * Get number of QWORDS possible for num.
  80. * Its the caller's duty to make sure num is a multiple of QWORD (8)
  81. */
  82. #define HAL_GET_NUM_QWORDS(num) ((num) >> 3)
  83. /*
  84. * Get number of DWORDS possible for num.
  85. * Its the caller's duty to make sure num is a multiple of DWORD (8)
  86. */
  87. #define HAL_GET_NUM_DWORDS(num) ((num) >> 2)
  88. struct hal_hw_cc_config {
  89. uint32_t lut_base_addr_31_0;
  90. uint32_t cc_global_en:1,
  91. page_4k_align:1,
  92. cookie_offset_msb:5,
  93. cookie_page_msb:5,
  94. lut_base_addr_39_32:8,
  95. wbm2sw6_cc_en:1,
  96. wbm2sw5_cc_en:1,
  97. wbm2sw4_cc_en:1,
  98. wbm2sw3_cc_en:1,
  99. wbm2sw2_cc_en:1,
  100. wbm2sw1_cc_en:1,
  101. wbm2sw0_cc_en:1,
  102. wbm2fw_cc_en:1,
  103. error_path_cookie_conv_en:1,
  104. release_path_cookie_conv_en:1,
  105. reserved:2;
  106. };
  107. /*
  108. * dp_hal_soc - opaque handle for DP HAL soc
  109. */
  110. struct hal_soc_handle;
  111. typedef struct hal_soc_handle *hal_soc_handle_t;
  112. /**
  113. * hal_ring_desc - opaque handle for DP ring descriptor
  114. */
  115. struct hal_ring_desc;
  116. typedef struct hal_ring_desc *hal_ring_desc_t;
  117. /**
  118. * hal_link_desc - opaque handle for DP link descriptor
  119. */
  120. struct hal_link_desc;
  121. typedef struct hal_link_desc *hal_link_desc_t;
  122. /**
  123. * hal_rxdma_desc - opaque handle for DP rxdma dst ring descriptor
  124. */
  125. struct hal_rxdma_desc;
  126. typedef struct hal_rxdma_desc *hal_rxdma_desc_t;
  127. /**
  128. * hal_buff_addrinfo - opaque handle for DP buffer address info
  129. */
  130. struct hal_buff_addrinfo;
  131. typedef struct hal_buff_addrinfo *hal_buff_addrinfo_t;
  132. /**
  133. * hal_rx_mon_desc_info - opaque handle for sw monitor ring desc info
  134. */
  135. struct hal_rx_mon_desc_info;
  136. typedef struct hal_rx_mon_desc_info *hal_rx_mon_desc_info_t;
  137. struct hal_buf_info;
  138. typedef struct hal_buf_info *hal_buf_info_t;
  139. struct rx_msdu_desc_info;
  140. typedef struct rx_msdu_desc_info *rx_msdu_desc_info_t;
  141. /**
  142. * Opaque hanlder for PPE VP config.
  143. */
  144. union hal_tx_ppe_vp_config;
  145. union hal_tx_cmn_config_ppe;
  146. /* TBD: This should be movded to shared HW header file */
  147. enum hal_srng_ring_id {
  148. /* UMAC rings */
  149. HAL_SRNG_REO2SW0 = 0,
  150. HAL_SRNG_REO2SW1 = 1,
  151. HAL_SRNG_REO2SW2 = 2,
  152. HAL_SRNG_REO2SW3 = 3,
  153. HAL_SRNG_REO2SW4 = 4,
  154. HAL_SRNG_REO2SW5 = 5,
  155. HAL_SRNG_REO2SW6 = 6,
  156. HAL_SRNG_REO2SW7 = 7,
  157. HAL_SRNG_REO2SW8 = 8,
  158. HAL_SRNG_REO2TCL = 9,
  159. HAL_SRNG_REO2PPE = 10,
  160. /* 11-15 unused */
  161. HAL_SRNG_SW2REO = 16,
  162. HAL_SRNG_SW2REO1 = 17,
  163. HAL_SRNG_SW2REO2 = 18,
  164. HAL_SRNG_SW2REO3 = 19,
  165. HAL_SRNG_REO_CMD = 20,
  166. HAL_SRNG_REO_STATUS = 21,
  167. /* 22-23 unused */
  168. HAL_SRNG_SW2TCL1 = 24,
  169. HAL_SRNG_SW2TCL2 = 25,
  170. HAL_SRNG_SW2TCL3 = 26,
  171. HAL_SRNG_SW2TCL4 = 27,
  172. HAL_SRNG_SW2TCL5 = 28,
  173. HAL_SRNG_SW2TCL6 = 29,
  174. HAL_SRNG_PPE2TCL1 = 30,
  175. /* 31-39 unused */
  176. HAL_SRNG_SW2TCL_CMD = 40,
  177. HAL_SRNG_TCL_STATUS = 41,
  178. HAL_SRNG_SW2TCL_CREDIT = 42,
  179. /* 43-63 unused */
  180. HAL_SRNG_CE_0_SRC = 64,
  181. HAL_SRNG_CE_1_SRC = 65,
  182. HAL_SRNG_CE_2_SRC = 66,
  183. HAL_SRNG_CE_3_SRC = 67,
  184. HAL_SRNG_CE_4_SRC = 68,
  185. HAL_SRNG_CE_5_SRC = 69,
  186. HAL_SRNG_CE_6_SRC = 70,
  187. HAL_SRNG_CE_7_SRC = 71,
  188. HAL_SRNG_CE_8_SRC = 72,
  189. HAL_SRNG_CE_9_SRC = 73,
  190. HAL_SRNG_CE_10_SRC = 74,
  191. HAL_SRNG_CE_11_SRC = 75,
  192. HAL_SRNG_CE_12_SRC = 76,
  193. HAL_SRNG_CE_13_SRC = 77,
  194. HAL_SRNG_CE_14_SRC = 78,
  195. HAL_SRNG_CE_15_SRC = 79,
  196. /* 80 */
  197. HAL_SRNG_CE_0_DST = 81,
  198. HAL_SRNG_CE_1_DST = 82,
  199. HAL_SRNG_CE_2_DST = 83,
  200. HAL_SRNG_CE_3_DST = 84,
  201. HAL_SRNG_CE_4_DST = 85,
  202. HAL_SRNG_CE_5_DST = 86,
  203. HAL_SRNG_CE_6_DST = 87,
  204. HAL_SRNG_CE_7_DST = 89,
  205. HAL_SRNG_CE_8_DST = 90,
  206. HAL_SRNG_CE_9_DST = 91,
  207. HAL_SRNG_CE_10_DST = 92,
  208. HAL_SRNG_CE_11_DST = 93,
  209. HAL_SRNG_CE_12_DST = 94,
  210. HAL_SRNG_CE_13_DST = 95,
  211. HAL_SRNG_CE_14_DST = 96,
  212. HAL_SRNG_CE_15_DST = 97,
  213. /* 98-99 unused */
  214. HAL_SRNG_CE_0_DST_STATUS = 100,
  215. HAL_SRNG_CE_1_DST_STATUS = 101,
  216. HAL_SRNG_CE_2_DST_STATUS = 102,
  217. HAL_SRNG_CE_3_DST_STATUS = 103,
  218. HAL_SRNG_CE_4_DST_STATUS = 104,
  219. HAL_SRNG_CE_5_DST_STATUS = 105,
  220. HAL_SRNG_CE_6_DST_STATUS = 106,
  221. HAL_SRNG_CE_7_DST_STATUS = 107,
  222. HAL_SRNG_CE_8_DST_STATUS = 108,
  223. HAL_SRNG_CE_9_DST_STATUS = 109,
  224. HAL_SRNG_CE_10_DST_STATUS = 110,
  225. HAL_SRNG_CE_11_DST_STATUS = 111,
  226. HAL_SRNG_CE_12_DST_STATUS = 112,
  227. HAL_SRNG_CE_13_DST_STATUS = 113,
  228. HAL_SRNG_CE_14_DST_STATUS = 114,
  229. HAL_SRNG_CE_15_DST_STATUS = 115,
  230. /* 116-119 unused */
  231. HAL_SRNG_WBM_IDLE_LINK = 120,
  232. HAL_SRNG_WBM_SW_RELEASE = 121,
  233. HAL_SRNG_WBM_SW1_RELEASE = 122,
  234. HAL_SRNG_WBM_PPE_RELEASE = 123,
  235. /* 124-127 unused */
  236. HAL_SRNG_WBM2SW0_RELEASE = 128,
  237. HAL_SRNG_WBM2SW1_RELEASE = 129,
  238. HAL_SRNG_WBM2SW2_RELEASE = 130,
  239. HAL_SRNG_WBM2SW3_RELEASE = 131,
  240. HAL_SRNG_WBM2SW4_RELEASE = 132,
  241. HAL_SRNG_WBM2SW5_RELEASE = 133,
  242. HAL_SRNG_WBM2SW6_RELEASE = 134,
  243. HAL_SRNG_WBM_ERROR_RELEASE = 135,
  244. /* 136-158 unused */
  245. HAL_SRNG_UMAC_ID_END = 159,
  246. /* Common DMAC rings shared by all LMACs */
  247. HAL_SRNG_SW2RXDMA_BUF0 = 160,
  248. HAL_SRNG_SW2RXDMA_BUF1 = 161,
  249. HAL_SRNG_SW2RXDMA_BUF2 = 162,
  250. /* 163-167 unused */
  251. HAL_SRNG_SW2RXMON_BUF0 = 168,
  252. /* 169-175 unused */
  253. /* 177-183 unused */
  254. HAL_SRNG_DMAC_CMN_ID_END = 183,
  255. /* LMAC rings - The following set will be replicated for each LMAC */
  256. HAL_SRNG_LMAC1_ID_START = 184,
  257. HAL_SRNG_WMAC1_SW2RXDMA0_BUF0 = HAL_SRNG_LMAC1_ID_START,
  258. #ifdef IPA_OFFLOAD
  259. HAL_SRNG_WMAC1_SW2RXDMA0_BUF1,
  260. HAL_SRNG_WMAC1_SW2RXDMA0_BUF2,
  261. #ifdef IPA_WDI3_VLAN_SUPPORT
  262. HAL_SRNG_WMAC1_SW2RXDMA0_BUF3,
  263. #endif
  264. HAL_SRNG_WMAC1_SW2RXDMA1_BUF,
  265. #else
  266. HAL_SRNG_WMAC1_SW2RXDMA1_BUF,
  267. #endif
  268. HAL_SRNG_WMAC1_SW2RXDMA2_BUF,
  269. HAL_SRNG_WMAC1_SW2RXDMA0_STATBUF,
  270. HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF,
  271. HAL_SRNG_WMAC1_RXDMA2SW0,
  272. HAL_SRNG_WMAC1_RXDMA2SW1,
  273. HAL_SRNG_WMAC1_RXMON2SW0 = HAL_SRNG_WMAC1_RXDMA2SW1,
  274. HAL_SRNG_WMAC1_SW2RXDMA1_DESC,
  275. #ifdef WLAN_FEATURE_CIF_CFR
  276. HAL_SRNG_WIFI_POS_SRC_DMA_RING,
  277. HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING,
  278. HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING1,
  279. #else
  280. HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING,
  281. HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING1,
  282. #endif
  283. HAL_SRNG_WMAC1_TXMON2SW0,
  284. HAL_SRNG_SW2TXMON_BUF0,
  285. HAL_SRNG_LMAC1_ID_END = (HAL_SRNG_SW2TXMON_BUF0 + 2),
  286. };
  287. #define HAL_RXDMA_MAX_RING_SIZE 0xFFFF
  288. #define HAL_MAX_LMACS 3
  289. #define HAL_MAX_RINGS_PER_LMAC (HAL_SRNG_LMAC1_ID_END - HAL_SRNG_LMAC1_ID_START)
  290. #define HAL_MAX_LMAC_RINGS (HAL_MAX_LMACS * HAL_MAX_RINGS_PER_LMAC)
  291. #define HAL_SRNG_ID_MAX (HAL_SRNG_DMAC_CMN_ID_END + HAL_MAX_LMAC_RINGS)
  292. /* SRNG type to be passed in APIs hal_srng_get_entrysize and hal_srng_setup */
  293. enum hal_ring_type {
  294. REO_DST = 0,
  295. REO_EXCEPTION = 1,
  296. REO_REINJECT = 2,
  297. REO_CMD = 3,
  298. REO_STATUS = 4,
  299. TCL_DATA = 5,
  300. TCL_CMD_CREDIT = 6,
  301. TCL_STATUS = 7,
  302. CE_SRC = 8,
  303. CE_DST = 9,
  304. CE_DST_STATUS = 10,
  305. WBM_IDLE_LINK = 11,
  306. SW2WBM_RELEASE = 12,
  307. WBM2SW_RELEASE = 13,
  308. RXDMA_BUF = 14,
  309. RXDMA_DST = 15,
  310. RXDMA_MONITOR_BUF = 16,
  311. RXDMA_MONITOR_STATUS = 17,
  312. RXDMA_MONITOR_DST = 18,
  313. RXDMA_MONITOR_DESC = 19,
  314. DIR_BUF_RX_DMA_SRC = 20,
  315. #ifdef WLAN_FEATURE_CIF_CFR
  316. WIFI_POS_SRC,
  317. #endif
  318. REO2PPE,
  319. PPE2TCL,
  320. PPE_RELEASE,
  321. TX_MONITOR_BUF,
  322. TX_MONITOR_DST,
  323. SW2RXDMA_NEW,
  324. MAX_RING_TYPES
  325. };
  326. enum SRNG_REGISTERS {
  327. DST_HP = 0,
  328. DST_TP,
  329. DST_ID,
  330. DST_MISC,
  331. DST_HP_ADDR_LSB,
  332. DST_HP_ADDR_MSB,
  333. DST_MSI1_BASE_LSB,
  334. DST_MSI1_BASE_MSB,
  335. DST_MSI1_DATA,
  336. #ifdef CONFIG_BERYLLIUM
  337. DST_MSI2_BASE_LSB,
  338. DST_MSI2_BASE_MSB,
  339. DST_MSI2_DATA,
  340. #endif
  341. DST_BASE_LSB,
  342. DST_BASE_MSB,
  343. DST_PRODUCER_INT_SETUP,
  344. #ifdef CONFIG_BERYLLIUM
  345. DST_PRODUCER_INT2_SETUP,
  346. #endif
  347. SRC_HP,
  348. SRC_TP,
  349. SRC_ID,
  350. SRC_MISC,
  351. SRC_TP_ADDR_LSB,
  352. SRC_TP_ADDR_MSB,
  353. SRC_MSI1_BASE_LSB,
  354. SRC_MSI1_BASE_MSB,
  355. SRC_MSI1_DATA,
  356. SRC_BASE_LSB,
  357. SRC_BASE_MSB,
  358. SRC_CONSUMER_INT_SETUP_IX0,
  359. SRC_CONSUMER_INT_SETUP_IX1,
  360. SRNG_REGISTER_MAX,
  361. };
  362. enum hal_srng_dir {
  363. HAL_SRNG_SRC_RING,
  364. HAL_SRNG_DST_RING
  365. };
  366. /**
  367. * enum hal_reo_remap_reg - REO remap registers
  368. * @HAL_REO_REMAP_REG_IX0: reo remap reg IX0
  369. * @HAL_REO_REMAP_REG_IX1: reo remap reg IX1
  370. * @HAL_REO_REMAP_REG_IX2: reo remap reg IX2
  371. * @HAL_REO_REMAP_REG_IX3: reo remap reg IX3
  372. */
  373. enum hal_reo_remap_reg {
  374. HAL_REO_REMAP_REG_IX0,
  375. HAL_REO_REMAP_REG_IX1,
  376. HAL_REO_REMAP_REG_IX2,
  377. HAL_REO_REMAP_REG_IX3
  378. };
  379. /* Lock wrappers for SRNG */
  380. #define hal_srng_lock_t qdf_spinlock_t
  381. #define SRNG_LOCK_INIT(_lock) qdf_spinlock_create(_lock)
  382. #define SRNG_LOCK(_lock) qdf_spin_lock_bh(_lock)
  383. #define SRNG_TRY_LOCK(_lock) qdf_spin_trylock_bh(_lock)
  384. #define SRNG_UNLOCK(_lock) qdf_spin_unlock_bh(_lock)
  385. #define SRNG_LOCK_DESTROY(_lock) qdf_spinlock_destroy(_lock)
  386. struct hal_soc;
  387. /**
  388. * dp_hal_ring - opaque handle for DP HAL SRNG
  389. */
  390. struct hal_ring_handle;
  391. typedef struct hal_ring_handle *hal_ring_handle_t;
  392. #define MAX_SRNG_REG_GROUPS 2
  393. /* Hal Srng bit mask
  394. * HAL_SRNG_FLUSH_EVENT: SRNG HP TP flush in case of link down
  395. */
  396. #define HAL_SRNG_FLUSH_EVENT BIT(0)
  397. #if defined(FEATURE_HAL_DELAYED_REG_WRITE)
  398. /**
  399. * struct hal_reg_write_q_elem - delayed register write queue element
  400. * @srng: hal_srng queued for a delayed write
  401. * @addr: iomem address of the register
  402. * @enqueue_val: register value at the time of delayed write enqueue
  403. * @dequeue_val: register value at the time of delayed write dequeue
  404. * @valid: whether this entry is valid or not
  405. * @enqueue_time: enqueue time (qdf_log_timestamp)
  406. * @work_scheduled_time: work scheduled time (qdf_log_timestamp)
  407. * @dequeue_time: dequeue time (qdf_log_timestamp)
  408. * @cpu_id: record cpuid when schedule work
  409. */
  410. struct hal_reg_write_q_elem {
  411. struct hal_srng *srng;
  412. void __iomem *addr;
  413. uint32_t enqueue_val;
  414. uint32_t dequeue_val;
  415. uint8_t valid;
  416. qdf_time_t enqueue_time;
  417. qdf_time_t work_scheduled_time;
  418. qdf_time_t dequeue_time;
  419. int cpu_id;
  420. };
  421. /**
  422. * struct hal_reg_write_srng_stats - srng stats to keep track of register writes
  423. * @enqueues: writes enqueued to delayed work
  424. * @dequeues: writes dequeued from delayed work (not written yet)
  425. * @coalesces: writes not enqueued since srng is already queued up
  426. * @direct: writes not enqueued and written to register directly
  427. * @dequeue_delay: dequeue operation be delayed
  428. */
  429. struct hal_reg_write_srng_stats {
  430. uint32_t enqueues;
  431. uint32_t dequeues;
  432. uint32_t coalesces;
  433. uint32_t direct;
  434. uint32_t dequeue_delay;
  435. };
  436. /**
  437. * enum hal_reg_sched_delay - ENUM for write sched delay histogram
  438. * @REG_WRITE_SCHED_DELAY_SUB_100us: index for delay < 100us
  439. * @REG_WRITE_SCHED_DELAY_SUB_1000us: index for delay < 1000us
  440. * @REG_WRITE_SCHED_DELAY_SUB_5000us: index for delay < 5000us
  441. * @REG_WRITE_SCHED_DELAY_GT_5000us: index for delay >= 5000us
  442. * @REG_WRITE_SCHED_DELAY_HIST_MAX: Max value (nnsize of histogram array)
  443. */
  444. enum hal_reg_sched_delay {
  445. REG_WRITE_SCHED_DELAY_SUB_100us,
  446. REG_WRITE_SCHED_DELAY_SUB_1000us,
  447. REG_WRITE_SCHED_DELAY_SUB_5000us,
  448. REG_WRITE_SCHED_DELAY_GT_5000us,
  449. REG_WRITE_SCHED_DELAY_HIST_MAX,
  450. };
  451. /**
  452. * struct hal_reg_write_soc_stats - soc stats to keep track of register writes
  453. * @enqueues: writes enqueued to delayed work
  454. * @dequeues: writes dequeued from delayed work (not written yet)
  455. * @coalesces: writes not enqueued since srng is already queued up
  456. * @direct: writes not enqueud and writted to register directly
  457. * @prevent_l1_fails: prevent l1 API failed
  458. * @q_depth: current queue depth in delayed register write queue
  459. * @max_q_depth: maximum queue for delayed register write queue
  460. * @sched_delay: = kernel work sched delay + bus wakeup delay, histogram
  461. * @dequeue_delay: dequeue operation be delayed
  462. */
  463. struct hal_reg_write_soc_stats {
  464. qdf_atomic_t enqueues;
  465. uint32_t dequeues;
  466. qdf_atomic_t coalesces;
  467. qdf_atomic_t direct;
  468. uint32_t prevent_l1_fails;
  469. qdf_atomic_t q_depth;
  470. uint32_t max_q_depth;
  471. uint32_t sched_delay[REG_WRITE_SCHED_DELAY_HIST_MAX];
  472. uint32_t dequeue_delay;
  473. };
  474. #endif
  475. struct hal_offload_info {
  476. uint8_t lro_eligible;
  477. uint8_t tcp_proto;
  478. uint8_t tcp_pure_ack;
  479. uint8_t ipv6_proto;
  480. uint8_t tcp_offset;
  481. uint16_t tcp_csum;
  482. uint16_t tcp_win;
  483. uint32_t tcp_seq_num;
  484. uint32_t tcp_ack_num;
  485. uint32_t flow_id;
  486. };
  487. #ifdef WLAN_DP_SRNG_USAGE_WM_TRACKING
  488. /**
  489. * enum hal_srng_high_wm_bin - BIN for SRNG high watermark
  490. * @HAL_SRNG_HIGH_WM_BIN_BELOW_50_PERCENT: <50% SRNG entries used
  491. * @HAL_SRNG_HIGH_WM_BIN_50_to_60: 50-60% SRNG entries used
  492. * @HAL_SRNG_HIGH_WM_BIN_60_to_70: 60-70% SRNG entries used
  493. * @HAL_SRNG_HIGH_WM_BIN_70_to_80: 70-80% SRNG entries used
  494. * @HAL_SRNG_HIGH_WM_BIN_80_to_90: 80-90% SRNG entries used
  495. * @HAL_SRNG_HIGH_WM_BIN_90_to_100: 90-100% SRNG entries used
  496. */
  497. enum hal_srng_high_wm_bin {
  498. HAL_SRNG_HIGH_WM_BIN_BELOW_50_PERCENT,
  499. HAL_SRNG_HIGH_WM_BIN_50_to_60,
  500. HAL_SRNG_HIGH_WM_BIN_60_to_70,
  501. HAL_SRNG_HIGH_WM_BIN_70_to_80,
  502. HAL_SRNG_HIGH_WM_BIN_80_to_90,
  503. HAL_SRNG_HIGH_WM_BIN_90_to_100,
  504. HAL_SRNG_HIGH_WM_BIN_MAX,
  505. };
  506. /**
  507. * struct hal_srng_high_wm_info - SRNG usage high watermark info
  508. * @val: highest number of entries used in SRNG
  509. * @timestamp: Timestamp when the max num entries were in used for a SRNG
  510. * @bin_thresh: threshold for each bins
  511. * @bins: Bins for srng usage
  512. */
  513. struct hal_srng_high_wm_info {
  514. uint32_t val;
  515. uint64_t timestamp;
  516. uint32_t bin_thresh[HAL_SRNG_HIGH_WM_BIN_MAX];
  517. uint32_t bins[HAL_SRNG_HIGH_WM_BIN_MAX];
  518. };
  519. #endif
  520. /* Common SRNG ring structure for source and destination rings */
  521. struct hal_srng {
  522. /* Unique SRNG ring ID */
  523. uint8_t ring_id;
  524. /* Ring initialization done */
  525. uint8_t initialized;
  526. /* Interrupt/MSI value assigned to this ring */
  527. int irq;
  528. /* Physical base address of the ring */
  529. qdf_dma_addr_t ring_base_paddr;
  530. /* Virtual base address of the ring */
  531. uint32_t *ring_base_vaddr;
  532. /* virtual address end */
  533. uint32_t *ring_vaddr_end;
  534. /* Number of entries in ring */
  535. uint32_t num_entries;
  536. /* Ring size */
  537. uint32_t ring_size;
  538. /* Ring size mask */
  539. uint32_t ring_size_mask;
  540. /* Size of ring entry */
  541. uint32_t entry_size;
  542. /* Interrupt timer threshold – in micro seconds */
  543. uint32_t intr_timer_thres_us;
  544. /* Interrupt batch counter threshold – in number of ring entries */
  545. uint32_t intr_batch_cntr_thres_entries;
  546. /* Applicable only for CE dest ring */
  547. uint32_t prefetch_timer;
  548. /* MSI Address */
  549. qdf_dma_addr_t msi_addr;
  550. /* MSI data */
  551. uint32_t msi_data;
  552. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  553. /* MSI2 Address */
  554. qdf_dma_addr_t msi2_addr;
  555. /* MSI2 data */
  556. uint32_t msi2_data;
  557. #endif
  558. /* Misc flags */
  559. uint32_t flags;
  560. /* Lock for serializing ring index updates */
  561. hal_srng_lock_t lock;
  562. /* Start offset of SRNG register groups for this ring
  563. * TBD: See if this is required - register address can be derived
  564. * from ring ID
  565. */
  566. void *hwreg_base[MAX_SRNG_REG_GROUPS];
  567. /* Ring type/name */
  568. enum hal_ring_type ring_type;
  569. /* Source or Destination ring */
  570. enum hal_srng_dir ring_dir;
  571. union {
  572. struct {
  573. /* SW tail pointer */
  574. uint32_t tp;
  575. /* Shadow head pointer location to be updated by HW */
  576. uint32_t *hp_addr;
  577. /* Cached head pointer */
  578. uint32_t cached_hp;
  579. /* Tail pointer location to be updated by SW – This
  580. * will be a register address and need not be
  581. * accessed through SW structure */
  582. uint32_t *tp_addr;
  583. /* Current SW loop cnt */
  584. uint32_t loop_cnt;
  585. /* max transfer size */
  586. uint16_t max_buffer_length;
  587. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  588. /* near full IRQ supported */
  589. uint16_t nf_irq_support;
  590. /* High threshold for Near full IRQ */
  591. uint16_t high_thresh;
  592. #endif
  593. } dst_ring;
  594. struct {
  595. /* SW head pointer */
  596. uint32_t hp;
  597. /* SW reap head pointer */
  598. uint32_t reap_hp;
  599. /* Shadow tail pointer location to be updated by HW */
  600. uint32_t *tp_addr;
  601. /* Cached tail pointer */
  602. uint32_t cached_tp;
  603. /* Head pointer location to be updated by SW – This
  604. * will be a register address and need not be accessed
  605. * through SW structure */
  606. uint32_t *hp_addr;
  607. /* Low threshold – in number of ring entries */
  608. uint32_t low_threshold;
  609. } src_ring;
  610. } u;
  611. struct hal_soc *hal_soc;
  612. /* Number of times hp/tp updated in runtime resume */
  613. uint32_t flush_count;
  614. /* hal srng event flag*/
  615. unsigned long srng_event;
  616. /* last flushed time stamp */
  617. uint64_t last_flush_ts;
  618. #if defined(CLEAR_SW2TCL_CONSUMED_DESC)
  619. /* last ring desc entry cleared */
  620. uint32_t last_desc_cleared;
  621. #endif
  622. #if defined(FEATURE_HAL_DELAYED_REG_WRITE)
  623. /* flag to indicate whether srng is already queued for delayed write */
  624. uint8_t reg_write_in_progress;
  625. /* last dequeue elem time stamp */
  626. qdf_time_t last_dequeue_time;
  627. /* srng specific delayed write stats */
  628. struct hal_reg_write_srng_stats wstats;
  629. #endif
  630. #ifdef WLAN_DP_SRNG_USAGE_WM_TRACKING
  631. struct hal_srng_high_wm_info high_wm;
  632. #endif
  633. };
  634. /* HW SRNG configuration table */
  635. struct hal_hw_srng_config {
  636. int start_ring_id;
  637. uint16_t max_rings;
  638. uint16_t entry_size;
  639. uint32_t reg_start[MAX_SRNG_REG_GROUPS];
  640. uint16_t reg_size[MAX_SRNG_REG_GROUPS];
  641. uint8_t lmac_ring;
  642. enum hal_srng_dir ring_dir;
  643. uint32_t max_size;
  644. bool nf_irq_support;
  645. };
  646. #define MAX_SHADOW_REGISTERS 40
  647. #define MAX_GENERIC_SHADOW_REG 5
  648. /**
  649. * struct shadow_reg_config - Hal soc structure that contains
  650. * the list of generic shadow registers
  651. * @target_register: target reg offset
  652. * @shadow_config_index: shadow config index in shadow config
  653. * list sent to FW
  654. * @va: virtual addr of shadow reg
  655. *
  656. * This structure holds the generic registers that are mapped to
  657. * the shadow region and holds the mapping of the target
  658. * register offset to shadow config index provided to FW during
  659. * init
  660. */
  661. struct shadow_reg_config {
  662. uint32_t target_register;
  663. int shadow_config_index;
  664. uint64_t va;
  665. };
  666. /* REO parameters to be passed to hal_reo_setup */
  667. struct hal_reo_params {
  668. /** rx hash steering enabled or disabled */
  669. bool rx_hash_enabled;
  670. /** reo remap 0 register */
  671. uint32_t remap0;
  672. /** reo remap 1 register */
  673. uint32_t remap1;
  674. /** reo remap 2 register */
  675. uint32_t remap2;
  676. /** fragment destination ring */
  677. uint8_t frag_dst_ring;
  678. /* Destination for alternate */
  679. uint8_t alt_dst_ind_0;
  680. /** padding */
  681. uint8_t padding[2];
  682. };
  683. /**
  684. * enum hal_reo_cmd_type: Enum for REO command type
  685. * @CMD_GET_QUEUE_STATS: Get REO queue status/stats
  686. * @CMD_FLUSH_QUEUE: Flush all frames in REO queue
  687. * @CMD_FLUSH_CACHE: Flush descriptor entries in the cache
  688. * @CMD_UNBLOCK_CACHE: Unblock a descriptor’s address that was blocked
  689. * earlier with a ‘REO_FLUSH_CACHE’ command
  690. * @CMD_FLUSH_TIMEOUT_LIST: Flush buffers/descriptors from timeout list
  691. * @CMD_UPDATE_RX_REO_QUEUE: Update REO queue settings
  692. */
  693. enum hal_reo_cmd_type {
  694. CMD_GET_QUEUE_STATS = 0,
  695. CMD_FLUSH_QUEUE = 1,
  696. CMD_FLUSH_CACHE = 2,
  697. CMD_UNBLOCK_CACHE = 3,
  698. CMD_FLUSH_TIMEOUT_LIST = 4,
  699. CMD_UPDATE_RX_REO_QUEUE = 5
  700. };
  701. /**
  702. * enum hal_tx_mcast_mlo_reinject_notify
  703. * @HAL_TX_MCAST_MLO_REINJECT_FW_NOTIFY: MLO Mcast reinject routed to FW
  704. * @HAL_TX_MCAST_MLO_REINJECT_TQM_NOTIFY: MLO Mcast reinject routed to TQM
  705. */
  706. enum hal_tx_mcast_mlo_reinject_notify {
  707. HAL_TX_MCAST_MLO_REINJECT_FW_NOTIFY = 0,
  708. HAL_TX_MCAST_MLO_REINJECT_TQM_NOTIFY,
  709. };
  710. /**
  711. * enum hal_tx_vdev_mismatch_notify
  712. * @HAL_TX_VDEV_MISMATCH_TQM_NOTIFY: vdev mismatch exception routed to TQM
  713. * @HAL_TX_VDEV_MISMATCH_FW_NOTIFY: vdev mismatch exception routed to FW
  714. */
  715. enum hal_tx_vdev_mismatch_notify {
  716. HAL_TX_VDEV_MISMATCH_TQM_NOTIFY = 0,
  717. HAL_TX_VDEV_MISMATCH_FW_NOTIFY,
  718. };
  719. struct hal_rx_pkt_capture_flags {
  720. uint8_t encrypt_type;
  721. uint8_t fragment_flag;
  722. uint8_t fcs_err;
  723. uint32_t chan_freq;
  724. uint32_t rssi_comb;
  725. uint64_t tsft;
  726. };
  727. struct hal_hw_txrx_ops {
  728. /* init and setup */
  729. void (*hal_srng_dst_hw_init)(struct hal_soc *hal,
  730. struct hal_srng *srng);
  731. void (*hal_srng_src_hw_init)(struct hal_soc *hal,
  732. struct hal_srng *srng);
  733. void (*hal_get_hw_hptp)(struct hal_soc *hal,
  734. hal_ring_handle_t hal_ring_hdl,
  735. uint32_t *headp, uint32_t *tailp,
  736. uint8_t ring_type);
  737. void (*hal_reo_setup)(struct hal_soc *hal_soc, void *reoparams);
  738. void (*hal_setup_link_idle_list)(
  739. struct hal_soc *hal_soc,
  740. qdf_dma_addr_t scatter_bufs_base_paddr[],
  741. void *scatter_bufs_base_vaddr[],
  742. uint32_t num_scatter_bufs,
  743. uint32_t scatter_buf_size,
  744. uint32_t last_buf_end_offset,
  745. uint32_t num_entries);
  746. qdf_iomem_t (*hal_get_window_address)(struct hal_soc *hal_soc,
  747. qdf_iomem_t addr);
  748. void (*hal_reo_set_err_dst_remap)(void *hal_soc);
  749. uint8_t (*hal_reo_enable_pn_in_dest)(void *hal_soc);
  750. void (*hal_reo_qdesc_setup)(hal_soc_handle_t hal_soc_hdl, int tid,
  751. uint32_t ba_window_size,
  752. uint32_t start_seq, void *hw_qdesc_vaddr,
  753. qdf_dma_addr_t hw_qdesc_paddr,
  754. int pn_type, uint8_t vdev_stats_id);
  755. uint32_t (*hal_gen_reo_remap_val)(enum hal_reo_remap_reg,
  756. uint8_t *ix0_map);
  757. /* tx */
  758. void (*hal_tx_desc_set_dscp_tid_table_id)(void *desc, uint8_t id);
  759. void (*hal_tx_set_dscp_tid_map)(struct hal_soc *hal_soc, uint8_t *map,
  760. uint8_t id);
  761. void (*hal_tx_update_dscp_tid)(struct hal_soc *hal_soc, uint8_t tid,
  762. uint8_t id,
  763. uint8_t dscp);
  764. void (*hal_tx_desc_set_lmac_id)(void *desc, uint8_t lmac_id);
  765. void (*hal_tx_desc_set_buf_addr)(void *desc, dma_addr_t paddr,
  766. uint8_t pool_id, uint32_t desc_id,
  767. uint8_t type);
  768. void (*hal_tx_desc_set_search_type)(void *desc, uint8_t search_type);
  769. void (*hal_tx_desc_set_search_index)(void *desc, uint32_t search_index);
  770. void (*hal_tx_desc_set_cache_set_num)(void *desc, uint8_t search_index);
  771. void (*hal_tx_comp_get_status)(void *desc, void *ts,
  772. struct hal_soc *hal);
  773. uint8_t (*hal_tx_comp_get_release_reason)(void *hal_desc);
  774. uint8_t (*hal_get_wbm_internal_error)(void *hal_desc);
  775. void (*hal_tx_desc_set_mesh_en)(void *desc, uint8_t en);
  776. void (*hal_tx_init_cmd_credit_ring)(hal_soc_handle_t hal_soc_hdl,
  777. hal_ring_handle_t hal_ring_hdl);
  778. uint32_t (*hal_tx_comp_get_buffer_source)(void *hal_desc);
  779. uint32_t (*hal_tx_get_num_ppe_vp_tbl_entries)(
  780. hal_soc_handle_t hal_soc_hdl);
  781. void (*hal_tx_set_ppe_cmn_cfg)(hal_soc_handle_t hal_soc_hdl,
  782. union hal_tx_cmn_config_ppe *cmn_cfg);
  783. void (*hal_tx_set_ppe_vp_entry)(hal_soc_handle_t hal_soc_hdl,
  784. union hal_tx_ppe_vp_config *vp_cfg,
  785. int ppe_vp_idx);
  786. void (*hal_tx_set_ppe_pri2tid)(hal_soc_handle_t hal_soc_hdl,
  787. uint32_t val,
  788. uint8_t map_no);
  789. void (*hal_tx_update_ppe_pri2tid)(hal_soc_handle_t hal_soc_hdl,
  790. uint8_t pri,
  791. uint8_t tid);
  792. void (*hal_tx_dump_ppe_vp_entry)(hal_soc_handle_t hal_soc_hdl);
  793. void (*hal_tx_enable_pri2tid_map)(hal_soc_handle_t hal_soc_hdl,
  794. bool value, uint8_t ppe_vp_idx);
  795. void (*hal_tx_config_rbm_mapping_be)(hal_soc_handle_t hal_soc_hdl,
  796. hal_ring_handle_t hal_ring_hdl,
  797. uint8_t rbm_id);
  798. /* rx */
  799. uint32_t (*hal_rx_msdu_start_nss_get)(uint8_t *);
  800. void (*hal_rx_mon_hw_desc_get_mpdu_status)(void *hw_desc_addr,
  801. struct mon_rx_status *rs);
  802. uint8_t (*hal_rx_get_tlv)(void *rx_tlv);
  803. void (*hal_rx_proc_phyrx_other_receive_info_tlv)(void *rx_tlv_hdr,
  804. void *ppdu_info_handle);
  805. void (*hal_rx_dump_msdu_start_tlv)(void *msdu_start, uint8_t dbg_level);
  806. void (*hal_rx_dump_msdu_end_tlv)(void *msdu_end,
  807. uint8_t dbg_level);
  808. uint32_t (*hal_get_link_desc_size)(void);
  809. uint32_t (*hal_rx_mpdu_start_tid_get)(uint8_t *buf);
  810. uint32_t (*hal_rx_msdu_start_reception_type_get)(uint8_t *buf);
  811. uint16_t (*hal_rx_msdu_end_da_idx_get)(uint8_t *buf);
  812. void* (*hal_rx_msdu_desc_info_get_ptr)(void *msdu_details_ptr);
  813. void* (*hal_rx_link_desc_msdu0_ptr)(void *msdu_link_ptr);
  814. void (*hal_reo_status_get_header)(hal_ring_desc_t ring_desc, int b,
  815. void *h);
  816. uint32_t (*hal_rx_status_get_tlv_info)(void *rx_tlv_hdr,
  817. void *ppdu_info,
  818. hal_soc_handle_t hal_soc_hdl,
  819. qdf_nbuf_t nbuf);
  820. void (*hal_rx_wbm_rel_buf_paddr_get)(hal_ring_desc_t rx_desc,
  821. struct hal_buf_info *buf_info);
  822. void (*hal_rx_wbm_err_info_get)(void *wbm_desc,
  823. void *wbm_er_info);
  824. void (*hal_rx_dump_mpdu_start_tlv)(void *mpdustart,
  825. uint8_t dbg_level);
  826. void (*hal_tx_set_pcp_tid_map)(struct hal_soc *hal_soc, uint8_t *map);
  827. void (*hal_tx_update_pcp_tid_map)(struct hal_soc *hal_soc, uint8_t pcp,
  828. uint8_t id);
  829. void (*hal_tx_set_tidmap_prty)(struct hal_soc *hal_soc, uint8_t prio);
  830. /* rx */
  831. uint8_t (*hal_rx_get_rx_fragment_number)(uint8_t *buf);
  832. uint8_t (*hal_rx_msdu_end_da_is_mcbc_get)(uint8_t *buf);
  833. uint8_t (*hal_rx_msdu_end_is_tkip_mic_err)(uint8_t *buf);
  834. uint8_t (*hal_rx_msdu_end_sa_is_valid_get)(uint8_t *buf);
  835. uint16_t (*hal_rx_msdu_end_sa_idx_get)(uint8_t *buf);
  836. uint32_t (*hal_rx_desc_is_first_msdu)(void *hw_desc_addr);
  837. uint32_t (*hal_rx_msdu_end_l3_hdr_padding_get)(uint8_t *buf);
  838. uint32_t (*hal_rx_encryption_info_valid)(uint8_t *buf);
  839. void (*hal_rx_print_pn)(uint8_t *buf);
  840. uint8_t (*hal_rx_msdu_end_first_msdu_get)(uint8_t *buf);
  841. uint8_t (*hal_rx_msdu_end_da_is_valid_get)(uint8_t *buf);
  842. uint8_t (*hal_rx_msdu_end_last_msdu_get)(uint8_t *buf);
  843. bool (*hal_rx_get_mpdu_mac_ad4_valid)(uint8_t *buf);
  844. uint32_t (*hal_rx_mpdu_start_sw_peer_id_get)(uint8_t *buf);
  845. uint32_t (*hal_rx_mpdu_peer_meta_data_get)(uint8_t *buf);
  846. uint32_t (*hal_rx_mpdu_get_to_ds)(uint8_t *buf);
  847. uint32_t (*hal_rx_mpdu_get_fr_ds)(uint8_t *buf);
  848. uint8_t (*hal_rx_get_mpdu_frame_control_valid)(uint8_t *buf);
  849. QDF_STATUS
  850. (*hal_rx_mpdu_get_addr1)(uint8_t *buf, uint8_t *mac_addr);
  851. QDF_STATUS
  852. (*hal_rx_mpdu_get_addr2)(uint8_t *buf, uint8_t *mac_addr);
  853. QDF_STATUS
  854. (*hal_rx_mpdu_get_addr3)(uint8_t *buf, uint8_t *mac_addr);
  855. QDF_STATUS
  856. (*hal_rx_mpdu_get_addr4)(uint8_t *buf, uint8_t *mac_addr);
  857. uint8_t (*hal_rx_get_mpdu_sequence_control_valid)(uint8_t *buf);
  858. bool (*hal_rx_is_unicast)(uint8_t *buf);
  859. uint32_t (*hal_rx_tid_get)(hal_soc_handle_t hal_soc_hdl, uint8_t *buf);
  860. uint32_t (*hal_rx_hw_desc_get_ppduid_get)(void *rx_tlv_hdr,
  861. void *rxdma_dst_ring_desc);
  862. uint32_t (*hal_rx_mpdu_start_mpdu_qos_control_valid_get)(uint8_t *buf);
  863. uint32_t (*hal_rx_msdu_end_sa_sw_peer_id_get)(uint8_t *buf);
  864. void * (*hal_rx_msdu0_buffer_addr_lsb)(void *link_desc_addr);
  865. void * (*hal_rx_msdu_desc_info_ptr_get)(void *msdu0);
  866. void * (*hal_ent_mpdu_desc_info)(void *hw_addr);
  867. void * (*hal_dst_mpdu_desc_info)(void *hw_addr);
  868. uint8_t (*hal_rx_get_fc_valid)(uint8_t *buf);
  869. uint8_t (*hal_rx_get_to_ds_flag)(uint8_t *buf);
  870. uint8_t (*hal_rx_get_mac_addr2_valid)(uint8_t *buf);
  871. uint8_t (*hal_rx_get_filter_category)(uint8_t *buf);
  872. uint32_t (*hal_rx_get_ppdu_id)(uint8_t *buf);
  873. void (*hal_reo_config)(struct hal_soc *soc,
  874. uint32_t reg_val,
  875. struct hal_reo_params *reo_params);
  876. uint32_t (*hal_rx_msdu_flow_idx_get)(uint8_t *buf);
  877. bool (*hal_rx_msdu_flow_idx_invalid)(uint8_t *buf);
  878. bool (*hal_rx_msdu_flow_idx_timeout)(uint8_t *buf);
  879. uint32_t (*hal_rx_msdu_fse_metadata_get)(uint8_t *buf);
  880. bool (*hal_rx_msdu_cce_match_get)(uint8_t *buf);
  881. uint16_t (*hal_rx_msdu_cce_metadata_get)(uint8_t *buf);
  882. void
  883. (*hal_rx_msdu_get_flow_params)(
  884. uint8_t *buf,
  885. bool *flow_invalid,
  886. bool *flow_timeout,
  887. uint32_t *flow_index);
  888. uint16_t (*hal_rx_tlv_get_tcp_chksum)(uint8_t *buf);
  889. uint16_t (*hal_rx_get_rx_sequence)(uint8_t *buf);
  890. void (*hal_rx_get_bb_info)(void *rx_tlv, void *ppdu_info_handle);
  891. void (*hal_rx_get_rtt_info)(void *rx_tlv, void *ppdu_info_handle);
  892. void (*hal_rx_msdu_packet_metadata_get)(uint8_t *buf,
  893. void *msdu_pkt_metadata);
  894. uint16_t (*hal_rx_get_fisa_cumulative_l4_checksum)(uint8_t *buf);
  895. uint16_t (*hal_rx_get_fisa_cumulative_ip_length)(uint8_t *buf);
  896. bool (*hal_rx_get_udp_proto)(uint8_t *buf);
  897. bool (*hal_rx_get_fisa_flow_agg_continuation)(uint8_t *buf);
  898. uint8_t (*hal_rx_get_fisa_flow_agg_count)(uint8_t *buf);
  899. bool (*hal_rx_get_fisa_timeout)(uint8_t *buf);
  900. uint8_t (*hal_rx_mpdu_start_tlv_tag_valid)(void *rx_tlv_hdr);
  901. void (*hal_rx_sw_mon_desc_info_get)(hal_ring_desc_t rxdma_dst_ring_desc,
  902. hal_rx_mon_desc_info_t mon_desc_info);
  903. uint8_t (*hal_rx_wbm_err_msdu_continuation_get)(void *ring_desc);
  904. uint32_t (*hal_rx_msdu_end_offset_get)(void);
  905. uint32_t (*hal_rx_attn_offset_get)(void);
  906. uint32_t (*hal_rx_msdu_start_offset_get)(void);
  907. uint32_t (*hal_rx_mpdu_start_offset_get)(void);
  908. uint32_t (*hal_rx_mpdu_end_offset_get)(void);
  909. uint32_t (*hal_rx_pkt_tlv_offset_get)(void);
  910. void * (*hal_rx_flow_setup_fse)(uint8_t *rx_fst,
  911. uint32_t table_offset,
  912. uint8_t *rx_flow);
  913. void * (*hal_rx_flow_get_tuple_info)(uint8_t *rx_fst,
  914. uint32_t hal_hash,
  915. uint8_t *tuple_info);
  916. QDF_STATUS (*hal_rx_flow_delete_entry)(uint8_t *fst,
  917. void *fse);
  918. uint32_t (*hal_rx_fst_get_fse_size)(void);
  919. void (*hal_compute_reo_remap_ix2_ix3)(uint32_t *ring,
  920. uint32_t num_rings,
  921. uint32_t *remap1,
  922. uint32_t *remap2);
  923. void (*hal_compute_reo_remap_ix0)(uint32_t *remap0);
  924. uint32_t (*hal_rx_flow_setup_cmem_fse)(
  925. struct hal_soc *soc, uint32_t cmem_ba,
  926. uint32_t table_offset, uint8_t *rx_flow);
  927. uint32_t (*hal_rx_flow_get_cmem_fse_ts)(struct hal_soc *soc,
  928. uint32_t fse_offset);
  929. void (*hal_rx_flow_get_cmem_fse)(struct hal_soc *soc,
  930. uint32_t fse_offset,
  931. uint32_t *fse, qdf_size_t len);
  932. void (*hal_cmem_write)(hal_soc_handle_t hal_soc_hdl, uint32_t offset,
  933. uint32_t value);
  934. void (*hal_rx_msdu_get_reo_destination_indication)(uint8_t *buf,
  935. uint32_t *reo_destination_indication);
  936. uint8_t (*hal_tx_get_num_tcl_banks)(void);
  937. uint32_t (*hal_get_reo_qdesc_size)(uint32_t ba_window_size, int tid);
  938. uint16_t (*hal_get_rx_max_ba_window)(int tid);
  939. void (*hal_set_link_desc_addr)(void *desc, uint32_t cookie,
  940. qdf_dma_addr_t link_desc_paddr,
  941. uint8_t bm_id);
  942. void (*hal_tx_init_data_ring)(hal_soc_handle_t hal_soc_hdl,
  943. hal_ring_handle_t hal_ring_hdl);
  944. void* (*hal_rx_msdu_ext_desc_info_get_ptr)(void *msdu_details_ptr);
  945. void (*hal_get_ba_aging_timeout)(hal_soc_handle_t hal_soc_hdl,
  946. uint8_t ac, uint32_t *value);
  947. void (*hal_set_ba_aging_timeout)(hal_soc_handle_t hal_soc_hdl,
  948. uint8_t ac, uint32_t value);
  949. uint32_t (*hal_get_reo_reg_base_offset)(void);
  950. void (*hal_rx_get_tlv_size)(uint16_t *rx_pkt_tlv_size,
  951. uint16_t *rx_mon_pkt_tlv_size);
  952. uint32_t (*hal_rx_msdu_is_wlan_mcast)(qdf_nbuf_t nbuf);
  953. uint32_t (*hal_rx_tlv_decap_format_get)(void *hw_desc_addr);
  954. void (*hal_rx_dump_pkt_tlvs)(hal_soc_handle_t hal_soc_hdl,
  955. uint8_t *buf, uint8_t dbg_level);
  956. int (*hal_rx_tlv_get_offload_info)(uint8_t *rx_tlv,
  957. struct hal_offload_info *offload_info);
  958. uint16_t (*hal_rx_tlv_phy_ppdu_id_get)(uint8_t *buf);
  959. uint32_t (*hal_rx_tlv_msdu_done_get)(uint8_t *buf);
  960. uint32_t (*hal_rx_tlv_msdu_len_get)(uint8_t *buf);
  961. uint16_t (*hal_rx_get_frame_ctrl_field)(uint8_t *buf);
  962. int (*hal_rx_get_proto_params)(uint8_t *buf, void *fisa_params);
  963. int (*hal_rx_get_l3_l4_offsets)(uint8_t *buf, uint32_t *l3_hdr_offset,
  964. uint32_t *l4_hdr_offset);
  965. uint32_t (*hal_rx_tlv_mic_err_get)(uint8_t *buf);
  966. uint32_t (*hal_rx_tlv_get_pkt_type)(uint8_t *buf);
  967. void (*hal_rx_tlv_get_pn_num)(uint8_t *buf, uint64_t *pn_num);
  968. void (*hal_rx_reo_prev_pn_get)(void *ring_desc, uint64_t *prev_pn);
  969. uint8_t * (*hal_rx_pkt_hdr_get)(uint8_t *buf);
  970. uint32_t (*hal_rx_msdu_reo_dst_ind_get)(hal_soc_handle_t hal_soc_hdl,
  971. void *msdu_link_desc);
  972. void (*hal_msdu_desc_info_set)(hal_soc_handle_t hal_soc_hdl,
  973. void *msdu_desc_info, uint32_t dst_ind,
  974. uint32_t nbuf_len);
  975. void (*hal_mpdu_desc_info_set)(hal_soc_handle_t hal_soc_hdl,
  976. void *mpdu_desc_info, uint32_t seq_no);
  977. uint32_t (*hal_rx_tlv_sgi_get)(uint8_t *buf);
  978. uint32_t (*hal_rx_tlv_get_freq)(uint8_t *buf);
  979. uint8_t (*hal_rx_msdu_get_keyid)(uint8_t *buf);
  980. uint32_t (*hal_rx_tlv_rate_mcs_get)(uint8_t *buf);
  981. uint32_t (*hal_rx_tlv_decrypt_err_get)(uint8_t *buf);
  982. uint32_t (*hal_rx_tlv_first_mpdu_get)(uint8_t *buf);
  983. uint32_t (*hal_rx_tlv_bw_get)(uint8_t *buf);
  984. uint32_t (*hal_rx_tlv_get_is_decrypted)(uint8_t *buf);
  985. uint32_t (*hal_rx_wbm_err_src_get)(hal_ring_desc_t ring_desc);
  986. uint8_t (*hal_rx_ret_buf_manager_get)(hal_ring_desc_t ring_desc);
  987. void (*hal_rx_msdu_link_desc_set)(hal_soc_handle_t hal_soc_hdl,
  988. void *src_srng_desc,
  989. hal_buff_addrinfo_t buf_addr_info,
  990. uint8_t bm_action);
  991. void (*hal_rx_buf_cookie_rbm_get)(uint32_t *buf_addr_info_hdl,
  992. hal_buf_info_t buf_info_hdl);
  993. void (*hal_rx_reo_buf_paddr_get)(hal_ring_desc_t rx_desc,
  994. struct hal_buf_info *buf_info);
  995. void (*hal_rxdma_buff_addr_info_set)(void *rxdma_entry,
  996. qdf_dma_addr_t paddr,
  997. uint32_t cookie, uint8_t manager);
  998. uint32_t (*hal_rx_msdu_flags_get)(rx_msdu_desc_info_t msdu_desc_info_hdl);
  999. uint32_t (*hal_rx_get_reo_error_code)(hal_ring_desc_t rx_desc);
  1000. void (*hal_rx_tlv_csum_err_get)(uint8_t *rx_tlv_hdr,
  1001. uint32_t *ip_csum_err,
  1002. uint32_t *tcp_udp_csum_err);
  1003. void (*hal_rx_mpdu_desc_info_get)(void *desc_addr,
  1004. void *mpdu_desc_info_hdl);
  1005. uint8_t (*hal_rx_err_status_get)(hal_ring_desc_t rx_desc);
  1006. uint8_t (*hal_rx_reo_buf_type_get)(hal_ring_desc_t rx_desc);
  1007. bool (*hal_rx_mpdu_info_ampdu_flag_get)(uint8_t *buf);
  1008. uint32_t (*hal_rx_tlv_mpdu_len_err_get)(void *hw_desc_addr);
  1009. uint32_t (*hal_rx_tlv_mpdu_fcs_err_get)(void *hw_desc_addr);
  1010. void (*hal_rx_tlv_get_pkt_capture_flags)(uint8_t *rx_tlv_hdr,
  1011. struct hal_rx_pkt_capture_flags *flags);
  1012. uint8_t *(*hal_rx_desc_get_80211_hdr)(void *hw_desc_addr);
  1013. uint32_t (*hal_rx_hw_desc_mpdu_user_id)(void *hw_desc_addr);
  1014. void (*hal_rx_priv_info_set_in_tlv)(uint8_t *buf,
  1015. uint8_t *priv_data,
  1016. uint32_t len);
  1017. void (*hal_rx_priv_info_get_from_tlv)(uint8_t *buf,
  1018. uint8_t *priv_data,
  1019. uint32_t len);
  1020. void (*hal_rx_tlv_msdu_len_set)(uint8_t *buf, uint32_t len);
  1021. void (*hal_rx_tlv_populate_mpdu_desc_info)(uint8_t *buf,
  1022. void *mpdu_desc_info_hdl);
  1023. uint8_t *(*hal_get_reo_ent_desc_qdesc_addr)(uint8_t *desc);
  1024. uint64_t (*hal_rx_get_qdesc_addr)(uint8_t *dst_ring_desc,
  1025. uint8_t *buf);
  1026. void (*hal_set_reo_ent_desc_reo_dest_ind)(uint8_t *desc,
  1027. uint32_t dst_ind);
  1028. /* REO CMD and STATUS */
  1029. int (*hal_reo_send_cmd)(hal_soc_handle_t hal_soc_hdl,
  1030. hal_ring_handle_t hal_ring_hdl,
  1031. enum hal_reo_cmd_type cmd,
  1032. void *params);
  1033. QDF_STATUS (*hal_reo_status_update)(hal_soc_handle_t hal_soc_hdl,
  1034. hal_ring_desc_t reo_desc,
  1035. void *st_handle,
  1036. uint32_t tlv, int *num_ref);
  1037. uint8_t (*hal_get_tlv_hdr_size)(void);
  1038. uint8_t (*hal_get_idle_link_bm_id)(uint8_t chip_id);
  1039. bool (*hal_txmon_is_mon_buf_addr_tlv)(void *tx_tlv_hdr);
  1040. void (*hal_txmon_populate_packet_info)(void *tx_tlv_hdr,
  1041. void *pkt_info);
  1042. /* TX MONITOR */
  1043. #ifdef QCA_MONITOR_2_0_SUPPORT
  1044. uint32_t (*hal_txmon_status_parse_tlv)(void *data_ppdu_info,
  1045. void *prot_ppdu_info,
  1046. void *data_status_info,
  1047. void *prot_status_info,
  1048. void *tx_tlv_hdr,
  1049. qdf_frag_t status_frag);
  1050. uint32_t (*hal_txmon_status_get_num_users)(void *tx_tlv_hdr,
  1051. uint8_t *num_users);
  1052. #endif /* QCA_MONITOR_2_0_SUPPORT */
  1053. void (*hal_reo_shared_qaddr_setup)(hal_soc_handle_t hal_soc_hdl);
  1054. void (*hal_reo_shared_qaddr_init)(hal_soc_handle_t hal_soc_hdl);
  1055. void (*hal_reo_shared_qaddr_detach)(hal_soc_handle_t hal_soc_hdl);
  1056. void (*hal_reo_shared_qaddr_write)(hal_soc_handle_t hal_soc_hdl,
  1057. uint16_t peer_id,
  1058. int tid,
  1059. qdf_dma_addr_t hw_qdesc_paddr);
  1060. #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET
  1061. uint8_t (*hal_get_first_wow_wakeup_packet)(uint8_t *buf);
  1062. #endif
  1063. void (*hal_reo_shared_qaddr_cache_clear)(hal_soc_handle_t hal_soc_hdl);
  1064. uint32_t (*hal_rx_tlv_l3_type_get)(uint8_t *buf);
  1065. void (*hal_tx_vdev_mismatch_routing_set)(hal_soc_handle_t hal_soc_hdl,
  1066. enum hal_tx_vdev_mismatch_notify config);
  1067. void (*hal_tx_mcast_mlo_reinject_routing_set)(
  1068. hal_soc_handle_t hal_soc_hdl,
  1069. enum hal_tx_mcast_mlo_reinject_notify config);
  1070. void (*hal_cookie_conversion_reg_cfg_be)(hal_soc_handle_t hal_soc_hdl,
  1071. struct hal_hw_cc_config
  1072. *cc_cfg);
  1073. };
  1074. /**
  1075. * struct hal_soc_stats - Hal layer stats
  1076. * @reg_write_fail: number of failed register writes
  1077. * @wstats: delayed register write stats
  1078. * @shadow_reg_write_fail: shadow reg write failure stats
  1079. * @shadow_reg_write_succ: shadow reg write success stats
  1080. *
  1081. * This structure holds all the statistics at HAL layer.
  1082. */
  1083. struct hal_soc_stats {
  1084. uint32_t reg_write_fail;
  1085. #if defined(FEATURE_HAL_DELAYED_REG_WRITE)
  1086. struct hal_reg_write_soc_stats wstats;
  1087. #endif
  1088. #ifdef GENERIC_SHADOW_REGISTER_ACCESS_ENABLE
  1089. uint32_t shadow_reg_write_fail;
  1090. uint32_t shadow_reg_write_succ;
  1091. #endif
  1092. };
  1093. #ifdef ENABLE_HAL_REG_WR_HISTORY
  1094. /* The history size should always be a power of 2 */
  1095. #define HAL_REG_WRITE_HIST_SIZE 8
  1096. /**
  1097. * struct hal_reg_write_fail_entry - Record of
  1098. * register write which failed.
  1099. * @timestamp: timestamp of reg write failure
  1100. * @reg_offset: offset of register where the write failed
  1101. * @write_val: the value which was to be written
  1102. * @read_val: the value read back from the register after write
  1103. */
  1104. struct hal_reg_write_fail_entry {
  1105. uint64_t timestamp;
  1106. uint32_t reg_offset;
  1107. uint32_t write_val;
  1108. uint32_t read_val;
  1109. };
  1110. /**
  1111. * struct hal_reg_write_fail_history - Hal layer history
  1112. * of all the register write failures.
  1113. * @index: index to add the new record
  1114. * @record: array of all the records in history
  1115. *
  1116. * This structure holds the history of register write
  1117. * failures at HAL layer.
  1118. */
  1119. struct hal_reg_write_fail_history {
  1120. qdf_atomic_t index;
  1121. struct hal_reg_write_fail_entry record[HAL_REG_WRITE_HIST_SIZE];
  1122. };
  1123. #endif
  1124. /**
  1125. * struct reo_queue_ref_table - Reo qref LUT addr
  1126. * @mlo_reo_qref_table_vaddr: MLO table vaddr
  1127. * @non_mlo_reo_qref_table_vaddr: Non MLO table vaddr
  1128. * @mlo_reo_qref_table_paddr: MLO table paddr
  1129. * @non_mlo_reo_qref_table_paddr: Non MLO table paddr
  1130. * @reo_qref_table_en: Enable flag
  1131. */
  1132. struct reo_queue_ref_table {
  1133. uint64_t *mlo_reo_qref_table_vaddr;
  1134. uint64_t *non_mlo_reo_qref_table_vaddr;
  1135. qdf_dma_addr_t mlo_reo_qref_table_paddr;
  1136. qdf_dma_addr_t non_mlo_reo_qref_table_paddr;
  1137. uint8_t reo_qref_table_en;
  1138. };
  1139. /**
  1140. * union hal_shadow_reg_cfg - Shadow register config
  1141. * @addr: Place holder where shadow address is saved
  1142. * @v2: shadow config v2 format
  1143. * @v3: shadow config v3 format
  1144. */
  1145. union hal_shadow_reg_cfg {
  1146. uint32_t addr;
  1147. struct pld_shadow_reg_v2_cfg v2;
  1148. #ifdef CONFIG_SHADOW_V3
  1149. struct pld_shadow_reg_v3_cfg v3;
  1150. #endif
  1151. };
  1152. /**
  1153. * struct hal_soc - HAL context to be used to access SRNG APIs
  1154. * (currently used by data path and
  1155. * transport (CE) modules)
  1156. * @list_shadow_reg_config: array of generic regs mapped to
  1157. * shadow regs
  1158. * @num_generic_shadow_regs_configured: number of generic regs
  1159. * mapped to shadow regs
  1160. */
  1161. struct hal_soc {
  1162. /* HIF handle to access HW registers */
  1163. struct hif_opaque_softc *hif_handle;
  1164. /* QDF device handle */
  1165. qdf_device_t qdf_dev;
  1166. /* Device base address */
  1167. void *dev_base_addr;
  1168. /* Device base address for ce - qca5018 target */
  1169. void *dev_base_addr_ce;
  1170. /* HAL internal state for all SRNG rings.
  1171. * TODO: See if this is required
  1172. */
  1173. struct hal_srng srng_list[HAL_SRNG_ID_MAX];
  1174. /* Remote pointer memory for HW/FW updates */
  1175. uint32_t *shadow_rdptr_mem_vaddr;
  1176. qdf_dma_addr_t shadow_rdptr_mem_paddr;
  1177. /* Shared memory for ring pointer updates from host to FW */
  1178. uint32_t *shadow_wrptr_mem_vaddr;
  1179. qdf_dma_addr_t shadow_wrptr_mem_paddr;
  1180. /* REO blocking resource index */
  1181. uint8_t reo_res_bitmap;
  1182. uint8_t index;
  1183. uint32_t target_type;
  1184. /* shadow register configuration */
  1185. union hal_shadow_reg_cfg shadow_config[MAX_SHADOW_REGISTERS];
  1186. int num_shadow_registers_configured;
  1187. bool use_register_windowing;
  1188. uint32_t register_window;
  1189. qdf_spinlock_t register_access_lock;
  1190. /* Static window map configuration for multiple window write*/
  1191. bool static_window_map;
  1192. /* srng table */
  1193. struct hal_hw_srng_config *hw_srng_table;
  1194. int32_t hal_hw_reg_offset[SRNG_REGISTER_MAX];
  1195. struct hal_hw_txrx_ops *ops;
  1196. /* Indicate srngs initialization */
  1197. bool init_phase;
  1198. /* Hal level stats */
  1199. struct hal_soc_stats stats;
  1200. #ifdef ENABLE_HAL_REG_WR_HISTORY
  1201. struct hal_reg_write_fail_history *reg_wr_fail_hist;
  1202. #endif
  1203. #ifdef FEATURE_HAL_DELAYED_REG_WRITE
  1204. /* queue(array) to hold register writes */
  1205. struct hal_reg_write_q_elem *reg_write_queue;
  1206. /* delayed work to be queued into workqueue */
  1207. qdf_work_t reg_write_work;
  1208. /* workqueue for delayed register writes */
  1209. qdf_workqueue_t *reg_write_wq;
  1210. /* write index used by caller to enqueue delayed work */
  1211. qdf_atomic_t write_idx;
  1212. /* read index used by worker thread to dequeue/write registers */
  1213. uint32_t read_idx;
  1214. #endif /*FEATURE_HAL_DELAYED_REG_WRITE */
  1215. qdf_atomic_t active_work_cnt;
  1216. #ifdef GENERIC_SHADOW_REGISTER_ACCESS_ENABLE
  1217. struct shadow_reg_config
  1218. list_shadow_reg_config[MAX_GENERIC_SHADOW_REG];
  1219. int num_generic_shadow_regs_configured;
  1220. #endif
  1221. /* flag to indicate cmn dmac rings in berryllium */
  1222. bool dmac_cmn_src_rxbuf_ring;
  1223. /* Reo queue ref table items */
  1224. struct reo_queue_ref_table reo_qref;
  1225. };
  1226. #if defined(FEATURE_HAL_DELAYED_REG_WRITE)
  1227. /**
  1228. * hal_delayed_reg_write() - delayed regiter write
  1229. * @hal_soc: HAL soc handle
  1230. * @srng: hal srng
  1231. * @addr: iomem address
  1232. * @value: value to be written
  1233. *
  1234. * Return: none
  1235. */
  1236. void hal_delayed_reg_write(struct hal_soc *hal_soc,
  1237. struct hal_srng *srng,
  1238. void __iomem *addr,
  1239. uint32_t value);
  1240. #endif
  1241. void hal_qca6750_attach(struct hal_soc *hal_soc);
  1242. void hal_qca6490_attach(struct hal_soc *hal_soc);
  1243. void hal_qca6390_attach(struct hal_soc *hal_soc);
  1244. void hal_qca6290_attach(struct hal_soc *hal_soc);
  1245. void hal_qca8074_attach(struct hal_soc *hal_soc);
  1246. void hal_kiwi_attach(struct hal_soc *hal_soc);
  1247. void hal_qcn9224_attach(struct hal_soc *hal_soc);
  1248. /*
  1249. * hal_soc_to_dp_hal_roc - API to convert hal_soc to opaque
  1250. * dp_hal_soc handle type
  1251. * @hal_soc - hal_soc type
  1252. *
  1253. * Return: hal_soc_handle_t type
  1254. */
  1255. static inline
  1256. hal_soc_handle_t hal_soc_to_hal_soc_handle(struct hal_soc *hal_soc)
  1257. {
  1258. return (hal_soc_handle_t)hal_soc;
  1259. }
  1260. /*
  1261. * hal_srng_to_hal_ring_handle - API to convert hal_srng to opaque
  1262. * dp_hal_ring handle type
  1263. * @hal_srng - hal_srng type
  1264. *
  1265. * Return: hal_ring_handle_t type
  1266. */
  1267. static inline
  1268. hal_ring_handle_t hal_srng_to_hal_ring_handle(struct hal_srng *hal_srng)
  1269. {
  1270. return (hal_ring_handle_t)hal_srng;
  1271. }
  1272. /*
  1273. * hal_ring_handle_to_hal_srng - API to convert dp_hal_ring to hal_srng handle
  1274. * @hal_ring - hal_ring_handle_t type
  1275. *
  1276. * Return: hal_srng pointer type
  1277. */
  1278. static inline
  1279. struct hal_srng *hal_ring_handle_to_hal_srng(hal_ring_handle_t hal_ring)
  1280. {
  1281. return (struct hal_srng *)hal_ring;
  1282. }
  1283. /* Size of REO queue reference table in Host
  1284. * 2k peers * 17 tids * 8bytes(rx_reo_queue_reference)
  1285. * = 278528 bytes
  1286. */
  1287. #define REO_QUEUE_REF_NON_ML_TABLE_SIZE 278528
  1288. /* Calculated based on 512 MLO peers */
  1289. #define REO_QUEUE_REF_ML_TABLE_SIZE 69632
  1290. #define HAL_ML_PEER_ID_START 0x2000
  1291. #define HAL_PEER_ID_IS_MLO(peer_id) ((peer_id) & HAL_ML_PEER_ID_START)
  1292. /*
  1293. * REO2PPE destination indication
  1294. */
  1295. #define REO2PPE_DST_IND 11
  1296. /**
  1297. * enum hal_pkt_type - Type of packet type reported by HW
  1298. * @HAL_DOT11A: 802.11a PPDU type
  1299. * @HAL_DOT11B: 802.11b PPDU type
  1300. * @HAL_DOT11N_MM: 802.11n Mixed Mode PPDU type
  1301. * @HAL_DOT11AC: 802.11ac PPDU type
  1302. * @HAL_DOT11AX: 802.11ax PPDU type
  1303. * @HAL_DOT11BA: 802.11ba (WUR) PPDU type
  1304. * @HAL_DOT11BE: 802.11be PPDU type
  1305. * @HAL_DOT11AZ: 802.11az (ranging) PPDU type
  1306. * @HAL_DOT11N_GF: 802.11n Green Field PPDU type
  1307. *
  1308. * Enum indicating the packet type reported by HW in rx_pkt_tlvs (RX data)
  1309. * or WBM2SW ring entry's descriptor (TX data completion)
  1310. */
  1311. enum hal_pkt_type {
  1312. HAL_DOT11A = 0,
  1313. HAL_DOT11B = 1,
  1314. HAL_DOT11N_MM = 2,
  1315. HAL_DOT11AC = 3,
  1316. HAL_DOT11AX = 4,
  1317. HAL_DOT11BA = 5,
  1318. HAL_DOT11BE = 6,
  1319. HAL_DOT11AZ = 7,
  1320. HAL_DOT11N_GF = 8,
  1321. HAL_DOT11_MAX,
  1322. };
  1323. #endif /* _HAL_INTERNAL_H_ */