hal_be_tx.h 29 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #ifndef _HAL_BE_TX_H_
  20. #define _HAL_BE_TX_H_
  21. #include "hal_be_hw_headers.h"
  22. #include "hal_tx.h"
  23. /* Number of TX banks reserved i.e, will not be used by host driver. */
  24. /* MAX_TCL_BANK reserved for FW use */
  25. #define HAL_TX_NUM_RESERVED_BANKS 1
  26. /*
  27. * Number of Priority to TID mapping
  28. */
  29. #define HAL_BE_TX_MAP0_PRI2TID_MAX 10
  30. #define HAL_BE_TX_MAP1_PRI2TID_MAX 6
  31. enum hal_be_tx_ret_buf_manager {
  32. HAL_BE_WBM_SW0_BM_ID = 5,
  33. HAL_BE_WBM_SW1_BM_ID = 6,
  34. HAL_BE_WBM_SW2_BM_ID = 7,
  35. HAL_BE_WBM_SW3_BM_ID = 8,
  36. HAL_BE_WBM_SW4_BM_ID = 9,
  37. HAL_BE_WBM_SW5_BM_ID = 10,
  38. HAL_BE_WBM_SW6_BM_ID = 11,
  39. };
  40. enum hal_tx_mcast_ctrl {
  41. /* mcast traffic exceptioned to FW
  42. * valid only for AP VAP default for AP
  43. */
  44. HAL_TX_MCAST_CTRL_FW_EXCEPTION = 0,
  45. /* mcast traffic dropped in TCL*/
  46. HAL_TX_MCAST_CTRL_DROP,
  47. /* MEC notification are enabled
  48. * valid only for client VAP
  49. */
  50. HAL_TX_MCAST_CTRL_MEC_NOTIFY,
  51. /* no special routing for mcast
  52. * valid for client vap when index search is enabled
  53. */
  54. HAL_TX_MCAST_CTRL_NO_SPECIAL,
  55. };
  56. /* enum hal_tx_notify_frame_type - TX notify frame type
  57. * @NO_TX_NOTIFY: Not a notify frame
  58. * @TX_HARD_NOTIFY: Hard notify TX frame
  59. * @TX_SOFT_NOTIFY_E: Soft Notify Tx frame
  60. * @TX_SEMI_HARD_NOTIFY_E: Semi Hard notify TX frame
  61. */
  62. enum hal_tx_notify_frame_type {
  63. NO_TX_NOTIFY = 0,
  64. TX_HARD_NOTIFY = 1,
  65. TX_SOFT_NOTIFY_E = 2,
  66. TX_SEMI_HARD_NOTIFY_E = 3
  67. };
  68. /*---------------------------------------------------------------------------
  69. * Structures
  70. * ---------------------------------------------------------------------------
  71. */
  72. /**
  73. * struct hal_tx_bank_config - SW config bank params
  74. * @epd: EPD indication flag
  75. * @encap_type: encapsulation type
  76. * @encrypt_type: encrypt type
  77. * @src_buffer_swap: big-endia switch for packet buffer
  78. * @link_meta_swap: big-endian switch for link metadata
  79. * @index_lookup_enable: Enabel index lookup
  80. * @addrx_en: Address-X search
  81. * @addry_en: Address-Y search
  82. * @mesh_enable:mesh enable flag
  83. * @vdev_id_check_en: vdev id check
  84. * @pmac_id: mac id
  85. * @mcast_pkt_ctrl: mulitcast packet control
  86. * @val: value representing bank config
  87. */
  88. union hal_tx_bank_config {
  89. struct {
  90. uint32_t epd:1,
  91. encap_type:2,
  92. encrypt_type:4,
  93. src_buffer_swap:1,
  94. link_meta_swap:1,
  95. index_lookup_enable:1,
  96. addrx_en:1,
  97. addry_en:1,
  98. mesh_enable:2,
  99. vdev_id_check_en:1,
  100. pmac_id:2,
  101. mcast_pkt_ctrl:2,
  102. dscp_tid_map_id:6,
  103. reserved:7;
  104. };
  105. uint32_t val;
  106. };
  107. /**
  108. * struct hal_tx_cmn_config_ppe - SW config exception related parameters
  109. * @drop_prec_err - Exception drop_prec errors.
  110. * @fake_mac_hdr - Exception fake mac header.
  111. * @cpu_code_inv - Exception cpu code invalid.
  112. * @data_buff_err - Exception buffer length/offset erorors.
  113. * @l3_l4_err - Exception m3_l4 checksum errors
  114. * @data_offset_max - Maximum data offset allowed.
  115. * @data_len_max - Maximum data length allowed.
  116. */
  117. union hal_tx_cmn_config_ppe {
  118. struct {
  119. uint32_t drop_prec_err:1,
  120. fake_mac_hdr:1,
  121. cpu_code_inv:1,
  122. data_buff_err:1,
  123. l3_l4_err:1,
  124. data_offset_max:12,
  125. data_len_max:14;
  126. };
  127. uint32_t val;
  128. };
  129. /**
  130. * hal_tx_ppe_vp_config - SW config PPE VP table
  131. * @vp_num - Virtual port number
  132. * @pmac_id - Lmac ID
  133. * @bank_id: Bank ID correspondig to this I/F.
  134. * @vdev_id: VDEV ID of the I/F.
  135. * @search_idx_reg_num: Register number of this SI.
  136. * @use_ppe_int_pri: Use the PPE INT_PRI to TID table
  137. * @to_fw: Use FW
  138. * @drop_prec_enable: Enable precendance drop.
  139. */
  140. union hal_tx_ppe_vp_config {
  141. struct {
  142. uint32_t vp_num:8,
  143. pmac_id:2,
  144. bank_id:6,
  145. vdev_id:8,
  146. search_idx_reg_num:3,
  147. use_ppe_int_pri:1,
  148. to_fw:1,
  149. drop_prec_enable:1;
  150. };
  151. uint32_t val;
  152. };
  153. /**
  154. * hal_tx_cmn_ppe_idx_map_config: Use ppe index mapping table
  155. * @search_idx: Search index
  156. * @cache_set: Cache set number
  157. */
  158. union hal_tx_ppe_idx_map_config {
  159. struct {
  160. uint32_t search_idx:20,
  161. cache_set:4;
  162. };
  163. uint32_t val;
  164. };
  165. /**
  166. * hal_tx_ppe_pri2tid_map0_config : Configure ppe INT_PRI to tid map
  167. * @int_pri0: INT_PRI_0
  168. * @int_pri1: INT_PRI_1
  169. * @int_pri2: INT_PRI_2
  170. * @int_pri3: INT_PRI_3
  171. * @int_pri4: INT_PRI_4
  172. * @int_pri5: INT_PRI_5
  173. * @int_pri6: INT_PRI_6
  174. * @int_pri7: INT_PRI_7
  175. * @int_pri8: INT_PRI_8
  176. * @int_pri9: INT_PRI_9
  177. */
  178. union hal_tx_ppe_pri2tid_map0_config {
  179. struct {
  180. uint32_t int_pri0:3,
  181. int_pri1:3,
  182. int_pri2:3,
  183. int_pri3:3,
  184. int_pri4:3,
  185. int_pri5:3,
  186. int_pri6:3,
  187. int_pri7:3,
  188. int_pri8:3,
  189. int_pri9:3;
  190. };
  191. uint32_t val;
  192. };
  193. /**
  194. * hal_tx_ppe_pri2tid_map1_config : Configure ppe INT_PRI to tid map
  195. * @int_pri0: INT_PRI_10
  196. * @int_pri1: INT_PRI_11
  197. * @int_pri2: INT_PRI_12
  198. * @int_pri3: INT_PRI_13
  199. * @int_pri4: INT_PRI_14
  200. * @int_pri5: INT_PRI_15
  201. */
  202. union hal_tx_ppe_pri2tid_map1_config {
  203. struct {
  204. uint32_t int_pri10:3,
  205. int_pri11:3,
  206. int_pri12:3,
  207. int_pri13:3,
  208. int_pri14:3,
  209. int_pri15:3;
  210. };
  211. uint32_t val;
  212. };
  213. /*---------------------------------------------------------------------------
  214. * Function declarations and documentation
  215. * ---------------------------------------------------------------------------
  216. */
  217. /*---------------------------------------------------------------------------
  218. * TCL Descriptor accessor APIs
  219. *---------------------------------------------------------------------------
  220. */
  221. /**
  222. * hal_tx_desc_set_tx_notify_frame - Set TX notify_frame field in Tx desc
  223. * @desc: Handle to Tx Descriptor
  224. * @val: Value to be set
  225. *
  226. * Return: None
  227. */
  228. static inline void hal_tx_desc_set_tx_notify_frame(void *desc,
  229. uint8_t val)
  230. {
  231. HAL_SET_FLD(desc, TCL_DATA_CMD, TX_NOTIFY_FRAME) |=
  232. HAL_TX_SM(TCL_DATA_CMD, TX_NOTIFY_FRAME, val);
  233. }
  234. /**
  235. * hal_tx_desc_set_flow_override_enable - Set flow_override_enable field
  236. * @desc: Handle to Tx Descriptor
  237. * @val: Value to be set
  238. *
  239. * Return: None
  240. */
  241. static inline void hal_tx_desc_set_flow_override_enable(void *desc,
  242. uint8_t val)
  243. {
  244. HAL_SET_FLD(desc, TCL_DATA_CMD, FLOW_OVERRIDE_ENABLE) |=
  245. HAL_TX_SM(TCL_DATA_CMD, FLOW_OVERRIDE_ENABLE, val);
  246. }
  247. /**
  248. * hal_tx_desc_set_flow_override - Set flow_override field in TX desc
  249. * @desc: Handle to Tx Descriptor
  250. * @val: Value to be set
  251. *
  252. * Return: None
  253. */
  254. static inline void hal_tx_desc_set_flow_override(void *desc,
  255. uint8_t val)
  256. {
  257. HAL_SET_FLD(desc, TCL_DATA_CMD, FLOW_OVERRIDE) |=
  258. HAL_TX_SM(TCL_DATA_CMD, FLOW_OVERRIDE, val);
  259. }
  260. /**
  261. * hal_tx_desc_set_who_classify_info_sel - Set who_classify_info_sel field
  262. * @desc: Handle to Tx Descriptor
  263. * @val: Value to be set
  264. *
  265. * Return: None
  266. */
  267. static inline void hal_tx_desc_set_who_classify_info_sel(void *desc,
  268. uint8_t val)
  269. {
  270. HAL_SET_FLD(desc, TCL_DATA_CMD, WHO_CLASSIFY_INFO_SEL) |=
  271. HAL_TX_SM(TCL_DATA_CMD, WHO_CLASSIFY_INFO_SEL, val);
  272. }
  273. /**
  274. * hal_tx_desc_set_buf_length - Set Data length in bytes in Tx Descriptor
  275. * @desc: Handle to Tx Descriptor
  276. * @data_length: MSDU length in case of direct descriptor.
  277. * Length of link extension descriptor in case of Link extension
  278. * descriptor.Includes the length of Metadata
  279. * Return: None
  280. */
  281. static inline void hal_tx_desc_set_buf_length(void *desc,
  282. uint16_t data_length)
  283. {
  284. HAL_SET_FLD(desc, TCL_DATA_CMD, DATA_LENGTH) |=
  285. HAL_TX_SM(TCL_DATA_CMD, DATA_LENGTH, data_length);
  286. }
  287. /**
  288. * hal_tx_desc_set_buf_offset - Sets Packet Offset field in Tx descriptor
  289. * @desc: Handle to Tx Descriptor
  290. * @offset: Packet offset from Metadata in case of direct buffer descriptor.
  291. *
  292. * Return: void
  293. */
  294. static inline void hal_tx_desc_set_buf_offset(void *desc,
  295. uint8_t offset)
  296. {
  297. HAL_SET_FLD(desc, TCL_DATA_CMD, PACKET_OFFSET) |=
  298. HAL_TX_SM(TCL_DATA_CMD, PACKET_OFFSET, offset);
  299. }
  300. /**
  301. * hal_tx_desc_set_l4_checksum_en - Set TCP/IP checksum enable flags
  302. * Tx Descriptor for MSDU_buffer type
  303. * @desc: Handle to Tx Descriptor
  304. * @en: UDP/TCP over ipv4/ipv6 checksum enable flags (5 bits)
  305. *
  306. * Return: void
  307. */
  308. static inline void hal_tx_desc_set_l4_checksum_en(void *desc,
  309. uint8_t en)
  310. {
  311. HAL_SET_FLD(desc, TCL_DATA_CMD, IPV4_CHECKSUM_EN) |=
  312. (HAL_TX_SM(TCL_DATA_CMD, UDP_OVER_IPV4_CHECKSUM_EN, en) |
  313. HAL_TX_SM(TCL_DATA_CMD, UDP_OVER_IPV6_CHECKSUM_EN, en) |
  314. HAL_TX_SM(TCL_DATA_CMD, TCP_OVER_IPV4_CHECKSUM_EN, en) |
  315. HAL_TX_SM(TCL_DATA_CMD, TCP_OVER_IPV6_CHECKSUM_EN, en));
  316. }
  317. /**
  318. * hal_tx_desc_set_l3_checksum_en - Set IPv4 checksum enable flag in
  319. * Tx Descriptor for MSDU_buffer type
  320. * @desc: Handle to Tx Descriptor
  321. * @checksum_en_flags: ipv4 checksum enable flags
  322. *
  323. * Return: void
  324. */
  325. static inline void hal_tx_desc_set_l3_checksum_en(void *desc,
  326. uint8_t en)
  327. {
  328. HAL_SET_FLD(desc, TCL_DATA_CMD, IPV4_CHECKSUM_EN) |=
  329. HAL_TX_SM(TCL_DATA_CMD, IPV4_CHECKSUM_EN, en);
  330. }
  331. /**
  332. * hal_tx_desc_set_fw_metadata- Sets the metadata that is part of TCL descriptor
  333. * @desc:Handle to Tx Descriptor
  334. * @metadata: Metadata to be sent to Firmware
  335. *
  336. * Return: void
  337. */
  338. static inline void hal_tx_desc_set_fw_metadata(void *desc,
  339. uint16_t metadata)
  340. {
  341. HAL_SET_FLD(desc, TCL_DATA_CMD, TCL_CMD_NUMBER) |=
  342. HAL_TX_SM(TCL_DATA_CMD, TCL_CMD_NUMBER, metadata);
  343. }
  344. /**
  345. * hal_tx_desc_set_to_fw - Set To_FW bit in Tx Descriptor.
  346. * @desc:Handle to Tx Descriptor
  347. * @to_fw: if set, Forward packet to FW along with classification result
  348. *
  349. * Return: void
  350. */
  351. static inline void hal_tx_desc_set_to_fw(void *desc, uint8_t to_fw)
  352. {
  353. HAL_SET_FLD(desc, TCL_DATA_CMD, TO_FW) |=
  354. HAL_TX_SM(TCL_DATA_CMD, TO_FW, to_fw);
  355. }
  356. /**
  357. * hal_tx_desc_set_hlos_tid - Set the TID value (override DSCP/PCP fields in
  358. * frame) to be used for Tx Frame
  359. * @desc: Handle to Tx Descriptor
  360. * @hlos_tid: HLOS TID
  361. *
  362. * Return: void
  363. */
  364. static inline void hal_tx_desc_set_hlos_tid(void *desc,
  365. uint8_t hlos_tid)
  366. {
  367. HAL_SET_FLD(desc, TCL_DATA_CMD, HLOS_TID) |=
  368. HAL_TX_SM(TCL_DATA_CMD, HLOS_TID, hlos_tid);
  369. HAL_SET_FLD(desc, TCL_DATA_CMD, HLOS_TID_OVERWRITE) |=
  370. HAL_TX_SM(TCL_DATA_CMD, HLOS_TID_OVERWRITE, 1);
  371. }
  372. /**
  373. * hal_tx_desc_sync - Commit the descriptor to Hardware
  374. * @hal_tx_des_cached: Cached descriptor that software maintains
  375. * @hw_desc: Hardware descriptor to be updated
  376. */
  377. static inline void hal_tx_desc_sync(void *hal_tx_desc_cached,
  378. void *hw_desc)
  379. {
  380. qdf_mem_copy(hw_desc, hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
  381. }
  382. /**
  383. * hal_tx_desc_set_vdev_id - set vdev id to the descriptor to Hardware
  384. * @hal_tx_des_cached: Cached descriptor that software maintains
  385. * @vdev_id: vdev id
  386. */
  387. static inline void hal_tx_desc_set_vdev_id(void *desc, uint8_t vdev_id)
  388. {
  389. HAL_SET_FLD(desc, TCL_DATA_CMD, VDEV_ID) |=
  390. HAL_TX_SM(TCL_DATA_CMD, VDEV_ID, vdev_id);
  391. }
  392. /**
  393. * hal_tx_desc_set_bank_id - set bank id to the descriptor to Hardware
  394. * @hal_tx_des_cached: Cached descriptor that software maintains
  395. * @bank_id: bank id
  396. */
  397. static inline void hal_tx_desc_set_bank_id(void *desc, uint8_t bank_id)
  398. {
  399. HAL_SET_FLD(desc, TCL_DATA_CMD, BANK_ID) |=
  400. HAL_TX_SM(TCL_DATA_CMD, BANK_ID, bank_id);
  401. }
  402. /**
  403. * hal_tx_desc_set_tcl_cmd_type - set tcl command type to the descriptor
  404. * to Hardware
  405. * @hal_tx_des_cached: Cached descriptor that software maintains
  406. * @tcl_cmd_type: tcl command type
  407. */
  408. static inline void
  409. hal_tx_desc_set_tcl_cmd_type(void *desc, uint8_t tcl_cmd_type)
  410. {
  411. HAL_SET_FLD(desc, TCL_DATA_CMD, TCL_CMD_TYPE) |=
  412. HAL_TX_SM(TCL_DATA_CMD, TCL_CMD_TYPE, tcl_cmd_type);
  413. }
  414. /**
  415. * hal_tx_desc_set_lmac_id_be - set lmac id to the descriptor to Hardware
  416. * @hal_soc_hdl: hal soc handle
  417. * @hal_tx_des_cached: Cached descriptor that software maintains
  418. * @lmac_id: lmac id
  419. */
  420. static inline void
  421. hal_tx_desc_set_lmac_id_be(hal_soc_handle_t hal_soc_hdl, void *desc,
  422. uint8_t lmac_id)
  423. {
  424. HAL_SET_FLD(desc, TCL_DATA_CMD, PMAC_ID) |=
  425. HAL_TX_SM(TCL_DATA_CMD, PMAC_ID, lmac_id);
  426. }
  427. /**
  428. * hal_tx_desc_set_search_index_be - set search index to the
  429. * descriptor to Hardware
  430. * @hal_soc_hdl: hal soc handle
  431. * @hal_tx_des_cached: Cached descriptor that software maintains
  432. * @search_index: search index
  433. */
  434. static inline void
  435. hal_tx_desc_set_search_index_be(hal_soc_handle_t hal_soc_hdl, void *desc,
  436. uint32_t search_index)
  437. {
  438. HAL_SET_FLD(desc, TCL_DATA_CMD, SEARCH_INDEX) |=
  439. HAL_TX_SM(TCL_DATA_CMD, SEARCH_INDEX, search_index);
  440. }
  441. /**
  442. * hal_tx_desc_set_cache_set_num - set cache set num to the
  443. * descriptor to Hardware
  444. * @hal_soc_hdl: hal soc handle
  445. * @hal_tx_des_cached: Cached descriptor that software maintains
  446. * @cache_num: cache number
  447. */
  448. static inline void
  449. hal_tx_desc_set_cache_set_num(hal_soc_handle_t hal_soc_hdl, void *desc,
  450. uint8_t cache_num)
  451. {
  452. HAL_SET_FLD(desc, TCL_DATA_CMD, CACHE_SET_NUM) |=
  453. HAL_TX_SM(TCL_DATA_CMD, CACHE_SET_NUM, cache_num);
  454. }
  455. /*---------------------------------------------------------------------------
  456. * WBM Descriptor accessor APIs for Tx completions
  457. * ---------------------------------------------------------------------------
  458. */
  459. /**
  460. * hal_tx_get_wbm_sw0_bm_id() - Get the BM ID for first tx completion ring
  461. *
  462. * Return: BM ID for first tx completion ring
  463. */
  464. static inline uint32_t hal_tx_get_wbm_sw0_bm_id(void)
  465. {
  466. return HAL_BE_WBM_SW0_BM_ID;
  467. }
  468. /**
  469. * hal_tx_comp_get_desc_id() - Get TX descriptor id within comp descriptor
  470. * @hal_desc: completion ring descriptor pointer
  471. *
  472. * This function will tx descriptor id, cookie, within hardware completion
  473. * descriptor. For cases when cookie conversion is disabled, the sw_cookie
  474. * is present in the 2nd DWORD.
  475. *
  476. * Return: cookie
  477. */
  478. static inline uint32_t hal_tx_comp_get_desc_id(void *hal_desc)
  479. {
  480. uint32_t comp_desc =
  481. *(uint32_t *)(((uint8_t *)hal_desc) +
  482. BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET);
  483. /* Cookie is placed on 2nd word */
  484. return (comp_desc & BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK) >>
  485. BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB;
  486. }
  487. /**
  488. * hal_tx_comp_get_paddr() - Get paddr within comp descriptor
  489. * @hal_desc: completion ring descriptor pointer
  490. *
  491. * This function will get buffer physical address within hardware completion
  492. * descriptor
  493. *
  494. * Return: Buffer physical address
  495. */
  496. static inline qdf_dma_addr_t hal_tx_comp_get_paddr(void *hal_desc)
  497. {
  498. uint32_t paddr_lo;
  499. uint32_t paddr_hi;
  500. paddr_lo = *(uint32_t *)(((uint8_t *)hal_desc) +
  501. BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET);
  502. paddr_hi = *(uint32_t *)(((uint8_t *)hal_desc) +
  503. BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET);
  504. paddr_hi = (paddr_hi & BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK) >>
  505. BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB;
  506. return (qdf_dma_addr_t)(paddr_lo | (((uint64_t)paddr_hi) << 32));
  507. }
  508. #ifdef DP_HW_COOKIE_CONVERT_EXCEPTION
  509. /* HW set dowrd-2 bit30 to 1 if HW CC is done */
  510. #define HAL_WBM2SW_COMPLETION_RING_TX_CC_DONE_OFFSET 0x8
  511. #define HAL_WBM2SW_COMPLETION_RING_TX_CC_DONE_MASK 0x40000000
  512. #define HAL_WBM2SW_COMPLETION_RING_TX_CC_DONE_LSB 0x1E
  513. /**
  514. * hal_tx_comp_get_cookie_convert_done() - Get cookie conversion done flag
  515. * @hal_desc: completion ring descriptor pointer
  516. *
  517. * This function will get the bit value that indicate HW cookie
  518. * conversion done or not
  519. *
  520. * Return: 1 - HW cookie conversion done, 0 - not
  521. */
  522. static inline uint8_t hal_tx_comp_get_cookie_convert_done(void *hal_desc)
  523. {
  524. return HAL_TX_DESC_GET(hal_desc, HAL_WBM2SW_COMPLETION_RING_TX,
  525. CC_DONE);
  526. }
  527. #endif
  528. /**
  529. * hal_tx_comp_get_desc_va() - Get Desc virtual address within completion Desc
  530. * @hal_desc: completion ring descriptor pointer
  531. *
  532. * This function will get the TX Desc virtual address
  533. *
  534. * Return: TX desc virtual address
  535. */
  536. static inline uintptr_t hal_tx_comp_get_desc_va(void *hal_desc)
  537. {
  538. uint64_t va_from_desc;
  539. va_from_desc = HAL_TX_DESC_GET(hal_desc,
  540. WBM2SW_COMPLETION_RING_TX,
  541. BUFFER_VIRT_ADDR_31_0) |
  542. (((uint64_t)HAL_TX_DESC_GET(
  543. hal_desc,
  544. WBM2SW_COMPLETION_RING_TX,
  545. BUFFER_VIRT_ADDR_63_32)) << 32);
  546. return (uintptr_t)va_from_desc;
  547. }
  548. /*---------------------------------------------------------------------------
  549. * TX BANK register accessor APIs
  550. * ---------------------------------------------------------------------------
  551. */
  552. /**
  553. * hal_tx_get_num_tcl_banks() - Get number of banks for target
  554. *
  555. * Return: None
  556. */
  557. static inline uint8_t
  558. hal_tx_get_num_tcl_banks(hal_soc_handle_t hal_soc_hdl)
  559. {
  560. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  561. int hal_banks = 0;
  562. if (hal_soc->ops->hal_tx_get_num_tcl_banks) {
  563. hal_banks = hal_soc->ops->hal_tx_get_num_tcl_banks();
  564. hal_banks -= HAL_TX_NUM_RESERVED_BANKS;
  565. hal_banks = (hal_banks < 0) ? 0 : hal_banks;
  566. }
  567. return hal_banks;
  568. }
  569. /**
  570. * hal_tx_populate_bank_register() - populate the bank register with
  571. * the software configs.
  572. * @soc: HAL soc handle
  573. * @config: bank config
  574. * @bank_id: bank id to be configured
  575. *
  576. * Returns: None
  577. */
  578. #ifdef HWIO_TCL_R0_SW_CONFIG_BANK_n_MCAST_PACKET_CTRL_SHFT
  579. static inline void
  580. hal_tx_populate_bank_register(hal_soc_handle_t hal_soc_hdl,
  581. union hal_tx_bank_config *config,
  582. uint8_t bank_id)
  583. {
  584. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  585. uint32_t reg_addr, reg_val = 0;
  586. reg_addr = HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(MAC_TCL_REG_REG_BASE,
  587. bank_id);
  588. reg_val |= (config->epd << HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT);
  589. reg_val |= (config->encap_type <<
  590. HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_SHFT);
  591. reg_val |= (config->encrypt_type <<
  592. HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_SHFT);
  593. reg_val |= (config->src_buffer_swap <<
  594. HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_SHFT);
  595. reg_val |= (config->link_meta_swap <<
  596. HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_SHFT);
  597. reg_val |= (config->index_lookup_enable <<
  598. HWIO_TCL_R0_SW_CONFIG_BANK_n_INDEX_LOOKUP_ENABLE_SHFT);
  599. reg_val |= (config->addrx_en <<
  600. HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRX_EN_SHFT);
  601. reg_val |= (config->addry_en <<
  602. HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRY_EN_SHFT);
  603. reg_val |= (config->mesh_enable <<
  604. HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_SHFT);
  605. reg_val |= (config->vdev_id_check_en <<
  606. HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_SHFT);
  607. reg_val |= (config->pmac_id <<
  608. HWIO_TCL_R0_SW_CONFIG_BANK_n_PMAC_ID_SHFT);
  609. reg_val |= (config->mcast_pkt_ctrl <<
  610. HWIO_TCL_R0_SW_CONFIG_BANK_n_MCAST_PACKET_CTRL_SHFT);
  611. HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
  612. }
  613. #else
  614. static inline void
  615. hal_tx_populate_bank_register(hal_soc_handle_t hal_soc_hdl,
  616. union hal_tx_bank_config *config,
  617. uint8_t bank_id)
  618. {
  619. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  620. uint32_t reg_addr, reg_val = 0;
  621. reg_addr = HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(MAC_TCL_REG_REG_BASE,
  622. bank_id);
  623. reg_val |= (config->epd << HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT);
  624. reg_val |= (config->encap_type <<
  625. HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_SHFT);
  626. reg_val |= (config->encrypt_type <<
  627. HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_SHFT);
  628. reg_val |= (config->src_buffer_swap <<
  629. HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_SHFT);
  630. reg_val |= (config->link_meta_swap <<
  631. HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_SHFT);
  632. reg_val |= (config->index_lookup_enable <<
  633. HWIO_TCL_R0_SW_CONFIG_BANK_n_INDEX_LOOKUP_ENABLE_SHFT);
  634. reg_val |= (config->addrx_en <<
  635. HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRX_EN_SHFT);
  636. reg_val |= (config->addry_en <<
  637. HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRY_EN_SHFT);
  638. reg_val |= (config->mesh_enable <<
  639. HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_SHFT);
  640. reg_val |= (config->vdev_id_check_en <<
  641. HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_SHFT);
  642. reg_val |= (config->pmac_id <<
  643. HWIO_TCL_R0_SW_CONFIG_BANK_n_PMAC_ID_SHFT);
  644. reg_val |= (config->dscp_tid_map_id <<
  645. HWIO_TCL_R0_SW_CONFIG_BANK_n_DSCP_TID_TABLE_NUM_SHFT);
  646. HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
  647. }
  648. #endif
  649. #ifdef DP_TX_IMPLICIT_RBM_MAPPING
  650. #define RBM_MAPPING_BMSK HWIO_TCL_R0_RBM_MAPPING0_SW2TCL1_RING_BMSK
  651. #define RBM_MAPPING_SHFT HWIO_TCL_R0_RBM_MAPPING0_SW2TCL2_RING_SHFT
  652. #define RBM_PPE2TCL_OFFSET \
  653. (HWIO_TCL_R0_RBM_MAPPING0_PPE2TCL1_RING_SHFT >> 2)
  654. #define RBM_TCL_CMD_CREDIT_OFFSET \
  655. (HWIO_TCL_R0_RBM_MAPPING0_SW2TCL_CREDIT_RING_SHFT >> 2)
  656. /**
  657. * hal_tx_config_rbm_mapping_be() - Update return buffer manager ring id
  658. * @hal_soc: HAL SoC context
  659. * @hal_ring_hdl: Source ring pointer
  660. * @rbm_id: return buffer manager ring id
  661. *
  662. * Return: void
  663. */
  664. static inline void
  665. hal_tx_config_rbm_mapping_be(hal_soc_handle_t hal_soc_hdl,
  666. hal_ring_handle_t hal_ring_hdl,
  667. uint8_t rbm_id)
  668. {
  669. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  670. hal_soc->ops->hal_tx_config_rbm_mapping_be(hal_soc_hdl, hal_ring_hdl,
  671. rbm_id);
  672. }
  673. #else
  674. static inline void
  675. hal_tx_config_rbm_mapping_be(hal_soc_handle_t hal_soc_hdl,
  676. hal_ring_handle_t hal_ring_hdl,
  677. uint8_t rbm_id)
  678. {
  679. }
  680. #endif
  681. /**
  682. * hal_tx_desc_set_buf_addr_be - Fill Buffer Address information in Tx Desc
  683. * @desc: Handle to Tx Descriptor
  684. * @paddr: Physical Address
  685. * @pool_id: Return Buffer Manager ID
  686. * @desc_id: Descriptor ID
  687. * @type: 0 - Address points to a MSDU buffer
  688. * 1 - Address points to MSDU extension descriptor
  689. *
  690. * Return: void
  691. */
  692. #ifdef DP_TX_IMPLICIT_RBM_MAPPING
  693. static inline void
  694. hal_tx_desc_set_buf_addr_be(hal_soc_handle_t hal_soc_hdl, void *desc,
  695. dma_addr_t paddr, uint8_t rbm_id,
  696. uint32_t desc_id, uint8_t type)
  697. {
  698. /* Set buffer_addr_info.buffer_addr_31_0 */
  699. HAL_SET_FLD(desc, TCL_DATA_CMD,
  700. BUF_ADDR_INFO_BUFFER_ADDR_31_0) =
  701. HAL_TX_SM(TCL_DATA_CMD, BUF_ADDR_INFO_BUFFER_ADDR_31_0, paddr);
  702. /* Set buffer_addr_info.buffer_addr_39_32 */
  703. HAL_SET_FLD(desc, TCL_DATA_CMD,
  704. BUF_ADDR_INFO_BUFFER_ADDR_39_32) |=
  705. HAL_TX_SM(TCL_DATA_CMD, BUF_ADDR_INFO_BUFFER_ADDR_39_32,
  706. (((uint64_t)paddr) >> 32));
  707. /* Set buffer_addr_info.sw_buffer_cookie = desc_id */
  708. HAL_SET_FLD(desc, TCL_DATA_CMD,
  709. BUF_ADDR_INFO_SW_BUFFER_COOKIE) |=
  710. HAL_TX_SM(TCL_DATA_CMD, BUF_ADDR_INFO_SW_BUFFER_COOKIE,
  711. desc_id);
  712. /* Set Buffer or Ext Descriptor Type */
  713. HAL_SET_FLD(desc, TCL_DATA_CMD,
  714. BUF_OR_EXT_DESC_TYPE) |=
  715. HAL_TX_SM(TCL_DATA_CMD, BUF_OR_EXT_DESC_TYPE, type);
  716. }
  717. #else
  718. static inline void
  719. hal_tx_desc_set_buf_addr_be(hal_soc_handle_t hal_soc_hdl, void *desc,
  720. dma_addr_t paddr, uint8_t rbm_id,
  721. uint32_t desc_id, uint8_t type)
  722. {
  723. /* Set buffer_addr_info.buffer_addr_31_0 */
  724. HAL_SET_FLD(desc, TCL_DATA_CMD,
  725. BUF_ADDR_INFO_BUFFER_ADDR_31_0) =
  726. HAL_TX_SM(TCL_DATA_CMD, BUF_ADDR_INFO_BUFFER_ADDR_31_0, paddr);
  727. /* Set buffer_addr_info.buffer_addr_39_32 */
  728. HAL_SET_FLD(desc, TCL_DATA_CMD,
  729. BUF_ADDR_INFO_BUFFER_ADDR_39_32) |=
  730. HAL_TX_SM(TCL_DATA_CMD, BUF_ADDR_INFO_BUFFER_ADDR_39_32,
  731. (((uint64_t)paddr) >> 32));
  732. /* Set buffer_addr_info.return_buffer_manager = rbm id */
  733. HAL_SET_FLD(desc, TCL_DATA_CMD,
  734. BUF_ADDR_INFO_RETURN_BUFFER_MANAGER) |=
  735. HAL_TX_SM(TCL_DATA_CMD,
  736. BUF_ADDR_INFO_RETURN_BUFFER_MANAGER, rbm_id);
  737. /* Set buffer_addr_info.sw_buffer_cookie = desc_id */
  738. HAL_SET_FLD(desc, TCL_DATA_CMD,
  739. BUF_ADDR_INFO_SW_BUFFER_COOKIE) |=
  740. HAL_TX_SM(TCL_DATA_CMD, BUF_ADDR_INFO_SW_BUFFER_COOKIE,
  741. desc_id);
  742. /* Set Buffer or Ext Descriptor Type */
  743. HAL_SET_FLD(desc, TCL_DATA_CMD,
  744. BUF_OR_EXT_DESC_TYPE) |=
  745. HAL_TX_SM(TCL_DATA_CMD, BUF_OR_EXT_DESC_TYPE, type);
  746. }
  747. #endif
  748. #ifdef HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_VAL_SHFT
  749. #define HAL_TCL_VDEV_MCAST_PACKET_CTRL_REG_ID(vdev_id) (vdev_id >> 0x4)
  750. #define HAL_TCL_VDEV_MCAST_PACKET_CTRL_INDEX_IN_REG(vdev_id) (vdev_id & 0xF)
  751. #define HAL_TCL_VDEV_MCAST_PACKET_CTRL_MASK 0x3
  752. #define HAL_TCL_VDEV_MCAST_PACKET_CTRL_SHIFT 0x2
  753. /**
  754. * hal_tx_vdev_mcast_ctrl_set - set mcast_ctrl value
  755. * @hal_soc: HAL SoC context
  756. * @mcast_ctrl_val: mcast ctrl value for this VAP
  757. *
  758. * Return: void
  759. */
  760. static inline void
  761. hal_tx_vdev_mcast_ctrl_set(hal_soc_handle_t hal_soc_hdl,
  762. uint8_t vdev_id,
  763. uint8_t mcast_ctrl_val)
  764. {
  765. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  766. uint32_t reg_addr, reg_val = 0;
  767. uint32_t val;
  768. uint8_t reg_idx = HAL_TCL_VDEV_MCAST_PACKET_CTRL_REG_ID(vdev_id);
  769. uint8_t index_in_reg =
  770. HAL_TCL_VDEV_MCAST_PACKET_CTRL_INDEX_IN_REG(vdev_id);
  771. reg_addr =
  772. HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_ADDR(MAC_TCL_REG_REG_BASE,
  773. reg_idx);
  774. val = HAL_REG_READ(hal_soc, reg_addr);
  775. /* mask out other stored value */
  776. val &= (~(HAL_TCL_VDEV_MCAST_PACKET_CTRL_MASK <<
  777. (HAL_TCL_VDEV_MCAST_PACKET_CTRL_SHIFT * index_in_reg)));
  778. reg_val = val |
  779. ((HAL_TCL_VDEV_MCAST_PACKET_CTRL_MASK & mcast_ctrl_val) <<
  780. (HAL_TCL_VDEV_MCAST_PACKET_CTRL_SHIFT * index_in_reg));
  781. HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
  782. }
  783. #else
  784. static inline void
  785. hal_tx_vdev_mcast_ctrl_set(hal_soc_handle_t hal_soc_hdl,
  786. uint8_t vdev_id,
  787. uint8_t mcast_ctrl_val)
  788. {
  789. }
  790. #endif
  791. /**
  792. * hal_tx_vdev_mismatch_routing_set - set vdev mismatch exception routing
  793. * @hal_soc: HAL SoC context
  794. * @config: HAL_TX_VDEV_MISMATCH_TQM_NOTIFY - route via TQM
  795. * HAL_TX_VDEV_MISMATCH_FW_NOTIFY - route via FW
  796. *
  797. * Return: void
  798. */
  799. #ifdef HWIO_TCL_R0_CMN_CONFIG_VDEVID_MISMATCH_EXCEPTION_BMSK
  800. static inline void
  801. hal_tx_vdev_mismatch_routing_set(hal_soc_handle_t hal_soc_hdl,
  802. enum hal_tx_vdev_mismatch_notify config)
  803. {
  804. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  805. hal_soc->ops->hal_tx_vdev_mismatch_routing_set(hal_soc_hdl, config);
  806. }
  807. #else
  808. static inline void
  809. hal_tx_vdev_mismatch_routing_set(hal_soc_handle_t hal_soc_hdl,
  810. enum hal_tx_vdev_mismatch_notify config)
  811. {
  812. }
  813. #endif
  814. /**
  815. * hal_tx_mcast_mlo_reinject_routing_set - set MLO multicast reinject routing
  816. * @hal_soc: HAL SoC context
  817. * @config: HAL_TX_MCAST_MLO_REINJECT_FW_NOTIFY - route via FW
  818. * HAL_TX_MCAST_MLO_REINJECT_TQM_NOTIFY - route via TQM
  819. *
  820. * Return: void
  821. */
  822. #if defined(HWIO_TCL_R0_CMN_CONFIG_MCAST_CMN_PN_SN_MLO_REINJECT_ENABLE_BMSK) && \
  823. defined(WLAN_MCAST_MLO)
  824. static inline void
  825. hal_tx_mcast_mlo_reinject_routing_set(
  826. hal_soc_handle_t hal_soc_hdl,
  827. enum hal_tx_mcast_mlo_reinject_notify config)
  828. {
  829. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  830. hal_soc->ops->hal_tx_mcast_mlo_reinject_routing_set(hal_soc_hdl,
  831. config);
  832. }
  833. #else
  834. static inline void
  835. hal_tx_mcast_mlo_reinject_routing_set(
  836. hal_soc_handle_t hal_soc_hdl,
  837. enum hal_tx_mcast_mlo_reinject_notify config)
  838. {
  839. }
  840. #endif
  841. /*
  842. * hal_tx_get_num_ppe_vp_tbl_entries() - Get the total number of VP table
  843. * @hal_soc: HAL SoC Context
  844. *
  845. * Return: Total number of entries.
  846. */
  847. static inline
  848. uint32_t hal_tx_get_num_ppe_vp_tbl_entries(hal_soc_handle_t hal_soc_hdl)
  849. {
  850. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  851. return hal_soc->ops->hal_tx_get_num_ppe_vp_tbl_entries(hal_soc_hdl);
  852. }
  853. /**
  854. * hal_tx_set_ppe_cmn_cfg()- Set the PPE common config
  855. * @hal_soc: HAL SoC context
  856. * @cmn_cfg: HAL PPE VP common config
  857. *
  858. * Return: void
  859. */
  860. static inline void
  861. hal_tx_set_ppe_cmn_cfg(hal_soc_handle_t hal_soc_hdl,
  862. union hal_tx_cmn_config_ppe *cmn_cfg)
  863. {
  864. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  865. hal_soc->ops->hal_tx_set_ppe_cmn_cfg(hal_soc_hdl, cmn_cfg);
  866. }
  867. /**
  868. * hal_tx_populate_ppe_vp_entry - Populate ppe VP entry
  869. * @hal_soc: HAL SoC context
  870. * @vp_cfg: HAL PPE VP config
  871. * @ppe_vp_idx: PPE VP index
  872. *
  873. * Return: void
  874. */
  875. static inline void
  876. hal_tx_populate_ppe_vp_entry(hal_soc_handle_t hal_soc_hdl,
  877. union hal_tx_ppe_vp_config *vp_cfg,
  878. int ppe_vp_idx)
  879. {
  880. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  881. hal_soc->ops->hal_tx_set_ppe_vp_entry(hal_soc_hdl, vp_cfg, ppe_vp_idx);
  882. }
  883. /**
  884. * hal_tx_set_int_pri2id - Set the prit2tid table.
  885. * @hal_soc: HAL SoC context
  886. * @pri2tid: Reference to SW INT_PRI to TID table
  887. *
  888. * Return: void
  889. */
  890. static inline void
  891. hal_tx_set_int_pri2tid(hal_soc_handle_t hal_soc_hdl,
  892. uint32_t val, uint8_t map_no)
  893. {
  894. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  895. hal_soc->ops->hal_tx_set_ppe_pri2tid(hal_soc_hdl, val, map_no);
  896. }
  897. /**
  898. * hal_tx_update_int_pri2id - Populate the prit2tid table.
  899. * @hal_soc: HAL SoC context
  900. * @pri: INT_PRI value
  901. * @tid: Wi-Fi TID
  902. *
  903. * Return: void
  904. */
  905. static inline void
  906. hal_tx_update_int_pri2tid(hal_soc_handle_t hal_soc_hdl,
  907. uint8_t pri, uint8_t tid)
  908. {
  909. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  910. hal_soc->ops->hal_tx_update_ppe_pri2tid(hal_soc_hdl, pri, tid);
  911. }
  912. /**
  913. * hal_tx_dump_ppe_vp_entry - Dump the PPE VP entry
  914. * @hal_soc_hdl: HAL SoC context
  915. *
  916. * Return: void
  917. */
  918. static inline void
  919. hal_tx_dump_ppe_vp_entry(hal_soc_handle_t hal_soc_hdl)
  920. {
  921. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  922. hal_soc->ops->hal_tx_dump_ppe_vp_entry(hal_soc_hdl);
  923. }
  924. /**
  925. * hal_tx_enable_pri2tid_map- Enable the priority to tid mapping
  926. * @hal_soc_hdl: HAL SoC context
  927. * @val: True/False value
  928. *
  929. * Return: void
  930. */
  931. static inline void
  932. hal_tx_enable_pri2tid_map(hal_soc_handle_t hal_soc_hdl, bool val,
  933. uint8_t ppe_vp_idx)
  934. {
  935. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  936. hal_soc->ops->hal_tx_enable_pri2tid_map(hal_soc_hdl, val,
  937. ppe_vp_idx);
  938. }
  939. #endif /* _HAL_BE_TX_H_ */